+#include "csi_instance.h"
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_q7(
+ const csi_fir_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+void csi_fir_init_q7(
+ csi_fir_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_q15(
+ const csi_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_fast_q15(
+ const csi_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns either
+ * CSI_MATH_SUCCESS
if initialization was successful or
+ * CSI_MATH_ARGUMENT_ERROR
if numTaps
is not a supported value.
+ */
+csi_status csi_fir_init_q15(
+ csi_fir_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_q31(
+ const csi_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_fast_q31(
+ const csi_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void csi_fir_init_q31(
+ csi_fir_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_f32(
+ const csi_fir_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void csi_fir_init_f32(
+ csi_fir_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_df1_q15(
+ const csi_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void csi_biquad_cascade_df1_init_q15(
+ csi_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_df1_fast_q15(
+ const csi_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_df1_q31(
+ const csi_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_df1_fast_q31(
+ const csi_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void csi_biquad_cascade_df1_init_q31(
+ csi_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_df1_f32(
+ const csi_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void csi_biquad_cascade_df1_init_f32(
+ csi_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_add_f32(
+ const csi_matrix_instance_f32 * pSrcA,
+ const csi_matrix_instance_f32 * pSrcB,
+ csi_matrix_instance_f32 * pDst);
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_add_q15(
+ const csi_matrix_instance_q15 * pSrcA,
+ const csi_matrix_instance_q15 * pSrcB,
+ csi_matrix_instance_q15 * pDst);
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_add_q31(
+ const csi_matrix_instance_q31 * pSrcA,
+ const csi_matrix_instance_q31 * pSrcB,
+ csi_matrix_instance_q31 * pDst);
+
+/**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_cmplx_mult_f32(
+ const csi_matrix_instance_f32 * pSrcA,
+ const csi_matrix_instance_f32 * pSrcB,
+ csi_matrix_instance_f32 * pDst);
+
+/**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_cmplx_mult_q15(
+ const csi_matrix_instance_q15 * pSrcA,
+ const csi_matrix_instance_q15 * pSrcB,
+ csi_matrix_instance_q15 * pDst);
+
+void csi_mult_q15xq31_sht(
+ q15_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t shiftValue,
+ uint32_t blockSize);
+
+/**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_cmplx_mult_q31(
+ const csi_matrix_instance_q31 * pSrcA,
+ const csi_matrix_instance_q31 * pSrcB,
+ csi_matrix_instance_q31 * pDst);
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either CSI_MATH_SIZE_MISMATCH
+ * or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_trans_f32(
+ const csi_matrix_instance_f32 * pSrc,
+ csi_matrix_instance_f32 * pDst);
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either CSI_MATH_SIZE_MISMATCH
+ * or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_trans_q15(
+ const csi_matrix_instance_q15 * pSrc,
+ csi_matrix_instance_q15 * pDst);
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either CSI_MATH_SIZE_MISMATCH
+ * or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_trans_q31(
+ const csi_matrix_instance_q31 * pSrc,
+ csi_matrix_instance_q31 * pDst);
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_mult_f32(
+ const csi_matrix_instance_f32 * pSrcA,
+ const csi_matrix_instance_f32 * pSrcB,
+ csi_matrix_instance_f32 * pDst);
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_mult_q15(
+ const csi_matrix_instance_q15 * pSrcA,
+ const csi_matrix_instance_q15 * pSrcB,
+ csi_matrix_instance_q15 * pDst);
+
+ csi_status csi_mat_mult_trans_q15(
+ const csi_matrix_instance_q15 * pSrcA,
+ const csi_matrix_instance_q15 * pSrcB,
+ csi_matrix_instance_q15 * pDst);
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_mult_fast_q15(
+ const csi_matrix_instance_q15 * pSrcA,
+ const csi_matrix_instance_q15 * pSrcB,
+ csi_matrix_instance_q15 * pDst);
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_mult_q31(
+ const csi_matrix_instance_q31 * pSrcA,
+ const csi_matrix_instance_q31 * pSrcB,
+ csi_matrix_instance_q31 * pDst);
+
+csi_status csi_mat_mult_trans_q31(
+ const csi_matrix_instance_q31 * pSrcA,
+ const csi_matrix_instance_q31 * pSrcB,
+ csi_matrix_instance_q31 * pDst);
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_mult_fast_q31(
+ const csi_matrix_instance_q31 * pSrcA,
+ const csi_matrix_instance_q31 * pSrcB,
+ csi_matrix_instance_q31 * pDst);
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_sub_f32(
+ const csi_matrix_instance_f32 * pSrcA,
+ const csi_matrix_instance_f32 * pSrcB,
+ csi_matrix_instance_f32 * pDst);
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_sub_q15(
+ const csi_matrix_instance_q15 * pSrcA,
+ const csi_matrix_instance_q15 * pSrcB,
+ csi_matrix_instance_q15 * pDst);
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_sub_q31(
+ const csi_matrix_instance_q31 * pSrcA,
+ const csi_matrix_instance_q31 * pSrcB,
+ csi_matrix_instance_q31 * pDst);
+
+void csi_sum_q15(
+ q15_t * pSrcA,
+ q63_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_scale_f32(
+ const csi_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ csi_matrix_instance_f32 * pDst);
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_scale_q15(
+ const csi_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ csi_matrix_instance_q15 * pDst);
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * CSI_MATH_SIZE_MISMATCH
or CSI_MATH_SUCCESS
based on the outcome of size checking.
+ */
+csi_status csi_mat_scale_q31(
+ const csi_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ csi_matrix_instance_q31 * pDst);
+
+/**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void csi_mat_init_q31(
+ csi_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+/**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void csi_mat_init_q15(
+ csi_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+/**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void csi_mat_init_f32(
+ csi_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void csi_pid_init_f32(
+ csi_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+void csi_pid_reset_f32(
+ csi_pid_instance_f32 * S);
+
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void csi_pid_init_q31(
+ csi_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+void csi_pid_reset_q31(
+ csi_pid_instance_q31 * S);
+
+
+/**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void csi_pid_init_q15(
+ csi_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+void csi_pid_reset_q15(
+ csi_pid_instance_q15 * S);
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_mult_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_mult_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void csi_mult_rnd_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_mult_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_mult_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/* Deprecated */
+csi_status csi_cfft_radix2_init_q15(
+ csi_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void csi_cfft_radix2_q15(
+ const csi_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+/* Deprecated */
+csi_status csi_cfft_radix4_init_q15(
+ csi_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void csi_cfft_radix4_q15(
+ const csi_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+/* Deprecated */
+csi_status csi_cfft_radix2_init_q31(
+ csi_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void csi_cfft_radix2_q31(
+ const csi_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+
+/* Deprecated */
+void csi_cfft_radix4_q31(
+ const csi_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+csi_status csi_cfft_radix4_init_q31(
+ csi_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+/* Deprecated */
+csi_status csi_cfft_radix2_init_f32(
+ csi_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void csi_cfft_radix2_f32(
+ const csi_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag,
+ float32_t onebyfftLen);
+
+
+/* Deprecated */
+csi_status csi_cfft_radix4_init_f32(
+ csi_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void csi_cfft_radix4_f32(
+ const csi_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag,
+ float32_t onebyfftLen);
+
+ void csi_cfft_fast_radix4_f32(
+ const csi_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag,
+ float32_t onebyfftLen);
+
+
+void csi_cfft_q15(
+ const csi_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+void csi_cfft_fast_q15(
+ const csi_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+void csi_cfft_q31(
+ const csi_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+void csi_cfft_fast_q31(
+ const csi_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+void csi_cfft_f32(
+ const csi_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+csi_status csi_rfft_init_q15(
+ csi_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void csi_rfft_q15(
+ const csi_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+void csi_rfft_fast_q15(
+ const csi_rfft_fast_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+
+csi_status csi_rfft_init_q31(
+ csi_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void csi_rfft_q31(
+ const csi_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+void csi_rfft_fast_q31(
+ const csi_rfft_fast_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+
+csi_status csi_rfft_init_f32(
+ csi_rfft_instance_f32 * S,
+ csi_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void csi_rfft_f32(
+ const csi_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+
+csi_status csi_rfft_fast_init_f32 (
+ csi_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+csi_status csi_rfft_32_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+csi_status csi_rfft_64_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+csi_status csi_rfft_128_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+csi_status csi_rfft_256_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+csi_status csi_rfft_512_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+csi_status csi_rfft_1024_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+csi_status csi_rfft_2048_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+csi_status csi_rfft_4096_fast_init_f32 ( csi_rfft_fast_instance_f32 * S );
+
+
+void csi_rfft_fast_f32(
+ csi_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+
+/**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if fftLenReal
is not a supported transform length.
+ */
+csi_status csi_dct4_init_f32(
+ csi_dct4_instance_f32 * S,
+ csi_rfft_fast_instance_f32 * S_RFFT,
+ csi_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void csi_dct4_f32(
+ const csi_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+
+/**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+csi_status csi_dct4_init_q31(
+ csi_dct4_instance_q31 * S,
+ csi_rfft_instance_q31 * S_RFFT,
+ csi_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void csi_dct4_q31(
+ const csi_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+void csi_dct4_fast_q31(
+ const csi_dct4_fast_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+/**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+csi_status csi_dct4_init_q15(
+ csi_dct4_instance_q15 * S,
+ csi_rfft_instance_q15 * S_RFFT,
+ csi_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void csi_dct4_q15(
+ const csi_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+void csi_dct4_fast_q15(
+ const csi_dct4_fast_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_add_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_add_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_add_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_add_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_sub_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_sub_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_sub_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_sub_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_scale_f32(
+ const float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_scale_q7(
+ const q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_scale_q15(
+ const q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_scale_q31(
+ const q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_abs_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_abs_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_abs_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void csi_abs_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ void csi_abs_max_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ void csi_abs_max_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void csi_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void csi_dot_prod_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void csi_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void csi_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_shift_q7(
+ const q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_shift_q15(
+ const q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_shift_q31(
+ const q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_offset_f32(
+ const float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_offset_q7(
+ const q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_offset_q15(
+ const q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_offset_q31(
+ const q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_negate_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_negate_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_negate_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void csi_negate_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_copy_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_copy_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_copy_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void csi_conv_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void csi_conv_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void csi_conv_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void csi_conv_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void csi_conv_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void csi_conv_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void csi_conv_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in] pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+*/
+void csi_conv_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void csi_conv_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+csi_status csi_conv_partial_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+/**
+ @brief Processing function for floating-point FIR decimator.
+ @param[in] S points to an instance of the floating-point FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ */
+void csi_fir_decimate_f32(
+ const csi_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ @brief Initialization function for the floating-point FIR decimator.
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref CSI_MATH_SUCCESS : Operation successful
+ - \ref CSI_MATH_LENGTH_ERROR : blockSize
is not a multiple of M
+ */
+csi_status csi_fir_decimate_init_f32(
+ csi_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_decimate_q15(
+ const csi_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_decimate_fast_q15(
+ const csi_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+csi_status csi_fir_decimate_init_q15(
+ csi_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_decimate_q31(
+ const csi_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_decimate_fast_q31(
+ const csi_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+csi_status csi_fir_decimate_init_q31(
+ csi_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_interpolate_q15(
+ const csi_fir_interpolate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+csi_status csi_fir_interpolate_init_q15(
+ csi_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_interpolate_q31(
+ const csi_fir_interpolate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+csi_status csi_fir_interpolate_init_q31(
+ csi_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_interpolate_f32(
+ const csi_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+csi_status csi_fir_interpolate_init_f32(
+ csi_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cas_df1_32x64_q31(
+ const csi_biquad_cas_df1_32x64_ins_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+void csi_biquad_cas_df1_32x64_init_q31(
+ csi_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_df2T_f32(
+ const csi_biquad_cascade_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_stereo_df2T_f32(
+ const csi_biquad_cascade_stereo_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_biquad_cascade_df2T_f64(
+ const csi_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+#if defined(CSI_MATH_NEON)
+void csi_biquad_cascade_df2T_compute_coefs_f32(
+ csi_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs);
+#endif
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void csi_biquad_cascade_df2T_init_f32(
+ csi_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void csi_biquad_cascade_stereo_df2T_init_f32(
+ csi_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void csi_biquad_cascade_df2T_init_f64(
+ csi_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void csi_fir_lattice_init_q15(
+ csi_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_lattice_q15(
+ const csi_fir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void csi_fir_lattice_init_q31(
+ csi_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_lattice_q31(
+ const csi_fir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void csi_fir_lattice_init_f32(
+ csi_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_fir_lattice_f32(
+ const csi_fir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_iir_lattice_f32(
+ const csi_iir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_iir_lattice_init_f32(
+ csi_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_iir_lattice_q31(
+ const csi_iir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_iir_lattice_init_q31(
+ csi_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_iir_lattice_q15(
+ const csi_iir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+void csi_iir_lattice_init_q15(
+ csi_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_f32(
+ const csi_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_init_f32(
+ csi_lms_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void csi_lms_init_q15(
+ csi_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_q15(
+ const csi_lms_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_q31(
+ const csi_lms_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void csi_lms_init_q31(
+ csi_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_norm_f32(
+ csi_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_norm_init_f32(
+ csi_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_norm_q31(
+ csi_lms_norm_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void csi_lms_norm_init_q31(
+ csi_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void csi_lms_norm_q15(
+ csi_lms_norm_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void csi_lms_norm_init_q15(
+ csi_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void csi_correlate_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void csi_correlate_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ @brief Correlation of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void csi_correlate_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+ */
+void csi_correlate_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence.
+ @param[in] srcALen length of the first input sequence.
+ @param[in] pSrcB points to the second input sequence.
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void csi_correlate_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void csi_correlate_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ @brief Correlation of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void csi_correlate_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+void csi_correlate_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void csi_correlate_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_sparse_f32(
+ csi_fir_sparse_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void csi_fir_sparse_init_f32(
+ csi_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_sparse_q31(
+ csi_fir_sparse_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void csi_fir_sparse_init_q31(
+ csi_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_sparse_q15(
+ csi_fir_sparse_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void csi_fir_sparse_init_q15(
+ csi_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void csi_fir_sparse_q7(
+ csi_fir_sparse_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void csi_fir_sparse_init_q7(
+ csi_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+void csi_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+void csi_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void csi_cmplx_conj_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void csi_cmplx_conj_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void csi_cmplx_conj_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void csi_cmplx_mag_squared_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void csi_cmplx_mag_squared_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+void csi_cmplx_mag_squared_q31_basic(
+ q31_t * pSrc,
+ q63_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void csi_cmplx_mag_squared_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S
points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return processed output sample.
+ */
+__STATIC_FORCEINLINE float32_t csi_pid_f32(
+ csi_pid_instance_f32 * S,
+ float32_t in)
+{
+ float32_t out;
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+ /* return to application */
+ return (out);
+}
+
+/**
+ @brief Process function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+__STATIC_FORCEINLINE q31_t csi_pid_q31(
+ csi_pid_instance_q31 * S,
+ q31_t in)
+{
+ q63_t acc;
+ q31_t out;
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+ /* out += y[n-1] */
+ out += S->state[2];
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+ /* return to application */
+ return (out);
+}
+
+
+/**
+ @brief Process function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+__STATIC_FORCEINLINE q15_t csi_pid_q15(
+ csi_pid_instance_q15 * S,
+ q15_t in)
+{
+ q63_t acc;
+ q15_t out;
+#if defined (CSI_MATH_DSP)
+ /* Implementation of PID controller */
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+ /* saturate the output */
+ out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+ /* return to application */
+ return (out);
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns CSI_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status CSI_MATH_SINGULAR.
+ */
+csi_status csi_mat_inverse_f32(
+ const csi_matrix_instance_f32 * src,
+ csi_matrix_instance_f32 * dst);
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns CSI_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status CSI_MATH_SINGULAR.
+ */
+csi_status csi_mat_inverse_f64(
+ const csi_matrix_instance_f64 * src,
+ csi_matrix_instance_f64 * dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic
to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha
and Ibeta
.
+ * When Ialpha
is superposed with Ia
as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0
, in this condition Ialpha
and Ibeta
+ * can be calculated using only Ia
and Ib
.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia
and Ib
are the instantaneous stator phases and
+ * pIalpha
and pIbeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none
+ */
+__STATIC_FORCEINLINE void csi_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+}
+
+
+/**
+ @brief Clarke transform for Q31 version
+ @param[in] Ia input three-phase coordinate a
+ @param[in] Ib input three-phase coordinate b
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void csi_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa
and pIb
are the instantaneous stator phases and
+ * Ialpha
and Ibeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Clarke transform
+* @param[in] Ialpha input two-phase orthogonal vector axis alpha
+* @param[in] Ibeta input two-phase orthogonal vector axis beta
+* @param[out] pIa points to output three-phase coordinate a
+* @param[out] pIb points to output three-phase coordinate b
+* @return none
+*/
+__STATIC_FORCEINLINE void csi_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+{
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+}
+
+
+/**
+ @brief Inverse Clarke transform for Q31 version
+ @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ @param[in] Ibeta input two-phase orthogonal vector axis beta
+ @param[out] pIa points to output three-phase coordinate a
+ @param[out] pIb points to output three-phase coordinate b
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void csi_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha
and the Ibeta
currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha
and Ibeta
are the stator vector components,
+ * pId
and pIq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+__STATIC_FORCEINLINE void csi_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+}
+
+
+/**
+ @brief Park transform for Q31 version
+ @param[in] Ialpha input two-phase vector coordinate alpha
+ @param[in] Ibeta input two-phase vector coordinate beta
+ @param[out] pId points to output rotor reference frame d
+ @param[out] pIq points to output rotor reference frame q
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void csi_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+#ifdef CSI_SIMD
+ asm volatile(
+ "rmul.s32.h t0, %0, %3\n\t"
+ "rmul.s32.h t1, %1, %2\n\t"
+ "add.s32.s t0, t0, t1\n\t"
+ "st.w t0, (%4, 0x0)\n\t"
+ "rmul.s32.h t0, %0, %2\n\t"
+ "rmul.s32.h t1, %1, %3\n\t"
+ "sub.s32.s t1, t1, t0\n\t"
+ "st.w t1, (%5, 0x0)\n\t"
+ ::"r"(Ialpha),"r"(Ibeta),"r"(sinVal),"r"(cosVal),"r"(pId),"r"(pIq)
+ :"t0","t1", "memory");
+#else
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+#endif
+}
+
+/**
+ * @} end of park group
+ */
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha
and pIbeta
are the stator vector components,
+ * Id
and Iq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Park transform
+* @param[in] Id input coordinate of rotor reference frame d
+* @param[in] Iq input coordinate of rotor reference frame q
+* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+* @param[in] sinVal sine value of rotation angle theta
+* @param[in] cosVal cosine value of rotation angle theta
+* @return none
+*/
+__STATIC_FORCEINLINE void csi_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+}
+
+
+/**
+ @brief Inverse Park transform for Q31 version
+ @param[in] Id input coordinate of rotor reference frame d
+ @param[in] Iq input coordinate of rotor reference frame q
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void csi_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+#ifdef CSI_SIMD
+ asm volatile(
+ "rmul.s32.h t0, %0, %3\n\t"
+ "rmul.s32.h t1, %1, %2\n\t"
+ "sub.s32.s t0, t0, t1\n\t"
+ "st.w t0, (%4, 0x0)\n\t"
+ "rmul.s32.h t0, %0, %2\n\t"
+ "rmul.s32.h t1, %1, %3\n\t"
+ "add.s32.s t0, t0, t1\n\t"
+ "st.w t0, (%5, 0x0)\n\t"
+ ::"r"(Id),"r"(Iq),"r"(sinVal),"r"(cosVal),"r"(pIalpha),"r"(pIbeta)
+ :"t0","t1", "memory");
+#else
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+#endif
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S
points to an instance of the Linear Interpolate function data structure.
+ * x
is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+__STATIC_FORCEINLINE float32_t csi_linear_interp_f32(
+ csi_linear_interp_instance_f32 * S,
+ float32_t x)
+{
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0) {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+
+ } else if ((uint32_t)i >= (S->nValues - 1)) {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+
+ } else {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+ }
+
+ /* returns output value */
+ return (y);
+}
+
+
+/**
+*
+* @brief Process function for the Q31 Linear Interpolation Function.
+* @param[in] pYData pointer to Q31 Linear Interpolation table
+* @param[in] x input sample to process
+* @param[in] nValues number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+__STATIC_FORCEINLINE q31_t csi_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+
+ } else if (index < 0) {
+ return (pYData[0]);
+
+ } else {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+__STATIC_FORCEINLINE q15_t csi_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+
+ } else if (index < 0) {
+ return (pYData[0]);
+
+ } else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+__STATIC_FORCEINLINE q7_t csi_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0) {
+ return (pYData[0]);
+ }
+
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1)) {
+ return (pYData[nValues - 1]);
+
+ } else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+}
+
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+float32_t csi_sin_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q31_t csi_sin_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q15_t csi_sin_q15(
+ q15_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+float32_t csi_cos_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q31_t csi_cos_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q15_t csi_cos_q15(
+ q15_t x);
+
+
+/**
+ @brief Floating-point vector of log values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+void csi_vlog_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ @brief Floating-point vector of exp values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+void csi_vexp_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1
is the current estimate,
+ * x0
is the previous estimate, and
+ * f'(x0)
is the derivative of f()
evaluated at x0
.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ @brief Q15 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref CSI_MATH_SUCCESS : input value is positive
+ - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+csi_status csi_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+/**
+ @brief Floating-point square root function.
+ @param[in] in input value
+ @param[out] pOut square root of input value
+ @return execution status
+ - \ref CSI_MATH_SUCCESS : input value is positive
+ - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+#ifdef __riscv
+__STATIC_FORCEINLINE csi_status csi_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+{
+ if (in >= 0.0f) {
+#ifdef CSI_NEWTON_SQRTF
+ float32_t eps = 0.000000011;
+ float32_t val = in / 2;
+ float32_t last;
+
+ if (in <= eps) {
+ *pOut = 0.0f;
+ } else {
+ do {
+ last = val;
+ val = (val + in / val) / 2;
+ } while (fabsf(val - last) > eps);
+ *pOut = val;
+ }
+#else
+ *pOut = sqrtf(in);
+#endif
+ return (CSI_MATH_SUCCESS);
+ } else {
+ *pOut = 0.0f;
+ return (CSI_MATH_ARGUMENT_ERROR);
+ }
+}
+#else
+csi_status csi_sqrt_f32(
+ float32_t in,
+ float32_t * pOut);
+#endif
+
+
+/**
+ @brief Q31 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref CSI_MATH_SUCCESS : input value is positive
+ - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+csi_status csi_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+/**
+ * @brief Vector Floating-point square root function.
+ * @param[in] pIn input vector.
+ * @param[out] pOut vector of square roots of input elements.
+ * @param[in] len length of input vector.
+ * @return The function returns CSI_MATH_SUCCESS if input value is positive value or CSI_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+#ifdef __csky__
+
+void csi_vsqrt_f32(
+ float32_t * pIn,
+ float32_t * pOut,
+ uint16_t len);
+
+ void csi_vsqrt_q15(
+ q15_t * pIn,
+ q15_t * pOut,
+ uint16_t len);
+
+void csi_vsqrt_q31(
+ q31_t * pIn,
+ q31_t * pOut,
+ uint16_t len);
+
+void csi_vsqrt_q7(
+ q7_t * pIn,
+ q7_t * pOut,
+ uint16_t len);
+
+
+#else
+__STATIC_FORCEINLINE void csi_vsqrt_f32(
+ float32_t * pIn,
+ float32_t * pOut,
+ uint16_t len)
+{
+ for (int i = 0; i < len; i++) {
+ csi_sqrt_f32(pIn[i], pOut + i);
+ }
+}
+
+__STATIC_FORCEINLINE void csi_vsqrt_q15(
+ q15_t * pIn,
+ q15_t * pOut,
+ uint16_t len
+)
+{
+ for (int i = 0; i < len; i++) {
+ csi_sqrt_q15(pIn[i], pOut + i);
+ }
+}
+__STATIC_FORCEINLINE void csi_vsqrt_q31(
+ q31_t * pIn,
+ q31_t * pOut,
+ uint16_t len
+)
+{
+ for (int i = 0; i < len; i++) {
+ csi_sqrt_q31(pIn[i], pOut + i);
+ }
+}
+#endif
+/**
+ * @} end of SQRT group
+ */
+
+/**
+ * @brief floating-point Circular write function.
+ a*/
+#ifndef __csky__
+__STATIC_FORCEINLINE void csi_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0U;
+ int32_t wOffset;
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+ /* Update the input pointer */
+ src += srcInc;
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+__STATIC_FORCEINLINE void csi_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0U;
+ int32_t rOffset;
+ int32_t* dst_end;
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = dst_base + dst_length;
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+#endif
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_power_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+void csi_power_int32(
+ int32_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_power_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_power_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_mean_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_mean_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_mean_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_var_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_var_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_rms_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_rms_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_std_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void csi_std_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void csi_cmplx_mag_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void csi_cmplx_mag_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void csi_cmplx_mag_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void csi_cmplx_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+/**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void csi_cmplx_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ void csi_dot_prod_u64xu8(
+ uint8_t * pSrcA,
+ uint64_t * pSrcB,
+ uint32_t blockSize,
+ uint64_t * result);
+
+/**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void csi_cmplx_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void csi_cmplx_mult_real_q15(
+ const q15_t * pSrcCmplx,
+ const q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void csi_cmplx_mult_real_q31(
+ const q31_t * pSrcCmplx,
+ const q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void csi_cmplx_mult_real_f32(
+ const float32_t * pSrcCmplx,
+ const float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+void csi_min_q7(
+ const q7_t * pSrc,
+ uint16_t blockSize,
+ q7_t * result,
+ uint16_t * index);
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+void csi_min_q15(
+ const q15_t * pSrc,
+ uint16_t blockSize,
+ q15_t * pResult,
+ uint16_t * pIndex);
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void csi_min_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void csi_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void csi_max_q7(
+ const q7_t * pSrc,
+ uint16_t blockSize,
+ q7_t * pResult,
+ uint16_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void csi_max_q15(
+ const q15_t * pSrc,
+ uint16_t blockSize,
+ q15_t * pResult,
+ uint16_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void csi_max_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void csi_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+void csi_max_no_idx_f32(
+ const float32_t *pSrc,
+ uint32_t blockSize,
+ float32_t *pResult);
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void csi_cmplx_mult_cmplx_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void csi_cmplx_mult_cmplx_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void csi_cmplx_mult_cmplx_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+void csi_cmplx_mult_cmplx_re_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void csi_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void csi_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void csi_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void csi_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void csi_q31_to_q15(
+ const q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void csi_q31_to_q7_rs(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t shiftValue,
+ uint32_t blockSize);
+
+void csi_q63_to_q31_rs(
+ q63_t * pSrc,
+ q31_t * pDst,
+ uint32_t shiftValue,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void csi_q31_to_q7(
+ const q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void csi_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void csi_q15_to_q31(
+ const q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void csi_q15_to_q7(
+ const q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void csi_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_q7_to_q31(
+ const q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void csi_q7_to_q15(
+ const q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief SVM linear instance init function
+ * @param[in] S Parameters for SVM functions
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void csi_svm_linear_init_f32(csi_svm_linear_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes);
+
+/**
+ * @brief SVM linear prediction
+ * @param[in] S Pointer to an instance of the linear SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+
+void csi_svm_linear_predict_f32(const csi_svm_linear_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM polynomial instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] degree Polynomial degree
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void csi_svm_polynomial_init_f32(csi_svm_polynomial_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ int32_t degree,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in] S Pointer to an instance of the polynomial SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void csi_svm_polynomial_predict_f32(const csi_svm_polynomial_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM radial basis function instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void csi_svm_rbf_init_f32(csi_svm_rbf_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult decision value
+ * @return none.
+ *
+ */
+void csi_svm_rbf_predict_f32(const csi_svm_rbf_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+/**
+ * @brief SVM sigmoid instance init function
+ * @param[in] S points to an instance of the rbf SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void csi_svm_sigmoid_init_f32(csi_svm_sigmoid_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void csi_svm_sigmoid_predict_f32(const csi_svm_sigmoid_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief Naive Gaussian Bayesian Estimator
+ *
+ * @param[in] S points to a naive bayes instance structure
+ * @param[in] in points to the elements of the input vector.
+ * @param[in] pBuffer points to a buffer of length numberOfClasses
+ * @return The predicted class
+ *
+ */
+
+
+uint32_t csi_gaussian_naive_bayes_predict_f32(const csi_gaussian_naive_bayes_instance_f32 *S,
+ const float32_t * in,
+ float32_t *pBuffer);
+
+/**
+ * @brief Computation of the LogSumExp
+ *
+ * In probabilistic computations, the dynamic of the probability values can be very
+ * wide because they come from gaussian functions.
+ * To avoid underflow and overflow issues, the values are represented by their log.
+ * In this representation, multiplying the original exp values is easy : their logs are added.
+ * But adding the original exp values is requiring some special handling and it is the
+ * goal of the LogSumExp function.
+ *
+ * If the values are x1...xn, the function is computing:
+ *
+ * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that
+ * rounding issues are minimised.
+ *
+ * The max xm of the values is extracted and the function is computing:
+ * xm + ln(exp(x1 - xm) + ... + exp(xn - xm))
+ *
+ * @param[in] *in Pointer to an array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return LogSumExp
+ *
+ */
+
+
+float32_t csi_logsumexp_f32(const float32_t *in, uint32_t blockSize);
+
+/**
+ * @brief Dot product with log arithmetic
+ *
+ * Vectors are containing the log of the samples
+ *
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[in] pTmpBuffer temporary buffer of length blockSize
+ * @return The log of the dot product .
+ *
+ */
+
+
+float32_t csi_logsumexp_dot_prod_f32(const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t *pTmpBuffer);
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float32_t csi_entropy_f32(const float32_t * pSrcA,uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float32_t csi_kullback_leibler_f32(const float32_t * pSrcA
+ ,const float32_t * pSrcB
+ ,uint32_t blockSize);
+
+
+/**
+ * @brief Weighted sum
+ *
+ *
+ * @param[in] *in Array of input values.
+ * @param[in] *weigths Weights
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Weighted sum
+ *
+ */
+float32_t csi_weighted_sum_f32(const float32_t *in
+ , const float32_t *weigths
+ , uint32_t blockSize);
+
+
+/**
+ * @brief Barycenter
+ *
+ *
+ * @param[in] in List of vectors
+ * @param[in] weights Weights of the vectors
+ * @param[out] out Barycenter
+ * @param[in] nbVectors Number of vectors
+ * @param[in] vecDim Dimension of space (vector dimension)
+ * @return None
+ *
+ */
+void csi_barycenter_f32(const float32_t *in
+ , const float32_t *weights
+ , float32_t *out
+ , uint32_t nbVectors
+ , uint32_t vecDim);
+
+/**
+ * @brief Euclidean distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t csi_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Bray-Curtis distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t csi_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Canberra distance between two vectors
+ *
+ * This function may divide by zero when samples pA[i] and pB[i] are both zero.
+ * The result of the computation will be correct. So the division per zero may be
+ * ignored.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t csi_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Chebyshev distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t csi_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Cityblock (Manhattan) distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t csi_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Correlation distance between two vectors
+ *
+ * The input vectors are modified in place !
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t csi_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cosine distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t csi_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Jensen-Shannon distance between two vectors
+ *
+ * This function is assuming that elements of second vector are > 0
+ * and 0 only when the corresponding element of first vector is 0.
+ * Otherwise the result of the computation does not make sense
+ * and for speed reasons, the cases returning NaN or Infinity are not
+ * managed.
+ *
+ * When the function is computing x log (x / y) with x 0 and y 0,
+ * it will compute the right value (0) but a division per zero will occur
+ * and shoudl be ignored in client code.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t csi_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
+
+/**
+ * @brief Minkowski distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] n Norm order (>= 2)
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+
+
+float32_t csi_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
+
+/**
+ * @brief Dice distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] order Distance order
+ * @param[in] blockSize Number of samples
+ * @return distance
+ *
+ */
+
+
+float32_t csi_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Hamming distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Jaccard distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Kulsinski distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Roger Stanimoto distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Russell-Rao distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Michener distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Sneath distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Yule distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t csi_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y)
is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } csi_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows
specifies the number of rows in the table;
+ * numCols
specifies the number of columns in the table;
+ * and pData
points to an array of size numRows*numCols
values.
+ * The data table pTable
is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols]
where x and y are integers.
+ *
+ * \par
+ * Let (x, y)
specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+/**
+* @brief Floating-point bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate.
+* @param[in] Y interpolation coordinate.
+* @return out interpolated value.
+*/
+__STATIC_FORCEINLINE float32_t csi_bilinear_interp_f32(
+ const csi_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+{
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+ /* return to application */
+ return (out);
+}
+
+
+/**
+* @brief Q31 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+__STATIC_FORCEINLINE q31_t csi_bilinear_interp_q31(
+ csi_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+{
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+}
+
+
+/**
+* @brief Q15 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+__STATIC_FORCEINLINE q15_t csi_bilinear_interp_q15(
+ csi_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+}
+
+
+/**
+* @brief Q7 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+__STATIC_FORCEINLINE q7_t csi_bilinear_interp_q7(
+ csi_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _CSI_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.c b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.c
new file mode 100644
index 00000000..c2a61d68
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.c
@@ -0,0 +1,178 @@
+/**
+ ******************************************************************************
+ * @file rv_Sv39.c
+ * @version V1.0
+ * @date
+ * @brief This file is the RISC-V arch c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2021 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include
+#include "rv_Sv39.h"
+
+/** @addtogroup RISCV_ARCH_Driver
+ * @{
+ */
+
+/** @addtogroup SV39
+ * @{
+ */
+
+/* allocate 4KB page table buffer */
+__attribute__((weak))
+uint64_t *
+RV_Sv39_alloc_PageTable_buf(void)
+{
+ return NULL;
+}
+
+/** @defgroup SV39_Public_Functions
+ * @{
+ */
+
+/******************************************************************************
+ * @brief OSD blend layer configuration
+ *
+ * @param cfg: point to the Page Table Entry.
+ * @param tlb_index: return the TLB index in use if MAP is created directly in TLB.
+ * @param ttb0: the root translation table in memory.
+ *
+ * @return Result of the operation.
+ *
+*******************************************************************************/
+
+int RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index, volatile uintptr_t *ttb0)
+{
+ uintptr_t smeh, smel, smcir;
+ uintptr_t t0;
+ volatile uint64_t *ttb1 = NULL;
+ volatile uint64_t *ttb2 = NULL;
+
+ if (Sv39_PTE_LOC_JTLB == cfg->where) {
+ t0 = cfg->va;
+ smeh = ((t0 >> 12) << SMEH_VPN_OFFSET) | cfg->size | cfg->asid;
+ __asm volatile("csrw smeh, %0"
+ :
+ : "r"(smeh)
+ : "memory");
+
+ t0 = cfg->pa;
+ smel = cfg->flags | ((t0 >> 12) << PTE_PPN_OFFSET);
+ __asm volatile("csrw smel, %0"
+ :
+ : "r"(smel)
+ : "memory");
+
+ if (cfg->tlb_entry >= SV39_JTLB_ENTRY_CNT) {
+ /* random write */
+ smcir = SMCIR_TLBWR;
+ } else {
+ RV_Sv39_Set_SMIR(cfg->tlb_entry);
+ smcir = SMCIR_TLBWI;
+ }
+
+ smcir |= cfg->asid;
+ RV_Sv39_Set_SMCIR(smcir);
+
+ RV_Sv39_Set_SMCIR(SMCIR_TLBP);
+ t0 = RV_Sv39_Get_SMIR();
+
+ *tlb_index = t0;
+
+ return (t0 & (SMCIR_PF | SMCIR_TF)) ? -1 : 0;
+ } else {
+ /* top level: 1GB */
+ t0 = SV39_VPN2(cfg->va);
+
+ if (!ttb0[t0]) {
+ /* no translation for this 1GB range */
+ if (Sv39_PAGESIZE_1GB == cfg->size) {
+ /* finish map for top level */
+ ttb0[t0] = (SV39_PA2PPN(cfg->pa) << PTE_PPN_OFFSET) |
+ (cfg->flags);
+ return 0;
+ } else {
+ ttb1 = RV_Sv39_alloc_PageTable_buf();
+
+ if (NULL == ttb1) {
+ return -1;
+ }
+
+ __COMPILE_BARRIER();
+ ttb0[t0] = (SV39_PA2PPN((uint64_t)ttb1) << PTE_PPN_OFFSET) |
+ PTE_D | PTE_A |
+ PTE_XWR_NEXT | PTE_V;
+ }
+ } else {
+ /* already mapped, get the next level table pointer */
+ ttb1 = (volatile uint64_t *)SV39_PTE2PA(ttb0[t0]);
+ }
+
+ /* second level: 2MB */
+ t0 = SV39_VPN1(cfg->va);
+
+ if (!ttb1[t0]) {
+ /* no translation for this 2MB range */
+ if (Sv39_PAGESIZE_2MB == cfg->size) {
+ ttb1[t0] = (SV39_PA2PPN(cfg->pa) << PTE_PPN_OFFSET) |
+ (cfg->flags);
+ return 0;
+ } else {
+ ttb2 = RV_Sv39_alloc_PageTable_buf();
+
+ if (NULL == ttb2) {
+ return -1;
+ }
+
+ ttb1[t0] = (SV39_PA2PPN((uint64_t)ttb2) << PTE_PPN_OFFSET) |
+ PTE_D | PTE_A |
+ PTE_XWR_NEXT | PTE_V;
+ }
+ } else {
+ ttb2 = (volatile uint64_t *)SV39_PTE2PA(ttb1[t0]);
+ }
+
+ /* third level: 4KB */
+ t0 = SV39_VPN0(cfg->va);
+ __COMPILE_BARRIER();
+ ttb2[t0] = (SV39_PA2PPN(cfg->pa) << PTE_PPN_OFFSET) |
+ (cfg->flags);
+ }
+
+ /* flush the D cache */
+
+ return 0;
+}
+
+/*@} end of group SV39_Public_Functions */
+
+/*@} end of group SV39 */
+
+/*@} end of group RISCV_ARCH_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.h b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.h
new file mode 100644
index 00000000..11dbe95f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.h
@@ -0,0 +1,228 @@
+#ifndef __RV_SV39_H__
+#define __RV_SV39_H__
+
+#include
+#include
+#include
+
+#define SV39_VPN2(va) (((va) >> (9 + 9 + 12)) & 0x1FF)
+#define SV39_VPN1(va) (((va) >> (0 + 9 + 12)) & 0x1FF)
+#define SV39_VPN0(va) (((va) >> (0 + 0 + 12)) & 0x1FF)
+
+#define SV39_PA2PPN(pa) (((pa) >> (0 + 0 + 12)) & 0xFFFFFFFFFF)
+#define SV39_PTE2PPN(pte) (((pte) >> (10)) & 0xFFFFFFF)
+#define SV39_PTE2PA(pte) ((uint64_t)(SV39_PTE2PPN(pte) << 12))
+
+#define SV39_JTLB_ENTRY_CNT (256)
+
+/* SMCIR */
+#define SMCIR_ASID_OFFSET (0)
+#define SMCIR_ASID_LEN (16)
+
+#define SMCIR_TLBII_OFFSET (25)
+#define SMCIR_TLBII_LEN (1)
+#define SMCIR_TLBII (1 << 25)
+
+#define SMCIR_TLBIALL_OFFSET (26)
+#define SMCIR_TLBIALL_LEN (1)
+#define SMCIR_TLBIALL (1 << 26)
+
+#define SMCIR_TLBIASID_OFFSET (27)
+#define SMCIR_TLBIASID_LEN (1)
+#define SMCIR_TLBIASID (1 << 27)
+
+#define SMCIR_TLBWR_OFFSET (28)
+#define SMCIR_TLBWR_LEN (1)
+#define SMCIR_TLBWR (1 << 28)
+
+#define SMCIR_TLBWI_OFFSET (29)
+#define SMCIR_TLBWI_LEN (1)
+#define SMCIR_TLBWI (1 << 29)
+
+#define SMCIR_TLBR_OFFSET (30)
+#define SMCIR_TLBR_LEN (1)
+#define SMCIR_TLBR (1 << 30)
+
+#define SMCIR_TLBP_OFFSET (31)
+#define SMCIR_TLBP_LEN (1)
+#define SMCIR_TLBP (1 << 31)
+
+/* SMIR */
+#define SMIR_INDEX_OFFSET (0)
+#define SMIR_INDEX_LEN (9)
+
+#define SMCIR_T_OFFSET (30)
+#define SMCIR_TF_LEN (1)
+#define SMCIR_TF (1 << 30)
+
+#define SMCIR_P_OFFSET (31)
+#define SMCIR_PF_LEN (1)
+#define SMCIR_PF (1 << 31)
+
+/* SMEH */
+#define SMEH_ASID_OFFSET (0)
+#define SMEH_ASID_LEN (16)
+
+#define SMEH_PAGESIZE_OFFSET (16)
+#define SMEH_PAGESIZE_LEN (3)
+#define SMEH_PAGESIZE_4KB (1 << 16)
+#define SMEH_PAGESIZE_2MB (2 << 16)
+#define SMEH_PAGESIZE_1GB (4 << 16)
+
+#define SMEH_VPN_OFFSET (19)
+#define SMEH_VPN_LEN (27)
+
+#undef PTE_V
+#undef PTE_U
+#undef PTE_G
+#undef PTE_A
+#undef PTE_D
+
+/* SMEL & PTE */
+#define PTE_V_OFFSET (0)
+#define PTE_V_LEN (1)
+#define PTE_V (1 << 0)
+
+#define PTE_R_OFFSET (1)
+#define PTE_R_LEN (1)
+
+#define PTE_W_OFFSET (2)
+#define PTE_W_LEN (1)
+
+#define PTE_X_OFFSET (3)
+#define PTE_X_LEN (1)
+
+#define PTE_XWR_MASK (~(0xE))
+#define PTE_XWR_NEXT (0 << 1)
+#define PTE_XWR_RO_PAGE (1 << 1)
+#define PTE_XWR_WR_PAGE (3 << 1)
+#define PTE_XWR_XO_PAGE (4 << 1)
+#define PTE_XWR_XR_PAGE (5 << 1)
+#define PTE_XWR_XWR_PAGE (7 << 1)
+
+#define PTE_U_OFFSET (4)
+#define PTE_U_LEN (1)
+#define PTE_U (1 << 4)
+
+#define PTE_G_OFFSET (5)
+#define PTE_G_LEN (1)
+#define PTE_G (1 << 5)
+
+#define PTE_A_OFFSET (6)
+#define PTE_A_LEN (1)
+#define PTE_A (1 << 6)
+
+#define PTE_D_OFFSET (7)
+#define PTE_D_LEN (1)
+#define PTE_D (1 << 7)
+
+#define SMEL_PPN_OFFSET (8)
+#define PTE_PPN_OFFSET (10)
+#define PTE_PPN_LEN (28)
+
+#define PTE_SEC_OFFSET (59)
+#define PTE_SEC_LEN (1)
+
+#define PTE_B_OFFSET (61)
+#define PTE_B_LEN (1)
+#define PTE_B ((uintptr_t)1 << 61)
+
+#define PTE_C_OFFSET (62)
+#define PTE_C_LEN (1)
+#define PTE_C ((uintptr_t)1 << 62)
+
+#define PTE_SO_OFFSET (63)
+#define PTE_SO_LEN (1)
+#define PTE_SO ((uintptr_t)1 << 63)
+
+/* SATP */
+#define SATP_PPN_OFFSET (0)
+#define SATP_PPN_LEN (28)
+
+#define SATP_ASID_OFFSET (44)
+#define SATP_ASID_LEN (16)
+
+#define SATP_MODE_OFFSET (60)
+#define SATP_MODE_LEN (4)
+#define SATP_MODE_SV39 ((uintptr_t)8 << 60)
+
+typedef enum {
+ Sv39_PAGESIZE_4KB = SMEH_PAGESIZE_4KB,
+ Sv39_PAGESIZE_2MB = SMEH_PAGESIZE_2MB,
+ Sv39_PAGESIZE_1GB = SMEH_PAGESIZE_1GB,
+ Sv39_PAGESIZE_NUM,
+ Sv39_PAGESIZE_MAX = 0x7FFFFFFFFFFFFFFF
+} Sv39_PAGESIZE_Type;
+
+typedef enum {
+ Sv39_PTE_LOC_JTLB = 0,
+ Sv39_PTE_LOC_PAGETABLE,
+ Sv39_PTE_LOC_NUM,
+ Sv39_PTE_LOC_MAX = 0x7FFFFFFFFFFFFFFF
+} Sv39_PTE_LOC_Type;
+
+typedef struct _Sv39_PTE_cfg {
+ uintptr_t va;
+ uintptr_t pa;
+ Sv39_PAGESIZE_Type size;
+ uintptr_t flags;
+ uintptr_t asid;
+ Sv39_PTE_LOC_Type where;
+ uintptr_t tlb_entry;
+} Sv39_PTE_cfg_t;
+
+__ALWAYS_STATIC_INLINE void RV_Sv39_INVALID_VMA(void)
+{
+ __asm volatile("fence"
+ :
+ :
+ : "memory");
+ __asm volatile("sfence.vma x0,x0"
+ :
+ :
+ : "memory");
+ __asm volatile("fence"
+ :
+ :
+ : "memory");
+}
+
+__ALWAYS_STATIC_INLINE void RV_Sv39_Set_SMCIR(uintptr_t smcir)
+{
+ __asm volatile("csrw smcir, %0"
+ :
+ : "r"(smcir)
+ : "memory");
+}
+
+__ALWAYS_STATIC_INLINE uintptr_t RV_Sv39_Get_SMIR(void)
+{
+ uintptr_t result;
+
+ __asm volatile("csrr %0, smir"
+ : "=r"(result)
+ :
+ : "memory");
+ return (result);
+}
+
+__ALWAYS_STATIC_INLINE void RV_Sv39_Set_SMIR(uintptr_t smir)
+{
+ __asm volatile("csrw smir, %0"
+ :
+ : "r"(smir)
+ : "memory");
+}
+
+__ALWAYS_STATIC_INLINE void RV_Sv39_Set_SATP(uintptr_t asid, uintptr_t *ppn)
+{
+ __asm volatile("csrw satp, %0"
+ :
+ : "r"(SATP_MODE_SV39 | (asid << SATP_ASID_OFFSET) | ((uintptr_t)(ppn) >> 12))
+ : "memory");
+}
+
+/* cache config into jTLB, return tlb index if success */
+int RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index, volatile uintptr_t *ttb0);
+
+#endif /* __RV_SV39_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hart.c b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hart.c
new file mode 100644
index 00000000..60ef44f0
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hart.c
@@ -0,0 +1,132 @@
+#include "csi_core.h"
+#include "rv_hart.h"
+#include
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define INSERT_FIELD(val, which, fieldval) \
+ (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+void __attribute__((noreturn)) rv_hart_hang(void)
+{
+ while (1) {
+ __WFI();
+ }
+
+ __builtin_unreachable();
+}
+
+/* determine CPU extension, return non-zero support */
+int rv_hart_misa_ext_chk(char ext)
+{
+ unsigned long misa = READ_CSR(misa);
+
+ if (misa) {
+ if ('A' <= ext && ext <= 'Z') {
+ return misa & (1 << (ext - 'A'));
+ }
+
+ if ('a' <= ext && ext <= 'z') {
+ return misa & (1 << (ext - 'a'));
+ }
+
+ return 0;
+ }
+
+ return 0;
+}
+
+void rv_enterSupervisor(void)
+{
+ __asm volatile(
+ "fence\n\t"
+ "csrw mepc, ra\n\t"
+ "li t0, ~(3 << 11)\n\t"
+ "li t1, 1 << 11\n\t"
+ "csrr t2, mstatus\n\t"
+ "and t0, t0, t2\n\t"
+ "or t0, t0, t1\n\t"
+ "csrw mstatus, t0\n\t"
+ "mret\n\t"
+ :
+ :
+ : "memory");
+}
+
+void rv_enterUser(void)
+{
+ __asm volatile(
+ "fence\n\t"
+ "csrw mepc, ra\n\t"
+ "li t0, ~(3 << 11)\n\t"
+ "csrr t2, mstatus\n\t"
+ "and t0, t0, t2\n\t"
+ "csrw mstatus, t0\n\t"
+ "mret\n\t"
+ :
+ :
+ : "memory");
+}
+
+void __attribute__((noreturn))
+rv_hart_switch_mode_from_M(uintptr_t arg0, uintptr_t arg1,
+ uintptr_t next_addr, uintptr_t next_mode)
+{
+#if __riscv_xlen == 32
+ unsigned long val;
+#else
+ unsigned long val;
+#endif
+
+ switch (next_mode) {
+ case PRV_M:
+ break;
+
+ case PRV_S:
+ if (!rv_hart_misa_ext_chk('S')) {
+ rv_hart_hang();
+ }
+
+ break;
+
+ case PRV_U:
+ if (!rv_hart_misa_ext_chk('U')) {
+ rv_hart_hang();
+ }
+
+ break;
+
+ default:
+ rv_hart_hang();
+ }
+
+ val = READ_CSR(mstatus);
+ val = INSERT_FIELD(val, MSTATUS_MPPM, next_mode);
+ val = INSERT_FIELD(val, MSTATUS_MPIE, 0);
+
+ WRITE_CSR(mstatus, val);
+ WRITE_CSR(mepc, next_addr);
+
+ if (next_mode == PRV_S) {
+ WRITE_CSR(stvec, next_addr);
+ WRITE_CSR(sscratch, 0);
+ WRITE_CSR(sie, 0);
+ WRITE_CSR(satp, 0);
+ } else if (next_mode == PRV_U) {
+ /* un-implemented
+ WRITE_CSR(utvec, next_addr);
+ WRITE_CSR(uscratch, 0);
+ WRITE_CSR(uie, 0);
+ */
+ }
+
+ register unsigned long a0 __asm("a0") = arg0;
+ register unsigned long a1 __asm("a1") = arg1;
+ __asm__ __volatile__("mret"
+ :
+ : "r"(a0), "r"(a1));
+ __builtin_unreachable();
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hart.h b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hart.h
new file mode 100644
index 00000000..4607afdd
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hart.h
@@ -0,0 +1,16 @@
+#ifndef _RV_HART_H_
+#define _RV_HART_H_
+
+#include
+
+void __attribute__((noreturn)) rv_hart_hang(void);
+int rv_hart_misa_ext_chk(char ext);
+
+void rv_enterSupervisor(void) __attribute__((naked, noinline));
+void rv_enterUser(void) __attribute__((naked, noinline));
+
+void __attribute__((noreturn))
+rv_hart_switch_mode_from_M(uintptr_t arg0, uintptr_t arg1,
+ uintptr_t next_addr, uintptr_t next_mode);
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h
new file mode 100644
index 00000000..78311671
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h
@@ -0,0 +1,353 @@
+#ifndef __RV_HPM_H__
+#define __RV_HPM_H__
+
+#include
+
+#if (__riscv_xlen == 32)
+
+#define RV_HPM_SET_COUNTER(name, val) \
+ do { \
+ uint32_t value = (uint32_t)val; \
+ __asm volatile("csrw " #name ", %0" \
+ : \
+ : "r"(value) \
+ : "memory"); \
+ uint32_t valueh = (uint32_t)((uint64_t)val >> 32); \
+ __asm volatile("csrw " #name "h, %0" \
+ : \
+ : "r"(valueh) \
+ : "memory"); \
+ } while (0);
+
+#define RV_HPM_GET_COUNTER(name, val) \
+ do { \
+ uint32_t countl0, counth0; \
+ uint32_t countl1, counth1; \
+ do { \
+ __asm volatile("csrr %0, " #name \
+ : "=r"(countl0) \
+ : \
+ : "memory"); \
+ __asm volatile("csrr %0, " #name "h" \
+ : "=r"(counth0) \
+ : \
+ : "memory"); \
+ __asm volatile("csrr %0, " #name \
+ : "=r"(countl1) \
+ : \
+ : "memory"); \
+ __asm volatile("csrr %0, " #name "h" \
+ : "=r"(counth1) \
+ : \
+ : "memory"); \
+ } while ((countl1 < countl0) || (counth1 < counth0)); \
+ val = (((uint64_t)counth1) << 32) + countl1; \
+ } while (0);
+
+#else
+
+#define RV_HPM_SET_COUNTER(name, val) \
+ do { \
+ uint64_t value = val; \
+ __asm volatile("csrw " #name ", %0" \
+ : \
+ : "r"(value) \
+ : "memory"); \
+ } while (0);
+
+#define RV_HPM_GET_COUNTER(name, val) \
+ do { \
+ uint64_t value; \
+ __asm volatile("csrr %0, " #name \
+ : "=r"(value) \
+ : \
+ : "memory"); \
+ val = value; \
+ } while (0);
+
+#endif
+
+/* Give permission for S-Mode */
+inline __attribute__((always_inline)) void RV_HPM_Set_mcounteren(uint32_t mcounteren)
+{
+ __asm volatile("csrw mcounteren, %0"
+ :
+ : "r"(mcounteren)
+ : "memory");
+}
+
+/* Give permission for U-Mode */
+inline __attribute__((always_inline)) void RV_HPM_Set_scounteren(uint32_t scounteren)
+{
+ __asm volatile("csrw mcounteren, %0"
+ :
+ : "r"(scounteren)
+ : "memory");
+}
+
+/* disable counter for power saving */
+inline __attribute__((always_inline)) void RV_HPM_Set_mcountinhibit(uint32_t mcountinhibit)
+{
+ __asm volatile("csrw mcountinhibit, %0"
+ :
+ : "r"(mcountinhibit)
+ : "memory");
+}
+
+/* allow S-mode to write to counters */
+inline __attribute__((always_inline)) void RV_HPM_Set_mcounterwen(uint32_t mcounterwen)
+{
+ __asm volatile("csrw mcounterwen, %0"
+ :
+ : "r"(mcounterwen)
+ : "memory");
+}
+
+/* M-mode: L1 ICache Miss rate measure Init */
+inline __attribute__((always_inline)) void RV_HPM_L1_ICache_Miss_Init_M(void)
+{
+ __asm volatile("csrw mhpmevent3, 1"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent4, 2"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter3, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter4, 0);
+}
+
+/* M-mode: L1 ICache Miss rate measure end */
+inline __attribute__((always_inline)) void RV_HPM_L1_ICache_Miss_Stop_M(uint64_t *m, uint64_t *c)
+{
+ uint64_t miss, count;
+
+ RV_HPM_GET_COUNTER(mhpmcounter3, count);
+ RV_HPM_GET_COUNTER(mhpmcounter4, miss);
+
+ *m = miss;
+ *c = count;
+}
+
+/* M-mode: Conditional Branch Mispredict rate measure Init */
+inline __attribute__((always_inline)) void RV_HPM_L1_BrPredict_Miss_Init_M(void)
+{
+#ifdef CPU_M0
+ __asm volatile("csrw mhpmevent8, 6"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent9, 7"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter8, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter9, 0);
+#endif
+#ifdef CPU_D0
+ __asm volatile("csrw mhpmevent9, 6"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent10, 7"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter9, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter10, 0);
+#endif
+}
+
+/* M-mode: Conditional Branch Mispredict rate measure end */
+inline __attribute__((always_inline)) void RV_HPM_L1_BrPredict_Miss_Stop_M(uint64_t *m, uint64_t *c)
+{
+ uint64_t miss, count;
+#ifdef CPU_M0
+ RV_HPM_GET_COUNTER(mhpmcounter9, count);
+ RV_HPM_GET_COUNTER(mhpmcounter8, miss);
+#endif
+#ifdef CPU_D0
+ RV_HPM_GET_COUNTER(mhpmcounter10, count);
+ RV_HPM_GET_COUNTER(mhpmcounter9, miss);
+#endif
+ *m = miss;
+ *c = count;
+}
+
+/* M-mode: L1 DCache read miss rate measure Init */
+inline __attribute__((always_inline)) void RV_HPM_L1_DCache_RdMiss_Init_M(void)
+{
+#ifdef CPU_M0
+ __asm volatile("csrw mhpmevent14, 12"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent15, 13"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter14, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter15, 0);
+#endif
+#ifdef CPU_D0
+ __asm volatile("csrw mhpmevent5, 12"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent6, 13"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter5, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter6, 0);
+#endif
+}
+
+/* M-mode: L1 DCache read miss rate measure end */
+inline __attribute__((always_inline)) void RV_HPM_L1_DCache_RdMiss_Stop_M(uint64_t *m, uint64_t *c)
+{
+ uint64_t miss, count;
+#ifdef CPU_M0
+ RV_HPM_GET_COUNTER(mhpmcounter14, count);
+ RV_HPM_GET_COUNTER(mhpmcounter15, miss);
+#endif
+#ifdef CPU_D0
+ RV_HPM_GET_COUNTER(mhpmcounter5, count);
+ RV_HPM_GET_COUNTER(mhpmcounter6, miss);
+#endif
+ *m = miss;
+ *c = count;
+}
+
+/* M-mode: L1 DCache write miss rate measure Init */
+inline __attribute__((always_inline)) void RV_HPM_L1_DCache_WrMiss_Init_M(void)
+{
+#ifdef CPU_M0
+ __asm volatile("csrw mhpmevent16, 14"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent17, 15"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter16, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter17, 0);
+#endif
+#ifdef CPU_D0
+ __asm volatile("csrw mhpmevent7, 14"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent8, 15"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter7, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter8, 0);
+#endif
+}
+
+/* M-mode: L1 DCache write miss rate measure end */
+inline __attribute__((always_inline)) void RV_HPM_L1_DCache_WrMiss_Stop_M(uint64_t *m, uint64_t *c)
+{
+ uint64_t miss, count;
+#ifdef CPU_M0
+ RV_HPM_GET_COUNTER(mhpmcounter16, count);
+ RV_HPM_GET_COUNTER(mhpmcounter17, miss);
+#endif
+#ifdef CPU_D0
+ RV_HPM_GET_COUNTER(mhpmcounter7, count);
+ RV_HPM_GET_COUNTER(mhpmcounter8, miss);
+#endif
+ *m = miss;
+ *c = count;
+}
+
+/* M-mode: TLB miss count measure Init */
+inline __attribute__((always_inline)) void RV_HPM_TLB_Miss_Init_M(void)
+{
+ __asm volatile("csrw mhpmevent5, 3"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent6, 4"
+ :
+ :
+ : "memory");
+ __asm volatile("csrw mhpmevent7, 5"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter5, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter6, 0);
+ RV_HPM_SET_COUNTER(mhpmcounter7, 0);
+}
+
+/* M-mode: TLB miss count measure end */
+inline __attribute__((always_inline)) void RV_HPM_TLB_Miss_Stop_M(uint64_t *IuTLB, uint64_t *DuTLB, uint64_t *jTLB)
+{
+ uint64_t du, iu, j;
+
+ RV_HPM_GET_COUNTER(mhpmcounter5, iu);
+ RV_HPM_GET_COUNTER(mhpmcounter6, du);
+ RV_HPM_GET_COUNTER(mhpmcounter7, j);
+
+ *IuTLB = iu;
+ *DuTLB = du;
+ *jTLB = j;
+}
+
+/* M-mode: Store Instruction counter measure Init */
+/* C906 mhpmevent13 none */
+inline __attribute__((always_inline)) void RV_HPM_Store_Insn_Init_M(void)
+{
+ __asm volatile("csrw mhpmevent13, 11"
+ :
+ :
+ : "memory");
+ RV_HPM_SET_COUNTER(mhpmcounter13, 0);
+}
+
+/* M-mode: Store Instruction counter measure end */
+inline __attribute__((always_inline)) void RV_HPM_Store_Insn_Stop_M(uint64_t *sc)
+{
+ uint64_t count;
+
+ RV_HPM_GET_COUNTER(mhpmcounter13, count);
+
+ *sc = count;
+}
+
+/* M-Mode: Set cycle counter */
+inline __attribute__((always_inline)) void RV_HPM_Cycle_Init_M(void)
+{
+ RV_HPM_SET_COUNTER(mcycle, 0);
+}
+
+/* M-Mode: Get cycle counter */
+inline __attribute__((always_inline)) void RV_HPM_Cycle_Get_M(uint64_t *cycle)
+{
+ uint64_t count;
+
+ RV_HPM_GET_COUNTER(mcycle, count);
+ *cycle = count;
+}
+
+/* M-Mode: Set minstret counter */
+inline __attribute__((always_inline)) void RV_HPM_Instret_Init_M(void)
+{
+ RV_HPM_SET_COUNTER(minstret, 0);
+}
+
+/* M-Mode: Get minstret counter */
+inline __attribute__((always_inline)) void RV_HPM_Instret_Get_M(uint64_t *instret)
+{
+ uint64_t count;
+
+ RV_HPM_GET_COUNTER(minstret, count);
+ *instret = count;
+}
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c
new file mode 100644
index 00000000..0e9b3f77
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c
@@ -0,0 +1,319 @@
+#include "csi_core.h"
+#include "rv_pmp.h"
+
+static void rvpmp_reg_write(uintptr_t i, uintptr_t attr, uintptr_t pa)
+{
+ register uintptr_t cfg = 0;
+ uintptr_t offset = 0;
+ uintptr_t mask = ENTRY_FLAG_MASK;
+
+ switch (i) {
+ case 0:
+ __asm volatile("csrw pmpaddr0, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 1:
+ __asm volatile("csrw pmpaddr1, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 2:
+ __asm volatile("csrw pmpaddr2, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 3:
+ __asm volatile("csrw pmpaddr3, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 4:
+ __asm volatile("csrw pmpaddr4, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 5:
+ __asm volatile("csrw pmpaddr5, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 6:
+ __asm volatile("csrw pmpaddr6, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 7:
+ __asm volatile("csrw pmpaddr7, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 8:
+ __asm volatile("csrw pmpaddr8, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 9:
+ __asm volatile("csrw pmpaddr9, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 10:
+ __asm volatile("csrw pmpaddr10, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 11:
+ __asm volatile("csrw pmpaddr11, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 12:
+ __asm volatile("csrw pmpaddr12, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 13:
+ __asm volatile("csrw pmpaddr13, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 14:
+ __asm volatile("csrw pmpaddr14, %0"
+ :
+ : "r"(pa));
+ break;
+
+ case 15:
+ __asm volatile("csrw pmpaddr15, %0"
+ :
+ : "r"(pa));
+ break;
+
+ default:
+ break;
+ }
+
+#if (__riscv_xlen == 32)
+
+ switch (i) {
+ case 0 ... 3:
+ __asm volatile("csrr %0, pmpcfg0"
+ : "=r"(cfg));
+ offset = i % ENTRY_IN_CFG_REG;
+ cfg &= ~(mask << (offset * ENTRY_FLAG_SIZE));
+ cfg |= attr << (offset * ENTRY_FLAG_SIZE);
+ __asm volatile("csrw pmpcfg0, %0"
+ :
+ : "r"(cfg));
+ break;
+
+ case 4 ... 7:
+ __asm volatile("csrr %0, pmpcfg1"
+ : "=r"(cfg));
+ offset = i % ENTRY_IN_CFG_REG;
+ cfg &= ~(mask << (offset * ENTRY_FLAG_SIZE));
+ cfg |= attr << (offset * ENTRY_FLAG_SIZE);
+ __asm volatile("csrw pmpcfg1, %0"
+ :
+ : "r"(cfg));
+ break;
+
+ case 8 ... 11:
+ __asm volatile("csrr %0, pmpcfg2"
+ : "=r"(cfg));
+ offset = i % ENTRY_IN_CFG_REG;
+ cfg &= ~(mask << (offset * ENTRY_FLAG_SIZE));
+ cfg |= attr << (offset * ENTRY_FLAG_SIZE);
+ __asm volatile("csrw pmpcfg2, %0"
+ :
+ : "r"(cfg));
+ break;
+
+ case 12 ... 15:
+ __asm volatile("csrr %0, pmpcfg3"
+ : "=r"(cfg));
+ offset = i % ENTRY_IN_CFG_REG;
+ cfg &= ~(mask << (offset * ENTRY_FLAG_SIZE));
+ cfg |= attr << (offset * ENTRY_FLAG_SIZE);
+ __asm volatile("csrw pmpcfg3, %0"
+ :
+ : "r"(cfg));
+ break;
+
+ default:
+ break;
+ }
+
+#elif (__riscv_xlen == 64)
+
+ switch (i) {
+ case 0 ... 7:
+ __asm volatile("csrr %0, pmpcfg0"
+ : "=r"(cfg));
+ offset = i % ENTRY_IN_CFG_REG;
+ cfg &= (~(mask << (offset * ENTRY_FLAG_SIZE)));
+ cfg |= (attr << (offset * ENTRY_FLAG_SIZE));
+ __asm volatile("csrw pmpcfg0, %0"
+ :
+ : "r"(cfg));
+ break;
+
+ case 8 ... 15:
+ __asm volatile("csrr %0, pmpcfg2"
+ : "=r"(cfg));
+ offset = i % ENTRY_IN_CFG_REG;
+ cfg &= ~(mask << (offset * ENTRY_FLAG_SIZE));
+ cfg |= attr << (offset * ENTRY_FLAG_SIZE);
+ __asm volatile("csrw pmpcfg2, %0"
+ :
+ : "r"(cfg));
+ break;
+
+ default:
+ break;
+ }
+
+#else
+#error "XLEN of riscv not supported"
+#endif
+}
+
+static uint32_t pmp_get_config(uintptr_t e)
+{
+ uintptr_t cfg = 0;
+ uint32_t offset = 0;
+
+#if (__riscv_xlen == 32)
+
+ switch (e) {
+ case 0 ... 3:
+ __asm volatile("csrr %0, pmpcfg0"
+ : "=r"(cfg));
+ break;
+
+ case 4 ... 7:
+ __asm volatile("csrr %0, pmpcfg1"
+ : "=r"(cfg));
+ break;
+
+ case 8 ... 11:
+ __asm volatile("csrr %0, pmpcfg2"
+ : "=r"(cfg));
+ break;
+
+ case 12 ... 15:
+ __asm volatile("csrr %0, pmpcfg3"
+ : "=r"(cfg));
+ break;
+
+ default:
+ break;
+ }
+
+#elif (__riscv_xlen == 64)
+
+ switch (e) {
+ case 0 ... 7:
+ __asm volatile("csrr %0, pmpcfg0"
+ : "=r"(cfg));
+ break;
+
+ case 8 ... 15:
+ __asm volatile("csrr %0, pmpcfg2"
+ : "=r"(cfg));
+ break;
+
+ default:
+ break;
+ }
+
+#else
+#error "XLEN of riscv not supported"
+#endif
+
+ offset = e % ENTRY_IN_CFG_REG;
+ cfg >>= (offset * ENTRY_FLAG_SIZE);
+
+ return cfg & ENTRY_FLAG_MASK;
+}
+
+pmp_status_type_e rvpmp_fill_entry(const pmp_config_entry_t *entry, uintptr_t i, uintptr_t force)
+{
+ uintptr_t am = 0;
+ uintptr_t attr = 0;
+ uintptr_t pa = 0;
+ pmp_status_type_e ret = PMP_STATUS_OK;
+ uint32_t cfg;
+
+ /* check entry */
+ cfg = pmp_get_config(i);
+ if (cfg & ENTRY_FLAG_M_MODE_L) {
+ return PMP_STATUS_DENIED;
+ } else if ((cfg & ENTRY_FLAG_ADDR_MASK) && (!force)) {
+ return PMP_STATUS_BUSY;
+ }
+
+ attr = entry->entry_flag;
+ pa = entry->entry_pa_base;
+
+ am = entry->entry_flag & ENTRY_FLAG_ADDR_MASK;
+
+ switch (am) {
+ case ENTRY_FLAG_ADDR_OFF:
+ break;
+ case ENTRY_FLAG_ADDR_TOR:
+ pa >>= 2;
+ break;
+
+ case ENTRY_FLAG_ADDR_NAPOT:
+ /* rule of NAPOT */
+ if (pa & (entry->entry_pa_length - 1))
+ ret = PMP_STATUS_INVALID;
+ pa |= (entry->entry_pa_length - 1) >> 1;
+ pa >>= 2;
+ break;
+
+ default:
+ attr = 0;
+ ret = PMP_STATUS_UNSUPPORTED;
+ break;
+ }
+
+ if (PMP_STATUS_OK == ret)
+ rvpmp_reg_write(i, attr, pa);
+
+ return ret;
+}
+
+pmp_status_type_e rvpmp_init(const pmp_config_entry_t *entry, uintptr_t n)
+{
+ uintptr_t i = 0;
+ pmp_status_type_e ret = PMP_STATUS_OK;
+
+ __asm volatile ("fence":::"memory");
+
+ for (; i < n; i++) {
+ ret = rvpmp_fill_entry(&entry[i], i, 0);
+ if (PMP_STATUS_OK != ret)
+ break;
+ }
+
+ __asm volatile ("fence":::"memory");
+
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h
new file mode 100644
index 00000000..851db5ce
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h
@@ -0,0 +1,75 @@
+#ifndef _RV_PMP_H_
+#define _RV_PMP_H_
+
+#include "stdint.h"
+
+#define RV_PMP_ENTRY (8)
+
+#define ENTRY_FLAG_PERM_R (1 << 0)
+#define ENTRY_FLAG_PERM_W (1 << 1)
+#define ENTRY_FLAG_PERM_X (1 << 2)
+#define ENTRY_FLAG_ADDR_OFF (0 << 3)
+#define ENTRY_FLAG_ADDR_TOR (1 << 3)
+#define ENTRY_FLAG_ADDR_NAPOT (3 << 3)
+#define ENTRY_FLAG_ADDR_MASK (3 << 3)
+#define ENTRY_FLAG_M_MODE_L (1 << 7)
+
+#define ENTRY_FLAG_SIZE (8)
+#define ENTRY_FLAG_MASK (0xFF)
+
+#define ENTRY_IN_CFG_REG (__riscv_xlen / ENTRY_FLAG_SIZE)
+
+/* E907: the smallest granularity is 128B */
+/* C906: the smallest granularity is 4K */
+#define PMP_REG_SZ_128B (1 << 7)
+#define PMP_REG_SZ_256B (1 << 8)
+#define PMP_REG_SZ_512B (1 << 9)
+#define PMP_REG_SZ_1K (1 << 10)
+#define PMP_REG_SZ_2K (1 << 11)
+#define PMP_REG_SZ_4K (1 << 12)
+#define PMP_REG_SZ_8K (1 << 13)
+#define PMP_REG_SZ_16K (1 << 14)
+#define PMP_REG_SZ_32K (1 << 15)
+#define PMP_REG_SZ_64K (1 << 16)
+#define PMP_REG_SZ_128K (1 << 17)
+#define PMP_REG_SZ_256K (1 << 18)
+#define PMP_REG_SZ_512K (1 << 19)
+#define PMP_REG_SZ_1M (1 << 20)
+#define PMP_REG_SZ_2M (1 << 21)
+#define PMP_REG_SZ_4M (1 << 22)
+#define PMP_REG_SZ_8M (1 << 23)
+#define PMP_REG_SZ_16M (1 << 24)
+#define PMP_REG_SZ_32M (1 << 25)
+#define PMP_REG_SZ_64M (1 << 26)
+#define PMP_REG_SZ_128M (1 << 27)
+#define PMP_REG_SZ_256M (1 << 28)
+#define PMP_REG_SZ_512M (1 << 29)
+#define PMP_REG_SZ_1G (1 << 30)
+#define PMP_REG_SZ_1024M (PMP_REG_SZ_1G)
+
+typedef enum _pmp_status_type_ {
+ PMP_STATUS_OK = 0,
+ PMP_STATUS_BUSY,
+ PMP_STATUS_DENIED,
+ PMP_STATUS_INVALID,
+ PMP_STATUS_UNSUPPORTED,
+ PMP_STATUS_MAX = 0x7FFFFFFF
+} pmp_status_type_e;
+
+typedef enum _addr_match_type_ {
+ PMP_ADDR_MATCH_OFF = 0,
+ PMP_ADDR_MATCH_TOR,
+ PMP_ADDR_MATCH_NA4,
+ PMP_ADDR_MATCH_NAPOT
+} pmp_addr_match_type_e;
+
+typedef struct _pmp_config_entry {
+ uintptr_t entry_pa_base;
+ uintptr_t entry_pa_length;
+ uintptr_t entry_flag;
+} pmp_config_entry_t;
+
+pmp_status_type_e rvpmp_fill_entry(const pmp_config_entry_t *entry, uintptr_t i, uintptr_t force);
+pmp_status_type_e rvpmp_init(const pmp_config_entry_t *entry, uintptr_t n);
+
+#endif /* _RV_PMP_H_ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_syscall.h b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_syscall.h
new file mode 100644
index 00000000..27da9a83
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head/rv_syscall.h
@@ -0,0 +1,46 @@
+#ifndef _RV_SYSCALL_H_
+#define _RV_SYSCALL_H_
+
+#include
+
+#define RV_SYSCALL_BACK_TO_MACHINE 0
+#define RV_SYSCALL_WFI 1
+
+#ifndef __riscv_32e
+
+#define RV_SYSCALL(which, arg0, arg1, arg2, arg3) ({ \
+ register uintptr_t a0 __asm("a0") = (uintptr_t)(arg0); \
+ register uintptr_t a1 __asm("a1") = (uintptr_t)(arg1); \
+ register uintptr_t a2 __asm("a2") = (uintptr_t)(arg2); \
+ register uintptr_t a3 __asm("a3") = (uintptr_t)(arg3); \
+ register uintptr_t a7 __asm("a7") = (uintptr_t)(which); \
+ asm volatile("ecall" \
+ : "+r"(a0) \
+ : "r"(a1), "r"(a2), "r"(a3), "r"(a7) \
+ : "memory"); \
+ a0; \
+})
+
+#else
+
+#define RV_SYSCALL(which, arg0, arg1, arg2, arg3) ({ \
+ register uintptr_t a0 __asm("a0") = (uintptr_t)(arg0); \
+ register uintptr_t a1 __asm("a1") = (uintptr_t)(arg1); \
+ register uintptr_t a2 __asm("a2") = (uintptr_t)(arg2); \
+ register uintptr_t a3 __asm("a3") = (uintptr_t)(arg3); \
+ register uintptr_t a5 __asm("a5") = (uintptr_t)(which); \
+ asm volatile("ecall" \
+ : "+r"(a0) \
+ : "r"(a1), "r"(a2), "r"(a3), "r"(a5) \
+ : "memory"); \
+ a0; \
+})
+
+#endif
+
+static inline void rv_syscall_back_to_machine(void)
+{
+ RV_SYSCALL(RV_SYSCALL_BACK_TO_MACHINE, 0, 0, 0, 0);
+}
+
+#endif /* _RV_SYSCALL_H_ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_adc.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_adc.h
new file mode 100644
index 00000000..5ea85a0a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_adc.h
@@ -0,0 +1,303 @@
+#ifndef _BFLB_ADC_H
+#define _BFLB_ADC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_CHANNEL adc channel definition
+ * @{
+ */
+#define ADC_CHANNEL_0 0
+#define ADC_CHANNEL_1 1
+#define ADC_CHANNEL_2 2
+#define ADC_CHANNEL_3 3
+#define ADC_CHANNEL_4 4
+#define ADC_CHANNEL_5 5
+#define ADC_CHANNEL_6 6
+#define ADC_CHANNEL_7 7
+#define ADC_CHANNEL_8 8
+#define ADC_CHANNEL_9 9
+#define ADC_CHANNEL_10 10
+#define ADC_CHANNEL_11 11
+#define ADC_CHANNEL_DACA 12
+#define ADC_CHANNEL_DACB 13
+#define ADC_CHANNEL_TSEN_P 14
+#define ADC_CHANNEL_TSEN_N 15
+#define ADC_CHANNEL_VREF 16
+#define ADC_CHANNEL_VABT_HALF 18
+#define ADC_CHANNEL_GND 23
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CLK_DIV adc clock divison definition
+ * @{
+ */
+#define ADC_CLK_DIV_4 1
+#define ADC_CLK_DIV_8 2
+#define ADC_CLK_DIV_12 3
+#define ADC_CLK_DIV_16 4
+#define ADC_CLK_DIV_20 5
+#define ADC_CLK_DIV_24 6
+#define ADC_CLK_DIV_32 7
+/**
+ * @}
+ */
+
+/** @defgroup ADC_RESOLUTION adc resolution definition
+ * @{
+ */
+#define ADC_RESOLUTION_12B 0
+#define ADC_RESOLUTION_14B 2
+#define ADC_RESOLUTION_16B 4
+/**
+ * @}
+ */
+
+/** @defgroup ADC_VREF adc reference select definition
+ * @{
+ */
+#define ADC_VREF_3P2V 0
+#define ADC_VREF_2P0V 1
+/**
+ * @}
+ */
+
+/** @defgroup ADC_TSEN_MOD adc tsen mode definition
+ * @{
+ */
+#define ADC_TSEN_MOD_INTERNAL_DIODE 0
+#define ADC_TSEN_MOD_EXTERNAL_DIODE 1
+/**
+ * @}
+ */
+
+/** @defgroup ADC_INTSTS adc interrupt status definition
+ * @{
+ */
+#define ADC_INTSTS_NEG_SATURATION (1 << 0)
+#define ADC_INTSTS_POS_SATURATION (1 << 1)
+#define ADC_INTSTS_FIFO_UNDERRUN (1 << 2)
+#define ADC_INTSTS_FIFO_OVERRUN (1 << 3)
+#define ADC_INTSTS_ADC_READY (1 << 4)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_INTCLR adc interrupt clear definition
+ * @{
+ */
+#define ADC_INTCLR_NEG_SATURATION (1 << 0)
+#define ADC_INTCLR_POS_SATURATION (1 << 1)
+#define ADC_INTCLR_FIFO_UNDERRUN (1 << 2)
+#define ADC_INTCLR_FIFO_OVERRUN (1 << 3)
+#define ADC_INTCLR_ADC_READY (1 << 4)
+/**
+ * @}
+ */
+
+/**
+ * @brief ADC configuration structure
+ *
+ * @param clk_div ADC clock divison, use @ref ADC_CLK_DIV
+ * @param scan_conv_mode ADC scan mode enable
+ * @param continuous_conv_mode ADC continuous conversion enable
+ * @param differential_mode ADC differential mode enable
+ * @param resolution ADC resolution, use @ref ADC_RESOLUTION
+ * @param vref ADC reference select, use @ref ADC_VREF
+ */
+struct bflb_adc_config_s {
+ uint8_t clk_div;
+ uint8_t scan_conv_mode;
+ uint8_t continuous_conv_mode;
+ uint8_t differential_mode;
+ uint8_t resolution;
+ uint8_t vref;
+};
+
+/**
+ * @brief ADC channel select
+ *
+ * @param pos_chan Select ADC positive input in none-scan mode
+ * @param neg_chan Select ADC negative input in none-scan mode
+ */
+struct bflb_adc_channel_s {
+ uint8_t pos_chan;
+ uint8_t neg_chan;
+};
+
+/**
+ * @brief ADC result select
+ *
+ * @param pos_chan ADC positive channel
+ * @param neg_chan ADC negative channel
+ * @param value ADC value
+ * @param millivolt ADC voltage result
+ */
+struct bflb_adc_result_s {
+ int8_t pos_chan;
+ int8_t neg_chan;
+ int32_t value;
+ int32_t millivolt;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize adc.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save adc configuration
+ */
+void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *config);
+
+/**
+ * @brief Deinitialize adc.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable adc rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_adc_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Config adc channels to sample.
+ *
+ * @param [in] dev device handle
+ * @param [in] chan pointer to the channel configurations.
+ * @param [in] channels pair number of channels
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_adc_channel_config(struct bflb_device_s *dev, struct bflb_adc_channel_s *chan, uint8_t channels);
+
+/**
+ * @brief Start adc conversion
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_start_conversion(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop adc conversion
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_stop_conversion(struct bflb_device_s *dev);
+
+/**
+ * @brief Get adc number of completed conversions
+ *
+ * @param [in] dev device handle
+ * @return number of completed conversions
+ */
+uint8_t bflb_adc_get_count(struct bflb_device_s *dev);
+
+/**
+ * @brief Read adc conversion value
+ *
+ * @param [in] dev device handle
+ * @return conversion value
+ */
+uint32_t bflb_adc_read_raw(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable adc conversion completion interrupt.
+ * Triggerring when a channel conversion is completed.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_adc_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable adc error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_adc_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get adc interrupt instatus.
+ *
+ * @param [in] dev device handle
+ * @return interrupt instatus value, use @ref ADC_INTSTS
+ */
+uint32_t bflb_adc_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear adc interrupt instatus.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear interrupt clear value, use @ref ADC_INTCLR
+ */
+void bflb_adc_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Parse adc conversion value into millivolt and actual numerical value.
+ *
+ * @param [in] dev device handle
+ * @param [in] buffer pointer to adc original value from bflb_adc_read_raw api
+ * @param [out] result pointer to save parse result
+ * @param [in] count count to parse
+ */
+void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct bflb_adc_result_s *result, uint16_t count);
+
+/**
+ * @brief Initialize adc temperature sensor
+ *
+ * @param [in] dev device handle
+ * @param [in] tsen_mod temperature sensor mode, use @ref ADC_TSEN_MOD
+ */
+void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod);
+
+/**
+ * @brief Get adc temperature
+ *
+ * @param [in] dev device handle
+ * @return temperature
+ */
+float bflb_adc_tsen_get_temp(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable adc vbat power.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_vbat_enable(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable adc vbat power.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_vbat_disable(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_auadc.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_auadc.h
new file mode 100644
index 00000000..6e4785fc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_auadc.h
@@ -0,0 +1,182 @@
+#ifndef _BFLB_AUADC_H
+#define _BFLB_AUADC_H
+
+#include "bflb_core.h"
+
+/**
+ * @defgroup AUADC_SAMPLING_RATE auadc sampling rate
+ */
+#define AUADC_SAMPLING_RATE_8K 0 /* audio mode */
+#define AUADC_SAMPLING_RATE_16K 1 /* audio mode */
+#define AUADC_SAMPLING_RATE_24K 2 /* audio mode, same as 22.02K, adjust the AUPLL clock */
+#define AUADC_SAMPLING_RATE_32K 3 /* audio mode */
+#define AUADC_SAMPLING_RATE_48K 4 /* audio mode, same as 44.1K, adjust the AUPLL clock */
+#define AUADC_SAMPLING_RATE_MEASURE_128K 8 /* only used in ADC measurement mode */
+#define AUADC_SAMPLING_RATE_MEASURE_256K 9 /* only used in ADC measurement mode */
+#define AUADC_SAMPLING_RATE_MEASURE_512K 10 /* only used in ADC measurement mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUADC_INPUT_MODE auadc input mode
+ */
+#define AUADC_INPUT_MODE_ADC 0 /* Analog ADC */
+#define AUADC_INPUT_MODE_PDM_L 1 /* PDM left channel */
+#define AUADC_INPUT_MODE_PDM_R 2 /* PDM right channel */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUADC_DATA_FORMAT auadc data format
+ */
+#define AUADC_DATA_FORMAT_16BIT 3
+#define AUADC_DATA_FORMAT_20BIT 2
+#define AUADC_DATA_FORMAT_24BIT 1
+#define AUADC_DATA_FORMAT_32BIT 0
+/**
+ * @}
+ */
+
+/**
+ * @brief AUADC_ADC_ANALOG_CH auadc adc input ch
+ */
+#define AUADC_ADC_ANALOG_CH_0 0
+#define AUADC_ADC_ANALOG_CH_1 1
+#define AUADC_ADC_ANALOG_CH_2 2
+#define AUADC_ADC_ANALOG_CH_3 3
+#define AUADC_ADC_ANALOG_CH_4 4
+#define AUADC_ADC_ANALOG_CH_5 5
+#define AUADC_ADC_ANALOG_CH_6 6
+#define AUADC_ADC_ANALOG_CH_7 7
+/**
+ * @}
+ */
+
+/**
+ * @brief AUADC_ADC_MEASURE_RATE auadc adc Sampling rate in measurement mode, @ AUADC_SAMPLING_RATE_MEASURE_256K
+ */
+
+#define AUADC_ADC_MEASURE_RATE_SPS_2_5 0
+#define AUADC_ADC_MEASURE_RATE_SPS_5 1
+#define AUADC_ADC_MEASURE_RATE_SPS_10 2
+#define AUADC_ADC_MEASURE_RATE_SPS_20 3
+#define AUADC_ADC_MEASURE_RATE_SPS_25 4
+#define AUADC_ADC_MEASURE_RATE_SPS_50 5
+#define AUADC_ADC_MEASURE_RATE_SPS_100 6
+#define AUADC_ADC_MEASURE_RATE_SPS_200 7
+#define AUADC_ADC_MEASURE_RATE_SPS_400 8
+#define AUADC_ADC_MEASURE_RATE_SPS_800 9
+#define AUADC_ADC_MEASURE_RATE_SPS_1000 10
+#define AUADC_ADC_MEASURE_RATE_SPS_2000 11
+#define AUADC_ADC_MEASURE_RATE_SPS_4000 12
+
+/**
+ * @}
+ */
+
+/**
+ * @brief AUADC_ADC_MODE auadc adc mode
+ */
+#define AUADC_ADC_MODE_AUDIO 0
+#define AUADC_ADC_MODE_MEASURE 1
+/**
+ * @}
+ */
+
+/**
+ * @brief AUADC_ADC_PGA_MODE auadc adc mode, Ac or DC, differential or single
+ */
+#define AUADC_ADC_PGA_MODE_AC_DIFFER 0
+#define AUADC_ADC_PGA_MODE_AC_SINGLE 1
+#define AUADC_ADC_PGA_MODE_DC_DIFFER 2
+#define AUADC_ADC_PGA_MODE_DC_SINGLE 3
+/**
+ * @}
+ */
+
+/** @defgroup AUADC_INTMASK auadc interrupt status definition
+ * @{
+ */
+#define AUADC_INTMASK_FIFO_OVER (1 << 1)
+#define AUADC_INTMASK_FIFO_UNDER (1 << 2)
+#define AUADC_INTMASK_FIFO_AVAILABLE (1 << 3)
+/**
+ * @}
+ */
+
+/** @defgroup AUADC_INTSTS auadc interrupt status definition
+ * @{
+ */
+#define AUADC_INTSTS_FIFO_OVER (1 << 1)
+#define AUADC_INTSTS_FIFO_UNDER (1 << 2)
+#define AUADC_INTSTS_FIFO_AVAILABLE (1 << 4)
+/**
+ * @}
+ */
+
+/** @defgroup AUADC_CMD auadc feature control cmd definition
+ * @{
+ */
+#define AUADC_CMD_RECORD_START (0x01)
+#define AUADC_CMD_RECORD_STOP (0x02)
+#define AUADC_CMD_SET_VOLUME_VAL (0x03)
+#define AUADC_CMD_SET_PGA_GAIN_VAL (0x04)
+#define AUADC_CMD_CLEAR_RX_FIFO (0x05)
+#define AUADC_CMD_GET_RX_FIFO_CNT (0x06)
+/**
+ * @}
+ */
+
+/**
+ * @brief auadc initialization configuration structure
+ *
+ * @param sampling_rate auadc sampling rate, use @ref AUADC_SAMPLING_RATE
+ * @param input_mode auadc mode, use @ref AUADC_INPUT_MODE
+ * @param data_format auadc fifo data format, use @ref AUADC_DATA_FORMAT
+ * @param fifo_threshold auadc tx fifo threshold, 0 ~ 7
+ */
+struct bflb_auadc_init_config_s {
+ uint8_t sampling_rate;
+ uint8_t input_mode;
+ uint8_t data_format;
+ uint8_t fifo_threshold;
+};
+
+/**
+ * @brief auadc adc analog initialization configuration structure
+ *
+ * @param analog_adc_en auadc sampling rate, use true or false
+ * @param adc_mode auadc adc work pattern, use @ref AUADC_ADC_MODE
+ * @param adc_pga_mode auadc adc PGA mode, use @ref AUADC_ADC_PGA_MODE
+ * @param adc_pga_posi_ch auadc adc positive channel selection, use @ref AUADC_ADC_ANALOG_CH
+ * @param adc_pga_nega_ch auadc adc negative channel selection, This channel is valid only when adc_pga_mode is differential, use @ref AUADC_ADC_ANALOG_CH
+ * @param adc_pga_gain auadc adc PGA Gain control, 6dB ~ 42dB, step by 3db
+ * @param adc_measure_rate auadc adc sampling rate in measurement mode @ AUADC_SAMPLING_RATE_MEASURE_256K, use @ref AUADC_ADC_MEASURE_RATE
+ */
+struct bflb_auadc_adc_init_config_s {
+ uint8_t auadc_analog_en;
+ uint8_t adc_mode;
+ uint8_t adc_pga_mode;
+ uint8_t adc_pga_posi_ch;
+ uint8_t adc_pga_nega_ch;
+ uint8_t adc_pga_gain;
+ uint8_t adc_measure_rate;
+};
+
+int bflb_auadc_init(struct bflb_device_s *dev, const struct bflb_auadc_init_config_s *config);
+
+int bflb_auadc_adc_init(struct bflb_device_s *dev, const struct bflb_auadc_adc_init_config_s *config);
+
+int bflb_auadc_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+int bflb_auadc_int_mask(struct bflb_device_s *dev, uint32_t int_sts);
+
+int bflb_auadc_int_unmask(struct bflb_device_s *dev, uint32_t int_sts);
+
+int bflb_auadc_get_intstatus(struct bflb_device_s *dev);
+
+int bflb_auadc_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_audac.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_audac.h
new file mode 100644
index 00000000..5bf695ee
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_audac.h
@@ -0,0 +1,165 @@
+#ifndef _BFLB_AUDAC_H
+#define _BFLB_AUDAC_H
+
+#include "bflb_core.h"
+
+/**
+ * @defgroup AUDAC_SAMPLING_RATE audac sampling rate
+ */
+#define AUDAC_SAMPLING_RATE_8K 0
+#define AUDAC_SAMPLING_RATE_16K 1
+#define AUDAC_SAMPLING_RATE_22P05K 5
+#define AUDAC_SAMPLING_RATE_24K 3
+#define AUDAC_SAMPLING_RATE_32K 2
+#define AUDAC_SAMPLING_RATE_44P1K 6
+#define AUDAC_SAMPLING_RATE_48K 4
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUDAC_OUTPUT_MODE audac output mode
+ */
+#define AUDAC_OUTPUT_MODE_PWM 0
+#define AUDAC_OUTPUT_MODE_GPDAC_CH_A 1
+#define AUDAC_OUTPUT_MODE_GPDAC_CH_B 2
+#define AUDAC_OUTPUT_MODE_GPDAC_CH_A_B 3
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUDAC_SOURCE_CHANNEL source channels num
+ */
+#define AUDAC_SOURCE_CHANNEL_SINGLE 0x01
+#define AUDAC_SOURCE_CHANNEL_DUAL 0x03
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUDAC_MIXER_MODE audac mixer mode, this parameter is valid only in AUDAC_SOURCE_CHANNEL_DUAL mode
+ */
+#define AUDAC_MIXER_MODE_ONLY_L 0
+#define AUDAC_MIXER_MODE_ONLY_R 1
+#define AUDAC_MIXER_MODE_SUM 2
+#define AUDAC_MIXER_MODE_AVERAGE 3
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUDAC_DATA_FORMAT audac data format
+ */
+#define AUDAC_DATA_FORMAT_16BIT 3
+#define AUDAC_DATA_FORMAT_20BIT 2
+#define AUDAC_DATA_FORMAT_24BIT 1
+#define AUDAC_DATA_FORMAT_32BIT 0
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUDAC_RAMP_RATE audac volume ramp rate
+ */
+#define AUDAC_RAMP_RATE_FS_2 0
+#define AUDAC_RAMP_RATE_FS_4 1
+#define AUDAC_RAMP_RATE_FS_8 2
+#define AUDAC_RAMP_RATE_FS_16 3
+#define AUDAC_RAMP_RATE_FS_32 4
+#define AUDAC_RAMP_RATE_FS_64 5
+#define AUDAC_RAMP_RATE_FS_128 6
+#define AUDAC_RAMP_RATE_FS_256 7
+#define AUDAC_RAMP_RATE_FS_512 8
+#define AUDAC_RAMP_RATE_FS_1024 9
+#define AUDAC_RAMP_RATE_FS_2048 10
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AUDAC_VOLUME_UPDATE_MODE audac volume ramp rate
+ */
+#define AUDAC_VOLUME_UPDATE_MODE_FORCE 0
+#define AUDAC_VOLUME_UPDATE_MODE_RAMP 1
+#define AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING 2
+/**
+ * @}
+ */
+
+/** @defgroup AUDAC_INTSTS audac interrupt status definition
+ * @{
+ */
+#define AUDAC_INTSTS_VOLUME_RAMP (1 << 0)
+#define AUDAC_INTSTS_FIFO_OVER (1 << 1)
+#define AUDAC_INTSTS_FIFO_UNDER (1 << 2)
+#define AUDAC_INTSTS_FIFO_AVAILABLE (1 << 3)
+
+/** @defgroup AUDAC_CMD audac feature control cmd definition
+ * @{
+ */
+#define AUDAC_CMD_PLAY_START (0x01)
+#define AUDAC_CMD_PLAY_STOP (0x02)
+#define AUDAC_CMD_SET_MUTE (0x03)
+#define AUDAC_CMD_SET_VOLUME_VAL (0x04)
+#define AUDAC_CMD_CLEAR_TX_FIFO (0x05)
+#define AUDAC_CMD_GET_TX_FIFO_CNT (0x06)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief AUDAC initialization configuration structure
+ *
+ * @param sampling_rate AUDAC sampling rate, use @ref AUDAC_SAMPLING_RATE
+ * @param output_mode AUDAC mode, use @ref AUDAC_OUTPUT_MODE
+ * @param source_channels_num AUDAC source channels num, use @ref AUDAC_SOURCE_CHANNEL
+ * @param mixer_mode AUDAC mixer mode, valid only in AUDAC_SOURCE_CHANNEL_DUAL mode, use @ref AUDAC_MIXER_MODE
+ * @param data_format AUDAC audac data format, use @ref AUDAC_DATA_FORMAT
+ * @param fifo_threshold AUDAC tx fifo threshold, 0 ~ 7
+ * @param dma_enable AUDAC dma mode enable, use true or false
+ */
+struct bflb_audac_init_config_s {
+ uint8_t sampling_rate;
+ uint8_t output_mode;
+ uint8_t source_channels_num;
+ uint8_t mixer_mode;
+ uint8_t data_format;
+ uint8_t fifo_threshold;
+};
+
+/**
+ * @brief AUDAC volume configuration structure
+ *
+ * @param mute_ramp_en AUDAC mute mode en, use true or false
+ * @param mute_up_ramp_rate AUDAC mute up ramp rate, valid when mute_ramp_en is true, use @ref AUDAC_RAMP_RATE
+ * @param mute_down_ramp_rate AUDAC mute down ramp rate, valid when mute_ramp_en is true, use @ref AUDAC_RAMP_RATE
+ * @param volume_update_mode AUDAC volume update mode, use @ref AUDAC_VOLUME_UPDATE_MODE
+ * @param volume_ramp_rate AUDAC volume ramp rate, valid when volume_update_mode is not AUDAC_VOLUME_UPDATE_MODE_FORCE, use @ref AUDAC_RAMP_RATE
+ * @param volume_zero_cross_timeout AUDAC volume update zero cross timeout period, valid only in AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING mode
+ */
+struct bflb_audac_volume_config_s {
+ bool mute_ramp_en;
+ uint8_t mute_up_ramp_rate;
+ uint8_t mute_down_ramp_rate;
+ uint8_t volume_update_mode;
+ uint8_t volume_ramp_rate;
+ uint8_t volume_zero_cross_timeout;
+};
+
+int bflb_audac_init(struct bflb_device_s *dev, const struct bflb_audac_init_config_s *config);
+
+int bflb_audac_volume_init(struct bflb_device_s *dev, const struct bflb_audac_volume_config_s *vol_cfg);
+
+int bflb_audac_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+int bflb_audac_int_mask(struct bflb_device_s *dev, uint32_t mask);
+
+int bflb_audac_get_intstatus(struct bflb_device_s *dev);
+
+int bflb_audac_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+int bflb_audac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_cam.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_cam.h
new file mode 100644
index 00000000..44db5401
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_cam.h
@@ -0,0 +1,325 @@
+#ifndef _BFLB_CAM_H
+#define _BFLB_CAM_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup CAM
+ * @{
+ */
+
+/** @defgroup CAM_INPUT_FORMAT CAMERA input format definition
+ * @{
+ */
+#define CAM_INPUT_FORMAT_YUV422_YUYV 0
+#define CAM_INPUT_FORMAT_YUV422_YVYU 1
+#define CAM_INPUT_FORMAT_YUV422_UYVY 2
+#define CAM_INPUT_FORMAT_YUV422_VYUY 3
+#define CAM_INPUT_FORMAT_GRAY 4
+#define CAM_INPUT_FORMAT_RGB565 5
+#define CAM_INPUT_FORMAT_BGR565 6
+#define CAM_INPUT_FORMAT_RGB888 7
+#define CAM_INPUT_FORMAT_BGR888 8
+/**
+ * @}
+ */
+
+/** @defgroup CAM_OUTPUT_FORMAT CAMERA output format definition
+ * @{
+ */
+#define CAM_OUTPUT_FORMAT_AUTO 0
+#define CAM_OUTPUT_FORMAT_YUV422 1
+#define CAM_OUTPUT_FORMAT_GRAY 2
+#define CAM_OUTPUT_FORMAT_YUV422_UV 3
+#define CAM_OUTPUT_FORMAT_YUV420_UV 4
+#define CAM_OUTPUT_FORMAT_RGB565_OR_BGR565 5
+#define CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 6
+#if !defined(BL702)
+#define CAM_OUTPUT_FORMAT_RGB888_TO_RGB565 7
+#define CAM_OUTPUT_FORMAT_RGB888_TO_BGR565 8
+#define CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888 9
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup CAM_INTSTS CAMERA interrupt status definition
+ * @{
+ */
+#if defined(BL702)
+#define CAM_INTSTS_NORMAL (1 << 0)
+#define CAM_INTSTS_MEMORY_OVERWRITE (1 << 2)
+#define CAM_INTSTS_FRAME_OVERWRITE (1 << 4)
+#define CAM_INTSTS_FIFO_OVERWRITE (1 << 6)
+#define CAM_INTSTS_HSYNC_MISMATCH (1 << 8)
+#define CAM_INTSTS_VSYNC_MISMATCH (1 << 9)
+#else
+#define CAM_INTSTS_NORMAL (1 << 12)
+#define CAM_INTSTS_MEMORY_OVERWRITE (1 << 13)
+#define CAM_INTSTS_FRAME_OVERWRITE (1 << 14)
+#define CAM_INTSTS_FIFO_OVERWRITE (1 << 15)
+#define CAM_INTSTS_HSYNC_MISMATCH (1 << 21)
+#define CAM_INTSTS_VSYNC_MISMATCH (1 << 22)
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup CAM_INTMASK CAMERA interrupt mask definition
+ * @{
+ */
+#if defined(BL702)
+#define CAM_INTMASK_NORMAL (1 << 0)
+#define CAM_INTMASK_MEMORY_OVERWRITE (1 << 2)
+#define CAM_INTMASK_FRAME_OVERWRITE (1 << 3)
+#define CAM_INTMASK_FIFO_OVERWRITE (1 << 4)
+#define CAM_INTMASK_HSYNC_MISMATCH (1 << 5)
+#define CAM_INTMASK_VSYNC_MISMATCH (1 << 6)
+#else
+#define CAM_INTMASK_NORMAL (1 << 8)
+#define CAM_INTMASK_MEMORY_OVERWRITE (1 << 9)
+#define CAM_INTMASK_FRAME_OVERWRITE (1 << 10)
+#define CAM_INTMASK_FIFO_OVERWRITE (1 << 11)
+#define CAM_INTMASK_HSYNC_MISMATCH (1 << 6)
+#define CAM_INTMASK_VSYNC_MISMATCH (1 << 7)
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup CAM_INTCLR CAMERA interrupt clear definition
+ * @{
+ */
+#define CAM_INTCLR_NORMAL (1 << 4)
+#define CAM_INTCLR_MEMORY_OVERWRITE (1 << 5)
+#define CAM_INTCLR_FRAME_OVERWRITE (1 << 6)
+#define CAM_INTCLR_FIFO_OVERWRITE (1 << 7)
+#define CAM_INTCLR_HSYNC_MISMATCH (1 << 8)
+#define CAM_INTCLR_VSYNC_MISMATCH (1 << 9)
+/**
+ * @}
+ */
+
+/** @defgroup CAM_POLARITY CAMERA hsync/vsync polarity active level definition
+ * @{
+ */
+#define CAM_POLARITY_ACTIVE_LOW 0
+#define CAM_POLARITY_ACTIVE_HIGH 1
+/**
+ * @}
+ */
+
+/** @defgroup CAM_INPUT_SOURCE CAMERA input source definition
+ * @{
+ */
+#define CAM_INPUT_SOURCE_DVP 0
+#if defined(BL808)
+#define CAM_INPUT_SOURCE_CSI 1
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup CAM_BURST CAMERA burst length definition
+ * @{
+ */
+#define CAM_BURST_INCR1 0
+#define CAM_BURST_INCR4 1
+#define CAM_BURST_INCR8 2
+#define CAM_BURST_INCR16 3
+#if !defined(BL702)
+#define CAM_BURST_INCR32 5
+#define CAM_BURST_INCR64 6
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup CAM_CMD CAMERA feature control cmd definition
+ * @{
+ */
+#define CAM_CMD_SET_VSYNC_POLARITY 1
+#define CAM_CMD_SET_HSYNC_POLARITY 2
+#define CAM_CMD_SET_BURST 3
+#if !defined(BL702)
+#define CAM_CMD_SET_RGBA8888_ALPHA 4
+#define CAM_CMD_GET_FRAME_ID 5
+#endif
+#define CAM_CMD_WRAP_MODE 6
+#define CAM_CMD_COUNT_TRIGGER_NORMAL_INT 7
+#if !defined(BL702)
+#define CAM_CMD_FRAME_ID_RESET 8
+#define CAM_CMD_INVERSE_VSYNC_POLARITY 9
+#define CAM_CMD_INVERSE_HSYNC_POLARITY 10
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @brief CAM configuration structure
+ *
+ * @param input_format CAM input format, use @ref CAM_INPUT_FORMAT
+ * @param resolution_x CAM resolution x
+ * @param resolution_y CAM resolution y
+ * @param h_blank CAM Hsync blank
+ * @param pixel_clock CAM pixel clock
+ * @param with_mjpeg CAM with mjpeg or not
+ * @param input_source CAM input source, use @ref CAM_INPUT_SOURCE
+ * @param output_format CAM output format, use @ref CAM_OUTPUT_FORMAT
+ * @param output_bufaddr CAM output buffer address , must be align 16
+ * @param output_bufsize CAM output buffer size, should not be less than one frame size
+ */
+struct bflb_cam_config_s {
+ uint8_t input_format;
+ uint16_t resolution_x;
+ uint16_t resolution_y;
+ uint16_t h_blank;
+ uint32_t pixel_clock;
+ bool with_mjpeg;
+ uint8_t input_source;
+ uint8_t output_format;
+ uint32_t output_bufaddr;
+ uint32_t output_bufsize;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize cam.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to cam configure structure
+ */
+void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config);
+
+/**
+ * @brief Enable cam.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cam_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable cam.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cam_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Mask or unmask cam interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type cam interrupt mask type, use @ref CAM_INTMASK
+ * @param [in] mask mask or unmask
+ */
+void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
+
+/**
+ * @brief Clear cam interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type int_type cam interrupt clear type, use @ref CAM_INTCLR
+ */
+void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type);
+
+/**
+ * @brief Crop vsync.
+ *
+ * @param [in] dev device handle
+ * @param [in] start_line start line of window
+ * @param [in] end_line end line of window, not include
+ */
+void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line);
+
+/**
+ * @brief Crop hsync.
+ *
+ * @param [in] dev device handle
+ * @param [in] start_pixel start pixel of each line
+ * @param [in] end_pixel end pixel of each line, not include
+ */
+void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel);
+
+/**
+ * @brief Pop one frame.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cam_pop_one_frame(struct bflb_device_s *dev);
+
+#if !defined(BL702)
+/**
+ * @brief Swap input order of y and uv.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Set frame filter, if frame_count = 3, frame_valid = 101b, second frame will be dropped every 3 frames.
+ *
+ * @param [in] dev device handle
+ * @param [in] frame_count frame filter period
+ * @param [in] frame_valid frame valid
+ */
+void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid);
+#endif
+
+/**
+ * @brief Get frame count.
+ *
+ * @param [in] dev device handle
+ * @return Frame count
+ */
+uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev);
+
+/**
+ * @brief Get frame information.
+ *
+ * @param [in] dev device handle
+ * @param [out] pic pointer to frame start address
+ * @return Size of frame
+ */
+uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Interrupt status
+ */
+uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control cam feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure
+ */
+int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_cks.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_cks.h
new file mode 100644
index 00000000..eb68b49e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_cks.h
@@ -0,0 +1,64 @@
+#ifndef _BFLB_CKS_H
+#define _BFLB_CKS_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup CKS
+ * @{
+ */
+
+/** @defgroup CKS_ENDIAN cks endian definition
+ * @{
+ */
+#define CKS_LITTLE_ENDIAN 0
+#define CKS_BIG_ENDIAN 1
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Reset checksum module.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cks_reset(struct bflb_device_s *dev);
+
+/**
+ * @brief Set checksum bitorder.
+ *
+ * @param [in] dev device handle
+ * @param [in] endian cks endian, use @ref CKS_ENDIAN
+ */
+void bflb_cks_set_endian(struct bflb_device_s *dev, uint8_t endian);
+
+/**
+ * @brief Compute data with checksum.
+ *
+ * @param [in] dev device handle
+ * @param [in] data input data buffer
+ * @param [in] length data length
+ * @return checksum value
+ */
+uint16_t bflb_cks_compute(struct bflb_device_s *dev, uint8_t *data, uint32_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_clock.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_clock.h
new file mode 100644
index 00000000..30564c76
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_clock.h
@@ -0,0 +1,246 @@
+#ifndef _BFLB_CLOCK_H
+#define _BFLB_CLOCK_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup CLOCK
+ * @{
+ */
+
+/** @defgroup BFLB_SYSTEM_CLOCK system clock definition
+ * @{
+ */
+#define BFLB_SYSTEM_ROOT_CLOCK 0
+#define BFLB_SYSTEM_CPU_CLK 1
+#define BFLB_SYSTEM_PBCLK 2
+#define BFLB_SYSTEM_XCLK 3
+#define BFLB_SYSTEM_32K_CLK 4
+/**
+ * @}
+ */
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define BFLB_GLB_CGEN1_BASE (0x40000000 + 0x24)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define BFLB_GLB_CGEN1_BASE (0x20000000 + 0x584)
+#define BFLB_GLB_CGEN2_BASE (0x20000000 + 0x588)
+#endif
+
+#define PERIPHERAL_CLOCK_ADC_DAC_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 2); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#define PERIPHERAL_CLOCK_SEC_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 4); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#define PERIPHERAL_CLOCK_DMA0_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 12); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_DMA1_ENABLE()
+#define PERIPHERAL_CLOCK_DMA2_ENABLE()
+#endif
+
+#define PERIPHERAL_CLOCK_UART0_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 16); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#define PERIPHERAL_CLOCK_UART1_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 17); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_UART2_ENABLE()
+#endif
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_SPI0_1_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 18); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+#else
+#define PERIPHERAL_CLOCK_SPI0_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 18); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+#endif
+
+#define PERIPHERAL_CLOCK_I2C0_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 19); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_I2C1_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 25); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#endif
+
+#define PERIPHERAL_CLOCK_PWM0_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 20); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#define PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 21); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#define PERIPHERAL_CLOCK_IR_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 22); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_CAN_UART2_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 26); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+#elif defined(BL616) || defined(BL628)
+#define PERIPHERAL_CLOCK_CAN_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 26); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+#endif
+
+#if defined(BL702)
+#define PERIPHERAL_CLOCK_USB_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 28); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#define PERIPHERAL_CLOCK_I2S_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 26); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#elif defined(BL616) || defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_USB_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 13); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#define PERIPHERAL_CLOCK_I2S_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 27); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+
+#endif
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define PERIPHERAL_CLOCK_SDH_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
+ regval |= (1 << 22); \
+ putreg32(regval, BFLB_GLB_CGEN2_BASE); \
+ } while (0)
+#endif
+
+#if defined(BL702)
+#define PERIPHERAL_CLOCK_EMAC_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+ regval |= (1 << 13); \
+ putreg32(regval, BFLB_GLB_CGEN1_BASE); \
+ } while (0)
+#elif defined(BL616) || defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_EMAC_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
+ regval |= (1 << 23); \
+ putreg32(regval, BFLB_GLB_CGEN2_BASE); \
+ } while (0)
+#endif
+
+#if defined(BL616)
+#define PERIPHERAL_CLOCK_AUDIO_ENABLE() \
+ do { \
+ volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
+ regval |= (1 << 21); \
+ putreg32(regval, BFLB_GLB_CGEN2_BASE); \
+ } while (0)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get system clock frequence
+ *
+ * @param [in] type system clock type
+ * @return frequence
+ */
+uint32_t bflb_clk_get_system_clock(uint8_t type);
+
+/**
+ * @brief Get peripheral clock frequence
+ *
+ * @param [in] type peripheral type
+ * @param [in] idx peripheral index
+ * @return frequence
+ */
+uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_common.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_common.h
new file mode 100644
index 00000000..7bd1441e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_common.h
@@ -0,0 +1,106 @@
+#ifndef _BFLB_COMMON_H
+#define _BFLB_COMMON_H
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dst
+ * @param [in] src
+ * @param [in] n
+ * @return void*
+ */
+void *arch_memcpy(void *dst, const void *src, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] s
+ * @param [in] c
+ * @param [in] n
+ * @return void*
+ */
+void *arch_memset(void *s, uint8_t c, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] s1
+ * @param [in] s2
+ * @param [in] n
+ * @return int
+ */
+int arch_memcmp(const void *s1, const void *s2, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] dst
+ * @param [in] src
+ * @param [in] n
+ * @return uint32_t*
+ */
+uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] pdst
+ * @param [in] psrc
+ * @param [in] n
+ * @return void*
+ */
+void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] dst
+ * @param [in] val
+ * @param [in] n
+ * @return uint32_t*
+ */
+uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] cnt
+ */
+void arch_delay_us(uint32_t cnt);
+
+/**
+ * @brief
+ *
+ * @param [in] cnt
+ */
+void arch_delay_ms(uint32_t cnt);
+
+/**
+ * @brief
+ *
+ * @param [in] in
+ * @param [in] len
+ * @return [in] uint16_t
+ */
+uint16_t bflb_soft_crc16(void *in, uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] in
+ * @param [in] len
+ * @return [in] uint32_t
+ */
+uint32_t bflb_soft_crc32(void *in, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_core.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_core.h
new file mode 100644
index 00000000..7c7da553
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_core.h
@@ -0,0 +1,143 @@
+#ifndef _BFLB_CORE_H
+#define _BFLB_CORE_H
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "bflb_list.h"
+#include "bflb_mtimer.h"
+#include "bflb_irq.h"
+#include "bflb_common.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup CORE
+ * @{
+ */
+
+#if !defined(BL602) && !defined(BL702) && !defined(BL702L) && \
+ !defined(BL616) && !defined(BL606P) && !defined(BL808) && !defined(BL628)
+#error please define a supported chip
+#endif
+
+#ifdef CONFIG_PARAM_ASSERT
+#define ASSERT_PARAM(expr) ((expr) ? (void)0 : assert_func(__FILE__, __LINE__, __FUNCTION__, #expr))
+void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *string);
+#else
+#define ASSERT_PARAM(expr) ((void)0U)
+#endif
+
+#if defined(BL702)
+#define BFLB_PSRAM_BASE 0x26000000
+#elif defined(BL616)
+#define BFLB_PSRAM_BASE 0xA8000000
+#elif defined(BL808)
+#define BFLB_PSRAM_BASE 0x50000000
+#elif defined(BL606P)
+#define BFLB_PSRAM_BASE 0x54000000
+#endif
+
+#define BFLB_DEVICE_TYPE_ADC 0
+#define BFLB_DEVICE_TYPE_DAC 1
+#define BFLB_DEVICE_TYPE_AUDIOADC 2
+#define BFLB_DEVICE_TYPE_AUDIODAC 3
+#define BFLB_DEVICE_TYPE_GPIO 4
+#define BFLB_DEVICE_TYPE_UART 5
+#define BFLB_DEVICE_TYPE_SPI 6
+#define BFLB_DEVICE_TYPE_I2C 7
+#define BFLB_DEVICE_TYPE_DMA 8
+#define BFLB_DEVICE_TYPE_I2S 9
+#define BFLB_DEVICE_TYPE_IR 10
+#define BFLB_DEVICE_TYPE_TIMER 11
+#define BFLB_DEVICE_TYPE_PWM 12
+#define BFLB_DEVICE_TYPE_ISO11898 13
+#define BFLB_DEVICE_TYPE_CAMERA 14
+#define BFLB_DEVICE_TYPE_FLASH 15
+#define BFLB_DEVICE_TYPE_QSPI 16
+#define BFLB_DEVICE_TYPE_SDH 17
+#define BFLB_DEVICE_TYPE_SDU 18
+#define BFLB_DEVICE_TYPE_ETH 19
+#define BFLB_DEVICE_TYPE_RTC 20
+#define BFLB_DEVICE_TYPE_CRC 21
+#define BFLB_DEVICE_TYPE_RNG 22
+#define BFLB_DEVICE_TYPE_MIPI 23
+#define BFLB_DEVICE_TYPE_DPI 24
+#define BFLB_DEVICE_TYPE_DSI 25
+#define BFLB_DEVICE_TYPE_CSI 26
+#define BFLB_DEVICE_TYPE_USB 27
+#define BFLB_DEVICE_TYPE_AES 28
+#define BFLB_DEVICE_TYPE_SHA 29
+#define BFLB_DEVICE_TYPE_MD5 30
+#define BFLB_DEVICE_TYPE_TRNG 31
+#define BFLB_DEVICE_TYPE_PKA 32
+#define BFLB_DEVICE_TYPE_CKS 33
+#define BFLB_DEVICE_TYPE_MJPEG 34
+#define BFLB_DEVICE_TYPE_KYS 35
+#define BFLB_DEVICE_TYPE_DBI 36
+#define BFLB_DEVICE_TYPE_PEC 37
+#define BFLB_DEVICE_TYPE_WDT 38
+#define BFLB_DEVICE_TYPE_EF_CTRL 39
+#define BFLB_DEVICE_TYPE_SDIO3 40
+#define BFLB_DEVICE_TYPE_SDIO2 41
+
+struct bflb_device_s {
+ const char *name;
+ uint32_t reg_base;
+ uint8_t irq_num;
+ uint8_t idx;
+ uint8_t sub_idx;
+ uint8_t dev_type;
+ void *user_data;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get device handle by name.
+ *
+ * @param [in] name device name
+ * @return device handle
+ */
+struct bflb_device_s *bflb_device_get_by_name(const char *name);
+
+/**
+ * @brief Get device handle by type and index.
+ *
+ * @param [in] type device type
+ * @param [in] idx device index
+ * @return device handle
+ */
+struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx);
+
+/**
+ * @brief Set user data into device handle.
+ *
+ * @param [in] device device handle
+ * @param [in] user_data pointer to user data
+ */
+void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_csi.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_csi.h
new file mode 100644
index 00000000..d430a4e3
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_csi.h
@@ -0,0 +1,158 @@
+#ifndef _BFLB_CSI_H
+#define _BFLB_CSI_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup CSI
+ * @{
+ */
+
+/** @defgroup CSI_LANE_NUMBER CSI lane number definition
+ * @{
+ */
+#define CSI_LANE_NUMBER_1 0
+#define CSI_LANE_NUMBER_2 1
+/**
+ * @}
+ */
+
+/** @defgroup CSI_INTSTS CSI interrupt status definition
+ * @{
+ */
+#define CSI_INTSTS_GENERIC_PACKET (1 << 0)
+#define CSI_INTSTS_LANE_MERGE_ERROR (1 << 1)
+#define CSI_INTSTS_ECC_ERROR (1 << 2)
+#define CSI_INTSTS_CRC_ERROR (1 << 3)
+#define CSI_INTSTS_PHY_HS_SOT_ERROR (1 << 4)
+#define CSI_INTSTS_PHY_HS_SOT_SYNC_ERROR (1 << 5)
+/**
+ * @}
+ */
+
+/** @defgroup CSI_INTMASK CSI interrupt mask definition
+ * @{
+ */
+#define CSI_INTMASK_GENERIC_PACKET (1 << 0)
+#define CSI_INTMASK_LANE_MERGE_ERROR (1 << 1)
+#define CSI_INTMASK_ECC_ERROR (1 << 2)
+#define CSI_INTMASK_CRC_ERROR (1 << 3)
+#define CSI_INTMASK_PHY_HS_SOT_ERROR (1 << 4)
+#define CSI_INTMASK_PHY_HS_SOT_SYNC_ERROR (1 << 5)
+/**
+ * @}
+ */
+
+/** @defgroup CSI_INTCLR CSI interrupt clear definition
+ * @{
+ */
+#define CSI_INTCLR_GENERIC_PACKET (1 << 0)
+#define CSI_INTCLR_LANE_MERGE_ERROR (1 << 1)
+#define CSI_INTCLR_ECC_ERROR (1 << 2)
+#define CSI_INTCLR_CRC_ERROR (1 << 3)
+#define CSI_INTCLR_PHY_HS_SOT_ERROR (1 << 4)
+#define CSI_INTCLR_PHY_HS_SOT_SYNC_ERROR (1 << 5)
+/**
+ * @}
+ */
+
+/**
+ * @brief CSI configuration structure
+ *
+ * @param lane_number CSI lane number, use @ref CSI_LANE_NUMBER
+ * @param tx_clk_escape CSI tx clock in escape mode
+ * @param data_rate CSI data rate
+ */
+struct bflb_csi_config_s {
+ uint8_t lane_number;
+ uint32_t tx_clk_escape;
+ uint32_t data_rate;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize csi.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to csi configure structure
+ */
+void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config);
+
+/**
+ * @brief Enable csi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_csi_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable csi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_csi_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Set threshold of line buffer, data will be sent to following module when threshold reached.
+ *
+ * @param [in] dev device handle
+ * @param [in] resolution_x number of columns
+ * @param [in] pixel_clock pixel clock
+ * @param [in] dsp_clock dsp clock
+ */
+void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock);
+
+/**
+ * @brief Mask or unmask csi interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type csi interrupt mask type, use @ref CSI_INTMASK
+ * @param [in] mask mask or unmask
+ */
+void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
+
+/**
+ * @brief Clear csi interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type csi interrupt clear type, use @ref CSI_INTCLR
+ */
+void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type);
+
+/**
+ * @brief Get csi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Interrupt status
+ */
+uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control csi feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure
+ */
+int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dac.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dac.h
new file mode 100644
index 00000000..39892a51
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dac.h
@@ -0,0 +1,98 @@
+#ifndef _BFLB_DAC_H
+#define _BFLB_DAC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @defgroup DAC_CLK_DIV dac clock div definition
+ * @{
+ */
+#define DAC_CLK_DIV_16 0
+#define DAC_CLK_DIV_32 1
+#define DAC_CLK_DIV_64 3
+#define DAC_CLK_DIV_1 4
+/**
+ * @}
+ */
+
+/** @defgroup DAC_CHANNEL dac channel select
+ * @{
+ */
+#define DAC_CHANNEL_A (1 << 0)
+#define DAC_CHANNEL_B (1 << 1)
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize dac frequence.
+ *
+ * @param [in] dev device handle
+ * @param [in] frequence dac clock div, use @ref DAC_CLK_DIV
+ */
+void bflb_dac_init(struct bflb_device_s *dev, uint8_t clk_div);
+
+/**
+ * @brief Deinitialize dac.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dac_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable dac tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_dac_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable dac channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_dac_channel_enable(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Disable dac channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_dac_channel_disable(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Set dac output value
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] value output value
+ */
+void bflb_dac_set_value(struct bflb_device_s *dev, uint8_t ch, uint16_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dbi.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dbi.h
new file mode 100644
index 00000000..5c40688c
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dbi.h
@@ -0,0 +1,295 @@
+#ifndef _BFLB_DBI_H
+#define _BFLB_DBI_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup DBI
+ * @{
+ */
+
+#if defined(BL616)
+#define DBI_QSPI_SUPPORT 1
+#define DBI_YUV_SUPPORT 1
+#define DBI_WRITE_DATA_BYTE_MAX 256
+#define DBI_READ_DATA_BYTE_MAX 8
+#define SPI_FIFO_NUM_MAX 8
+#elif defined(BL606P) || defined(BL808)
+#define DBI_QSPI_SUPPORT 0
+#define DBI_YUV_SUPPORT 0
+#define DBI_WRITE_DATA_BYTE_MAX 4
+#define DBI_READ_DATA_BYTE_MAX 4
+#define SPI_FIFO_NUM_MAX 8
+#else
+#error "unknown device"
+#endif
+
+#define DBI_WRITE_PIXEL_CNT_MAX 0x00FFFFFF
+
+/** @defgroup DBI_MODE dbi working mode definition
+ * @{
+ */
+#define DBI_MODE_TYPE_B 0 /* mipi-dbi typeB 8-wire-data mode */
+#define DBI_MODE_TYPE_C_4_WIRE 1 /* mipi-dbi typeC 4-wire mode */
+#define DBI_MODE_TYPE_C_3_WIRE 2 /* mipi-dbi typeC 3-wire mode */
+#if (DBI_QSPI_SUPPORT)
+#define DBI_MODE_EX_QSPI 3 /* Not the mipi standard. Extra support for QSPI mode */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup DBI_PIXEL_INPUT_FORMAT dbi fifo input pixel format, the FIFO are filled in 32-bits width definition
+ * @{
+ */
+#define DBI_PIXEL_INPUT_FORMAT_NBGR_8888 0 /* 32-bit/pixel, memory byte: [0]->pixel[0][R], [1]->pixel[0][G], [2]->pixel[0][B], [3]->invalid, [4]->pixel[1][R], ... */
+#define DBI_PIXEL_INPUT_FORMAT_NRGB_8888 1 /* 32-bit/pixel, memory byte: [0]->pixel[0][B], [1]->pixel[0][G], [2]->pixel[0][R], [3]->invalid, [4]->pixel[1][B], ... */
+#define DBI_PIXEL_INPUT_FORMAT_BGRN_8888 2 /* 32-bit/pixel, memory byte: [0]->invalid, [1]->pixel[0][R], [2]->pixel[0][G], [3]->pixel[0][B], [4]->invalid, [5]->pixel[1][R], ... */
+#define DBI_PIXEL_INPUT_FORMAT_RGBN_8888 3 /* 32-bit/pixel, memory byte: [0]->invalid, [1]->pixel[0][B], [2]->pixel[0][G], [3]->pixel[0][R], [4]->invalid, [5]->pixel[1][B], ... */
+#define DBI_PIXEL_INPUT_FORMAT_RGB_888 4 /* 24-bit/pixel, memory byte: [0]->pixel[0][R], [1]->pixel[0][G], [2]->pixel[0][B], [3]->pixel[1][R], [4]->pixel[1][G], ... */
+#define DBI_PIXEL_INPUT_FORMAT_BGR_888 5 /* 24-bit/pixel, memory byte: [0]->pixel[0][B], [1]->pixel[0][G], [2]->pixel[0][R], [3]->pixel[1][B], [4]->pixel[1][G], ... */
+#define DBI_PIXEL_INPUT_FORMAT_BGR_565 6 /* 16-bit/pixel, */
+#define DBI_PIXEL_INPUT_FORMAT_RGB_565 7 /* 16-bit/pixel, */
+/**
+ * @}
+ */
+
+/** @defgroup DBI_PIXEL_OUTPUT_FORMAT dbi output pixel format definition
+ * @{
+ */
+#define DBI_PIXEL_OUTPUT_FORMAT_RGB_565 0 /* 16-bit/pixel */
+#define DBI_PIXEL_OUTPUT_FORMAT_RGB_888 1 /* 24-bit/pixel, Compatible with RGB666 format */
+/**
+ * @}
+ */
+
+/** @defgroup DBI_CLOCK_MODE dbi clock phase and polarity definition
+ * @{
+ */
+#define DBI_CLOCK_MODE_0 0 /* CPOL=0 CHPHA=0 */
+#define DBI_CLOCK_MODE_1 1 /* CPOL=0 CHPHA=1 */
+#define DBI_CLOCK_MODE_2 2 /* CPOL=1 CHPHA=0 */
+#define DBI_CLOCK_MODE_3 3 /* CPOL=1 CHPHA=1 */
+/**
+ * @}
+ */
+
+/** @defgroup DBI_QSPI_WIRE_NUM dbi qspi wire num definition
+ * @{
+ */
+#define DBI_QSPI_WIRE_NUM_1 0 /* 1-wire mode */
+#define DBI_QSPI_WIRE_NUM_4 1 /* 4-wire mode */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_INTSTS dbi interrupt status definition
+ * @{
+ */
+#define DBI_INTSTS_TC (1 << 0)
+#define SPI_INTSTS_TX_FIFO (1 << 1)
+#define SPI_INTSTS_FIFO_ERR (1 << 2)
+/**
+ * @}
+ */
+
+/** @defgroup DBI_INTCLR dbi interrupt clear definition
+ * @{
+ */
+#define DBI_INTCLR_TC (1 << 0)
+/**
+ * @}
+ */
+
+/** @defgroup DBI_CMD dbi feature control cmd definition
+ * @{
+ */
+#define DBI_CMD_CLEAR_TX_FIFO (0x01)
+#define DBI_CMD_GET_TX_FIFO_CNT (0x02)
+#define DBI_CMD_MASK_CMD_PHASE (0x03)
+#define DBI_CMD_CS_CONTINUE (0x04)
+#define DBI_CMD_SET_DUMMY_CNT (0x05)
+#define DBI_CMD_GET_SIZE_OF_PIXEL_CNT (0x06)
+#define DBI_CMD_INPUT_PIXEL_FORMAT (0x07)
+#define DBI_CMD_OUTPUT_PIXEL_FORMAT (0x08)
+#if (DBI_QSPI_SUPPORT)
+#define DBI_CMD_YUV_TO_RGB_ENABLE (0x10)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DBI configuration structure
+ *
+ * @param dbi_mode DBI working mode, use @ref DBI_MODE
+ * @param pixel_input_format DBI input pixel_format, use @ref DBI_PIXEL_INPUT_FORMAT
+ * @param pixel_output_format DBI output pixel_format, use @ref DBI_PIXEL_OUTPUT_FORMAT
+ * @param clk_mode DBI clock phase and polarity, use @ref DBI_CLOCK_MODE
+ * @param clk_freq_hz DBI clock frequency
+ * @param tx_fifo_threshold DBI tx fifo threshold, should be less than 16
+ * @param cmd_wire_mode DBI qspi mode, number of wire in the command phase, use @ref DBI_QSPI_WIRE_NUM
+ * @param addr_wire_mode DBI qspi mode, number of wire in the address phase, use @ref DBI_QSPI_WIRE_NUM
+ * @param data_wire_mode DBI qspi mode, number of wire in the data phase, use @ref DBI_QSPI_WIRE_NUM
+ */
+struct bflb_dbi_config_s {
+ uint8_t dbi_mode;
+ uint8_t pixel_input_format;
+ uint8_t pixel_output_format;
+ uint8_t clk_mode;
+ uint32_t clk_freq_hz;
+ uint8_t tx_fifo_threshold;
+#if (DBI_QSPI_SUPPORT)
+ uint8_t cmd_wire_mode;
+ uint8_t addr_wire_mode;
+ uint8_t data_wire_mode;
+#endif
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize dbi.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save dbi config
+ */
+void bflb_dbi_init(struct bflb_device_s *dev, const struct bflb_dbi_config_s *config);
+
+/**
+ * @brief Deinitialize dbi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dbi_deinit(struct bflb_device_s *dev);
+
+#if DBI_QSPI_SUPPORT
+/**
+ * @brief Set the address value and address length of the QSPI
+ *
+ * @param [in] dev device handle
+ * @param [in] addr_byte_size address size(byte), range 1 ~ 4
+ * @param [in] addr_val address value: [0:7]->addr[0], [8:15]->addr[1], [16:23]->addr[2], [24:31]->addr[3].
+ */
+void bflb_dbi_qspi_set_addr(struct bflb_device_s *dev, uint8_t addr_byte_size, uint32_t addr_val);
+
+#endif
+
+/**
+ * @brief Send cmd with pixel data, send cmd -> send address(only QSPI mode) -> send parameter_data.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd command
+ * @param [in] data_len Parameter length (byte), The maximum is DBI_WRITE_DATA_BYTE_MAX
+ * @param [in] data_buff Parameter buffer, Cannot be null
+ * @return
+ */
+int bflb_dbi_send_cmd_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff);
+
+/**
+ * @brief To read the data after sending the command, send cmd -> send address(only QSPI mode) -> read parameter_data.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd command
+ * @param [in] data_len Length of data to be read (byte), The maximum is DBI_READ_DATA_BYTE_MAX
+ * @param [in] data_buff Buff of data to be read, discard data if null
+ * @return
+ */
+int bflb_dbi_send_cmd_read_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff);
+
+/**
+ * @brief Send cmd with pixel data, send cmd -> send address(only QSPI mode) -> send pixel_data,
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd command
+ * @param [in] pixel_cnt Number of pixels,The maximum is DBI_WRITE_PIXEL_CNT_MAX
+ * @param [in] pixel_buff Pixels buffer, NULL when using DMA, in which case data needs to be transferred by DMA later, and wait for the transfer to complete
+ * @return
+ */
+int bflb_dbi_send_cmd_pixel(struct bflb_device_s *dev, uint8_t cmd, uint32_t pixel_cnt, void *pixel_buff);
+
+/**
+ * @brief Enable dbi tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_dbi_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable or disable dbi rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dbi_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable dbi transfer completion interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dbi_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable dbi error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dbi_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get dbi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref DBI_INTSTS
+ */
+uint32_t bflb_dbi_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear dbi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref SPI_INTCLR
+ */
+void bflb_dbi_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Control dbi feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref DBI_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_dbi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dma.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dma.h
new file mode 100644
index 00000000..fb7aeed1
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_dma.h
@@ -0,0 +1,506 @@
+#ifndef _BFLB_DMA_H
+#define _BFLB_DMA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @defgroup DMA_DIRECTION dma transfer direction definition
+ * @{
+ */
+#define DMA_MEMORY_TO_MEMORY 0
+#define DMA_MEMORY_TO_PERIPH 1
+#define DMA_PERIPH_TO_MEMORY 2
+#define DMA_PERIPH_TO_PERIPH 3
+/**
+ * @}
+ */
+
+/** @defgroup DMA_ADDR_INCREMENT dma source and destination address increment definition
+ * @{
+ */
+#define DMA_ADDR_INCREMENT_DISABLE 0
+#define DMA_ADDR_INCREMENT_ENABLE 1
+/**
+ * @}
+ */
+
+/** @defgroup DMA_DATA_WIDTH dma data width definition
+ * @{
+ */
+#define DMA_DATA_WIDTH_8BIT 0
+#define DMA_DATA_WIDTH_16BIT 1
+#define DMA_DATA_WIDTH_32BIT 2
+/**
+ * @}
+ */
+
+/** @defgroup DMA_BURST_COUNT dma burst increment count definition
+ * @{
+ */
+#define DMA_BURST_INCR1 0
+#define DMA_BURST_INCR4 1
+#define DMA_BURST_INCR8 2
+#define DMA_BURST_INCR16 3
+/**
+ * @}
+ */
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+ * @{
+ */
+#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
+#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
+#if !defined(BL702L)
+#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
+#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C)
+#endif
+#define DMA_ADDR_I2C0_TDR (0x4000A300 + 0x88)
+#define DMA_ADDR_I2C0_RDR (0x4000A300 + 0x8C)
+#define DMA_ADDR_SPI0_TDR (0x4000A200 + 0x88)
+#define DMA_ADDR_SPI0_RDR (0x4000A200 + 0x8C)
+#if !defined(BL702L)
+#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
+#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
+#endif
+#define DMA_ADDR_ADC_RDR (0x40002000 + 0x04)
+#if !defined(BL702L)
+#define DMA_ADDR_DAC_TDR (0x40002000 + 0x48)
+#endif
+#if defined(BL702L)
+#define DMA_ADDR_IR_TDR (0x4000A600 + 0x88)
+#define DMA_ADDR_AUADC_RDR (0x4000AD00 + 0x88)
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+ * @{
+ */
+#define DMA_REQUEST_NONE 0x00000000
+#define DMA_REQUEST_UART0_RX 0x00000000
+#define DMA_REQUEST_UART0_TX 0x00000001
+#if !defined(BL702L)
+#define DMA_REQUEST_UART1_RX 0x00000002
+#define DMA_REQUEST_UART1_TX 0x00000003
+#endif
+#define DMA_REQUEST_I2C0_RX 0x00000006
+#define DMA_REQUEST_I2C0_TX 0x00000007
+#if defined(BL702L)
+#define DMA_REQUEST_IR_TX 0x00000008
+#endif
+#define DMA_REQUEST_SPI0_RX 0x0000000A
+#define DMA_REQUEST_SPI0_TX 0x0000000B
+#if defined(BL702L)
+#define DMA_REQUEST_AUADC_RX 0x0000000D
+#endif
+#if !defined(BL702L)
+#define DMA_REQUEST_I2S_RX 0x00000014
+#define DMA_REQUEST_I2S_TX 0x00000015
+#endif
+#define DMA_REQUEST_ADC 0x00000016
+#if !defined(BL702L)
+#define DMA_REQUEST_DAC 0x00000017
+#endif
+/**
+ * @}
+ */
+
+#elif defined(BL616)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+ * @{
+ */
+#define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88)
+#define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C)
+#define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88)
+#define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C)
+#define DMA_ADDR_I2C0_TDR (0x2000A300 + 0x88)
+#define DMA_ADDR_I2C0_RDR (0x2000A300 + 0x8C)
+#define DMA_ADDR_SPI0_TDR (0x2000A200 + 0x88)
+#define DMA_ADDR_SPI0_RDR (0x2000A200 + 0x8C)
+#define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88)
+#define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C)
+#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04)
+#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48)
+#define DMA_ADDR_DBI_TDR (0x2000A800 + 0x88)
+#define DMA_ADDR_AUDAC_TDR (0x20055000 + 0x94)
+#define DMA_ADDR_AUADC_RDR (0x2000A000 + 0xC88)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+ * @{
+ */
+#define DMA_REQUEST_NONE 0x00000000
+#define DMA_REQUEST_UART0_RX 0x00000000
+#define DMA_REQUEST_UART0_TX 0x00000001
+#define DMA_REQUEST_UART1_RX 0x00000002
+#define DMA_REQUEST_UART1_TX 0x00000003
+#define DMA_REQUEST_I2C0_RX 0x00000006
+#define DMA_REQUEST_I2C0_TX 0x00000007
+#define DMA_REQUEST_SPI0_RX 0x0000000A
+#define DMA_REQUEST_SPI0_TX 0x0000000B
+#define DMA_REQUEST_DBI_TX 0x00000014
+#define DMA_REQUEST_AUADC_RX 0x00000015
+#define DMA_REQUEST_AUDAC_TX 0x0000000D
+#define DMA_REQUEST_I2S_RX 0x00000010
+#define DMA_REQUEST_I2S_TX 0x00000011
+#define DMA_REQUEST_ADC 0x00000016
+#define DMA_REQUEST_DAC 0x00000017
+#define DMA_REQUEST_PEC0_SM0_RX 0x00000018
+#define DMA_REQUEST_PEC0_SM1_RX 0x00000019
+#define DMA_REQUEST_PEC0_SM2_RX 0x0000001A
+#define DMA_REQUEST_PEC0_SM3_RX 0x0000001B
+#define DMA_REQUEST_PEC0_SM0_TX 0x0000001C
+#define DMA_REQUEST_PEC0_SM1_TX 0x0000001D
+#define DMA_REQUEST_PEC0_SM2_TX 0x0000001E
+#define DMA_REQUEST_PEC0_SM3_TX 0x0000001F
+
+/**
+ * @}
+ */
+
+#elif defined(BL808) || defined(BL606P)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+ * @{
+ */
+#define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88)
+#define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C)
+#define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88)
+#define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C)
+#define DMA_ADDR_UART2_TDR (0x2000AA00 + 0x88)
+#define DMA_ADDR_UART2_RDR (0x2000AA00 + 0x8C)
+#define DMA_ADDR_UART3_TDR (0x30002000 + 0x88)
+#define DMA_ADDR_UART3_RDR (0x30002000 + 0x8C)
+#define DMA_ADDR_I2C0_TDR (0x2000A300 + 0x88)
+#define DMA_ADDR_I2C0_RDR (0x2000A300 + 0x8C)
+#define DMA_ADDR_I2C1_TDR (0x2000A900 + 0x88)
+#define DMA_ADDR_I2C1_RDR (0x2000A900 + 0x8C)
+#define DMA_ADDR_I2C2_TDR (0x30003000 + 0x88)
+#define DMA_ADDR_I2C2_RDR (0x30003000 + 0x8C)
+#define DMA_ADDR_I2C3_TDR (0x30004000 + 0x88)
+#define DMA_ADDR_I2C3_RDR (0x30004000 + 0x8C)
+#define DMA_ADDR_SPI0_TDR (0x2000A200 + 0x88)
+#define DMA_ADDR_SPI0_RDR (0x2000A200 + 0x8C)
+#define DMA_ADDR_SPI1_TDR (0x30008000 + 0x88)
+#define DMA_ADDR_SPI1_RDR (0x30008000 + 0x8C)
+#define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88)
+#define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C)
+#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04)
+#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48)
+#define DMA_ADDR_IR_TDR (0x2000A600 + 0x88)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+ * @{
+ */
+#define DMA_REQUEST_NONE 0x00000000
+#define DMA_REQUEST_UART0_RX 0x00000000
+#define DMA_REQUEST_UART0_TX 0x00000001
+#define DMA_REQUEST_UART1_RX 0x00000002
+#define DMA_REQUEST_UART1_TX 0x00000003
+#define DMA_REQUEST_UART2_RX 0x00000004
+#define DMA_REQUEST_UART2_TX 0x00000005
+#define DMA_REQUEST_I2C0_RX 0x00000006
+#define DMA_REQUEST_I2C0_TX 0x00000007
+#define DMA_REQUEST_IR_TX 0x00000008
+#define DMA_REQUEST_SPI0_RX 0x0000000A
+#define DMA_REQUEST_SPI0_TX 0x0000000B
+#define DMA_REQUEST_AUDIO_RX 0x0000000C
+#define DMA_REQUEST_AUDIO_TX 0x0000000D
+#define DMA_REQUEST_I2C1_RX 0x0000000E
+#define DMA_REQUEST_I2C1_TX 0x0000000F
+#define DMA_REQUEST_I2S_RX 0x00000010
+#define DMA_REQUEST_I2S_TX 0x00000011
+#define DMA_REQUEST_ADC 0x00000016
+#define DMA_REQUEST_DAC 0x00000017
+
+/* Only support dma2 */
+#define DMA_REQUEST_UART3_RX 0x00000000
+#define DMA_REQUEST_UART3_TX 0x00000001
+#define DMA_REQUEST_SPI1_RX 0x00000002
+#define DMA_REQUEST_SPI1_TX 0x00000003
+#define DMA_REQUEST_I2C2_RX 0x00000006
+#define DMA_REQUEST_I2C2_TX 0x00000007
+#define DMA_REQUEST_I2C3_RX 0x00000008
+#define DMA_REQUEST_I2C3_TX 0x00000009
+/**
+ * @}
+ */
+
+#elif defined(BL628)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+ * @{
+ */
+#define DMA_ADDR_UART0_TDR (0x20010000 + 0x88)
+#define DMA_ADDR_UART0_RDR (0x20010000 + 0x8C)
+#define DMA_ADDR_UART1_TDR (0x20011000 + 0x88)
+#define DMA_ADDR_UART1_RDR (0x20011000 + 0x8C)
+#define DMA_ADDR_UART2_TDR (0x20012000 + 0x88)
+#define DMA_ADDR_UART2_RDR (0x20012000 + 0x8C)
+#define DMA_ADDR_I2C0_TDR (0x20014000 + 0x88)
+#define DMA_ADDR_I2C0_RDR (0x20014000 + 0x8C)
+#define DMA_ADDR_I2C1_TDR (0x20015000 + 0x88)
+#define DMA_ADDR_I2C1_RDR (0x20015000 + 0x8C)
+#define DMA_ADDR_SPI0_TDR (0x20018000 + 0x88)
+#define DMA_ADDR_SPI0_RDR (0x20018000 + 0x8C)
+#define DMA_ADDR_I2S_TDR (0x2001E000 + 0x88)
+#define DMA_ADDR_I2S_RDR (0x2001E000 + 0x8C)
+#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04)
+#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+ * @{
+ */
+#define DMA_REQUEST_NONE 0x00000000
+#define DMA_REQUEST_UART0_RX 0x00000000
+#define DMA_REQUEST_UART0_TX 0x00000001
+#define DMA_REQUEST_UART1_RX 0x00000002
+#define DMA_REQUEST_UART1_TX 0x00000003
+#define DMA_REQUEST_UART2_RX 0x00000004
+#define DMA_REQUEST_UART2_TX 0x00000005
+#define DMA_REQUEST_I2C0_RX 0x00000006
+#define DMA_REQUEST_I2C0_TX 0x00000007
+#define DMA_REQUEST_I2C1_RX 0x00000008
+#define DMA_REQUEST_I2C1_TX 0x00000009
+#define DMA_REQUEST_SPI0_RX 0x0000000A
+#define DMA_REQUEST_SPI0_TX 0x0000000B
+#define DMA_REQUEST_I2S_RX 0x00000010
+#define DMA_REQUEST_I2S_TX 0x00000011
+#define DMA_REQUEST_ADC 0x00000016
+#define DMA_REQUEST_DAC 0x00000017
+/**
+ * @}
+ */
+
+#endif
+
+/** @defgroup DMA_CMD dma feature control cmd definition
+ * @{
+ */
+#define DMA_CMD_SET_SRCADDR_INCREMENT (0x01)
+#define DMA_CMD_SET_DSTADDR_INCREMENT (0x02)
+#define DMA_CMD_SET_ADD_MODE (0x03)
+#define DMA_CMD_SET_REDUCE_MODE (0x04)
+#define DMA_CMD_SET_LLI_CONFIG (0x05)
+#define DMA_CMD_GET_LLI_CONTROL (0x06)
+/**
+ * @}
+ */
+
+union bflb_dma_lli_control_s {
+ struct
+ {
+ uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */
+ uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */
+ uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */
+ uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */
+ uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */
+ uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */
+ uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */
+ uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */
+ uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */
+ uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */
+ uint32_t SI : 1; /* [ 26], r/w, 0x1 */
+ uint32_t DI : 1; /* [ 27], r/w, 0x1 */
+ uint32_t Prot : 3; /* [30:28], r/w, 0x0 */
+ uint32_t I : 1; /* [ 31], r/w, 0x0 */
+ } bits;
+ uint32_t WORD;
+};
+
+/**
+ * @brief DMA channel lli pool structure
+ *
+ * @param src_addr DMA source address
+ * @param dst_addr DMA destination address
+ * @param nextlli DMA next lli address
+ * @param control DMA lli config
+ */
+struct bflb_dma_channel_lli_pool_s {
+ uint32_t src_addr;
+ uint32_t dst_addr;
+ uint32_t nextlli;
+ union bflb_dma_lli_control_s control;
+};
+
+/**
+ * @brief DMA channel lli transfer structure
+ *
+ * @param src_addr DMA source address
+ * @param dst_addr DMA destination address
+ * @param nbytes How many bytes should be transferred
+ */
+struct bflb_dma_channel_lli_transfer_s {
+ uint32_t src_addr;
+ uint32_t dst_addr;
+ uint32_t nbytes;
+};
+
+/**
+ * @brief DMA configuration structure
+ *
+ * @param direction DMA transfer direction, use @ref DMA_DIRECTION
+ * @param src_req DMA source request, use @ref DMA_PERIPHERAL_REQUEST
+ * @param dst_req DMA destination request, use @ref DMA_PERIPHERAL_REQUEST
+ * @param src_addr_inc DMA source address increment, use @ref DMA_ADDR_INCREMENT
+ * @param dst_addr_inc DMA destination address increment, use @ref DMA_ADDR_INCREMENT
+ * @param src_burst_count DMA source burst count, use @ref DMA_BURST_COUNT
+ * @param dst_burst_count DMA destination burst count, use @ref DMA_BURST_COUNT
+ * @param src_width DMA source data width, use @ref DMA_DATA_WIDTH
+ * @param dst_width DMA destination data width, use @ref DMA_DATA_WIDTH
+ */
+struct bflb_dma_channel_config_s {
+ uint8_t direction;
+ uint32_t src_req;
+ uint32_t dst_req;
+ uint8_t src_addr_inc;
+ uint8_t dst_addr_inc;
+ uint8_t src_burst_count;
+ uint8_t dst_burst_count;
+ uint8_t src_width;
+ uint8_t dst_width;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize dma channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save dma channel configuration
+ */
+void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_channel_config_s *config);
+
+/**
+ * @brief Deinitialize dma channel.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Start dma channel transfer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop dma channel transfer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Check if dma channel is in busy.
+ *
+ * @param [in] dev device handle
+ * @return true means dma channel does not transfer completely, otherwise transfers completely.
+ */
+bool bflb_dma_channel_isbusy(struct bflb_device_s *dev);
+
+/**
+ * @brief Register dma channel transmission completion interrupt callback.
+ *
+ * @param [in] dev device handle
+ * @param [in] callback interrupt callback
+ * @param [in] arg user data
+ */
+void bflb_dma_channel_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg), void *arg);
+
+/**
+ * @brief Unregister dma channel transmission completion interrupt callback.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_irq_detach(struct bflb_device_s *dev);
+
+/**
+ * @brief Config dma channel lli.
+ *
+ * @param [in] dev device handle
+ * @param [in] lli_pool pointer to lli pool
+ * @param [in] max_lli_count lli pool size
+ * @param [in] transfer pointer to transfer structure
+ * @param [in] count transfer count.
+ * @return A negated errno value on failure, otherwise means number of used lli.
+ */
+int bflb_dma_channel_lli_reload(struct bflb_device_s *dev,
+ struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count,
+ struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count);
+
+/**
+ * @brief Enable lli continueous mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] lli_pool pointer to lli pool
+ * @param [in] used_lli_count number of used lli.
+ */
+void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
+ struct bflb_dma_channel_lli_pool_s *lli_pool,
+ uint32_t used_lli_count);
+
+/**
+ * @brief Control dma feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command. use @ref DMA_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+/**
+ * @brief Enable or disable dma channel transmission completion interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Check if dma channel transfers completely.
+ *
+ * @param [in] dev device handle
+ * @return true means yes, false means no.
+ */
+bool bflb_dma_channel_get_tcint_status(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear dma channel transmission completion interrupt status.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_ef_ctrl.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_ef_ctrl.h
new file mode 100644
index 00000000..f945b849
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_ef_ctrl.h
@@ -0,0 +1,139 @@
+#ifndef _BFLB_EF_CTRL_H
+#define _BFLB_EF_CTRL_H
+
+#include "bflb_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup EF_CTRL
+ * @{
+ */
+
+/**
+ * @brief Efuse common trim config definition
+ */
+typedef struct
+{
+ char *name; /*!< trim anme */
+ uint16_t en_addr; /*!< enable address */
+ uint16_t parity_addr; /*!< parity address */
+ uint16_t value_addr; /*!< value address */
+ uint16_t value_len; /*!< value length */
+} bflb_ef_ctrl_com_trim_cfg_t;
+
+/**
+ * @brief Efuse common trim type definition
+ */
+typedef struct
+{
+ uint8_t en; /*!< Enable status */
+ uint8_t parity; /*!< Trim parity */
+ uint8_t empty; /*!< Trim empty */
+ uint8_t len; /*!< Trim value len in bit */
+ uint32_t value; /*!< Trim value */
+} bflb_ef_ctrl_com_trim_t;
+
+/**
+ * @brief Get efuse control common trim list.
+ *
+ * @param [in] trim_list pointer to save trim list
+ * @return trim list length
+ */
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @return int
+ */
+int bflb_ef_ctrl_autoload_done(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] offset
+ * @param [in] pword
+ * @param [in] count
+ * @param [in] program
+ */
+void bflb_ef_ctrl_write_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t program);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] offset
+ * @param [in] pword
+ * @param [in] count
+ * @param [in] reload
+ */
+void bflb_ef_ctrl_read_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t reload);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] name
+ * @param [in] trim
+ * @param [in] reload
+ */
+void bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_t *trim, uint8_t reload);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] name
+ * @param [in] value
+ * @param [in] program
+ */
+void bflb_ef_ctrl_write_common_trim(struct bflb_device_s *dev, char *name, uint32_t value, uint8_t program);
+
+/**
+ * @brief
+ *
+ * @param [in] val
+ * @param [in] start
+ * @param [in] len
+ * @return uint8_t
+ */
+uint8_t bflb_ef_ctrl_is_all_bits_zero(uint32_t val, uint8_t start, uint8_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] val
+ * @return uint32_t
+ */
+uint32_t bflb_ef_ctrl_get_byte_zero_cnt(uint8_t val);
+
+/**
+ * @brief
+ *
+ * @param [in] val
+ * @param [in] len
+ * @return uint8_t
+ */
+uint8_t bflb_ef_ctrl_get_trim_parity(uint32_t val, uint8_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_efuse.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_efuse.h
new file mode 100644
index 00000000..845cdccc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_efuse.h
@@ -0,0 +1,30 @@
+#ifndef _BFLB_EFUSE_H
+#define _BFLB_EFUSE_H
+
+#include "bflb_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void bflb_efuse_get_chipid(uint8_t chipid[8]);
+
+uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload);
+int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program);
+int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+
+float bflb_efuse_get_adc_trim(void);
+uint32_t bflb_efuse_get_adc_tsen_trim(void);
+
+void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes);
+void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len);
+void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len);
+
+void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program);
+void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_emac.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_emac.h
new file mode 100644
index 00000000..7e28fd6a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_emac.h
@@ -0,0 +1,343 @@
+#ifndef _BFLB_EMAC_H
+#define _BFLB_EMAC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup EMAC
+ * @{
+ */
+
+#define EMAC_DO_FLUSH_DATA (1)
+
+/* EMAC clock use external or use internal; 0: used external 1: used internal */
+#define EMAC_CLK_USE_EXTERNAL (0)
+#define EMAC_CLK_USE_INTERNAL (1)
+
+/** @defgroup EMAC_CMD emac feature control cmd definition
+ * @{
+ */
+#define EMAC_CMD_NO_PREAMBLE_MODE (0x01)
+#define EMAC_CMD_EN_PROMISCUOUS (0x02)
+#define EMAC_CMD_FRAME_GAP_CHECK (0x03)
+#define EMAC_CMD_FULL_DUPLEX (0x04)
+#define EMAC_CMD_EN_TX_CRC_FIELD (0x05)
+#define EMAC_CMD_RECV_HUGE_FRAMES (0x06)
+#define EMAC_CMD_EN_AUTO_PADDING (0x07)
+#define EMAC_CMD_RECV_SMALL_FRAME (0x08)
+#define EMAC_CMD_SET_PHY_ADDRESS (0x09)
+#define EMAC_CMD_SET_MAC_ADDRESS (0x0A)
+#define EMAC_CMD_SET_PACKET_GAP (0x0B)
+#define EMAC_CMD_SET_MIN_FRAME (0x0C)
+#define EMAC_CMD_SET_MAX_FRAME (0x0D)
+#define EMAC_CMD_SET_MAXRET (0x0E)
+#define EMAC_CMD_SET_COLLVALID (0x0F)
+/**
+ * @}
+ */
+
+/** @defgroup PHY_STATE phy state definition
+ * @{
+ */
+#define PHY_STATE_DOWN (0) /* PHY is not usable */
+#define PHY_STATE_READY (1) /* PHY is OK, wait for controller */
+#define PHY_STATE_UP (2) /* Network is ready for TX/RX */
+#define PHY_STATE_RUNNING (3) /* working */
+#define PHY_STATE_NOLINK (4) /* no cable connected */
+#define PHY_STATE_STOPPED (5) /* PHY has been stopped */
+#define PHY_STATE_TESTING (6) /* in test mode */
+/**
+ * @}
+ */
+
+/* EMAC PACKET */
+#define EMAC_NORMAL_PACKET (uint32_t)(0)
+#define EMAC_FRAGMENT_PACKET (uint32_t)(0x01)
+#define EMAC_NOCOPY_PACKET (uint32_t)(0x02)
+
+/* ETH packet size */
+/* ETH | Header | Extra | VLAN tag | Payload | CRC | */
+/* Size | 14 | 2 | 4 | 46 ~ 1500 | 4 | */
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER_SZIE ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC_SIZE ((uint32_t)4U) /*!< Ethernet CRC */
+#define ETH_EXTRA_SIZE ((uint32_t)2U) /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG_SIZE ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD_SIZE ((uint32_t)46U) /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD_SIZE ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) /*!< Jumbo frame payload size */
+
+/* ETH tx & rx buffer size */
+#ifndef ETH_TX_BUFFER_SIZE
+#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
+#endif
+#ifndef ETH_RX_BUFFER_SIZE
+#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
+#endif
+
+/* emac interrupt UNMASK/MASK define */
+#define EMAC_INT_EN_TX_DONE (1 << 0)
+#define EMAC_INT_EN_TX_ERROR (1 << 1)
+#define EMAC_INT_EN_RX_DONE (1 << 2)
+#define EMAC_INT_EN_RX_ERROR (1 << 3)
+#define EMAC_INT_EN_RX_BUSY (1 << 4)
+#define EMAC_INT_EN_TX_CTRL (1 << 5)
+#define EMAC_INT_EN_RX_CTRL (1 << 6)
+#define EMAC_INT_EN_ALL (0x7f << 0)
+
+/* emac interrupt status define */
+#define EMAC_INT_STS_TX_DONE (1 << 0)
+#define EMAC_INT_STS_TX_ERROR (1 << 1)
+#define EMAC_INT_STS_RX_DONE (1 << 2)
+#define EMAC_INT_STS_RX_ERROR (1 << 3)
+#define EMAC_INT_STS_RX_BUSY (1 << 4)
+#define EMAC_INT_STS_TX_CTRL (1 << 5)
+#define EMAC_INT_STS_RX_CTRL (1 << 6)
+#define EMAC_INT_STS_ALL (0x7f << 0)
+
+/* emac buffer descriptors type define */
+#define EMAC_BD_TYPE_INVLAID (0)
+#define EMAC_BD_TYPE_TX (1)
+#define EMAC_BD_TYPE_RX (2)
+#define EMAC_BD_TYPE_NONE (3)
+#define EMAC_BD_TYPE_MAX (0x7FFFFFFF)
+
+/**
+ * @brief EMAC configuration structure
+ *
+ * @param mac_addr EMAC mac addr
+ * @param inside_clk EMAC select inside or external @ref EMAC_CLK_USE_EXTERNAL or EMAC_CLK_USE_INTERNAL
+ * @param mii_clk_div mii clock div
+ * @param min_frame_len min frame len
+ * @param max_frame_len max frame len
+ *
+ */
+struct bflb_emac_config_s {
+ uint8_t mac_addr[6];
+ uint8_t inside_clk;
+ uint8_t mii_clk_div;
+ uint16_t min_frame_len;
+ uint16_t max_frame_len;
+};
+
+/**
+ * @brief EMAC phy configuration structure
+ *
+ * @param auto_negotiation EMAC phy speed and mode auto negotiation
+ * @param full_duplex EMAC phy duplex mode
+ * @param phy_state EMAC phy down,ready,up,running,nolink,halted, @ref PHY_STATE
+ * @param use_irq EMAC phy interrupt enable 0: no IRQ used
+ * @param speed EMAC phy speed mode
+ * @param phy_address EMAC phy address
+ * @param phy_id EMAC phy read phy id
+ */
+struct bflb_emac_phy_cfg_s {
+ uint8_t auto_negotiation;
+ uint8_t full_duplex;
+ uint8_t phy_state;
+ uint8_t use_irq;
+ uint16_t speed;
+ uint16_t phy_address;
+ uint32_t phy_id;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] config
+ */
+void bflb_emac_init(struct bflb_device_s *dev, const struct bflb_emac_config_s *config);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_start(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_start_tx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_stop_tx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_start_rx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_stop_rx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] eth_tx_buff
+ * @param [in] tx_buf_count
+ * @param [in] eth_rx_buff
+ * @param [in] rx_buf_count
+ */
+void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] bdt
+ * @return uint32_t
+ */
+uint32_t bflb_emac_bd_get_cur_active(struct bflb_device_s *dev, uint8_t bdt);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_rx_enqueue(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_rx_on_err(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_tx_dequeue(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_tx_on_err(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] flags
+ * @param [in] len
+ * @param [in] data_in
+ * @return int
+ */
+int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in);
+
+/**
+ * @brief
+ *
+ * @param [in] flags
+ * @param [in] len
+ * @param [in] data_out
+ * @return int
+ */
+int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out);
+
+/**
+ * @brief
+ *
+ * @return int
+ */
+int emac_bd_fragment_support(void);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] flag
+ * @param [in] enable
+ */
+void bflb_emac_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] flag
+ */
+void bflb_emac_int_clear(struct bflb_device_s *dev, uint32_t flag);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint32_t
+ */
+uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] cmd
+ * @param [in] arg
+ * @return int
+ */
+int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] phy_reg
+ * @param [in] phy_reg_val
+ * @return int
+ */
+int bflb_emac_phy_reg_read(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t *phy_reg_val);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] phy_reg
+ * @param [in] phy_reg_val
+ * @return int
+ */
+int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t phy_reg_val);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_flash.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_flash.h
new file mode 100644
index 00000000..8ad92374
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_flash.h
@@ -0,0 +1,177 @@
+#ifndef _BFLB_FLASH_H
+#define _BFLB_FLASH_H
+
+#include "bflb_core.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @defgroup FLASH_IOMODE flash iomode definition
+ * @{
+ */
+#define FLASH_IOMODE_NIO 0 /*!< Normal IO mode define */
+#define FLASH_IOMODE_DO 1 /*!< Dual Output mode define */
+#define FLASH_IOMODE_QO 2 /*!< Quad Output mode define */
+#define FLASH_IOMODE_DIO 3 /*!< Dual IO mode define */
+#define FLASH_IOMODE_QIO 4 /*!< Quad IO mode define */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_AES_KEY_TYPE flash aes key type definition
+ * @{
+ */
+#define FLASH_AES_KEY_128BITS 0
+#define FLASH_AES_KEY_192BITS 2
+#define FLASH_AES_KEY_256BITS 1
+#define FLASH_AES_KEY_DOUBLE_128BITS 3
+/**
+ * @}
+ */
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define FLASH_XIP_BASE (0x23000000)
+#elif defined(BL616) || defined(BL628)
+#define FLASH_XIP_BASE (0xA0000000)
+#elif defined(BL808) || defined(BL606P)
+#define FLASH_XIP_BASE (0x58000000)
+#endif
+
+struct bflb_flash_aes_config_s {
+ uint8_t region;
+ uint8_t region_enable;
+ uint8_t lock_enable;
+ const uint8_t *key;
+ uint8_t keybits;
+ uint8_t *iv;
+ uint32_t start_addr;
+ uint32_t end_addr;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize flash.
+ *
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_init(void);
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+/**
+ * @brief flash_set_cmds
+ *
+ * @return None
+ */
+void bflb_flash_set_cmds(spi_flash_cfg_type *p_flash_cfg);
+#endif
+
+/**
+ * @brief Get flash jedec id.
+ *
+ * @return uint32_t
+ */
+uint32_t bflb_flash_get_jedec_id(void);
+
+/**
+ * @brief Get flash config.
+ *
+ * @param [out] cfg_addr pointer to save config
+ * @param [in] len flash config size
+ */
+void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
+
+/**
+ * @brief Set flash iomode.
+ *
+ * @param [in] iomode flash iomode, use @ref FLASH_IOMODE
+ */
+void bflb_flash_set_iomode(uint8_t iomode);
+
+/**
+ * @brief Get flash image offset.
+ *
+ * @return flash image offset
+ */
+uint32_t bflb_flash_get_image_offset(void);
+
+/**
+ * @brief Erase flash with sectors.
+ *
+ * @param [in] addr
+ * @param [in] len
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_erase(uint32_t addr, uint32_t len);
+
+/**
+ * @brief Write data into flash.
+ *
+ * @param [in] addr flash physical address
+ * @param [in] data pointer to data buffer
+ * @param [in] len length of data
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Read data from flash.
+ *
+ * @param [in] addr flash physical address
+ * @param [out] data pointer to data buffer
+ * @param [in] len length of data
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Config flash cache.
+ *
+ * @param [in] cont_read enable or not continuous read mode.
+ * @param [in] cache_enable enable cache or not
+ * @param [in] cache_way_disable ways of cache to disable
+ * @param [in] flash_offset flash image offset
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
+
+/**
+ * @brief Initialize flash aes controller.
+ *
+ * @param [in] config pointer to flash aes config.
+ */
+void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config);
+
+/**
+ * @brief Enable flash decrypt with aes.
+ *
+ */
+void bflb_flash_aes_enable(void);
+
+/**
+ * @brief Disable flash decrypt with aes.
+ *
+ */
+void bflb_flash_aes_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_gpio.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_gpio.h
new file mode 100644
index 00000000..e4f410d8
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_gpio.h
@@ -0,0 +1,409 @@
+#ifndef _BFLB_GPIO_H
+#define _BFLB_GPIO_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/**
+ * @brief Gpio pin definitions
+ *
+ * BL602 : GPIO0/1/2/7/8/14/15/20/21/22
+ * BL604 : GPIO0 ~ GPIO5, GPIO7/8/11/12/14/16/17/20/21/22
+ * BL606 : GPIO0 ~ GPIO22
+ * BL702 : GPIO0/1/2/7/8/9/14/15/17/23/24/25/26/27/28
+ * BL704 : GPIO0 ~ GPIO3, GPIO7 ~ GPIO11, GPIO14/15, GPIO17 ~ GPIO28,
+ * BL706 : GPIO0 ~ GPIO31
+ * BL606P : GPIO0 ~ GPIO5, GPIO11 ~ GPIO12, GPIO16 ~ GPIO21, GPIO24 ~ GPIO28, GPIO34 ~ GPIO41
+ * BL616 : GPIO0 ~ GPIO3, GPIO10 ~ GPIO17, GPIO20 ~ GPIO22, GPIO27 ~ GPIO30
+ * BL618 : GPIO0 ~ GPIO34
+ * BL808C : GPIO0 ~ GPIO23, GPIO34 ~ GPIO45
+ * BL808D : GPIO0 ~ GPIO8, GPIO11 ~ GPIO41
+ *
+ */
+
+/** @defgroup GPIO_PIN gpio pin definition
+ * @{
+ */
+#define GPIO_PIN_0 0
+#define GPIO_PIN_1 1
+#define GPIO_PIN_2 2
+#define GPIO_PIN_3 3
+#define GPIO_PIN_4 4
+#define GPIO_PIN_5 5
+#define GPIO_PIN_6 6
+#define GPIO_PIN_7 7
+#define GPIO_PIN_8 8
+#define GPIO_PIN_9 9
+#define GPIO_PIN_10 10
+#define GPIO_PIN_11 11
+#define GPIO_PIN_12 12
+#define GPIO_PIN_13 13
+#define GPIO_PIN_14 14
+#define GPIO_PIN_15 15
+#define GPIO_PIN_16 16
+#define GPIO_PIN_17 17
+#define GPIO_PIN_18 18
+#define GPIO_PIN_19 19
+#define GPIO_PIN_20 20
+#define GPIO_PIN_21 21
+#define GPIO_PIN_22 22
+#define GPIO_PIN_23 23
+#define GPIO_PIN_24 24
+#define GPIO_PIN_25 25
+#define GPIO_PIN_26 26
+#define GPIO_PIN_27 27
+#define GPIO_PIN_28 28
+#define GPIO_PIN_29 29
+#define GPIO_PIN_30 30
+#define GPIO_PIN_31 31
+#define GPIO_PIN_32 32
+#define GPIO_PIN_33 33
+#define GPIO_PIN_34 34
+#define GPIO_PIN_35 35
+#define GPIO_PIN_36 36
+#define GPIO_PIN_37 37
+#define GPIO_PIN_38 38
+#define GPIO_PIN_39 39
+#define GPIO_PIN_40 40
+#define GPIO_PIN_41 41
+#define GPIO_PIN_42 42
+#define GPIO_PIN_43 43
+#define GPIO_PIN_44 44
+#define GPIO_PIN_45 45
+/**
+ * @}
+ */
+
+/* cfgset list */
+#define GPIO_FUNC_SHIFT (0) /* Bits 0-4: GPIO function */
+#define GPIO_FUNC_MASK (0x1f << GPIO_FUNC_SHIFT)
+#if defined(BL602)
+#define GPIO_FUNC_SDIO (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
+#elif defined(BL702)
+#define GPIO_FUNC_CLK_OUT (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC (19 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM_MCLK (23 << GPIO_FUNC_SHIFT)
+#elif defined(BL702L)
+#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_KEYSCAN (13 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
+#elif defined(BL616)
+#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_QSPI (24 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_AUDAC_PWM (25 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
+#elif defined(BL606P) || defined(BL808)
+#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM1 (17 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI1 (18 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C2 (19 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C3 (20 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C3 (20 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG_LP (25 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG_M0 (26 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG_D0 (27 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
+#elif defined(BL628)
+#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_UART (7 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
+#endif
+
+#define GPIO_MODE_SHIFT (5) /* Bits 5-6: Port Mode */
+#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
+#define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input Enable */
+#define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output Enable */
+#define GPIO_ANALOG (2 << GPIO_MODE_SHIFT) /* Analog Enable */
+#define GPIO_ALTERNATE (3 << GPIO_MODE_SHIFT) /* Alternate Enable */
+
+#define GPIO_PUPD_SHIFT (7) /* Bits 7-8: Pull-up/down */
+#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
+#define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
+#define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
+#define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */
+
+#define GPIO_SMT_SHIFT (9) /* Bits 9: SMT Enable */
+#define GPIO_SMT_MASK (1 << GPIO_SMT_SHIFT)
+#define GPIO_SMT_DIS (0 << GPIO_SMT_SHIFT)
+#define GPIO_SMT_EN (1 << GPIO_SMT_SHIFT)
+
+#define GPIO_DRV_SHIFT (10) /* Bits 10-11: Drive */
+#define GPIO_DRV_MASK (3 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_0 (0 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_1 (1 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_2 (2 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_3 (3 << GPIO_DRV_SHIFT)
+
+/** @defgroup GPIO_INT_TRIG_MODE gpio interrupt trigger mode definition
+ * @{
+ */
+#define GPIO_INT_TRIG_MODE_SYNC_FALLING_EDGE 0
+#define GPIO_INT_TRIG_MODE_SYNC_RISING_EDGE 1
+#define GPIO_INT_TRIG_MODE_SYNC_LOW_LEVEL 2
+#define GPIO_INT_TRIG_MODE_SYNC_HIGH_LEVEL 3
+#if defined(BL602) || defined(BL702)
+#define GPIO_INT_TRIG_MODE_ASYNC_FALLING_EDGE 4
+#define GPIO_INT_TRIG_MODE_ASYNC_RISING_EDGE 5
+#define GPIO_INT_TRIG_MODE_ASYNC_LOW_LEVEL 6
+#define GPIO_INT_TRIG_MODE_ASYNC_HIGH_LEVEL 7
+#else
+#define GPIO_INT_TRIG_MODE_SYNC_FALLING_RISING_EDGE 4
+#define GPIO_INT_TRIG_MODE_ASYNC_FALLING_EDGE 8
+#define GPIO_INT_TRIG_MODE_ASYNC_RISING_EDGE 9
+#define GPIO_INT_TRIG_MODE_ASYNC_LOW_LEVEL 10
+#define GPIO_INT_TRIG_MODE_ASYNC_HIGH_LEVEL 11
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_UART_FUNC gpio uart function definition
+ * @{
+ */
+#define GPIO_UART_FUNC_UART0_RTS 0
+#define GPIO_UART_FUNC_UART0_CTS 1
+#define GPIO_UART_FUNC_UART0_TX 2
+#define GPIO_UART_FUNC_UART0_RX 3
+#define GPIO_UART_FUNC_UART1_RTS 4
+#define GPIO_UART_FUNC_UART1_CTS 5
+#define GPIO_UART_FUNC_UART1_TX 6
+#define GPIO_UART_FUNC_UART1_RX 7
+#if defined(BL808) || defined(BL606P)
+#define GPIO_UART_FUNC_UART2_RTS 8
+#define GPIO_UART_FUNC_UART2_CTS 9
+#define GPIO_UART_FUNC_UART2_TX 10
+#define GPIO_UART_FUNC_UART2_RX 11
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_ISO11898_FUNC gpio iso11898 function definition
+ * @{
+ */
+#if defined(BL808) || defined(BL606P)|| defined(BL616)|| defined(BL628)
+#define GPIO_ISO11898_FUNC_TX 10
+#define GPIO_ISO11898_FUNC_RX 11
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_CMD gpio feature control cmd definition
+ * @{
+ */
+#define GPIO_CMD_GET_GPIO_FUN (0x01)
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize gpio pin.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] cfgset gpio config mask
+ */
+void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset);
+
+/**
+ * @brief Deinitialize gpio pin with input float.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Write gpio pin with high level.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Write gpio pin with low level.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Read level from gpio pin.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @return true means high level, otherwise low level
+ */
+bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Write gpio pin 0~31.
+ *
+ * @param [in] dev device handle
+ * @param [in] val gpio pin 0~31 value
+ */
+void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val);
+
+/**
+ * @brief Write gpio pin 32~63.
+ *
+ * @param [in] dev device handle
+ * @param [in] val gpio pin 32~63 value
+ */
+void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val);
+
+/**
+ * @brief Read level from gpio pin 0~31.
+ *
+ * @param [in] dev device handle
+ * @return level of gpio pin 0~31
+ */
+uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev);
+
+/**
+ * @brief Read level from gpio pin 32~63.
+ *
+ * @param [in] dev device handle
+ * @return level of gpio pin32~63
+ */
+uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev);
+
+/**
+ * @brief Config gpio pin interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] trig_mode mode to trigger interrupt
+ */
+void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode);
+
+/**
+ * @brief Enable or disable gpio pin interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask);
+
+/**
+ * @brief Get gpio pin interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @return true means yes, false means no
+ */
+bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Clear gpio pin interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Config gpio pin with uart function.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] uart_func uart function, use @ref GPIO_UART_FUNC
+ */
+void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func);
+
+/**
+ * @brief Config gpio pin with iso11898 function.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] iso11898_func iso11898 function, use @ref GPIO_ISO11898_FUNC
+ */
+void bflb_gpio_iso11898_init(struct bflb_device_s *dev, uint8_t pin, uint8_t iso11898_func);
+
+/**
+ * @brief Control gpio feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref GPIO_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+
+int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_i2c.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_i2c.h
new file mode 100644
index 00000000..3395e833
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_i2c.h
@@ -0,0 +1,194 @@
+#ifndef _BFLB_I2C_H
+#define _BFLB_I2C_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Bit definitions for the flags field in struct bflb_i2c_msg_s
+ *
+ * START/STOP Rules:
+ *
+ * 1. The lower half I2C driver will always issue the START condition at the
+ * beginning of a message unless I2C_M_NOSTART flag is set in the
+ * message.
+ *
+ * 2. The lower half I2C driver will always issue the STOP condition at the
+ * end of the messages unless:
+ *
+ * a. The I2C_M_NOSTOP flag is set in the message, OR
+ * b. The following message has the I2C_M_NOSTART flag set (meaning
+ * that following message is simply a continuation of the transfer).
+ *
+ * A proper I2C repeated start would then have I2C_M_NOSTOP set on msg[n]
+ * and I2C_M_NOSTART *not* set on msg[n+1]. See the following table:
+ *
+ * msg[n].flags msg[n+1].flags Behavior
+ * ------------ --------------- -----------------------------------------
+ * 0 0 Two normal, separate messages with STOP
+ * on msg[n] then START on msg[n+1]
+ * 0* I2C_M_NOSTART Continuation of the same transfer (must
+ * be the same direction). See NOTE below.
+ * NO_STOP 0 No STOP on msg[n]; repeated START on
+ * msg[n+1].
+ *
+ * * NOTE: NO_STOP is implied in this case and may or not be explicitly
+ * included in the msg[n] flags
+ */
+
+#define I2C_M_READ 0x0001 /* Read data, from slave to master */
+#define I2C_M_TEN 0x0002 /* Ten bit address */
+#define I2C_M_DMA 0x0004 /* Enable dma mode */
+#define I2C_M_NOSTOP 0x0040 /* Message should not end with a STOP */
+#define I2C_M_NOSTART 0x0080 /* Message should not begin with a START */
+
+/** @defgroup I2C_INTSTS i2c interrupt status definition
+ * @{
+ */
+#define I2C_INTSTS_END (1 << 0) /* Transfer end interrupt */
+#define I2C_INTSTS_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */
+#define I2C_INTSTS_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */
+#define I2C_INTSTS_NACK (1 << 3) /* NACK interrupt */
+#define I2C_INTSTS_ARB (1 << 4) /* Arbitration lost interrupt */
+#define I2C_INTSTS_FER (1 << 5) /* TX/RX FIFO error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_INTCLR i2c interrupt clear definition
+ * @{
+ */
+#define I2C_INTCLR_END (1 << 0) /* Transfer end interrupt */
+#define I2C_INTCLR_NACK (1 << 3) /* NACK interrupt */
+#define I2C_INTCLR_ARB (1 << 4) /* Arbitration lost interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_INTEN i2c interrupt enable definition
+ * @{
+ */
+#define I2C_INTEN_END (1 << 0) /* Transfer end interrupt */
+#define I2C_INTEN_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */
+#define I2C_INTEN_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */
+#define I2C_INTEN_NACK (1 << 3) /* NACK interrupt */
+#define I2C_INTEN_ARB (1 << 4) /* Arbitration lost interrupt */
+#define I2C_INTEN_FER (1 << 5) /* TX/RX FIFO error interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @brief I2C message structure
+ *
+ * @param addr Slave address (7- or 10-bit)
+ * @param flags See I2C_M_* definitions
+ * @param buffer Buffer to be transferred
+ * @param length Length of the buffer in bytes, should be less than 256.
+ */
+struct bflb_i2c_msg_s {
+ uint16_t addr;
+ uint16_t flags;
+ uint8_t *buffer;
+ uint16_t length;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize i2c.
+ *
+ * @param [in] dev device handle
+ * @param [in] frequency i2c frequency, range from 305Hz to 400KHz
+ */
+void bflb_i2c_init(struct bflb_device_s *dev, uint32_t frequency);
+
+/**
+ * @brief Deinitialize i2c.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_i2c_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable i2c tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2c_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable i2c rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2c_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Start transferring i2c message.
+ *
+ * @param [in] dev device handle
+ * @param [in] msgs pointer to i2c message
+ * @param [in] count message count
+ * @return A negated errno value on failure.
+ */
+int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, int count);
+
+/**
+ * @brief Enable or disable i2c interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type interrupt type ,use @ref I2C_INTEN
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2c_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
+
+/**
+ * @brief Clear i2c interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref I2C_INTCLR
+ */
+void bflb_i2c_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Get i2c interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status value, use @ref I2C_INTSTS
+ */
+uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control i2c feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_i2s.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_i2s.h
new file mode 100644
index 00000000..e006116d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_i2s.h
@@ -0,0 +1,207 @@
+#ifndef _BFLB_I2S_H
+#define _BFLB_I2S_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/** @defgroup I2S_ROLE i2s role definition
+ * @{
+ */
+#define I2S_ROLE_MASTER 0
+#define I2S_ROLE_SLAVE 1
+/**
+ * @}
+ */
+
+/** @defgroup I2S_FORMAT_MODE i2s mode definition
+ * @{
+ */
+#define I2S_MODE_LEFT_JUSTIFIED 0 /* left-justified or Phillips standard */
+#define I2S_MODE_RIGHT_JUSTIFIED 1 /* right-justified */
+#define I2S_MODE_DSP_SHORT_FRAME_SYNC 2 /* dsp modeA/B short frame sync */
+#define I2S_MODE_DSP_LONG_FRAME_SYNC 3 /* dsp modeA/B long frame sync */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_CHANNEL_MODE i2s mode definition
+ * @{
+ */
+#define I2S_CHANNEL_MODE_NUM_1 0
+#define I2S_CHANNEL_MODE_NUM_2 1
+#define I2S_CHANNEL_MODE_NUM_3 2 /* only DSP mode, frame_size must equal data_size */
+#define I2S_CHANNEL_MODE_NUM_4 3 /* only DSP mode, frame_size must equal data_size */
+#define I2S_CHANNEL_MODE_NUM_6 4 /* only DSP mode, frame_size must equal data_size */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_SLOT_WIDTH i2s slot width definition
+ * @{
+ */
+#define I2S_SLOT_WIDTH_8 0
+#define I2S_SLOT_WIDTH_16 1
+#define I2S_SLOT_WIDTH_24 2
+#define I2S_SLOT_WIDTH_32 3
+/**
+ * @}
+ */
+
+/** @defgroup I2S_INTSTS i2s interrupt status definition
+ * @{
+ */
+#define I2S_INTSTS_TX_FIFO (1 << 1)
+#define I2S_INTSTS_RX_FIFO (1 << 2)
+#define I2S_INTSTS_FIFO_ERR (1 << 3)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_CMD i2s feature control cmd definition
+ * @{
+ */
+#define I2S_CMD_CLEAR_TX_FIFO (0x01)
+#define I2S_CMD_CLEAR_RX_FIFO (0x02)
+#define I2S_CMD_RX_DEGLITCH (0x03)
+#define I2S_CMD_DATA_ENABLE (0x04)
+#define I2S_CMD_CHANNEL_LR_MERGE (0x05)
+#define I2S_CMD_CHANNEL_LR_EXCHG (0x06)
+#define I2S_CMD_MUTE (0x07)
+#define I2S_CMD_BIT_REVERSE (0x08)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_CMD_DATA_ENABLE_TYPE i2s data enable type
+ * @{
+ */
+#define I2S_CMD_DATA_ENABLE_TX (1 << 1)
+#define I2S_CMD_DATA_ENABLE_RX (1 << 2)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief I2S configuration structure
+ *
+ * @param bclk_freq_hz I2S bit frequence, Sampling_rate = bclk_freq_hz / frame_width / channel_num.
+ * @param role I2S role, use @ref I2S_ROLE
+ * @param format_mode I2S mode, use @ref I2S_FORMAT_MODE
+ * @param channel_mode I2S channel num, Only DSP mode supports more than 2 channels, use @ref I2S_CHANNEL_MODE
+ * @param frame_width I2S frame width, use @ref I2S_SLOT_WIDTH
+ * @param data_width I2S data order, frame_size must equal data_size in 3/4/6-channel mode, use @ref I2S_SLOT_WIDTH
+ * @param fs_offset_cycle I2S first bit offset of the data
+ * @param tx_fifo_threshold I2S tx fifo threshold, should be less than 16
+ * @param rx_fifo_threshold I2S rx fifo threshold, should be less than 16
+ */
+struct bflb_i2s_config_s {
+ uint32_t bclk_freq_hz;
+ uint8_t role;
+ uint8_t format_mode;
+ uint8_t channel_mode;
+ uint8_t frame_width;
+ uint8_t data_width;
+ uint8_t fs_offset_cycle;
+
+ uint8_t tx_fifo_threshold;
+ uint8_t rx_fifo_threshold;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize i2s.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save i2s config
+ */
+void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config);
+
+/**
+ * @brief Deinitialize i2s.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_i2s_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable i2s tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable i2s rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable or disable i2s rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable i2s rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable i2s error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get i2s interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref I2S_INTSTS
+ */
+uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control i2s feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref I2S_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_ir.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_ir.h
new file mode 100644
index 00000000..821f5766
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_ir.h
@@ -0,0 +1,375 @@
+#ifndef _BFLB_IR_H
+#define _BFLB_IR_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup IR
+ * @{
+ */
+
+#if !defined(BL616)
+/** @defgroup IR_TX_MODE ir tx mode definition
+ * @{
+ */
+#define IR_TX_NEC 0
+#define IR_TX_RC5 1
+#define IR_TX_SWM 2
+#define IR_TX_CUSTOMIZE 3
+/**
+ * @}
+ */
+
+/** @defgroup IR_TX_FIFO_WIDTH ir tx fifo width valid width definition
+ * @{
+ */
+#if !defined(BL602) && !defined(BL702)
+#define IR_TX_FIFO_WIDTH_8BIT 0
+#define IR_TX_FIFO_WIDTH_16BIT 1
+#define IR_TX_FIFO_WIDTH_24BIT 2
+#endif
+#define IR_TX_FIFO_WIDTH_32BIT 3
+/**
+ * @}
+ */
+
+/** @defgroup IR_TX_INTEN ir tx interrupt enable definition
+ * @{
+ */
+#define IR_TX_INTEN_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_TX_INTEN_FIFO (1 << 1)
+#define IR_TX_INTEN_FER (1 << 2)
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup IR_TX_INTSTS ir tx interrupt status definition
+ * @{
+ */
+#define IR_TX_INTSTS_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_TX_INTSTS_FIFO (1 << 1)
+#define IR_TX_INTSTS_FER (1 << 2)
+#endif
+/**
+ * @}
+ */
+
+#endif
+
+#if !defined(BL702L)
+/** @defgroup IR_RX_MODE ir rx mode definition
+ * @{
+ */
+#define IR_RX_NEC 0
+#define IR_RX_RC5 1
+#define IR_RX_SWM 2
+/**
+ * @}
+ */
+
+/** @defgroup IR_RX_INTEN ir rx interrupt enable definition
+ * @{
+ */
+#define IR_RX_INTEN_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_RX_INTEN_FIFO (1 << 1)
+#define IR_RX_INTEN_FER (1 << 2)
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup IR_RX_INTSTS ir rx interrupt status definition
+ * @{
+ */
+#define IR_RX_INTSTS_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_RX_INTSTS_FIFO (1 << 1)
+#define IR_RX_INTSTS_FER (1 << 2)
+#endif
+/**
+ * @}
+ */
+#endif
+
+#if !defined(BL616)
+/**
+ * @brief IR TX configuration structure
+ *
+ * @param tx_mode TX mode select, use @ref IR_TX_MODE
+ * @param data_bits Bit count of data phase (don't care if tx freerun mode is enabled)
+ * @param tail_inverse Enable or disable signal of tail pulse inverse (don't care if SWM is enabled)
+ * @param tail_enable Enable or disable signal of tail pulse (don't care if SWM is enabled)
+ * @param head_inverse Enable or disable signal of head pulse inverse (don't care if SWM is enabled)
+ * @param head_enable Enable or disable signal of head pulse (don't care if SWM is enabled)
+ * @param logic1_inverse Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled)
+ * @param logic0_inverse Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled)
+ * @param data_enable Enable or disable signal of data pulse (don't care if SWM is enabled)
+ * @param swm_enable Enable or disable software mode(SWM)
+ * @param output_modulation Enable or disable signal of output modulation
+ * @param output_inverse Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high
+ * @param freerun_enable Enable or disable tx freerun mode (don't care if SWM is enabled)
+ * @param continue_enable Disable:idle time between frames = (tailPulseWidth_0+tailPulseWidth_1)*pulseWidthUnit,Enable:no idle time between frames
+ * @param fifo_width IR frame size(also the valid width for each fifo entry), use @ref IR_TX_FIFO_WIDTH
+ * @param fifo_threshold TX FIFO threshold
+ * @param logic0_pulse_width_1 Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled)
+ * @param logic0_pulse_width_0 Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled)
+ * @param logic1_pulse_width_1 Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled)
+ * @param logic1_pulse_width_0 Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled)
+ * @param head_pulse_width_1 Pulse width of head pulse phase 1 (don't care if SWM is enabled)
+ * @param head_pulse_width_0 Pulse width of head pulse phase 0 (don't care if SWM is enabled)
+ * @param tail_pulse_width_1 Pulse width of tail pulse phase 1 (don't care if SWM is enabled)
+ * @param tail_pulse_width_0 Pulse width of tail pulse phase 0 (don't care if SWM is enabled)
+ * @param modu_width_1 Modulation phase 1 width
+ * @param modu_width_0 Modulation phase 0 width
+ * @param pulse_width_unit Pulse width unit
+ */
+struct bflb_ir_tx_config_s {
+ uint8_t tx_mode;
+ uint8_t data_bits;
+ uint8_t tail_inverse;
+ uint8_t tail_enable;
+ uint8_t head_inverse;
+ uint8_t head_enable;
+ uint8_t logic1_inverse;
+ uint8_t logic0_inverse;
+ uint8_t data_enable;
+ uint8_t swm_enable;
+ uint8_t output_modulation;
+ uint8_t output_inverse;
+ uint8_t freerun_enable;
+ uint8_t continue_enable;
+ uint8_t fifo_width;
+ uint8_t fifo_threshold;
+ uint8_t logic0_pulse_width_1;
+ uint8_t logic0_pulse_width_0;
+ uint8_t logic1_pulse_width_1;
+ uint8_t logic1_pulse_width_0;
+ uint8_t head_pulse_width_1;
+ uint8_t head_pulse_width_0;
+ uint8_t tail_pulse_width_1;
+ uint8_t tail_pulse_width_0;
+ uint8_t modu_width_1;
+ uint8_t modu_width_0;
+ uint16_t pulse_width_unit;
+};
+#endif
+
+#if !defined(BL702L)
+/**
+ * @brief IR RX configuration structure
+ *
+ * @param rx_mode RX mode select, use @ref IR_RX_MODE
+ * @param input_inverse Enable or disable signal of input inverse
+ * @param deglitch_enable Enable or disable signal of rx input de-glitch function
+ * @param deglitch_cnt De-glitch function cycle count
+ * @param data_threshold Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled)
+ * @param end_threshold Pulse width threshold to trigger end condition
+ * @param fifo_threshold RX FIFO threshold
+ */
+struct bflb_ir_rx_config_s {
+ uint8_t rx_mode;
+ uint8_t input_inverse;
+ uint8_t deglitch_enable;
+ uint8_t deglitch_cnt;
+ uint16_t data_threshold;
+ uint16_t end_threshold;
+ uint16_t fifo_threshold;
+};
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(BL616)
+/**
+ * @brief Initialize ir tx.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to ir tx configure structure
+ */
+void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config);
+
+/**
+ * @brief Send data in NEC/RC5/customize mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] data data buffer to send
+ * @param [in] length length of data buffer
+ */
+void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length);
+
+/**
+ * @brief Send data in software mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] data data data buffer to send
+ * @param [in] length length of data buffer
+ */
+void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
+
+/**
+ * @brief Enable or disable ir tx.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Mask or unmask ir tx interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type ir tx interrupt type, use @ref IR_TX_INTEN
+ * @param [in] mask mask or unmask
+ */
+void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
+
+/**
+ * @brief Get ir tx interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Ir tx interrupt status
+ */
+uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir tx interrupt.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_txint_clear(struct bflb_device_s *dev);
+
+#if !defined(BL602) && !defined(BL702)
+/**
+ * @brief Enable or disable ir tx dma mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Get ir tx fifo available count.
+ *
+ * @param [in] dev device handle
+ * @return Ir tx fifo available count
+ */
+uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir tx fifo.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
+#endif
+#endif
+
+#if !defined(BL702L)
+/**
+ * @brief Initialize ir rx.
+ *
+ * @param [in] dev device handle
+ * @param [in] config config pointer to ir rx configure structure
+ */
+void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config);
+
+/**
+ * @brief Receive data in NEC/RC5/customize mode.
+ *
+ * @param [in] dev device handle
+ * @param [out] data data received
+ * @return Bit count of data received
+ */
+uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data);
+
+/**
+ * @brief Receive data in software mode.
+ *
+ * @param [in] dev device handle
+ * @param [out] data data buffer to receive
+ * @param [in] length of data buffer
+ * @return Length of data received
+ */
+uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
+
+/**
+ * @brief Enable or disable ir rx.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_ir_rx_enable(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Get ir rx fifo available count.
+ *
+ * @param [in] dev device handle
+ * @return Ir rx fifo available count
+ */
+uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir rx fifo.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_rxfifo_clear(struct bflb_device_s *dev);
+
+/**
+ * @brief Mask ir rx interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type ir rx interrupt type, use @ref IR_RX_INTEN
+ * @param [in] mask mask or unmask
+ */
+void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
+
+/**
+ * @brief Get ir rx interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Ir rx interrupt status
+ */
+uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir rx interrupt.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_rxint_clear(struct bflb_device_s *dev);
+
+#endif
+
+/**
+ * @brief Control ir feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure
+ */
+int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_irq.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_irq.h
new file mode 100644
index 00000000..c56a7235
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_irq.h
@@ -0,0 +1,125 @@
+#ifndef _BFLB_IRQ_H
+#define _BFLB_IRQ_H
+
+#include "stdint.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup IRQ
+ * @{
+ */
+
+typedef void (*irq_callback)(int irq, void *arg);
+
+/**
+ * @brief IRQ configuration structure
+ *
+ * @param handler Address of the interrupt handler
+ * @param arg The argument provided to the interrupt handler
+ */
+struct bflb_irq_info_s {
+ irq_callback handler;
+ void *arg;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Interrupt initialize.
+ *
+ */
+void bflb_irq_initialize(void);
+
+/**
+ * @brief Disable global irq and save the previous status.
+ *
+ * @return last status
+ */
+uintptr_t bflb_irq_save(void);
+
+/**
+ * @brief Enable global irq by the previous status.
+ *
+ * @param [in] flags previous status by bflb_irq_save
+ */
+void bflb_irq_restore(uintptr_t flags);
+
+/**
+ * @brief Attach interrupt with callback.
+ *
+ * @param [in] irq irq number
+ * @param [in] isr interrupt callback
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_irq_attach(int irq, irq_callback isr, void *arg);
+
+/**
+ * @brief Detach interrupt, reset interrupt callback.
+ *
+ * @param [in] irq irq number
+ * @return A negated errno value on failure.
+ */
+int bflb_irq_detach(int irq);
+
+/**
+ * @brief Enable interrupt.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_enable(int irq);
+
+/**
+ * @brief Disable interrupt.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_disable(int irq);
+
+/**
+ * @brief Set interrupt with pending.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_set_pending(int irq);
+
+/**
+ * @brief Clear interrupt pending status.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_clear_pending(int irq);
+
+/**
+ * @brief Set interrupt group.
+ *
+ * @param [in] nlbits
+ */
+void bflb_irq_set_nlbits(uint8_t nlbits);
+
+/**
+ * @brief Set interrupt priority.
+ *
+ * @param [in] irq irq number
+ * @param [in] preemptprio preempt priority
+ * @param [in] subprio sub priority
+ */
+void bflb_irq_set_priority(int irq, uint8_t preemptprio, uint8_t subprio);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_iso11898.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_iso11898.h
new file mode 100644
index 00000000..2d7b683a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_iso11898.h
@@ -0,0 +1,249 @@
+#ifndef _BFLB_ISO11898_H
+#define _BFLB_ISO11898_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup ISO11898
+ * @{
+ */
+
+#define ISO11898_TIMEOUT (320 * 1000 * 1000)
+
+#define ISO11898_MODE_NORMAL 0 /*!< normal mode */
+#define ISO11898_MODE_LOOPBACK 1 /*!< loopback mode */
+#define ISO11898_MODE_SILENT 2 /*!< silent mode */
+#define ISO11898_MODE_SILENT_LOOPBACK 3 /*!< loopback combined with silent mode */
+
+#define ISO11898_SAMPLE_SINGLE 0 /*!< the bus is sampled three times, recommended for low/medium speed buses */
+#define ISO11898_SAMPLE_TRIPLE 1 /*!< the bus is sampled once, recommended for high speed buses */
+
+#define ISO11898_SJW_1TQ 0 /*!< 1 time quantum */
+#define ISO11898_SJW_2TQ 1 /*!< 2 time quantum */
+#define ISO11898_SJW_3TQ 2 /*!< 3 time quantum */
+#define ISO11898_SJW_4TQ 3 /*!< 4 time quantum */
+
+#define ISO11898_BS1_1TQ 0 /*!< 1 time quantum */
+#define ISO11898_BS1_2TQ 1 /*!< 2 time quantum */
+#define ISO11898_BS1_3TQ 2 /*!< 3 time quantum */
+#define ISO11898_BS1_4TQ 3 /*!< 4 time quantum */
+#define ISO11898_BS1_5TQ 4 /*!< 5 time quantum */
+#define ISO11898_BS1_6TQ 5 /*!< 6 time quantum */
+#define ISO11898_BS1_7TQ 6 /*!< 7 time quantum */
+#define ISO11898_BS1_8TQ 7 /*!< 8 time quantum */
+#define ISO11898_BS1_9TQ 8 /*!< 9 time quantum */
+#define ISO11898_BS1_10TQ 9 /*!< 10 time quantum */
+#define ISO11898_BS1_11TQ 10 /*!< 11 time quantum */
+#define ISO11898_BS1_12TQ 11 /*!< 12 time quantum */
+#define ISO11898_BS1_13TQ 12 /*!< 13 time quantum */
+#define ISO11898_BS1_14TQ 13 /*!< 14 time quantum */
+#define ISO11898_BS1_15TQ 14 /*!< 15 time quantum */
+#define ISO11898_BS1_16TQ 15 /*!< 16 time quantum */
+
+#define ISO11898_BS2_1TQ 0 /*!< 1 time quantum */
+#define ISO11898_BS2_2TQ 1 /*!< 2 time quantum */
+#define ISO11898_BS2_3TQ 2 /*!< 3 time quantum */
+#define ISO11898_BS2_4TQ 3 /*!< 4 time quantum */
+#define ISO11898_BS2_5TQ 4 /*!< 5 time quantum */
+#define ISO11898_BS2_6TQ 5 /*!< 6 time quantum */
+#define ISO11898_BS2_7TQ 6 /*!< 7 time quantum */
+#define ISO11898_BS2_8TQ 7 /*!< 8 time quantum */
+
+#define ISO11898_ID_STANDARD 0 /*!< standard ID */
+#define ISO11898_ID_EXTENDED 1 /*!< extended ID */
+
+#define ISO11898_RTR_DATA 0 /*!< data frame */
+#define ISO11898_RTR_REMOTE 1 /*!< remote frame */
+
+/** @defgroup ISO11898_INTSTS iso11898 interrupt status definition
+ * @{
+ */
+#define ISO11898_INTSTS_RX (1 << 0)
+#define ISO11898_INTSTS_TX (1 << 1)
+#define ISO11898_INTSTS_ERROR_WARNING (1 << 2)
+#define ISO11898_INTSTS_DATA_OVERRUN (1 << 3)
+#define ISO11898_INTSTS_ERROR_PASSIVE (1 << 5)
+#define ISO11898_INTSTS_ARBITRATION_LOST (1 << 6)
+#define ISO11898_INTSTS_BUS_ERROR (1 << 7)
+/**
+ * @}
+ */
+
+#define ISO11898_STATUS_RX_NOT_EMPTY (1 << 0)
+#define ISO11898_STATUS_RX_OVERRUN (1 << 1)
+#define ISO11898_STATUS_TX_AVAILABLE (1 << 2)
+#define ISO11898_STATUS_TX_COMPLETE (1 << 3)
+#define ISO11898_STATUS_RX_RECEIVING (1 << 4)
+#define ISO11898_STATUS_TX_SENDING (1 << 5)
+#define ISO11898_STATUS_ERROR_COUNTER (1 << 6)
+#define ISO11898_STATUS_BUS_OFF (1 << 7)
+
+#define ISO11898_FILTER_TYPE_SINGLE 0
+#define ISO11898_FILTER_TYPE_DUAL 1
+
+struct bflb_iso11898_config_s {
+ uint8_t prescaler; /*!< specifies the length of a time quantum, ranges from 1 to 63, tq=tclk*2*(prescaler+1) */
+ uint8_t mode; /*!< specifies the CAN operating mode. @ref ISO11898_MODE_XXX */
+ uint8_t sample; /*!< specifies the number of sample times. @ref ISO11898_SAMPLE_XXX */
+ uint8_t sjw; /*!< specifies the maximum number of time quanta the ISO11898 hardware is allowed to lengthen or shorten a bit to perform resynchronization. @ref ISO11898_SJW_XXX */
+ uint8_t bs1; /*!< specifies the number of time quanta in Bit Segment 1. @ref ISO11898_BS1_XXX */
+ uint8_t bs2; /*!< specifies the number of time quanta in Bit Segment 2. @ref ISO11898_BS2_XXX */
+};
+
+struct bflb_iso11898_msg_s {
+ uint32_t std_id; /*!< specifies the standard identifier, this parameter can be a value between 0 to 0x7FF */
+ uint32_t ext_id; /*!< specifies the extended identifier, this parameter can be a value between 0 to 0x1FFFFFFF */
+ uint8_t id_type; /*!< specifies the type of identifier for the message that will be send or received. @ref ISO11898_ID_XXX */
+ uint8_t rtr; /*!< specifies the type of frame for the message that will be send or received, @ref ISO11898_RTR_XXX */
+ uint8_t dlc; /*!< specifies the length of the frame that will be send or received, this parameter can be a value between 0 to 8 */
+ uint8_t data[8]; /*!< contains the data to be send or received, it ranges from 0 to 0xFF */
+};
+
+struct bflb_iso11898_filter_s {
+ uint8_t filter_type;
+ uint8_t code0;
+ uint8_t code1;
+ uint8_t code2;
+ uint8_t code3;
+ uint8_t mask0;
+ uint8_t mask1;
+ uint8_t mask2;
+ uint8_t mask3;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] config
+ */
+void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_iso11898_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_iso11898_abort_send(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] msg
+ * @param [in] timeout
+ * @return int8_t
+ */
+int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] msg
+ * @param [in] timeout
+ * @return int8_t
+ */
+int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mode
+ */
+void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint8_t
+ */
+uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint8_t
+ */
+uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] filter
+ */
+void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mask
+ */
+void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mask
+ */
+void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mask
+ */
+void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint32_t
+ */
+uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] cmd
+ * @param [in] arg
+ * @return int
+ */
+int bflb_iso11898_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_kys.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_kys.h
new file mode 100644
index 00000000..677aff33
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_kys.h
@@ -0,0 +1,53 @@
+#ifndef _BFLB_KYS_H
+#define _BFLB_KYS_H
+
+#include "bflb_core.h"
+
+struct bflb_kys_config_s {
+ uint8_t col; /* Col of keyboard,max:8 */
+ uint8_t row; /* Row of keyboard,max:8 */
+ uint8_t deglitch_en; /* Disable deglitch function */
+ uint8_t deglitch_cnt; /* Deglitch count */
+ uint8_t idle_duration; /* Idle duration between column scans */
+ uint8_t ghost_en; /* Disable ghost key event detection */
+};
+
+/* keyscan interrupt enable define */
+#if defined(BL702)
+#define KEYSCAN_INT_EN (0x1 << 0)
+#else
+#define KEYSCAN_INT_EN_DONE (0x1 << 7)
+#define KEYSCAN_INT_EN_FIFOFULL (0x1 << 8)
+#define KEYSCAN_INT_EN_FIFOHALF (0x1 << 9)
+#define KEYSCAN_INT_EN_FIFOQUARTER (0x1 << 10)
+#define KEYSCAN_INT_EN_FIFO_NONEMPTY (0x1 << 11)
+#define KEYSCAN_INT_EN_GHOST (0x1 << 12)
+#endif
+
+/* keyscan interrupt clear */
+#if defined(BL702L)
+#define KEYSCAN_INT_CLR_DONE (0x1 << 7)
+#define KEYSCAN_INT_CLR_FIFO (0x1 << 8)
+#define KEYSCAN_INT_CLR_GHOST (0x1 << 12)
+#endif
+
+#if defined(BL702)
+/* keyscan keycode status and clear */
+#define KEYSCAN_STS_KEYCODE0 (0x1 << 0)
+#define KEYSCAN_STS_KEYCODE1 (0x1 << 1)
+#define KEYSCAN_STS_KEYCODE2 (0x1 << 2)
+#define KEYSCAN_STS_KEYCODE3 (0x1 << 3)
+#endif
+
+void bflb_kys_init(struct bflb_device_s *dev, const struct bflb_kys_config_s *config);
+void bflb_kys_enable(struct bflb_device_s *dev);
+void bflb_kys_disable(struct bflb_device_s *dev);
+void bflb_kys_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable);
+void bflb_kys_int_clear(struct bflb_device_s *dev, uint32_t flag);
+uint32_t bflb_kys_get_int_status(struct bflb_device_s *dev);
+#if defined(BL702L)
+void bflb_kys_get_fifo_info(struct bflb_device_s *dev, uint8_t *fifo_head, uint8_t *fifo_tail, uint8_t *fifo_valid_cnt);
+#endif
+uint8_t bflb_kys_read_keyvalue(struct bflb_device_s *dev, uint8_t index);
+
+#endif // _BFLB_KYS_H
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_l1c.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_l1c.h
new file mode 100644
index 00000000..7d15367f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_l1c.h
@@ -0,0 +1,98 @@
+#ifndef _BFLB_L1C_H
+#define _BFLB_L1C_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup L1C
+ * @{
+ */
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_icache_enable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_icache_disable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_icache_invalid_all(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_enable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_disable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_clean_all(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_invalidate_all(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_clean_invalidate_all(void);
+
+/**
+ * @brief
+ *
+ * @param [in] addr
+ * @param [in] size
+ */
+void bflb_l1c_dcache_clean_range(void *addr, uint32_t size);
+
+/**
+ * @brief
+ *
+ * @param [in] addr
+ * @param [in] size
+ */
+void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size);
+
+/**
+ * @brief
+ *
+ * @param [in] addr
+ * @param [in] size
+ */
+void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size);
+
+void bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high);
+uint32_t bflb_l1c_miss_count_get(void);
+void bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_list.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_list.h
new file mode 100644
index 00000000..7ad2245a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_list.h
@@ -0,0 +1,270 @@
+/**
+ * @file bflb_list.h
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _BFLB_LIST_H
+#define _BFLB_LIST_H
+
+#include "string.h"
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * container_of - return the member address of ptr, if the type of ptr is the
+ * struct type.
+ */
+#define bflb_container_of(ptr, type, member) \
+ ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
+
+/**
+ * Double List structure
+ */
+struct bflb_dlist_node {
+ struct bflb_dlist_node *next; /**< point to next node. */
+ struct bflb_dlist_node *prev; /**< point to prev node. */
+};
+typedef struct bflb_dlist_node bflb_dlist_t; /**< Type for lists. */
+
+/**
+ * @brief initialize a list
+ *
+ * @param l list to be initialized
+ */
+static inline void bflb_dlist_init(bflb_dlist_t *l)
+{
+ l->next = l->prev = l;
+}
+
+/**
+ * @brief insert a node after a list
+ *
+ * @param l list to insert it
+ * @param n new node to be inserted
+ */
+static inline void bflb_dlist_insert_after(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+ l->next->prev = n;
+ n->next = l->next;
+
+ l->next = n;
+ n->prev = l;
+}
+
+/**
+ * @brief insert a node before a list
+ *
+ * @param n new node to be inserted
+ * @param l list to insert it
+ */
+static inline void bflb_dlist_insert_before(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+ l->prev->next = n;
+ n->prev = l->prev;
+
+ l->prev = n;
+ n->next = l;
+}
+
+/**
+ * @brief remove node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void bflb_dlist_remove(bflb_dlist_t *n)
+{
+ n->next->prev = n->prev;
+ n->prev->next = n->next;
+
+ n->next = n->prev = n;
+}
+
+/**
+ * @brief move node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void bflb_dlist_move_head(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+ bflb_dlist_remove(n);
+ bflb_dlist_insert_after(l, n);
+}
+
+/**
+ * @brief move node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void bflb_dlist_move_tail(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+ bflb_dlist_remove(n);
+ bflb_dlist_insert_before(l, n);
+}
+
+/**
+ * @brief tests whether a list is empty
+ * @param l the list to test.
+ */
+static inline int bflb_dlist_isempty(const bflb_dlist_t *l)
+{
+ return l->next == l;
+}
+
+/**
+ * @brief get the list length
+ * @param l the list to get.
+ */
+static inline unsigned int bflb_dlist_len(const bflb_dlist_t *l)
+{
+ unsigned int len = 0;
+ const bflb_dlist_t *p = l;
+
+ while (p->next != l) {
+ p = p->next;
+ len++;
+ }
+
+ return len;
+}
+
+/**
+ * @brief initialize a dlist object
+ */
+#define DLIST_OBJECT_INIT(object) \
+ { \
+ &(object), &(object) \
+ }
+/**
+ * @brief initialize a dlist object
+ */
+#define DLIST_DEFINE(list) \
+ bflb_dlist_t list = { &(list), &(list) }
+
+/**
+ * @brief get the struct for this entry
+ * @param node the entry point
+ * @param type the type of structure
+ * @param member the name of list in structure
+ */
+#define bflb_dlist_entry(node, type, member) \
+ bflb_container_of(node, type, member)
+
+/**
+ * dlist_first_entry - get the first element from a list
+ * @ptr: the list head to take the element from.
+ * @type: the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define bflb_dlist_first_entry(ptr, type, member) \
+ bflb_dlist_entry((ptr)->next, type, member)
+/**
+ * dlist_first_entry_or_null - get the first element from a list
+ * @ptr: the list head to take the element from.
+ * @type: the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define bflb_dlist_first_entry_or_null(ptr, type, member) \
+ (bflb_dlist_isempty(ptr) ? NULL : bflb_dlist_first_entry(ptr, type, member))
+
+/**
+ * dlist_for_each - iterate over a list
+ * @pos: the dlist_t * to use as a loop cursor.
+ * @head: the head for your list.
+ */
+#define bflb_dlist_for_each(pos, head) \
+ for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * dlist_for_each_prev - iterate over a list
+ * @pos: the dlist_t * to use as a loop cursor.
+ * @head: the head for your list.
+ */
+#define bflb_dlist_for_each_prev(pos, head) \
+ for (pos = (head)->prev; pos != (head); pos = pos->prev)
+
+/**
+ * dlist_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos: the dlist_t * to use as a loop cursor.
+ * @n: another dlist_t * to use as temporary storage
+ * @head: the head for your list.
+ */
+#define bflb_dlist_for_each_safe(pos, n, head) \
+ for (pos = (head)->next, n = pos->next; pos != (head); \
+ pos = n, n = pos->next)
+
+#define bflb_dlist_for_each_prev_safe(pos, n, head) \
+ for (pos = (head)->prev, n = pos->prev; pos != (head); \
+ pos = n, n = pos->prev)
+/**
+ * dlist_for_each_entry - iterate over list of given type
+ * @pos: the type * to use as a loop cursor.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry(pos, head, member) \
+ for (pos = bflb_dlist_entry((head)->next, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = bflb_dlist_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * dlist_for_each_entry_reverse - iterate over list of given type
+ * @pos: the type * to use as a loop cursor.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry_reverse(pos, head, member) \
+ for (pos = bflb_dlist_entry((head)->prev, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = bflb_dlist_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos: the type * to use as a loop cursor.
+ * @n: another type * to use as temporary storage
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry_safe(pos, n, head, member) \
+ for (pos = bflb_dlist_entry((head)->next, typeof(*pos), member), \
+ n = bflb_dlist_entry(pos->member.next, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = n, n = bflb_dlist_entry(n->member.next, typeof(*n), member))
+
+/**
+ * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos: the type * to use as a loop cursor.
+ * @n: another type * to use as temporary storage
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry_safe_reverse(pos, n, head, member) \
+ for (pos = bflb_dlist_entry((head)->prev, typeof(*pos), field), \
+ n = bflb_dlist_entry(pos->member.prev, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = n, n = bflb_dlist_entry(pos->member.prev, typeof(*pos), member))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_mjpeg.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_mjpeg.h
new file mode 100644
index 00000000..7cde648d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_mjpeg.h
@@ -0,0 +1,251 @@
+#ifndef _BFLB_MJPEG_H
+#define _BFLB_MJPEG_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup MJPEG
+ * @{
+ */
+
+/** @defgroup MJPEG_FORMAT mjpeg format definition
+ * @{
+ */
+#define MJPEG_FORMAT_YUV422_YUYV 0
+#define MJPEG_FORMAT_YUV422_YVYU 1
+#define MJPEG_FORMAT_YUV422_UYVY 2
+#define MJPEG_FORMAT_YUV422_VYUY 3
+#define MJPEG_FORMAT_YUV422SP_NV16 4
+#define MJPEG_FORMAT_YUV422SP_NV61 5
+#define MJPEG_FORMAT_YUV420SP_NV12 6
+#define MJPEG_FORMAT_YUV420SP_NV21 7
+#define MJPEG_FORMAT_GRAY 8
+/**
+ * @}
+ */
+
+/** @defgroup MJPEG_INTSTS mjpeg interrupt status definition
+ * @{
+ */
+#define MJPEG_INTSTS_ONE_FRAME (1 << 4)
+/**
+ * @}
+ */
+
+/** @defgroup MJPEG_INTCLR mjpeg interrupt clear definition
+ * @{
+ */
+#define MJPEG_INTCLR_ONE_FRAME (1 << 8)
+/**
+ * @}
+ */
+
+/** @defgroup MJPEG_CMD mjpeg feature control cmd definition
+ * @{
+ */
+#define MJPEG_CMD_SET_INPUTADDR0 0x00
+#define MJPEG_CMD_SET_INPUTADDR1 0x01
+/**
+ * @}
+ */
+
+#define MJPEG_MAX_FRAME_COUNT 4
+
+/**
+ * @brief MJPEG configuration structure
+ *
+ * @param format MJPEG format, use @ref MJPEG_FORMAT
+ * @param resolution_x MJPEG width, must be a multiple of 8 or a multiple of 16
+ * @param resolution_y MJPEG higth, must be a multiple of 8 or a multiple of 16
+ * @param input_bufaddr0 MJPEG input buffer address 0 for yy , must be align 16
+ * @param input_bufaddr1 MJPEG input buffer address 0 for yy , must be align 16
+ * @param output_bufaddr MJPEG output buffer address , must be align 16
+ * @param output_bufsize MJPEG output buffer size, must be larger than resolution_x*resolution_y*2*MJPEG_MAX_FRAME_COUNT
+ */
+struct bflb_mjpeg_config_s {
+ uint8_t format;
+ uint8_t quality;
+ uint16_t rows;
+ uint16_t resolution_x;
+ uint16_t resolution_y;
+ uint32_t input_bufaddr0;
+ uint32_t input_bufaddr1;
+ uint32_t output_bufaddr;
+ uint32_t output_bufsize;
+ uint16_t *input_yy_table;
+ uint16_t *input_uv_table;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize mjpeg.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save mjpeg config
+ */
+void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s *config);
+
+/**
+ * @brief Start mjpeg compression with camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop mjpeg compression with camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Start mjpeg compression without camera.
+ *
+ * @param [in] dev device handle
+ * @param [in] frame_count frame count to compress
+ */
+void bflb_mjpeg_sw_run(struct bflb_device_s *dev, uint8_t frame_count);
+
+/**
+ * @brief Start mjpeg kick mode compression without camera.
+ *
+ * @param [in] dev device handle
+ * @param [in] kick_count kick block horizontal count to compress
+ */
+void bflb_mjpeg_kick_run(struct bflb_device_s *dev, uint16_t kick_count);
+
+/**
+ * @brief Stop mjpeg kick mode compression without camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_kick_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief kick one times compression without camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_kick(struct bflb_device_s *dev);
+/**
+ * @brief Enable or disable mjpeg one frame compression completion interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_mjpeg_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable mjpeg error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_mjpeg_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get mjpeg interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status
+ */
+uint32_t bflb_mjpeg_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear mjpeg interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value
+ */
+void bflb_mjpeg_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Get number of frame count that has compressed.
+ *
+ * @param [in] dev device handle
+ * @return compressed frame count
+ */
+uint8_t bflb_mjpeg_get_frame_count(struct bflb_device_s *dev);
+
+/**
+ * @brief Drop one frame that has compressed.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_pop_one_frame(struct bflb_device_s *dev);
+
+/**
+ * @brief Get one frame information.
+ *
+ * @param [in] dev device handle
+ * @param [in] pic pointer to save frame address.
+ * @return frame length
+ */
+uint32_t bflb_mjpeg_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
+
+/**
+ * @brief Calculate jpeg quantize table.
+ *
+ * @param [in] quality image quality
+ * @param [in] input_table pointer to save input table
+ * @param [in] output_table pointer to save output table
+ */
+void bflb_mjpeg_calculate_quantize_table(uint8_t quality, uint16_t *input_table, uint16_t *output_table);
+
+/**
+ * @brief Fill quantize table into mjpeg register.
+ *
+ * @param [in] dev device handle
+ * @param [in] input_yy yy quantize table
+ * @param [in] input_uv uv quantize table
+ */
+void bflb_mjpeg_fill_quantize_table(struct bflb_device_s *dev, uint16_t *input_yy, uint16_t *input_uv);
+
+/**
+ * @brief Fill jpeg header into mjpeg register and enable hardware auto adding jpeg tail.
+ *
+ * @param [in] dev device handle
+ * @param [in] header pointer to jpeg header
+ * @param [in] header_len jpeg header length
+ */
+void bflb_mjpeg_fill_jpeg_header_tail(struct bflb_device_s *dev, uint8_t *header, uint32_t header_len);
+
+/**
+ * @brief Set mjpeg input when uses camera with yuv402sp.
+ *
+ * @param [in] dev device handle
+ * @param [in] yy camera id for yy
+ * @param [in] uv camera id for uv
+ */
+void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, uint8_t uv);
+
+/**
+ * @brief Control mjpeg feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_mjpeg_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_mtimer.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_mtimer.h
new file mode 100644
index 00000000..447820d6
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_mtimer.h
@@ -0,0 +1,74 @@
+#ifndef _BFLB_MTIMER_H
+#define _BFLB_MTIMER_H
+
+#include "stdint.h"
+#include "stdio.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup MTIMER
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Config mtimer interrupt.
+ *
+ * @param [in] ticks ticks to invoke interrupt.
+ * @param [in] interruptfun interrupt callback
+ */
+void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void));
+
+/**
+ * @brief Get mtimer current frequence.
+ *
+ * @return frequence
+ */
+uint32_t bflb_mtimer_get_freq(void);
+
+/**
+ * @brief Mtimer delay with ms.
+ *
+ * @param [in] time delay time
+ */
+void bflb_mtimer_delay_ms(uint32_t time);
+
+/**
+ * @brief Mtimer delay with us.
+ *
+ * @param [in] time delay time
+ */
+void bflb_mtimer_delay_us(uint32_t time);
+
+/**
+ * @brief Get current mtimer time with us.
+ *
+ * @return time with us
+ */
+uint64_t bflb_mtimer_get_time_us();
+
+/**
+ * @brief Get current mtimer time with ms.
+ *
+ * @return time with ms
+ */
+uint64_t bflb_mtimer_get_time_ms();
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pec_ip.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pec_ip.h
new file mode 100644
index 00000000..fcf1768d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pec_ip.h
@@ -0,0 +1,189 @@
+#ifndef __BFLB_PEC_IP_H__
+#define __BFLB_PEC_IP_H__
+
+#include "bflb_core.h"
+
+#define PEC0 0
+#define PEC_MAX 1
+
+#define PEC_SM0 0
+#define PEC_SM1 1
+#define PEC_SM2 2
+#define PEC_SM3 3
+#define PEC_SM_MAX 4
+
+#define PEC_FLAG_0 (1 << 0)
+#define PEC_FLAG_1 (1 << 1)
+#define PEC_FLAG_2 (1 << 2)
+#define PEC_FLAG_3 (1 << 3)
+#define PEC_FLAG_4 (1 << 4)
+#define PEC_FLAG_5 (1 << 5)
+#define PEC_FLAG_6 (1 << 6)
+#define PEC_FLAG_7 (1 << 7)
+
+#define PEC_IP_NULL 0
+#define PEC_IP_PWM 1
+#define PEC_IP_UART_TX 2
+#define PEC_IP_UART_RX 3
+#define PEC_IP_SPI 4
+#define PEC_IP_I2C 5
+#define PEC_IP_WS2812 6
+#define PEC_IP_JTAG 7
+#define PEC_IP_DPI 8
+#define PEC_IP_LA 9
+#define PEC_IP_SEG 10
+#define PEC_IP_DBI_B 11
+#define PEC_IP_4xI2S 12
+
+#define PEC_ERR_OK 0
+#define PEC_ERR_NOT_SUPPORT 1
+#define PEC_ERR_PIN_CONFLICT 2
+#define PEC_ERR_SM_LACK 3
+#define PEC_ERR_CODE_SPACE_LACK 4
+#define PEC_ERR_FLAG_LACK 5
+
+extern uint32_t bflb_pec_get_tx_fifo_addr(uint8_t pec_id, uint8_t sm_id);
+extern uint32_t bflb_pec_get_rx_fifo_addr(uint8_t pec_id, uint8_t sm_id);
+extern void bflb_pec_dma_tx_enable(uint8_t pec_id, uint8_t sm_id, uint8_t enable);
+extern void bflb_pec_dma_rx_enable(uint8_t pec_id, uint8_t sm_id, uint8_t enable);
+
+struct bflb_pec_pwm_s {
+ uint32_t high_cnt; /*!< high level count */
+ uint32_t low_cnt; /*!< low level count */
+ uint16_t div; /*!< divisor */
+ uint8_t pin; /*!< PWM output assert pin index */
+ uint8_t pec;
+ uint8_t sm;
+ uint8_t addr;
+};
+
+int bflb_pec_pwm_init(struct bflb_pec_pwm_s *pwm);
+void bflb_pec_pwm_start(struct bflb_pec_pwm_s *pwm);
+void bflb_pec_pwm_stop(struct bflb_pec_pwm_s *pwm);
+
+struct bflb_pec_jtag_s {
+ uint8_t pin_tck;
+ uint8_t pin_tms;
+ uint8_t pin_tdo;
+ uint8_t pin_tdi;
+ uint8_t pec;
+ uint8_t sm;
+ uint8_t addr;
+};
+
+int bflb_pec_jtag_init(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_set_tck(struct bflb_pec_jtag_s *jtag, uint8_t value);
+void bflb_pec_jtag_set_tms(struct bflb_pec_jtag_s *jtag, uint8_t value);
+void bflb_pec_jtag_set_tdi(struct bflb_pec_jtag_s *jtag, uint8_t value);
+int bflb_pec_jtag_get_tdo(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_set_path(struct bflb_pec_jtag_s *jtag, uint32_t path, uint32_t bits);
+void bflb_pec_jtag_select_ir(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_exit_ir(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_select_dr(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_exit_dr(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_scan_ir(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out, uint8_t *ir_in);
+void bflb_pec_jtag_scan_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_out, uint8_t *dr_in);
+void bflb_pec_jtag_scan(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out, uint8_t *ir_in, uint8_t dr_bits, uint8_t *dr_out, uint8_t *dr_in);
+void bflb_pec_jtag_write_ir(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out);
+void bflb_pec_jtag_write_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_out);
+void bflb_pec_jtag_read_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_in);
+
+/* pixel format */
+#define PEC_DBI_B_PIXEL_FORMAT_NRGB8888 1 /* 32-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_NBGR8888 2 /* 32-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_RGB888 3 /* 24-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_BGR888 4 /* 24-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_RGB565 5 /* 16-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_BGR565 6 /* 16-bit */
+
+/* transmit mode */
+#define PEC_DBI_TRANSMIT_MODE_CMD 0
+#define PEC_DBI_TRANSMIT_MODE_PIXEL 1
+
+struct bflb_pec_dbi_b_s {
+ uint32_t clk_src;
+ uint32_t clk;
+ uint8_t pixel_format;
+ uint8_t pin_dc;
+ uint8_t pin_wr;
+ uint8_t pin_data;
+ uint8_t pec;
+ uint8_t sm;
+ uint8_t addr;
+ uint8_t fifo_threshold;
+};
+
+int bflb_pec_dbi_b_init(struct bflb_pec_dbi_b_s *dbi_b);
+uint32_t bflb_pec_dbi_b_build_head(struct bflb_pec_dbi_b_s *dbi_b, uint8_t transmit_mode, uint8_t cmd, size_t data_num);
+uint32_t bflb_pec_dbi_b_get_fifo_address(struct bflb_pec_dbi_b_s *dbi_b);
+int bflb_pec_dbi_b_get_fifo_cnt(struct bflb_pec_dbi_b_s *dbi_b);
+int bflb_pec_dbi_b_dma_enable(struct bflb_pec_dbi_b_s *dbi_b, bool en);
+
+/* Signal polarity selection */
+#define V_SYNC_SINGLE_POL 0
+#define H_SYNC_SINGLE_POL 0
+#define DE_SINGLE_POL 1
+
+struct bflb_pec_dpi_s {
+ uint16_t width;
+ uint16_t height;
+
+ uint16_t hsw;
+ uint16_t hbp;
+ uint16_t hfp;
+
+ uint16_t vsw;
+ uint16_t vbp;
+ uint16_t vfp;
+
+ bool data_latch_mode;
+ bool de_sig_enable;
+ bool de_sig_polarity;
+ bool v_sync_sig_polarity;
+ bool h_sync_sig_polarity;
+
+ uint32_t *invalid_row_para;
+
+ uint16_t frame_rate;
+ uint16_t data_format;
+
+ uint8_t pin_clk;
+ uint8_t pin_hs;
+ uint8_t pin_data;
+ uint8_t pec;
+ uint8_t sm;
+};
+
+int bflb_pec_dpi_init(struct bflb_pec_dpi_s *dpi);
+
+#define PEC_I2S_SAMPLE_RATE_24KHZ 1
+#define PEC_I2S_SAMPLE_RATE_48KHZ 2
+#define PEC_I2S_SAMPLE_RATE_96KHZ 3
+
+#define PEC_I2S_DATA_FORMAT_BIT24IN32R 0
+#define PEC_I2S_DATA_FORMAT_BIT16 1
+#define PEC_I2S_DATA_FORMAT_BIT32 2
+
+struct bflb_pec_i2sx4_s {
+ uint8_t sample_rate;
+ uint8_t data_format;
+ uint8_t pin_bck;
+ uint8_t pin_ws;
+ uint8_t pin_d0;
+ uint8_t pin_d1;
+ uint8_t pin_d2;
+ uint8_t pin_d3;
+ uint8_t pec;
+ // uint8_t sm;
+ // uint8_t addr;
+ uint8_t flag;
+};
+
+int bflb_pec_i2sx4_init(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_enable(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_disable(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_rx_start(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_rx_stop(struct bflb_pec_i2sx4_s *i2s);
+uint8_t bflb_pec_i2sx4_get_data(struct bflb_pec_i2sx4_s *i2s, uint8_t ch, uint32_t *data);
+
+#endif /* __BFLB_PEC_IP_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pwm_v1.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pwm_v1.h
new file mode 100644
index 00000000..d5ee6ed6
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pwm_v1.h
@@ -0,0 +1,189 @@
+#ifndef _BFLB_PWM_V1_H
+#define _BFLB_PWM_V2_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup PWM_V1
+ * @{
+ */
+
+/** @defgroup PWM_CHANNEL pwm channel definition
+ * @{
+ */
+#define PWM_CH0 0
+#define PWM_CH1 1
+#define PWM_CH2 2
+#define PWM_CH3 3
+#define PWM_CH4 4
+#define PWM_V1_CH_MAX 5
+/**
+ * @}
+ */
+
+/** @defgroup PWM_INTSTS pwm interrupt status definition
+ * @{
+ */
+#define PWM_INTSTS_REPT_CH0 (1 << 0)
+#define PWM_INTSTS_REPT_CH1 (1 << 1)
+#define PWM_INTSTS_REPT_CH2 (1 << 2)
+#define PWM_INTSTS_REPT_CH3 (1 << 3)
+#define PWM_INTSTS_REPT_CH4 (1 << 4)
+/**
+ * @}
+ */
+
+/** @defgroup PWM_INTCLR pwm interrupt clear definition
+ * @{
+ */
+#define PWM_INTCLR_REPT_CH0 (1 << 8)
+#define PWM_INTCLR_REPT_CH1 (1 << 9)
+#define PWM_INTCLR_REPT_CH2 (1 << 10)
+#define PWM_INTCLR_REPT_CH3 (1 << 11)
+#define PWM_INTCLR_REPT_CH4 (1 << 12)
+/**
+ * @}
+ */
+
+/** @defgroup PWM_CMD pwm feature control cmd definition
+ * @{
+ */
+#define PWM_CMD_SET_STOP_MODE (0x01)
+#define PWM_CMD_SET_OUT_INVERT (0x02)
+#define PWM_CMD_SET_SW_MODE (0x03)
+#define PWM_CMD_SET_SW_FORCE_VALUE (0x04)
+#define PWM_CMD_SET_REPT_COUNT (0x05)
+/**
+ * @}
+ */
+
+/** @defgroup PWM_STOP_MODE pwm stop mode definition
+ * @{
+ */
+#define PWM_STOP_MODE_ABRUPT 0
+#define PWM_STOP_MODE_GRACEFUL 1
+/**
+ * @}
+ */
+
+/**
+ * @brief PWM configuration structure
+ *
+ * @param clk_source PWM clock source, use @ref BFLB_SYSTEM_CLOCK
+ * @param clk_div PWM clock dividor, should be in 1~65535
+ * @param period PWM period count, should be in 2~65535
+ */
+struct bflb_pwm_v1_channel_config_s {
+ uint8_t clk_source;
+ uint16_t clk_div;
+ uint16_t period;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize pwm channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] config pointer to save pwm channel config
+ */
+void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struct bflb_pwm_v1_channel_config_s *config);
+
+/**
+ * @brief Deinitialize pwm channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v1_channel_deinit(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Start pwm channel output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Stop pwm channel output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Set pwm channel period to change pwm frequence. Frequcence(hz) = pwm source clock /div/period.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] period pwm period
+ */
+void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t period);
+
+/**
+ * @brief Set pwm dutycycle. Dutycycle(%) = (high_threhold - low_threhold)/period * 100%.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] low_threhold pwm low threhold
+ * @param [in] high_threhold pwm high threhold
+ */
+void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
+
+/**
+ * @brief Enable pwm interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable);
+
+/**
+ * @brief Get pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref PWM_INTSTS
+ */
+uint32_t bflb_pwm_v1_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref PWM_INTCLR
+ */
+void bflb_pwm_v1_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] cmd feature command, use @ref PWM_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pwm_v2.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pwm_v2.h
new file mode 100644
index 00000000..88ebe746
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_pwm_v2.h
@@ -0,0 +1,309 @@
+#ifndef _BFLB_PWM_V2_H
+#define _BFLB_PWM_V2_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup PWM_V2
+ * @{
+ */
+
+/** @defgroup PWM_CHANNEL pwm channel definition
+ * @{
+ */
+#define PWM_CH0 0
+#define PWM_CH1 1
+#define PWM_CH2 2
+#define PWM_CH3 3
+#define PWM_V2_CH_MAX 4
+/**
+ * @}
+ */
+
+/** @defgroup PWM_POLARITY pwm polarity definition
+ * @{
+ */
+#define PWM_POLARITY_ACTIVE_LOW 0
+#define PWM_POLARITY_ACTIVE_HIGH 1
+/**
+ * @}
+ */
+
+/** @defgroup PWM_STATE pwm state definition
+ * @{
+ */
+#define PWM_STATE_INACTIVE 0
+#define PWM_STATE_ACTIVE 1
+/**
+ * @}
+ */
+
+/** @defgroup PWM_TRIG_SDC_SRC pwm trigger adc source definition
+ * @{
+ */
+#define PWM_TRIG_ADC_SRC_CH0_L 0
+#define PWM_TRIG_ADC_SRC_CH0_H 1
+#define PWM_TRIG_ADC_SRC_CH1_L 2
+#define PWM_TRIG_ADC_SRC_CH1_H 3
+#define PWM_TRIG_ADC_SRC_CH2_L 4
+#define PWM_TRIG_ADC_SRC_CH2_H 5
+#define PWM_TRIG_ADC_SRC_CH3_L 6
+#define PWM_TRIG_ADC_SRC_CH3_H 7
+#define PWM_TRIG_ADC_SRC_PERIOD 8
+#define PWM_TRIG_ADC_SRC_NONE 0xF
+/**
+ * @}
+ */
+
+/** @defgroup PWM_INTEN pwm interrupt enable definition
+ * @{
+ */
+#define PWM_INTEN_CH0_L (1 << 0)
+#define PWM_INTEN_CH0_H (1 << 1)
+#define PWM_INTEN_CH1_L (1 << 2)
+#define PWM_INTEN_CH1_H (1 << 3)
+#define PWM_INTEN_CH2_L (1 << 4)
+#define PWM_INTEN_CH2_H (1 << 5)
+#define PWM_INTEN_CH3_L (1 << 6)
+#define PWM_INTEN_CH3_H (1 << 7)
+#define PWM_INTEN_PERIOD (1 << 8)
+#define PWM_INTEN_BRAKE (1 << 9)
+#define PWM_INTEN_REPT (1 << 10)
+/**
+ * @}
+ */
+
+/** @defgroup PWM_INTSTS pwm interrupt status definition
+ * @{
+ */
+#define PWM_INTSTS_CH0_L (1 << 0)
+#define PWM_INTSTS_CH0_H (1 << 1)
+#define PWM_INTSTS_CH1_L (1 << 2)
+#define PWM_INTSTS_CH1_H (1 << 3)
+#define PWM_INTSTS_CH2_L (1 << 4)
+#define PWM_INTSTS_CH2_H (1 << 5)
+#define PWM_INTSTS_CH3_L (1 << 6)
+#define PWM_INTSTS_CH3_H (1 << 7)
+#define PWM_INTSTS_PERIOD (1 << 8)
+#define PWM_INTSTS_BRAKE (1 << 9)
+#define PWM_INTSTS_REPT (1 << 10)
+/**
+ * @}
+ */
+
+/** @defgroup PWM_INTCLR pwm interrupt clear definition
+ * @{
+ */
+#define PWM_INTCLR_CH0_L (1 << 0)
+#define PWM_INTCLR_CH0_H (1 << 1)
+#define PWM_INTCLR_CH1_L (1 << 2)
+#define PWM_INTCLR_CH1_H (1 << 3)
+#define PWM_INTCLR_CH2_L (1 << 4)
+#define PWM_INTCLR_CH2_H (1 << 5)
+#define PWM_INTCLR_CH3_L (1 << 6)
+#define PWM_INTCLR_CH3_H (1 << 7)
+#define PWM_INTCLR_PERIOD (1 << 8)
+#define PWM_INTCLR_BRAKE (1 << 9)
+#define PWM_INTCLR_REPT (1 << 10)
+/**
+ * @}
+ */
+
+/** @defgroup PWM_CMD pwm feature control cmd definition
+ * @{
+ */
+#define PWM_CMD_SET_TRIG_ADC_SRC (0x01)
+#define PWM_CMD_SET_EXT_BRAKE_POLARITY (0x02)
+#define PWM_CMD_SET_EXT_BRAKE_ENABLE (0x03)
+#define PWM_CMD_SET_SW_BRAKE_ENABLE (0x04)
+#define PWM_CMD_SET_STOP_ON_REPT (0x05)
+#define PWM_CMD_SET_REPT_COUNT (0x06)
+/**
+ * @}
+ */
+
+/**
+ * @brief PWM channel configuration structure
+ *
+ * @param positive_polarity PWM posotive channel polarity, use @ref PWM_POLARITY
+ * @param negative_polarity PWM negative channel polarity, use @ref PWM_POLARITY
+ * @param positive_stop_state PWM posotive channel state when stop, use @ref PWM_STATE
+ * @param negative_stop_state PWM negative channel state when stop, use @ref PWM_STATE
+ * @param positive_brake_state PWM posotive channel state when brake, use @ref PWM_STATE
+ * @param negative_brake_state PWM negative channel state when brake, use @ref PWM_STATE
+ * @param dead_time PWM channel dead time
+ */
+struct bflb_pwm_v2_channel_config_s {
+ uint8_t positive_polarity;
+ uint8_t negative_polarity;
+ uint8_t positive_stop_state;
+ uint8_t negative_stop_state;
+ uint8_t positive_brake_state;
+ uint8_t negative_brake_state;
+ uint8_t dead_time;
+};
+
+/**
+ * @brief PWM configuration structure
+ *
+ * @param clk_source PWM clock source, use @ref BFLB_SYSTEM_CLOCK
+ * @param clk_div PWM clock dividor, should be in 1~65535
+ * @param period PWM period count, should be in 2~65535
+ */
+struct bflb_pwm_v2_config_s {
+ uint8_t clk_source;
+ uint16_t clk_div;
+ uint16_t period;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize pwm.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save pwm config
+ */
+void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config_s *config);
+
+/**
+ * @brief Deinitialize pwm.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_pwm_v2_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Start pwm output.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_pwm_v2_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop pwm output.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_pwm_v2_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Set pwm period to change pwm frequence. Frequcence(hz) = pwm source clock /div/period.
+ *
+ * @param [in] dev device handle
+ * @param [in] period pwm period
+ */
+void bflb_pwm_v2_set_period(struct bflb_device_s *dev, uint16_t period);
+
+/**
+ * @brief Get pwm frequcency.
+ *
+ * @param [in] dev device handle
+ * @return frequcency
+ */
+float bflb_pwm_v2_get_frequency(struct bflb_device_s *dev);
+
+/**
+ * @brief Config pwm channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] config pointer to save pwm channel config
+ */
+void bflb_pwm_v2_channel_init(struct bflb_device_s *dev, uint8_t ch, struct bflb_pwm_v2_channel_config_s *config);
+
+/**
+ * @brief Set pwm dutycycle. Dutycycle(%) = (high_threhold - low_threhold)/period * 100%.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] low_threhold pwm low threhold
+ * @param [in] high_threhold pwm high threhold
+ */
+void bflb_pwm_v2_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
+
+/**
+ * @brief Start pwm positive output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_positive_start(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Start pwm negative output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_negative_start(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Stop pwm positive output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_positive_stop(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Stop pwm negative output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_negative_stop(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Enable pwm interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_en interrupt type
+ * @param [in] enable true means enable, otherwise disable
+ */
+void bflb_pwm_v2_int_enable(struct bflb_device_s *dev, uint32_t int_en, bool enable);
+
+/**
+ * @brief Get pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref PWM_INTSTS
+ */
+uint32_t bflb_pwm_v2_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref PWM_INTCLR
+ */
+void bflb_pwm_v2_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Control pwm feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref PWM_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_rtc.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_rtc.h
new file mode 100644
index 00000000..a8fa56d7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_rtc.h
@@ -0,0 +1,49 @@
+#ifndef _BFLB_RTC_H
+#define _BFLB_RTC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+#define BFLB_RTC_SEC2TIME(s) (s * 32768)
+#define BFLB_RTC_TIME2SEC(time) (time / 32768)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set rtc alarming time.
+ *
+ * @param [in] dev device handle
+ * @param [in] time alarming time, unit is (1/32768 s)
+ */
+void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time);
+
+/**
+ * @brief Get rtc current time.
+ *
+ * @param [in] dev device handle
+ * @return current rtc running time
+ */
+uint64_t bflb_rtc_get_time(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sdio2.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sdio2.h
new file mode 100644
index 00000000..e5cfc65b
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sdio2.h
@@ -0,0 +1,71 @@
+/**
+ ******************************************************************************
+ * @file bflb_sdio2.h
+ * @version V1.0
+ * @date 2022-09-27
+ * @brief This file is the low hardware abstraction layer file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2022 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _BFLB_SDIO2_H
+#define _BFLB_SDIO2_H
+
+//#define BFLB_SDIO2_ENUM 1
+
+#ifndef BFLB_SDIO2_ENUM
+#include "bflb_core.h"
+#else
+#include "stdio.h"
+#include "stdint.h"
+struct bflb_device_s {
+ const char *name;
+ uint32_t reg_base;
+ uint8_t irq_num;
+ uint8_t idx;
+ uint8_t sub_idx;
+ uint8_t dev_type;
+ void *user_data;
+};
+#endif
+
+/* SDIO2 buffer size */
+#define SDIO2_BYTE_PER_BUF (1024 * 2)
+#define SDIO2_MAX_PORT_NUM 16
+#define SDIO2_MAX_FUNC 1
+
+int bflb_sdio2_init(struct bflb_device_s *dev);
+int bflb_sdio2_check_host_ready(struct bflb_device_s *dev);
+uint32_t bflb_sdio2_get_block_size(struct bflb_device_s *dev);
+int bflb_sdio2_tx_rx_queue_init(struct bflb_device_s *dev);
+int bflb_sdio2_send_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int len);
+int bflb_sdio2_recv_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int *len);
+void bflb_sdio2_isr(int irq, void *arg);
+
+#endif /* _BFLB_SDIO3_H */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_aes.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_aes.h
new file mode 100644
index 00000000..6ff8e014
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_aes.h
@@ -0,0 +1,247 @@
+#ifndef _BFLB_SEC_AES_H
+#define _BFLB_SEC_AES_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup SEC_AES
+ * @{
+ */
+
+/** @defgroup AES_MODE aes mode definition
+ * @{
+ */
+#define AES_MODE_ECB 0
+#define AES_MODE_CTR 1
+#define AES_MODE_CBC 2
+#define AES_MODE_XTS 3
+/**
+ * @}
+ */
+
+/** @defgroup AES_LINK_KEYBITS aes link mode keybits definition
+ * @{
+ */
+#define AES_LINK_KEY_128BITS 0
+#define AES_LINK_KEY_192BITS 2
+#define AES_LINK_KEY_256BITS 1
+#define AES_LINK_KEY_DOUBLE_128BITS 3
+/**
+ * @}
+ */
+
+#define AES_LINK_XTS_MODE1 0
+#define AES_LINK_XTS_MODE2 1
+
+struct bflb_aes_link_s {
+ uint32_t : 3; /*!< [2:0]Reserved */
+ uint32_t aes_key : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */
+ uint32_t aes_dec_en : 1; /*!< [5]Encode or decode */
+ uint32_t aes_newkey_dis : 1; /*!< [6]Use new key or use same key as last one */
+ uint32_t aes_hwkey_en : 1; /*!< [7]Enable or disable using hardware hey */
+ uint32_t : 1; /*!< [8]Reserved */
+ uint32_t aes_intclr : 1; /*!< [9]Clear interrupt */
+ uint32_t aes_intset : 1; /*!< [10]Set interrupt */
+ uint32_t : 1; /*!< [11]Reserved */
+ uint32_t aes_mode : 2; /*!< [13:12]ECB/CTR/CBC mode select */
+ uint32_t aes_newiv_dis : 1; /*!< [14]Use new iv or use same iv as last one */
+ uint32_t aes_xts : 1; /*!< [15]XTS mode select */
+ uint32_t aes_msglen : 16; /*!< [31:16]Number of 128-bit block */
+ uint32_t aes_srcaddr; /*!< Message source address */
+ uint32_t aes_dstaddr; /*!< Message destination address */
+ uint32_t aes_iv0; /*!< Big endian initial vector(MSB) */
+ uint32_t aes_iv1; /*!< Big endian initial vector */
+ uint32_t aes_iv2; /*!< Big endian initial vector */
+ uint32_t aes_iv3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */
+ uint32_t aes_key0; /*!< Big endian aes key(aes-128/256 key MSB) */
+ uint32_t aes_key1; /*!< Big endian aes key */
+ uint32_t aes_key2; /*!< Big endian aes key */
+ uint32_t aes_key3; /*!< Big endian aes key(aes-128 key LSB) */
+ uint32_t aes_key4; /*!< Big endian aes key */
+ uint32_t aes_key5; /*!< Big endian aes key */
+ uint32_t aes_key6; /*!< Big endian aes key */
+ uint32_t aes_key7; /*!< Big endian aes key(aes-256 key LSB) */
+} __attribute__((aligned(4)));
+
+struct bflb_aes_xts_link_s {
+ uint32_t : 3; /*!< [2:0]Reserved */
+ uint32_t aes_key : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */
+ uint32_t aes_dec_en : 1; /*!< [5]Encode or decode */
+ uint32_t aes_newkey_dis : 1; /*!< [6]Use new key or use same key as last one */
+ uint32_t aes_hwkey_en : 1; /*!< [7]Enable or disable using hardware hey */
+ uint32_t : 1; /*!< [8]Reserved */
+ uint32_t aes_intclr : 1; /*!< [9]Clear interrupt */
+ uint32_t aes_intset : 1; /*!< [10]Set interrupt */
+ uint32_t : 1; /*!< [11]Reserved */
+ uint32_t aes_mode : 2; /*!< [13:12]ECB/CTR/CBC mode select */
+ uint32_t aes_newiv_dis : 1; /*!< [14]Use new iv or use same iv as last one */
+ uint32_t aes_xts : 1; /*!< [15]XTS mode select */
+ uint32_t aes_msglen : 16; /*!< [31:16]Number of 128-bit block */
+ uint32_t aes_srcaddr; /*!< Message source address */
+ uint32_t aes_dstaddr; /*!< Message destination address */
+ uint32_t aes_iv0; /*!< Big endian initial vector(MSB) */
+ uint32_t aes_iv1; /*!< Big endian initial vector */
+ uint32_t aes_iv2; /*!< Big endian initial vector */
+ uint32_t aes_iv3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */
+ uint32_t aes_key10; /*!< Big endian aes key(aes-128/256 key MSB) */
+ uint32_t aes_key11; /*!< Big endian aes key1 */
+ uint32_t aes_key12; /*!< Big endian aes key1 */
+ uint32_t aes_key13; /*!< Big endian aes key1(aes-128 key LSB) */
+ uint32_t aes_key14; /*!< Big endian aes key1 */
+ uint32_t aes_key15; /*!< Big endian aes key1 */
+ uint32_t aes_key16; /*!< Big endian aes key1 */
+ uint32_t aes_key17; /*!< Big endian aes key1(aes-256 key LSB) */
+ uint32_t : 16; /*!< [15:0]Reserved */
+ uint32_t aes_unitlen : 16; /*!< [31:16]Big endian aes unit len */
+ uint32_t aes_key20; /*!< Big endian aes key2(aes-128/256 key MSB) */
+ uint32_t aes_key21; /*!< Big endian aes key2 */
+ uint32_t aes_key22; /*!< Big endian aes key2 */
+ uint32_t aes_key23; /*!< Big endian aes key2(aes-128 key LSB) */
+ uint32_t aes_key24; /*!< Big endian aes key2 */
+ uint32_t aes_key25; /*!< Big endian aes key2 */
+ uint32_t aes_key26; /*!< Big endian aes key2 */
+ uint32_t aes_key27; /*!< Big endian aes key2(aes-256 key LSB) */
+} __attribute__((aligned(4)));
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable aes.
+ *
+ * @param [in] dev
+ */
+void bflb_aes_init(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable aes.
+ *
+ * @param [in] dev
+ */
+void bflb_aes_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Set aes hardware key.
+ *
+ * @param [in] keysel hardware key mode in efuse table
+ */
+void bflb_aes_set_hwkey(uint8_t keysel);
+
+/**
+ * @brief Set aes hardware key source.
+ *
+ * @param [in] dev device handle
+ * @param [in] source hardware key source
+ */
+void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source);
+
+/**
+ * @brief Set aes mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] mode aes mode, use @ref AES_MODE
+ */
+void bflb_aes_set_mode(struct bflb_device_s *dev, uint8_t mode);
+
+/**
+ * @brief Set aes key.
+ *
+ * @param [in] dev device handle
+ * @param [in] key pointer to aes key, if NULL, means use hardware key
+ * @param [in] keybits aes keybits, can be 128/192/256
+ */
+void bflb_aes_setkey(struct bflb_device_s *dev, const uint8_t *key, uint16_t keybits);
+
+/**
+ * @brief Perform aes encrypt.
+ *
+ * @param [in] dev device handle
+ * @param [in] input pointer to plaintext
+ * @param [in] iv input iv, if NULL, means use last iv.
+ * @param [in] output pointer to ciphertext
+ * @param [in] len encrypt length, muse be multiple of 16
+ * @return A negated errno value on failure.
+ */
+int bflb_aes_encrypt(struct bflb_device_s *dev,
+ const uint8_t *input,
+ const uint8_t *iv,
+ uint8_t *output,
+ uint32_t len);
+
+/**
+ * @brief Perform aes decrypt.
+ *
+ * @param [in] dev device handle
+ * @param [in] input pointer to ciphertext
+ * @param [in] iv input iv, if NULL, means use last iv.
+ * @param [in] output pointer to plaintext
+ * @param [in] len decrypt length, muse be multiple of 16
+ * @return A negated errno value on failure.
+ */
+int bflb_aes_decrypt(struct bflb_device_s *dev,
+ const uint8_t *input,
+ const uint8_t *iv,
+ uint8_t *output,
+ uint32_t len);
+
+/**
+ * @brief Enable aes link mode.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_aes_link_init(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable aes link mode.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_aes_link_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Perform encrypt or decrypt with link mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] link_addr link struct pointer address, must be located in 0x2xxxxxxx
+ * @param [in] input pointer to plaintext or ciphertext
+ * @param [in] output pointer to plaintext or ciphertext
+ * @param [in] len update length, muse be multiple of 16
+ * @return A negated errno value on failure.
+ */
+int bflb_aes_link_update(struct bflb_device_s *dev,
+ uint32_t link_addr,
+ const uint8_t *input,
+ uint8_t *output,
+ uint32_t len);
+
+/**
+ * @brief Enable aes in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_request_aes_access(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable aes in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_release_aes_access(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_dsa.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_dsa.h
new file mode 100644
index 00000000..ccce397b
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_dsa.h
@@ -0,0 +1,82 @@
+#ifndef _BFLB_SEC_DSA_H
+#define _BFLB_SEC_DSA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup SEC_DSA
+ * @{
+ */
+
+struct bflb_dsa_crt_s {
+ uint32_t *dP;
+ uint32_t *dQ;
+ uint32_t *qInv;
+ uint32_t *p;
+ uint32_t *invR_p;
+ uint32_t *primeN_p;
+ uint32_t *q;
+ uint32_t *invR_q;
+ uint32_t *primeN_q;
+};
+
+struct bflb_dsa_s {
+ uint32_t size;
+ uint32_t crtSize;
+ uint32_t *n;
+ uint32_t *e;
+ uint32_t *d;
+ struct bflb_dsa_crt_s crtCfg;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] size
+ * @return int
+ */
+int bflb_sec_dsa_init(struct bflb_dsa_s *handle, uint32_t size);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] hash
+ * @param [in] hashLenInWord
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_dsa_sign(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] hash
+ * @param [in] hashLenInWord
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_dsa_verify(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_ecdsa.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_ecdsa.h
new file mode 100644
index 00000000..d1cd6d4e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_ecdsa.h
@@ -0,0 +1,158 @@
+#ifndef _BFLB_SEC_ECDSA_H
+#define _BFLB_SEC_ECDSA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup SEC_ECDSA
+ * @{
+ */
+
+#define ECP_SECP256R1 0
+#define ECP_SECP256K1 1
+
+struct bflb_ecdsa_s {
+ uint8_t ecpId;
+ uint8_t pad[3];
+ uint32_t *privateKey;
+ uint32_t *publicKeyx;
+ uint32_t *publicKeyy;
+};
+
+struct bflb_ecdh_s {
+ uint8_t ecpId;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] id
+ * @return int
+ */
+int bflb_sec_ecdsa_init(struct bflb_ecdsa_s *handle, uint8_t id);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @return int
+ */
+int bflb_sec_ecdsa_deinit(struct bflb_ecdsa_s *handle);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] random_k
+ * @param [in] hash
+ * @param [in] hashLenInWord
+ * @param [in] r
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_ecdsa_sign(struct bflb_ecdsa_s *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] hash
+ * @param [in] hashLen
+ * @param [in] r
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_ecdsa_verify(struct bflb_ecdsa_s *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] private_key
+ * @return int
+ */
+int bflb_sec_ecdsa_get_private_key(struct bflb_ecdsa_s *handle, uint32_t *private_key);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] private_key
+ * @param [in] pRx
+ * @param [in] pRy
+ * @return int
+ */
+int bflb_sec_ecdsa_get_public_key(struct bflb_ecdsa_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] id
+ * @return int
+ */
+int bflb_sec_ecdh_init(struct bflb_ecdh_s *handle, uint8_t id);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @return int
+ */
+int bflb_sec_ecdh_deinit(struct bflb_ecdh_s *handle);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] pkX
+ * @param [in] pkY
+ * @param [in] private_key
+ * @param [in] pRx
+ * @param [in] pRy
+ * @return int
+ */
+int bflb_sec_ecdh_get_encrypt_key(struct bflb_ecdh_s *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] private_key
+ * @param [in] pRx
+ * @param [in] pRy
+ * @return int
+ */
+int bflb_sec_ecdh_get_public_key(struct bflb_ecdh_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+
+/**
+ * @brief
+ *
+ * @param [in] data
+ * @param [in] max_ref
+ * @param [in] size
+ * @return int
+ */
+int bflb_sec_ecc_get_random_value(uint32_t *data, uint32_t *max_ref, uint32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_irq.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_irq.h
new file mode 100644
index 00000000..52cdabc7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_irq.h
@@ -0,0 +1,53 @@
+#ifndef _BFLB_SEC_IRQ_H
+#define _BFLB_SEC_IRQ_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup SEC_IRQ
+ * @{
+ */
+
+#define BFLB_SEC_ENG_IRQ_TYPE_AES 0
+#define BFLB_SEC_ENG_IRQ_TYPE_SHA 1
+#define BFLB_SEC_ENG_IRQ_TYPE_PKA 2
+#define BFLB_SEC_ENG_IRQ_TYPE_TRNG 3
+#define BFLB_SEC_ENG_IRQ_TYPE_GMAC 4
+#define BFLB_SEC_ENG_IRQ_TYPE_CDET 5
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] sec_type
+ * @param [in] callback
+ * @param [in] arg
+ */
+void bflb_sec_irq_attach(uint8_t sec_type, void (*callback)(void *arg), void *arg);
+
+/**
+ * @brief
+ *
+ * @param [in] sec_type
+ */
+void bflb_sec_irq_detach(uint8_t sec_type);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_pka.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_pka.h
new file mode 100644
index 00000000..26f4681f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_pka.h
@@ -0,0 +1,285 @@
+#ifndef _BFLB_SEC_PKA_H
+#define _BFLB_SEC_PKA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup SEC_PKA
+ * @{
+ */
+
+#define SEC_ENG_PKA_REG_SIZE_8 1
+#define SEC_ENG_PKA_REG_SIZE_16 2
+#define SEC_ENG_PKA_REG_SIZE_32 3
+#define SEC_ENG_PKA_REG_SIZE_64 4
+#define SEC_ENG_PKA_REG_SIZE_96 5
+#define SEC_ENG_PKA_REG_SIZE_128 6
+#define SEC_ENG_PKA_REG_SIZE_192 7
+#define SEC_ENG_PKA_REG_SIZE_256 8
+#define SEC_ENG_PKA_REG_SIZE_384 9
+#define SEC_ENG_PKA_REG_SIZE_512 10
+
+#define SEC_ENG_PKA_OP_PPSEL 0x00
+#define SEC_ENG_PKA_OP_LMOD2N 0x11
+#define SEC_ENG_PKA_OP_LDIV2N 0x12
+#define SEC_ENG_PKA_OP_LMUL2N 0x13
+#define SEC_ENG_PKA_OP_LDIV 0x14
+#define SEC_ENG_PKA_OP_LSQR 0x15
+#define SEC_ENG_PKA_OP_LMUL 0x16
+#define SEC_ENG_PKA_OP_LSUB 0x17
+#define SEC_ENG_PKA_OP_LADD 0x18
+#define SEC_ENG_PKA_OP_LCMP 0x19
+#define SEC_ENG_PKA_OP_MDIV2 0x21
+#define SEC_ENG_PKA_OP_MINV 0x22
+#define SEC_ENG_PKA_OP_MEXP 0x23
+#define SEC_ENG_PKA_OP_MSQR 0x24
+#define SEC_ENG_PKA_OP_MMUL 0x25
+#define SEC_ENG_PKA_OP_MREM 0x26
+#define SEC_ENG_PKA_OP_MSUB 0x27
+#define SEC_ENG_PKA_OP_MADD 0x28
+#define SEC_ENG_PKA_OP_RESIZE 0x31
+#define SEC_ENG_PKA_OP_MOVDAT 0x32
+#define SEC_ENG_PKA_OP_NLIR 0x33
+#define SEC_ENG_PKA_OP_SLIR 0x34
+#define SEC_ENG_PKA_OP_CLIR 0x35
+#define SEC_ENG_PKA_OP_CFLIRI_BUFFER 0x36
+#define SEC_ENG_PKA_OP_CTLIRI_PLD 0x37
+#define SEC_ENG_PKA_OP_CFLIR_BUFFER 0x38
+#define SEC_ENG_PKA_OP_CTLIR_PLD 0x39
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void bflb_pka_init(struct bflb_device_s *dev);
+void bflb_pka_deinit(struct bflb_device_s *dev);
+
+void bflb_pka_lmod2n(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint16_t bit_shift,
+ uint8_t lastop);
+
+void bflb_pka_ldiv2n(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint16_t bit_shift,
+ uint8_t lastop);
+
+void bflb_pka_lmul2n(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint16_t bit_shift,
+ uint8_t lastop);
+
+void bflb_pka_ldiv(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_lsqr(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t lastop);
+
+void bflb_pka_lmul(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize,
+ uint8_t lastop);
+
+void bflb_pka_lsub(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize,
+ uint8_t lastop);
+
+void bflb_pka_ladd(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize,
+ uint8_t lastop);
+
+uint8_t bflb_pka_lcmp(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize);
+
+void bflb_pka_minv(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_mexp(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_msqr(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_mmul(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_mrem(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_msub(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_madd(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t s1_regindex,
+ uint8_t s1_regsize,
+ uint8_t s2_regindex,
+ uint8_t s2_regsize,
+ uint8_t lastop);
+
+void bflb_pka_regsize(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t lastop);
+
+void bflb_pka_movdat(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t lastop);
+
+void bflb_pka_nlir(struct bflb_device_s *dev,
+ uint8_t s0_regindex,
+ uint8_t s0_regsize,
+ uint8_t d0_regindex,
+ uint8_t d0_regsize,
+ uint8_t lastop);
+
+void bflb_pka_slir(struct bflb_device_s *dev,
+ uint8_t regindex,
+ uint8_t regsize,
+ uint32_t data,
+ uint8_t lastop);
+
+void bflb_pka_clir(struct bflb_device_s *dev,
+ uint8_t regindex,
+ uint8_t regsize,
+ uint16_t size,
+ uint8_t lastop);
+
+void bflb_pka_write(struct bflb_device_s *dev,
+ uint8_t regindex,
+ uint8_t regsize,
+ const uint32_t *data,
+ uint16_t size,
+ uint8_t lastop);
+
+void bflb_pka_read(struct bflb_device_s *dev,
+ uint8_t regindex,
+ uint8_t regsize,
+ uint32_t *data,
+ uint16_t size);
+
+void bflb_pka_gf2mont(struct bflb_device_s *dev,
+ uint8_t s_regindex,
+ uint8_t s_regsize,
+ uint8_t d_regindex,
+ uint8_t d_regsize,
+ uint8_t t_regindex,
+ uint8_t t_regsize,
+ uint8_t p_regindex,
+ uint8_t p_regsize,
+ uint32_t size);
+
+void bflb_pka_mont2gf(struct bflb_device_s *dev,
+ uint8_t s_regindex,
+ uint8_t s_regsize,
+ uint8_t d_regindex,
+ uint8_t d_regsize,
+ uint8_t invt_regindex,
+ uint8_t invt_regsize,
+ uint8_t t_regindex,
+ uint8_t t_regsize,
+ uint8_t p_regindex,
+ uint8_t p_regsize);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_sha.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_sha.h
new file mode 100644
index 00000000..3053de58
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_sha.h
@@ -0,0 +1,318 @@
+#ifndef _BFLB_SEC_SHA_H
+#define _BFLB_SEC_SHA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup SEC_SHA
+ * @{
+ */
+
+#define SHA_MODE_SHA256 0
+#define SHA_MODE_SHA224 1
+#define SHA_MODE_SHA1 2
+#define SHA_MODE_SHA512 4
+#define SHA_MODE_SHA384 5
+#define SHA_MODE_SHA512T224 6
+#define SHA_MODE_SHA512T256 7
+
+struct bflb_sha1_ctx_s {
+ uint32_t total[2]; /*!< Number of bytes processed */
+ __attribute__((aligned(32))) uint8_t sha_buf[64]; /*!< Data not processed but in this temp buffer */
+ __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+ uint8_t sha_feed; /*!< Sha has feed data */
+};
+
+struct bflb_sha256_ctx_s {
+ uint32_t total[2]; /*!< Number of bytes processed */
+ __attribute__((aligned(32))) uint8_t sha_buf[64]; /*!< Data not processed but in this temp buffer */
+ __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+ uint8_t sha_feed; /*!< Sha has feed data */
+};
+
+struct bflb_sha512_ctx_s {
+ uint64_t total[2]; /*!< Number of bytes processed */
+ __attribute__((aligned(32))) uint8_t sha_buf[128]; /*!< Data not processed but in this temp buffer */
+ __attribute__((aligned(32))) uint8_t sha_padding[128]; /*!< Padding data */
+ uint8_t sha_feed; /*!< Sha has feed data */
+};
+
+struct bflb_sha1_link_ctx_s {
+ uint32_t total[2]; /*!< Number of bytes processed */
+ __attribute__((aligned(32))) uint8_t sha_buf[64]; /*!< Data not processed but in this temp buffer */
+ __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+ uint32_t link_addr; /*!< Link configure address */
+};
+
+struct bflb_sha256_link_ctx_s {
+ uint32_t total[2]; /*!< Number of bytes processed */
+ __attribute__((aligned(32))) uint8_t sha_buf[64]; /*!< Data not processed but in this temp buffer */
+ __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+ uint32_t link_addr; /*!< Link configure address */
+};
+
+struct bflb_sha512_link_ctx_s {
+ uint64_t total[2]; /*!< Number of bytes processed */
+ __attribute__((aligned(32))) uint8_t sha_buf[128]; /*!< Data not processed but in this temp buffer */
+ __attribute__((aligned(32))) uint8_t sha_padding[128]; /*!< Padding data */
+ uint32_t link_addr; /*!< Link configure address */
+};
+
+struct bflb_sha_link_s {
+ uint32_t : 2; /*!< [1:0]Reserved */
+ uint32_t sha_mode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */
+ uint32_t : 1; /*!< [5]Reserved */
+ uint32_t sha_newhash_dis : 1; /*!< [6]New hash or accumulate last hash */
+ uint32_t : 2; /*!< [8:7]Reserved */
+ uint32_t sha_intclr : 1; /*!< [9]Clear interrupt */
+ uint32_t sha_intset : 1; /*!< [10]Set interrupt */
+ uint32_t : 1; /*!< [11]Reserved */
+ uint32_t sha_mode_ext : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */
+ uint32_t : 2; /*!< [15:14]Reserved */
+ uint32_t sha_msglen : 16; /*!< [31:16]Number of 512-bit block */
+ uint32_t sha_srcaddr; /*!< Message source address */
+ uint32_t result[16]; /*!< Result of SHA */
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mode
+ */
+void bflb_sha_init(struct bflb_device_s *dev, uint8_t mode);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ */
+void bflb_sha1_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ */
+void bflb_sha256_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ */
+void bflb_sha512_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, const uint8_t *input, uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, const uint8_t *input, uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint64_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_sha_link_init(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_sha_link_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] link
+ */
+void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_link_ctx_s *ctx, struct bflb_sha_link_s *link);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] link
+ */
+void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_link_ctx_s *ctx, struct bflb_sha_link_s *link);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] link
+ */
+void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_link_ctx_s *ctx, struct bflb_sha_link_s *link);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha1_link_update(struct bflb_device_s *dev,
+ struct bflb_sha1_link_ctx_s *ctx,
+ const uint8_t *input,
+ uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha256_link_update(struct bflb_device_s *dev,
+ struct bflb_sha256_link_ctx_s *ctx,
+ const uint8_t *input,
+ uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha512_link_update(struct bflb_device_s *dev,
+ struct bflb_sha512_link_ctx_s *ctx,
+ const uint8_t *input,
+ uint64_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha1_link_finish(struct bflb_device_s *dev,
+ struct bflb_sha1_link_ctx_s *ctx,
+ uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha256_link_finish(struct bflb_device_s *dev,
+ struct bflb_sha256_link_ctx_s *ctx,
+ uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha512_link_finish(struct bflb_device_s *dev,
+ struct bflb_sha512_link_ctx_s *ctx,
+ uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_group0_request_sha_access(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_group0_release_sha_access(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_trng.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_trng.h
new file mode 100644
index 00000000..a7107030
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_sec_trng.h
@@ -0,0 +1,69 @@
+#ifndef _BFLB_SEC_TRNG_H
+#define _BFLB_SEC_TRNG_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup TRNG
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Read trng data.
+ *
+ * @param [in] dev device handle
+ * @param [in] data pointer to trng data
+ * @return A negated errno value on failure.
+ */
+int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]);
+
+/**
+ * @brief Read trng data with custom length.
+ *
+ * @param [in] data pointer to trng data
+ * @param [in] len length to read
+ * @return A negated errno value on failure.
+ */
+int bflb_trng_readlen(uint8_t *data, uint32_t len);
+
+/**
+ * @brief Get trng data.
+ *
+ * @return trng data with word
+ */
+long random(void);
+
+/**
+ * @brief Enable trng in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_request_trng_access(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable trng in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_release_trng_access(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_spi.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_spi.h
new file mode 100644
index 00000000..237fbd6f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_spi.h
@@ -0,0 +1,273 @@
+#ifndef _BFLB_SPI_H
+#define _BFLB_SPI_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+#if defined(BL602) || defined(BL702)
+#define SPI_FIFO_WORD_NUM_MAX 4
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 0
+#elif defined(BL606P) || defined(BL808)
+#define SPI_FIFO_BYTE_NUM_MAX 32
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 1
+#elif defined(BL616) || defined(BL628)
+#define SPI_FIFO_BYTE_NUM_MAX 32
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 1
+#elif defined(BL702L)
+#define SPI_FIFO_BYTE_NUM_MAX 16
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 1
+#else
+#error "unknown device"
+#endif
+
+/** @defgroup SPI_ROLE spi role definition
+ * @{
+ */
+#define SPI_ROLE_MASTER 0
+#define SPI_ROLE_SLAVE 1
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MODE spi mode definition
+ * @{
+ */
+#define SPI_MODE0 0 /* CPOL=0 CHPHA=0 */
+#define SPI_MODE1 1 /* CPOL=0 CHPHA=1 */
+#define SPI_MODE2 2 /* CPOL=1 CHPHA=0 */
+#define SPI_MODE3 3 /* CPOL=1 CHPHA=1 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_DATA_WIDTH spi data width definition
+ * @{
+ */
+#define SPI_DATA_WIDTH_8BIT 1
+#define SPI_DATA_WIDTH_16BIT 2
+#define SPI_DATA_WIDTH_24BIT 3
+#define SPI_DATA_WIDTH_32BIT 4
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BIT_ORDER spi bit order definition
+ * @{
+ */
+#define SPI_BIT_LSB 1
+#define SPI_BIT_MSB 0
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BYTE_ORDER spi byte order definition
+ * @{
+ */
+#define SPI_BYTE_LSB 0
+#if !defined(BL602) && !defined(BL702)
+#define SPI_BYTE_MSB 1
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup SPI_INTSTS spi interrupt status definition
+ * @{
+ */
+#define SPI_INTSTS_TC (1 << 0)
+#define SPI_INTSTS_TX_FIFO (1 << 1)
+#define SPI_INTSTS_RX_FIFO (1 << 2)
+#define SPI_INTSTS_SLAVE_TIMEOUT (1 << 3)
+#define SPI_INTSTS_SLAVE_TX_UNDERRUN (1 << 4)
+#define SPI_INTSTS_FIFO_ERR (1 << 5)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_INTCLR spi interrupt clear definition
+ * @{
+ */
+#define SPI_INTCLR_TC (1 << 16)
+#define SPI_INTCLR_SLAVE_TIMEOUT (1 << 19)
+#define SPI_INTCLR_SLAVE_TX_UNDERRUN (1 << 20)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CMD spi feature control cmd definition
+ * @{
+ */
+#define SPI_CMD_SET_DATA_WIDTH (0x01)
+#define SPI_CMD_GET_DATA_WIDTH (0x02)
+#define SPI_CMD_CLEAR_TX_FIFO (0x03)
+#define SPI_CMD_CLEAR_RX_FIFO (0x04)
+#define SPI_CMD_SET_CS_INTERVAL (0x05)
+#define SPI_CMD_RX_IGNORE (0x06)
+/**
+ * @}
+ */
+
+/**
+ * @brief SPI configuration structure
+ *
+ * @param freq SPI frequence, should be less than spi_clk/2
+ * @param role SPI role, use @ref SPI_ROLE
+ * @param mode SPI mode, use @ref SPI_MODE
+ * @param data_width SPI data width, use @ref SPI_DATA_WIDTH
+ * @param bit_order SPI bit order, use @ref SPI_BIT_ORDER
+ * @param byte_order SPI byte order, use @ref SPI_BYTE_ORDER
+ * @param tx_fifo_threshold SPI tx fifo threshold, should be less than 4
+ * @param rx_fifo_threshold SPI rx fifo threshold, should be less than 4
+ */
+struct bflb_spi_config_s {
+ uint32_t freq;
+ uint8_t role;
+ uint8_t mode;
+ uint8_t data_width;
+ uint8_t bit_order;
+ uint8_t byte_order;
+ uint8_t tx_fifo_threshold;
+ uint8_t rx_fifo_threshold;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize spi.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save spi config
+ */
+void bflb_spi_init(struct bflb_device_s *dev, const struct bflb_spi_config_s *config);
+
+/**
+ * @brief Deinitialize spi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_spi_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable spi tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_spi_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable spi rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_spi_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Send and receive one data on spi.
+ *
+ * @param [in] dev device handle
+ * @param [in] data data to send
+ * @return receive data
+ */
+uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t data);
+
+/**
+ * @brief Send and receive a block of data on spi.
+ *
+ * @param [in] dev device handle
+ * @param [in] txbuffer pointer to send buffer
+ * @param [in] rxbuffer pointer to receive buffer
+ * @param [in] nbytes bytes to send
+ * @return A negated errno value on failure.
+ */
+int bflb_spi_poll_exchange(struct bflb_device_s *dev, const void *txbuffer, void *rxbuffer, size_t nbytes);
+
+/**
+ * @brief Check if spi is busy.
+ *
+ * @param [in] dev device handle
+ * @return true means busy, otherwise not.
+ */
+bool bflb_spi_isbusy(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable spi rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable spi rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable spi transfer done interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable spi error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get spi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref SPI_INTSTS
+ */
+uint32_t bflb_spi_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear spi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref SPI_INTCLR
+ */
+void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Control spi feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref SPI_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_spi_psram.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_spi_psram.h
new file mode 100644
index 00000000..33969d84
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_spi_psram.h
@@ -0,0 +1,152 @@
+/**
+ ******************************************************************************
+ * @file bflb_spi_psram.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BFLB_SPI_PSRAM_H__
+#define __BFLB_SPI_PSRAM_H__
+
+#include "sf_ctrl_reg.h"
+#include "bflb_common.h"
+#include "bflb_sf_ctrl.h"
+
+/** @addtogroup BFLB_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup PSRAM
+ * @{
+ */
+
+/** @defgroup PSRAM_Public_Types
+ * @{
+ */
+
+/**
+ * @brief Psram drive strength type definition
+ */
+
+#define PSRAM_DRIVE_STRENGTH_50_OHMS 0 /*!< Drive strength 50 ohms(default) */
+#define PSRAM_DRIVE_STRENGTH_100_OHMS 1 /*!< Drive strength 100 ohms */
+#define PSRAM_DRIVE_STRENGTH_200_OHMS 2 /*!< Drive strength 200 ohms */
+
+/**
+ * @brief Psram burst length size type definition
+ */
+#define PSRAM_BURST_LENGTH_16_BYTES 0 /*!< Burst Length 16 bytes */
+#define PSRAM_BURST_LENGTH_32_BYTES 1 /*!< Burst Length 32 bytes */
+#define PSRAM_BURST_LENGTH_64_BYTES 2 /*!< Burst Length 64 bytes */
+#define PSRAM_BURST_LENGTH_512_BYTES 3 /*!< Burst Length 512 bytes(default) */
+
+/**
+ * @brief Psram ctrl mode type definition
+ */
+#define PSRAM_SPI_CTRL_MODE 0 /*!< Psram SPI ctrl mode */
+#define PSRAM_QPI_CTRL_MODE 1 /*!< Psram QPI ctrl mode */
+
+/**
+ * @brief Psram ctrl configuration structure type definition
+ */
+struct spi_psram_cfg_type {
+ uint8_t read_id_cmd; /*!< Read ID command */
+ uint8_t read_id_dmy_clk; /*!< Read ID command dummy clock */
+ uint8_t burst_toggle_cmd; /*!< Burst toggle length command */
+ uint8_t reset_enable_cmd; /*!< Psram reset enable command */
+ uint8_t reset_cmd; /*!< Psram reset command */
+ uint8_t enter_quad_mode_cmd; /*!< Psram enter quad mode command */
+ uint8_t exit_quad_mode_cmd; /*!< Psram exit quad mode command */
+ uint8_t read_reg_cmd; /*!< Read register command */
+ uint8_t read_reg_dmy_clk; /*!< Read register command dummy clock */
+ uint8_t write_reg_cmd; /*!< Write register command */
+ uint8_t read_cmd; /*!< Psram read command */
+ uint8_t read_dmy_clk; /*!< Psram read command dummy clock */
+ uint8_t f_read_cmd; /*!< Psram fast read command */
+ uint8_t f_read_dmy_clk; /*!< Psram fast read command dummy clock */
+ uint8_t f_read_quad_cmd; /*!< Psram fast read quad command */
+ uint8_t f_read_quad_dmy_clk; /*!< Psram fast read quad command dummy clock */
+ uint8_t write_cmd; /*!< Psram write command */
+ uint8_t quad_write_cmd; /*!< Psram quad write command */
+ uint16_t page_size; /*!< Psram page size */
+#if defined(BL702L)
+ uint8_t burst_toggle_en; /*!< Psram burst toggle mode enable */
+#endif
+ uint8_t ctrl_mode; /*!< Psram ctrl mode */
+ uint8_t drive_strength; /*!< Psram drive strength */
+ uint8_t burst_length; /*!< Psram burst length size */
+};
+
+/*@} end of group PSRAM_Public_Types */
+
+/** @defgroup PSRAM_Public_Constants
+ * @{
+ */
+
+/*@} end of group PSRAM_Public_Constants */
+
+/** @defgroup PSRAM_Public_Macros
+ * @{
+ */
+
+/*@} end of group PSRAM_Public_Macros */
+
+/** @defgroup PSRAM_Public_Functions
+ * @{
+ */
+
+/**
+ * @brief PSRAM Functions
+ */
+void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg,
+ struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg);
+void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
+void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
+int bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg);
+int bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg);
+void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data);
+int bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg);
+int bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg);
+int bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
+int bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
+int bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint32_t len);
+int bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint8_t wt_en,
+ uint8_t wb_en, uint8_t wa_en);
+int bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
+int bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
+
+/*@} end of group PSRAM_Public_Functions */
+
+/*@} end of group PSRAM */
+
+/*@} end of group BFLB_Peripheral_Driver */
+
+#endif /* __BFLB_SPI_PSRAM_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_timer.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_timer.h
new file mode 100644
index 00000000..43a09d2e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_timer.h
@@ -0,0 +1,204 @@
+#ifndef _BFLB_TIMER_H
+#define _BFLB_TIMER_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup TIMER
+ * @{
+ */
+
+/** @defgroup TIMER_CLK_SOURCE timer clock source definition
+ * @{
+ */
+#if !defined(BL702L)
+#define TIMER_CLKSRC_BCLK 0
+#endif
+#define TIMER_CLKSRC_32K 1
+#define TIMER_CLKSRC_1K 2
+#define TIMER_CLKSRC_XTAL 3
+#if !defined(BL702) && !defined(BL602)
+#define TIMER_CLKSRC_GPIO 4
+#endif
+#define TIMER_CLKSRC_NO 5
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_COUNTER_MODE timer counter mode definition
+ * @{
+ */
+#define TIMER_COUNTER_MODE_PROLOAD 0
+#define TIMER_COUNTER_MODE_UP 1
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_COMP_ID timer compare id definition
+ * @{
+ */
+#define TIMER_COMP_ID_0 0
+#define TIMER_COMP_ID_1 1
+#define TIMER_COMP_ID_2 2
+#define TIMER_COMP_NONE 3
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_CAPTURE_POLARITY timer capture polarity definition
+ * @{
+ */
+#define TIMER_CAPTURE_POLARITY_POSITIVE 0
+#define TIMER_CAPTURE_POLARITY_NEGATIVE 1
+/**
+ * @}
+ */
+
+/**
+ * @brief TIMER configuration structure
+ *
+ * @param counter_mode Timer counter mode, use @ref TIMER_COUNTER_MODE
+ * @param clock_source Timer clock source, use @ref TIMER_CLK_SOURCE
+ * @param clock_div Timer clock divison value, from 0 to 255
+ * @param trigger_comp_id Timer count register preload trigger source slelect, use @ref TIMER_COMP_ID
+ * @param comp0_val Timer compare 0 value
+ * @param comp1_val Timer compare 1 value
+ * @param comp2_val Timer compare 2 value
+ * @param preload_val Timer preload value
+ */
+struct bflb_timer_config_s {
+ uint8_t counter_mode;
+ uint8_t clock_source;
+ uint8_t clock_div;
+ uint8_t trigger_comp_id;
+ uint32_t comp0_val;
+ uint32_t comp1_val;
+ uint32_t comp2_val;
+ uint32_t preload_val;
+};
+
+/**
+ * @brief TIMER capture configuration structure
+ *
+ * @param pin Timer capture pin
+ * @param polarity Timer capture polarity, use @ref TIMER_CAPTURE_POLARITY
+ */
+struct bflb_timer_capture_config_s {
+ uint8_t pin;
+ uint8_t polarity;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize timer.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save timer config
+ */
+void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s *config);
+
+/**
+ * @brief Deinitialize timer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_timer_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Start timer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_timer_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop timer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_timer_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Set timer preload value.
+ *
+ * @param [in] dev device handle
+ * @param [in] val preload value
+ */
+void bflb_timer_set_preloadvalue(struct bflb_device_s *dev, uint32_t val);
+
+/**
+ * @brief Set compare value of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @param [in] val compare value
+ */
+void bflb_timer_set_compvalue(struct bflb_device_s *dev, uint8_t cmp_no, uint32_t val);
+
+/**
+ * @brief Get compare value of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @return uint32_t
+ */
+uint32_t bflb_timer_get_compvalue(struct bflb_device_s *dev, uint8_t cmp_no);
+
+/**
+ * @brief Get timer counter value.
+ *
+ * @param [in] dev device handle
+ * @return counter value
+ */
+uint32_t bflb_timer_get_countervalue(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable timer interrupt of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_timer_compint_mask(struct bflb_device_s *dev, uint8_t cmp_no, bool mask);
+
+/**
+ * @brief Get timer interrupt status of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @return true mean yes, otherwise no.
+ */
+bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no);
+
+/**
+ * @brief Clear timer interrupt status of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ */
+void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no);
+
+#if !defined(BL702) || !defined(BL602)
+void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config);
+uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_uart.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_uart.h
new file mode 100644
index 00000000..555ef6ec
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_uart.h
@@ -0,0 +1,368 @@
+#ifndef _BFLB_UART_H
+#define _BFLB_UART_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/** @defgroup UART_DIRECTION uart direction enable definition
+ * @{
+ */
+#define UART_DIRECTION_TX (1 << 0)
+#define UART_DIRECTION_RX (1 << 1)
+#define UART_DIRECTION_TXRX (UART_DIRECTION_TX | UART_DIRECTION_RX)
+#define UART_DIRECTION_MASK UART_DIRECTION_TXRX
+/**
+ * @}
+ */
+
+/** @defgroup UART_DATABITS uart data bits definition
+ * @{
+ */
+#define UART_DATA_BITS_5 0
+#define UART_DATA_BITS_6 1
+#define UART_DATA_BITS_7 2
+#define UART_DATA_BITS_8 3
+/**
+ * @}
+ */
+
+/** @defgroup UART_STOPBITS uart stop bits definition
+ * @{
+ */
+#define UART_STOP_BITS_0_5 0
+#define UART_STOP_BITS_1 1
+#define UART_STOP_BITS_1_5 2
+#define UART_STOP_BITS_2 3
+/**
+ * @}
+ */
+
+/** @defgroup UART_PARITY uart parity definition
+ * @{
+ */
+#define UART_PARITY_NONE 0
+#define UART_PARITY_ODD 1
+#define UART_PARITY_EVEN 2
+#define UART_PARITY_MARK 3
+#define UART_PARITY_SPACE 4
+/**
+ * @}
+ */
+
+/** @defgroup UART_BITORDER uart bitorder definition
+ * @{
+ */
+#define UART_LSB_FIRST 0
+#define UART_MSB_FIRST 1
+/**
+ * @}
+ */
+
+/** @defgroup UART_FLOWCTRL uart flow ctrl definition
+ * @{
+ */
+#define UART_FLOWCTRL_NONE 0
+#define UART_FLOWCTRL_RTS (1 << 0)
+#define UART_FLOWCTRL_CTS (1 << 1)
+#define UART_FLOWCTRL_RTS_CTS (UART_FLOWCTRL_RTS | UART_FLOWCTRL_CTS)
+/**
+ * @}
+ */
+
+/** @defgroup UART_INTSTS uart interrupt status definition
+ * @{
+ */
+#define UART_INTSTS_TX_END (1 << 0)
+#define UART_INTSTS_RX_END (1 << 1)
+#define UART_INTSTS_TX_FIFO (1 << 2)
+#define UART_INTSTS_RX_FIFO (1 << 3)
+#define UART_INTSTS_RTO (1 << 4)
+#define UART_INTSTS_PCE (1 << 5)
+#define UART_INTSTS_TX_FER (1 << 6)
+#define UART_INTSTS_RX_FER (1 << 7)
+#if !defined(BL602)
+#define UART_INTSTS_RX_LSE (1 << 8)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_INTSTS_RX_BCR (1 << 9)
+#define UART_INTSTS_RX_ADS (1 << 10)
+#define UART_INTSTS_RX_AD5 (1 << 11)
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup UART_INTCLR uart interrupt clear definition
+ * @{
+ */
+#define UART_INTCLR_TX_END (1 << 0)
+#define UART_INTCLR_RX_END (1 << 1)
+#define UART_INTCLR_RTO (1 << 4)
+#define UART_INTCLR_PCE (1 << 5)
+#if !defined(BL602)
+#define UART_INTCLR_RX_LSE (1 << 8)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_INTCLR_RX_BCR (1 << 9)
+#define UART_INTCLR_RX_ADS (1 << 10)
+#define UART_INTCLR_RX_AD5 (1 << 11)
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup UART_CMD uart feature control cmd definition
+ * @{
+ */
+#define UART_CMD_SET_BAUD_RATE (0x01)
+#define UART_CMD_SET_DATA_BITS (0x02)
+#define UART_CMD_SET_STOP_BITS (0x03)
+#define UART_CMD_SET_PARITY_BITS (0x04)
+#define UART_CMD_CLR_TX_FIFO (0x05)
+#define UART_CMD_CLR_RX_FIFO (0x06)
+#define UART_CMD_SET_RTO_VALUE (0x07)
+#define UART_CMD_SET_RTS_VALUE (0x08)
+#define UART_CMD_GET_TX_FIFO_CNT (0x09)
+#define UART_CMD_GET_RX_FIFO_CNT (0x0a)
+#define UART_CMD_SET_AUTO_BAUD (0x0b)
+#define UART_CMD_GET_AUTO_BAUD (0x0c)
+#define UART_CMD_SET_BREAK_VALUE (0x0d)
+#define UART_CMD_SET_TX_LIN_VALUE (0x0e)
+#define UART_CMD_SET_RX_LIN_VALUE (0x0f)
+#define UART_CMD_SET_TX_RX_EN (0x10)
+#define UART_CMD_SET_TX_RS485_EN (0x11)
+#define UART_CMD_SET_TX_RS485_POLARITY (0x12)
+#define UART_CMD_SET_ABR_ALLOWABLE_ERROR (0x13)
+#define UART_CMD_SET_SW_RTS_CONTROL (0x14)
+#define UART_CMD_IR_CONFIG (0x15)
+#define UART_CMD_SET_TX_FREERUN (0x16)
+#define UART_CMD_SET_TX_END_INTERRUPT (0x17)
+#define UART_CMD_SET_RX_END_INTERRUPT (0x18)
+#define UART_CMD_SET_TX_TRANSFER_LEN (0x19)
+#define UART_CMD_SET_RX_TRANSFER_LEN (0x20)
+#define UART_CMD_SET_TX_EN (0x21)
+#define UART_CMD_SET_BCR_END_INTERRUPT (0x22)
+#define UART_CMD_GET_BCR_COUNT (0x23)
+/**
+ * @}
+ */
+
+#define UART_AUTO_BAUD_START 0
+#define UART_AUTO_BAUD_0X55 1
+
+struct bflb_uart_ir_config_s {
+ bool tx_en;
+ bool rx_en;
+ bool tx_inverse;
+ bool rx_inverse;
+ uint16_t tx_pluse_start;
+ uint16_t tx_pluse_stop;
+ uint16_t rx_pluse_start;
+};
+
+/**
+ * @brief UART configuration structure
+ *
+ * @param baudrate UART baudrate setting in bps,should be less than uart_clk/2
+ * @param direction UART direction, use @ref UART_DIRECTION
+ * @param data_bits UART data bits, use @ref UART_DATABITS
+ * @param stop_bits UART stop bits, use @ref UART_STOPBITS
+ * @param parity UART parity bit, use @ref UART_PARITY
+ * @param bit_order UART bit first, use @ref UART_BITORDER
+ * @param flow_ctrl UART flow control setting, use @ref UART_FLOWCTRL
+ * @param tx_fifo_threshold UART tx fifo threshold, should be less than 32.
+ * @param rx_fifo_threshold UART rx fifo threshold, should be less than 32.
+ */
+struct bflb_uart_config_s {
+ uint32_t baudrate;
+ uint8_t direction;
+ uint8_t data_bits;
+ uint8_t stop_bits;
+ uint8_t parity;
+ uint8_t bit_order;
+ uint8_t flow_ctrl;
+ uint8_t tx_fifo_threshold;
+ uint8_t rx_fifo_threshold;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize uart.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save uart config
+ */
+void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *config);
+
+/**
+ * @brief Deinitialize uart.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_uart_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable uart.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_uart_enable(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable uart.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_uart_disable(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable uart tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable uart rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Put one char on uart.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch char
+ * @return A negated errno value on failure.
+ */
+int bflb_uart_putchar(struct bflb_device_s *dev, int ch);
+
+/**
+ * @brief Get char from uart.
+ *
+ * @param [in] dev device handle
+ * @return A negated errno value on failure, otherwise received char.
+ */
+int bflb_uart_getchar(struct bflb_device_s *dev);
+
+/**
+ * @brief Put a block of data on uart.This is a poll api.
+ *
+ * @param [in] dev device handle
+ * @param [in] data pointer to save send data
+ * @param [in] len length to send
+ * @return A negated errno value on failure.
+ */
+int bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Get a block of data from uart. This is a asynchronous api.
+ *
+ * @param [in] dev device handle
+ * @param [in] data pointer to save received data
+ * @param [in] len max length wants to receive
+ * @return actual received length
+ */
+int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Check if there is free space in tx fifo.
+ *
+ * @param [in] dev device handle
+ * @return Return true if the tranmsit hardware is ready to send another byte
+ */
+bool bflb_uart_txready(struct bflb_device_s *dev);
+
+/**
+ * @brief Check if there is no data in tx fifo.
+ *
+ * @param [in] dev device handle
+ * @return Return true if all characters have been sent
+ */
+bool bflb_uart_txempty(struct bflb_device_s *dev);
+
+/**
+ * @brief Check if there is data in rx fifo.
+ *
+ * @param [in] dev device handle
+ * @return true means yes.Otherwise there is no data in rx fifo
+ */
+bool bflb_uart_rxavailable(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable uart tx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable uart rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable uart error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get uart interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref UART_INTSTS
+ */
+uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear uart interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref UART_INTCLR
+ */
+void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+
+/**
+ * @brief Control uart feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref UART_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/bflb_wdg.h b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_wdg.h
new file mode 100644
index 00000000..0110d503
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/bflb_wdg.h
@@ -0,0 +1,117 @@
+#ifndef _BFLB_WDG_H
+#define _BFLB_WDG_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+ * @{
+ */
+
+/** @addtogroup WDG
+ * @{
+ */
+
+#if !defined(BL702L)
+#define WDG_CLKSRC_BCLK 0
+#endif
+#define WDG_CLKSRC_32K 1
+#define WDG_CLKSRC_1K 2
+#define WDG_CLKSRC_XTAL 3
+#if !defined(BL702) && !defined(BL602)
+#define WDG_CLKSRC_GPIO 4
+#endif
+#define WDG_CLKSRC_NO 5
+
+/** @defgroup WDG_MODE Watch-dog reset/interrupt mode definition
+ * @{
+ */
+#define WDG_MODE_INTERRUPT 0
+#define WDG_MODE_RESET 1
+/**
+ * @}
+ */
+
+/**
+ * @brief WDG configuration structure
+ *
+ * @param clock_source Wdg clock source, use BFLB_SYSTEM_* definition
+ * @param clock_div Wdg clock divison value, from 0 to 255
+ * @param comp_val Wdg compare value
+ * @param mode Wdg reset/interrupt mode
+ */
+struct bflb_wdg_config_s {
+ uint8_t clock_source;
+ uint8_t clock_div;
+ uint16_t comp_val;
+ uint8_t mode;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize watchdog.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save watchdog config
+ */
+void bflb_wdg_init(struct bflb_device_s *dev, const struct bflb_wdg_config_s *config);
+
+/**
+ * @brief Start watchdog.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop watchdog.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Get watchdog counter value.
+ *
+ * @param [in] dev device handle
+ * @return counter value
+ */
+uint16_t bflb_wdg_get_countervalue(struct bflb_device_s *dev);
+
+/**
+ * @brief Set watchdog counter value.
+ *
+ * @param [in] dev device handle
+ * @param [in] counter value
+ */
+void bflb_wdg_set_countervalue(struct bflb_device_s *dev, uint16_t value);
+
+/**
+ * @brief Reset watchdog counter value.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_reset_countervalue(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear watchdog compare interrupt status.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_compint_clear(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/compiler/compiler_gcc.h b/arch/riscv32/bl808/src/drivers/lhal/include/compiler/compiler_gcc.h
new file mode 100644
index 00000000..82ff6b49
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/compiler/compiler_gcc.h
@@ -0,0 +1,68 @@
+#ifndef __COMPILER_GCC_H
+#define __COMPILER_GCC_H
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __ALWAYS_INLINE
+#define __ALWAYS_INLINE inline __attribute__((always_inline))
+#endif
+#ifndef __ALWAYS_STATIC_INLINE
+#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __UNUSED
+#define __UNUSED __attribute__((unused))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+#define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __IRQ
+#define __IRQ __attribute__((interrupt))
+#endif
+#ifndef __IRQ_ALIGN64
+#define __IRQ_ALIGN64 __attribute__((interrupt, aligned(64)))
+#endif
+#ifndef ALIGN4
+#define ALIGN4 __attribute((aligned(4)))
+#endif
+#ifndef __PACK_START
+#define __PACK_START
+#endif
+#ifndef __PACK_END
+#define __PACK_END __attribute__((packed))
+#endif
+#ifndef likely
+#define likely(x) __builtin_expect(!!(x), 1)
+#endif
+#ifndef unlikely
+#define unlikely(x) __builtin_expect(!!(x), 0)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef SECTION
+#define SECTION(x) __attribute__((section(x)))
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/compiler/compiler_ld.h b/arch/riscv32/bl808/src/drivers/lhal/include/compiler/compiler_ld.h
new file mode 100644
index 00000000..0ff7dd98
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/compiler/compiler_ld.h
@@ -0,0 +1,20 @@
+#ifndef __COMPILER_LD_H
+#define __COMPILER_LD_H
+
+#define ATTR_STRINGIFY(x) #x
+#define ATTR_TOSTRING(x) ATTR_STRINGIFY(x)
+#define ATTR_UNI_SYMBOL __FILE__ ATTR_TOSTRING(__LINE__)
+#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code." ATTR_UNI_SYMBOL)))
+#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const." ATTR_UNI_SYMBOL)))
+#define ATTR_TCM_SECTION __attribute__((section(".tcm_code." ATTR_UNI_SYMBOL)))
+#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const." ATTR_UNI_SYMBOL)))
+#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
+#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
+#define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram")))
+#define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram")))
+#define ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((section(".nocache_noinit_ram")))
+#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code")))
+#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data")))
+#define ATTR_FALLTHROUGH() __attribute__((fallthrough))
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/adc_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/adc_reg.h
new file mode 100644
index 00000000..3bdc3623
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/adc_reg.h
@@ -0,0 +1,268 @@
+/**
+ ******************************************************************************
+ * @file adc_reg.h
+ * @version V1.0
+ * @date 2022-08-05
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_ADC_H__
+#define __HARDWARE_ADC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+/* gpip base */
+#define GPIP_GPADC_CONFIG_OFFSET (0x0) /* gpadc_config */
+#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4) /* gpadc_dma_rdata */
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define GPIP_GPADC_PIR_TRAIN_OFFSET (0x20) /* gpadc_pir_train */
+#endif
+/* aon base */
+#define AON_GPADC_REG_CMD_OFFSET (0x90C) /* gpadc_reg_cmd */
+#define AON_GPADC_REG_CONFIG1_OFFSET (0x910) /* gpadc_reg_config1 */
+#define AON_GPADC_REG_CONFIG2_OFFSET (0x914) /* gpadc_reg_config2 */
+#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918) /* adc converation sequence 1 */
+#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C) /* adc converation sequence 2 */
+#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920) /* adc converation sequence 3 */
+#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924) /* adc converation sequence 4 */
+#define AON_GPADC_REG_STATUS_OFFSET (0x928) /* gpadc_reg_status */
+#define AON_GPADC_REG_ISR_OFFSET (0x92C) /* gpadc_reg_isr */
+#define AON_GPADC_REG_RESULT_OFFSET (0x930) /* gpadc_reg_result */
+#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) /* gpadc_reg_raw_result */
+#define AON_GPADC_REG_DEFINE_OFFSET (0x938) /* gpadc_reg_define */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : gpadc_config */
+#define GPIP_GPADC_DMA_EN (1 << 0U)
+#define GPIP_GPADC_FIFO_CLR (1 << 1U)
+#define GPIP_GPADC_FIFO_NE (1 << 2U)
+#define GPIP_GPADC_FIFO_FULL (1 << 3U)
+#define GPIP_GPADC_RDY (1 << 4U)
+#define GPIP_GPADC_FIFO_OVERRUN (1 << 5U)
+#define GPIP_GPADC_FIFO_UNDERRUN (1 << 6U)
+#if defined(BL702) || defined(BL702L)
+#define GPIP_GPADC_FIFO_RDY (1 << 7U)
+#endif
+#define GPIP_GPADC_RDY_CLR (1 << 8U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR (1 << 9U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR (1 << 10U)
+#define GPIP_GPADC_RDY_MASK (1 << 12U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK (1 << 13U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK (1 << 14U)
+#if defined(BL702) || defined(BL702L)
+#define GPIP_GPADC_FIFO_RDY_MASK (1 << 15U)
+#endif
+#define GPIP_GPADC_FIFO_DATA_COUNT_SHIFT (16U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_MASK (0x3f << GPIP_GPADC_FIFO_DATA_COUNT_SHIFT)
+#define GPIP_GPADC_FIFO_THL_SHIFT (22U)
+#define GPIP_GPADC_FIFO_THL_MASK (0x3 << GPIP_GPADC_FIFO_THL_SHIFT)
+
+/* 0x4 : gpadc_dma_rdata */
+#define GPIP_GPADC_DMA_RDATA_SHIFT (0U)
+#define GPIP_GPADC_DMA_RDATA_MASK (0x3ffffff << GPIP_GPADC_DMA_RDATA_SHIFT)
+
+/* 0x20 : gpadc_pir_train */
+#define GPIP_PIR_EXTEND_SHIFT (0U)
+#define GPIP_PIR_EXTEND_MASK (0x1f << GPIP_PIR_EXTEND_SHIFT)
+#define GPIP_PIR_CNT_V_SHIFT (8U)
+#define GPIP_PIR_CNT_V_MASK (0x1f << GPIP_PIR_CNT_V_SHIFT)
+#define GPIP_PIR_TRAIN (1 << 16U)
+#define GPIP_PIR_STOP (1 << 17U)
+
+/* 0x90C : gpadc_reg_cmd */
+#define AON_GPADC_GLOBAL_EN (1 << 0U)
+#define AON_GPADC_CONV_START (1 << 1U)
+#define AON_GPADC_SOFT_RST (1 << 2U)
+#define AON_GPADC_NEG_SEL_SHIFT (3U)
+#define AON_GPADC_NEG_SEL_MASK (0x1f << AON_GPADC_NEG_SEL_SHIFT)
+#define AON_GPADC_POS_SEL_SHIFT (8U)
+#define AON_GPADC_POS_SEL_MASK (0x1f << AON_GPADC_POS_SEL_SHIFT)
+#define AON_GPADC_NEG_GND (1 << 13U)
+#define AON_GPADC_MICBIAS_EN (1 << 14U)
+#define AON_GPADC_MICPGA_EN (1 << 15U)
+#define AON_GPADC_BYP_MICBOOST (1 << 16U)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define AON_GPADC_RCAL_EN (1 << 17U)
+#endif
+#define AON_GPADC_DWA_EN (1 << 18U)
+#define AON_GPADC_MIC2_DIFF (1 << 19U)
+#define AON_GPADC_MIC1_DIFF (1 << 20U)
+#define AON_GPADC_MIC_PGA2_GAIN_SHIFT (21U)
+#define AON_GPADC_MIC_PGA2_GAIN_MASK (0x3 << AON_GPADC_MIC_PGA2_GAIN_SHIFT)
+#define AON_GPADC_MICBOOST_32DB_EN (1 << 23U)
+#define AON_GPADC_CHIP_SEN_PU (1 << 27U)
+#define AON_GPADC_SEN_SEL_SHIFT (28U)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define AON_GPADC_SEN_SEL_MASK (0x7 << AON_GPADC_SEN_SEL_SHIFT)
+#define AON_GPADC_SEN_TEST_EN (1 << 31U)
+#elif defined(BL702) || defined(BL602) || defined(BL702L)
+#define AON_GPADC_SEN_SEL_MASK (0x3 << AON_GPADC_SEN_SEL_SHIFT)
+#define AON_GPADC_SEN_TEST_EN (1 << 30U)
+#endif
+
+/* 0x910 : gpadc_reg_config1 */
+#define AON_GPADC_CAL_OS_EN (1 << 0U)
+#define AON_GPADC_CONT_CONV_EN (1 << 1U)
+#define AON_GPADC_RES_SEL_SHIFT (2U)
+#define AON_GPADC_RES_SEL_MASK (0x7 << AON_GPADC_RES_SEL_SHIFT)
+#define AON_GPADC_VCM_SEL_EN (1 << 8U)
+#define AON_GPADC_VCM_HYST_SEL (1 << 9U)
+#define AON_GPADC_LOWV_DET_EN (1 << 10U)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define AON_GPADC_PWM_TRG_EN (1 << 11U)
+#define AON_GPADC_CLK_ANA_DLY_SHIFT (12U)
+#define AON_GPADC_CLK_ANA_DLY_MASK (0xf << AON_GPADC_CLK_ANA_DLY_SHIFT)
+#define AON_GPADC_CLK_ANA_DLY_EN (1 << 16U)
+#endif
+#define AON_GPADC_CLK_ANA_INV (1 << 17U)
+#define AON_GPADC_CLK_DIV_RATIO_SHIFT (18U)
+#define AON_GPADC_CLK_DIV_RATIO_MASK (0x7 << AON_GPADC_CLK_DIV_RATIO_SHIFT)
+#define AON_GPADC_SCAN_LENGTH_SHIFT (21U)
+#define AON_GPADC_SCAN_LENGTH_MASK (0xf << AON_GPADC_SCAN_LENGTH_SHIFT)
+#define AON_GPADC_SCAN_EN (1 << 25U)
+#define AON_GPADC_DITHER_EN (1 << 26U)
+#define AON_GPADC_V11_SEL_SHIFT (27U)
+#define AON_GPADC_V11_SEL_MASK (0x3 << AON_GPADC_V11_SEL_SHIFT)
+#define AON_GPADC_V18_SEL_SHIFT (29U)
+#define AON_GPADC_V18_SEL_MASK (0x3 << AON_GPADC_V18_SEL_SHIFT)
+
+/* 0x914 : gpadc_reg_config2 */
+#define AON_GPADC_DIFF_MODE (1 << 2U)
+#define AON_GPADC_VREF_SEL (1 << 3U)
+#define AON_GPADC_VBAT_EN (1 << 4U)
+#define AON_GPADC_TSEXT_SEL (1 << 5U)
+#define AON_GPADC_TS_EN (1 << 6U)
+#define AON_GPADC_PGA_VCM_SHIFT (7U)
+#define AON_GPADC_PGA_VCM_MASK (0x3 << AON_GPADC_PGA_VCM_SHIFT)
+#define AON_GPADC_PGA_OS_CAL_SHIFT (9U)
+#define AON_GPADC_PGA_OS_CAL_MASK (0xf << AON_GPADC_PGA_OS_CAL_SHIFT)
+#define AON_GPADC_PGA_EN (1 << 13U)
+#define AON_GPADC_PGA_VCMI_EN (1 << 14U)
+#define AON_GPADC_CHOP_MODE_SHIFT (15U)
+#define AON_GPADC_CHOP_MODE_MASK (0x3 << AON_GPADC_CHOP_MODE_SHIFT)
+#define AON_GPADC_BIAS_SEL (1 << 17U)
+#define AON_GPADC_TEST_EN (1 << 18U)
+#define AON_GPADC_TEST_SEL_SHIFT (19U)
+#define AON_GPADC_TEST_SEL_MASK (0x7 << AON_GPADC_TEST_SEL_SHIFT)
+#define AON_GPADC_PGA2_GAIN_SHIFT (22U)
+#define AON_GPADC_PGA2_GAIN_MASK (0x7 << AON_GPADC_PGA2_GAIN_SHIFT)
+#define AON_GPADC_PGA1_GAIN_SHIFT (25U)
+#define AON_GPADC_PGA1_GAIN_MASK (0x7 << AON_GPADC_PGA1_GAIN_SHIFT)
+#define AON_GPADC_DLY_SEL_SHIFT (28U)
+#define AON_GPADC_DLY_SEL_MASK (0x7 << AON_GPADC_DLY_SEL_SHIFT)
+#define AON_GPADC_TSVBE_LOW (1 << 31U)
+
+/* 0x918 : adc converation sequence 1 */
+#define AON_GPADC_SCAN_POS_0_SHIFT (0U)
+#define AON_GPADC_SCAN_POS_0_MASK (0x1f << AON_GPADC_SCAN_POS_0_SHIFT)
+#define AON_GPADC_SCAN_POS_1_SHIFT (5U)
+#define AON_GPADC_SCAN_POS_1_MASK (0x1f << AON_GPADC_SCAN_POS_1_SHIFT)
+#define AON_GPADC_SCAN_POS_2_SHIFT (10U)
+#define AON_GPADC_SCAN_POS_2_MASK (0x1f << AON_GPADC_SCAN_POS_2_SHIFT)
+#define AON_GPADC_SCAN_POS_3_SHIFT (15U)
+#define AON_GPADC_SCAN_POS_3_MASK (0x1f << AON_GPADC_SCAN_POS_3_SHIFT)
+#define AON_GPADC_SCAN_POS_4_SHIFT (20U)
+#define AON_GPADC_SCAN_POS_4_MASK (0x1f << AON_GPADC_SCAN_POS_4_SHIFT)
+#define AON_GPADC_SCAN_POS_5_SHIFT (25U)
+#define AON_GPADC_SCAN_POS_5_MASK (0x1f << AON_GPADC_SCAN_POS_5_SHIFT)
+
+/* 0x91C : adc converation sequence 2 */
+#define AON_GPADC_SCAN_POS_6_SHIFT (0U)
+#define AON_GPADC_SCAN_POS_6_MASK (0x1f << AON_GPADC_SCAN_POS_6_SHIFT)
+#define AON_GPADC_SCAN_POS_7_SHIFT (5U)
+#define AON_GPADC_SCAN_POS_7_MASK (0x1f << AON_GPADC_SCAN_POS_7_SHIFT)
+#define AON_GPADC_SCAN_POS_8_SHIFT (10U)
+#define AON_GPADC_SCAN_POS_8_MASK (0x1f << AON_GPADC_SCAN_POS_8_SHIFT)
+#define AON_GPADC_SCAN_POS_9_SHIFT (15U)
+#define AON_GPADC_SCAN_POS_9_MASK (0x1f << AON_GPADC_SCAN_POS_9_SHIFT)
+#define AON_GPADC_SCAN_POS_10_SHIFT (20U)
+#define AON_GPADC_SCAN_POS_10_MASK (0x1f << AON_GPADC_SCAN_POS_10_SHIFT)
+#define AON_GPADC_SCAN_POS_11_SHIFT (25U)
+#define AON_GPADC_SCAN_POS_11_MASK (0x1f << AON_GPADC_SCAN_POS_11_SHIFT)
+
+/* 0x920 : adc converation sequence 3 */
+#define AON_GPADC_SCAN_NEG_0_SHIFT (0U)
+#define AON_GPADC_SCAN_NEG_0_MASK (0x1f << AON_GPADC_SCAN_NEG_0_SHIFT)
+#define AON_GPADC_SCAN_NEG_1_SHIFT (5U)
+#define AON_GPADC_SCAN_NEG_1_MASK (0x1f << AON_GPADC_SCAN_NEG_1_SHIFT)
+#define AON_GPADC_SCAN_NEG_2_SHIFT (10U)
+#define AON_GPADC_SCAN_NEG_2_MASK (0x1f << AON_GPADC_SCAN_NEG_2_SHIFT)
+#define AON_GPADC_SCAN_NEG_3_SHIFT (15U)
+#define AON_GPADC_SCAN_NEG_3_MASK (0x1f << AON_GPADC_SCAN_NEG_3_SHIFT)
+#define AON_GPADC_SCAN_NEG_4_SHIFT (20U)
+#define AON_GPADC_SCAN_NEG_4_MASK (0x1f << AON_GPADC_SCAN_NEG_4_SHIFT)
+#define AON_GPADC_SCAN_NEG_5_SHIFT (25U)
+#define AON_GPADC_SCAN_NEG_5_MASK (0x1f << AON_GPADC_SCAN_NEG_5_SHIFT)
+
+/* 0x924 : adc converation sequence 4 */
+#define AON_GPADC_SCAN_NEG_6_SHIFT (0U)
+#define AON_GPADC_SCAN_NEG_6_MASK (0x1f << AON_GPADC_SCAN_NEG_6_SHIFT)
+#define AON_GPADC_SCAN_NEG_7_SHIFT (5U)
+#define AON_GPADC_SCAN_NEG_7_MASK (0x1f << AON_GPADC_SCAN_NEG_7_SHIFT)
+#define AON_GPADC_SCAN_NEG_8_SHIFT (10U)
+#define AON_GPADC_SCAN_NEG_8_MASK (0x1f << AON_GPADC_SCAN_NEG_8_SHIFT)
+#define AON_GPADC_SCAN_NEG_9_SHIFT (15U)
+#define AON_GPADC_SCAN_NEG_9_MASK (0x1f << AON_GPADC_SCAN_NEG_9_SHIFT)
+#define AON_GPADC_SCAN_NEG_10_SHIFT (20U)
+#define AON_GPADC_SCAN_NEG_10_MASK (0x1f << AON_GPADC_SCAN_NEG_10_SHIFT)
+#define AON_GPADC_SCAN_NEG_11_SHIFT (25U)
+#define AON_GPADC_SCAN_NEG_11_MASK (0x1f << AON_GPADC_SCAN_NEG_11_SHIFT)
+
+/* 0x928 : gpadc_reg_status */
+#define AON_GPADC_DATA_RDY (1 << 0U)
+#define AON_GPADC_RESERVED_SHIFT (16U)
+#define AON_GPADC_RESERVED_MASK (0xffff << AON_GPADC_RESERVED_SHIFT)
+
+/* 0x92C : gpadc_reg_isr */
+#define AON_GPADC_NEG_SATUR (1 << 0U)
+#define AON_GPADC_POS_SATUR (1 << 1U)
+#define AON_GPADC_NEG_SATUR_CLR (1 << 4U)
+#define AON_GPADC_POS_SATUR_CLR (1 << 5U)
+#define AON_GPADC_NEG_SATUR_MASK (1 << 8U)
+#define AON_GPADC_POS_SATUR_MASK (1 << 9U)
+
+/* 0x930 : gpadc_reg_result */
+#define AON_GPADC_DATA_OUT_SHIFT (0U)
+#define AON_GPADC_DATA_OUT_MASK (0x3ffffff << AON_GPADC_DATA_OUT_SHIFT)
+
+/* 0x934 : gpadc_reg_raw_result */
+#define AON_GPADC_RAW_DATA_SHIFT (0U)
+#define AON_GPADC_RAW_DATA_MASK (0xfff << AON_GPADC_RAW_DATA_SHIFT)
+
+/* 0x938 : gpadc_reg_define */
+#define AON_GPADC_OS_CAL_DATA_SHIFT (0U)
+#define AON_GPADC_OS_CAL_DATA_MASK (0xffff << AON_GPADC_OS_CAL_DATA_SHIFT)
+
+#endif /* __HARDWARE_ADC_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/auadc_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/auadc_reg.h
new file mode 100644
index 00000000..19f35265
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/auadc_reg.h
@@ -0,0 +1,193 @@
+/**
+ ******************************************************************************
+ * @file auadc_reg.h
+ * @version V1.0
+ * @date 2022-12-03
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __AUADC_REG_H__
+#define __AUADC_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define AUADC_AUDPDM_TOP_OFFSET (0x00) /* audpdm_top */
+#define AUADC_AUDPDM_ITF_OFFSET (0x04) /* audpdm_itf */
+#define AUADC_PDM_ADC_0_OFFSET (0x08) /* pdm_adc_0 */
+#define AUADC_PDM_ADC_1_OFFSET (0x0C) /* pdm_adc_1 */
+#define AUADC_PDM_DAC_0_OFFSET (0x10) /* pdm_dac_0 */
+#define AUADC_PDM_PDM_0_OFFSET (0x1C) /* pdm_pdm_0 */
+#define AUADC_PDM_ADC_S0_OFFSET (0x38) /* pdm_adc_s0 */
+#define AUADC_AUDADC_ANA_CFG1_OFFSET (0x60) /* audadc_ana_cfg1 */
+#define AUADC_AUDADC_ANA_CFG2_OFFSET (0x64) /* audadc_ana_cfg2 */
+#define AUADC_AUDADC_CMD_OFFSET (0x68) /* audadc_cmd */
+#define AUADC_AUDADC_DATA_OFFSET (0x6C) /* audadc_data */
+#define AUADC_AUDADC_RX_FIFO_CTRL_OFFSET (0x80) /* audadc_rx_fifo_ctrl */
+#define AUADC_AUDADC_RX_FIFO_STATUS_OFFSET (0x84) /* audadc_rx_fifo_status */
+#define AUADC_AUDADC_RX_FIFO_DATA_OFFSET (0x88) /* audadc_rx_fifo_data */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0xC00 : audpdm_top */
+#define AUADC_AUDIO_CKG_EN (1 << 0U)
+#define AUADC_ADC_ITF_INV_SEL (1 << 2U)
+#define AUADC_PDM_ITF_INV_SEL (1 << 3U)
+#define AUADC_ADC_RATE_SHIFT (28U)
+#define AUADC_ADC_RATE_MASK (0xf << AUADC_ADC_RATE_SHIFT)
+
+/* 0xC04 : audpdm_itf */
+#define AUADC_ADC_0_EN (1 << 0U)
+#define AUADC_ADC_ITF_EN (1 << 30U)
+
+/* 0xC08 : pdm_adc_0 */
+#define AUADC_ADC_0_FIR_MODE (1 << 0U)
+
+/* 0xC0C : pdm_adc_1 */
+#define AUADC_ADC_0_K1_SHIFT (0U)
+#define AUADC_ADC_0_K1_MASK (0xf << AUADC_ADC_0_K1_SHIFT)
+#define AUADC_ADC_0_K1_EN (1 << 4U)
+#define AUADC_ADC_0_K2_SHIFT (5U)
+#define AUADC_ADC_0_K2_MASK (0xf << AUADC_ADC_0_K2_SHIFT)
+#define AUADC_ADC_0_K2_EN (1 << 9U)
+
+/* 0xC10 : pdm_dac_0 */
+#define AUADC_ADC_PDM_H_SHIFT (0U)
+#define AUADC_ADC_PDM_H_MASK (0xf << AUADC_ADC_PDM_H_SHIFT)
+#define AUADC_ADC_PDM_L_SHIFT (6U)
+#define AUADC_ADC_PDM_L_MASK (0xf << AUADC_ADC_PDM_L_SHIFT)
+#define AUADC_ADC_0_SRC (1 << 12U)
+
+/* 0xC1C : pdm_pdm_0 */
+#define AUADC_PDM_0_EN (1 << 0U)
+#define AUADC_ADC_0_PDM_SEL_SHIFT (3U)
+#define AUADC_ADC_0_PDM_SEL_MASK (0x7 << AUADC_ADC_0_PDM_SEL_SHIFT)
+
+/* 0xC38 : pdm_adc_s0 */
+#define AUADC_ADC_S0_VOLUME_SHIFT (0U)
+#define AUADC_ADC_S0_VOLUME_MASK (0x1ff << AUADC_ADC_S0_VOLUME_SHIFT)
+
+/* 0xC60 : audadc_ana_cfg1 */
+#define AUADC_AUDADC_PGA_CHOP_CKSEL (1 << 0U)
+#define AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT (1U)
+#define AUADC_AUDADC_PGA_CHOP_FREQ_MASK (0x7 << AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT)
+#define AUADC_AUDADC_PGA_CHOP_EN (1 << 4U)
+#define AUADC_AUDADC_PGA_CHOP_CFG_SHIFT (5U)
+#define AUADC_AUDADC_PGA_CHOP_CFG_MASK (0x3 << AUADC_AUDADC_PGA_CHOP_CFG_SHIFT)
+#define AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT (8U)
+#define AUADC_AUDADC_PGA_RHPAS_SEL_MASK (0x3 << AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT)
+#define AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT (12U)
+#define AUADC_AUDADC_PGA_NOIS_CTRL_MASK (0x3 << AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT)
+#define AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT (16U)
+#define AUADC_AUDADC_ICTRL_PGA_AAF_MASK (0x3 << AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT)
+#define AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT (20U)
+#define AUADC_AUDADC_ICTRL_PGA_MIC_MASK (0x3 << AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT)
+#define AUADC_AUDADC_PGA_LP_EN (1 << 24U)
+#define AUADC_AUDADC_CKB_EN (1 << 28U)
+#define AUADC_AUDADC_SEL_EDGE (1 << 29U)
+
+/* 0xC64 : audadc_ana_cfg2 */
+#define AUADC_AUDADC_DITHER_ORDER (1 << 0U)
+#define AUADC_AUDADC_DITHER_SEL_SHIFT (1U)
+#define AUADC_AUDADC_DITHER_SEL_MASK (0x3 << AUADC_AUDADC_DITHER_SEL_SHIFT)
+#define AUADC_AUDADC_DITHER_ENA (1 << 3U)
+#define AUADC_AUDADC_QUAN_GAIN_SHIFT (4U)
+#define AUADC_AUDADC_QUAN_GAIN_MASK (0x3 << AUADC_AUDADC_QUAN_GAIN_SHIFT)
+#define AUADC_AUDADC_DEM_EN (1 << 8U)
+#define AUADC_AUDADC_NCTRL_ADC2_SHIFT (12U)
+#define AUADC_AUDADC_NCTRL_ADC2_MASK (0x3 << AUADC_AUDADC_NCTRL_ADC2_SHIFT)
+#define AUADC_AUDADC_NCTRL_ADC1_SHIFT (16U)
+#define AUADC_AUDADC_NCTRL_ADC1_MASK (0x7 << AUADC_AUDADC_NCTRL_ADC1_SHIFT)
+#define AUADC_AUDADC_ICTRL_ADC_SHIFT (20U)
+#define AUADC_AUDADC_ICTRL_ADC_MASK (0x3 << AUADC_AUDADC_ICTRL_ADC_SHIFT)
+#define AUADC_AUDADC_SDM_LP_EN (1 << 24U)
+#define AUADC_AUDADC_RESERVED_SHIFT (28U)
+#define AUADC_AUDADC_RESERVED_MASK (0x3 << AUADC_AUDADC_RESERVED_SHIFT)
+
+/* 0xC68 : audadc_cmd */
+#define AUADC_AUDADC_MEAS_ODR_SEL_SHIFT (0U)
+#define AUADC_AUDADC_MEAS_ODR_SEL_MASK (0xf << AUADC_AUDADC_MEAS_ODR_SEL_SHIFT)
+#define AUADC_AUDADC_MEAS_FILTER_TYPE (1 << 4U)
+#define AUADC_AUDADC_MEAS_FILTER_EN (1 << 5U)
+#define AUADC_AUDADC_AUDIO_OSR_SEL (1 << 6U)
+#define AUADC_AUDADC_PGA_GAIN_SHIFT (8U)
+#define AUADC_AUDADC_PGA_GAIN_MASK (0xf << AUADC_AUDADC_PGA_GAIN_SHIFT)
+#define AUADC_AUDADC_PGA_MODE_SHIFT (12U)
+#define AUADC_AUDADC_PGA_MODE_MASK (0x3 << AUADC_AUDADC_PGA_MODE_SHIFT)
+#define AUADC_AUDADC_CHANNEL_SELN_SHIFT (16U)
+#define AUADC_AUDADC_CHANNEL_SELN_MASK (0x7 << AUADC_AUDADC_CHANNEL_SELN_SHIFT)
+#define AUADC_AUDADC_CHANNEL_SELP_SHIFT (20U)
+#define AUADC_AUDADC_CHANNEL_SELP_MASK (0x7 << AUADC_AUDADC_CHANNEL_SELP_SHIFT)
+#define AUADC_AUDADC_CHANNEL_EN_SHIFT (24U)
+#define AUADC_AUDADC_CHANNEL_EN_MASK (0x3 << AUADC_AUDADC_CHANNEL_EN_SHIFT)
+#define AUADC_AUDADC_CONV (1 << 28U)
+#define AUADC_AUDADC_SDM_PU (1 << 29U)
+#define AUADC_AUDADC_PGA_PU (1 << 30U)
+
+/* 0xC6C : audadc_data */
+#define AUADC_AUDADC_RAW_DATA_SHIFT (0U)
+#define AUADC_AUDADC_RAW_DATA_MASK (0xffffff << AUADC_AUDADC_RAW_DATA_SHIFT)
+#define AUADC_AUDADC_DATA_RDY (1 << 24U)
+#define AUADC_AUDADC_SOFT_RST (1 << 29U)
+#define AUADC_AUDADC_VALID_4S_VAL (1 << 30U)
+#define AUADC_AUDADC_VALID_4S_EN (1 << 31U)
+
+/* 0xC80 : audadc_rx_fifo_ctrl */
+#define AUADC_RX_FIFO_FLUSH (1 << 0U)
+#define AUADC_RXO_INT_EN (1 << 1U)
+#define AUADC_RXU_INT_EN (1 << 2U)
+#define AUADC_RXA_INT_EN (1 << 3U)
+#define AUADC_RX_DRQ_EN (1 << 4U)
+#define AUADC_RX_DATA_RES_SHIFT (5U)
+#define AUADC_RX_DATA_RES_MASK (0x3 << AUADC_RX_DATA_RES_SHIFT)
+#define AUADC_RX_CH_EN (1 << 8U)
+#define AUADC_RX_DRQ_CNT_SHIFT (14U)
+#define AUADC_RX_DRQ_CNT_MASK (0x3 << AUADC_RX_DRQ_CNT_SHIFT)
+#define AUADC_RX_TRG_LEVEL_SHIFT (16U)
+#define AUADC_RX_TRG_LEVEL_MASK (0xf << AUADC_RX_TRG_LEVEL_SHIFT)
+#define AUADC_RX_DATA_MODE_SHIFT (24U)
+#define AUADC_RX_DATA_MODE_MASK (0x3 << AUADC_RX_DATA_MODE_SHIFT)
+
+/* 0xC84 : audadc_rx_fifo_status */
+#define AUADC_RXO_INT (1 << 1U)
+#define AUADC_RXU_INT (1 << 2U)
+#define AUADC_RXA_INT (1 << 4U)
+#define AUADC_RXA_CNT_SHIFT (16U)
+#define AUADC_RXA_CNT_MASK (0xf << AUADC_RXA_CNT_SHIFT)
+#define AUADC_RXA (1 << 24U)
+
+/* 0xC88 : audadc_rx_fifo_data */
+#define AUADC_RX_DATA_SHIFT (0U)
+#define AUADC_RX_DATA_MASK (0xffffffff << AUADC_RX_DATA_SHIFT)
+
+#endif /* __AUADC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/audac_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/audac_reg.h
new file mode 100644
index 00000000..a98de5f7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/audac_reg.h
@@ -0,0 +1,167 @@
+/**
+ ******************************************************************************
+ * @file audac_reg.h
+ * @version V1.0
+ * @date 2022-12-03
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __AUDAC_REG_H__
+#define __AUDAC_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define AUDAC_0_OFFSET (0x000) /* audac_0 */
+#define AUDAC_STATUS_OFFSET (0x4) /* audac_status */
+#define AUDAC_S0_OFFSET (0x8) /* audac_s0 */
+#define AUDAC_S0_MISC_OFFSET (0xC) /* audac_s0_misc */
+#define AUDAC_ZD_0_OFFSET (0x10) /* audac_zd_0 */
+#define AUDAC_1_OFFSET (0x14) /* audac_1 */
+#define AUDAC_RSVD_OFFSET (0x18) /* audac_rsvd */
+#define AUDAC_TEST_0_OFFSET (0x1C) /* audac_test_0 */
+#define AUDAC_TEST_1_OFFSET (0x20) /* audac_test_1 */
+#define AUDAC_TEST_2_OFFSET (0x24) /* audac_test_2 */
+#define AUDAC_TEST_3_OFFSET (0x28) /* audac_test_3 */
+#define AUDAC_FIFO_CTRL_OFFSET (0x8C) /* audac_fifo_ctrl */
+#define AUDAC_FIFO_STATUS_OFFSET (0x90) /* audac_fifo_status */
+#define AUDAC_FIFO_DATA_OFFSET (0x94) /* audac_fifo_data */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x000 : audac_0 */
+#define AUDAC_DAC_0_EN (1 << 0U)
+#define AUDAC_DAC_ITF_EN (1 << 1U)
+#define AUDAC_CKG_ENA (1 << 27U)
+#define AUDAC_AU_PWM_MODE_SHIFT (28U)
+#define AUDAC_AU_PWM_MODE_MASK (0xf << AUDAC_AU_PWM_MODE_SHIFT)
+
+/* 0x4 : audac_status */
+#define AUDAC_DAC_H0_BUSY (1 << 12U)
+#define AUDAC_DAC_H0_MUTE_DONE (1 << 13U)
+#define AUDAC_DAC_S0_INT (1 << 16U)
+#define AUDAC_DAC_S0_INT_CLR (1 << 17U)
+#define AUDAC_ZD_AMUTE (1 << 23U)
+#define AUDAC_AUDIO_INT_ALL (1 << 24U)
+
+/* 0x8 : audac_s0 */
+#define AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT (2U)
+#define AUDAC_DAC_S0_CTRL_RMP_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT)
+#define AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT (6U)
+#define AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT)
+#define AUDAC_DAC_S0_CTRL_MODE_SHIFT (10U)
+#define AUDAC_DAC_S0_CTRL_MODE_MASK (0x3 << AUDAC_DAC_S0_CTRL_MODE_SHIFT)
+#define AUDAC_DAC_S0_VOLUME_UPDATE (1 << 12U)
+#define AUDAC_DAC_S0_VOLUME_SHIFT (13U)
+#define AUDAC_DAC_S0_VOLUME_MASK (0x1ff << AUDAC_DAC_S0_VOLUME_SHIFT)
+#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT (22U)
+#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT)
+#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT (26U)
+#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT)
+#define AUDAC_DAC_S0_MUTE_SOFTMODE (1 << 30U)
+#define AUDAC_DAC_S0_MUTE (1 << 31U)
+
+/* 0xC : audac_s0_misc */
+#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT (28U)
+#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT)
+
+/* 0x10 : audac_zd_0 */
+#define AUDAC_ZD_TIME_SHIFT (0U)
+#define AUDAC_ZD_TIME_MASK (0x7fff << AUDAC_ZD_TIME_SHIFT)
+#define AUDAC_ZD_EN (1 << 16U)
+
+/* 0x14 : audac_1 */
+#define AUDAC_DAC_MIX_SEL_SHIFT (0U)
+#define AUDAC_DAC_MIX_SEL_MASK (0x3 << AUDAC_DAC_MIX_SEL_SHIFT)
+#define AUDAC_DAC_DSM_OUT_FMT (1 << 4U)
+#define AUDAC_DAC_DSM_ORDER_SHIFT (5U)
+#define AUDAC_DAC_DSM_ORDER_MASK (0x3 << AUDAC_DAC_DSM_ORDER_SHIFT)
+#define AUDAC_DAC_DSM_SCALING_MODE_SHIFT (7U)
+#define AUDAC_DAC_DSM_SCALING_MODE_MASK (0x3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT)
+#define AUDAC_DAC_DSM_SCALING_EN (1 << 10U)
+#define AUDAC_DAC_DSM_DITHER_AMP_SHIFT (11U)
+#define AUDAC_DAC_DSM_DITHER_AMP_MASK (0x7 << AUDAC_DAC_DSM_DITHER_AMP_SHIFT)
+#define AUDAC_DAC_DSM_DITHER_EN (1 << 14U)
+#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT (15U)
+#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_MASK (0x3 << AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT)
+
+/* 0x18 : audac_rsvd */
+#define AUDAC_AU_PWM_RESERVED_SHIFT (0U)
+#define AUDAC_AU_PWM_RESERVED_MASK (0xffffffff << AUDAC_AU_PWM_RESERVED_SHIFT)
+
+/* 0x1C : audac_test_0 */
+#define AUDAC_DAC_IN_0_SHIFT (0U)
+#define AUDAC_DAC_IN_0_MASK (0xffff << AUDAC_DAC_IN_0_SHIFT)
+#define AUDAC_DAC_DPGA_0_SHIFT (16U)
+#define AUDAC_DAC_DPGA_0_MASK (0xffff << AUDAC_DAC_DPGA_0_SHIFT)
+
+/* 0x20 : audac_test_1 */
+#define AUDAC_DAC_FIR_0_SHIFT (0U)
+#define AUDAC_DAC_FIR_0_MASK (0x1ffff << AUDAC_DAC_FIR_0_SHIFT)
+
+/* 0x24 : audac_test_2 */
+#define AUDAC_DAC_SINC_0_SHIFT (0U)
+#define AUDAC_DAC_SINC_0_MASK (0xffff << AUDAC_DAC_SINC_0_SHIFT)
+
+/* 0x28 : audac_test_3 */
+#define AUDAC_AU_PWM_TEST_READ_SHIFT (0U)
+#define AUDAC_AU_PWM_TEST_READ_MASK (0xffffffff << AUDAC_AU_PWM_TEST_READ_SHIFT)
+
+/* 0x8C : audac_fifo_ctrl */
+#define AUDAC_TX_FIFO_FLUSH (1 << 0U)
+#define AUDAC_TXO_INT_EN (1 << 1U)
+#define AUDAC_TXU_INT_EN (1 << 2U)
+#define AUDAC_TXA_INT_EN (1 << 3U)
+#define AUDAC_TX_DRQ_EN (1 << 4U)
+#define AUDAC_TX_CH_EN_SHIFT (8U)
+#define AUDAC_TX_CH_EN_MASK (0x3 << AUDAC_TX_CH_EN_SHIFT)
+#define AUDAC_TX_DRQ_CNT_SHIFT (14U)
+#define AUDAC_TX_DRQ_CNT_MASK (0x3 << AUDAC_TX_DRQ_CNT_SHIFT)
+#define AUDAC_TX_TRG_LEVEL_SHIFT (16U)
+#define AUDAC_TX_TRG_LEVEL_MASK (0x1f << AUDAC_TX_TRG_LEVEL_SHIFT)
+#define AUDAC_TX_DATA_MODE_SHIFT (24U)
+#define AUDAC_TX_DATA_MODE_MASK (0x3 << AUDAC_TX_DATA_MODE_SHIFT)
+
+/* 0x90 : audac_fifo_status */
+#define AUDAC_TXO_INT (1 << 1U)
+#define AUDAC_TXU_INT (1 << 2U)
+#define AUDAC_TXA_INT (1 << 4U)
+#define AUDAC_TXA_CNT_SHIFT (16U)
+#define AUDAC_TXA_CNT_MASK (0x1f << AUDAC_TXA_CNT_SHIFT)
+#define AUDAC_TXA (1 << 24U)
+
+/* 0x94 : audac_fifo_data */
+#define AUDAC_TX_DATA_SHIFT (0U)
+#define AUDAC_TX_DATA_MASK (0xffffffff << AUDAC_TX_DATA_SHIFT)
+
+#endif /* __AUDAC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/cam_front_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/cam_front_reg.h
new file mode 100644
index 00000000..7d337347
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/cam_front_reg.h
@@ -0,0 +1,185 @@
+/**
+ ******************************************************************************
+ * @file cam_front_reg.h
+ * @version V1.0
+ * @date 2022-12-03
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_CAM_FRONT_H__
+#define __HARDWARE_CAM_FRONT_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CAM_FRONT_CONFIG_OFFSET (0x0)/* config */
+#define CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET (0x8)/* dvp2bus_src_sel_1 */
+#if defined(BL616)
+#define CAM_FRONT_SNSR_CTRL_OFFSET (0xC)/* snsr_ctrl */
+#define CAM_FRONT_EMI_MISC_OFFSET (0x10)/* emi_misc */
+#define CAM_FRONT_ISP_ID_YUV_OFFSET (0x14)/* isp_id_yuv */
+#endif
+#if defined(BL808)
+#define CAM_FRONT_PIX_DATA_CTRL_OFFSET (0x4)/* pix_data_ctrl */
+#define CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET (0x14)/* dvp2bus_src_sel_2 */
+#define CAM_FRONT_ISP_ID_YUV_OFFSET (0x28)/* isp_id_yuv */
+#define CAM_FRONT_ADJA_CTRL_2_OFFSET (0x108)/* adjA_ctrl_2 */
+#define CAM_FRONT_Y2RA_CONFIG_0_OFFSET (0x160)/* y2rA_config_0 */
+#define CAM_FRONT_Y2RA_CONFIG_1_OFFSET (0x164)/* y2rA_config_1 */
+#define CAM_FRONT_Y2RA_CONFIG_2_OFFSET (0x168)/* y2rA_config_2 */
+#define CAM_FRONT_Y2RA_CONFIG_3_OFFSET (0x16C)/* y2rA_config_3 */
+#define CAM_FRONT_Y2RA_CONFIG_4_OFFSET (0x170)/* y2rA_config_4 */
+#define CAM_FRONT_Y2RA_CONFIG_5_OFFSET (0x174)/* y2rA_config_5 */
+#define CAM_FRONT_Y2RA_CONFIG_6_OFFSET (0x178)/* y2rA_config_6 */
+#define CAM_FRONT_Y2RA_CONFIG_7_OFFSET (0x17C)/* y2rA_config_7 */
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : config */
+#define CAM_FRONT_RG_DVPAS_ENABLE (1<<0U)
+#define CAM_FRONT_RG_DVPAS_HS_INV (1<<1U)
+#define CAM_FRONT_RG_DVPAS_VS_INV (1<<2U)
+#define CAM_FRONT_RG_DVPAS_DA_ORDER (1<<3U)
+#define CAM_FRONT_RG_DVPAS_FIFO_TH_SHIFT (16U)
+#define CAM_FRONT_RG_DVPAS_FIFO_TH_MASK (0x7ff<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_CAM_H__
+#define __HARDWARE_CAM_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0)/* dvp2axi_configue */
+#define CAM_DVP2AXI_ADDR_START_OFFSET (0x4)/* dvp2axi_addr_start */
+#define CAM_DVP2AXI_MEM_BCNT_OFFSET (0x8)/* dvp2axi_mem_bcnt */
+#define CAM_DVP2AXI_HSYNC_CROP_OFFSET (0x30)/* dvp2axi_hsync_crop */
+#define CAM_DVP2AXI_VSYNC_CROP_OFFSET (0x34)/* dvp2axi_vsync_crop */
+#define CAM_DVP2AXI_FRAM_EXM_OFFSET (0x38)/* dvp2axi_fram_exm */
+#define CAM_FRAME_START_ADDR0_OFFSET (0x40)/* frame_start_addr0 */
+#define CAM_FRAME_START_ADDR1_OFFSET (0x48)/* frame_start_addr1 */
+#define CAM_FRAME_START_ADDR2_OFFSET (0x50)/* frame_start_addr2 */
+#define CAM_FRAME_START_ADDR3_OFFSET (0x58)/* frame_start_addr3 */
+#if defined(BL702)
+#define CAM_DVP2AXI_FRAME_BCNT_0_OFFSET (0xC)/* dvp2axi_frame_bcnt_0 */
+#define CAM_DVP2AXI_ADDR_START_1_OFFSET (0x10)/* dvp2axi_addr_start_1 */
+#define CAM_DVP2AXI_MEM_BCNT_1_OFFSET (0x14)/* dvp2axi_mem_bcnt_1 */
+#define CAM_DVP2AXI_FRAME_BCNT_1_OFFSET (0x18)/* dvp2axi_frame_bcnt_1 */
+#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0x1C)/* dvp_status_and_error */
+#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x20)/* dvp_frame_fifo_pop */
+#define CAM_SNSR_CONTROL_OFFSET (0x24)/* snsr_control */
+#define CAM_INT_CONTROL_OFFSET (0x28)/* int_control */
+#define CAM_FRAME_BYTE_CNT0_0_OFFSET (0x44)/* frame_byte_cnt0_0 */
+#define CAM_FRAME_BYTE_CNT0_1_OFFSET (0x4C)/* frame_byte_cnt0_1 */
+#define CAM_FRAME_BYTE_CNT0_2_OFFSET (0x54)/* frame_byte_cnt0_2 */
+#define CAM_FRAME_BYTE_CNT0_3_OFFSET (0x5C)/* frame_byte_cnt0_3 */
+#define CAM_FRAME_START_ADDR0_4_OFFSET (0x60)/* frame_start_addr0_4 */
+#define CAM_FRAME_BYTE_CNT0_4_OFFSET (0x64)/* frame_byte_cnt0_4 */
+#define CAM_FRAME_START_ADDR0_5_OFFSET (0x68)/* frame_start_addr0_5 */
+#define CAM_FRAME_BYTE_CNT0_5_OFFSET (0x6C)/* frame_byte_cnt0_5 */
+#define CAM_FRAME_START_ADDR0_6_OFFSET (0x70)/* frame_start_addr0_6 */
+#define CAM_FRAME_BYTE_CNT0_6_OFFSET (0x74)/* frame_byte_cnt0_6 */
+#define CAM_FRAME_START_ADDR0_7_OFFSET (0x78)/* frame_start_addr0_7 */
+#define CAM_FRAME_BYTE_CNT0_7_OFFSET (0x7C)/* frame_byte_cnt0_7 */
+#define CAM_FRAME_START_ADDR1_0_OFFSET (0x80)/* frame_start_addr1_0 */
+#define CAM_FRAME_BYTE_CNT1_0_OFFSET (0x84)/* frame_byte_cnt1_0 */
+#define CAM_FRAME_START_ADDR1_1_OFFSET (0x88)/* frame_start_addr1_1 */
+#define CAM_FRAME_BYTE_CNT1_1_OFFSET (0x8C)/* frame_byte_cnt1_1 */
+#define CAM_FRAME_START_ADDR1_2_OFFSET (0x90)/* frame_start_addr1_2 */
+#define CAM_FRAME_BYTE_CNT1_2_OFFSET (0x94)/* frame_byte_cnt1_2 */
+#define CAM_FRAME_START_ADDR1_3_OFFSET (0x98)/* frame_start_addr1_3 */
+#define CAM_FRAME_BYTE_CNT1_3_OFFSET (0x9C)/* frame_byte_cnt1_3 */
+#define CAM_FRAME_START_ADDR1_4_OFFSET (0xA0)/* frame_start_addr1_4 */
+#define CAM_FRAME_BYTE_CNT1_4_OFFSET (0xA4)/* frame_byte_cnt1_4 */
+#define CAM_FRAME_START_ADDR1_5_OFFSET (0xA8)/* frame_start_addr1_5 */
+#define CAM_FRAME_BYTE_CNT1_5_OFFSET (0xAC)/* frame_byte_cnt1_5 */
+#define CAM_FRAME_START_ADDR1_6_OFFSET (0xB0)/* frame_start_addr1_6 */
+#define CAM_FRAME_BYTE_CNT1_6_OFFSET (0xB4)/* frame_byte_cnt1_6 */
+#define CAM_FRAME_START_ADDR1_7_OFFSET (0xB8)/* frame_start_addr1_7 */
+#define CAM_FRAME_BYTE_CNT1_7_OFFSET (0xBC)/* frame_byte_cnt1_7 */
+#define CAM_DVP_DEBUG_OFFSET (0xFF0)/* dvp_debug */
+#define CAM_DVP_DUMMY_REG_OFFSET (0xFFC)/* dvp_dummy_reg */
+#else
+#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0xC)/* dvp_status_and_error */
+#define CAM_DVP2AXI_FRAME_BCNT_OFFSET (0x10)/* dvp2axi_frame_bcnt */
+#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x14)/* dvp_frame_fifo_pop */
+#define CAM_DVP2AXI_FRAME_VLD_OFFSET (0x18)/* dvp2axi_frame_vld */
+#define CAM_DVP2AXI_FRAME_PERIOD_OFFSET (0x1C)/* dvp2axi_frame_period */
+#define CAM_DVP2AXI_MISC_OFFSET (0x20)/* dvp2axi_misc */
+#define CAM_FRAME_ID_STS01_OFFSET (0x60)/* frame_id_sts01 */
+#define CAM_FRAME_ID_STS23_OFFSET (0x64)/* frame_id_sts23 */
+#define CAM_DVP_DEBUG_OFFSET (0xF0)/* dvp_debug */
+#define CAM_DVP_DUMMY_REG_OFFSET (0xFC)/* dvp_dummy_reg */
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : dvp2axi_configue */
+#define CAM_REG_DVP_ENABLE (1<<0U)
+#define CAM_REG_SW_MODE (1<<1U)
+#define CAM_REG_FRAM_VLD_POL (1<<2U)
+#define CAM_REG_LINE_VLD_POL (1<<3U)
+#define CAM_REG_XLEN_SHIFT (4U)
+#if defined(BL702)
+#define CAM_REG_XLEN_MASK (0x3<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __CKS_REG_H__
+#define __CKS_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CKS_CONFIG_OFFSET (0x0)/* cks_config */
+#define CKS_DATA_IN_OFFSET (0x4)/* data_in */
+#define CKS_OUT_OFFSET (0x8)/* cks_out */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : cks_config */
+#define CKS_CR_CKS_CLR (1<<0U)
+#define CKS_CR_CKS_BYTE_SWAP (1<<1U)
+
+/* 0x4 : data_in */
+#define CKS_DATA_IN_SHIFT (0U)
+#define CKS_DATA_IN_MASK (0xff<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_CSI_H__
+#define __HARDWARE_CSI_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CSI_MIPI_CONFIG_OFFSET (0x0)/* mipi_config */
+#define CSI_INT_STATUS_OFFSET (0x10)/* csi_int_status */
+#define CSI_INT_MASK_OFFSET (0x14)/* csi_int_mask */
+#define CSI_INT_CLEAR_OFFSET (0x18)/* csi_int_clear */
+#define CSI_INT_ENABLE_OFFSET (0x1C)/* csi_int_enable */
+#define CSI_GNR_BUF_STATUS_OFFSET (0x20)/* gnr_buf_status */
+#define CSI_GNR_BUF_RDATA_OFFSET (0x24)/* gnr_buf_rdata */
+#define CSI_DPHY_CONFIG_0_OFFSET (0x80)/* dphy_config_0 */
+#define CSI_DPHY_CONFIG_1_OFFSET (0x84)/* dphy_config_1 */
+#define CSI_DPHY_CONFIG_2_OFFSET (0x88)/* dphy_config_2 */
+#define CSI_DPHY_CONFIG_3_OFFSET (0x8C)/* dphy_config_3 */
+#define CSI_DPHY_CONFIG_4_OFFSET (0x90)/* dphy_config_4 */
+#define CSI_DPHY_CONFIG_5_OFFSET (0x94)/* dphy_config_5 */
+#define CSI_DUMMY_REG_OFFSET (0xFC)/* dummy_reg */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : mipi_config */
+#define CSI_CR_CSI_EN (1<<0U)
+#define CSI_CR_LANE_NUM (1<<1U)
+#define CSI_CR_LANE_INV (1<<3U)
+#define CSI_CR_DATA_BIT_INV (1<<4U)
+#define CSI_CR_SYNC_SP_EN (1<<5U)
+#define CSI_CR_UNPACK_EN (1<<6U)
+#define CSI_CR_VC_DVP0_SHIFT (12U)
+#define CSI_CR_VC_DVP0_MASK (0x3<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_DAC_H__
+#define __HARDWARE_DAC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+/* gpip base */
+#define GPIP_GPDAC_CONFIG_OFFSET (0x40) /* gpdac_config */
+#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44) /* gpdac_dma_config */
+#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48) /* gpdac_dma_wdata */
+#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C) /* gpdac_tx_fifo_status */
+/* glb base */
+#if defined(BL702)
+#define GLB_GPDAC_CTRL_OFFSET (0x308) /* gpdac_ctrl */
+#define GLB_GPDAC_ACTRL_OFFSET (0x30C) /* gpdac_actrl */
+#define GLB_GPDAC_BCTRL_OFFSET (0x310) /* gpdac_bctrl */
+#define GLB_GPDAC_DATA_OFFSET (0x314) /* gpdac_data */
+#else
+#define GLB_GPDAC_CTRL_OFFSET (0x120) /* gpdac_ctrl */
+#define GLB_GPDAC_ACTRL_OFFSET (0x124) /* gpdac_actrl */
+#define GLB_GPDAC_BCTRL_OFFSET (0x128) /* gpdac_bctrl */
+#define GLB_GPDAC_DATA_OFFSET (0x12C) /* gpdac_data */
+#endif
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x40 : gpdac_config */
+#define GPIP_GPDAC_EN (1 << 0U)
+#if defined(BL702)
+#define GPIP_GPDAC_EN2 (1 << 1U)
+#define GPIP_DSM_MODE_SHIFT (4U)
+#define GPIP_DSM_MODE_MASK (0x3 << GPIP_DSM_MODE_SHIFT)
+#endif
+#define GPIP_GPDAC_MODE_SHIFT (8U)
+#define GPIP_GPDAC_MODE_MASK (0x7 << GPIP_GPDAC_MODE_SHIFT)
+#define GPIP_GPDAC_CH_A_SEL_SHIFT (16U)
+#define GPIP_GPDAC_CH_A_SEL_MASK (0xf << GPIP_GPDAC_CH_A_SEL_SHIFT)
+#define GPIP_GPDAC_CH_B_SEL_SHIFT (20U)
+#define GPIP_GPDAC_CH_B_SEL_MASK (0xf << GPIP_GPDAC_CH_B_SEL_SHIFT)
+
+/* 0x44 : gpdac_dma_config */
+#define GPIP_GPDAC_DMA_TX_EN (1 << 0U)
+#if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808)
+#define GPIP_GPDAC_DMA_INV_MSB (1 << 1U)
+#endif
+#define GPIP_GPDAC_DMA_FORMAT_SHIFT (4U)
+#define GPIP_GPDAC_DMA_FORMAT_MASK (0x3 << GPIP_GPDAC_DMA_FORMAT_SHIFT)
+
+/* 0x48 : gpdac_dma_wdata */
+#define GPIP_GPDAC_DMA_WDATA_SHIFT (0U)
+#define GPIP_GPDAC_DMA_WDATA_MASK (0xffffffff << GPIP_GPDAC_DMA_WDATA_SHIFT)
+
+/* 0x4C : gpdac_tx_fifo_status */
+#define GPIP_TX_FIFO_EMPTY (1 << 0U)
+#define GPIP_TX_FIFO_FULL (1 << 1U)
+#define GPIP_TX_CS_SHIFT (2U)
+#define GPIP_TX_CS_MASK (0x3 << GPIP_TX_CS_SHIFT)
+#define GPIP_TXFIFORDPTR_SHIFT (4U)
+#define GPIP_TXFIFORDPTR_MASK (0x7 << GPIP_TXFIFORDPTR_SHIFT)
+#define GPIP_TXFIFOWRPTR_SHIFT (8U)
+#define GPIP_TXFIFOWRPTR_MASK (0x3 << GPIP_TXFIFOWRPTR_SHIFT)
+
+/* 0x308 : gpdac_ctrl */
+#define GLB_GPDACA_RSTN_ANA (1 << 0U)
+#define GLB_GPDACB_RSTN_ANA (1 << 1U)
+#define GLB_GPDAC_TEST_EN (1 << 7U)
+#define GLB_GPDAC_REF_SEL (1 << 8U)
+#define GLB_GPDAC_TEST_SEL_SHIFT (9U)
+#define GLB_GPDAC_TEST_SEL_MASK (0x7 << GLB_GPDAC_TEST_SEL_SHIFT)
+#if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808)
+#define GLB_GPDAC_ANA_CLK_SEL (1 << 12U)
+#define GLB_GPDAC_DAT_CHA_SEL (1 << 13U)
+#define GLB_GPDAC_DAT_CHB_SEL (1 << 14U)
+#endif
+#define GLB_GPDAC_RESERVED_SHIFT (24U)
+#define GLB_GPDAC_RESERVED_MASK (0xff << GLB_GPDAC_RESERVED_SHIFT)
+
+/* 0x30C : gpdac_actrl */
+#define GLB_GPDAC_A_EN (1 << 0U)
+#define GLB_GPDAC_IOA_EN (1 << 1U)
+#define GLB_GPDAC_A_RNG_SHIFT (18U)
+#define GLB_GPDAC_A_RNG_MASK (0x3 << GLB_GPDAC_A_RNG_SHIFT)
+#define GLB_GPDAC_A_OUTMUX_SHIFT (20U)
+#define GLB_GPDAC_A_OUTMUX_MASK (0x7 << GLB_GPDAC_A_OUTMUX_SHIFT)
+
+/* 0x310 : gpdac_bctrl */
+#define GLB_GPDAC_B_EN (1 << 0U)
+#define GLB_GPDAC_IOB_EN (1 << 1U)
+#define GLB_GPDAC_B_RNG_SHIFT (18U)
+#define GLB_GPDAC_B_RNG_MASK (0x3 << GLB_GPDAC_B_RNG_SHIFT)
+#define GLB_GPDAC_B_OUTMUX_SHIFT (20U)
+#define GLB_GPDAC_B_OUTMUX_MASK (0x7 << GLB_GPDAC_B_OUTMUX_SHIFT)
+
+/* 0x314 : gpdac_data */
+#if defined(BL702) || defined(BL602) || defined(BL606P) || defined(BL808)
+#define GLB_GPDAC_B_DATA_SHIFT (0U)
+#define GLB_GPDAC_B_DATA_MASK (0x3ff << GLB_GPDAC_B_DATA_SHIFT)
+#define GLB_GPDAC_A_DATA_SHIFT (16U)
+#define GLB_GPDAC_A_DATA_MASK (0x3ff << GLB_GPDAC_A_DATA_SHIFT)
+#elif defined(BL616) || defined(BL628)
+#define GLB_GPDAC_B_DATA_SHIFT (0U)
+#define GLB_GPDAC_B_DATA_MASK (0x1fff << GLB_GPDAC_B_DATA_SHIFT)
+#define GLB_GPDAC_A_DATA_SHIFT (16U)
+#define GLB_GPDAC_A_DATA_MASK (0x1fff << GLB_GPDAC_A_DATA_SHIFT)
+#endif
+
+#endif /* __HARDWARE_DAC_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dbi_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dbi_reg.h
new file mode 100644
index 00000000..9ae0a18d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dbi_reg.h
@@ -0,0 +1,201 @@
+/**
+ ******************************************************************************
+ * @file dbi_reg.h
+ * @version V1.0
+ * @date 2023-02-08
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __DBI_REG_H__
+#define __DBI_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define DBI_CONFIG_OFFSET (0x0) /* dbi_config */
+#define DBI_QSPI_CONFIG_OFFSET (0x4) /* qspi_config */
+#define DBI_PIX_CNT_OFFSET (0x8) /* dbi_pix_cnt */
+#define DBI_PRD_OFFSET (0xC) /* dbi_prd */
+#define DBI_CMD_OFFSET (0x10) /* dbi_cmd */
+#define DBI_QSPI_ADR_OFFSET (0x14) /* dbi_qspi_adr */
+#define DBI_RDATA_0_OFFSET (0x18) /* dbi_rdata_0 */
+#define DBI_RDATA_1_OFFSET (0x1C) /* dbi_rdata_1 */
+#define DBI_INT_STS_OFFSET (0x30) /* dbi_int_sts */
+#define DBI_YUV_RGB_CONFIG_0_OFFSET (0x60) /* dbi_yuv_rgb_config_0 */
+#define DBI_YUV_RGB_CONFIG_1_OFFSET (0x64) /* dbi_yuv_rgb_config_1 */
+#define DBI_YUV_RGB_CONFIG_2_OFFSET (0x68) /* dbi_yuv_rgb_config_2 */
+#define DBI_YUV_RGB_CONFIG_3_OFFSET (0x6C) /* dbi_yuv_rgb_config_3 */
+#define DBI_YUV_RGB_CONFIG_4_OFFSET (0x70) /* dbi_yuv_rgb_config_4 */
+#define DBI_YUV_RGB_CONFIG_5_OFFSET (0x74) /* dbi_yuv_rgb_config_5 */
+#define DBI_FIFO_CONFIG_0_OFFSET (0x80) /* dbi_fifo_config_0 */
+#define DBI_FIFO_CONFIG_1_OFFSET (0x84) /* dbi_fifo_config_1 */
+#define DBI_FIFO_WDATA_OFFSET (0x88) /* dbi_fifo_wdata */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : dbi_config */
+#define DBI_CR_DBI_EN (1 << 0U)
+#define DBI_CR_DBI_SEL_SHIFT (1U)
+#define DBI_CR_DBI_SEL_MASK (0x3 << DBI_CR_DBI_SEL_SHIFT)
+#define DBI_CR_DBI_CMD_EN (1 << 4U)
+#define DBI_CR_DBI_DAT_EN (1 << 5U)
+#define DBI_CR_DBI_DAT_WR (1 << 6U)
+#define DBI_CR_DBI_DAT_TP (1 << 7U)
+#define DBI_CR_DBI_DAT_BC_SHIFT (8U)
+#define DBI_CR_DBI_DAT_BC_MASK (0xff << DBI_CR_DBI_DAT_BC_SHIFT)
+#define DBI_CR_DBI_SCL_POL (1 << 16U)
+#define DBI_CR_DBI_SCL_PH (1 << 17U)
+#define DBI_CR_DBI_CONT_EN (1 << 18U)
+#define DBI_CR_DBI_DMY_EN (1 << 19U)
+#define DBI_CR_DBI_DMY_CNT_SHIFT (20U)
+#define DBI_CR_DBI_DMY_CNT_MASK (0xf << DBI_CR_DBI_DMY_CNT_SHIFT)
+#define DBI_CR_DBI_CS_STRETCH (1 << 24U)
+#define DBI_STS_DBI_BUS_BUSY (1 << 31U)
+
+/* 0x4 : qspi_config */
+#define DBI_CR_QSPI_CMD_4B (1 << 0U)
+#define DBI_CR_QSPI_ADR_4B (1 << 1U)
+#define DBI_CR_QSPI_DAT_4B (1 << 2U)
+#define DBI_CR_QSPI_ADR_BC_SHIFT (4U)
+#define DBI_CR_QSPI_ADR_BC_MASK (0x3 << DBI_CR_QSPI_ADR_BC_SHIFT)
+
+/* 0x8 : dbi_pix_cnt */
+#define DBI_CR_DBI_PIX_CNT_SHIFT (0U)
+#define DBI_CR_DBI_PIX_CNT_MASK (0xffffff << DBI_CR_DBI_PIX_CNT_SHIFT)
+#define DBI_CR_DBI_PIX_FORMAT (1 << 31U)
+
+/* 0xC : dbi_prd */
+#define DBI_CR_DBI_PRD_S_SHIFT (0U)
+#define DBI_CR_DBI_PRD_S_MASK (0xff << DBI_CR_DBI_PRD_S_SHIFT)
+#define DBI_CR_DBI_PRD_I_SHIFT (8U)
+#define DBI_CR_DBI_PRD_I_MASK (0xff << DBI_CR_DBI_PRD_I_SHIFT)
+#define DBI_CR_DBI_PRD_D_PH_0_SHIFT (16U)
+#define DBI_CR_DBI_PRD_D_PH_0_MASK (0xff << DBI_CR_DBI_PRD_D_PH_0_SHIFT)
+#define DBI_CR_DBI_PRD_D_PH_1_SHIFT (24U)
+#define DBI_CR_DBI_PRD_D_PH_1_MASK (0xff << DBI_CR_DBI_PRD_D_PH_1_SHIFT)
+
+/* 0x10 : dbi_cmd */
+#define DBI_CR_DBI_CMD_SHIFT (0U)
+#define DBI_CR_DBI_CMD_MASK (0xff << DBI_CR_DBI_CMD_SHIFT)
+
+/* 0x14 : dbi_qspi_adr */
+#define DBI_CR_QSPI_ADR_SHIFT (0U)
+#define DBI_CR_QSPI_ADR_MASK (0xffffffff << DBI_CR_QSPI_ADR_SHIFT)
+
+/* 0x18 : dbi_rdata_0 */
+#define DBI_STS_DBI_RDATA_0_SHIFT (0U)
+#define DBI_STS_DBI_RDATA_0_MASK (0xffffffff << DBI_STS_DBI_RDATA_0_SHIFT)
+
+/* 0x1C : dbi_rdata_1 */
+#define DBI_STS_DBI_RDATA_1_SHIFT (0U)
+#define DBI_STS_DBI_RDATA_1_MASK (0xffffffff << DBI_STS_DBI_RDATA_1_SHIFT)
+
+/* 0x30 : dbi_int_sts */
+#define DBI_END_INT (1 << 0U)
+#define DBI_TXF_INT (1 << 1U)
+#define DBI_FER_INT (1 << 2U)
+#define DBI_CR_DBI_END_MASK (1 << 8U)
+#define DBI_CR_DBI_TXF_MASK (1 << 9U)
+#define DBI_CR_DBI_FER_MASK (1 << 10U)
+#define DBI_CR_DBI_END_CLR (1 << 16U)
+#define DBI_CR_DBI_END_EN (1 << 24U)
+#define DBI_CR_DBI_TXF_EN (1 << 25U)
+#define DBI_CR_DBI_FER_EN (1 << 26U)
+
+/* 0x60 : dbi_yuv_rgb_config_0 */
+#define DBI_CR_Y2R_PRE_0_SHIFT (0U)
+#define DBI_CR_Y2R_PRE_0_MASK (0x1ff << DBI_CR_Y2R_PRE_0_SHIFT)
+#define DBI_CR_Y2R_PRE_1_SHIFT (10U)
+#define DBI_CR_Y2R_PRE_1_MASK (0x1ff << DBI_CR_Y2R_PRE_1_SHIFT)
+#define DBI_CR_Y2R_PRE_2_SHIFT (20U)
+#define DBI_CR_Y2R_PRE_2_MASK (0x1ff << DBI_CR_Y2R_PRE_2_SHIFT)
+#define DBI_CR_Y2R_EN (1 << 31U)
+
+/* 0x64 : dbi_yuv_rgb_config_1 */
+#define DBI_CR_Y2R_POS_0_SHIFT (0U)
+#define DBI_CR_Y2R_POS_0_MASK (0x1ff << DBI_CR_Y2R_POS_0_SHIFT)
+#define DBI_CR_Y2R_POS_1_SHIFT (10U)
+#define DBI_CR_Y2R_POS_1_MASK (0x1ff << DBI_CR_Y2R_POS_1_SHIFT)
+#define DBI_CR_Y2R_POS_2_SHIFT (20U)
+#define DBI_CR_Y2R_POS_2_MASK (0x1ff << DBI_CR_Y2R_POS_2_SHIFT)
+
+/* 0x68 : dbi_yuv_rgb_config_2 */
+#define DBI_CR_Y2R_MTX_00_SHIFT (0U)
+#define DBI_CR_Y2R_MTX_00_MASK (0xfff << DBI_CR_Y2R_MTX_00_SHIFT)
+#define DBI_CR_Y2R_MTX_01_SHIFT (12U)
+#define DBI_CR_Y2R_MTX_01_MASK (0xfff << DBI_CR_Y2R_MTX_01_SHIFT)
+#define DBI_CR_Y2R_MTX_02_L_SHIFT (24U)
+#define DBI_CR_Y2R_MTX_02_L_MASK (0xff << DBI_CR_Y2R_MTX_02_L_SHIFT)
+
+/* 0x6C : dbi_yuv_rgb_config_3 */
+#define DBI_CR_Y2R_MTX_02_U_SHIFT (0U)
+#define DBI_CR_Y2R_MTX_02_U_MASK (0xf << DBI_CR_Y2R_MTX_02_U_SHIFT)
+#define DBI_CR_Y2R_MTX_10_SHIFT (4U)
+#define DBI_CR_Y2R_MTX_10_MASK (0xfff << DBI_CR_Y2R_MTX_10_SHIFT)
+#define DBI_CR_Y2R_MTX_11_SHIFT (16U)
+#define DBI_CR_Y2R_MTX_11_MASK (0xfff << DBI_CR_Y2R_MTX_11_SHIFT)
+#define DBI_CR_Y2R_MTX_12_L_SHIFT (28U)
+#define DBI_CR_Y2R_MTX_12_L_MASK (0xf << DBI_CR_Y2R_MTX_12_L_SHIFT)
+
+/* 0x70 : dbi_yuv_rgb_config_4 */
+#define DBI_CR_Y2R_MTX_12_U_SHIFT (0U)
+#define DBI_CR_Y2R_MTX_12_U_MASK (0xff << DBI_CR_Y2R_MTX_12_U_SHIFT)
+#define DBI_CR_Y2R_MTX_20_SHIFT (8U)
+#define DBI_CR_Y2R_MTX_20_MASK (0xfff << DBI_CR_Y2R_MTX_20_SHIFT)
+#define DBI_CR_Y2R_MTX_21_SHIFT (20U)
+#define DBI_CR_Y2R_MTX_21_MASK (0xfff << DBI_CR_Y2R_MTX_21_SHIFT)
+
+/* 0x74 : dbi_yuv_rgb_config_5 */
+#define DBI_CR_Y2R_MTX_22_SHIFT (0U)
+#define DBI_CR_Y2R_MTX_22_MASK (0xfff << DBI_CR_Y2R_MTX_22_SHIFT)
+
+/* 0x80 : dbi_fifo_config_0 */
+#define DBI_DMA_TX_EN (1 << 0U)
+#define DBI_TX_FIFO_CLR (1 << 2U)
+#define DBI_TX_FIFO_OVERFLOW (1 << 4U)
+#define DBI_TX_FIFO_UNDERFLOW (1 << 5U)
+#define DBI_FIFO_YUV_MODE (1 << 28U)
+#define DBI_FIFO_FORMAT_SHIFT (29U)
+#define DBI_FIFO_FORMAT_MASK (0x7 << DBI_FIFO_FORMAT_SHIFT)
+
+/* 0x84 : dbi_fifo_config_1 */
+#define DBI_TX_FIFO_CNT_SHIFT (0U)
+#define DBI_TX_FIFO_CNT_MASK (0xf << DBI_TX_FIFO_CNT_SHIFT)
+#define DBI_TX_FIFO_TH_SHIFT (16U)
+#define DBI_TX_FIFO_TH_MASK (0x7 << DBI_TX_FIFO_TH_SHIFT)
+
+/* 0x88 : dbi_fifo_wdata */
+#define DBI_FIFO_WDATA_SHIFT (0U)
+#define DBI_FIFO_WDATA_MASK (0xffffffff << DBI_FIFO_WDATA_SHIFT)
+
+#endif /* __DBI_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dma_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dma_reg.h
new file mode 100644
index 00000000..83b0d5c1
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dma_reg.h
@@ -0,0 +1,190 @@
+/**
+ ******************************************************************************
+ * @file dma_reg.h
+ * @version V1.0
+ * @date 2022-06-20
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_DMA_H__
+#define __HARDWARE_DMA_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define DMA_INTSTATUS_OFFSET (0x0) /* DMA_IntStatus */
+#define DMA_INTTCSTATUS_OFFSET (0x4) /* DMA_IntTCStatus */
+#define DMA_INTTCCLEAR_OFFSET (0x8) /* DMA_IntTCClear */
+#define DMA_INTERRORSTATUS_OFFSET (0xC) /* DMA_IntErrorStatus */
+#define DMA_INTERRCLR_OFFSET (0x10) /* DMA_IntErrClr */
+#define DMA_RAWINTTCSTATUS_OFFSET (0x14) /* DMA_RawIntTCStatus */
+#define DMA_RAWINTERRORSTATUS_OFFSET (0x18) /* DMA_RawIntErrorStatus */
+#define DMA_ENBLDCHNS_OFFSET (0x1C) /* DMA_EnbldChns */
+#define DMA_SOFTBREQ_OFFSET (0x20) /* DMA_SoftBReq */
+#define DMA_SOFTSREQ_OFFSET (0x24) /* DMA_SoftSReq */
+#define DMA_SOFTLBREQ_OFFSET (0x28) /* DMA_SoftLBReq */
+#define DMA_SOFTLSREQ_OFFSET (0x2C) /* DMA_SoftLSReq */
+#define DMA_TOP_CONFIG_OFFSET (0x30) /* DMA_Top_Config */
+#define DMA_SYNC_OFFSET (0x34) /* DMA_Sync */
+
+#define DMA_CxSRCADDR_OFFSET (0x00) /* DMA_CxSrcAddr */
+#define DMA_CxDSTADDR_OFFSET (0x04) /* DMA_CxDstAddr */
+#define DMA_CxLLI_OFFSET (0x08) /* DMA_CxLLI */
+#define DMA_CxCONTROL_OFFSET (0x0C) /* DMA_CxControl */
+#define DMA_CxCONFIG_OFFSET (0x10) /* DMA_CxConfig */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : DMA_IntStatus */
+#define DMA_INTSTATUS_SHIFT (0U)
+#define DMA_INTSTATUS_MASK (0xff << DMA_INTSTATUS_SHIFT)
+
+/* 0x4 : DMA_IntTCStatus */
+#define DMA_INTTCSTATUS_SHIFT (0U)
+#define DMA_INTTCSTATUS_MASK (0xff << DMA_INTTCSTATUS_SHIFT)
+
+/* 0x8 : DMA_IntTCClear */
+#define DMA_INTTCCLEAR_SHIFT (0U)
+#define DMA_INTTCCLEAR_MASK (0xff << DMA_INTTCCLEAR_SHIFT)
+
+/* 0xC : DMA_IntErrorStatus */
+#define DMA_INTERRORSTATUS_SHIFT (0U)
+#define DMA_INTERRORSTATUS_MASK (0xff << DMA_INTERRORSTATUS_SHIFT)
+
+/* 0x10 : DMA_IntErrClr */
+#define DMA_INTERRCLR_SHIFT (0U)
+#define DMA_INTERRCLR_MASK (0xff << DMA_INTERRCLR_SHIFT)
+
+/* 0x14 : DMA_RawIntTCStatus */
+#define DMA_RAWINTTCSTATUS_SHIFT (0U)
+#define DMA_RAWINTTCSTATUS_MASK (0xff << DMA_RAWINTTCSTATUS_SHIFT)
+
+/* 0x18 : DMA_RawIntErrorStatus */
+#define DMA_RAWINTERRORSTATUS_SHIFT (0U)
+#define DMA_RAWINTERRORSTATUS_MASK (0xff << DMA_RAWINTERRORSTATUS_SHIFT)
+
+/* 0x1C : DMA_EnbldChns */
+#define DMA_ENABLEDCHANNELS_SHIFT (0U)
+#define DMA_ENABLEDCHANNELS_MASK (0xff << DMA_ENABLEDCHANNELS_SHIFT)
+
+/* 0x20 : DMA_SoftBReq */
+#define DMA_SOFTBREQ_SHIFT (0U)
+#define DMA_SOFTBREQ_MASK (0xffffffff << DMA_SOFTBREQ_SHIFT)
+
+/* 0x24 : DMA_SoftSReq */
+#define DMA_SOFTSREQ_SHIFT (0U)
+#define DMA_SOFTSREQ_MASK (0xffffffff << DMA_SOFTSREQ_SHIFT)
+
+/* 0x28 : DMA_SoftLBReq */
+#define DMA_SOFTLBREQ_SHIFT (0U)
+#define DMA_SOFTLBREQ_MASK (0xffffffff << DMA_SOFTLBREQ_SHIFT)
+
+/* 0x2C : DMA_SoftLSReq */
+#define DMA_SOFTLSREQ_SHIFT (0U)
+#define DMA_SOFTLSREQ_MASK (0xffffffff << DMA_SOFTLSREQ_SHIFT)
+
+/* 0x30 : DMA_Top_Config */
+#define DMA_E (1 << 0U)
+#define DMA_M (1 << 1U)
+
+/* 0x34 : DMA_Sync */
+#define DMA_SYNC_SHIFT (0U)
+#define DMA_SYNC_MASK (0xffffffff << DMA_SYNC_SHIFT)
+
+/* 0x100 : DMA_CxSrcAddr */
+#define DMA_SRCADDR_SHIFT (0U)
+#define DMA_SRCADDR_MASK (0xffffffff << DMA_SRCADDR_SHIFT)
+
+/* 0x104 : DMA_CxDstAddr */
+#define DMA_DSTADDR_SHIFT (0U)
+#define DMA_DSTADDR_MASK (0xffffffff << DMA_DSTADDR_SHIFT)
+
+/* 0x108 : DMA_CxLLI */
+#define DMA_LLI_SHIFT (0U)
+#define DMA_LLI_MASK (0xffffffff << DMA_LLI_SHIFT)
+
+/* 0x10C : DMA_CxControl */
+#define DMA_TRANSFERSIZE_SHIFT (0U)
+#define DMA_TRANSFERSIZE_MASK (0xfff << DMA_TRANSFERSIZE_SHIFT)
+#define DMA_SBSIZE_SHIFT (12U)
+#if defined(BL602)
+#define DMA_SBSIZE_MASK (0x7 << DMA_SBSIZE_SHIFT)
+#else
+#define DMA_SBSIZE_MASK (0x3 << DMA_SBSIZE_SHIFT)
+#define DMA_DST_MIN_MODE (1 << 14U)
+#endif
+#define DMA_DBSIZE_SHIFT (15U)
+#if defined(BL602)
+#define DMA_DBSIZE_MASK (0x7 << DMA_DBSIZE_SHIFT)
+#else
+#define DMA_DBSIZE_MASK (0x3 << DMA_DBSIZE_SHIFT)
+#define DMA_DST_ADD_MODE (1 << 17U)
+#endif
+#define DMA_SWIDTH_SHIFT (18U)
+#if defined(BL602)
+#define DMA_SWIDTH_MASK (0x7 << DMA_SWIDTH_SHIFT)
+#else
+#define DMA_SWIDTH_MASK (0x3 << DMA_SWIDTH_SHIFT)
+#endif
+#define DMA_DWIDTH_SHIFT (21U)
+#if defined(BL602)
+#define DMA_DWIDTH_MASK (0x7 << DMA_DWIDTH_SHIFT)
+#define DMA_SLARGERD (1 << 24U)
+#else
+#define DMA_DWIDTH_MASK (0x3 << DMA_DWIDTH_SHIFT)
+#define DMA_FIX_CNT_SHIFT (23U)
+#define DMA_FIX_CNT_MASK (0x7 << DMA_FIX_CNT_SHIFT)
+#endif
+#define DMA_SI (1 << 26U)
+#define DMA_DI (1 << 27U)
+#define DMA_PROT_SHIFT (28U)
+#define DMA_PROT_MASK (0x7 << DMA_PROT_SHIFT)
+#define DMA_I (1 << 31U)
+
+/* 0x110 : DMA_CxConfig */
+#define DMA_E (1 << 0U)
+#define DMA_SRCPERIPHERAL_SHIFT (1U)
+#define DMA_SRCPERIPHERAL_MASK (0x1f << DMA_SRCPERIPHERAL_SHIFT)
+#define DMA_DSTPERIPHERAL_SHIFT (6U)
+#define DMA_DSTPERIPHERAL_MASK (0x1f << DMA_DSTPERIPHERAL_SHIFT)
+#define DMA_FLOWCNTRL_SHIFT (11U)
+#define DMA_FLOWCNTRL_MASK (0x7 << DMA_FLOWCNTRL_SHIFT)
+#define DMA_IE (1 << 14U)
+#define DMA_ITC (1 << 15U)
+#define DMA_L (1 << 16U)
+#define DMA_A (1 << 17U)
+#define DMA_H (1 << 18U)
+#define DMA_LLICOUNTER_SHIFT (20U)
+#define DMA_LLICOUNTER_MASK (0x3ff << DMA_LLICOUNTER_SHIFT)
+
+#endif /* __HARDWARE_DMA_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dtsrc_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dtsrc_reg.h
new file mode 100644
index 00000000..1c3a21c7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/dtsrc_reg.h
@@ -0,0 +1,168 @@
+/**
+ ******************************************************************************
+ * @file dtsrc_reg.h
+ * @version V1.0
+ * @date 2022-12-15
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_DTSRC_H__
+#define __HARDWARE_DTSRC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define DTSRC_CONFIG_OFFSET (0x0)/* config */
+#define DTSRC_FRAME_SIZE_H_OFFSET (0x4)/* frame_size_h */
+#define DTSRC_FRAME_SIZE_V_OFFSET (0x8)/* frame_size_v */
+#define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC)/* frame_size_cea_861 */
+#define DTSRC_PIX_DATA_RANGE_OFFSET (0x10)/* pix_data_range */
+#define DTSRC_PIX_DATA_STEP_OFFSET (0x14)/* pix_data_step */
+#define DTSRC_AXI2DVP_SETTING_OFFSET (0x20)/* axi2dvp_setting */
+#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24)/* axi2dvp_start_addr_by */
+#define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28)/* axi2dvp_burst_cnt */
+#define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C)/* axi2dvp_status */
+#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30)/* axi2dvp_swap_addr_by */
+#define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34)/* axi2dvp_prefetch */
+#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38)/* snsr2dvp_wait_pos */
+#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40)/* axi2dvp_start_addr_uv */
+#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44)/* axi2dvp_swap_addr_uv */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : config */
+#define DTSRC_CR_ENABLE (1<<0U)
+#define DTSRC_CR_AXI_EN (1<<1U)
+#define DTSRC_CR_MODE_CEA_861 (1<<2U)
+#define DTSRC_CR_SNSR_EN (1<<3U)
+#define DTSRC_CR_SNSR_HSYNC_INV (1<<4U)
+#define DTSRC_CR_SNSR_VSYNC_INV (1<<5U)
+#define DTSRC_CR_AXI_SWAP_MODE (1<<7U)
+#define DTSRC_CR_AXI_SWAP_IDX_SEL_SHIFT (8U)
+#define DTSRC_CR_AXI_SWAP_IDX_SEL_MASK (0xf<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_EF_CTRL_H__
+#define __HARDWARE_EF_CTRL_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800) /* efuse control */
+#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804) /* efuse cycle config 0 */
+#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808) /* efuse cycle config 1 */
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C) /* efuse manual config 1 */
+#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810) /* efuse status */
+#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814) /* efuse config 0 */
+
+/* 0x800 :efuse control */
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MASK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMASK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMASK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
+//#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY
+#define EF_CTRL_EF_IF_0_BUSY_POS (2U)
+#define EF_CTRL_EF_IF_0_BUSY_LEN (1U)
+#define EF_CTRL_EF_IF_0_BUSY_MASK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
+#define EF_CTRL_EF_IF_0_BUSY_UMASK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
+#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW
+#define EF_CTRL_EF_IF_0_RW_POS (3U)
+#define EF_CTRL_EF_IF_0_RW_LEN (1U)
+#define EF_CTRL_EF_IF_0_RW_MASK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
+#define EF_CTRL_EF_IF_0_RW_UMASK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
+#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG
+#define EF_CTRL_EF_IF_0_TRIG_POS (4U)
+#define EF_CTRL_EF_IF_0_TRIG_LEN (1U)
+#define EF_CTRL_EF_IF_0_TRIG_MASK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
+#define EF_CTRL_EF_IF_0_TRIG_UMASK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
+#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN
+#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_MASK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_UMASK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_MASK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMASK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL EF_CTRL_EF_CLK_SAHB_DATA_SEL
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS (7U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MASK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMASK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
+#endif
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MASK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMASK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
+#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG
+#define EF_CTRL_EF_IF_POR_DIG_POS (16U)
+#define EF_CTRL_EF_IF_POR_DIG_LEN (1U)
+#define EF_CTRL_EF_IF_POR_DIG_MASK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
+#define EF_CTRL_EF_IF_POR_DIG_UMASK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE EF_CTRL_EF_CLK_SAHB_DATA_GATE
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS (17U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MASK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMASK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
+#else
+#define EF_CTRL_EF_PCLK_FORCE_ON EF_CTRL_EF_PCLK_FORCE_ON
+#define EF_CTRL_EF_PCLK_FORCE_ON_POS (17U)
+#define EF_CTRL_EF_PCLK_FORCE_ON_LEN (1U)
+#define EF_CTRL_EF_PCLK_FORCE_ON_MASK (((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS)
+#define EF_CTRL_EF_PCLK_FORCE_ON_UMASK (~(((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS))
+#endif
+#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN
+#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_MASK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_UMASK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MASK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMASK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
+#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT
+#define EF_CTRL_EF_IF_0_INT_POS (20U)
+#define EF_CTRL_EF_IF_0_INT_LEN (1U)
+#define EF_CTRL_EF_IF_0_INT_MASK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
+#define EF_CTRL_EF_IF_0_INT_UMASK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
+#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR
+#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U)
+#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U)
+#define EF_CTRL_EF_IF_0_INT_CLR_MASK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
+#define EF_CTRL_EF_IF_0_INT_CLR_UMASK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
+#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET
+#define EF_CTRL_EF_IF_0_INT_SET_POS (22U)
+#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U)
+#define EF_CTRL_EF_IF_0_INT_SET_MASK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
+#define EF_CTRL_EF_IF_0_INT_SET_UMASK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_MASK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMASK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
+
+/* 0x80C : ef_if_0_manual, 606P and 808 manual config is the same but not need witch clock */
+#if defined(BL702) || defined(BL602) || defined(BL702L) || defined(BL606P) || defined(BL808)
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C)
+#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS (0U)
+#define EF_CTRL_EF_IF_A_LEN (10U)
+#define EF_CTRL_EF_IF_A_MASK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMASK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS (10U)
+#define EF_CTRL_EF_IF_PD_LEN (1U)
+#define EF_CTRL_EF_IF_PD_MASK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMASK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS (11U)
+#define EF_CTRL_EF_IF_PS_LEN (1U)
+#define EF_CTRL_EF_IF_PS_MASK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMASK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS (12U)
+#define EF_CTRL_EF_IF_STROBE_LEN (1U)
+#define EF_CTRL_EF_IF_STROBE_MASK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMASK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS (13U)
+#define EF_CTRL_EF_IF_PGENB_LEN (1U)
+#define EF_CTRL_EF_IF_PGENB_MASK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMASK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS (14U)
+#define EF_CTRL_EF_IF_LOAD_LEN (1U)
+#define EF_CTRL_EF_IF_LOAD_MASK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMASK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS (15U)
+#define EF_CTRL_EF_IF_CSB_LEN (1U)
+#define EF_CTRL_EF_IF_CSB_MASK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMASK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q
+#define EF_CTRL_EF_IF_0_Q_POS (16U)
+#define EF_CTRL_EF_IF_0_Q_LEN (8U)
+#define EF_CTRL_EF_IF_0_Q_MASK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
+#define EF_CTRL_EF_IF_0_Q_UMASK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MASK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMASK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+#else
+/* 0x80C : ef_if_0_manual_0 */
+#define EF_CTRL_EF_IF_0_MANUAL_0_OFFSET (0x80C)
+#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS (0U)
+#define EF_CTRL_EF_IF_A_LEN (12U)
+#define EF_CTRL_EF_IF_A_MASK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMASK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS (18U)
+#define EF_CTRL_EF_IF_PD_LEN (1U)
+#define EF_CTRL_EF_IF_PD_MASK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMASK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS (19U)
+#define EF_CTRL_EF_IF_PS_LEN (1U)
+#define EF_CTRL_EF_IF_PS_MASK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMASK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS (20U)
+#define EF_CTRL_EF_IF_STROBE_LEN (1U)
+#define EF_CTRL_EF_IF_STROBE_MASK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMASK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS (21U)
+#define EF_CTRL_EF_IF_PGENB_LEN (1U)
+#define EF_CTRL_EF_IF_PGENB_MASK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMASK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS (22U)
+#define EF_CTRL_EF_IF_LOAD_LEN (1U)
+#define EF_CTRL_EF_IF_LOAD_MASK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMASK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS (23U)
+#define EF_CTRL_EF_IF_CSB_LEN (1U)
+#define EF_CTRL_EF_IF_CSB_MASK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMASK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MASK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMASK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+#endif
+
+#if defined(BL606P) || defined(BL808)
+/* 0x900 : ef_if_ctrl_1 */
+#define EF_CTRL_EF_IF_CTRL_1_OFFSET (0x900)
+#define EF_CTRL_EF_IF_1_BUSY EF_CTRL_EF_IF_1_BUSY
+#define EF_CTRL_EF_IF_1_BUSY_POS (2U)
+#define EF_CTRL_EF_IF_1_BUSY_LEN (1U)
+#define EF_CTRL_EF_IF_1_BUSY_MASK (((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS)
+#define EF_CTRL_EF_IF_1_BUSY_UMASK (~(((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS))
+#define EF_CTRL_EF_IF_1_RW EF_CTRL_EF_IF_1_RW
+#define EF_CTRL_EF_IF_1_RW_POS (3U)
+#define EF_CTRL_EF_IF_1_RW_LEN (1U)
+#define EF_CTRL_EF_IF_1_RW_MASK (((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS)
+#define EF_CTRL_EF_IF_1_RW_UMASK (~(((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS))
+#define EF_CTRL_EF_IF_1_TRIG EF_CTRL_EF_IF_1_TRIG
+#define EF_CTRL_EF_IF_1_TRIG_POS (4U)
+#define EF_CTRL_EF_IF_1_TRIG_LEN (1U)
+#define EF_CTRL_EF_IF_1_TRIG_MASK (((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS)
+#define EF_CTRL_EF_IF_1_TRIG_UMASK (~(((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS))
+#define EF_CTRL_EF_IF_1_MANUAL_EN EF_CTRL_EF_IF_1_MANUAL_EN
+#define EF_CTRL_EF_IF_1_MANUAL_EN_POS (5U)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_LEN (1U)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_MASK (((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_UMASK (~(((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_1_CYC_MODIFY EF_CTRL_EF_IF_1_CYC_MODIFY
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_POS (6U)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_LEN (1U)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_MASK (((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_UMASK (~(((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS))
+#define EF_CTRL_EF_IF_1_INT EF_CTRL_EF_IF_1_INT
+#define EF_CTRL_EF_IF_1_INT_POS (20U)
+#define EF_CTRL_EF_IF_1_INT_LEN (1U)
+#define EF_CTRL_EF_IF_1_INT_MASK (((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS)
+#define EF_CTRL_EF_IF_1_INT_UMASK (~(((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS))
+#define EF_CTRL_EF_IF_1_INT_CLR EF_CTRL_EF_IF_1_INT_CLR
+#define EF_CTRL_EF_IF_1_INT_CLR_POS (21U)
+#define EF_CTRL_EF_IF_1_INT_CLR_LEN (1U)
+#define EF_CTRL_EF_IF_1_INT_CLR_MASK (((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS)
+#define EF_CTRL_EF_IF_1_INT_CLR_UMASK (~(((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS))
+#define EF_CTRL_EF_IF_1_INT_SET EF_CTRL_EF_IF_1_INT_SET
+#define EF_CTRL_EF_IF_1_INT_SET_POS (22U)
+#define EF_CTRL_EF_IF_1_INT_SET_LEN (1U)
+#define EF_CTRL_EF_IF_1_INT_SET_MASK (((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS)
+#define EF_CTRL_EF_IF_1_INT_SET_UMASK (~(((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS))
+
+/* 0x904 : ef_if_1_manual */
+#define EF_CTRL_EF_IF_1_MANUAL_OFFSET (0x904)
+#define EF_CTRL_EF_IF_1_Q EF_CTRL_EF_IF_1_Q
+#define EF_CTRL_EF_IF_1_Q_POS (16U)
+#define EF_CTRL_EF_IF_1_Q_LEN (8U)
+#define EF_CTRL_EF_IF_1_Q_MASK (((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS)
+#define EF_CTRL_EF_IF_1_Q_UMASK (~(((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS))
+
+/* 0x908 : ef_if_1_status */
+#define EF_CTRL_EF_IF_1_STATUS_OFFSET (0x908)
+#define EF_CTRL_EF_IF_1_STATUS EF_CTRL_EF_IF_1_STATUS
+#define EF_CTRL_EF_IF_1_STATUS_POS (0U)
+#define EF_CTRL_EF_IF_1_STATUS_LEN (32U)
+#define EF_CTRL_EF_IF_1_STATUS_MASK (((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS)
+#define EF_CTRL_EF_IF_1_STATUS_UMASK (~(((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS))
+#endif
+
+#endif /* __HARDWARE_EF_CTRL_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/emac_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/emac_reg.h
new file mode 100644
index 00000000..d41765cb
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/emac_reg.h
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file emac_reg.h
+ * @version V1.0
+ * @date 2022-09-27
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2022 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_EMAC_H__
+#define __HARDWARE_EMAC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#define EMAC_MODE_OFFSET (0x0)
+#define EMAC_INT_SOURCE_OFFSET (0x4)
+#define EMAC_INT_MASK_OFFSET (0x8)
+#define EMAC_IPGT_OFFSET (0xC)
+#define EMAC_PACKETLEN_OFFSET (0x18)
+#define EMAC_COLLCONFIG_OFFSET (0x1C)
+#define EMAC_TX_BD_NUM_OFFSET (0x20)
+#define EMAC_MIIMODE_OFFSET (0x28)
+#define EMAC_MIICOMMAND_OFFSET (0x2C)
+#define EMAC_MIIADDRESS_OFFSET (0x30)
+#define EMAC_MIITX_DATA_OFFSET (0x34)
+#define EMAC_MIIRX_DATA_OFFSET (0x38)
+#define EMAC_MIISTATUS_OFFSET (0x3C)
+#define EMAC_MAC_ADDR0_OFFSET (0x40)
+#define EMAC_MAC_ADDR1_OFFSET (0x44)
+#define EMAC_HASH0_ADDR_OFFSET (0x48)
+#define EMAC_HASH1_ADDR_OFFSET (0x4C)
+#define EMAC_TXCTRL_OFFSET (0x50)
+#define EMAC_DMA_DESC_OFFSET (0x400)
+
+/* 0x0 : EMAC MODE config */
+#define EMAC_RX_EN (1 << 0U)
+#define EMAC_TX_EN (1 << 1U)
+#define EMAC_NOPRE (1 << 2U)
+#define EMAC_BRO (1 << 3U)
+#define EMAC_PRO (1 << 5U)
+#define EMAC_IFG (1 << 6U)
+#define EMAC_FULLD (1 << 10U)
+#define EMAC_CRCEN (1 << 13U)
+#define EMAC_HUGEN (1 << 14U)
+#define EMAC_PAD (1 << 15U)
+#define EMAC_RECSMALL (1 << 16U)
+#define EMAC_RMII_EN (1 << 17U)
+
+/* 0x4 : INT_SOURCE */
+#define EMAC_TXB (1 << 0U)
+#define EMAC_TXE (1 << 1U)
+#define EMAC_RXB (1 << 2U)
+#define EMAC_RXE (1 << 3U)
+#define EMAC_BUSY (1 << 4U)
+#define EMAC_TXC (1 << 5U)
+#define EMAC_RXC (1 << 6U)
+
+/* 0x8 : INT_MASK */
+#define EMAC_TXB_M (1 << 0U)
+#define EMAC_TXE_M (1 << 1U)
+#define EMAC_RXB_M (1 << 2U)
+#define EMAC_RXE_M (1 << 3U)
+#define EMAC_BUSY_M (1 << 4U)
+#define EMAC_TXC_M (1 << 5U)
+#define EMAC_RXC_M (1 << 6U)
+
+/* 0xC : IPGT */
+#define EMAC_IPGT_SHIFT (0U)
+#define EMAC_IPGT_MASK (0x7f << EMAC_IPGT_SHIFT)
+
+/* 0x18 : PACKETLEN */
+#define EMAC_MAXFL_SHIFT (0U)
+#define EMAC_MAXFL_MASK (0xffff << EMAC_MAXFL_SHIFT)
+#define EMAC_MINFL_SHIFT (16U)
+#define EMAC_MINFL_MASK (0xffff << EMAC_MINFL_SHIFT)
+
+/* 0x1C : COLLCONFIG */
+#define EMAC_COLLVALID_SHIFT (0U)
+#define EMAC_COLLVALID_MASK (0x3F << EMAC_COLLVALID_SHIFT)
+#define EMAC_MAXRET_SHIFT (16U)
+#define EMAC_MAXRET_MASK (0xF << EMAC_MAXRET_SHIFT)
+
+/* 0x20 : TX_BD_NUM */
+#define EMAC_TXBDNUM_SHIFT (0U)
+#define EMAC_TXBDNUM_MASK (0xff << EMAC_TXBDNUM_SHIFT)
+#define EMAC_TXBDPTR_SHIFT (16U)
+#define EMAC_TXBDPTR_MASK (0x7f << EMAC_TXBDPTR_SHIFT)
+#define EMAC_RXBDPTR_SHIFT (24U)
+#define EMAC_RXBDPTR_MASK (0x7f << EMAC_RXBDPTR_SHIFT)
+
+/* 0x28 : MIIMODE */
+#define EMAC_CLKDIV_SHIFT (0U)
+#define EMAC_CLKDIV_MASK (0xff << EMAC_CLKDIV_SHIFT)
+#define EMAC_MIINOPRE (1 << 8U)
+
+/* 0x2C : MIICOMMAND */
+#define EMAC_SCANSTAT (1 << 0U)
+#define EMAC_RSTAT (1 << 1U)
+#define EMAC_WCTRLDATA (1 << 2U)
+
+/* 0x30 : MIIADDRESS */
+#define EMAC_FIAD_SHIFT (0U)
+#define EMAC_FIAD_MASK (0x1f << EMAC_FIAD_SHIFT)
+#define EMAC_RGAD_SHIFT (8U)
+#define EMAC_RGAD_MASK (0x1f << EMAC_RGAD_SHIFT)
+
+/* 0x34 : MIITX_DATA */
+#define EMAC_CTRLDATA_SHIFT (0U)
+#define EMAC_CTRLDATA_MASK (0xffff << EMAC_CTRLDATA_SHIFT)
+
+/* 0x38 : MIIRX_DATA */
+#define EMAC_PRSD_SHIFT (0U)
+#define EMAC_PRSD_MASK (0xffff << EMAC_PRSD_SHIFT)
+
+/* 0x3C : MIISTATUS */
+#define EMAC_MIIM_LINKFAIL (1 << 0U)
+#define EMAC_MIIM_BUSY (1 << 1U)
+
+/* 0x40 : MAC_ADDR0 */
+#define EMAC_MAC_B5_SHIFT (0U)
+#define EMAC_MAC_B5_MASK (0xff << EMAC_MAC_B5_SHIFT)
+#define EMAC_MAC_B4_SHIFT (8U)
+#define EMAC_MAC_B4_MASK (0xff << EMAC_MAC_B4_SHIFT)
+#define EMAC_MAC_B3_SHIFT (16U)
+#define EMAC_MAC_B3_MASK (0xff << EMAC_MAC_B3_SHIFT)
+#define EMAC_MAC_B2_SHIFT (24U)
+#define EMAC_MAC_B2_MASK (0xff << EMAC_MAC_B2_SHIFT)
+
+/* 0x44 : MAC_ADDR1 */
+#define EMAC_MAC_B1_SHIFT (0U)
+#define EMAC_MAC_B1_MASK (0xff << EMAC_MAC_B1_SHIFT)
+#define EMAC_MAC_B0_SHIFT (8U)
+#define EMAC_MAC_B0_MASK (0xff << EMAC_MAC_B0_SHIFT)
+
+/* 0x48 : HASH0_ADDR */
+#define EMAC_HASH0_SHIFT (0U)
+#define EMAC_HASH0_MASK (0xffffffff << EMAC_HASH0_SHIFT)
+
+/* 0x4C : HASH1_ADDR */
+#define EMAC_HASH1_SHIFT (0U)
+#define EMAC_HASH1_MASK (0xffffffff << EMAC_HASH1_SHIFT)
+
+/* 0x50 : TXCTRL */
+#define EMAC_TXPAUSETV_SHIFT (0U)
+#define EMAC_TXPAUSETV_MASK (0xffff << EMAC_TXPAUSETV_SHIFT)
+#define EMAC_TXPAUSERQ_SHIFT (16U)
+#define EMAC_TXPAUSERQ_MASK (0x1 << EMAC_TXPAUSETV_SHIFT)
+
+/* 0x400 :EAMC DMA BD DESC */
+/* EMAC TX BD DESC BASE: (TX_BD_NUM * 8) */
+#define EMAC_BD_TX_CS_SHIFT (0) /*!< Carrier Sense Lost */
+#define EMAC_BD_TX_CS_MASK (1 << EMAC_BD_TX_CS_SHIFT)
+#define EMAC_BD_TX_DF_SHIFT (1) /*!< Defer Indication */
+#define EMAC_BD_TX_DF_MASK (1 << EMAC_BD_TX_DF_SHIFT)
+#define EMAC_BD_TX_LC_SHIFT (2) /*!< Late Collision */
+#define EMAC_BD_TX_LC_MASK (1 << EMAC_BD_TX_LC_SHIFT)
+#define EMAC_BD_TX_RL_SHIFT (3) /*!< Retransmission Limit */
+#define EMAC_BD_TX_RL_MASK (1 << EMAC_BD_TX_RL_SHIFT)
+#define EMAC_BD_TX_RTRY_SHIFT (4) /*!< Retry Count */
+#define EMAC_BD_TX_RTRY_MASK (4 << EMAC_BD_TX_RTRY_SHIFT)
+#define EMAC_BD_TX_UR_SHIFT (8) /*!< Underrun */
+#define EMAC_BD_TX_UR_MASK (1 << EMAC_BD_TX_UR_SHIFT)
+#define EMAC_BD_TX_EOF_SHIFT (10) /*!< EOF */
+#define EMAC_BD_TX_EOF_MASK (1 << EMAC_BD_TX_EOF_SHIFT)
+#define EMAC_BD_TX_CRC_SHIFT (11) /*!< CRC Enable */
+#define EMAC_BD_TX_CRC_MASK (1 << EMAC_BD_TX_CRC_SHIFT)
+#define EMAC_BD_TX_PAD_SHIFT (12) /*!< PAD enable */
+#define EMAC_BD_TX_PAD_MASK (1 << EMAC_BD_TX_PAD_SHIFT)
+#define EMAC_BD_TX_WR_SHIFT (13) /*!< Wrap */
+#define EMAC_BD_TX_WR_MASK (1 << EMAC_BD_TX_WR_SHIFT)
+#define EMAC_BD_TX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */
+#define EMAC_BD_TX_IRQ_MASK (1 << EMAC_BD_TX_IRQ_SHIFT)
+#define EMAC_BD_TX_RD_SHIFT (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */
+#define EMAC_BD_TX_RD_MASK (1 << EMAC_BD_TX_RD_SHIFT)
+#define EMAC_BD_TX_LEN_SHIFT (16) /*!< TX Data buffer length */
+#define EMAC_BD_TX_LEN_MASK (0xffff << EMAC_BD_TX_LEN_SHIFT)
+
+/* RX BD DESC BASE: ((TX_BD_NUM + RX_BD_NUM) * 8) */
+#define EMAC_BD_RX_LC_SHIFT (0) /*!< Late Collision */
+#define EMAC_BD_RX_LC_MASK (1 << EMAC_BD_RX_LC_SHIFT)
+#define EMAC_BD_RX_CRC_SHIFT (1) /*!< RX CRC Error */
+#define EMAC_BD_RX_CRC_MASK (1 << EMAC_BD_RX_CRC_SHIFT)
+#define EMAC_BD_RX_SF_SHIFT (2) /*!< Short Frame */
+#define EMAC_BD_RX_SF_MASK (1 << EMAC_BD_RX_SF_SHIFT)
+#define EMAC_BD_RX_TL_SHIFT (3) /*!< Too Long */
+#define EMAC_BD_RX_TL_MASK (1 << EMAC_BD_RX_TL_SHIFT)
+#define EMAC_BD_RX_DN_SHIFT (4) /*!< Dribble Nibble */
+#define EMAC_BD_RX_DN_MASK (1 << EMAC_BD_RX_DN_SHIFT)
+#define EMAC_BD_RX_RE_SHIFT (5) /*!< Receive Error */
+#define EMAC_BD_RX_RE_MASK (1 << EMAC_BD_RX_RE_SHIFT)
+#define EMAC_BD_RX_OR_SHIFT (6) /*!< Overrun */
+#define EMAC_BD_RX_OR_MASK (1 << EMAC_BD_RX_OR_SHIFT)
+#define EMAC_BD_RX_M_SHIFT (7) /*!< Miss */
+#define EMAC_BD_RX_M_MASK (1 << EMAC_BD_RX_M_SHIFT)
+#define EMAC_BD_RX_CF_SHIFT (8) /*!< Control Frame Received */
+#define EMAC_BD_RX_CF_MASK (1 << EMAC_BD_RX_CF_SHIFT)
+#define EMAC_BD_RX_WR_SHIFT (13) /*!< Wrap */
+#define EMAC_BD_RX_WR_MASK (1 << EMAC_BD_RX_WR_SHIFT)
+#define EMAC_BD_RX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */
+#define EMAC_BD_RX_IRQ_MASK (1 << EMAC_BD_RX_IRQ_SHIFT)
+#define EMAC_BD_RX_E_SHIFT (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */
+#define EMAC_BD_RX_E_MASK (1 << EMAC_BD_RX_E_SHIFT)
+#define EMAC_BD_RX_LEN_SHIFT (16) /*!< RX Data buffer length */
+#define EMAC_BD_RX_LEN_MASK (0xffff << EMAC_BD_RX_LEN_SHIFT)
+
+/* MAX BD DESC 0x7FF */
+
+#endif /* __HARDWARE_EMAC_H__ */
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/gpio_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/gpio_reg.h
new file mode 100644
index 00000000..bfba6cd8
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/gpio_reg.h
@@ -0,0 +1,2042 @@
+/**
+ ******************************************************************************
+ * @file gpio_reg.h
+ * @version V1.0
+ * @date 2022-08-03
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_GPIO_H__
+#define __HARDWARE_GPIO_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#if defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+#define GLB_GPIO_CFG0_OFFSET (0x8C4)/* gpio_cfg0 */
+#define GLB_GPIO_CFG1_OFFSET (0x8C8)/* gpio_cfg1 */
+#define GLB_GPIO_CFG2_OFFSET (0x8CC)/* gpio_cfg2 */
+#define GLB_GPIO_CFG3_OFFSET (0x8D0)/* gpio_cfg3 */
+#define GLB_GPIO_CFG4_OFFSET (0x8D4)/* gpio_cfg4 */
+#define GLB_GPIO_CFG5_OFFSET (0x8D8)/* gpio_cfg5 */
+#define GLB_GPIO_CFG6_OFFSET (0x8DC)/* gpio_cfg6 */
+#define GLB_GPIO_CFG7_OFFSET (0x8E0)/* gpio_cfg7 */
+#define GLB_GPIO_CFG8_OFFSET (0x8E4)/* gpio_cfg8 */
+#define GLB_GPIO_CFG9_OFFSET (0x8E8)/* gpio_cfg9 */
+#define GLB_GPIO_CFG10_OFFSET (0x8EC)/* gpio_cfg10 */
+#define GLB_GPIO_CFG11_OFFSET (0x8F0)/* gpio_cfg11 */
+#define GLB_GPIO_CFG12_OFFSET (0x8F4)/* gpio_cfg12 */
+#define GLB_GPIO_CFG13_OFFSET (0x8F8)/* gpio_cfg13 */
+#define GLB_GPIO_CFG14_OFFSET (0x8FC)/* gpio_cfg14 */
+#define GLB_GPIO_CFG15_OFFSET (0x900)/* gpio_cfg15 */
+#define GLB_GPIO_CFG16_OFFSET (0x904)/* gpio_cfg16 */
+#define GLB_GPIO_CFG17_OFFSET (0x908)/* gpio_cfg17 */
+#define GLB_GPIO_CFG18_OFFSET (0x90C)/* gpio_cfg18 */
+#define GLB_GPIO_CFG19_OFFSET (0x910)/* gpio_cfg19 */
+#define GLB_GPIO_CFG20_OFFSET (0x914)/* gpio_cfg20 */
+#define GLB_GPIO_CFG21_OFFSET (0x918)/* gpio_cfg21 */
+#define GLB_GPIO_CFG22_OFFSET (0x91C)/* gpio_cfg22 */
+#define GLB_GPIO_CFG23_OFFSET (0x920)/* gpio_cfg23 */
+#define GLB_GPIO_CFG24_OFFSET (0x924)/* gpio_cfg24 */
+#define GLB_GPIO_CFG25_OFFSET (0x928)/* gpio_cfg25 */
+#define GLB_GPIO_CFG26_OFFSET (0x92C)/* gpio_cfg26 */
+#define GLB_GPIO_CFG27_OFFSET (0x930)/* gpio_cfg27 */
+#define GLB_GPIO_CFG28_OFFSET (0x934)/* gpio_cfg28 */
+#define GLB_GPIO_CFG29_OFFSET (0x938)/* gpio_cfg29 */
+#define GLB_GPIO_CFG30_OFFSET (0x93C)/* gpio_cfg30 */
+#define GLB_GPIO_CFG31_OFFSET (0x940)/* gpio_cfg31 */
+#define GLB_GPIO_CFG32_OFFSET (0x944)/* gpio_cfg32 */
+#define GLB_GPIO_CFG33_OFFSET (0x948)/* gpio_cfg33 */
+#define GLB_GPIO_CFG34_OFFSET (0x94C)/* gpio_cfg34 */
+#define GLB_GPIO_CFG35_OFFSET (0x950)/* gpio_cfg35 */
+#define GLB_GPIO_CFG36_OFFSET (0x954)/* gpio_cfg36 */
+#define GLB_GPIO_CFG37_OFFSET (0x958)/* gpio_cfg37 */
+#define GLB_GPIO_CFG38_OFFSET (0x95C)/* gpio_cfg38 */
+#define GLB_GPIO_CFG39_OFFSET (0x960)/* gpio_cfg39 */
+#define GLB_GPIO_CFG40_OFFSET (0x964)/* gpio_cfg40 */
+#define GLB_GPIO_CFG41_OFFSET (0x968)/* gpio_cfg41 */
+#define GLB_GPIO_CFG42_OFFSET (0x96C)/* gpio_cfg42 */
+#define GLB_GPIO_CFG43_OFFSET (0x970)/* gpio_cfg43 */
+#define GLB_GPIO_CFG44_OFFSET (0x974)/* gpio_cfg44 */
+#define GLB_GPIO_CFG45_OFFSET (0x978)/* gpio_cfg45 */
+#define GLB_GPIO_CFG46_OFFSET (0x97C)/* gpio_cfg46 */
+#define GLB_GPIO_CFG47_OFFSET (0x980)/* gpio_cfg47 */
+#define GLB_GPIO_CFG48_OFFSET (0x984)/* gpio_cfg48 */
+#define GLB_GPIO_CFG49_OFFSET (0x988)/* gpio_cfg49 */
+#define GLB_GPIO_CFG50_OFFSET (0x98C)/* gpio_cfg50 */
+#define GLB_GPIO_CFG51_OFFSET (0x990)/* gpio_cfg51 */
+#define GLB_GPIO_CFG52_OFFSET (0x994)/* gpio_cfg52 */
+#define GLB_GPIO_CFG53_OFFSET (0x998)/* gpio_cfg53 */
+#define GLB_GPIO_CFG54_OFFSET (0x99C)/* gpio_cfg54 */
+#define GLB_GPIO_CFG55_OFFSET (0x9A0)/* gpio_cfg55 */
+#define GLB_GPIO_CFG56_OFFSET (0x9A4)/* gpio_cfg56 */
+#define GLB_GPIO_CFG57_OFFSET (0x9A8)/* gpio_cfg57 */
+#define GLB_GPIO_CFG58_OFFSET (0x9AC)/* gpio_cfg58 */
+#define GLB_GPIO_CFG59_OFFSET (0x9B0)/* gpio_cfg59 */
+#define GLB_GPIO_CFG60_OFFSET (0x9B4)/* gpio_cfg60 */
+#define GLB_GPIO_CFG61_OFFSET (0x9B8)/* gpio_cfg61 */
+#define GLB_GPIO_CFG62_OFFSET (0x9BC)/* gpio_cfg62 */
+#define GLB_GPIO_CFG63_OFFSET (0x9C0)/* gpio_cfg63 */
+#define GLB_GPIO_CFG128_OFFSET (0xAC4)/* gpio_cfg128 */
+#define GLB_GPIO_CFG129_OFFSET (0xAC8)/* gpio_cfg129 */
+#define GLB_GPIO_CFG136_OFFSET (0xAE4)/* gpio_cfg136 */
+#define GLB_GPIO_CFG137_OFFSET (0xAE8)/* gpio_cfg137 */
+#define GLB_GPIO_CFG138_OFFSET (0xAEC)/* gpio_cfg138 */
+#define GLB_GPIO_CFG139_OFFSET (0xAF0)/* gpio_cfg139 */
+#define GLB_GPIO_CFG140_OFFSET (0xAF4)/* gpio_cfg140 */
+#define GLB_GPIO_CFG141_OFFSET (0xAF8)/* gpio_cfg141 */
+#define GLB_GPIO_CFG142_OFFSET (0xAFC)/* gpio_cfg142 */
+#define GLB_GPIO_CFG143_OFFSET (0xB00)/* gpio_cfg143 */
+#define GLB_GPIO_CFG144_OFFSET (0xB04)/* gpio_cfg144 */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x8C4 : gpio_cfg0 */
+#define GLB_REG_GPIO_0_IE (1<<0U)
+#define GLB_REG_GPIO_0_SMT (1<<1U)
+#define GLB_REG_GPIO_0_DRV_SHIFT (2U)
+#define GLB_REG_GPIO_0_DRV_MASK (0x3<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_I2C_H__
+#define __HARDWARE_I2C_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define I2C_CONFIG_OFFSET (0x0) /* i2c_config */
+#define I2C_INT_STS_OFFSET (0x4) /* i2c_int_sts */
+#define I2C_SUB_ADDR_OFFSET (0x8) /* i2c_sub_addr */
+#define I2C_BUS_BUSY_OFFSET (0xC) /* i2c_bus_busy */
+#define I2C_PRD_START_OFFSET (0x10) /* i2c_prd_start */
+#define I2C_PRD_STOP_OFFSET (0x14) /* i2c_prd_stop */
+#define I2C_PRD_DATA_OFFSET (0x18) /* i2c_prd_data */
+#define I2C_FIFO_CONFIG_0_OFFSET (0x80) /* i2c_fifo_config_0 */
+#define I2C_FIFO_CONFIG_1_OFFSET (0x84) /* i2c_fifo_config_1 */
+#define I2C_FIFO_WDATA_OFFSET (0x88) /* i2c_fifo_wdata */
+#define I2C_FIFO_RDATA_OFFSET (0x8C) /* i2c_fifo_rdata */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : i2c_config */
+#define I2C_CR_I2C_M_EN (1 << 0U)
+#define I2C_CR_I2C_PKT_DIR (1 << 1U)
+#define I2C_CR_I2C_DEG_EN (1 << 2U)
+#define I2C_CR_I2C_SCL_SYNC_EN (1 << 3U)
+#define I2C_CR_I2C_SUB_ADDR_EN (1 << 4U)
+#define I2C_CR_I2C_SUB_ADDR_BC_SHIFT (5U)
+#define I2C_CR_I2C_SUB_ADDR_BC_MASK (0x3 << I2C_CR_I2C_SUB_ADDR_BC_SHIFT)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) || defined(BL702L)
+#define I2C_CR_I2C_10B_ADDR_EN (1 << 7U)
+#define I2C_CR_I2C_SLV_ADDR_SHIFT (8U)
+#define I2C_CR_I2C_SLV_ADDR_MASK (0x3ff << I2C_CR_I2C_SLV_ADDR_SHIFT)
+#define I2C_CR_I2C_PKT_LEN_SHIFT (20U)
+#define I2C_CR_I2C_PKT_LEN_MASK (0xff << I2C_CR_I2C_PKT_LEN_SHIFT)
+#else
+#define I2C_CR_I2C_SLV_ADDR_SHIFT (8U)
+#define I2C_CR_I2C_SLV_ADDR_MASK (0x7f << I2C_CR_I2C_SLV_ADDR_SHIFT)
+#define I2C_CR_I2C_PKT_LEN_SHIFT (16U)
+#define I2C_CR_I2C_PKT_LEN_MASK (0xff << I2C_CR_I2C_PKT_LEN_SHIFT)
+#endif
+
+#define I2C_CR_I2C_DEG_CNT_SHIFT (28U)
+#define I2C_CR_I2C_DEG_CNT_MASK (0xf << I2C_CR_I2C_DEG_CNT_SHIFT)
+
+/* 0x4 : i2c_int_sts */
+#define I2C_END_INT (1 << 0U)
+#define I2C_TXF_INT (1 << 1U)
+#define I2C_RXF_INT (1 << 2U)
+#define I2C_NAK_INT (1 << 3U)
+#define I2C_ARB_INT (1 << 4U)
+#define I2C_FER_INT (1 << 5U)
+#define I2C_CR_I2C_END_MASK (1 << 8U)
+#define I2C_CR_I2C_TXF_MASK (1 << 9U)
+#define I2C_CR_I2C_RXF_MASK (1 << 10U)
+#define I2C_CR_I2C_NAK_MASK (1 << 11U)
+#define I2C_CR_I2C_ARB_MASK (1 << 12U)
+#define I2C_CR_I2C_FER_MASK (1 << 13U)
+#define I2C_CR_I2C_END_CLR (1 << 16U)
+#define I2C_CR_I2C_NAK_CLR (1 << 19U)
+#define I2C_CR_I2C_ARB_CLR (1 << 20U)
+#define I2C_CR_I2C_END_EN (1 << 24U)
+#define I2C_CR_I2C_TXF_EN (1 << 25U)
+#define I2C_CR_I2C_RXF_EN (1 << 26U)
+#define I2C_CR_I2C_NAK_EN (1 << 27U)
+#define I2C_CR_I2C_ARB_EN (1 << 28U)
+#define I2C_CR_I2C_FER_EN (1 << 29U)
+
+/* 0x8 : i2c_sub_addr */
+#define I2C_CR_I2C_SUB_ADDR_B0_SHIFT (0U)
+#define I2C_CR_I2C_SUB_ADDR_B0_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B0_SHIFT)
+#define I2C_CR_I2C_SUB_ADDR_B1_SHIFT (8U)
+#define I2C_CR_I2C_SUB_ADDR_B1_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B1_SHIFT)
+#define I2C_CR_I2C_SUB_ADDR_B2_SHIFT (16U)
+#define I2C_CR_I2C_SUB_ADDR_B2_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B2_SHIFT)
+#define I2C_CR_I2C_SUB_ADDR_B3_SHIFT (24U)
+#define I2C_CR_I2C_SUB_ADDR_B3_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B3_SHIFT)
+
+/* 0xC : i2c_bus_busy */
+#define I2C_STS_I2C_BUS_BUSY (1 << 0U)
+#define I2C_CR_I2C_BUS_BUSY_CLR (1 << 1U)
+
+/* 0x10 : i2c_prd_start */
+#define I2C_CR_I2C_PRD_S_PH_0_SHIFT (0U)
+#define I2C_CR_I2C_PRD_S_PH_0_MASK (0xff << I2C_CR_I2C_PRD_S_PH_0_SHIFT)
+#define I2C_CR_I2C_PRD_S_PH_1_SHIFT (8U)
+#define I2C_CR_I2C_PRD_S_PH_1_MASK (0xff << I2C_CR_I2C_PRD_S_PH_1_SHIFT)
+#define I2C_CR_I2C_PRD_S_PH_2_SHIFT (16U)
+#define I2C_CR_I2C_PRD_S_PH_2_MASK (0xff << I2C_CR_I2C_PRD_S_PH_2_SHIFT)
+#define I2C_CR_I2C_PRD_S_PH_3_SHIFT (24U)
+#define I2C_CR_I2C_PRD_S_PH_3_MASK (0xff << I2C_CR_I2C_PRD_S_PH_3_SHIFT)
+
+/* 0x14 : i2c_prd_stop */
+#define I2C_CR_I2C_PRD_P_PH_0_SHIFT (0U)
+#define I2C_CR_I2C_PRD_P_PH_0_MASK (0xff << I2C_CR_I2C_PRD_P_PH_0_SHIFT)
+#define I2C_CR_I2C_PRD_P_PH_1_SHIFT (8U)
+#define I2C_CR_I2C_PRD_P_PH_1_MASK (0xff << I2C_CR_I2C_PRD_P_PH_1_SHIFT)
+#define I2C_CR_I2C_PRD_P_PH_2_SHIFT (16U)
+#define I2C_CR_I2C_PRD_P_PH_2_MASK (0xff << I2C_CR_I2C_PRD_P_PH_2_SHIFT)
+#define I2C_CR_I2C_PRD_P_PH_3_SHIFT (24U)
+#define I2C_CR_I2C_PRD_P_PH_3_MASK (0xff << I2C_CR_I2C_PRD_P_PH_3_SHIFT)
+
+/* 0x18 : i2c_prd_data */
+#define I2C_CR_I2C_PRD_D_PH_0_SHIFT (0U)
+#define I2C_CR_I2C_PRD_D_PH_0_MASK (0xff << I2C_CR_I2C_PRD_D_PH_0_SHIFT)
+#define I2C_CR_I2C_PRD_D_PH_1_SHIFT (8U)
+#define I2C_CR_I2C_PRD_D_PH_1_MASK (0xff << I2C_CR_I2C_PRD_D_PH_1_SHIFT)
+#define I2C_CR_I2C_PRD_D_PH_2_SHIFT (16U)
+#define I2C_CR_I2C_PRD_D_PH_2_MASK (0xff << I2C_CR_I2C_PRD_D_PH_2_SHIFT)
+#define I2C_CR_I2C_PRD_D_PH_3_SHIFT (24U)
+#define I2C_CR_I2C_PRD_D_PH_3_MASK (0xff << I2C_CR_I2C_PRD_D_PH_3_SHIFT)
+
+/* 0x80 : i2c_fifo_config_0 */
+#define I2C_DMA_TX_EN (1 << 0U)
+#define I2C_DMA_RX_EN (1 << 1U)
+#define I2C_TX_FIFO_CLR (1 << 2U)
+#define I2C_RX_FIFO_CLR (1 << 3U)
+#define I2C_TX_FIFO_OVERFLOW (1 << 4U)
+#define I2C_TX_FIFO_UNDERFLOW (1 << 5U)
+#define I2C_RX_FIFO_OVERFLOW (1 << 6U)
+#define I2C_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x84 : i2c_fifo_config_1 */
+#define I2C_TX_FIFO_CNT_SHIFT (0U)
+#define I2C_TX_FIFO_CNT_MASK (0x3 << I2C_TX_FIFO_CNT_SHIFT)
+#define I2C_RX_FIFO_CNT_SHIFT (8U)
+#define I2C_RX_FIFO_CNT_MASK (0x3 << I2C_RX_FIFO_CNT_SHIFT)
+#define I2C_TX_FIFO_TH (1 << 16U)
+#define I2C_RX_FIFO_TH (1 << 24U)
+
+/* 0x88 : i2c_fifo_wdata */
+#define I2C_FIFO_WDATA_SHIFT (0U)
+#define I2C_FIFO_WDATA_MASK (0xffffffff << I2C_FIFO_WDATA_SHIFT)
+
+/* 0x8C : i2c_fifo_rdata */
+#define I2C_FIFO_RDATA_SHIFT (0U)
+#define I2C_FIFO_RDATA_MASK (0xffffffff << I2C_FIFO_RDATA_SHIFT)
+
+#endif /* __HARDWARE_I2C_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/i2s_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/i2s_reg.h
new file mode 100644
index 00000000..e5bc85c1
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/i2s_reg.h
@@ -0,0 +1,135 @@
+/**
+ ******************************************************************************
+ * @file i2s_reg.h
+ * @version V1.0
+ * @date 2023-01-03
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __I2S_REG_H__
+#define __I2S_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define I2S_CONFIG_OFFSET (0x0) /* i2s_config */
+#define I2S_INT_STS_OFFSET (0x4) /* i2s_int_sts */
+#define I2S_BCLK_CONFIG_OFFSET (0x10) /* i2s_bclk_config */
+#define I2S_FIFO_CONFIG_0_OFFSET (0x80) /* i2s_fifo_config_0 */
+#define I2S_FIFO_CONFIG_1_OFFSET (0x84) /* i2s_fifo_config_1 */
+#define I2S_FIFO_WDATA_OFFSET (0x88) /* i2s_fifo_wdata */
+#define I2S_FIFO_RDATA_OFFSET (0x8C) /* i2s_fifo_rdata */
+#define I2S_IO_CONFIG_OFFSET (0xFC) /* i2s_io_config */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : i2s_config */
+#define I2S_CR_I2S_M_EN (1 << 0U)
+#define I2S_CR_I2S_S_EN (1 << 1U)
+#define I2S_CR_I2S_TXD_EN (1 << 2U)
+#define I2S_CR_I2S_RXD_EN (1 << 3U)
+#define I2S_CR_MONO_MODE (1 << 4U)
+#define I2S_CR_MUTE_MODE (1 << 5U)
+#define I2S_CR_FS_1T_MODE (1 << 6U)
+#define I2S_CR_FS_CH_CNT_SHIFT (7U)
+#define I2S_CR_FS_CH_CNT_MASK (0x3 << I2S_CR_FS_CH_CNT_SHIFT)
+#define I2S_CR_FRAME_SIZE_SHIFT (12U)
+#define I2S_CR_FRAME_SIZE_MASK (0x3 << I2S_CR_FRAME_SIZE_SHIFT)
+#define I2S_CR_DATA_SIZE_SHIFT (14U)
+#define I2S_CR_DATA_SIZE_MASK (0x3 << I2S_CR_DATA_SIZE_SHIFT)
+#define I2S_CR_I2S_MODE_SHIFT (16U)
+#define I2S_CR_I2S_MODE_MASK (0x3 << I2S_CR_I2S_MODE_SHIFT)
+#define I2S_CR_ENDIAN (1 << 18U)
+#define I2S_CR_MONO_RX_CH (1 << 19U)
+#define I2S_CR_OFS_CNT_SHIFT (20U)
+#define I2S_CR_OFS_CNT_MASK (0x1f << I2S_CR_OFS_CNT_SHIFT)
+#define I2S_CR_OFS_EN (1 << 25U)
+
+/* 0x4 : i2s_int_sts */
+#define I2S_TXF_INT (1 << 0U)
+#define I2S_RXF_INT (1 << 1U)
+#define I2S_FER_INT (1 << 2U)
+#define I2S_CR_I2S_TXF_MASK (1 << 8U)
+#define I2S_CR_I2S_RXF_MASK (1 << 9U)
+#define I2S_CR_I2S_FER_MASK (1 << 10U)
+#define I2S_CR_I2S_TXF_EN (1 << 24U)
+#define I2S_CR_I2S_RXF_EN (1 << 25U)
+#define I2S_CR_I2S_FER_EN (1 << 26U)
+
+/* 0x10 : i2s_bclk_config */
+#define I2S_CR_BCLK_DIV_L_SHIFT (0U)
+#define I2S_CR_BCLK_DIV_L_MASK (0xfff << I2S_CR_BCLK_DIV_L_SHIFT)
+#define I2S_CR_BCLK_DIV_H_SHIFT (16U)
+#define I2S_CR_BCLK_DIV_H_MASK (0xfff << I2S_CR_BCLK_DIV_H_SHIFT)
+
+/* 0x80 : i2s_fifo_config_0 */
+#define I2S_DMA_TX_EN (1 << 0U)
+#define I2S_DMA_RX_EN (1 << 1U)
+#define I2S_TX_FIFO_CLR (1 << 2U)
+#define I2S_RX_FIFO_CLR (1 << 3U)
+#define I2S_TX_FIFO_OVERFLOW (1 << 4U)
+#define I2S_TX_FIFO_UNDERFLOW (1 << 5U)
+#define I2S_RX_FIFO_OVERFLOW (1 << 6U)
+#define I2S_RX_FIFO_UNDERFLOW (1 << 7U)
+#define I2S_CR_FIFO_LR_MERGE (1 << 8U)
+#define I2S_CR_FIFO_LR_EXCHG (1 << 9U)
+#define I2S_CR_FIFO_24B_LJ (1 << 10U)
+
+/* 0x84 : i2s_fifo_config_1 */
+#define I2S_TX_FIFO_CNT_SHIFT (0U)
+#define I2S_TX_FIFO_CNT_MASK (0x1f << I2S_TX_FIFO_CNT_SHIFT)
+#define I2S_RX_FIFO_CNT_SHIFT (8U)
+#define I2S_RX_FIFO_CNT_MASK (0x1f << I2S_RX_FIFO_CNT_SHIFT)
+#define I2S_TX_FIFO_TH_SHIFT (16U)
+#define I2S_TX_FIFO_TH_MASK (0xf << I2S_TX_FIFO_TH_SHIFT)
+#define I2S_RX_FIFO_TH_SHIFT (24U)
+#define I2S_RX_FIFO_TH_MASK (0xf << I2S_RX_FIFO_TH_SHIFT)
+
+/* 0x88 : i2s_fifo_wdata */
+#define I2S_FIFO_WDATA_SHIFT (0U)
+#define I2S_FIFO_WDATA_MASK (0xffffffff << I2S_FIFO_WDATA_SHIFT)
+
+/* 0x8C : i2s_fifo_rdata */
+#define I2S_FIFO_RDATA_SHIFT (0U)
+#define I2S_FIFO_RDATA_MASK (0xffffffff << I2S_FIFO_RDATA_SHIFT)
+
+/* 0xFC : i2s_io_config */
+#define I2S_CR_I2S_TXD_INV (1 << 0U)
+#define I2S_CR_I2S_RXD_INV (1 << 1U)
+#define I2S_CR_I2S_FS_INV (1 << 2U)
+#define I2S_CR_I2S_BCLK_INV (1 << 3U)
+#define I2S_CR_DEG_CNT_SHIFT (4U)
+#define I2S_CR_DEG_CNT_MASK (0x7 << I2S_CR_DEG_CNT_SHIFT)
+#define I2S_CR_DEG_EN (1 << 7U)
+
+#endif /* __I2S_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/ir_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/ir_reg.h
new file mode 100644
index 00000000..1ae98945
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/ir_reg.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file ir_reg.h
+ * @version V1.0
+ * @date 2022-09-28
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_IR_H__
+#define __HARDWARE_IR_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#if !defined(BL616)
+#define IRTX_CONFIG_OFFSET (0x0) /* irtx_config */
+#define IRTX_INT_STS_OFFSET (0x4) /* irtx_int_sts */
+#if defined(BL602) || defined(BL702)
+#define IRTX_DATA_WORD0_OFFSET (0x8) /* irtx_data_word0 */
+#define IRTX_DATA_WORD1_OFFSET (0xC) /* irtx_data_word1 */
+#endif
+#define IRTX_PULSE_WIDTH_OFFSET (0x10) /* irtx_pulse_width */
+#if defined(BL602) || defined(BL702)
+#define IRTX_PW_OFFSET (0x14) /* irtx_pw */
+#define IRTX_SWM_PW_0_OFFSET (0x40) /* irtx_swm_pw_0 */
+#define IRTX_SWM_PW_1_OFFSET (0x44) /* irtx_swm_pw_1 */
+#define IRTX_SWM_PW_2_OFFSET (0x48) /* irtx_swm_pw_2 */
+#define IRTX_SWM_PW_3_OFFSET (0x4C) /* irtx_swm_pw_3 */
+#define IRTX_SWM_PW_4_OFFSET (0x50) /* irtx_swm_pw_4 */
+#define IRTX_SWM_PW_5_OFFSET (0x54) /* irtx_swm_pw_5 */
+#define IRTX_SWM_PW_6_OFFSET (0x58) /* irtx_swm_pw_6 */
+#define IRTX_SWM_PW_7_OFFSET (0x5C) /* irtx_swm_pw_7 */
+#else
+#define IRTX_PW_0_OFFSET (0x14) /* irtx_pw_0 */
+#define IRTX_PW_1_OFFSET (0x18) /* irtx_pw_1 */
+#endif
+#endif
+#if !defined(BL702L)
+#if defined(BL602) || defined(BL702)
+#define IRRX_CONFIG_OFFSET (0x80) /* irrx_config */
+#define IRRX_INT_STS_OFFSET (0x84) /* irrx_int_sts */
+#define IRRX_PW_CONFIG_OFFSET (0x88) /* irrx_pw_config */
+#define IRRX_DATA_COUNT_OFFSET (0x90) /* irrx_data_count */
+#define IRRX_DATA_WORD0_OFFSET (0x94) /* irrx_data_word0 */
+#define IRRX_DATA_WORD1_OFFSET (0x98) /* irrx_data_word1 */
+#else
+#define IRRX_CONFIG_OFFSET (0x40) /* irrx_config */
+#define IRRX_INT_STS_OFFSET (0x44) /* irrx_int_sts */
+#define IRRX_PW_CONFIG_OFFSET (0x48) /* irrx_pw_config */
+#define IRRX_DATA_COUNT_OFFSET (0x50) /* irrx_data_count */
+#define IRRX_DATA_WORD0_OFFSET (0x54) /* irrx_data_word0 */
+#define IRRX_DATA_WORD1_OFFSET (0x58) /* irrx_data_word1 */
+#endif
+#endif
+#if defined(BL602) || defined(BL702)
+#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0) /* irrx_swm_fifo_config_0 */
+#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4) /* irrx_swm_fifo_rdata */
+#else
+#define IR_FIFO_CONFIG_0_OFFSET (0x80) /* ir_fifo_config_0 */
+#define IR_FIFO_CONFIG_1_OFFSET (0x84) /* ir_fifo_config_1 */
+#define IR_FIFO_WDATA_OFFSET (0x88) /* ir_fifo_wdata */
+#if !defined(BL702L)
+#define IR_FIFO_RDATA_OFFSET (0x8C) /* ir_fifo_rdata */
+#endif
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+#if !defined(BL616)
+/* 0x0 : irtx_config */
+#define IR_CR_IRTX_EN (1 << 0U)
+#define IR_CR_IRTX_OUT_INV (1 << 1U)
+#define IR_CR_IRTX_MOD_EN (1 << 2U)
+#define IR_CR_IRTX_SWM_EN (1 << 3U)
+#define IR_CR_IRTX_DATA_EN (1 << 4U)
+#define IR_CR_IRTX_LOGIC0_HL_INV (1 << 5U)
+#define IR_CR_IRTX_LOGIC1_HL_INV (1 << 6U)
+#define IR_CR_IRTX_HEAD_EN (1 << 8U)
+#define IR_CR_IRTX_HEAD_HL_INV (1 << 9U)
+#define IR_CR_IRTX_TAIL_EN (1 << 10U)
+#define IR_CR_IRTX_TAIL_HL_INV (1 << 11U)
+#if defined(BL602) || defined(BL702)
+#define IR_CR_IRTX_DATA_NUM_SHIFT (12U)
+#define IR_CR_IRTX_DATA_NUM_MASK (0x3f << IR_CR_IRTX_DATA_NUM_SHIFT)
+#else
+#define IR_CR_IRTX_FRM_EN (1 << 12U)
+#define IR_CR_IRTX_FRM_CONT_EN (1 << 13U)
+#define IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT (14U)
+#define IR_CR_IRTX_FRM_FRAME_SIZE_MASK (0x3 << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT)
+#define IR_CR_IRTX_DATA_NUM_SHIFT (16U)
+#define IR_CR_IRTX_DATA_NUM_MASK (0x7f << IR_CR_IRTX_DATA_NUM_SHIFT)
+#endif
+
+/* 0x4 : irtx_int_sts */
+#define IRTX_END_INT (1 << 0U)
+#if !defined(BL602) && !defined(BL702)
+#define IRTX_FRDY_INT (1 << 1U)
+#define IRTX_FER_INT (1 << 2U)
+#endif
+#define IR_CR_IRTX_END_MASK (1 << 8U)
+#if !defined(BL602) && !defined(BL702)
+#define IR_CR_IRTX_FRDY_MASK (1 << 9U)
+#define IR_CR_IRTX_FER_MASK (1 << 10U)
+#endif
+#define IR_CR_IRTX_END_CLR (1 << 16U)
+#define IR_CR_IRTX_END_EN (1 << 24U)
+#if !defined(BL602) && !defined(BL702)
+#define IR_CR_IRTX_FRDY_EN (1 << 25U)
+#define IR_CR_IRTX_FER_EN (1 << 26U)
+#else
+/* 0x8 : irtx_data_word0 */
+#define IR_CR_IRTX_DATA_WORD0_SHIFT (0U)
+#define IR_CR_IRTX_DATA_WORD0_MASK (0xffffffff<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __ISO11898_REG_H__
+#define __ISO11898_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define ISO11898_MODE_OFFSET (0x0)/* mode */
+#define ISO11898_COMMAND_OFFSET (0x4)/* command */
+#define ISO11898_STATUS_OFFSET (0x8)/* status */
+#define ISO11898_INTERRUPT_OFFSET (0xc)/* interrupt */
+#define ISO11898_INTERRUPT_ENABLE_OFFSET (0x10)/* interrupt_enable */
+#define ISO11898_BUS_TIMING_0_OFFSET (0x18)/* bus_timing_0 */
+#define ISO11898_BUS_TIMING_1_OFFSET (0x1c)/* bus_timing_1 */
+#define ISO11898_ARB_LOST_CAPTURE_OFFSET (0x2c)/* arb_lost_capture */
+#define ISO11898_ERROR_CODE_CAPTURE_OFFSET (0x30)/* error_code_capture */
+#define ISO11898_ERROR_WARNING_LIMIT_OFFSET (0x34)/* error_warning_limit */
+#define ISO11898_RX_ERR_COUNT_OFFSET (0x38)/* rx_err_count */
+#define ISO11898_TX_ERR_COUNT_OFFSET (0x3c)/* tx_err_count */
+#define ISO11898_FRAME_INFORMATION_OFFSET (0x40)/* frame_information */
+#define ISO11898_ACCEPTANCE_CODE_0_OFFSET (0x40)/* acceptance_code_0 */
+#define ISO11898_SFF_ID1_OFFSET (0x44)/* sff_id1 */
+#define ISO11898_EFF_ID1_OFFSET (0x44)/* eff_id1 */
+#define ISO11898_ACCEPTANCE_CODE_1_OFFSET (0x44)/* acceptance_code_1 */
+#define ISO11898_SFF_ID2_OFFSET (0x48)/* sff_id2 */
+#define ISO11898_EFF_ID2_OFFSET (0x48)/* eff_id2 */
+#define ISO11898_ACCEPTANCE_CODE_2_OFFSET (0x48)/* acceptance_code_2 */
+#define ISO11898_SFF_DATA1_OFFSET (0x4c)/* sff_data1 */
+#define ISO11898_EFF_ID3_OFFSET (0x4c)/* eff_id3 */
+#define ISO11898_ACCEPTANCE_CODE_3_OFFSET (0x4c)/* acceptance_code_3 */
+#define ISO11898_SFF_DATA2_OFFSET (0x50)/* sff_data2 */
+#define ISO11898_EFF_ID4_OFFSET (0x50)/* eff_id4 */
+#define ISO11898_ACCEPTANCE_MASK_0_OFFSET (0x50)/* acceptance_mask_0 */
+#define ISO11898_SFF_DATA3_OFFSET (0x54)/* sff_data3 */
+#define ISO11898_EFF_DATA1_OFFSET (0x54)/* eff_data1 */
+#define ISO11898_ACCEPTANCE_MASK_1_OFFSET (0x54)/* acceptance_mask_1 */
+#define ISO11898_SFF_DATA4_OFFSET (0x58)/* sff_data4 */
+#define ISO11898_EFF_DATA2_OFFSET (0x58)/* eff_data2 */
+#define ISO11898_ACCEPTANCE_MASK_2_OFFSET (0x58)/* acceptance_mask_2 */
+#define ISO11898_SFF_DATA5_OFFSET (0x5c)/* sff_data5 */
+#define ISO11898_EFF_DATA3_OFFSET (0x5c)/* eff_data3 */
+#define ISO11898_ACCEPTANCE_MASK_3_OFFSET (0x5c)/* acceptance_mask_3 */
+#define ISO11898_SFF_DATA6_OFFSET (0x60)/* sff_data6 */
+#define ISO11898_EFF_DATA4_OFFSET (0x60)/* eff_data4 */
+#define ISO11898_SFF_DATA7_OFFSET (0x64)/* sff_data7 */
+#define ISO11898_EFF_DATA5_OFFSET (0x64)/* eff_data5 */
+#define ISO11898_SFF_DATA8_OFFSET (0x68)/* sff_data8 */
+#define ISO11898_EFF_DATA6_OFFSET (0x68)/* eff_data6 */
+#define ISO11898_EFF_DATA7_OFFSET (0x6c)/* eff_data7 */
+#define ISO11898_EFF_DATA8_OFFSET (0x70)/* eff_data8 */
+#define ISO11898_RX_MESSAGE_COUNT_OFFSET (0x74)/* rx_message_count */
+#define ISO11898_CLOCK_DIVIDER_OFFSET (0x7c)/* clock_divider */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : mode */
+#define ISO11898_RESET_REQUEST (1<<0U)
+#define ISO11898_LISTEN_ONLY (1<<1U)
+#define ISO11898_SELF_TEST (1<<2U)
+#define ISO11898_FILTER_TYPE (1<<3U)
+
+/* 0x4 : command */
+#define ISO11898_TRANSMIT_REQUEST (1<<0U)
+#define ISO11898_ABORT_TRANSMISSION (1<<1U)
+#define ISO11898_RELEASE_RECEIVE_BUFFER (1<<2U)
+#define ISO11898_CLEAR_DATA_OVERRUN (1<<3U)
+#define ISO11898_SELF_REQUEST (1<<4U)
+
+/* 0x8 : status */
+#define ISO11898_RECEIVE_BUFFER_STS (1<<0U)
+#define ISO11898_DATA_OVERRUN_STS (1<<1U)
+#define ISO11898_TRANSMIT_BUFFER_STS (1<<2U)
+#define ISO11898_TRANSMIT_COMPLETE_STS (1<<3U)
+#define ISO11898_RECEIVE_STS (1<<4U)
+#define ISO11898_TRANSMIT_STS (1<<5U)
+#define ISO11898_ERROR_STS (1<<6U)
+#define ISO11898_BUS_STS (1<<7U)
+
+/* 0xc : interrupt */
+#define ISO11898_RECEIVE_INT (1<<0U)
+#define ISO11898_TRANSMIT_INT (1<<1U)
+#define ISO11898_ERROR_INT (1<<2U)
+#define ISO11898_DATA_OVERRUN_INT (1<<3U)
+#define ISO11898_ERROR_PASSIVE_INT (1<<5U)
+#define ISO11898_ARB_LOST_INT (1<<6U)
+#define ISO11898_BUS_ERROR_INT (1<<7U)
+
+/* 0x10 : interrupt_enable */
+#define ISO11898_RECEIVE_INT_EN (1<<0U)
+#define ISO11898_TRANSMIT_INT_EN (1<<1U)
+#define ISO11898_ERROR_INT_EN (1<<2U)
+#define ISO11898_DATA_OVERRUN_INT_EN (1<<3U)
+#define ISO11898_ERROR_PASSIVE_INT_EN (1<<5U)
+#define ISO11898_ARB_LOST_INT_EN (1<<6U)
+#define ISO11898_BUS_ERROR_INT_EN (1<<7U)
+
+/* 0x18 : bus_timing_0 */
+#define ISO11898_BAUD_RATE_PRESCALER_SHIFT (0U)
+#define ISO11898_BAUD_RATE_PRESCALER_MASK (0x3f<© COPYRIGHT(c) 2022 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without
+ *modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_KYS_H__
+#define __HARDWARE_KYS_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#define KYS_KS_CTRL_OFFSET (0x0)
+#define KYS_KS_INT_EN_OFFSET (0x10)
+#define KYS_KS_INT_STS_OFFSET (0x14)
+#define KYS_KEYCODE_CLR_OFFSET (0x18)
+#if defined(bl702)
+#define KYS_KEYFIFO_VALUE_OFFSET (0x1C)
+#else
+#define KYS_KEYFIFO_IDX_OFFSET (0x30)
+#define KYS_KEYFIFO_VALUE_OFFSET (0x34)
+#endif
+
+/* 0x0 : ks_ctrl */
+#define KYS_KS_EN_SHIFT (0U)
+#define KYS_KS_EN_MASK (0x1 << KYS_KS_EN_SHIFT)
+#define KYS_GHOST_EN_SHIFT (2U)
+#define KYS_GHOST_EN_MASK (0x1 << KYS_GHOST_EN_SHIFT)
+#define KYS_DEG_EN_SHIFT (3U)
+#define KYS_DEG_EN_MASK (0x1 << KYS_DEG_EN_SHIFT)
+#define KYS_DEG_CNT_SHIFT (4U)
+#define KYS_DEG_CNT_MASK (0xf << KYS_DEG_CNT_SHIFT)
+#define KYS_RC_EXT_SHIFT (8U)
+#define KYS_RC_EXT_MASK (0x3 << KYS_RC_EXT_SHIFT)
+#define KYS_ROW_NUM_SHIFT (16U)
+#define KYS_ROW_NUM_MASK (0x7 << KYS_ROW_NUM_SHIFT)
+#if defined(bl702)
+#define KYS_COL_NUM_SHIFT (20U)
+#define KYS_COL_NUM_MASK (0x7 << KYS_COL_NUM_SHIFT)
+#else
+#define KYS_FIFO_MODE_SHIFT (1U)
+#define KYS_FIFO_MODE_MASK (0x1 << KYS_FIFO_MODE_SHIFT)
+#define KYS_COL_NUM_SHIFT (20U)
+#define KYS_COL_NUM_MASK (0x1f << KYS_COL_NUM_SHIFT)
+#endif
+
+/* 0x10 : ks_int_en */
+#if defined(bl702)
+#define KYS_KS_INT_EN_SHIFT (0U)
+#define KYS_KS_INT_EN_MASK (0x1 << KYS_KS_INT_EN_SHIFT)
+#else
+#define KYS_KS_DONE_INT_EN_SHIFT (7U)
+#define KYS_KS_DONE_INT_EN_MASK (0x1 << KYS_KS_DONE_INT_EN_SHIFT)
+#define KYS_KEYFIFO_FULL_INT_EN_SHIFT (8U)
+#define KYS_KEYFIFO_FULL_INT_EN_MASK (0x1 << KYS_KEYFIFO_FULL_INT_EN_SHIFT)
+#define KYS_KEYFIFO_HALF_INT_EN_SHIFT (9U)
+#define KYS_KEYFIFO_HALF_INT_EN_MASK (0x1 << KYS_KEYFIFO_HALF_INT_EN_SHIFT)
+#define KYS_KEYFIFO_QUARTER_INT_EN_SHIFT (10U)
+#define KYS_KEYFIFO_QUARTER_INT_EN_MASK (0x1 << KYS_KEYFIFO_QUARTER_INT_EN_SHIFT)
+#define KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT (11U)
+#define KYS_KEYFIFO_NONEMPTY_INT_EN_MASK (0x1 << KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT)
+#define KYS_GHOST_INT_EN_SHIFT (12U)
+#define KYS_GHOST_INT_EN_MASK (0x1 << KYS_GHOST_INT_EN_SHIFT)
+#endif
+
+/* 0x14 : ks_int_sts */
+#if defined(bl702)
+#define KYS_KEYCODE_VALID_SHIFT (0U)
+#define KYS_KEYCODE_VALID_MASK (0xf << KYS_KEYCODE_VALID_SHIFT)
+#else
+#define KYS_KEYCODE_DONE_SHIFT (7U)
+#define KYS_KEYCODE_DONE_MASK (0x1 << KYS_KEYCODE_DONE_SHIFT)
+#define KYS_KEYFIFO_FULL_SHIFT (8U)
+#define KYS_KEYFIFO_FULL_MASK (0x1 << KYS_KEYFIFO_FULL_SHIFT)
+#define KYS_KEYFIFO_HALF_SHIFT (9U)
+#define KYS_KEYFIFO_HALF_MSK (0x1 << KYS_KEYFIFO_HALF_SHIFT)
+#define KYS_KEYFIFO_QUARTER_SHIFT (10U)
+#define KYS_KEYFIFO_QUARTER_MSK (0x1 << KYS_KEYFIFO_QUARTER_SHIFT)
+#define KYS_KEYFIFO_NONEMPTY_SHIFT (11U)
+#define KYS_KEYFIFO_NONEMPTY_MSK (0x1 << KYS_KEYFIFO_NONEMPTY_SHIFT)
+#define KYS_GHOST_DET_SHIFT (12U)
+#define KYS_GHOST_DET_MASK (0x1 << KYS_GHOST_DET_SHIFT)
+#endif
+
+/* 0x18 : keycode_clr */
+#if defined(bl702)
+#define KYS_KEYCODE_CLR_SHIFT (0U)
+#define KYS_KEYCODE_CLR_MASK (0xf << KYS_KEYCODE_CLR_SHIFT)
+#else
+#define KYS_KS_DONE_CLR_SHIFT (7U)
+#define KYS_KS_DONE_CLR_MASK (0x1 << KYS_KS_DONE_CLR_SHIFT)
+#define KYS_KEYFIFO_FULL_CLR_SHIFT (8U)
+#define KYS_KEYFIFO_FULL_CLR_MASK (0x1 << KYS_KEYFIFO_FULL_CLR_SHIFT)
+#define KYS_GHOST_CLR_SHIFT (12U)
+#define KYS_GHOST_CLR_MASK (0x1 << KYS_GHOST_CLR_SHIFT)
+#endif
+
+#if defined(bl702)
+/* 0x1c : keycode value */
+#define KYS_KEYCODE0_SHIFT (0U)
+#define KYS_KEYCODE0_MASK (0xff << KYS_KEYCODE0_SHIFT)
+#define KYS_KEYCODE1_SHIFT (8U)
+#define KYS_KEYCODE1_MASK (0xff << KYS_KEYCODE1_SHIFT)
+#define KYS_KEYCODE2_SHIFT (16U)
+#define KYS_KEYCODE2_MASK (0xff << KYS_KEYCODE2_SHIFT)
+#define KYS_KEYCODE3_SHIFT (24U)
+#define KYS_KEYCODE3_MASK (0xff << KYS_KEYCODE3_SHIFT)
+#endif
+
+#if defined(bl702l)
+/* 0x30 : keyfifo_idx */
+#define KYS_KEYFIFO_HEAD_SHIFT (0U)
+#define KYS_KEYFIFO_HEAD_MASK (0x7 << KYS_KEYFIFO_HEAD_SHIFT)
+#define KYS_KEYFIFO_TAIL_SHIFT (8U)
+#define KYS_KEYFIFO_TAIL_MASK (0x7 << KYS_KEYFIFO_TAIL_SHIFT)
+
+/* 0x34 : keyfifo_value */
+#define KYS_KEYFIFO_VALUE_SHIFT (0U)
+#define KYS_KEYFIFO_VALUE_MASK (0xff << KYS_KEYFIFO_VALUE_SHIFT)
+#endif
+
+#endif /* __HARDWARE_KYS_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/mjpeg_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/mjpeg_reg.h
new file mode 100644
index 00000000..1fbd4f69
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/mjpeg_reg.h
@@ -0,0 +1,319 @@
+/**
+ ******************************************************************************
+ * @file mjpeg_reg.h
+ * @version V1.0
+ * @date 2022-11-01
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_MJPEG_REG_H__
+#define __HARDWARE_MJPEG_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define MJPEG_CONTROL_1_OFFSET (0x0)/* mjpeg_control_1 */
+#define MJPEG_CONTROL_2_OFFSET (0x4)/* mjpeg_control_2 */
+#define MJPEG_YY_FRAME_ADDR_OFFSET (0x08)/* mjpeg_yy_frame_addr */
+#define MJPEG_UV_FRAME_ADDR_OFFSET (0x0C)/* mjpeg_uv_frame_addr */
+#define MJPEG_YUV_MEM_OFFSET (0x10)/* mjpeg_yuv_mem */
+#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14)/* jpeg_frame_addr */
+#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18)/* jpeg_store_memory */
+#define MJPEG_CONTROL_3_OFFSET (0x1C)/* mjpeg_control_3 */
+#define MJPEG_FRAME_FIFO_POP_OFFSET (0x20)/* mjpeg_frame_fifo_pop */
+#define MJPEG_FRAME_SIZE_OFFSET (0x24)/* mjpeg_frame_size */
+#define MJPEG_HEADER_BYTE_OFFSET (0x28)/* mjpeg_header_byte */
+#define MJPEG_SWAP_MODE_OFFSET (0x30)/* mjpeg_swap_mode */
+#define MJPEG_SWAP_BIT_CNT_OFFSET (0x34)/* mjpeg_swap_bit_cnt */
+#define MJPEG_YUV_MEM_SW_OFFSET (0x38)/* mjpeg_yuv_mem_sw */
+#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40)/* mjpeg_Y_frame_read_status_1 */
+#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44)/* mjpeg_Y_frame_read_status_2 */
+#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48)/* mjpeg_Y_frame_write_status */
+#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C)/* mjpeg_UV_frame_read_status_1 */
+#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50)/* mjpeg_UV_frame_read_status_2 */
+#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54)/* mjpeg_UV_frame_write_status */
+#define MJPEG_FRAME_W_HBLK_STATUS_OFFSET (0x58)/* mjpeg_frame_w_hblk_status */
+#define MJPEG_START_ADDR0_OFFSET (0x80)/* mjpeg_start_addr0 */
+#define MJPEG_BIT_CNT0_OFFSET (0x84)/* mjpeg_bit_cnt0 */
+#define MJPEG_START_ADDR1_OFFSET (0x88)/* mjpeg_start_addr1 */
+#define MJPEG_BIT_CNT1_OFFSET (0x8C)/* mjpeg_bit_cnt1 */
+#define MJPEG_START_ADDR2_OFFSET (0x90)/* mjpeg_start_addr2 */
+#define MJPEG_BIT_CNT2_OFFSET (0x94)/* mjpeg_bit_cnt2 */
+#define MJPEG_START_ADDR3_OFFSET (0x98)/* mjpeg_start_addr3 */
+#define MJPEG_BIT_CNT3_OFFSET (0x9C)/* mjpeg_bit_cnt3 */
+#define MJPEG_Q_ENC_OFFSET (0x100)/* mjpeg_q_enc */
+#define MJPEG_FRAME_ID_10_OFFSET (0x110)/* mjpeg_frame_id_10 */
+#define MJPEG_FRAME_ID_32_OFFSET (0x114)/* mjpeg_frame_id_32 */
+#define MJPEG_DEBUG_OFFSET (0x1F0)/* mjpeg_debug */
+#define MJPEG_DUMMY_REG_OFFSET (0x1FC)/* mjpeg_dummy_reg */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : mjpeg_control_1 */
+#define MJPEG_REG_MJPEG_ENABLE (1<<0U)
+#define MJPEG_REG_MJPEG_BIT_ORDER (1<<1U)
+#define MJPEG_REG_ORDER_U_EVEN (1<<2U)
+#define MJPEG_REG_HW_MODE_SWEN (1<<3U)
+#define MJPEG_REG_LAST_HF_WBLK_DMY (1<<4U)
+#define MJPEG_REG_LAST_HF_HBLK_DMY (1<<5U)
+#define MJPEG_REG_REFLECT_DMY (1<<6U)
+#define MJPEG_REG_READ_FWRAP (1<<7U)
+#define MJPEG_REG_W_XLEN_SHIFT (8U)
+#define MJPEG_REG_W_XLEN_MASK (0x7<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __PWM_REG_H__
+#define __PWM_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#if defined(BL702L)
+#define PWM_INT_CONFIG_OFFSET (-0x20) /* pwm_int_config */
+#else
+#define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */
+#endif
+#define PWM0_CLKDIV_OFFSET (0x20) /* pwm0_clkdiv */
+#define PWM0_THRE1_OFFSET (0x24) /* pwm0_thre1 */
+#define PWM0_THRE2_OFFSET (0x28) /* pwm0_thre2 */
+#define PWM0_PERIOD_OFFSET (0x2C) /* pwm0_period */
+#define PWM0_CONFIG_OFFSET (0x30) /* pwm0_config */
+#define PWM0_INTERRUPT_OFFSET (0x34) /* pwm0_interrupt */
+#define PWM1_CLKDIV_OFFSET (0x40) /* pwm1_clkdiv */
+#define PWM1_THRE1_OFFSET (0x44) /* pwm1_thre1 */
+#define PWM1_THRE2_OFFSET (0x48) /* pwm1_thre2 */
+#define PWM1_PERIOD_OFFSET (0x4C) /* pwm1_period */
+#define PWM1_CONFIG_OFFSET (0x50) /* pwm1_config */
+#define PWM1_INTERRUPT_OFFSET (0x54) /* pwm1_interrupt */
+#define PWM2_CLKDIV_OFFSET (0x60) /* pwm2_clkdiv */
+#define PWM2_THRE1_OFFSET (0x64) /* pwm2_thre1 */
+#define PWM2_THRE2_OFFSET (0x68) /* pwm2_thre2 */
+#define PWM2_PERIOD_OFFSET (0x6C) /* pwm2_period */
+#define PWM2_CONFIG_OFFSET (0x70) /* pwm2_config */
+#define PWM2_INTERRUPT_OFFSET (0x74) /* pwm2_interrupt */
+#define PWM3_CLKDIV_OFFSET (0x80) /* pwm3_clkdiv */
+#define PWM3_THRE1_OFFSET (0x84) /* pwm3_thre1 */
+#define PWM3_THRE2_OFFSET (0x88) /* pwm3_thre2 */
+#define PWM3_PERIOD_OFFSET (0x8C) /* pwm3_period */
+#define PWM3_CONFIG_OFFSET (0x90) /* pwm3_config */
+#define PWM3_INTERRUPT_OFFSET (0x94) /* pwm3_interrupt */
+#define PWM4_CLKDIV_OFFSET (0xA0) /* pwm4_clkdiv */
+#define PWM4_THRE1_OFFSET (0xA4) /* pwm4_thre1 */
+#define PWM4_THRE2_OFFSET (0xA8) /* pwm4_thre2 */
+#define PWM4_PERIOD_OFFSET (0xAC) /* pwm4_period */
+#define PWM4_CONFIG_OFFSET (0xB0) /* pwm4_config */
+#define PWM4_INTERRUPT_OFFSET (0xB4) /* pwm4_interrupt */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : pwm_int_config */
+#define PWM_INTERRUPT_STS_SHIFT (0U)
+#define PWM_INTERRUPT_STS_MASK (0x3f << PWM_INTERRUPT_STS_SHIFT)
+#define PWM_INT_CLEAR_SHIFT (8U)
+#define PWM_INT_CLEAR_MASK (0x3f << PWM_INT_CLEAR_SHIFT)
+
+/* 0x20 : pwm0_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x24 : pwm0_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x28 : pwm0_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x2C : pwm0_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x30 : pwm0_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV (1 << 2U)
+#define PWM_STOP_MODE (1 << 3U)
+#define PWM_SW_FORCE_VAL (1 << 4U)
+#define PWM_SW_MODE (1 << 5U)
+#define PWM_STOP_EN (1 << 6U)
+#define PWM_STS_TOP (1 << 7U)
+
+/* 0x34 : pwm0_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE (1 << 16U)
+
+/* 0x40 : pwm1_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x44 : pwm1_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x48 : pwm1_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x4C : pwm1_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x50 : pwm1_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV (1 << 2U)
+#define PWM_STOP_MODE (1 << 3U)
+#define PWM_SW_FORCE_VAL (1 << 4U)
+#define PWM_SW_MODE (1 << 5U)
+#define PWM_STOP_EN (1 << 6U)
+#define PWM_STS_TOP (1 << 7U)
+
+/* 0x54 : pwm1_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE (1 << 16U)
+
+/* 0x60 : pwm2_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x64 : pwm2_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x68 : pwm2_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x6C : pwm2_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x70 : pwm2_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV (1 << 2U)
+#define PWM_STOP_MODE (1 << 3U)
+#define PWM_SW_FORCE_VAL (1 << 4U)
+#define PWM_SW_MODE (1 << 5U)
+#define PWM_STOP_EN (1 << 6U)
+#define PWM_STS_TOP (1 << 7U)
+
+/* 0x74 : pwm2_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE (1 << 16U)
+
+/* 0x80 : pwm3_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x84 : pwm3_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x88 : pwm3_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x8C : pwm3_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x90 : pwm3_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV (1 << 2U)
+#define PWM_STOP_MODE (1 << 3U)
+#define PWM_SW_FORCE_VAL (1 << 4U)
+#define PWM_SW_MODE (1 << 5U)
+#define PWM_STOP_EN (1 << 6U)
+#define PWM_STS_TOP (1 << 7U)
+
+/* 0x94 : pwm3_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE (1 << 16U)
+
+/* 0xA0 : pwm4_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0xA4 : pwm4_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT)
+
+/* 0xA8 : pwm4_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT)
+
+/* 0xAC : pwm4_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0xB0 : pwm4_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV (1 << 2U)
+#define PWM_STOP_MODE (1 << 3U)
+#define PWM_SW_FORCE_VAL (1 << 4U)
+#define PWM_SW_MODE (1 << 5U)
+#define PWM_STOP_EN (1 << 6U)
+#define PWM_STS_TOP (1 << 7U)
+
+/* 0xB4 : pwm4_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE (1 << 16U)
+
+#endif /* __PWM_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/pwm_v2_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/pwm_v2_reg.h
new file mode 100644
index 00000000..b69b385e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/pwm_v2_reg.h
@@ -0,0 +1,208 @@
+/**
+ ******************************************************************************
+ * @file pwm_reg.h
+ * @version V1.0
+ * @date 2022-08-15
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_PWM_V2_H__
+#define __HARDWARE_PWM_V2_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */
+#define PWM_MC0_CONFIG0_OFFSET (0x40) /* pwm_mc0_config0 */
+#define PWM_MC0_CONFIG1_OFFSET (0x44) /* pwm_mc0_config1 */
+#define PWM_MC0_PERIOD_OFFSET (0x48) /* pwm_mc0_period */
+#define PWM_MC0_DEAD_TIME_OFFSET (0x4C) /* pwm_mc0_dead_time */
+#define PWM_MC0_CH0_THRE_OFFSET (0x50) /* pwm_mc0_ch0_thre */
+#define PWM_MC0_CH1_THRE_OFFSET (0x54) /* pwm_mc0_ch1_thre */
+#define PWM_MC0_CH2_THRE_OFFSET (0x58) /* pwm_mc0_ch2_thre */
+#define PWM_MC0_CH3_THRE_OFFSET (0x5C) /* pwm_mc0_ch3_thre */
+#define PWM_MC0_INT_STS_OFFSET (0x60) /* pwm_mc0_int_sts */
+#define PWM_MC0_INT_MASK_OFFSET (0x64) /* pwm_mc0_int_mask */
+#define PWM_MC0_INT_CLEAR_OFFSET (0x68) /* pwm_mc0_int_clear */
+#define PWM_MC0_INT_EN_OFFSET (0x6C) /* pwm_mc0_int_en */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : pwm_int_config */
+#define PWM0_INT_STS (1 << 0U)
+#define PWM1_INT_STS (1 << 1U)
+#define PWM0_INT_CLR (1 << 8U)
+#define PWM1_INT_CLR (1 << 9U)
+
+/* 0x40 : pwm_mc0_config0 */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT)
+#define PWM_STOP_ON_REPT (1 << 19U)
+#define PWM_ADC_TRG_SRC_SHIFT (20U)
+#define PWM_ADC_TRG_SRC_MASK (0xf << PWM_ADC_TRG_SRC_SHIFT)
+#define PWM_SW_BREAK_EN (1 << 24U)
+#define PWM_EXT_BREAK_EN (1 << 25U)
+#define PWM_EXT_BREAK_PL (1 << 26U)
+#define PWM_STOP_EN (1 << 27U)
+#define PWM_STOP_MODE (1 << 28U)
+#define PWM_STS_STOP (1 << 29U)
+#define PWM_REG_CLK_SEL_SHIFT (30U)
+#define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT)
+
+/* 0x44 : pwm_mc0_config1 */
+#define PWM_CH0_PEN (1 << 0U)
+#define PWM_CH0_PSI (1 << 1U)
+#define PWM_CH0_NEN (1 << 2U)
+#define PWM_CH0_NSI (1 << 3U)
+#define PWM_CH1_PEN (1 << 4U)
+#define PWM_CH1_PSI (1 << 5U)
+#define PWM_CH1_NEN (1 << 6U)
+#define PWM_CH1_NSI (1 << 7U)
+#define PWM_CH2_PEN (1 << 8U)
+#define PWM_CH2_PSI (1 << 9U)
+#define PWM_CH2_NEN (1 << 10U)
+#define PWM_CH2_NSI (1 << 11U)
+#define PWM_CH3_PEN (1 << 12U)
+#define PWM_CH3_PSI (1 << 13U)
+#define PWM_CH3_NEN (1 << 14U)
+#define PWM_CH3_NSI (1 << 15U)
+#define PWM_CH0_PPL (1 << 16U)
+#define PWM_CH0_NPL (1 << 17U)
+#define PWM_CH1_PPL (1 << 18U)
+#define PWM_CH1_NPL (1 << 19U)
+#define PWM_CH2_PPL (1 << 20U)
+#define PWM_CH2_NPL (1 << 21U)
+#define PWM_CH3_PPL (1 << 22U)
+#define PWM_CH3_NPL (1 << 23U)
+#define PWM_CH0_PBS (1 << 24U)
+#define PWM_CH0_NBS (1 << 25U)
+#define PWM_CH1_PBS (1 << 26U)
+#define PWM_CH1_NBS (1 << 27U)
+#define PWM_CH2_PBS (1 << 28U)
+#define PWM_CH2_NBS (1 << 29U)
+#define PWM_CH3_PBS (1 << 30U)
+#define PWM_CH3_NBS (1 << 31U)
+
+/* 0x48 : pwm_mc0_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT)
+#define PWM_INT_PERIOD_CNT_SHIFT (16U)
+#define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+
+/* 0x4C : pwm_mc0_dead_time */
+#define PWM_CH0_DTG_SHIFT (0U)
+#define PWM_CH0_DTG_MASK (0xff << PWM_CH0_DTG_SHIFT)
+#define PWM_CH1_DTG_SHIFT (8U)
+#define PWM_CH1_DTG_MASK (0xff << PWM_CH1_DTG_SHIFT)
+#define PWM_CH2_DTG_SHIFT (16U)
+#define PWM_CH2_DTG_MASK (0xff << PWM_CH2_DTG_SHIFT)
+#define PWM_CH3_DTG_SHIFT (24U)
+#define PWM_CH3_DTG_MASK (0xff << PWM_CH3_DTG_SHIFT)
+
+/* 0x50 : pwm_mc0_ch0_thre */
+#define PWM_CH0_THREL_SHIFT (0U)
+#define PWM_CH0_THREL_MASK (0xffff << PWM_CH0_THREL_SHIFT)
+#define PWM_CH0_THREH_SHIFT (16U)
+#define PWM_CH0_THREH_MASK (0xffff << PWM_CH0_THREH_SHIFT)
+
+/* 0x54 : pwm_mc0_ch1_thre */
+#define PWM_CH1_THREL_SHIFT (0U)
+#define PWM_CH1_THREL_MASK (0xffff << PWM_CH1_THREL_SHIFT)
+#define PWM_CH1_THREH_SHIFT (16U)
+#define PWM_CH1_THREH_MASK (0xffff << PWM_CH1_THREH_SHIFT)
+
+/* 0x58 : pwm_mc0_ch2_thre */
+#define PWM_CH2_THREL_SHIFT (0U)
+#define PWM_CH2_THREL_MASK (0xffff << PWM_CH2_THREL_SHIFT)
+#define PWM_CH2_THREH_SHIFT (16U)
+#define PWM_CH2_THREH_MASK (0xffff << PWM_CH2_THREH_SHIFT)
+
+/* 0x5C : pwm_mc0_ch3_thre */
+#define PWM_CH3_THREL_SHIFT (0U)
+#define PWM_CH3_THREL_MASK (0xffff << PWM_CH3_THREL_SHIFT)
+#define PWM_CH3_THREH_SHIFT (16U)
+#define PWM_CH3_THREH_MASK (0xffff << PWM_CH3_THREH_SHIFT)
+
+/* 0x60 : pwm_mc0_int_sts */
+#define PWM_CH0L_INT (1 << 0U)
+#define PWM_CH0H_INT (1 << 1U)
+#define PWM_CH1L_INT (1 << 2U)
+#define PWM_CH1H_INT (1 << 3U)
+#define PWM_CH2L_INT (1 << 4U)
+#define PWM_CH2H_INT (1 << 5U)
+#define PWM_CH3L_INT (1 << 6U)
+#define PWM_CH3H_INT (1 << 7U)
+#define PWM_PRDE_INT (1 << 8U)
+#define PWM_BRK_INT (1 << 9U)
+#define PWM_REPT_INT (1 << 10U)
+
+/* 0x64 : pwm_mc0_int_mask */
+#define PWM_CR_PWM_CH0L_MASK (1 << 0U)
+#define PWM_CR_PWM_CH0H_MASK (1 << 1U)
+#define PWM_CR_PWM_CH1L_MASK (1 << 2U)
+#define PWM_CR_PWM_CH1H_MASK (1 << 3U)
+#define PWM_CR_PWM_CH2L_MASK (1 << 4U)
+#define PWM_CR_PWM_CH2H_MASK (1 << 5U)
+#define PWM_CR_PWM_CH3L_MASK (1 << 6U)
+#define PWM_CR_PWM_CH3H_MASK (1 << 7U)
+#define PWM_CR_PWM_PRDE_MASK (1 << 8U)
+#define PWM_CR_PWM_BRK_MASK (1 << 9U)
+#define PWM_CR_PWM_REPT_MASK (1 << 10U)
+
+/* 0x68 : pwm_mc0_int_clear */
+#define PWM_CR_PWM_CH0L_CLR (1 << 0U)
+#define PWM_CR_PWM_CH0H_CLR (1 << 1U)
+#define PWM_CR_PWM_CH1L_CLR (1 << 2U)
+#define PWM_CR_PWM_CH1H_CLR (1 << 3U)
+#define PWM_CR_PWM_CH2L_CLR (1 << 4U)
+#define PWM_CR_PWM_CH2H_CLR (1 << 5U)
+#define PWM_CR_PWM_CH3L_CLR (1 << 6U)
+#define PWM_CR_PWM_CH3H_CLR (1 << 7U)
+#define PWM_CR_PWM_PRDE_CLR (1 << 8U)
+#define PWM_CR_PWM_BRK_CLR (1 << 9U)
+#define PWM_CR_PWM_REPT_CLR (1 << 10U)
+
+/* 0x6C : pwm_mc0_int_en */
+#define PWM_CR_PWM_CH0L_EN (1 << 0U)
+#define PWM_CR_PWM_CH0H_EN (1 << 1U)
+#define PWM_CR_PWM_CH1L_EN (1 << 2U)
+#define PWM_CR_PWM_CH1H_EN (1 << 3U)
+#define PWM_CR_PWM_CH2L_EN (1 << 4U)
+#define PWM_CR_PWM_CH2H_EN (1 << 5U)
+#define PWM_CR_PWM_CH3L_EN (1 << 6U)
+#define PWM_CR_PWM_CH3H_EN (1 << 7U)
+#define PWM_CR_PWM_PRDE_EN (1 << 8U)
+#define PWM_CR_PWM_BRK_EN (1 << 9U)
+#define PWM_CR_PWM_REPT_EN (1 << 10U)
+
+#endif /* __HARDWARE_PWM_V2_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/rtc_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/rtc_reg.h
new file mode 100644
index 00000000..dee3bfee
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/rtc_reg.h
@@ -0,0 +1,92 @@
+/**
+ ******************************************************************************
+ * @file rtc_reg.h
+ * @version V1.0
+ * @date 2022-08-05
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_RTC_H__
+#define __HARDWARE_RTC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define HBN_CTL_OFFSET (0x0) /* HBN_CTL */
+#define HBN_TIME_L_OFFSET (0x4) /* HBN_TIME_L */
+#define HBN_TIME_H_OFFSET (0x8) /* HBN_TIME_H */
+#define HBN_RTC_TIME_L_OFFSET (0xC) /* RTC_TIME_L */
+#define HBN_RTC_TIME_H_OFFSET (0x10) /* RTC_TIME_H */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : HBN_CTL */
+#define HBN_RTC_CTL_SHIFT (0U)
+#define HBN_RTC_CTL_MASK (0x7f << HBN_RTC_CTL_SHIFT)
+#define HBN_MODE (1 << 7U)
+#define HBN_TRAP_MODE (1 << 8U)
+#define HBN_PWRDN_HBN_CORE (1 << 9U)
+#define HBN_PWRDN_HBN_RTC (1 << 11U)
+#define HBN_SW_RST (1 << 12U)
+#define HBN_DIS_PWR_OFF_LDO11 (1 << 13U)
+#define HBN_DIS_PWR_OFF_LDO11_RT (1 << 14U)
+#define HBN_LDO11_RT_VOUT_SEL_SHIFT (15U)
+#define HBN_LDO11_RT_VOUT_SEL_MASK (0xf << HBN_LDO11_RT_VOUT_SEL_SHIFT)
+#define HBN_LDO11_AON_VOUT_SEL_SHIFT (19U)
+#define HBN_LDO11_AON_VOUT_SEL_MASK (0xf << HBN_LDO11_AON_VOUT_SEL_SHIFT)
+#define HBN_PU_DCDC18_AON (1 << 23U)
+#define HBN_RTC_DLY_OPTION (1 << 24U)
+#define HBN_PWR_ON_OPTION (1 << 25U)
+#define HBN_SRAM_SLP_OPTION (1 << 26U)
+#define HBN_SRAM_SLP (1 << 27U)
+#define HBN_STATE_SHIFT (28U)
+#define HBN_STATE_MASK (0xf << HBN_STATE_SHIFT)
+
+/* 0x4 : HBN_TIME_L */
+#define HBN_TIME_L_SHIFT (0U)
+#define HBN_TIME_L_MASK (0xffffffff << HBN_TIME_L_SHIFT)
+
+/* 0x8 : HBN_TIME_H */
+#define HBN_TIME_H_SHIFT (0U)
+#define HBN_TIME_H_MASK (0xff << HBN_TIME_H_SHIFT)
+
+/* 0xC : RTC_TIME_L */
+#define HBN_RTC_TIME_LATCH_L_SHIFT (0U)
+#define HBN_RTC_TIME_LATCH_L_MASK (0xffffffff << HBN_RTC_TIME_LATCH_L_SHIFT)
+
+/* 0x10 : RTC_TIME_H */
+#define HBN_RTC_TIME_LATCH_H_SHIFT (0U)
+#define HBN_RTC_TIME_LATCH_H_MASK (0xff << HBN_RTC_TIME_LATCH_H_SHIFT)
+#define HBN_RTC_TIME_LATCH (1 << 31U)
+
+#endif /* __HARDWARE_RTC_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sdio2_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sdio2_reg.h
new file mode 100644
index 00000000..9862a41e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sdio2_reg.h
@@ -0,0 +1,139 @@
+/**
+ ******************************************************************************
+ * @file sdio2.h
+ * @version V1.0
+ * @date 2022-08-03
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_SDIO2_H__
+#define __HARDWARE_SDIO2_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SDIO2_IO_ENABLE_OFFSET (0x0002) /* SDIO I/O Enable */
+#define SDIO2_FN1_BLK_SIZE_0_OFFSET (0x0028) /* SDIO block size infor */
+#define SDIO2_FN1_BLK_SIZE_1_OFFSET (0x0029) /* SDIO block size infor */
+#define SDIO2_DEV_SLEEP_OFFSET (0x0092) /* SDIO Device Sleep */
+#define SDIO2_CCR_FUNC_OFFSET (0x0100) /* Address offset of CCR between two functions */
+#define SDIO2_HOST_TO_CARD_EVENT_OFFSET (0x0100)
+#define SDIO2_HOST_INT_CAUSE_OFFSET (0x0101)
+#define SDIO2_HOST_INT_MASK_OFFSET (0x0102)
+#define SDIO2_HOST_INT_STATUS_OFFSET (0x0103)
+#define SDIO2_RD_BIT_MAP_OFFSET (0x0104)
+#define SDIO2_WR_BIT_MAP_OFFSET (0x0106)
+#define SDIO2_RD_LEN_OFFSET (0x0108)
+#define SDIO2_HOST_TRANS_STATUS_OFFSET (0x0128)
+#define SDIO2_CARD_TO_HOST_EVENT_OFFSET (0x0130)
+#define SDIO2_CARD_INT_MASK_OFFSET (0x0134)
+#define SDIO2_CARD_INT_STATUS_OFFSET (0x0138)
+#define SDIO2_CARD_INT_MODE_OFFSET (0x013C)
+#define SDIO2_SQ_READ_BASE_OFFSET (0x0140)
+#define SDIO2_SQ_WRITE_BASE_OFFSET (0x0144)
+#define SDIO2_READ_INDEX_OFFSET (0x0148)
+#define SDIO2_WRITE_INDEX_OFFSET (0x0149)
+#define SDIO2_DNLD_QUEUE_WRPTR_OFFSET (0x014A)
+#define SDIO2_UPLD_QUEUE_WRPTR_OFFSET (0x014B)
+#define SDIO2_DNLD_QUEUE_OFFSET (0x014C)
+#define SDIO2_UPLD_QUEUE_OFFSET (0x0154)
+#define SDIO2_CHIP_VERSION_OFFSET (0x015C)
+#define SDIO2_IP_VERSION0_OFFSET (0x015E)
+#define SDIO2_IP_VERSION1_OFFSET (0x015F)
+#define SDIO2_SCRATCH2_OFFSET (0x0164)
+#define SDIO2_SCRATCH1_OFFSET (0x0166)
+#define SDIO2_OCR0_OFFSET (0x0168)
+#define SDIO2_OCR1_OFFSET (0x0169)
+#define SDIO2_OCR2_OFFSET (0x016A)
+#define SDIO2_CONFIG_OFFSET (0x016B)
+#define SDIO2_CONFIG2_OFFSET (0x016C)
+#define SDIO2_DEBUG_OFFSET (0x0170)
+#define SDIO2_DMA_ADDR_OFFSET (0x0174)
+#define SDIO2_IO_PORT_OFFSET (0x0178)
+
+
+// Bit Def. Scratch register 0
+#define SDIO2_SCRATCH_OFFSET (0x0160)
+
+// Bit Def. Block size 1 mask (Offset 0x29)
+#define SDIO2_FN1_BLK_SIZE_1_MASK 0x01
+
+// Bit Def. Host To Card Interrupt Event (Offset 0x100/200)
+#define SDIO2_HCR_CONFIG_HostPwrUp (1 << 1)
+
+// Bit Def. Host Transfer Status (Offset 0x128/228)
+#define SDIO2_CCR_HOST_INT_DnLdReStart (1 << 0)
+#define SDIO2_CCR_HOST_INT_UpLdReStart (1 << 1)
+#define SDIO2_CCR_HOST_INT_DnLdCRC_err (1 << 2)
+
+// Bit Def. Card To Host Interrupt Event (Offset 0x130/230)
+#define SDIO2_CCR_CS_DnLdRdy (1 << 0)
+#define SDIO2_CCR_CS_UpLdRdy (1 << 1)
+#define SDIO2_CCR_CS_ReadCISRdy (1 << 2)
+#define SDIO2_CCR_CS_IORdy (1 << 3)
+
+// Bit Def. Card Interrupt Mask (Offset 0x134/234)
+#define SDIO2_CCR_CIM_DnLdOvr (1 << 0)
+#define SDIO2_CCR_CIM_UpLdOvr (1 << 1)
+#define SDIO2_CCR_CIM_Abort (1 << 2)
+#define SDIO2_CCR_CIM_PwrDn (1 << 3)
+#define SDIO2_CCR_CIM_PwrUp (1 << 4)
+
+#define SDIO2_CCR_CIM_MASK 0x0007
+
+// Bit Def. Card Interrupt Status (Offset 0x138/238)
+#define SDIO2_CCR_CIC_DnLdOvr (1 << 0)
+#define SDIO2_CCR_CIC_UpLdOvr (1 << 1)
+#define SDIO2_CCR_CIC_Abort (1 << 2)
+#define SDIO2_CCR_CIC_PwrDn (1 << 3)
+#define SDIO2_CCR_CIC_PwrUp (1 << 4)
+
+#define SDIO2_CCR_CIC_MASK 0x001F
+
+// Bit Def. Card Interrupt RSR (Offset 0x13C/23C)
+#define SDIO2_CCR_CIO_DnLdOvr (1 << 0)
+#define SDIO2_CCR_CIO_UpLdOvr (1 << 1)
+#define SDIO2_CCR_CIO_Abort (1 << 2)
+#define SDIO2_CCR_CIO_PwrDn (1 << 3)
+#define SDIO2_CCR_CIO_PwrUp (1 << 4)
+#define SDIO2_CCR_CIO_MASK 0x001F
+
+//Config2 register mask
+#define SDIO2_CONFIG2_MSK 0x00000C00
+
+//CardIntMode register mask
+
+#define SDIO2_CARD_INT_MODE_MSK 0x00000003
+#define SDIO2_HOST_INT_MSK 0x00000002
+
+#endif /* __HARDWARE_SDIO2_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sec_eng_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sec_eng_reg.h
new file mode 100644
index 00000000..54e99c4a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sec_eng_reg.h
@@ -0,0 +1,558 @@
+/**
+ ******************************************************************************
+ * @file sec_eng_reg.h
+ * @version V1.0
+ * @date 2022-08-15
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_SEC_ENG_H__
+#define __HARDWARE_SEC_ENG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) /* se_sha_0_ctrl */
+#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4) /* se_sha_0_msa */
+#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8) /* se_sha_0_status */
+#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET (0xC) /* se_sha_0_endian */
+#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10) /* se_sha_0_hash_l_0 */
+#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14) /* se_sha_0_hash_l_1 */
+#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18) /* se_sha_0_hash_l_2 */
+#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C) /* se_sha_0_hash_l_3 */
+#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20) /* se_sha_0_hash_l_4 */
+#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24) /* se_sha_0_hash_l_5 */
+#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28) /* se_sha_0_hash_l_6 */
+#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C) /* se_sha_0_hash_l_7 */
+#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30) /* se_sha_0_hash_h_0 */
+#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34) /* se_sha_0_hash_h_1 */
+#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38) /* se_sha_0_hash_h_2 */
+#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C) /* se_sha_0_hash_h_3 */
+#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40) /* se_sha_0_hash_h_4 */
+#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44) /* se_sha_0_hash_h_5 */
+#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48) /* se_sha_0_hash_h_6 */
+#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C) /* se_sha_0_hash_h_7 */
+#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50) /* se_sha_0_link */
+#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC) /* se_sha_0_ctrl_prot */
+#define SEC_ENG_SE_AES_0_CTRL_OFFSET (0x100) /* se_aes_0_ctrl */
+#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104) /* se_aes_0_msa */
+#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108) /* se_aes_0_mda */
+#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C) /* se_aes_0_status */
+#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110) /* se_aes_0_iv_0 */
+#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114) /* se_aes_0_iv_1 */
+#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118) /* se_aes_0_iv_2 */
+#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C) /* se_aes_0_iv_3 */
+#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120) /* se_aes_0_key_0 */
+#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124) /* se_aes_0_key_1 */
+#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128) /* se_aes_0_key_2 */
+#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C) /* se_aes_0_key_3 */
+#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130) /* se_aes_0_key_4 */
+#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134) /* se_aes_0_key_5 */
+#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138) /* se_aes_0_key_6 */
+#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C) /* se_aes_0_key_7 */
+#define SEC_ENG_SE_AES_0_KEY_SEL_OFFSET (0x140) /* se_aes_0_key_sel */
+#define SEC_ENG_SE_AES_1_KEY_SEL_OFFSET (0x144) /* se_aes_1_key_sel */
+#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET (0x148) /* se_aes_0_endian */
+#define SEC_ENG_SE_AES_0_SBOOT_OFFSET (0x14C) /* se_aes_0_sboot */
+#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150) /* se_aes_0_link */
+#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC) /* se_aes_0_ctrl_prot */
+#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET (0x200) /* se_trng_0_ctrl_0 */
+#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204) /* se_trng_0_status */
+#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208) /* se_trng_0_dout_0 */
+#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C) /* se_trng_0_dout_1 */
+#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210) /* se_trng_0_dout_2 */
+#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214) /* se_trng_0_dout_3 */
+#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218) /* se_trng_0_dout_4 */
+#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C) /* se_trng_0_dout_5 */
+#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220) /* se_trng_0_dout_6 */
+#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224) /* se_trng_0_dout_7 */
+#define SEC_ENG_SE_TRNG_0_TEST_OFFSET (0x228) /* se_trng_0_test */
+#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET (0x22C) /* se_trng_0_ctrl_1 */
+#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET (0x230) /* se_trng_0_ctrl_2 */
+#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234) /* se_trng_0_ctrl_3 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) /* se_trng_0_test_out_0 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) /* se_trng_0_test_out_1 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) /* se_trng_0_test_out_2 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) /* se_trng_0_test_out_3 */
+#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC) /* se_trng_0_ctrl_prot */
+#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET (0x300) /* se_pka_0_ctrl_0 */
+#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C) /* se_pka_0_seed */
+#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310) /* se_pka_0_ctrl_1 */
+#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340) /* se_pka_0_rw */
+#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360) /* se_pka_0_rw_burst */
+#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC) /* se_pka_0_ctrl_prot */
+#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET (0x400) /* se_cdet_0_ctrl_0 */
+#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404) /* se_cdet_0_ctrl_1 */
+#define SEC_ENG_SE_CDET_0_CTRL_2_OFFSET (0x408) /* se_cdet_0_ctrl_2 */
+#define SEC_ENG_SE_CDET_0_CTRL_3_OFFSET (0x40C) /* se_cdet_0_ctrl_3 */
+#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC) /* se_cdet_0_ctrl_prot */
+#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET (0x500) /* se_gmac_0_ctrl_0 */
+#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504) /* se_gmac_0_lca */
+#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508) /* se_gmac_0_status */
+#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC) /* se_gmac_0_ctrl_prot */
+#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET (0xF00) /* se_ctrl_prot_rd */
+#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04) /* se_ctrl_reserved_0 */
+#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08) /* se_ctrl_reserved_1 */
+#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C) /* se_ctrl_reserved_2 */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : se_sha_0_ctrl */
+#define SEC_ENG_SE_SHA_0_BUSY (1 << 0U)
+#define SEC_ENG_SE_SHA_0_TRIG_1T (1 << 1U)
+#define SEC_ENG_SE_SHA_0_MODE_SHIFT (2U)
+#define SEC_ENG_SE_SHA_0_MODE_MASK (0x7 << SEC_ENG_SE_SHA_0_MODE_SHIFT)
+#define SEC_ENG_SE_SHA_0_EN (1 << 5U)
+#define SEC_ENG_SE_SHA_0_HASH_SEL (1 << 6U)
+#define SEC_ENG_SE_SHA_0_INT (1 << 8U)
+#define SEC_ENG_SE_SHA_0_INT_CLR_1T (1 << 9U)
+#define SEC_ENG_SE_SHA_0_INT_SET_1T (1 << 10U)
+#define SEC_ENG_SE_SHA_0_INT_MASK (1 << 11U)
+#define SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT (12U)
+#define SEC_ENG_SE_SHA_0_MODE_EXT_MASK (0x3 << SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT)
+#define SEC_ENG_SE_SHA_0_LINK_MODE (1 << 15U)
+#define SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT (16U)
+#define SEC_ENG_SE_SHA_0_MSG_LEN_MASK (0xffff << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT)
+
+/* 0x4 : se_sha_0_msa */
+#define SEC_ENG_SE_SHA_0_MSA_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_MSA_MASK (0xffffffff << SEC_ENG_SE_SHA_0_MSA_SHIFT)
+
+/* 0x8 : se_sha_0_status */
+#define SEC_ENG_SE_SHA_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_SHA_0_STATUS_SHIFT)
+
+/* 0xC : se_sha_0_endian */
+#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN (1 << 0U)
+
+/* 0x10 : se_sha_0_hash_l_0 */
+#define SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_0_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT)
+
+/* 0x14 : se_sha_0_hash_l_1 */
+#define SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_1_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT)
+
+/* 0x18 : se_sha_0_hash_l_2 */
+#define SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_2_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT)
+
+/* 0x1C : se_sha_0_hash_l_3 */
+#define SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_3_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT)
+
+/* 0x20 : se_sha_0_hash_l_4 */
+#define SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_4_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT)
+
+/* 0x24 : se_sha_0_hash_l_5 */
+#define SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_5_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT)
+
+/* 0x28 : se_sha_0_hash_l_6 */
+#define SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_6_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT)
+
+/* 0x2C : se_sha_0_hash_l_7 */
+#define SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_7_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT)
+
+/* 0x30 : se_sha_0_hash_h_0 */
+#define SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_0_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT)
+
+/* 0x34 : se_sha_0_hash_h_1 */
+#define SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_1_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT)
+
+/* 0x38 : se_sha_0_hash_h_2 */
+#define SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_2_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT)
+
+/* 0x3C : se_sha_0_hash_h_3 */
+#define SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_3_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT)
+
+/* 0x40 : se_sha_0_hash_h_4 */
+#define SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_4_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT)
+
+/* 0x44 : se_sha_0_hash_h_5 */
+#define SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_5_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT)
+
+/* 0x48 : se_sha_0_hash_h_6 */
+#define SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_6_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT)
+
+/* 0x4C : se_sha_0_hash_h_7 */
+#define SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_7_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT)
+
+/* 0x50 : se_sha_0_link */
+#define SEC_ENG_SE_SHA_0_LCA_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_LCA_MASK (0xffffffff << SEC_ENG_SE_SHA_0_LCA_SHIFT)
+
+/* 0xFC : se_sha_0_ctrl_prot */
+#define SEC_ENG_SE_SHA_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_SHA_ID1_EN (1 << 2U)
+
+/* 0x100 : se_aes_0_ctrl */
+#define SEC_ENG_SE_AES_0_BUSY (1 << 0U)
+#define SEC_ENG_SE_AES_0_TRIG_1T (1 << 1U)
+#define SEC_ENG_SE_AES_0_EN (1 << 2U)
+#define SEC_ENG_SE_AES_0_MODE_SHIFT (3U)
+#define SEC_ENG_SE_AES_0_MODE_MASK (0x3 << SEC_ENG_SE_AES_0_MODE_SHIFT)
+#define SEC_ENG_SE_AES_0_DEC_EN (1 << 5U)
+#define SEC_ENG_SE_AES_0_DEC_KEY_SEL (1 << 6U)
+#define SEC_ENG_SE_AES_0_HW_KEY_EN (1 << 7U)
+#define SEC_ENG_SE_AES_0_INT (1 << 8U)
+#define SEC_ENG_SE_AES_0_INT_CLR_1T (1 << 9U)
+#define SEC_ENG_SE_AES_0_INT_SET_1T (1 << 10U)
+#define SEC_ENG_SE_AES_0_INT_MASK (1 << 11U)
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT (12U)
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_MASK (0x3 << SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT)
+#define SEC_ENG_SE_AES_0_IV_SEL (1 << 14U)
+#define SEC_ENG_SE_AES_0_LINK_MODE (1 << 15U)
+#define SEC_ENG_SE_AES_0_MSG_LEN_SHIFT (16U)
+#define SEC_ENG_SE_AES_0_MSG_LEN_MASK (0xffff << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT)
+
+/* 0x104 : se_aes_0_msa */
+#define SEC_ENG_SE_AES_0_MSA_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_MSA_MASK (0xffffffff << SEC_ENG_SE_AES_0_MSA_SHIFT)
+
+/* 0x108 : se_aes_0_mda */
+#define SEC_ENG_SE_AES_0_MDA_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_MDA_MASK (0xffffffff << SEC_ENG_SE_AES_0_MDA_SHIFT)
+
+/* 0x10C : se_aes_0_status */
+#define SEC_ENG_SE_AES_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_AES_0_STATUS_SHIFT)
+
+/* 0x110 : se_aes_0_iv_0 */
+#define SEC_ENG_SE_AES_0_IV_0_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_0_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_0_SHIFT)
+
+/* 0x114 : se_aes_0_iv_1 */
+#define SEC_ENG_SE_AES_0_IV_1_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_1_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_1_SHIFT)
+
+/* 0x118 : se_aes_0_iv_2 */
+#define SEC_ENG_SE_AES_0_IV_2_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_2_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_2_SHIFT)
+
+/* 0x11C : se_aes_0_iv_3 */
+#define SEC_ENG_SE_AES_0_IV_3_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_3_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_3_SHIFT)
+
+/* 0x120 : se_aes_0_key_0 */
+#define SEC_ENG_SE_AES_0_KEY_0_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_0_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_0_SHIFT)
+
+/* 0x124 : se_aes_0_key_1 */
+#define SEC_ENG_SE_AES_0_KEY_1_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_1_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_1_SHIFT)
+
+/* 0x128 : se_aes_0_key_2 */
+#define SEC_ENG_SE_AES_0_KEY_2_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_2_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_2_SHIFT)
+
+/* 0x12C : se_aes_0_key_3 */
+#define SEC_ENG_SE_AES_0_KEY_3_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_3_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_3_SHIFT)
+
+/* 0x130 : se_aes_0_key_4 */
+#define SEC_ENG_SE_AES_0_KEY_4_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_4_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_4_SHIFT)
+
+/* 0x134 : se_aes_0_key_5 */
+#define SEC_ENG_SE_AES_0_KEY_5_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_5_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_5_SHIFT)
+
+/* 0x138 : se_aes_0_key_6 */
+#define SEC_ENG_SE_AES_0_KEY_6_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_6_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_6_SHIFT)
+
+/* 0x13C : se_aes_0_key_7 */
+#define SEC_ENG_SE_AES_0_KEY_7_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_7_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_7_SHIFT)
+
+/* 0x140 : se_aes_0_key_sel */
+#define SEC_ENG_SE_AES_0_KEY_SEL_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_SEL_MASK (0x3 << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT)
+
+/* 0x144 : se_aes_1_key_sel */
+#define SEC_ENG_SE_AES_1_KEY_SEL_SHIFT (0U)
+#define SEC_ENG_SE_AES_1_KEY_SEL_MASK (0x3 << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT)
+
+/* 0x148 : se_aes_0_endian */
+#define SEC_ENG_SE_AES_0_DOUT_ENDIAN (1 << 0U)
+#define SEC_ENG_SE_AES_0_DIN_ENDIAN (1 << 1U)
+#define SEC_ENG_SE_AES_0_KEY_ENDIAN (1 << 2U)
+#define SEC_ENG_SE_AES_0_IV_ENDIAN (1 << 3U)
+#define SEC_ENG_SE_AES_0_TWK_ENDIAN (1 << 4U)
+#define SEC_ENG_SE_AES_0_CTR_LEN_SHIFT (30U)
+#define SEC_ENG_SE_AES_0_CTR_LEN_MASK (0x3 << SEC_ENG_SE_AES_0_CTR_LEN_SHIFT)
+
+/* 0x14C : se_aes_sboot */
+#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL (1 << 0U)
+#define SEC_ENG_SE_AES_0_XTS_MODE (1 << 15U)
+#define SEC_ENG_SE_AES_0_UNI_LEN_SHIFT (16U)
+#define SEC_ENG_SE_AES_0_UNI_LEN_MASK (0xffff << SEC_ENG_SE_AES_0_UNI_LEN_SHIFT)
+
+/* 0x150 : se_aes_0_link */
+#define SEC_ENG_SE_AES_0_LCA_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_LCA_MASK (0xffffffff << SEC_ENG_SE_AES_0_LCA_SHIFT)
+
+/* 0x1FC : se_aes_0_ctrl_prot */
+#define SEC_ENG_SE_AES_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_AES_ID1_EN (1 << 2U)
+
+/* 0x200 : se_trng_0_ctrl_0 */
+#define SEC_ENG_SE_TRNG_0_BUSY (1 << 0U)
+#define SEC_ENG_SE_TRNG_0_TRIG_1T (1 << 1U)
+#define SEC_ENG_SE_TRNG_0_EN (1 << 2U)
+#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T (1 << 3U)
+#define SEC_ENG_SE_TRNG_0_HT_ERROR (1 << 4U)
+#define SEC_ENG_SE_TRNG_0_INT (1 << 8U)
+#define SEC_ENG_SE_TRNG_0_INT_CLR_1T (1 << 9U)
+#define SEC_ENG_SE_TRNG_0_INT_SET_1T (1 << 10U)
+#define SEC_ENG_SE_TRNG_0_INT_MASK (1 << 11U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL (1 << 13U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED (1 << 14U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_EN (1 << 15U)
+
+/* 0x204 : se_trng_0_status */
+#define SEC_ENG_SE_TRNG_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_STATUS_SHIFT)
+
+/* 0x208 : se_trng_0_dout_0 */
+#define SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_0_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT)
+
+/* 0x20C : se_trng_0_dout_1 */
+#define SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_1_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT)
+
+/* 0x210 : se_trng_0_dout_2 */
+#define SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_2_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT)
+
+/* 0x214 : se_trng_0_dout_3 */
+#define SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_3_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT)
+
+/* 0x218 : se_trng_0_dout_4 */
+#define SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_4_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT)
+
+/* 0x21C : se_trng_0_dout_5 */
+#define SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_5_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT)
+
+/* 0x220 : se_trng_0_dout_6 */
+#define SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_6_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT)
+
+/* 0x224 : se_trng_0_dout_7 */
+#define SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_7_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT)
+
+/* 0x228 : se_trng_0_test */
+#define SEC_ENG_SE_TRNG_0_TEST_EN (1 << 0U)
+#define SEC_ENG_SE_TRNG_0_CP_TEST_EN (1 << 1U)
+#define SEC_ENG_SE_TRNG_0_CP_BYPASS (1 << 2U)
+#define SEC_ENG_SE_TRNG_0_HT_DIS (1 << 3U)
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT (4U)
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MASK (0xff << SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT)
+
+/* 0x22C : se_trng_0_ctrl_1 */
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT)
+
+/* 0x230 : se_trng_0_ctrl_2 */
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MASK (0xffff << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT)
+
+/* 0x234 : se_trng_0_ctrl_3 */
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_MASK (0xff << SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT)
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT (8U)
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MASK (0xff << SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT)
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT (16U)
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_MASK (0x3ff << SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT)
+#define SEC_ENG_SE_TRNG_0_HT_OD_EN (1 << 26U)
+#define SEC_ENG_SE_TRNG_0_ROSC_EN (1 << 31U)
+
+/* 0x240 : se_trng_0_test_out_0 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT)
+
+/* 0x244 : se_trng_0_test_out_1 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT)
+
+/* 0x248 : se_trng_0_test_out_2 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT)
+
+/* 0x24C : se_trng_0_test_out_3 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT)
+
+/* 0x2FC : se_trng_0_ctrl_prot */
+#define SEC_ENG_SE_TRNG_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_TRNG_ID1_EN (1 << 2U)
+
+/* 0x300 : se_pka_0_ctrl_0 */
+#define SEC_ENG_SE_PKA_0_DONE (1 << 0U)
+#define SEC_ENG_SE_PKA_0_DONE_CLR_1T (1 << 1U)
+#define SEC_ENG_SE_PKA_0_BUSY (1 << 2U)
+#define SEC_ENG_SE_PKA_0_EN (1 << 3U)
+#define SEC_ENG_SE_PKA_0_PROT_MD_SHIFT (4U)
+#define SEC_ENG_SE_PKA_0_PROT_MD_MASK (0xf << SEC_ENG_SE_PKA_0_PROT_MD_SHIFT)
+#define SEC_ENG_SE_PKA_0_INT (1 << 8U)
+#define SEC_ENG_SE_PKA_0_INT_CLR_1T (1 << 9U)
+#define SEC_ENG_SE_PKA_0_INT_SET (1 << 10U)
+#define SEC_ENG_SE_PKA_0_INT_MASK (1 << 11U)
+#define SEC_ENG_SE_PKA_0_ENDIAN (1 << 12U)
+#define SEC_ENG_SE_PKA_0_RAM_CLR_MD (1 << 13U)
+#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T (1 << 15U)
+#define SEC_ENG_SE_PKA_0_STATUS_SHIFT (16U)
+#define SEC_ENG_SE_PKA_0_STATUS_MASK (0xffff << SEC_ENG_SE_PKA_0_STATUS_SHIFT)
+
+/* 0x30C : se_pka_0_seed */
+#define SEC_ENG_SE_PKA_0_SEED_SHIFT (0U)
+#define SEC_ENG_SE_PKA_0_SEED_MASK (0xffffffff << SEC_ENG_SE_PKA_0_SEED_SHIFT)
+
+/* 0x310 : se_pka_0_ctrl_1 */
+#define SEC_ENG_SE_PKA_0_HBURST_SHIFT (0U)
+#define SEC_ENG_SE_PKA_0_HBURST_MASK (0x7 << SEC_ENG_SE_PKA_0_HBURST_SHIFT)
+#define SEC_ENG_SE_PKA_0_HBYPASS (1 << 3U)
+
+/* 0x340 : se_pka_0_rw */
+
+/* 0x360 : se_pka_0_rw_burst */
+
+/* 0x3FC : se_pka_0_ctrl_prot */
+#define SEC_ENG_SE_PKA_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_PKA_ID1_EN (1 << 2U)
+
+/* 0x400 : se_cdet_0_ctrl_0 */
+#define SEC_ENG_SE_CDET_0_EN (1 << 0U)
+#define SEC_ENG_SE_CDET_0_BUSY (1 << 1U)
+#define SEC_ENG_SE_CDET_0_STATUS_SHIFT (3U)
+#define SEC_ENG_SE_CDET_0_STATUS_MASK (0x1f << SEC_ENG_SE_CDET_0_STATUS_SHIFT)
+#define SEC_ENG_SE_CDET_0_INT (1 << 8U)
+#define SEC_ENG_SE_CDET_0_INT_CLR (1 << 9U)
+#define SEC_ENG_SE_CDET_0_INT_SET (1 << 10U)
+#define SEC_ENG_SE_CDET_0_INT_MASK (1 << 11U)
+#define SEC_ENG_SE_CDET_0_MODE (1 << 12U)
+
+/* 0x404 : se_cdet_0_ctrl_1 */
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT (0U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MASK (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT (16U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MASK (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT)
+
+/* 0x408 : se_cdet_0_ctrl_2 */
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT (0U)
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_MASK (0xffff << SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT)
+#define SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT (16U)
+#define SEC_ENG_SE_CDET_0_T_DLY_N_MASK (0xff << SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT)
+#define SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT (24U)
+#define SEC_ENG_SE_CDET_0_G_SLP_N_MASK (0xff << SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT)
+
+/* 0x40C : se_cdet_0_ctrl_3 */
+#define SEC_ENG_SE_CDET_0_T_COUNT_SHIFT (0U)
+#define SEC_ENG_SE_CDET_0_T_COUNT_MASK (0xffff << SEC_ENG_SE_CDET_0_T_COUNT_SHIFT)
+#define SEC_ENG_SE_CDET_0_G_COUNT_SHIFT (16U)
+#define SEC_ENG_SE_CDET_0_G_COUNT_MASK (0xffff << SEC_ENG_SE_CDET_0_G_COUNT_SHIFT)
+
+/* 0x4FC : se_cdet_0_ctrl_prot */
+#define SEC_ENG_SE_CDET_PROT_EN (1 << 0U)
+#define SEC_ENG_SE_CDET_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_CDET_ID1_EN (1 << 2U)
+
+/* 0x500 : se_gmac_0_ctrl_0 */
+#define SEC_ENG_SE_GMAC_0_BUSY (1 << 0U)
+#define SEC_ENG_SE_GMAC_0_TRIG_1T (1 << 1U)
+#define SEC_ENG_SE_GMAC_0_EN (1 << 2U)
+#define SEC_ENG_SE_GMAC_0_INT (1 << 8U)
+#define SEC_ENG_SE_GMAC_0_INT_CLR_1T (1 << 9U)
+#define SEC_ENG_SE_GMAC_0_INT_SET_1T (1 << 10U)
+#define SEC_ENG_SE_GMAC_0_INT_MASK (1 << 11U)
+#define SEC_ENG_SE_GMAC_0_T_ENDIAN (1 << 12U)
+#define SEC_ENG_SE_GMAC_0_H_ENDIAN (1 << 13U)
+#define SEC_ENG_SE_GMAC_0_X_ENDIAN (1 << 14U)
+
+/* 0x504 : se_gmac_0_lca */
+#define SEC_ENG_SE_GMAC_0_LCA_SHIFT (0U)
+#define SEC_ENG_SE_GMAC_0_LCA_MASK (0xffffffff << SEC_ENG_SE_GMAC_0_LCA_SHIFT)
+
+/* 0x508 : se_gmac_0_status */
+#define SEC_ENG_SE_GMAC_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_GMAC_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_GMAC_0_STATUS_SHIFT)
+
+/* 0x5FC : se_gmac_0_ctrl_prot */
+#define SEC_ENG_SE_GMAC_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_GMAC_ID1_EN (1 << 2U)
+
+/* 0xF00 : se_ctrl_prot_rd */
+#define SEC_ENG_SE_SHA_ID0_EN_RD (1 << 0U)
+#define SEC_ENG_SE_SHA_ID1_EN_RD (1 << 1U)
+#define SEC_ENG_SE_AES_ID0_EN_RD (1 << 2U)
+#define SEC_ENG_SE_AES_ID1_EN_RD (1 << 3U)
+#define SEC_ENG_SE_TRNG_ID0_EN_RD (1 << 4U)
+#define SEC_ENG_SE_TRNG_ID1_EN_RD (1 << 5U)
+#define SEC_ENG_SE_PKA_ID0_EN_RD (1 << 6U)
+#define SEC_ENG_SE_PKA_ID1_EN_RD (1 << 7U)
+#define SEC_ENG_SE_CDET_ID0_EN_RD (1 << 8U)
+#define SEC_ENG_SE_CDET_ID1_EN_RD (1 << 9U)
+#define SEC_ENG_SE_GMAC_ID0_EN_RD (1 << 10U)
+#define SEC_ENG_SE_GMAC_ID1_EN_RD (1 << 11U)
+#define SEC_ENG_SE_DBG_DIS (1 << 31U)
+
+/* 0xF04 : se_ctrl_reserved_0 */
+#define SEC_ENG_SE_CTRL_RESERVED_0_SHIFT (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_0_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_0_SHIFT)
+
+/* 0xF08 : se_ctrl_reserved_1 */
+#define SEC_ENG_SE_CTRL_RESERVED_1_SHIFT (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_1_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_1_SHIFT)
+
+/* 0xF0C : se_ctrl_reserved_2 */
+#define SEC_ENG_SE_CTRL_RESERVED_2_SHIFT (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_2_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_2_SHIFT)
+
+#endif /* __HARDWARE_SEC_ENG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sf_ctrl_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sf_ctrl_reg.h
new file mode 100644
index 00000000..2f1b5ee4
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/sf_ctrl_reg.h
@@ -0,0 +1,983 @@
+/**
+ ******************************************************************************
+ * @file sf_ctrl_reg.h
+ * @version V1.0
+ * @date 2022-10-20
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __SF_CTRL_REG_H__
+#define __SF_CTRL_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SF_CTRL_0_OFFSET (0x0)/* sf_ctrl_0 */
+#define SF_CTRL_1_OFFSET (0x4)/* sf_ctrl_1 */
+#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8)/* sf_if_sahb_0 */
+#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC)/* sf_if_sahb_1 */
+#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10)/* sf_if_sahb_2 */
+#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14)/* sf_if_iahb_0 */
+#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18)/* sf_if_iahb_1 */
+#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C)/* sf_if_iahb_2 */
+#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)/* sf_if_status_0 */
+#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)/* sf_if_status_1 */
+#define SF_CTRL_SF_AES_OFFSET (0x28)/* sf_aes */
+#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)/* sf_ahb2sif_status */
+#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30)/* sf_if_io_dly_0 */
+#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34)/* sf_if_io_dly_1 */
+#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38)/* sf_if_io_dly_2 */
+#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C)/* sf_if_io_dly_3 */
+#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40)/* sf_if_io_dly_4 */
+#define SF_CTRL_SF_RESERVED_OFFSET (0x44)/* sf_reserved */
+#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48)/* sf2_if_io_dly_0 */
+#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C)/* sf2_if_io_dly_1 */
+#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50)/* sf2_if_io_dly_2 */
+#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54)/* sf2_if_io_dly_3 */
+#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58)/* sf2_if_io_dly_4 */
+#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C)/* sf3_if_io_dly_0 */
+#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60)/* sf3_if_io_dly_1 */
+#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64)/* sf3_if_io_dly_2 */
+#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68)/* sf3_if_io_dly_3 */
+#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C)/* sf3_if_io_dly_4 */
+#define SF_CTRL_2_OFFSET (0x70)/* sf_ctrl_2 */
+#define SF_CTRL_3_OFFSET (0x74)/* sf_ctrl_3 */
+#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78)/* sf_if_iahb_3 */
+#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C)/* sf_if_iahb_4 */
+#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80)/* sf_if_iahb_5 */
+#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84)/* sf_if_iahb_6 */
+#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88)/* sf_if_iahb_7 */
+#define SF_CTRL_SF_IF_IAHB_8_OFFSET (0x8C)/* sf_if_iahb_8 */
+#define SF_CTRL_SF_IF_IAHB_9_OFFSET (0x90)/* sf_if_iahb_9 */
+#define SF_CTRL_SF_IF_IAHB_10_OFFSET (0x94)/* sf_if_iahb_10 */
+#define SF_CTRL_SF_IF_IAHB_11_OFFSET (0x98)/* sf_if_iahb_11 */
+#define SF_CTRL_SF_IF_IAHB_12_OFFSET (0x9C)/* sf_if_iahb_12 */
+#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0xA0)/* sf_id0_offset */
+#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0xA4)/* sf_id1_offset */
+#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0xA8)/* sf_bk2_id0_offset */
+#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0xAC)/* sf_bk2_id1_offset */
+#define SF_CTRL_SF_DBG_OFFSET (0xB0)/* sf_dbg */
+#define SF_CTRL_SF_IF2_CTRL_0_OFFSET (0xC0)/* sf_if2_ctrl_0 */
+#define SF_CTRL_SF_IF2_CTRL_1_OFFSET (0xC4)/* sf_if2_ctrl_1 */
+#define SF_CTRL_SF_IF2_SAHB_0_OFFSET (0xC8)/* sf_if2_sahb_0 */
+#define SF_CTRL_SF_IF2_SAHB_1_OFFSET (0xCC)/* sf_if2_sahb_1 */
+#define SF_CTRL_SF_IF2_SAHB_2_OFFSET (0xD0)/* sf_if2_sahb_2 */
+#define SF_CTRL_PROT_EN_RD_OFFSET (0x100)/* sf_ctrl_prot_en_rd */
+#define SF_CTRL_PROT_EN_OFFSET (0x104)/* sf_ctrl_prot_en */
+#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)/* sf_aes_key_r0_0 */
+#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)/* sf_aes_key_r0_1 */
+#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)/* sf_aes_key_r0_2 */
+#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)/* sf_aes_key_r0_3 */
+#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)/* sf_aes_key_r0_4 */
+#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)/* sf_aes_key_r0_5 */
+#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)/* sf_aes_key_r0_6 */
+#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)/* sf_aes_key_r0_7 */
+#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)/* sf_aes_iv_r0_w0 */
+#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)/* sf_aes_iv_r0_w1 */
+#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)/* sf_aes_iv_r0_w2 */
+#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)/* sf_aes_iv_r0_w3 */
+#define SF_CTRL_SF_AES_R0_START_OFFSET (0x230)/* sf_aes_r0_start */
+#define SF_CTRL_SF_AES_R0_END_OFFSET (0x234)/* sf_aes_r0_end */
+#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x280)/* sf_aes_key_r1_0 */
+#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x284)/* sf_aes_key_r1_1 */
+#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x288)/* sf_aes_key_r1_2 */
+#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x28C)/* sf_aes_key_r1_3 */
+#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x290)/* sf_aes_key_r1_4 */
+#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x294)/* sf_aes_key_r1_5 */
+#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x298)/* sf_aes_key_r1_6 */
+#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x29C)/* sf_aes_key_r1_7 */
+#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x2A0)/* sf_aes_iv_r1_w0 */
+#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x2A4)/* sf_aes_iv_r1_w1 */
+#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x2A8)/* sf_aes_iv_r1_w2 */
+#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x2AC)/* sf_aes_iv_r1_w3 */
+#define SF_CTRL_SF_AES_R1_START_OFFSET (0x2B0)/* sf_aes_r1_start */
+#define SF_CTRL_SF_AES_R1_END_OFFSET (0x2B4)/* sf_aes_r1_end */
+#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x300)/* sf_aes_key_r2_0 */
+#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x304)/* sf_aes_key_r2_1 */
+#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x308)/* sf_aes_key_r2_2 */
+#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x30C)/* sf_aes_key_r2_3 */
+#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x310)/* sf_aes_key_r2_4 */
+#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x314)/* sf_aes_key_r2_5 */
+#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x318)/* sf_aes_key_r2_6 */
+#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x31C)/* sf_aes_key_r2_7 */
+#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x320)/* sf_aes_iv_r2_w0 */
+#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x324)/* sf_aes_iv_r2_w1 */
+#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x328)/* sf_aes_iv_r2_w2 */
+#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x32C)/* sf_aes_iv_r2_w3 */
+#define SF_CTRL_SF_AES_R2_START_OFFSET (0x330)/* sf_aes_r2_start */
+#define SF_CTRL_SF_AES_R2_END_OFFSET (0x334)/* sf_aes_r2_end */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : sf_ctrl_0 */
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL (1<<2U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN (1<<3U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL (1<<4U)
+#define SF_CTRL_SF_IF_READ_DLY_N_SHIFT (8U)
+#define SF_CTRL_SF_IF_READ_DLY_N_MASK (0x7<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_SPI_H__
+#define __HARDWARE_SPI_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SPI_CONFIG_OFFSET (0x0) /* spi_config */
+#define SPI_INT_STS_OFFSET (0x4) /* spi_int_sts */
+#define SPI_BUS_BUSY_OFFSET (0x8) /* spi_bus_busy */
+#define SPI_PRD_0_OFFSET (0x10) /* spi_prd_0 */
+#define SPI_PRD_1_OFFSET (0x14) /* spi_prd_1 */
+#define SPI_RXD_IGNR_OFFSET (0x18) /* spi_rxd_ignr */
+#define SPI_STO_VALUE_OFFSET (0x1C) /* spi_sto_value */
+#define SPI_FIFO_CONFIG_0_OFFSET (0x80) /* spi_fifo_config_0 */
+#define SPI_FIFO_CONFIG_1_OFFSET (0x84) /* spi_fifo_config_1 */
+#define SPI_FIFO_WDATA_OFFSET (0x88) /* spi_fifo_wdata */
+#define SPI_FIFO_RDATA_OFFSET (0x8C) /* spi_fifo_rdata */
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_BACKUP_IO_EN_OFFSET (0xFC) /* backup_io_en */
+#endif
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : spi_config */
+#define SPI_CR_SPI_M_EN (1 << 0U)
+#define SPI_CR_SPI_S_EN (1 << 1U)
+#define SPI_CR_SPI_FRAME_SIZE_SHIFT (2U)
+#define SPI_CR_SPI_FRAME_SIZE_MASK (0x3 << SPI_CR_SPI_FRAME_SIZE_SHIFT)
+#define SPI_CR_SPI_SCLK_POL (1 << 4U)
+#define SPI_CR_SPI_SCLK_PH (1 << 5U)
+#define SPI_CR_SPI_BIT_INV (1 << 6U)
+#define SPI_CR_SPI_BYTE_INV (1 << 7U)
+#define SPI_CR_SPI_RXD_IGNR_EN (1 << 8U)
+#define SPI_CR_SPI_M_CONT_EN (1 << 9U)
+#define SPI_CR_SPI_S_3PIN_MODE (1 << 10U)
+#define SPI_CR_SPI_DEG_EN (1 << 11U)
+#define SPI_CR_SPI_DEG_CNT_SHIFT (12U)
+#define SPI_CR_SPI_DEG_CNT_MASK (0xf << SPI_CR_SPI_DEG_CNT_SHIFT)
+
+/* 0x4 : spi_int_sts */
+#define SPI_END_INT (1 << 0U)
+#define SPI_TXF_INT (1 << 1U)
+#define SPI_RXF_INT (1 << 2U)
+#define SPI_STO_INT (1 << 3U)
+#define SPI_TXU_INT (1 << 4U)
+#define SPI_FER_INT (1 << 5U)
+#define SPI_CR_SPI_END_MASK (1 << 8U)
+#define SPI_CR_SPI_TXF_MASK (1 << 9U)
+#define SPI_CR_SPI_RXF_MASK (1 << 10U)
+#define SPI_CR_SPI_STO_MASK (1 << 11U)
+#define SPI_CR_SPI_TXU_MASK (1 << 12U)
+#define SPI_CR_SPI_FER_MASK (1 << 13U)
+#define SPI_CR_SPI_END_CLR (1 << 16U)
+#define SPI_CR_SPI_STO_CLR (1 << 19U)
+#define SPI_CR_SPI_TXU_CLR (1 << 20U)
+#define SPI_CR_SPI_END_EN (1 << 24U)
+#define SPI_CR_SPI_TXF_EN (1 << 25U)
+#define SPI_CR_SPI_RXF_EN (1 << 26U)
+#define SPI_CR_SPI_STO_EN (1 << 27U)
+#define SPI_CR_SPI_TXU_EN (1 << 28U)
+#define SPI_CR_SPI_FER_EN (1 << 29U)
+
+/* 0x8 : spi_bus_busy */
+#define SPI_STS_SPI_BUS_BUSY (1 << 0U)
+
+/* 0x10 : spi_prd_0 */
+#define SPI_CR_SPI_PRD_S_SHIFT (0U)
+#define SPI_CR_SPI_PRD_S_MASK (0xff << SPI_CR_SPI_PRD_S_SHIFT)
+#define SPI_CR_SPI_PRD_P_SHIFT (8U)
+#define SPI_CR_SPI_PRD_P_MASK (0xff << SPI_CR_SPI_PRD_P_SHIFT)
+#define SPI_CR_SPI_PRD_D_PH_0_SHIFT (16U)
+#define SPI_CR_SPI_PRD_D_PH_0_MASK (0xff << SPI_CR_SPI_PRD_D_PH_0_SHIFT)
+#define SPI_CR_SPI_PRD_D_PH_1_SHIFT (24U)
+#define SPI_CR_SPI_PRD_D_PH_1_MASK (0xff << SPI_CR_SPI_PRD_D_PH_1_SHIFT)
+
+/* 0x14 : spi_prd_1 */
+#define SPI_CR_SPI_PRD_I_SHIFT (0U)
+#define SPI_CR_SPI_PRD_I_MASK (0xff << SPI_CR_SPI_PRD_I_SHIFT)
+
+/* 0x18 : spi_rxd_ignr */
+#define SPI_CR_SPI_RXD_IGNR_P_SHIFT (0U)
+#define SPI_CR_SPI_RXD_IGNR_P_MASK (0x1f << SPI_CR_SPI_RXD_IGNR_P_SHIFT)
+#define SPI_CR_SPI_RXD_IGNR_S_SHIFT (16U)
+#define SPI_CR_SPI_RXD_IGNR_S_MASK (0x1f << SPI_CR_SPI_RXD_IGNR_S_SHIFT)
+
+/* 0x1C : spi_sto_value */
+#define SPI_CR_SPI_STO_VALUE_SHIFT (0U)
+#define SPI_CR_SPI_STO_VALUE_MASK (0xfff << SPI_CR_SPI_STO_VALUE_SHIFT)
+
+/* 0x80 : spi_fifo_config_0 */
+#define SPI_DMA_TX_EN (1 << 0U)
+#define SPI_DMA_RX_EN (1 << 1U)
+#define SPI_TX_FIFO_CLR (1 << 2U)
+#define SPI_RX_FIFO_CLR (1 << 3U)
+#define SPI_TX_FIFO_OVERFLOW (1 << 4U)
+#define SPI_TX_FIFO_UNDERFLOW (1 << 5U)
+#define SPI_RX_FIFO_OVERFLOW (1 << 6U)
+#define SPI_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x84 : spi_fifo_config_1 */
+#define SPI_TX_FIFO_CNT_SHIFT (0U)
+#if defined(BL702) || defined(BL602)
+#define SPI_TX_FIFO_CNT_MASK (0x7 << SPI_TX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define SPI_TX_FIFO_CNT_MASK (0x1f << SPI_TX_FIFO_CNT_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_TX_FIFO_CNT_MASK (0x3f << SPI_TX_FIFO_CNT_SHIFT)
+#endif
+#define SPI_RX_FIFO_CNT_SHIFT (8U)
+#if defined(BL702) || defined(BL602)
+#define SPI_RX_FIFO_CNT_MASK (0x7 << SPI_RX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define SPI_RX_FIFO_CNT_MASK (0x1f << SPI_RX_FIFO_CNT_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_RX_FIFO_CNT_MASK (0x3f << SPI_RX_FIFO_CNT_SHIFT)
+#endif
+#define SPI_TX_FIFO_TH_SHIFT (16U)
+#if defined(BL702) || defined(BL602)
+#define SPI_TX_FIFO_TH_MASK (0x3 << SPI_TX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define SPI_TX_FIFO_TH_MASK (0xf << SPI_TX_FIFO_TH_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_TX_FIFO_TH_MASK (0x1f << SPI_TX_FIFO_TH_SHIFT)
+#endif
+#define SPI_RX_FIFO_TH_SHIFT (24U)
+#if defined(BL702) || defined(BL602)
+#define SPI_RX_FIFO_TH_MASK (0x3 << SPI_RX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define SPI_RX_FIFO_TH_MASK (0xf << SPI_RX_FIFO_TH_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_RX_FIFO_TH_MASK (0x1f << SPI_RX_FIFO_TH_SHIFT)
+#endif
+
+/* 0x88 : spi_fifo_wdata */
+#define SPI_FIFO_WDATA_SHIFT (0U)
+#define SPI_FIFO_WDATA_MASK (0xffffffff << SPI_FIFO_WDATA_SHIFT)
+
+/* 0x8C : spi_fifo_rdata */
+#define SPI_FIFO_RDATA_SHIFT (0U)
+#define SPI_FIFO_RDATA_MASK (0xffffffff << SPI_FIFO_RDATA_SHIFT)
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+/* 0xFC : backup_io_en */
+#define SPI_BACKUP_IO_EN (1 << 0U)
+#endif
+
+#endif /* __HARDWARE_SPI_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/timer_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/timer_reg.h
new file mode 100644
index 00000000..6af022d5
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/timer_reg.h
@@ -0,0 +1,285 @@
+/**
+ ******************************************************************************
+ * @file timer_reg.h
+ * @version V1.0
+ * @date 2022-08-03
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_TIMER_H__
+#define __HARDWARE_TIMER_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define TIMER_TCCR_OFFSET (0x0) /* Timer Clock Source */
+#define TIMER_TMR0_0_OFFSET (0x10) /* Timer0 Match Value 0 */
+#define TIMER_TMR0_1_OFFSET (0x14) /* Timer0 Match Value 1 */
+#define TIMER_TMR0_2_OFFSET (0x18) /* Timer0 Match Value 2 */
+#define TIMER_TMR1_0_OFFSET (0x1C) /* Timer1 Match Value 0 */
+#define TIMER_TMR1_1_OFFSET (0x20) /* Timer1 Match Value 1 */
+#define TIMER_TMR1_2_OFFSET (0x24) /* Timer1 Match Value 2 */
+#define TIMER_TCR0_OFFSET (0x2C) /* Timer0 Counter Value */
+#define TIMER_TCR1_OFFSET (0x30) /* Timer1 Counter Value */
+#define TIMER_TSR0_OFFSET (0x38) /* Timer0 Match Status */
+#define TIMER_TSR1_OFFSET (0x3C) /* Timer1 Match Status */
+#define TIMER_TIER0_OFFSET (0x44) /* Timer0 Match Interrupt Enable */
+#define TIMER_TIER1_OFFSET (0x48) /* Timer1 Match Interrupt Enable */
+#define TIMER_TPLVR0_OFFSET (0x50) /* Timer0 Pre-Load Value */
+#define TIMER_TPLVR1_OFFSET (0x54) /* Timer1 Pre-Load Value */
+#define TIMER_TPLCR0_OFFSET (0x5C) /* Timer0 Pre-Load Control */
+#define TIMER_TPLCR1_OFFSET (0x60) /* Timer1 Pre-Load Control */
+#define TIMER_WMER_OFFSET (0x64) /* Watch-dog reset/interrupt Mode */
+#define TIMER_WMR_OFFSET (0x68) /* Watch-dog Match Value */
+#define TIMER_WVR_OFFSET (0x6C) /* Watch-dog Counter Value */
+#define TIMER_WSR_OFFSET (0x70) /* Watch-dog Reset Status */
+#define TIMER_TICR0_OFFSET (0x78) /* Timer0 Interrupt Clear */
+#define TIMER_TICR1_OFFSET (0x7C) /* Timer1 Interrupt Clear */
+#define TIMER_WICR_OFFSET (0x80) /* WDT Interrupt Clear */
+#define TIMER_TCER_OFFSET (0x84) /* Timer Counter Enable/Clear */
+#define TIMER_TCMR_OFFSET (0x88) /* Timer Counter Mode */
+#define TIMER_TILR0_OFFSET (0x90) /* Timer0 Match Interrupt Mode */
+#define TIMER_TILR1_OFFSET (0x94) /* Timer1 Match Interrupt Mode */
+#define TIMER_WCR_OFFSET (0x98) /* WDT Counter Reset */
+#define TIMER_WFAR_OFFSET (0x9C) /* WDT Access Key1 */
+#define TIMER_WSAR_OFFSET (0xA0) /* WDT Access Key2 */
+#define TIMER_TCVWR0_OFFSET (0xA8) /* Timer0 Counter Latch Value */
+#define TIMER_TCVWR1_OFFSET (0xAC) /* Timer1 Counter Latch Value */
+#define TIMER_TCVSYN0_OFFSET (0xB4) /* Timer0 Counter Sync Value */
+#define TIMER_TCVSYN1_OFFSET (0xB8) /* Timer1 Counter Sync Value */
+#define TIMER_TCDR_OFFSET (0xBC) /* Timer Division */
+#if !defined(BL702) || !defined(BL602)
+#define TIMER_GPIO_OFFSET (0xC0) /* GPIO Mode */
+#define TIMER_GPIO_LAT1_OFFSET (0xC4) /* GPIO Latch Value1 */
+#define TIMER_GPIO_LAT2_OFFSET (0xC8) /* GPIO Latch Value2 */
+#define TIMER_TCDR_FORCE_OFFSET (0xCC) /* Timer Division Force */
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : Timer Clock Source */
+#if defined(BL702) || defined(BL602)
+#define TIMER_CS_0_SHIFT (2U)
+#define TIMER_CS_0_MASK (0x3 << TIMER_CS_0_SHIFT)
+#define TIMER_CS_1_SHIFT (5U)
+#define TIMER_CS_1_MASK (0x3 << TIMER_CS_1_SHIFT)
+#define TIMER_CS_WDT_SHIFT (8U)
+#define TIMER_CS_WDT_MASK (0x3 << TIMER_CS_WDT_SHIFT)
+#else
+#define TIMER_CS_0_SHIFT (0U)
+#define TIMER_CS_0_MASK (0xf << TIMER_CS_0_SHIFT)
+#define TIMER_CS_1_SHIFT (4U)
+#define TIMER_CS_1_MASK (0xf << TIMER_CS_1_SHIFT)
+#define TIMER_CS_WDT_SHIFT (8U)
+#define TIMER_CS_WDT_MASK (0xf << TIMER_CS_WDT_SHIFT)
+#define TIMER_ID_SHIFT (24U)
+#define TIMER_ID_MASK (0xff << TIMER_ID_SHIFT)
+#endif
+
+/* 0x10 : Timer0 Match Value 0 */
+#define TIMER_TMR0_0_SHIFT (0U)
+#define TIMER_TMR0_0_MASK (0xffffffff << TIMER_TMR0_0_SHIFT)
+
+/* 0x14 : Timer0 Match Value 1 */
+#define TIMER_TMR0_1_SHIFT (0U)
+#define TIMER_TMR0_1_MASK (0xffffffff << TIMER_TMR0_1_SHIFT)
+
+/* 0x18 : Timer0 Match Value 2 */
+#define TIMER_TMR0_2_SHIFT (0U)
+#define TIMER_TMR0_2_MASK (0xffffffff << TIMER_TMR0_2_SHIFT)
+
+/* 0x1C : Timer1 Match Value 0 */
+#define TIMER_TMR1_0_SHIFT (0U)
+#define TIMER_TMR1_0_MASK (0xffffffff << TIMER_TMR1_0_SHIFT)
+
+/* 0x20 : Timer1 Match Value 1 */
+#define TIMER_TMR1_1_SHIFT (0U)
+#define TIMER_TMR1_1_MASK (0xffffffff << TIMER_TMR1_1_SHIFT)
+
+/* 0x24 : Timer1 Match Value 2 */
+#define TIMER_TMR1_2_SHIFT (0U)
+#define TIMER_TMR1_2_MASK (0xffffffff << TIMER_TMR1_2_SHIFT)
+
+/* 0x2C : Timer0 Counter Value */
+#define TIMER_TCR0_CNT_SHIFT (0U)
+#define TIMER_TCR0_CNT_MASK (0xffffffff << TIMER_TCR0_CNT_SHIFT)
+
+/* 0x30 : Timer1 Counter Value */
+#define TIMER_TCR1_CNT_SHIFT (0U)
+#define TIMER_TCR1_CNT_MASK (0xffffffff << TIMER_TCR1_CNT_SHIFT)
+
+/* 0x38 : Timer0 Match Status */
+#define TIMER_TSR0_0 (1 << 0U)
+#define TIMER_TSR0_1 (1 << 1U)
+#define TIMER_TSR0_2 (1 << 2U)
+
+/* 0x3C : Timer1 Match Status */
+#define TIMER_TSR1_0 (1 << 0U)
+#define TIMER_TSR1_1 (1 << 1U)
+#define TIMER_TSR1_2 (1 << 2U)
+
+/* 0x44 : Timer0 Match Interrupt Enable */
+#define TIMER_TIER0_0 (1 << 0U)
+#define TIMER_TIER0_1 (1 << 1U)
+#define TIMER_TIER0_2 (1 << 2U)
+
+/* 0x48 : Timer1 Match Interrupt Enable */
+#define TIMER_TIER1_0 (1 << 0U)
+#define TIMER_TIER1_1 (1 << 1U)
+#define TIMER_TIER1_2 (1 << 2U)
+
+/* 0x50 : Timer0 Pre-Load Value */
+#define TIMER_TPLVR0_SHIFT (0U)
+#define TIMER_TPLVR0_MASK (0xffffffff << TIMER_TPLVR0_SHIFT)
+
+/* 0x54 : Timer1 Pre-Load Value */
+#define TIMER_TPLVR1_SHIFT (0U)
+#define TIMER_TPLVR1_MASK (0xffffffff << TIMER_TPLVR1_SHIFT)
+
+/* 0x5C : Timer0 Pre-Load Control */
+#define TIMER_TPLCR0_SHIFT (0U)
+#define TIMER_TPLCR0_MASK (0x3 << TIMER_TPLCR0_SHIFT)
+
+/* 0x60 : Timer1 Pre-Load Control */
+#define TIMER_TPLCR1_SHIFT (0U)
+#define TIMER_TPLCR1_MASK (0x3 << TIMER_TPLCR1_SHIFT)
+
+/* 0x64 : Watch-dog reset/interrupt Mode */
+#define TIMER_WE (1 << 0U)
+#define TIMER_WRIE (1 << 1U)
+
+/* 0x68 : Watch-dog Match Value */
+#define TIMER_WMR_SHIFT (0U)
+#define TIMER_WMR_MASK (0xffff << TIMER_WMR_SHIFT)
+#define TIMER_WDT_ALIGN (1 << 16U)
+
+/* 0x6C : Watch-dog Counter Value */
+#define TIMER_WDT_CNT_SHIFT (0U)
+#define TIMER_WDT_CNT_MASK (0xffff << TIMER_WDT_CNT_SHIFT)
+
+/* 0x70 : Watch-dog Reset Status */
+#define TIMER_WTS (1 << 0U)
+
+/* 0x78 : Timer0 Interrupt Clear */
+#define TIMER_TCLR0_0 (1 << 0U)
+#define TIMER_TCLR0_1 (1 << 1U)
+#define TIMER_TCLR0_2 (1 << 2U)
+
+/* 0x7C : Timer1 Interrupt Clear */
+#define TIMER_TCLR1_0 (1 << 0U)
+#define TIMER_TCLR1_1 (1 << 1U)
+#define TIMER_TCLR1_2 (1 << 2U)
+
+/* 0x80 : WDT Interrupt Clear */
+#define TIMER_WICLR (1 << 0U)
+
+/* 0x84 : Timer Counter Enable/Clear */
+#define TIMER0_EN (1 << 1U)
+#define TIMER1_EN (1 << 2U)
+#define TIMER_TCR0_CNT_CLR (1 << 5U)
+#define TIMER_TCR1_CNT_CLR (1 << 6U)
+
+/* 0x88 : Timer Counter Mode */
+#define TIMER0_MODE (1 << 1U)
+#define TIMER1_MODE (1 << 2U)
+#define TIMER0_ALIGN (1 << 5U)
+#define TIMER1_ALIGN (1 << 6U)
+
+/* 0x90 : Timer0 Match Interrupt Mode */
+#define TIMER_TILR0_0 (1 << 0U)
+#define TIMER_TILR0_1 (1 << 1U)
+#define TIMER_TILR0_2 (1 << 2U)
+
+/* 0x94 : Timer1 Match Interrupt Mode */
+#define TIMER_TILR1_0 (1 << 0U)
+#define TIMER_TILR1_1 (1 << 1U)
+#define TIMER_TILR1_2 (1 << 2U)
+
+/* 0x98 : WDT Counter Reset */
+#define TIMER_WCR (1 << 0U)
+
+/* 0x9C : WDT Access Key1 */
+#define TIMER_WFAR_SHIFT (0U)
+#define TIMER_WFAR_MASK (0xffff << TIMER_WFAR_SHIFT)
+
+/* 0xA0 : WDT Access Key2 */
+#define TIMER_WSAR_SHIFT (0U)
+#define TIMER_WSAR_MASK (0xffff << TIMER_WSAR_SHIFT)
+
+/* 0xA8 : Timer0 Counter Latch Value */
+#define TIMER_TCR0_CNT_LAT_SHIFT (0U)
+#define TIMER_TCR0_CNT_LAT_MASK (0xffffffff << TIMER_TCR0_CNT_LAT_SHIFT)
+
+/* 0xAC : Timer1 Counter Latch Value */
+#define TIMER_TCR1_CNT_LAT_SHIFT (0U)
+#define TIMER_TCR1_CNT_LAT_MASK (0xffffffff << TIMER_TCR1_CNT_LAT_SHIFT)
+
+/* 0xB4 : Timer0 Counter Sync Value */
+#define TIMER_TCR0_CNT_SYNC_SHIFT (0U)
+#define TIMER_TCR0_CNT_SYNC_MASK (0xffffffff << TIMER_TCR0_CNT_SYNC_SHIFT)
+
+/* 0xB8 : Timer1 Counter Sync Value */
+#define TIMER_TCR1_CNT_SYNC_SHIFT (0U)
+#define TIMER_TCR1_CNT_SYNC_MASK (0xffffffff << TIMER_TCR1_CNT_SYNC_SHIFT)
+
+/* 0xBC : Timer Division */
+#define TIMER_TCDR0_SHIFT (8U)
+#define TIMER_TCDR0_MASK (0xff << TIMER_TCDR0_SHIFT)
+#define TIMER_TCDR1_SHIFT (16U)
+#define TIMER_TCDR1_MASK (0xff << TIMER_TCDR1_SHIFT)
+#define TIMER_WCDR_SHIFT (24U)
+#define TIMER_WCDR_MASK (0xff << TIMER_WCDR_SHIFT)
+
+#if !defined(BL702) || !defined(BL602)
+/* 0xC0 : GPIO Mode */
+#define TIMER0_GPIO_EN (1 << 1U)
+#define TIMER0_GPIO_INV (1 << 5U)
+#define TIMER1_GPIO_INV (1 << 6U)
+#define TIMER_WDT_GPIO_INV (1 << 7U)
+#define TIMER_GPIO_LAT_OK (1 << 31U)
+
+/* 0xC4 : GPIO Latch Value1 */
+#define TIMER_GPIO_LAT1_SHIFT (0U)
+#define TIMER_GPIO_LAT1_MASK (0xffffffff << TIMER_GPIO_LAT1_SHIFT)
+
+/* 0xC8 : GPIO Latch Value2 */
+#define TIMER_GPIO_LAT2_SHIFT (0U)
+#define TIMER_GPIO_LAT2_MASK (0xffffffff << TIMER_GPIO_LAT2_SHIFT)
+
+/* 0xCC : Timer Division Force */
+#define TIMER_TCDR0_FORCE (1 << 1U)
+#define TIMER_TCDR1_FORCE (1 << 2U)
+#define TIMER_WCDR_FORCE (1 << 4U)
+#endif
+
+#endif /* __HARDWARE_TIMER_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/uart_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/uart_reg.h
new file mode 100644
index 00000000..39e2f9ec
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/uart_reg.h
@@ -0,0 +1,370 @@
+/**
+ ******************************************************************************
+ * @file uart_reg.h
+ * @version V1.0
+ * @date 2022-06-10
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_UART_H__
+#define __HARDWARE_UART_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define UART_UTX_CONFIG_OFFSET (0x0) /* utx_config */
+#define UART_URX_CONFIG_OFFSET (0x4) /* urx_config */
+#define UART_BIT_PRD_OFFSET (0x8) /* uart_bit_prd */
+#define UART_DATA_CONFIG_OFFSET (0xC) /* data_config */
+#if !defined(BL702L)
+#define UART_UTX_IR_POSITION_OFFSET (0x10) /* utx_ir_position */
+#define UART_URX_IR_POSITION_OFFSET (0x14) /* urx_ir_position */
+#endif
+#define UART_URX_RTO_TIMER_OFFSET (0x18) /* urx_rto_timer */
+#if !defined(BL602)
+#define UART_SW_MODE_OFFSET (0x1C) /* uart_sw_mode */
+#endif
+#define UART_INT_STS_OFFSET (0x20) /* UART interrupt status */
+#define UART_INT_MASK_OFFSET (0x24) /* UART interrupt mask */
+#define UART_INT_CLEAR_OFFSET (0x28) /* UART interrupt clear */
+#define UART_INT_EN_OFFSET (0x2C) /* UART interrupt enable */
+#define UART_STATUS_OFFSET (0x30) /* uart_status */
+#define UART_STS_URX_ABR_PRD_OFFSET (0x34) /* sts_urx_abr_prd */
+#if !defined(BL602) && !defined(BL702)
+#define UART_URX_ABR_PRD_B01_OFFSET (0x38) /* urx_abr_prd_b01 */
+#define UART_URX_ABR_PRD_B23_OFFSET (0x3C) /* urx_abr_prd_b23 */
+#define UART_URX_ABR_PRD_B45_OFFSET (0x40) /* urx_abr_prd_b45 */
+#define UART_URX_ABR_PRD_B67_OFFSET (0x44) /* urx_abr_prd_b67 */
+#define UART_URX_ABR_PW_TOL_OFFSET (0x48) /* urx_abr_pw_tol */
+#define UART_URX_BCR_INT_CFG_OFFSET (0x50) /* urx_bcr_int_cfg */
+#define UART_UTX_RS485_CFG_OFFSET (0x54) /* utx_rs485_cfg */
+#endif
+#define UART_FIFO_CONFIG_0_OFFSET (0x80) /* uart_fifo_config_0 */
+#define UART_FIFO_CONFIG_1_OFFSET (0x84) /* uart_fifo_config_1 */
+#define UART_FIFO_WDATA_OFFSET (0x88) /* uart_fifo_wdata */
+#define UART_FIFO_RDATA_OFFSET (0x8C) /* uart_fifo_rdata */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : utx_config */
+#define UART_CR_UTX_EN (1 << 0U)
+#define UART_CR_UTX_CTS_EN (1 << 1U)
+#define UART_CR_UTX_FRM_EN (1 << 2U)
+#if !defined(BL602)
+#define UART_CR_UTX_LIN_EN (1 << 3U)
+#endif
+#define UART_CR_UTX_PRT_EN (1 << 4U)
+#define UART_CR_UTX_PRT_SEL (1 << 5U)
+#if !defined(BL702L)
+#define UART_CR_UTX_IR_EN (1 << 6U)
+#define UART_CR_UTX_IR_INV (1 << 7U)
+#endif
+#define UART_CR_UTX_BIT_CNT_D_SHIFT (8U)
+#define UART_CR_UTX_BIT_CNT_D_MASK (0x7 << UART_CR_UTX_BIT_CNT_D_SHIFT)
+#if defined(BL602)
+#define UART_CR_UTX_BIT_CNT_P_SHIFT (12U)
+#else
+#define UART_CR_UTX_BIT_CNT_P_SHIFT (11U)
+#endif
+#define UART_CR_UTX_BIT_CNT_P_MASK (0x3 << UART_CR_UTX_BIT_CNT_P_SHIFT)
+#if !defined(BL602)
+#define UART_CR_UTX_BIT_CNT_B_SHIFT (13U)
+#define UART_CR_UTX_BIT_CNT_B_MASK (0x7 << UART_CR_UTX_BIT_CNT_B_SHIFT)
+#endif
+#define UART_CR_UTX_LEN_SHIFT (16U)
+#define UART_CR_UTX_LEN_MASK (0xffff << UART_CR_UTX_LEN_SHIFT)
+
+/* 0x4 : urx_config */
+#define UART_CR_URX_EN (1 << 0U)
+#if defined(BL602)
+#define UART_CR_URX_RTS_SW_MODE (1 << 1U)
+#define UART_CR_URX_RTS_SW_VAL (1 << 2U)
+#define UART_CR_URX_ABR_EN (1 << 3U)
+#else
+#define UART_CR_URX_ABR_EN (1 << 1U)
+#define UART_CR_URX_LIN_EN (1 << 3U)
+#endif
+#define UART_CR_URX_PRT_EN (1 << 4U)
+#define UART_CR_URX_PRT_SEL (1 << 5U)
+#if !defined(BL702L)
+#define UART_CR_URX_IR_EN (1 << 6U)
+#define UART_CR_URX_IR_INV (1 << 7U)
+#endif
+#define UART_CR_URX_BIT_CNT_D_SHIFT (8U)
+#define UART_CR_URX_BIT_CNT_D_MASK (0x7 << UART_CR_URX_BIT_CNT_D_SHIFT)
+#define UART_CR_URX_DEG_EN (1 << 11U)
+#define UART_CR_URX_DEG_CNT_SHIFT (12U)
+#define UART_CR_URX_DEG_CNT_MASK (0xf << UART_CR_URX_DEG_CNT_SHIFT)
+#define UART_CR_URX_LEN_SHIFT (16U)
+#define UART_CR_URX_LEN_MASK (0xffff << UART_CR_URX_LEN_SHIFT)
+
+/* 0x8 : uart_bit_prd */
+#define UART_CR_UTX_BIT_PRD_SHIFT (0U)
+#define UART_CR_UTX_BIT_PRD_MASK (0xffff << UART_CR_UTX_BIT_PRD_SHIFT)
+#define UART_CR_URX_BIT_PRD_SHIFT (16U)
+#define UART_CR_URX_BIT_PRD_MASK (0xffff << UART_CR_URX_BIT_PRD_SHIFT)
+
+/* 0xC : data_config */
+#define UART_CR_UART_BIT_INV (1 << 0U)
+
+#if !defined(BL702L)
+/* 0x10 : utx_ir_position */
+#define UART_CR_UTX_IR_POS_S_SHIFT (0U)
+#define UART_CR_UTX_IR_POS_S_MASK (0xffff << UART_CR_UTX_IR_POS_S_SHIFT)
+#define UART_CR_UTX_IR_POS_P_SHIFT (16U)
+#define UART_CR_UTX_IR_POS_P_MASK (0xffff << UART_CR_UTX_IR_POS_P_SHIFT)
+
+/* 0x14 : urx_ir_position */
+#define UART_CR_URX_IR_POS_S_SHIFT (0U)
+#define UART_CR_URX_IR_POS_S_MASK (0xffff << UART_CR_URX_IR_POS_S_SHIFT)
+#endif
+
+/* 0x18 : urx_rto_timer */
+#define UART_CR_URX_RTO_VALUE_SHIFT (0U)
+#define UART_CR_URX_RTO_VALUE_MASK (0xff << UART_CR_URX_RTO_VALUE_SHIFT)
+
+#if !defined(BL602)
+/* 0x1C : uart_sw_mode */
+#define UART_CR_UTX_TXD_SW_MODE (1 << 0U)
+#define UART_CR_UTX_TXD_SW_VAL (1 << 1U)
+#define UART_CR_URX_RTS_SW_MODE (1 << 2U)
+#define UART_CR_URX_RTS_SW_VAL (1 << 3U)
+#endif
+
+/* 0x20 : UART interrupt status */
+#define UART_UTX_END_INT (1 << 0U)
+#define UART_URX_END_INT (1 << 1U)
+#define UART_UTX_FIFO_INT (1 << 2U)
+#define UART_URX_FIFO_INT (1 << 3U)
+#define UART_URX_RTO_INT (1 << 4U)
+#define UART_URX_PCE_INT (1 << 5U)
+#define UART_UTX_FER_INT (1 << 6U)
+#define UART_URX_FER_INT (1 << 7U)
+#if !defined(BL602)
+#define UART_URX_LSE_INT (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_URX_BCR_INT (1 << 9U)
+#define UART_URX_ADS_INT (1 << 10U)
+#define UART_URX_AD5_INT (1 << 11U)
+#endif
+
+/* 0x24 : UART interrupt mask */
+#define UART_CR_UTX_END_MASK (1 << 0U)
+#define UART_CR_URX_END_MASK (1 << 1U)
+#define UART_CR_UTX_FIFO_MASK (1 << 2U)
+#define UART_CR_URX_FIFO_MASK (1 << 3U)
+#define UART_CR_URX_RTO_MASK (1 << 4U)
+#define UART_CR_URX_PCE_MASK (1 << 5U)
+#define UART_CR_UTX_FER_MASK (1 << 6U)
+#define UART_CR_URX_FER_MASK (1 << 7U)
+#if !defined(BL602)
+#define UART_CR_URX_LSE_MASK (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_CR_URX_BCR_MASK (1 << 9U)
+#define UART_CR_URX_ADS_MASK (1 << 10U)
+#define UART_CR_URX_AD5_MASK (1 << 11U)
+#endif
+
+/* 0x28 : UART interrupt clear */
+#define UART_CR_UTX_END_CLR (1 << 0U)
+#define UART_CR_URX_END_CLR (1 << 1U)
+#define UART_CR_URX_RTO_CLR (1 << 4U)
+#define UART_CR_URX_PCE_CLR (1 << 5U)
+#if !defined(BL602)
+#define UART_CR_URX_LSE_CLR (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_CR_URX_BCR_CLR (1 << 9U)
+#define UART_CR_URX_ADS_CLR (1 << 10U)
+#define UART_CR_URX_AD5_CLR (1 << 11U)
+#endif
+
+/* 0x2C : UART interrupt enable */
+#define UART_CR_UTX_END_EN (1 << 0U)
+#define UART_CR_URX_END_EN (1 << 1U)
+#define UART_CR_UTX_FIFO_EN (1 << 2U)
+#define UART_CR_URX_FIFO_EN (1 << 3U)
+#define UART_CR_URX_RTO_EN (1 << 4U)
+#define UART_CR_URX_PCE_EN (1 << 5U)
+#define UART_CR_UTX_FER_EN (1 << 6U)
+#define UART_CR_URX_FER_EN (1 << 7U)
+#if !defined(BL602)
+#define UART_CR_URX_LSE_EN (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_CR_URX_BCR_EN (1 << 9U)
+#define UART_CR_URX_ADS_EN (1 << 10U)
+#define UART_CR_URX_AD5_EN (1 << 11U)
+#endif
+
+/* 0x30 : uart_status */
+#define UART_STS_UTX_BUS_BUSY (1 << 0U)
+#define UART_STS_URX_BUS_BUSY (1 << 1U)
+
+/* 0x34 : sts_urx_abr_prd */
+#define UART_STS_URX_ABR_PRD_START_SHIFT (0U)
+#define UART_STS_URX_ABR_PRD_START_MASK (0xffff << UART_STS_URX_ABR_PRD_START_SHIFT)
+#define UART_STS_URX_ABR_PRD_0X55_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_0X55_MASK (0x3ff << UART_STS_URX_ABR_PRD_0X55_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_0X55_MASK (0xffff << UART_STS_URX_ABR_PRD_0X55_SHIFT)
+#endif
+
+#if !defined(BL602) && !defined(BL702)
+/* 0x38 : urx_abr_prd_b01 */
+#define UART_STS_URX_ABR_PRD_BIT0_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT0_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT0_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT0_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT0_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT1_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT1_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT1_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT1_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT1_SHIFT)
+#endif
+
+/* 0x3C : urx_abr_prd_b23 */
+#define UART_STS_URX_ABR_PRD_BIT2_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT2_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT2_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT2_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT2_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT3_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT3_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT3_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT3_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT3_SHIFT)
+#endif
+
+/* 0x40 : urx_abr_prd_b45 */
+#define UART_STS_URX_ABR_PRD_BIT4_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT4_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT4_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT4_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT4_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT5_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT5_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT5_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT5_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT5_SHIFT)
+#endif
+
+/* 0x44 : urx_abr_prd_b67 */
+#define UART_STS_URX_ABR_PRD_BIT6_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT6_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT6_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT6_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT6_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT7_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT7_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT7_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT7_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT7_SHIFT)
+#endif
+
+/* 0x48 : urx_abr_pw_tol */
+#define UART_CR_URX_ABR_PW_TOL_SHIFT (0U)
+#define UART_CR_URX_ABR_PW_TOL_MASK (0xff << UART_CR_URX_ABR_PW_TOL_SHIFT)
+
+/* 0x50 : urx_bcr_int_cfg */
+#define UART_CR_URX_BCR_VALUE_SHIFT (0U)
+#define UART_CR_URX_BCR_VALUE_MASK (0xffff << UART_CR_URX_BCR_VALUE_SHIFT)
+#define UART_STS_URX_BCR_COUNT_SHIFT (16U)
+#define UART_STS_URX_BCR_COUNT_MASK (0xffff << UART_STS_URX_BCR_COUNT_SHIFT)
+
+/* 0x54 : utx_rs485_cfg */
+#define UART_CR_UTX_RS485_EN (1 << 0U)
+#define UART_CR_UTX_RS485_POL (1 << 1U)
+#endif
+
+/* 0x80 : uart_fifo_config_0 */
+#define UART_DMA_TX_EN (1 << 0U)
+#define UART_DMA_RX_EN (1 << 1U)
+#define UART_TX_FIFO_CLR (1 << 2U)
+#define UART_RX_FIFO_CLR (1 << 3U)
+#define UART_TX_FIFO_OVERFLOW (1 << 4U)
+#define UART_TX_FIFO_UNDERFLOW (1 << 5U)
+#define UART_RX_FIFO_OVERFLOW (1 << 6U)
+#define UART_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x84 : uart_fifo_config_1 */
+#define UART_TX_FIFO_CNT_SHIFT (0U)
+#if defined(BL702)
+#define UART_TX_FIFO_CNT_MASK (0xff << UART_TX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define UART_TX_FIFO_CNT_MASK (0x1f << UART_TX_FIFO_CNT_SHIFT)
+#else
+#define UART_TX_FIFO_CNT_MASK (0x3f << UART_TX_FIFO_CNT_SHIFT)
+#endif
+#define UART_RX_FIFO_CNT_SHIFT (8U)
+#if defined(BL702)
+#define UART_RX_FIFO_CNT_MASK (0xff << UART_RX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define UART_RX_FIFO_CNT_MASK (0x1f << UART_RX_FIFO_CNT_SHIFT)
+#else
+#define UART_RX_FIFO_CNT_MASK (0x3f << UART_RX_FIFO_CNT_SHIFT)
+#endif
+#define UART_TX_FIFO_TH_SHIFT (16U)
+#if defined(BL702)
+#define UART_TX_FIFO_TH_MASK (0x7f << UART_TX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define UART_TX_FIFO_TH_MASK (0xf << UART_TX_FIFO_TH_SHIFT)
+#else
+#define UART_TX_FIFO_TH_MASK (0x1f << UART_TX_FIFO_TH_SHIFT)
+#endif
+#define UART_RX_FIFO_TH_SHIFT (24U)
+#if defined(BL702)
+#define UART_RX_FIFO_TH_MASK (0x7f << UART_RX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define UART_RX_FIFO_TH_MASK (0xf << UART_RX_FIFO_TH_SHIFT)
+#else
+#define UART_RX_FIFO_TH_MASK (0x1f << UART_RX_FIFO_TH_SHIFT)
+#endif
+
+/* 0x88 : uart_fifo_wdata */
+#define UART_FIFO_WDATA_SHIFT (0U)
+#define UART_FIFO_WDATA_MASK (0xff << UART_FIFO_WDATA_SHIFT)
+
+/* 0x8C : uart_fifo_rdata */
+#define UART_FIFO_RDATA_SHIFT (0U)
+#define UART_FIFO_RDATA_MASK (0xff << UART_FIFO_RDATA_SHIFT)
+
+#endif /* __HARDWARE_UART_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/usb_v1_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/usb_v1_reg.h
new file mode 100644
index 00000000..57cc404e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/usb_v1_reg.h
@@ -0,0 +1,618 @@
+/**
+ ******************************************************************************
+ * @file usb_v1_reg.h
+ * @version V1.0
+ * @date 2022-08-15
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_USB_V1_H__
+#define __HARDWARE_USB_V1_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define USB_CONFIG_OFFSET (0x0) /* usb_config */
+#define USB_LPM_CONFIG_OFFSET (0x4) /* usb_lpm_config */
+#define USB_RESUME_CONFIG_OFFSET (0x8) /* usb_resume_config */
+#define USB_SETUP_DATA_0_OFFSET (0x10) /* usb_setup_data_0 */
+#define USB_SETUP_DATA_1_OFFSET (0x14) /* usb_setup_data_1 */
+#define USB_FRAME_NO_OFFSET (0x18) /* usb_frame_no */
+#define USB_ERROR_OFFSET (0x1C) /* usb_error */
+#define USB_INT_EN_OFFSET (0x20) /* USB interrupt enable */
+#define USB_INT_STS_OFFSET (0x24) /* USB interrupt status */
+#define USB_INT_MASK_OFFSET (0x28) /* USB interrupt mask */
+#define USB_INT_CLEAR_OFFSET (0x2C) /* USB interrupt clear */
+#define USB_EP1_CONFIG_OFFSET (0x40) /* ep1_config */
+#define USB_EP2_CONFIG_OFFSET (0x44) /* ep2_config */
+#define USB_EP3_CONFIG_OFFSET (0x48) /* ep3_config */
+#define USB_EP4_CONFIG_OFFSET (0x4C) /* ep4_config */
+#define USB_EP5_CONFIG_OFFSET (0x50) /* ep5_config */
+#define USB_EP6_CONFIG_OFFSET (0x54) /* ep6_config */
+#define USB_EP7_CONFIG_OFFSET (0x58) /* ep7_config */
+#define USB_EP0_FIFO_CONFIG_OFFSET (0x100) /* ep0_fifo_config */
+#define USB_EP0_FIFO_STATUS_OFFSET (0x104) /* ep0_fifo_status */
+#define USB_EP0_TX_FIFO_WDATA_OFFSET (0x108) /* ep0_tx_fifo_wdata */
+#define USB_EP0_RX_FIFO_RDATA_OFFSET (0x10C) /* ep0_rx_fifo_rdata */
+#define USB_EP1_FIFO_CONFIG_OFFSET (0x110) /* ep1_fifo_config */
+#define USB_EP1_FIFO_STATUS_OFFSET (0x114) /* ep1_fifo_status */
+#define USB_EP1_TX_FIFO_WDATA_OFFSET (0x118) /* ep1_tx_fifo_wdata */
+#define USB_EP1_RX_FIFO_RDATA_OFFSET (0x11C) /* ep1_rx_fifo_rdata */
+#define USB_EP2_FIFO_CONFIG_OFFSET (0x120) /* ep2_fifo_config */
+#define USB_EP2_FIFO_STATUS_OFFSET (0x124) /* ep2_fifo_status */
+#define USB_EP2_TX_FIFO_WDATA_OFFSET (0x128) /* ep2_tx_fifo_wdata */
+#define USB_EP2_RX_FIFO_RDATA_OFFSET (0x12C) /* ep2_rx_fifo_rdata */
+#define USB_EP3_FIFO_CONFIG_OFFSET (0x130) /* ep3_fifo_config */
+#define USB_EP3_FIFO_STATUS_OFFSET (0x134) /* ep3_fifo_status */
+#define USB_EP3_TX_FIFO_WDATA_OFFSET (0x138) /* ep3_tx_fifo_wdata */
+#define USB_EP3_RX_FIFO_RDATA_OFFSET (0x13C) /* ep3_rx_fifo_rdata */
+#define USB_EP4_FIFO_CONFIG_OFFSET (0x140) /* ep4_fifo_config */
+#define USB_EP4_FIFO_STATUS_OFFSET (0x144) /* ep4_fifo_status */
+#define USB_EP4_TX_FIFO_WDATA_OFFSET (0x148) /* ep4_tx_fifo_wdata */
+#define USB_EP4_RX_FIFO_RDATA_OFFSET (0x14C) /* ep4_rx_fifo_rdata */
+#define USB_EP5_FIFO_CONFIG_OFFSET (0x150) /* ep5_fifo_config */
+#define USB_EP5_FIFO_STATUS_OFFSET (0x154) /* ep5_fifo_status */
+#define USB_EP5_TX_FIFO_WDATA_OFFSET (0x158) /* ep5_tx_fifo_wdata */
+#define USB_EP5_RX_FIFO_RDATA_OFFSET (0x15C) /* ep5_rx_fifo_rdata */
+#define USB_EP6_FIFO_CONFIG_OFFSET (0x160) /* ep6_fifo_config */
+#define USB_EP6_FIFO_STATUS_OFFSET (0x164) /* ep6_fifo_status */
+#define USB_EP6_TX_FIFO_WDATA_OFFSET (0x168) /* ep6_tx_fifo_wdata */
+#define USB_EP6_RX_FIFO_RDATA_OFFSET (0x16C) /* ep6_rx_fifo_rdata */
+#define USB_EP7_FIFO_CONFIG_OFFSET (0x170) /* ep7_fifo_config */
+#define USB_EP7_FIFO_STATUS_OFFSET (0x174) /* ep7_fifo_status */
+#define USB_EP7_TX_FIFO_WDATA_OFFSET (0x178) /* ep7_tx_fifo_wdata */
+#define USB_EP7_RX_FIFO_RDATA_OFFSET (0x17C) /* ep7_rx_fifo_rdata */
+#define USB_RSVD_0_OFFSET (0x1F0) /* rsvd_0 */
+#define USB_RSVD_1_OFFSET (0x1F4) /* rsvd_1 */
+#define USB_XCVR_IF_CONFIG_OFFSET (0x1FC) /* xcvr_if_config */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : usb_config */
+#define USB_CR_USB_EN (1 << 0U)
+#define USB_CR_USB_ROM_DCT_EN (1 << 4U)
+#define USB_CR_USB_EP0_SW_CTRL (1 << 8U)
+#define USB_CR_USB_EP0_SW_ADDR_SHIFT (9U)
+#define USB_CR_USB_EP0_SW_ADDR_MASK (0x7f << USB_CR_USB_EP0_SW_ADDR_SHIFT)
+#define USB_CR_USB_EP0_SW_SIZE_SHIFT (16U)
+#define USB_CR_USB_EP0_SW_SIZE_MASK (0xff << USB_CR_USB_EP0_SW_SIZE_SHIFT)
+#define USB_CR_USB_EP0_SW_STALL (1 << 24U)
+#define USB_CR_USB_EP0_SW_NACK_IN (1 << 25U)
+#define USB_CR_USB_EP0_SW_NACK_OUT (1 << 26U)
+#define USB_CR_USB_EP0_SW_RDY (1 << 27U)
+#define USB_STS_USB_EP0_SW_RDY (1 << 28U)
+
+/* 0x4 : usb_lpm_config */
+#define USB_CR_LPM_EN (1 << 0U)
+#define USB_CR_LPM_RESP_UPD (1 << 1U)
+#define USB_CR_LPM_RESP_SHIFT (2U)
+#define USB_CR_LPM_RESP_MASK (0x3 << USB_CR_LPM_RESP_SHIFT)
+#define USB_STS_LPM_ATTR_SHIFT (20U)
+#define USB_STS_LPM_ATTR_MASK (0x7ff << USB_STS_LPM_ATTR_SHIFT)
+#define USB_STS_LPM (1 << 31U)
+
+/* 0x8 : usb_resume_config */
+#define USB_CR_RES_WIDTH_SHIFT (0U)
+#define USB_CR_RES_WIDTH_MASK (0x7ff << USB_CR_RES_WIDTH_SHIFT)
+#define USB_CR_RES_TRIG (1 << 12U)
+#define USB_CR_RES_FORCE (1 << 31U)
+
+/* 0x10 : usb_setup_data_0 */
+#define USB_STS_SETUP_DATA_B0_SHIFT (0U)
+#define USB_STS_SETUP_DATA_B0_MASK (0xff << USB_STS_SETUP_DATA_B0_SHIFT)
+#define USB_STS_SETUP_DATA_B1_SHIFT (8U)
+#define USB_STS_SETUP_DATA_B1_MASK (0xff << USB_STS_SETUP_DATA_B1_SHIFT)
+#define USB_STS_SETUP_DATA_B2_SHIFT (16U)
+#define USB_STS_SETUP_DATA_B2_MASK (0xff << USB_STS_SETUP_DATA_B2_SHIFT)
+#define USB_STS_SETUP_DATA_B3_SHIFT (24U)
+#define USB_STS_SETUP_DATA_B3_MASK (0xff << USB_STS_SETUP_DATA_B3_SHIFT)
+
+/* 0x14 : usb_setup_data_1 */
+#define USB_STS_SETUP_DATA_B4_SHIFT (0U)
+#define USB_STS_SETUP_DATA_B4_MASK (0xff << USB_STS_SETUP_DATA_B4_SHIFT)
+#define USB_STS_SETUP_DATA_B5_SHIFT (8U)
+#define USB_STS_SETUP_DATA_B5_MASK (0xff << USB_STS_SETUP_DATA_B5_SHIFT)
+#define USB_STS_SETUP_DATA_B6_SHIFT (16U)
+#define USB_STS_SETUP_DATA_B6_MASK (0xff << USB_STS_SETUP_DATA_B6_SHIFT)
+#define USB_STS_SETUP_DATA_B7_SHIFT (24U)
+#define USB_STS_SETUP_DATA_B7_MASK (0xff << USB_STS_SETUP_DATA_B7_SHIFT)
+
+/* 0x18 : usb_frame_no */
+#define USB_STS_FRAME_NO_SHIFT (0U)
+#define USB_STS_FRAME_NO_MASK (0x7ff << USB_STS_FRAME_NO_SHIFT)
+#define USB_STS_PID_SHIFT (12U)
+#define USB_STS_PID_MASK (0xf << USB_STS_PID_SHIFT)
+#define USB_STS_EP_NO_SHIFT (16U)
+#define USB_STS_EP_NO_MASK (0xf << USB_STS_EP_NO_SHIFT)
+
+/* 0x1C : usb_error */
+#define USB_UTMI_RX_ERR (1 << 0U)
+#define USB_XFER_TO_ERR (1 << 1U)
+#define USB_IVLD_EP_ERR (1 << 2U)
+#define USB_PID_SEQ_ERR (1 << 3U)
+#define USB_PID_CKS_ERR (1 << 4U)
+#define USB_CRC5_ERR (1 << 5U)
+#define USB_CRC16_ERR (1 << 6U)
+
+/* 0x20 : USB interrupt enable */
+#define USB_CR_SOF_EN (1 << 0U)
+#define USB_CR_USB_RESET_EN (1 << 1U)
+#define USB_CR_VBUS_TGL_EN (1 << 2U)
+#define USB_CR_GET_DCT_CMD_EN (1 << 3U)
+#define USB_CR_EP0_SETUP_CMD_EN (1 << 4U)
+#define USB_CR_EP0_SETUP_DONE_EN (1 << 5U)
+#define USB_CR_EP0_IN_CMD_EN (1 << 6U)
+#define USB_CR_EP0_IN_DONE_EN (1 << 7U)
+#define USB_CR_EP0_OUT_CMD_EN (1 << 8U)
+#define USB_CR_EP0_OUT_DONE_EN (1 << 9U)
+#define USB_CR_EP1_CMD_EN (1 << 10U)
+#define USB_CR_EP1_DONE_EN (1 << 11U)
+#define USB_CR_EP2_CMD_EN (1 << 12U)
+#define USB_CR_EP2_DONE_EN (1 << 13U)
+#define USB_CR_EP3_CMD_EN (1 << 14U)
+#define USB_CR_EP3_DONE_EN (1 << 15U)
+#define USB_CR_EP4_CMD_EN (1 << 16U)
+#define USB_CR_EP4_DONE_EN (1 << 17U)
+#define USB_CR_EP5_CMD_EN (1 << 18U)
+#define USB_CR_EP5_DONE_EN (1 << 19U)
+#define USB_CR_EP6_CMD_EN (1 << 20U)
+#define USB_CR_EP6_DONE_EN (1 << 21U)
+#define USB_CR_EP7_CMD_EN (1 << 22U)
+#define USB_CR_EP7_DONE_EN (1 << 23U)
+#define USB_CR_USB_REND_EN (1 << 27U)
+#define USB_CR_LPM_WKUP_EN (1 << 28U)
+#define USB_CR_LPM_PKT_EN (1 << 29U)
+#define USB_CR_SOF_3MS_EN (1 << 30U)
+#define USB_CR_USB_ERR_EN (1 << 31U)
+
+/* 0x24 : USB interrupt status */
+#define USB_SOF_INT (1 << 0U)
+#define USB_RESET_INT (1 << 1U)
+#define USB_VBUS_TGL_INT (1 << 2U)
+#define USB_GET_DCT_CMD_INT (1 << 3U)
+#define USB_EP0_SETUP_CMD_INT (1 << 4U)
+#define USB_EP0_SETUP_DONE_INT (1 << 5U)
+#define USB_EP0_IN_CMD_INT (1 << 6U)
+#define USB_EP0_IN_DONE_INT (1 << 7U)
+#define USB_EP0_OUT_CMD_INT (1 << 8U)
+#define USB_EP0_OUT_DONE_INT (1 << 9U)
+#define USB_EP1_CMD_INT (1 << 10U)
+#define USB_EP1_DONE_INT (1 << 11U)
+#define USB_EP2_CMD_INT (1 << 12U)
+#define USB_EP2_DONE_INT (1 << 13U)
+#define USB_EP3_CMD_INT (1 << 14U)
+#define USB_EP3_DONE_INT (1 << 15U)
+#define USB_EP4_CMD_INT (1 << 16U)
+#define USB_EP4_DONE_INT (1 << 17U)
+#define USB_EP5_CMD_INT (1 << 18U)
+#define USB_EP5_DONE_INT (1 << 19U)
+#define USB_EP6_CMD_INT (1 << 20U)
+#define USB_EP6_DONE_INT (1 << 21U)
+#define USB_EP7_CMD_INT (1 << 22U)
+#define USB_EP7_DONE_INT (1 << 23U)
+#define USB_REND_INT (1 << 27U)
+#define USB_LPM_WKUP_INT (1 << 28U)
+#define USB_LPM_PKT_INT (1 << 29U)
+#define USB_SOF_3MS_INT (1 << 30U)
+#define USB_ERR_INT (1 << 31U)
+
+/* 0x28 : USB interrupt mask */
+#define USB_CR_SOF_MASK (1 << 0U)
+#define USB_CR_USB_RESET_MASK (1 << 1U)
+#define USB_CR_VBUS_TGL_MASK (1 << 2U)
+#define USB_CR_GET_DCT_CMD_MASK (1 << 3U)
+#define USB_CR_EP0_SETUP_CMD_MASK (1 << 4U)
+#define USB_CR_EP0_SETUP_DONE_MASK (1 << 5U)
+#define USB_CR_EP0_IN_CMD_MASK (1 << 6U)
+#define USB_CR_EP0_IN_DONE_MASK (1 << 7U)
+#define USB_CR_EP0_OUT_CMD_MASK (1 << 8U)
+#define USB_CR_EP0_OUT_DONE_MASK (1 << 9U)
+#define USB_CR_EP1_CMD_MASK (1 << 10U)
+#define USB_CR_EP1_DONE_MASK (1 << 11U)
+#define USB_CR_EP2_CMD_MASK (1 << 12U)
+#define USB_CR_EP2_DONE_MASK (1 << 13U)
+#define USB_CR_EP3_CMD_MASK (1 << 14U)
+#define USB_CR_EP3_DONE_MASK (1 << 15U)
+#define USB_CR_EP4_CMD_MASK (1 << 16U)
+#define USB_CR_EP4_DONE_MASK (1 << 17U)
+#define USB_CR_EP5_CMD_MASK (1 << 18U)
+#define USB_CR_EP5_DONE_MASK (1 << 19U)
+#define USB_CR_EP6_CMD_MASK (1 << 20U)
+#define USB_CR_EP6_DONE_MASK (1 << 21U)
+#define USB_CR_EP7_CMD_MASK (1 << 22U)
+#define USB_CR_EP7_DONE_MASK (1 << 23U)
+#define USB_CR_USB_REND_MASK (1 << 27U)
+#define USB_CR_LPM_WKUP_MASK (1 << 28U)
+#define USB_CR_LPM_PKT_MASK (1 << 29U)
+#define USB_CR_SOF_3MS_MASK (1 << 30U)
+#define USB_CR_USB_ERR_MASK (1 << 31U)
+
+/* 0x2C : USB interrupt clear */
+#define USB_CR_SOF_CLR (1 << 0U)
+#define USB_CR_USB_RESET_CLR (1 << 1U)
+#define USB_CR_VBUS_TGL_CLR (1 << 2U)
+#define USB_CR_GET_DCT_CMD_CLR (1 << 3U)
+#define USB_CR_EP0_SETUP_CMD_CLR (1 << 4U)
+#define USB_CR_EP0_SETUP_DONE_CLR (1 << 5U)
+#define USB_CR_EP0_IN_CMD_CLR (1 << 6U)
+#define USB_CR_EP0_IN_DONE_CLR (1 << 7U)
+#define USB_CR_EP0_OUT_CMD_CLR (1 << 8U)
+#define USB_CR_EP0_OUT_DONE_CLR (1 << 9U)
+#define USB_CR_EP1_CMD_CLR (1 << 10U)
+#define USB_CR_EP1_DONE_CLR (1 << 11U)
+#define USB_CR_EP2_CMD_CLR (1 << 12U)
+#define USB_CR_EP2_DONE_CLR (1 << 13U)
+#define USB_CR_EP3_CMD_CLR (1 << 14U)
+#define USB_CR_EP3_DONE_CLR (1 << 15U)
+#define USB_CR_EP4_CMD_CLR (1 << 16U)
+#define USB_CR_EP4_DONE_CLR (1 << 17U)
+#define USB_CR_EP5_CMD_CLR (1 << 18U)
+#define USB_CR_EP5_DONE_CLR (1 << 19U)
+#define USB_CR_EP6_CMD_CLR (1 << 20U)
+#define USB_CR_EP6_DONE_CLR (1 << 21U)
+#define USB_CR_EP7_CMD_CLR (1 << 22U)
+#define USB_CR_EP7_DONE_CLR (1 << 23U)
+#define USB_CR_USB_REND_CLR (1 << 27U)
+#define USB_CR_LPM_WKUP_CLR (1 << 28U)
+#define USB_CR_LPM_PKT_CLR (1 << 29U)
+#define USB_CR_SOF_3MS_CLR (1 << 30U)
+#define USB_CR_USB_ERR_CLR (1 << 31U)
+
+/* 0x40 : ep1_config */
+#define USB_CR_EP1_SIZE_SHIFT (0U)
+#define USB_CR_EP1_SIZE_MASK (0x7ff << USB_CR_EP1_SIZE_SHIFT)
+#define USB_CR_EP1_DIR_SHIFT (11U)
+#define USB_CR_EP1_DIR_MASK (0x3 << USB_CR_EP1_DIR_SHIFT)
+#define USB_CR_EP1_TYPE_SHIFT (13U)
+#define USB_CR_EP1_TYPE_MASK (0x7 << USB_CR_EP1_TYPE_SHIFT)
+#define USB_CR_EP1_STALL (1 << 16U)
+#define USB_CR_EP1_NACK (1 << 17U)
+#define USB_CR_EP1_RDY (1 << 18U)
+#define USB_STS_EP1_RDY (1 << 19U)
+
+/* 0x44 : ep2_config */
+#define USB_CR_EP2_SIZE_SHIFT (0U)
+#define USB_CR_EP2_SIZE_MASK (0x7ff << USB_CR_EP2_SIZE_SHIFT)
+#define USB_CR_EP2_DIR_SHIFT (11U)
+#define USB_CR_EP2_DIR_MASK (0x3 << USB_CR_EP2_DIR_SHIFT)
+#define USB_CR_EP2_TYPE_SHIFT (13U)
+#define USB_CR_EP2_TYPE_MASK (0x7 << USB_CR_EP2_TYPE_SHIFT)
+#define USB_CR_EP2_STALL (1 << 16U)
+#define USB_CR_EP2_NACK (1 << 17U)
+#define USB_CR_EP2_RDY (1 << 18U)
+#define USB_STS_EP2_RDY (1 << 19U)
+
+/* 0x48 : ep3_config */
+#define USB_CR_EP3_SIZE_SHIFT (0U)
+#define USB_CR_EP3_SIZE_MASK (0x7ff << USB_CR_EP3_SIZE_SHIFT)
+#define USB_CR_EP3_DIR_SHIFT (11U)
+#define USB_CR_EP3_DIR_MASK (0x3 << USB_CR_EP3_DIR_SHIFT)
+#define USB_CR_EP3_TYPE_SHIFT (13U)
+#define USB_CR_EP3_TYPE_MASK (0x7 << USB_CR_EP3_TYPE_SHIFT)
+#define USB_CR_EP3_STALL (1 << 16U)
+#define USB_CR_EP3_NACK (1 << 17U)
+#define USB_CR_EP3_RDY (1 << 18U)
+#define USB_STS_EP3_RDY (1 << 19U)
+
+/* 0x4C : ep4_config */
+#define USB_CR_EP4_SIZE_SHIFT (0U)
+#define USB_CR_EP4_SIZE_MASK (0x7ff << USB_CR_EP4_SIZE_SHIFT)
+#define USB_CR_EP4_DIR_SHIFT (11U)
+#define USB_CR_EP4_DIR_MASK (0x3 << USB_CR_EP4_DIR_SHIFT)
+#define USB_CR_EP4_TYPE_SHIFT (13U)
+#define USB_CR_EP4_TYPE_MASK (0x7 << USB_CR_EP4_TYPE_SHIFT)
+#define USB_CR_EP4_STALL (1 << 16U)
+#define USB_CR_EP4_NACK (1 << 17U)
+#define USB_CR_EP4_RDY (1 << 18U)
+#define USB_STS_EP4_RDY (1 << 19U)
+
+/* 0x50 : ep5_config */
+#define USB_CR_EP5_SIZE_SHIFT (0U)
+#define USB_CR_EP5_SIZE_MASK (0x7ff << USB_CR_EP5_SIZE_SHIFT)
+#define USB_CR_EP5_DIR_SHIFT (11U)
+#define USB_CR_EP5_DIR_MASK (0x3 << USB_CR_EP5_DIR_SHIFT)
+#define USB_CR_EP5_TYPE_SHIFT (13U)
+#define USB_CR_EP5_TYPE_MASK (0x7 << USB_CR_EP5_TYPE_SHIFT)
+#define USB_CR_EP5_STALL (1 << 16U)
+#define USB_CR_EP5_NACK (1 << 17U)
+#define USB_CR_EP5_RDY (1 << 18U)
+#define USB_STS_EP5_RDY (1 << 19U)
+
+/* 0x54 : ep6_config */
+#define USB_CR_EP6_SIZE_SHIFT (0U)
+#define USB_CR_EP6_SIZE_MASK (0x7ff << USB_CR_EP6_SIZE_SHIFT)
+#define USB_CR_EP6_DIR_SHIFT (11U)
+#define USB_CR_EP6_DIR_MASK (0x3 << USB_CR_EP6_DIR_SHIFT)
+#define USB_CR_EP6_TYPE_SHIFT (13U)
+#define USB_CR_EP6_TYPE_MASK (0x7 << USB_CR_EP6_TYPE_SHIFT)
+#define USB_CR_EP6_STALL (1 << 16U)
+#define USB_CR_EP6_NACK (1 << 17U)
+#define USB_CR_EP6_RDY (1 << 18U)
+#define USB_STS_EP6_RDY (1 << 19U)
+
+/* 0x58 : ep7_config */
+#define USB_CR_EP7_SIZE_SHIFT (0U)
+#define USB_CR_EP7_SIZE_MASK (0x7ff << USB_CR_EP7_SIZE_SHIFT)
+#define USB_CR_EP7_DIR_SHIFT (11U)
+#define USB_CR_EP7_DIR_MASK (0x3 << USB_CR_EP7_DIR_SHIFT)
+#define USB_CR_EP7_TYPE_SHIFT (13U)
+#define USB_CR_EP7_TYPE_MASK (0x7 << USB_CR_EP7_TYPE_SHIFT)
+#define USB_CR_EP7_STALL (1 << 16U)
+#define USB_CR_EP7_NACK (1 << 17U)
+#define USB_CR_EP7_RDY (1 << 18U)
+#define USB_STS_EP7_RDY (1 << 19U)
+
+/* 0x100 : ep0_fifo_config */
+#define USB_EP0_DMA_TX_EN (1 << 0U)
+#define USB_EP0_DMA_RX_EN (1 << 1U)
+#define USB_EP0_TX_FIFO_CLR (1 << 2U)
+#define USB_EP0_RX_FIFO_CLR (1 << 3U)
+#define USB_EP0_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP0_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP0_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP0_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x104 : ep0_fifo_status */
+#define USB_EP0_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP0_TX_FIFO_CNT_MASK (0x7f << USB_EP0_TX_FIFO_CNT_SHIFT)
+#define USB_EP0_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP0_TX_FIFO_FULL (1 << 15U)
+#define USB_EP0_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP0_RX_FIFO_CNT_MASK (0x7f << USB_EP0_RX_FIFO_CNT_SHIFT)
+#define USB_EP0_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP0_RX_FIFO_FULL (1 << 31U)
+
+/* 0x108 : ep0_tx_fifo_wdata */
+#define USB_EP0_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP0_TX_FIFO_WDATA_MASK (0xff << USB_EP0_TX_FIFO_WDATA_SHIFT)
+
+/* 0x10C : ep0_rx_fifo_rdata */
+#define USB_EP0_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP0_RX_FIFO_RDATA_MASK (0xff << USB_EP0_RX_FIFO_RDATA_SHIFT)
+
+/* 0x110 : ep1_fifo_config */
+#define USB_EP1_DMA_TX_EN (1 << 0U)
+#define USB_EP1_DMA_RX_EN (1 << 1U)
+#define USB_EP1_TX_FIFO_CLR (1 << 2U)
+#define USB_EP1_RX_FIFO_CLR (1 << 3U)
+#define USB_EP1_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP1_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP1_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP1_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x114 : ep1_fifo_status */
+#define USB_EP1_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP1_TX_FIFO_CNT_MASK (0x7f << USB_EP1_TX_FIFO_CNT_SHIFT)
+#define USB_EP1_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP1_TX_FIFO_FULL (1 << 15U)
+#define USB_EP1_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP1_RX_FIFO_CNT_MASK (0x7f << USB_EP1_RX_FIFO_CNT_SHIFT)
+#define USB_EP1_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP1_RX_FIFO_FULL (1 << 31U)
+
+/* 0x118 : ep1_tx_fifo_wdata */
+#define USB_EP1_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP1_TX_FIFO_WDATA_MASK (0xff << USB_EP1_TX_FIFO_WDATA_SHIFT)
+
+/* 0x11C : ep1_rx_fifo_rdata */
+#define USB_EP1_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP1_RX_FIFO_RDATA_MASK (0xff << USB_EP1_RX_FIFO_RDATA_SHIFT)
+
+/* 0x120 : ep2_fifo_config */
+#define USB_EP2_DMA_TX_EN (1 << 0U)
+#define USB_EP2_DMA_RX_EN (1 << 1U)
+#define USB_EP2_TX_FIFO_CLR (1 << 2U)
+#define USB_EP2_RX_FIFO_CLR (1 << 3U)
+#define USB_EP2_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP2_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP2_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP2_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x124 : ep2_fifo_status */
+#define USB_EP2_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP2_TX_FIFO_CNT_MASK (0x7f << USB_EP2_TX_FIFO_CNT_SHIFT)
+#define USB_EP2_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP2_TX_FIFO_FULL (1 << 15U)
+#define USB_EP2_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP2_RX_FIFO_CNT_MASK (0x7f << USB_EP2_RX_FIFO_CNT_SHIFT)
+#define USB_EP2_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP2_RX_FIFO_FULL (1 << 31U)
+
+/* 0x128 : ep2_tx_fifo_wdata */
+#define USB_EP2_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP2_TX_FIFO_WDATA_MASK (0xff << USB_EP2_TX_FIFO_WDATA_SHIFT)
+
+/* 0x12C : ep2_rx_fifo_rdata */
+#define USB_EP2_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP2_RX_FIFO_RDATA_MASK (0xff << USB_EP2_RX_FIFO_RDATA_SHIFT)
+
+/* 0x130 : ep3_fifo_config */
+#define USB_EP3_DMA_TX_EN (1 << 0U)
+#define USB_EP3_DMA_RX_EN (1 << 1U)
+#define USB_EP3_TX_FIFO_CLR (1 << 2U)
+#define USB_EP3_RX_FIFO_CLR (1 << 3U)
+#define USB_EP3_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP3_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP3_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP3_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x134 : ep3_fifo_status */
+#define USB_EP3_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP3_TX_FIFO_CNT_MASK (0x7f << USB_EP3_TX_FIFO_CNT_SHIFT)
+#define USB_EP3_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP3_TX_FIFO_FULL (1 << 15U)
+#define USB_EP3_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP3_RX_FIFO_CNT_MASK (0x7f << USB_EP3_RX_FIFO_CNT_SHIFT)
+#define USB_EP3_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP3_RX_FIFO_FULL (1 << 31U)
+
+/* 0x138 : ep3_tx_fifo_wdata */
+#define USB_EP3_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP3_TX_FIFO_WDATA_MASK (0xff << USB_EP3_TX_FIFO_WDATA_SHIFT)
+
+/* 0x13C : ep3_rx_fifo_rdata */
+#define USB_EP3_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP3_RX_FIFO_RDATA_MASK (0xff << USB_EP3_RX_FIFO_RDATA_SHIFT)
+
+/* 0x140 : ep4_fifo_config */
+#define USB_EP4_DMA_TX_EN (1 << 0U)
+#define USB_EP4_DMA_RX_EN (1 << 1U)
+#define USB_EP4_TX_FIFO_CLR (1 << 2U)
+#define USB_EP4_RX_FIFO_CLR (1 << 3U)
+#define USB_EP4_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP4_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP4_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP4_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x144 : ep4_fifo_status */
+#define USB_EP4_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP4_TX_FIFO_CNT_MASK (0x7f << USB_EP4_TX_FIFO_CNT_SHIFT)
+#define USB_EP4_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP4_TX_FIFO_FULL (1 << 15U)
+#define USB_EP4_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP4_RX_FIFO_CNT_MASK (0x7f << USB_EP4_RX_FIFO_CNT_SHIFT)
+#define USB_EP4_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP4_RX_FIFO_FULL (1 << 31U)
+
+/* 0x148 : ep4_tx_fifo_wdata */
+#define USB_EP4_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP4_TX_FIFO_WDATA_MASK (0xff << USB_EP4_TX_FIFO_WDATA_SHIFT)
+
+/* 0x14C : ep4_rx_fifo_rdata */
+#define USB_EP4_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP4_RX_FIFO_RDATA_MASK (0xff << USB_EP4_RX_FIFO_RDATA_SHIFT)
+
+/* 0x150 : ep5_fifo_config */
+#define USB_EP5_DMA_TX_EN (1 << 0U)
+#define USB_EP5_DMA_RX_EN (1 << 1U)
+#define USB_EP5_TX_FIFO_CLR (1 << 2U)
+#define USB_EP5_RX_FIFO_CLR (1 << 3U)
+#define USB_EP5_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP5_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP5_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP5_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x154 : ep5_fifo_status */
+#define USB_EP5_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP5_TX_FIFO_CNT_MASK (0x7f << USB_EP5_TX_FIFO_CNT_SHIFT)
+#define USB_EP5_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP5_TX_FIFO_FULL (1 << 15U)
+#define USB_EP5_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP5_RX_FIFO_CNT_MASK (0x7f << USB_EP5_RX_FIFO_CNT_SHIFT)
+#define USB_EP5_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP5_RX_FIFO_FULL (1 << 31U)
+
+/* 0x158 : ep5_tx_fifo_wdata */
+#define USB_EP5_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP5_TX_FIFO_WDATA_MASK (0xff << USB_EP5_TX_FIFO_WDATA_SHIFT)
+
+/* 0x15C : ep5_rx_fifo_rdata */
+#define USB_EP5_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP5_RX_FIFO_RDATA_MASK (0xff << USB_EP5_RX_FIFO_RDATA_SHIFT)
+
+/* 0x160 : ep6_fifo_config */
+#define USB_EP6_DMA_TX_EN (1 << 0U)
+#define USB_EP6_DMA_RX_EN (1 << 1U)
+#define USB_EP6_TX_FIFO_CLR (1 << 2U)
+#define USB_EP6_RX_FIFO_CLR (1 << 3U)
+#define USB_EP6_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP6_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP6_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP6_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x164 : ep6_fifo_status */
+#define USB_EP6_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP6_TX_FIFO_CNT_MASK (0x7f << USB_EP6_TX_FIFO_CNT_SHIFT)
+#define USB_EP6_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP6_TX_FIFO_FULL (1 << 15U)
+#define USB_EP6_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP6_RX_FIFO_CNT_MASK (0x7f << USB_EP6_RX_FIFO_CNT_SHIFT)
+#define USB_EP6_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP6_RX_FIFO_FULL (1 << 31U)
+
+/* 0x168 : ep6_tx_fifo_wdata */
+#define USB_EP6_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP6_TX_FIFO_WDATA_MASK (0xff << USB_EP6_TX_FIFO_WDATA_SHIFT)
+
+/* 0x16C : ep6_rx_fifo_rdata */
+#define USB_EP6_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP6_RX_FIFO_RDATA_MASK (0xff << USB_EP6_RX_FIFO_RDATA_SHIFT)
+
+/* 0x170 : ep7_fifo_config */
+#define USB_EP7_DMA_TX_EN (1 << 0U)
+#define USB_EP7_DMA_RX_EN (1 << 1U)
+#define USB_EP7_TX_FIFO_CLR (1 << 2U)
+#define USB_EP7_RX_FIFO_CLR (1 << 3U)
+#define USB_EP7_TX_FIFO_OVERFLOW (1 << 4U)
+#define USB_EP7_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP7_RX_FIFO_OVERFLOW (1 << 6U)
+#define USB_EP7_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x174 : ep7_fifo_status */
+#define USB_EP7_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP7_TX_FIFO_CNT_MASK (0x7f << USB_EP7_TX_FIFO_CNT_SHIFT)
+#define USB_EP7_TX_FIFO_EMPTY (1 << 14U)
+#define USB_EP7_TX_FIFO_FULL (1 << 15U)
+#define USB_EP7_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP7_RX_FIFO_CNT_MASK (0x7f << USB_EP7_RX_FIFO_CNT_SHIFT)
+#define USB_EP7_RX_FIFO_EMPTY (1 << 30U)
+#define USB_EP7_RX_FIFO_FULL (1 << 31U)
+
+/* 0x178 : ep7_tx_fifo_wdata */
+#define USB_EP7_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP7_TX_FIFO_WDATA_MASK (0xff << USB_EP7_TX_FIFO_WDATA_SHIFT)
+
+/* 0x17C : ep7_rx_fifo_rdata */
+#define USB_EP7_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP7_RX_FIFO_RDATA_MASK (0xff << USB_EP7_RX_FIFO_RDATA_SHIFT)
+
+/* 0x1F0 : rsvd_0 */
+
+/* 0x1F4 : rsvd_1 */
+
+/* 0x1FC : xcvr_if_config */
+#define USB_CR_XCVR_FORCE_TX_EN (1 << 0U)
+#define USB_CR_XCVR_FORCE_TX_OE (1 << 1U)
+#define USB_CR_XCVR_FORCE_TX_DP (1 << 2U)
+#define USB_CR_XCVR_FORCE_TX_DN (1 << 3U)
+#define USB_CR_XCVR_FORCE_RX_EN (1 << 4U)
+#define USB_CR_XCVR_FORCE_RX_D (1 << 5U)
+#define USB_CR_XCVR_FORCE_RX_DP (1 << 6U)
+#define USB_CR_XCVR_FORCE_RX_DN (1 << 7U)
+#define USB_CR_XCVR_OM_RX_SEL (1 << 8U)
+#define USB_CR_XCVR_OM_RX_D (1 << 9U)
+#define USB_CR_XCVR_OM_RX_DP (1 << 10U)
+#define USB_CR_XCVR_OM_RX_DN (1 << 11U)
+#define USB_STS_VBUS_DET (1 << 31U)
+
+#endif /* __HARDWARE_USB_V1_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/include/hardware/usb_v2_reg.h b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/usb_v2_reg.h
new file mode 100644
index 00000000..a126038c
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/include/hardware/usb_v2_reg.h
@@ -0,0 +1,734 @@
+/**
+ ******************************************************************************
+ * @file usb_v2_reg.h
+ * @version V1.0
+ * @date 2022-08-15
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_USB_V2_H__
+#define __HARDWARE_USB_V2_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define USB_HCCAP_OFFSET (0x0) /* HCCAP */
+#define USB_HCSPARAMS_OFFSET (0x4) /* HCSPARAMS */
+#define USB_HCCPARAMS_OFFSET (0x8) /* HCCPARAMS */
+#define USBCMD_OFFSET (0x10) /* USBCMD */
+#define USBSTS_OFFSET (0x14) /* USBSTS */
+#define USBINTR_OFFSET (0x18) /* USBINTR */
+#define USB_FRINDEX_OFFSET (0x1C) /* FRINDEX */
+#define USB_PERIODICLISTBASE_OFFSET (0x24) /* PERIODICLISTBASE */
+#define USB_ASYNCLISTADDR_OFFSET (0x28) /* ASYNCLISTADDR */
+#define USB_PORTSC_OFFSET (0x30) /* PORTSC */
+#define USB_HCMISC_OFFSET (0x40) /* HCMISC */
+#define USB_FS_EOF_OFFSET (0x44) /* FS_EOF */
+#define USB_HS_EOF_OFFSET (0x48) /* HS_EOF */
+#define USB_OTG_CSR_OFFSET (0x80) /* OTG_CSR */
+#define USB_OTG_ISR_OFFSET (0x84) /* OTG_ISR */
+#define USB_OTG_IER_OFFSET (0x88) /* OTG_IER */
+#define USB_GLB_ISR_OFFSET (0xC0) /* GLB_ISR */
+#define USB_GLB_INT_OFFSET (0xC4) /* GLB_INT */
+#define USB_REVISION_OFFSET (0xE0) /* REVISION */
+#define USB_FEATURE_OFFSET (0xE4) /* FEATURE */
+#define USB_AXI_CR_OFFSET (0xE8) /* AXI_CR */
+#define USB_DEV_CTL_OFFSET (0x100) /* DEV_CTL */
+#define USB_DEV_ADR_OFFSET (0x104) /* DEV_ADR */
+#define USB_DEV_TST_OFFSET (0x108) /* DEV_TST */
+#define USB_DEV_SFN_OFFSET (0x10C) /* DEV_SFN */
+#define USB_DEV_SMT_OFFSET (0x110) /* DEV_SMT */
+#define USB_PHY_TST_OFFSET (0x114) /* PHY_TST */
+#define USB_DEV_VCTL_OFFSET (0x118) /* DEV_VCTL */
+#define USB_DEV_CXCFG_OFFSET (0x11C) /* DEV_CXCFG */
+#define USB_DEV_CXCFE_OFFSET (0x120) /* DEV_CXCFE */
+#define USB_DEV_ICR_OFFSET (0x124) /* DEV_ICR */
+#define USB_DEV_MIGR_OFFSET (0x130) /* DEV_MIGR */
+#define USB_DEV_MISG0_OFFSET (0x134) /* DEV_MISG0 */
+#define USB_DEV_MISG1_OFFSET (0x138) /* DEV_MISG1 */
+#define USB_DEV_MISG2_OFFSET (0x13C) /* DEV_MISG2 */
+#define USB_DEV_IGR_OFFSET (0x140) /* DEV_IGR */
+#define USB_DEV_ISG0_OFFSET (0x144) /* DEV_ISG0 */
+#define USB_DEV_ISG1_OFFSET (0x148) /* DEV_ISG1 */
+#define USB_DEV_ISG2_OFFSET (0x14C) /* DEV_ISG2 */
+#define USB_DEV_RXZ_OFFSET (0x150) /* DEV_RXZ */
+#define USB_DEV_TXZ_OFFSET (0x154) /* DEV_TXZ */
+#define USB_DEV_ISE_OFFSET (0x158) /* DEV_ISE */
+#define USB_DEV_INMPS1_OFFSET (0x160) /* DEV_INMPS1 */
+#define USB_DEV_INMPS2_OFFSET (0x164) /* DEV_INMPS2 */
+#define USB_DEV_INMPS3_OFFSET (0x168) /* DEV_INMPS3 */
+#define USB_DEV_INMPS4_OFFSET (0x16C) /* DEV_INMPS4 */
+#define USB_DEV_INMPS5_OFFSET (0x170) /* DEV_INMPS5 */
+#define USB_DEV_INMPS6_OFFSET (0x174) /* DEV_INMPS6 */
+#define USB_DEV_INMPS7_OFFSET (0x178) /* DEV_INMPS7 */
+#define USB_DEV_INMPS8_OFFSET (0x17C) /* DEV_INMPS8 */
+#define USB_DEV_OUTMPS1_OFFSET (0x180) /* DEV_OUTMPS1 */
+#define USB_DEV_OUTMPS2_OFFSET (0x184) /* DEV_OUTMPS2 */
+#define USB_DEV_OUTMPS3_OFFSET (0x188) /* DEV_OUTMPS3 */
+#define USB_DEV_OUTMPS4_OFFSET (0x18C) /* DEV_OUTMPS4 */
+#define USB_DEV_OUTMPS5_OFFSET (0x190) /* DEV_OUTMPS5 */
+#define USB_DEV_OUTMPS6_OFFSET (0x194) /* DEV_OUTMPS6 */
+#define USB_DEV_OUTMPS7_OFFSET (0x198) /* DEV_OUTMPS7 */
+#define USB_DEV_OUTMPS8_OFFSET (0x19C) /* DEV_OUTMPS8 */
+#define USB_DEV_EPMAP0_OFFSET (0x1A0) /* DEV_EPMAP0 */
+#define USB_DEV_EPMAP1_OFFSET (0x1A4) /* DEV_EPMAP1 */
+#define USB_DEV_FMAP_OFFSET (0x1A8) /* DEV_FMAP */
+#define USB_DEV_FCFG_OFFSET (0x1AC) /* DEV_FCFG */
+#define USB_DEV_FIBC0_OFFSET (0x1B0) /* DEV_FIBC0 */
+#define USB_DEV_FIBC1_OFFSET (0x1B4) /* DEV_FIBC1 */
+#define USB_DEV_FIBC2_OFFSET (0x1B8) /* DEV_FIBC2 */
+#define USB_DEV_FIBC3_OFFSET (0x1BC) /* DEV_FIBC3 */
+#define USB_DMA_TFN_OFFSET (0x1C0) /* DMA_TFN */
+#define USB_DMA_CPS0_OFFSET (0x1C4) /* DMA_CPS0 */
+#define USB_DMA_CPS1_OFFSET (0x1C8) /* DMA_CPS1 */
+#define USB_DMA_CPS2_OFFSET (0x1CC) /* DMA_CPS2 */
+#define USB_DMA_CPS3_OFFSET (0x1D0) /* DMA_CPS3 */
+#define USB_DMA_CPS4_OFFSET (0x1D4) /* DMA_CPS4 */
+#define USB_DEV_FMAP2_OFFSET (0x1D8) /* DEV_FMAP2 */
+#define USB_DEV_FCFG2_OFFSET (0x1DC) /* DEV_FCFG2 */
+#define USB_DEV_FMAP3_OFFSET (0x1E0) /* DEV_FMAP3 */
+#define USB_DEV_FCFG3_OFFSET (0x1E4) /* DEV_FCFG3 */
+#define USB_DEV_FMAP4_OFFSET (0x1E8) /* DEV_FMAP4 */
+#define USB_DEV_FCFG4_OFFSET (0x1EC) /* DEV_FCFG4 */
+#define USB_DEV_FIBC4_OFFSET (0x1F0) /* DEV_FIBC4 */
+#define USB_DEV_FIBC5_OFFSET (0x1F4) /* DEV_FIBC5 */
+#define USB_DEV_FIBC6_OFFSET (0x1F8) /* DEV_FIBC6 */
+#define USB_DEV_FIBC7_OFFSET (0x1FC) /* DEV_FIBC7 */
+#define USB_VDMA_CXFPS1_OFFSET (0x300) /* VDMA_CXFPS1 */
+#define USB_VDMA_CXFPS2_OFFSET (0x304) /* VDMA_CXFPS2 */
+#define USB_VDMA_F0PS1_OFFSET (0x308) /* VDMA_F0PS1 */
+#define USB_VDMA_F0PS2_OFFSET (0x30C) /* VDMA_F0PS2 */
+#define USB_VDMA_F1PS1_OFFSET (0x310) /* VDMA_F1PS1 */
+#define USB_VDMA_F1PS2_OFFSET (0x314) /* VDMA_F1PS2 */
+#define USB_VDMA_F2PS1_OFFSET (0x318) /* VDMA_F2PS1 */
+#define USB_VDMA_F2PS2_OFFSET (0x31C) /* VDMA_F2PS2 */
+#define USB_VDMA_F3PS1_OFFSET (0x320) /* VDMA_F3PS1 */
+#define USB_VDMA_F3PS2_OFFSET (0x324) /* VDMA_F3PS2 */
+#define USB_DEV_ISG3_OFFSET (0x328) /* DEV_ISG3 */
+#define USB_DEV_MISG3_OFFSET (0x32C) /* DEV_MISG3 */
+#define USB_VDMA_CTRL_OFFSET (0x330) /* VDMA_CTRL */
+#define USB_LPM_CAP_OFFSET (0x334) /* LPM_CAP */
+#define USB_DEV_ISG4_OFFSET (0x338) /* DEV_ISG4 */
+#define USB_DEV_MISG4_OFFSET (0x33C) /* DEV_MISG4 */
+#define USB_VDMA_FNPS1_OFFSET (0x350) /* VDMA_FNPS1 */
+#define USB_VDMA_FNPS2_OFFSET (0x354) /* VDMA_FNPS2 */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : HCCAP */
+#define USB_CAPLENGTH_SHIFT (0U)
+#define USB_CAPLENGTH_MASK (0xff << USB_CAPLENGTH_SHIFT)
+#define USB_HCIVERSION_SHIFT (16U)
+#define USB_HCIVERSION_MASK (0xffff << USB_HCIVERSION_SHIFT)
+
+/* 0x4 : HCSPARAMS */
+#define USB_N_PORTS_SHIFT (0U)
+#define USB_N_PORTS_MASK (0xf << USB_N_PORTS_SHIFT)
+
+/* 0x8 : HCCPARAMS */
+#define USB_PROG_FR_LIST_FLAG (1 << 1U)
+#define USB_ASYN_SCH_PARK_CAP (1 << 2U)
+
+/* 0x10 : USBCMD */
+#define USB_RS (1 << 0U)
+#define USB_HC_RESET (1 << 1U)
+#define USB_FRL_SIZE_SHIFT (2U)
+#define USB_FRL_SIZE_MASK (0x3 << USB_FRL_SIZE_SHIFT)
+#define USB_PSCH_EN (1 << 4U)
+#define USB_ASCH_EN (1 << 5U)
+#define USB_INT_OAAD (1 << 6U)
+#define USB_ASYN_PK_CNT_SHIFT (8U)
+#define USB_ASYN_PK_CNT_MASK (0x3 << USB_ASYN_PK_CNT_SHIFT)
+#define USB_ASYN_PK_EN (1 << 11U)
+#define USB_INT_THRC_SHIFT (16U)
+#define USB_INT_THRC_MASK (0xff << USB_INT_THRC_SHIFT)
+
+/* 0x14 : USBSTS */
+#define USB_INT (1 << 0U)
+#define USBERR_INT (1 << 1U)
+#define USB_PO_CHG_DET (1 << 2U)
+#define USB_FRL_ROL (1 << 3U)
+#define USB_H_SYSERR (1 << 4U)
+#define USB_INT_OAA (1 << 5U)
+#define USB_HCHALTED (1 << 12U)
+#define USB_RECLAMATION (1 << 13U)
+#define USB_PSCH_STS (1 << 14U)
+#define USB_ASCH_STS (1 << 15U)
+
+/* 0x18 : USBINTR */
+#define USB_INT_EN (1 << 0U)
+#define USBERR_INT_EN (1 << 1U)
+#define USB_PO_CHG_INT_EN (1 << 2U)
+#define USB_FRL_ROL_EN (1 << 3U)
+#define USB_H_SYSERR_EN (1 << 4U)
+#define USB_INT_OAA_EN (1 << 5U)
+
+/* 0x1C : FRINDEX */
+#define USB_FRINDEX_SHIFT (0U)
+#define USB_FRINDEX_MASK (0x3fff << USB_FRINDEX_SHIFT)
+
+/* 0x24 : PERIODICLISTBASE */
+#define USB_PERI_BASADR_SHIFT (12U)
+#define USB_PERI_BASADR_MASK (0xfffff << USB_PERI_BASADR_SHIFT)
+
+/* 0x28 : ASYNCLISTADDR */
+#define USB_ASYNC_LADR_SHIFT (5U)
+#define USB_ASYNC_LADR_MASK (0x7fffff << USB_ASYNC_LADR_SHIFT)
+
+/* 0x30 : PORTSC */
+#define USB_CONN_STS (1 << 0U)
+#define USB_CONN_CHG (1 << 1U)
+#define USB_PO_EN (1 << 2U)
+#define USB_PO_EN_CHG (1 << 3U)
+#define USB_F_PO_RESM (1 << 6U)
+#define USB_PO_SUSP (1 << 7U)
+#define USB_PO_RESET (1 << 8U)
+#define USB_LINE_STS_SHIFT (10U)
+#define USB_LINE_STS_MASK (0x3 << USB_LINE_STS_SHIFT)
+#define USB_PORT_TEST_SHIFT (16U)
+#define USB_PORT_TEST_MASK (0xf << USB_PORT_TEST_SHIFT)
+#define USB_HC_TST_PKDONE (1 << 20U)
+
+/* 0x40 : HCMISC */
+#define USB_ASYN_SCH_SLPT_SHIFT (0U)
+#define USB_ASYN_SCH_SLPT_MASK (0x3 << USB_ASYN_SCH_SLPT_SHIFT)
+#define USB_EOF1_TIME_SHIFT (2U)
+#define USB_EOF1_TIME_MASK (0x3 << USB_EOF1_TIME_SHIFT)
+#define USB_EOF2_TIME_SHIFT (4U)
+#define USB_EOF2_TIME_MASK (0x3 << USB_EOF2_TIME_SHIFT)
+#define USB_HOSTPHY_SUSPEND (1 << 6U)
+#define USB_HC_WKP_DET_EN (1 << 8U)
+#define USB_HC_CONN_DET_EN (1 << 9U)
+
+/* 0x44 : FS_EOF */
+#define USB_FS_EOF1_TIME_SHIFT (0U)
+#define USB_FS_EOF1_TIME_MASK (0xfff << USB_FS_EOF1_TIME_SHIFT)
+#define USB_FS_EOF1_TIME_125US_SHIFT (12U)
+#define USB_FS_EOF1_TIME_125US_MASK (0x7 << USB_FS_EOF1_TIME_125US_SHIFT)
+#define USB_ITDDMASM_SHIFT (16U)
+#define USB_ITDDMASM_MASK (0xf << USB_ITDDMASM_SHIFT)
+#define USB_ITDTRAVSM_SHIFT (20U)
+#define USB_ITDTRAVSM_MASK (0x3 << USB_ITDTRAVSM_SHIFT)
+#define USB_DMADMSM_SHIFT (22U)
+#define USB_DMADMSM_MASK (0xf << USB_DMADMSM_SHIFT)
+#define USB_QHTTRSM_SHIFT (26U)
+#define USB_QHTTRSM_MASK (0x7 << USB_QHTTRSM_SHIFT)
+#define USB_QHTRAVSM_SHIFT (29U)
+#define USB_QHTRAVSM_MASK (0x7 << USB_QHTRAVSM_SHIFT)
+
+/* 0x48 : HS_EOF */
+#define USB_HS_EOF1_TIME_SHIFT (0U)
+#define USB_HS_EOF1_TIME_MASK (0xfff << USB_HS_EOF1_TIME_SHIFT)
+#define USB_FS_EOF1_TIME_125US_SHIFT (12U)
+#define USB_FS_EOF1_TIME_125US_MASK (0x7 << USB_FS_EOF1_TIME_125US_SHIFT)
+#define USB_SITDDMASM_SHIFT (16U)
+#define USB_SITDDMASM_MASK (0xf << USB_SITDDMASM_SHIFT)
+#define USB_SITDTRAVSM_SHIFT (20U)
+#define USB_SITDTRAVSM_MASK (0x3 << USB_SITDTRAVSM_SHIFT)
+
+/* 0x80 : OTG_CSR */
+#define USB_B_BUS_REQ (1 << 0U)
+#define USB_B_HNP_EN (1 << 1U)
+#define USB_B_DSCHRG_VBUS (1 << 2U)
+#define USB_A_BUS_REQ_HOV (1 << 4U)
+#define USB_A_BUS_DROP_HOV (1 << 5U)
+#define USB_A_SET_B_HNP_EN (1 << 6U)
+#define USB_A_SRP_DET_EN (1 << 7U)
+#define USB_A_SRP_RESP_TYP (1 << 8U)
+#define USB_ID_FLT_SEL (1 << 9U)
+#define USB_VBUS_FLT_SEL_HOV_POV (1 << 10U)
+#define USB_HDISCON_FLT_SEL_HOV (1 << 11U)
+#define USB_IDPULUP_HOV_POV (1 << 13U)
+#define USB_B_SESS_END_POV (1 << 16U)
+#define USB_B_SESS_VLD_POV (1 << 17U)
+#define USB_A_SESS_VLD (1 << 18U)
+#define USB_VBUS_VLD_HOV (1 << 19U)
+#define USB_CROLE_HOV_POV (1 << 20U)
+#define USB_ID_HOV_POV (1 << 21U)
+#define USB_SPD_TYP_HOV_POV_SHIFT (22U)
+#define USB_SPD_TYP_HOV_POV_MASK (0x3 << USB_SPD_TYP_HOV_POV_SHIFT)
+
+/* 0x84 : OTG_ISR */
+#define USB_B_SRP_DN (1 << 0U)
+#define USB_A_SRP_DET (1 << 4U)
+#define USB_A_VBUS_ERR_HOV (1 << 5U)
+#define USB_B_SESS_END_INT_POV (1 << 6U)
+#define USB_RLCHG (1 << 8U)
+#define USB_IDCHG (1 << 9U)
+#define USB_OVC_HOV (1 << 10U)
+#define USB_A_WAIT_CON_HOV (1 << 11U)
+#define USB_APLGRMV (1 << 12U)
+
+/* 0x88 : OTG_IER */
+#define USB_B_SRP_DN_EN (1 << 0U)
+#define USB_A_SRP_DET_INT_EN (1 << 4U)
+#define USB_A_VBUS_ERR_EN_HOV (1 << 5U)
+#define USB_B_SESS_END_EN_POV (1 << 6U)
+#define USB_RLCHG_EN (1 << 8U)
+#define USB_IDCHG_EN (1 << 9U)
+#define USB_OVC_EN_HOV (1 << 10U)
+#define USB_A_WAIT_CON_EN_HOV (1 << 11U)
+#define USB_APLGRMV_EN (1 << 12U)
+
+/* 0xC0 : GLB_ISR */
+#define USB_DEV_INT (1 << 0U)
+#define USB_OTG_INT (1 << 1U)
+#define USB_HC_INT (1 << 2U)
+
+/* 0xC4 : GLB_INT */
+#define USB_MDEV_INT (1 << 0U)
+#define USB_MOTG_INT (1 << 1U)
+#define USB_MHC_INT (1 << 2U)
+
+/* 0xE0 : REVISION */
+#define USB_REVISION_SHIFT (0U)
+#define USB_REVISION_MASK (0xffffffff << USB_REVISION_SHIFT)
+
+/* 0xE4 : FEATURE */
+#define USB_DMABUFSIZE_SHIFT (0U)
+#define USB_DMABUFSIZE_MASK (0x1f << USB_DMABUFSIZE_SHIFT)
+#define USB_FIFO_NUM_SHIFT (5U)
+#define USB_FIFO_NUM_MASK (0x1f << USB_FIFO_NUM_SHIFT)
+#define USB_EP_NUM_SHIFT (10U)
+#define USB_EP_NUM_MASK (0x1f << USB_EP_NUM_SHIFT)
+#define USB_DEV_ONLY (1 << 15U)
+#define USB_HOST_ONLY (1 << 16U)
+
+/* 0xE8 : AXI_CR */
+#define USB_AXI_SGLBST (1 << 0U)
+
+/* 0x100 : DEV_CTL */
+#define USB_CAP_RMWAKUP (1 << 0U)
+#define USB_HALF_SPEED_HOV (1 << 1U)
+#define USB_GLINT_EN_HOV (1 << 2U)
+#define USB_GOSUSP (1 << 3U)
+#define USB_SFRST_HOV (1 << 4U)
+#define USB_CHIP_EN_HOV (1 << 5U)
+#define USB_HS_EN_HOV (1 << 6U)
+#define USB_SYSBUS_WIDTH_HOV (1 << 7U)
+#define USB_FORCE_FS (1 << 9U)
+#define USB_IDLE_DEGLITCH_HOV (1 << 10U)
+#define USB_LPM_BESL_MAX_SHIFT (12U)
+#define USB_LPM_BESL_MAX_MASK (0xf << USB_LPM_BESL_MAX_SHIFT)
+#define USB_LPM_BESL_MIN_SHIFT (16U)
+#define USB_LPM_BESL_MIN_MASK (0xf << USB_LPM_BESL_MIN_SHIFT)
+#define USB_LPM_BESL_SHIFT (20U)
+#define USB_LPM_BESL_MASK (0xf << USB_LPM_BESL_SHIFT)
+#define USB_LPM_EN (1 << 25U)
+#define USB_LPM_ACCEPT (1 << 26U)
+
+/* 0x104 : DEV_ADR */
+#define USB_DEVADR_SHIFT (0U)
+#define USB_DEVADR_MASK (0x7f << USB_DEVADR_SHIFT)
+#define USB_AFT_CONF (1 << 7U)
+
+/* 0x108 : DEV_TST */
+#define USB_TST_CLRFF_HOV (1 << 0U)
+#define USB_TST_LPCX (1 << 1U)
+#define USB_TST_CLREA (1 << 2U)
+#define USB_TST_DISTO_HOV (1 << 4U)
+#define USB_TST_MOD_HOV (1 << 5U)
+#define USB_DISGENSOF (1 << 6U)
+#define USB_TST_MOD_TYP_HOV (1 << 7U)
+
+/* 0x10C : DEV_SFN */
+#define USB_SOFN_SHIFT (0U)
+#define USB_SOFN_MASK (0x7ff << USB_SOFN_SHIFT)
+#define USB_USOFN_SHIFT (11U)
+#define USB_USOFN_MASK (0x7 << USB_USOFN_SHIFT)
+
+/* 0x110 : DEV_SMT */
+#define USB_SOFMT_SHIFT (0U)
+#define USB_SOFMT_MASK (0xffff << USB_SOFMT_SHIFT)
+
+/* 0x114 : PHY_TST */
+#define USB_UNPLUG (1 << 0U)
+#define USB_TST_JSTA (1 << 1U)
+#define USB_TST_KSTA (1 << 2U)
+#define USB_TST_SE0NAK (1 << 3U)
+#define USB_TST_PKT (1 << 4U)
+
+/* 0x11C : DEV_CXCFG */
+#define USB_VSTA_HOV_SHIFT (0U)
+#define USB_VSTA_HOV_MASK (0xff << USB_VSTA_HOV_SHIFT)
+
+/* 0x120 : DEV_CXCFE */
+#define USB_CX_DONE (1 << 0U)
+#define USB_TST_PKDONE (1 << 1U)
+#define USB_CX_STL (1 << 2U)
+#define USB_CX_CLR (1 << 3U)
+#define USB_CX_FUL (1 << 4U)
+#define USB_CX_EMP (1 << 5U)
+#define USB_F0_EMP (1 << 8U)
+#define USB_F1_EMP (1 << 9U)
+#define USB_F2_EMP (1 << 10U)
+#define USB_F3_EMP (1 << 11U)
+
+/* 0x124 : DEV_ICR */
+#define USB_IDLE_CNT_SHIFT (0U)
+#define USB_IDLE_CNT_MASK (0x7 << USB_IDLE_CNT_SHIFT)
+
+/* 0x130 : DEV_MIGR */
+#define USB_MINT_G0 (1 << 0U)
+#define USB_MINT_G1 (1 << 1U)
+#define USB_MINT_G2 (1 << 2U)
+#define USB_MINT_G3 (1 << 3U)
+#define USB_MINT_G4 (1 << 4U)
+
+/* 0x134 : DEV_MISG0 */
+#define USB_MCX_SETUP_INT (1 << 0U)
+#define USB_MCX_IN_INT (1 << 1U)
+#define USB_MCX_OUT_INT (1 << 2U)
+#define USB_MCX_COMFAIL_INT (1 << 4U)
+#define USB_MCX_COMABORT_INT (1 << 5U)
+
+/* 0x138 : DEV_MISG1 */
+#define USB_MF0_OUT_INT (1 << 0U)
+#define USB_MF0_SPK_INT (1 << 1U)
+#define USB_MF1_OUT_INT (1 << 2U)
+#define USB_MF1_SPK_INT (1 << 3U)
+#define USB_MF2_OUT_INT (1 << 4U)
+#define USB_MF2_SPK_INT (1 << 5U)
+#define USB_MF3_OUT_INT (1 << 6U)
+#define USB_MF3_SPK_INT (1 << 7U)
+#define USB_MF0_IN_INT (1 << 16U)
+#define USB_MF1_IN_INT (1 << 17U)
+#define USB_MF2_IN_INT (1 << 18U)
+#define USB_MF3_IN_INT (1 << 19U)
+
+/* 0x13C : DEV_MISG2 */
+#define USB_MUSBRST_INT (1 << 0U)
+#define USB_MSUSP_INT (1 << 1U)
+#define USB_MRESM_INT (1 << 2U)
+#define USB_MSEQ_ERR_INT (1 << 3U)
+#define USB_MSEQ_ABORT_INT (1 << 4U)
+#define USB_MTX0BYTE_INT (1 << 5U)
+#define USB_MRX0BYTE_INT (1 << 6U)
+#define USB_MDMA_CMPLT_HOV (1 << 7U)
+#define USB_MDMA_ERROR_HOV (1 << 8U)
+#define USB_MDEV_IDLE_HOV (1 << 9U)
+#define USB_MDEV_WAKEUP_BYVBUS (1 << 10U)
+
+/* 0x140 : DEV_IGR */
+#define USB_INT_G0 (1 << 0U)
+#define USB_INT_G1 (1 << 1U)
+#define USB_INT_G2 (1 << 2U)
+#define USB_INT_G3 (1 << 3U)
+#define USB_INT_G4 (1 << 4U)
+
+/* 0x144 : DEV_ISG0 */
+#define USB_CX_SETUP_INT (1 << 0U)
+#define USB_CX_IN_INT (1 << 1U)
+#define USB_CX_OUT_INT (1 << 2U)
+#define USB_CX_COMFAIL_INT (1 << 4U)
+#define USB_CX_COMABT_INT (1 << 5U)
+
+/* 0x148 : DEV_ISG1 */
+#define USB_F0_OUT_INT (1 << 0U)
+#define USB_F0_SPK_INT (1 << 1U)
+#define USB_F1_OUT_INT (1 << 2U)
+#define USB_F1_SPK_INT (1 << 3U)
+#define USB_F2_OUT_INT (1 << 4U)
+#define USB_F2_SPK_INT (1 << 5U)
+#define USB_F3_OUT_INT (1 << 6U)
+#define USB_F3_SPK_INT (1 << 7U)
+#define USB_F0_IN_INT (1 << 16U)
+#define USB_F1_IN_INT (1 << 17U)
+#define USB_F2_IN_INT (1 << 18U)
+#define USB_F3_IN_INT (1 << 19U)
+
+/* 0x14C : DEV_ISG2 */
+#define USBRST_INT (1 << 0U)
+#define USB_SUSP_INT (1 << 1U)
+#define USB_RESM_INT (1 << 2U)
+#define USB_ISO_SEQ_ERR_INT (1 << 3U)
+#define USB_ISO_SEQ_ABORT_INT (1 << 4U)
+#define USB_TX0BYTE_INT (1 << 5U)
+#define USB_RX0BYTE_INT (1 << 6U)
+#define USB_DMA_CMPLT_HOV (1 << 7U)
+#define USB_DMA_ERROR_HOV (1 << 8U)
+#define USB_DEV_IDLE_HOV (1 << 9U)
+#define USB_DEV_WAKEUP_BYVBUS (1 << 10U)
+
+/* 0x150 : DEV_RXZ */
+#define USB_RX0BYTE_EP1 (1 << 0U)
+#define USB_RX0BYTE_EP2 (1 << 1U)
+#define USB_RX0BYTE_EP3 (1 << 2U)
+#define USB_RX0BYTE_EP4 (1 << 3U)
+
+/* 0x154 : DEV_TXZ */
+#define USB_TX0BYTE_EP1 (1 << 0U)
+#define USB_TX0BYTE_EP2 (1 << 1U)
+#define USB_TX0BYTE_EP3 (1 << 2U)
+#define USB_TX0BYTE_EP4 (1 << 3U)
+
+/* 0x158 : DEV_ISE */
+#define USB_ISO_ABT_ERR_EP1 (1 << 0U)
+#define USB_ISO_ABT_ERR_EP2 (1 << 1U)
+#define USB_ISO_ABT_ERR_EP3 (1 << 2U)
+#define USB_ISO_ABT_ERR_EP4 (1 << 3U)
+#define USB_ISO_SEQ_ERR_EP1 (1 << 16U)
+#define USB_ISO_SEQ_ERR_EP2 (1 << 17U)
+#define USB_ISO_SEQ_ERR_EP3 (1 << 18U)
+#define USB_ISO_SEQ_ERR_EP4 (1 << 19U)
+
+/* 0x160 : DEV_INMPS1 */
+#define USB_MAXPS_IEP1_SHIFT (0U)
+#define USB_MAXPS_IEP1_MASK (0x7ff << USB_MAXPS_IEP1_SHIFT)
+#define USB_STL_IEP1 (1 << 11U)
+#define USB_RSTG_IEP1 (1 << 12U)
+#define USB_TX_NUM_HBW_IEP1_SHIFT (13U)
+#define USB_TX_NUM_HBW_IEP1_MASK (0x3 << USB_TX_NUM_HBW_IEP1_SHIFT)
+#define USB_TX0BYTE_IEP1 (1 << 15U)
+
+/* 0x164 : DEV_INMPS2 */
+/* 0x168 : DEV_INMPS3 */
+/* 0x16C : DEV_INMPS4 */
+/* 0x170 : DEV_INMPS5 */
+/* 0x174 : DEV_INMPS6 */
+/* 0x178 : DEV_INMPS7 */
+/* 0x17C : DEV_INMPS8 */
+
+/* 0x180 : DEV_OUTMPS1 */
+#define USB_MAXPS_OEP1_SHIFT (0U)
+#define USB_MAXPS_OEP1_MASK (0x7ff << USB_MAXPS_OEP1_SHIFT)
+#define USB_STL_OEP1 (1 << 11U)
+#define USB_RSTG_OEP1 (1 << 12U)
+
+/* 0x184 : DEV_OUTMPS2 */
+/* 0x188 : DEV_OUTMPS3 */
+/* 0x18C : DEV_OUTMPS4 */
+/* 0x190 : DEV_OUTMPS5 */
+/* 0x194 : DEV_OUTMPS6 */
+/* 0x198 : DEV_OUTMPS7 */
+/* 0x19C : DEV_OUTMPS8 */
+
+/* 0x1A0 : DEV_EPMAP0 */
+#define USB_FNO_IEP1_SHIFT (0U)
+#define USB_FNO_IEP1_MASK (0xf << USB_FNO_IEP1_SHIFT)
+#define USB_FNO_OEP1_SHIFT (4U)
+#define USB_FNO_OEP1_MASK (0xf << USB_FNO_OEP1_SHIFT)
+#define USB_FNO_IEP2_SHIFT (8U)
+#define USB_FNO_IEP2_MASK (0xf << USB_FNO_IEP2_SHIFT)
+#define USB_FNO_OEP2_SHIFT (12U)
+#define USB_FNO_OEP2_MASK (0xf << USB_FNO_OEP2_SHIFT)
+#define USB_FNO_IEP3_SHIFT (16U)
+#define USB_FNO_IEP3_MASK (0xf << USB_FNO_IEP3_SHIFT)
+#define USB_FNO_OEP3_SHIFT (20U)
+#define USB_FNO_OEP3_MASK (0xf << USB_FNO_OEP3_SHIFT)
+#define USB_FNO_IEP4_SHIFT (24U)
+#define USB_FNO_IEP4_MASK (0xf << USB_FNO_IEP4_SHIFT)
+#define USB_FNO_OEP4_SHIFT (28U)
+#define USB_FNO_OEP4_MASK (0xf << USB_FNO_OEP4_SHIFT)
+
+/* 0x1A4 : DEV_EPMAP1 */
+
+/* 0x1A8 : DEV_FMAP */
+#define USB_EPNO_FIFO0_SHIFT (0U)
+#define USB_EPNO_FIFO0_MASK (0xf << USB_EPNO_FIFO0_SHIFT)
+#define USB_DIR_FIFO0_SHIFT (4U)
+#define USB_DIR_FIFO0_MASK (0x3 << USB_DIR_FIFO0_SHIFT)
+#define USB_EPNO_FIFO1_SHIFT (8U)
+#define USB_EPNO_FIFO1_MASK (0xf << USB_EPNO_FIFO1_SHIFT)
+#define USB_DIR_FIFO1_SHIFT (12U)
+#define USB_DIR_FIFO1_MASK (0x3 << USB_DIR_FIFO1_SHIFT)
+#define USB_EPNO_FIFO2_SHIFT (16U)
+#define USB_EPNO_FIFO2_MASK (0xf << USB_EPNO_FIFO2_SHIFT)
+#define USB_DIR_FIFO2_SHIFT (20U)
+#define USB_DIR_FIFO2_MASK (0x3 << USB_DIR_FIFO2_SHIFT)
+#define USB_EPNO_FIFO3_SHIFT (24U)
+#define USB_EPNO_FIFO3_MASK (0xf << USB_EPNO_FIFO3_SHIFT)
+#define USB_DIR_FIFO3_SHIFT (28U)
+#define USB_DIR_FIFO3_MASK (0x3 << USB_DIR_FIFO3_SHIFT)
+
+/* 0x1AC : DEV_FCFG */
+#define USB_BLK_TYP_F0_SHIFT (0U)
+#define USB_BLK_TYP_F0_MASK (0x3 << USB_BLK_TYP_F0_SHIFT)
+#define USB_BLKNO_F0_SHIFT (2U)
+#define USB_BLKNO_F0_MASK (0x3 << USB_BLKNO_F0_SHIFT)
+#define USB_BLKSZ_F0 (1 << 4U)
+#define USB_EN_F0 (1 << 5U)
+#define USB_BLK_TYP_F1_SHIFT (8U)
+#define USB_BLK_TYP_F1_MASK (0x3 << USB_BLK_TYP_F1_SHIFT)
+#define USB_BLKNO_F1_SHIFT (10U)
+#define USB_BLKNO_F1_MASK (0x3 << USB_BLKNO_F1_SHIFT)
+#define USB_BLKSZ_F1 (1 << 12U)
+#define USB_EN_F1 (1 << 13U)
+#define USB_BLK_TYP_F2_SHIFT (16U)
+#define USB_BLK_TYP_F2_MASK (0x3 << USB_BLK_TYP_F2_SHIFT)
+#define USB_BLKNO_F2_SHIFT (18U)
+#define USB_BLKNO_F2_MASK (0x3 << USB_BLKNO_F2_SHIFT)
+#define USB_BLKSZ_F2 (1 << 20U)
+#define USB_EN_F2 (1 << 21U)
+#define USB_BLK_TYP_F3_SHIFT (24U)
+#define USB_BLK_TYP_F3_MASK (0x3 << USB_BLK_TYP_F3_SHIFT)
+#define USB_BLKNO_F3_SHIFT (26U)
+#define USB_BLKNO_F3_MASK (0x3 << USB_BLKNO_F3_SHIFT)
+#define USB_BLKSZ_F3 (1 << 28U)
+#define USB_EN_F3 (1 << 29U)
+
+/* 0x1B0 : DEV_FIBC0 */
+#define USB_BC_F0_SHIFT (0U)
+#define USB_BC_F0_MASK (0x7ff << USB_BC_F0_SHIFT)
+#define USB_FFRST0_HOV (1 << 12U)
+
+/* 0x1B4 : DEV_FIBC1 */
+/* 0x1B8 : DEV_FIBC2 */
+/* 0x1BC : DEV_FIBC3 */
+
+/* 0x1C0 : DMA_TFN */
+#define USB_ACC_F0_HOV (1 << 0U)
+#define USB_ACC_F1_HOV (1 << 1U)
+#define USB_ACC_F2_HOV (1 << 2U)
+#define USB_ACC_F3_HOV (1 << 3U)
+#define USB_ACC_CXF_HOV (1 << 4U)
+
+/* 0x1C4 : DMA_CPS0 */
+#define USB_AWCHACHE_HOV_SHIFT (0U)
+#define USB_AWCHACHE_HOV_MASK (0xf << USB_AWCHACHE_HOV_SHIFT)
+#define USB_AWPORT_HOV_SHIFT (4U)
+#define USB_AWPORT_HOV_MASK (0x7 << USB_AWPORT_HOV_SHIFT)
+#define USB_AWLOCK_HOV_SHIFT (7U)
+#define USB_AWLOCK_HOV_MASK (0x3 << USB_AWLOCK_HOV_SHIFT)
+#define USB_ARCACHE_HOV_SHIFT (9U)
+#define USB_ARCACHE_HOV_MASK (0xf << USB_ARCACHE_HOV_SHIFT)
+#define USB_ARPORT_HOV_SHIFT (13U)
+#define USB_ARPORT_HOV_MASK (0x7 << USB_ARPORT_HOV_SHIFT)
+#define USB_ARLOCK_HOV_SHIFT (16U)
+#define USB_ARLOCK_HOV_MASK (0x3 << USB_ARLOCK_HOV_SHIFT)
+#define USB_BUF_LD_EN_HOV (1 << 18U)
+#define USB_DST_WD_HOV (1 << 19U)
+
+/* 0x1C8 : DMA_CPS1 */
+#define USB_DMA_START_HOV (1 << 0U)
+#define USB_DMA_TYPE_HOV (1 << 1U)
+#define USB_DMA_IO_HOV (1 << 2U)
+#define USB_DMA_ABORT_HOV (1 << 3U)
+#define USB_CLRFIFO_DMAABORT_HOV (1 << 4U)
+#define USB_DMA_LEN_HOV_SHIFT (8U)
+#define USB_DMA_LEN_HOV_MASK (0x1ffff << USB_DMA_LEN_HOV_SHIFT)
+#define USB_R_HPORT_HOV_SHIFT (25U)
+#define USB_R_HPORT_HOV_MASK (0xf << USB_R_HPORT_HOV_SHIFT)
+#define USB_UNDEF_LEN_BURST_HOV (1 << 29U)
+#define USB_L1_WAKEUP (1 << 30U)
+#define USB_DEVPHY_SUSPEND_HOV (1 << 31U)
+
+/* 0x1CC : DMA_CPS2 */
+#define USB_DMA_MADDR_HOV_SHIFT (0U)
+#define USB_DMA_MADDR_HOV_MASK (0xffffffff << USB_DMA_MADDR_HOV_SHIFT)
+
+/* 0x1D0 : DMA_CPS3 */
+#define USB_SETUP_CMD_RPORT_SHIFT (0U)
+#define USB_SETUP_CMD_RPORT_MASK (0xffffffff << USB_SETUP_CMD_RPORT_SHIFT)
+
+/* 0x1D4 : DMA_CPS4 */
+/* 0x1D8 : DEV_FMAP2 */
+/* 0x1DC : DEV_FCFG2 */
+/* 0x1E0 : DEV_FMAP3 */
+/* 0x1E4 : DEV_FCFG3 */
+/* 0x1E8 : DEV_FMAP4 */
+/* 0x1EC : DEV_FCFG4 */
+/* 0x1F0 : DEV_FIBC4 */
+/* 0x1F4 : DEV_FIBC5 */
+/* 0x1F8 : DEV_FIBC6 */
+/* 0x1FC : DEV_FIBC7 */
+
+/* 0x300 : VDMA_CXFPS1 */
+#define USB_VDMA_START_CXF (1 << 0U)
+#define USB_VDMA_TYPE_CXF (1 << 1U)
+#define USB_VDMA_IO_CXF (1 << 2U)
+#define USB_VDMA_LEN_CXF_SHIFT (8U)
+#define USB_VDMA_LEN_CXF_MASK (0x1ffff << USB_VDMA_LEN_CXF_SHIFT)
+
+/* 0x304 : VDMA_CXFPS2 */
+#define USB_VDMA_MADDR_CXF_SHIFT (8U)
+#define USB_VDMA_MADDR_CXF_MASK (0x1ffff << USB_VDMA_MADDR_CXF_SHIFT)
+
+/* 0x308 : VDMA_F0PS1 */
+#define USB_VDMA_START_F0 (1 << 0U)
+#define USB_VDMA_TYPE_F0 (1 << 1U)
+#define USB_VDMA_IO_F0 (1 << 2U)
+#define USB_VDMA_LEN_F0_SHIFT (8U)
+#define USB_VDMA_LEN_F0_MASK (0x1ffff << USB_VDMA_LEN_F0_SHIFT)
+
+/* 0x30c : VDMA_F0PS2 */
+#define USB_VDMA_MADDR_F0_SHIFT (8U)
+#define USB_VDMA_MADDR_F0_MASK (0x1ffff << USB_VDMA_MADDR_F0_SHIFT)
+
+/* 0x310 : VDMA_F1PS1 */
+/* 0x314 : VDMA_F1PS2 */
+/* 0x318 : VDMA_F2PS1 */
+/* 0x31C : VDMA_F2PS2 */
+/* 0x320 : VDMA_F3PS1 */
+/* 0x324 : VDMA_F3PS2 */
+
+/* 0x328 : DEV_ISG3 */
+#define USB_VDMA_CMPLT_CXF (1 << 0U)
+#define USB_VDMA_CMPLT_F0 (1 << 1U)
+#define USB_VDMA_CMPLT_F1 (1 << 2U)
+#define USB_VDMA_CMPLT_F2 (1 << 3U)
+#define USB_VDMA_CMPLT_F3 (1 << 4U)
+#define USB_VDMA_ERROR_CXF (1 << 16U)
+#define USB_VDMA_ERROR_F0 (1 << 17U)
+#define USB_VDMA_ERROR_F1 (1 << 18U)
+#define USB_VDMA_ERROR_F2 (1 << 19U)
+#define USB_VDMA_ERROR_F3 (1 << 20U)
+
+/* 0x32C : DEV_MISG3 */
+#define USB_MVDMA_CMPLT_CXF (1 << 0U)
+#define USB_MVDMA_CMPLT_F0 (1 << 1U)
+#define USB_MVDMA_CMPLT_F1 (1 << 2U)
+#define USB_MVDMA_CMPLT_F2 (1 << 3U)
+#define USB_MVDMA_CMPLT_F3 (1 << 4U)
+#define USB_MVDMA_ERROR_CXF (1 << 16U)
+#define USB_MVDMA_ERROR_F0 (1 << 17U)
+#define USB_MVDMA_ERROR_F1 (1 << 18U)
+#define USB_MVDMA_ERROR_F2 (1 << 19U)
+#define USB_MVDMA_ERROR_F3 (1 << 20U)
+
+/* 0x330 : VDMA_CTRL */
+#define USB_VDMA_EN (1 << 0U)
+
+/* 0x334 : LPM_CAP */
+#define USB_LPM_WAKEUP_EN (1 << 0U)
+
+/* 0x338 : DEV_ISG4 */
+#define USB_L1_INT (1 << 0U)
+
+/* 0x33C : DEV_MISG4 */
+#define USB_ML1_INT (1 << 0U)
+
+/* 0x350 : VDMA_FnPS1 */
+/* 0x354 : VDMA_FnPS2 */
+
+#endif /* __HARDWARE_USB_V2_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_adc.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_adc.c
new file mode 100644
index 00000000..2d231c79
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_adc.c
@@ -0,0 +1,646 @@
+#include "bflb_adc.h"
+#include "bflb_efuse.h"
+#include "hardware/adc_reg.h"
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define ADC_GPIP_BASE ((uint32_t)0x40002000)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define ADC_GPIP_BASE ((uint32_t)0x20002000)
+#endif
+
+volatile float coe = 1.0;
+volatile uint32_t tsen_offset;
+
+void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *config)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ /* adc disable */
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_GLOBAL_EN;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval |= AON_GPADC_GLOBAL_EN;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ /* adc reset */
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval |= AON_GPADC_SOFT_RST;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_SOFT_RST;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ /* disable int and clear status */
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval |= (GPIP_GPADC_FIFO_UNDERRUN_MASK | GPIP_GPADC_FIFO_OVERRUN_MASK | GPIP_GPADC_RDY_MASK |
+ GPIP_GPADC_FIFO_UNDERRUN_CLR | GPIP_GPADC_FIFO_OVERRUN_CLR | GPIP_GPADC_RDY_CLR);
+
+#if defined(BL702) || defined(BL702L)
+ regval |= (GPIP_GPADC_FIFO_RDY_MASK | GPIP_GPADC_FIFO_RDY);
+#endif
+ regval |= GPIP_GPADC_FIFO_CLR;
+ regval &= ~GPIP_GPADC_FIFO_THL_MASK;
+ regval &= ~GPIP_GPADC_DMA_EN;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ bflb_adc_start_conversion(dev);
+ bflb_mtimer_delay_ms(1);
+ bflb_adc_stop_conversion(dev);
+
+ regval = 0;
+ regval |= (2 << AON_GPADC_V18_SEL_SHIFT); /* V18 select 1.82V */
+ regval |= (1 << AON_GPADC_V11_SEL_SHIFT); /* V11 select 1.1V */
+ regval |= (config->clk_div << AON_GPADC_CLK_DIV_RATIO_SHIFT); /* clock div */
+ regval |= (config->resolution << AON_GPADC_RES_SEL_SHIFT); /* resolution */
+ if (config->scan_conv_mode) {
+ regval |= AON_GPADC_SCAN_EN;
+ regval |= AON_GPADC_CLK_ANA_INV;
+ }
+ if (config->continuous_conv_mode) {
+ regval |= AON_GPADC_CONT_CONV_EN;
+ }
+
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ regval = 0;
+ regval |= (2 << AON_GPADC_DLY_SEL_SHIFT);
+ regval |= (2 << AON_GPADC_CHOP_MODE_SHIFT); /* Vref AZ and PGA chop on */
+ regval |= (1 << AON_GPADC_PGA1_GAIN_SHIFT); /* gain 1 */
+ regval |= (1 << AON_GPADC_PGA2_GAIN_SHIFT); /* gain 1 */
+ regval |= AON_GPADC_PGA_EN;
+ regval |= (8 << AON_GPADC_PGA_OS_CAL_SHIFT);
+ regval |= (1 << AON_GPADC_PGA_VCM_SHIFT); /* PGA output common mode control 1.4V */
+
+ if (config->vref == ADC_VREF_2P0V) {
+ regval |= AON_GPADC_VREF_SEL;
+ }
+
+ if (config->differential_mode) {
+ regval |= AON_GPADC_DIFF_MODE;
+ }
+
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval |= AON_GPADC_MIC2_DIFF; /* mic2 diff enable */
+ if (config->differential_mode) {
+ regval &= ~AON_GPADC_NEG_GND;
+ } else {
+ regval |= AON_GPADC_NEG_GND;
+ }
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ /* calibration offset */
+ regval = getreg32(reg_base + AON_GPADC_REG_DEFINE_OFFSET);
+ regval &= ~AON_GPADC_OS_CAL_DATA_MASK;
+ putreg32(regval, reg_base + AON_GPADC_REG_DEFINE_OFFSET);
+
+ /* disable int and clear status */
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval |= (GPIP_GPADC_FIFO_UNDERRUN_MASK | GPIP_GPADC_FIFO_OVERRUN_MASK | GPIP_GPADC_RDY_MASK |
+ GPIP_GPADC_FIFO_UNDERRUN_CLR | GPIP_GPADC_FIFO_OVERRUN_CLR | GPIP_GPADC_RDY_CLR);
+
+#if defined(BL702) || defined(BL702L)
+ regval |= (GPIP_GPADC_FIFO_RDY_MASK | GPIP_GPADC_FIFO_RDY);
+#endif
+ regval |= GPIP_GPADC_FIFO_CLR;
+ regval &= ~GPIP_GPADC_FIFO_THL_MASK;
+ regval &= ~GPIP_GPADC_DMA_EN;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval &= ~(GPIP_GPADC_FIFO_UNDERRUN_CLR |
+ GPIP_GPADC_FIFO_OVERRUN_CLR |
+ GPIP_GPADC_RDY_CLR |
+ GPIP_GPADC_FIFO_CLR);
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval |= AON_GPADC_NEG_SATUR_MASK;
+ regval |= AON_GPADC_POS_SATUR_MASK;
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+ coe = bflb_efuse_get_adc_trim(); /* read from efuse */
+ tsen_offset = bflb_efuse_get_adc_tsen_trim(); /* read from efuse */
+}
+
+void bflb_adc_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ /* adc disable */
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_GLOBAL_EN;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ /* adc reset */
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval |= AON_GPADC_SOFT_RST;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_SOFT_RST;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ putreg32(0, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+ putreg32(0, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+}
+
+void bflb_adc_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t regval;
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ if (enable) {
+ regval |= GPIP_GPADC_DMA_EN;
+ } else {
+ regval &= ~GPIP_GPADC_DMA_EN;
+ }
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+}
+
+int bflb_adc_channel_config(struct bflb_device_s *dev, struct bflb_adc_channel_s *chan, uint8_t channels)
+{
+ uint32_t regval;
+ uint32_t regval2;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ if (!(getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET) & AON_GPADC_SCAN_EN)) {
+ if (channels > 1) {
+ return -EINVAL;
+ }
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_POS_SEL_MASK;
+ regval &= ~AON_GPADC_NEG_SEL_MASK;
+ regval |= (chan->pos_chan << AON_GPADC_POS_SEL_SHIFT);
+ regval |= (chan->neg_chan << AON_GPADC_NEG_SEL_SHIFT);
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+ } else {
+ if (channels < 6) {
+ regval = 0;
+ regval2 = 0;
+ for (uint8_t i = 0; i < channels; i++) {
+ regval |= (chan[i].pos_chan << (i * 5));
+ regval2 |= (chan[i].neg_chan << (i * 5));
+ }
+ putreg32(regval, reg_base + AON_GPADC_REG_SCN_POS1_OFFSET);
+ putreg32(regval2, reg_base + AON_GPADC_REG_SCN_NEG1_OFFSET);
+ } else {
+ regval = 0;
+ regval2 = 0;
+ for (uint8_t i = 0; i < 6; i++) {
+ regval |= (chan[i].pos_chan << (i * 5));
+ regval2 |= (chan[i].neg_chan << (i * 5));
+ }
+ putreg32(regval, reg_base + AON_GPADC_REG_SCN_POS1_OFFSET);
+ putreg32(regval2, reg_base + AON_GPADC_REG_SCN_NEG1_OFFSET);
+
+ regval = 0;
+ regval2 = 0;
+ for (uint8_t i = 0; i < (channels - 6); i++) {
+ regval |= (chan[i + 6].pos_chan << (i * 5));
+ regval2 |= (chan[i + 6].neg_chan << (i * 5));
+ }
+ putreg32(regval, reg_base + AON_GPADC_REG_SCN_POS2_OFFSET);
+ putreg32(regval2, reg_base + AON_GPADC_REG_SCN_NEG2_OFFSET);
+ }
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+ regval &= ~AON_GPADC_SCAN_LENGTH_MASK;
+ regval |= ((channels - 1) << AON_GPADC_SCAN_LENGTH_SHIFT);
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+ }
+ return 0;
+}
+
+void bflb_adc_start_conversion(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_CONV_START;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ bflb_mtimer_delay_us(100);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval |= AON_GPADC_CONV_START;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+}
+
+void bflb_adc_stop_conversion(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_CONV_START;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+}
+
+uint8_t bflb_adc_get_count(struct bflb_device_s *dev)
+{
+ return ((getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_FIFO_DATA_COUNT_MASK) >> GPIP_GPADC_FIFO_DATA_COUNT_SHIFT);
+}
+
+uint32_t bflb_adc_read_raw(struct bflb_device_s *dev)
+{
+ return getreg32(ADC_GPIP_BASE + GPIP_GPADC_DMA_RDATA_OFFSET) & GPIP_GPADC_DMA_RDATA_MASK;
+}
+
+void bflb_adc_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ if (mask) {
+ regval |= GPIP_GPADC_RDY_MASK;
+ } else {
+ regval &= ~GPIP_GPADC_RDY_MASK;
+ }
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+}
+
+void bflb_adc_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t regval2;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval2 = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ if (mask) {
+ regval |= AON_GPADC_POS_SATUR_MASK;
+ regval |= AON_GPADC_NEG_SATUR_MASK;
+ regval2 |= GPIP_GPADC_FIFO_UNDERRUN_MASK;
+ regval2 |= GPIP_GPADC_FIFO_OVERRUN_MASK;
+ } else {
+ regval &= ~AON_GPADC_POS_SATUR_MASK;
+ regval &= ~AON_GPADC_NEG_SATUR_MASK;
+ regval2 &= ~GPIP_GPADC_FIFO_UNDERRUN_MASK;
+ regval2 &= ~GPIP_GPADC_FIFO_OVERRUN_MASK;
+ }
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+ putreg32(regval2, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+}
+
+uint32_t bflb_adc_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval = 0;
+
+ reg_base = dev->reg_base;
+
+ if (getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET) & AON_GPADC_NEG_SATUR) {
+ regval |= ADC_INTSTS_NEG_SATURATION;
+ }
+ if (getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET) & AON_GPADC_POS_SATUR) {
+ regval |= ADC_INTSTS_POS_SATURATION;
+ }
+ if (getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_FIFO_UNDERRUN) {
+ regval |= ADC_INTSTS_FIFO_UNDERRUN;
+ }
+ if (getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_FIFO_OVERRUN) {
+ regval |= ADC_INTSTS_FIFO_OVERRUN;
+ }
+ if (getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_RDY) {
+ regval |= ADC_INTSTS_ADC_READY;
+ }
+ return regval;
+}
+
+void bflb_adc_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ if (int_clear & ADC_INTCLR_NEG_SATURATION) {
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval &= ~AON_GPADC_NEG_SATUR_CLR;
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval |= AON_GPADC_NEG_SATUR_CLR;
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval &= ~AON_GPADC_NEG_SATUR_CLR;
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+ }
+ if (int_clear & ADC_INTCLR_POS_SATURATION) {
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval &= ~AON_GPADC_POS_SATUR_CLR;
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval |= AON_GPADC_POS_SATUR_CLR;
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+ regval &= ~AON_GPADC_POS_SATUR_CLR;
+ putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+ }
+ if (int_clear & ADC_INTCLR_FIFO_UNDERRUN) {
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval &= ~GPIP_GPADC_FIFO_UNDERRUN_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval |= GPIP_GPADC_FIFO_UNDERRUN_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval &= ~GPIP_GPADC_FIFO_UNDERRUN_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ }
+ if (int_clear & ADC_INTCLR_FIFO_OVERRUN) {
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval &= ~GPIP_GPADC_FIFO_OVERRUN_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval |= GPIP_GPADC_FIFO_OVERRUN_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval &= ~GPIP_GPADC_FIFO_OVERRUN_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ }
+ if (int_clear & ADC_INTCLR_ADC_READY) {
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval &= ~GPIP_GPADC_RDY_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval |= GPIP_GPADC_RDY_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval &= ~GPIP_GPADC_RDY_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ }
+}
+
+void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct bflb_adc_result_s *result, uint16_t count)
+{
+ uint32_t reg_base;
+ uint8_t resolution;
+ uint8_t diff_mode;
+ uint8_t vref;
+ uint32_t conv_result = 0;
+ uint16_t ref = 3200;
+ uint8_t neg = 0;
+ uint32_t tmp;
+
+ reg_base = dev->reg_base;
+
+ resolution = (getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET) & AON_GPADC_RES_SEL_MASK) >> AON_GPADC_RES_SEL_SHIFT;
+ diff_mode = (getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET) & AON_GPADC_DIFF_MODE) >> 2;
+ vref = (getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET) & AON_GPADC_VREF_SEL) >> 3;
+
+ if (vref == ADC_VREF_2P0V) {
+ ref = 2000;
+ }
+
+ /* single mode */
+ if (diff_mode == 0) {
+ for (uint16_t i = 0; i < count; i++) {
+ result[i].pos_chan = buffer[i] >> 21;
+ result[i].neg_chan = -1;
+
+ if (resolution == ADC_RESOLUTION_12B) {
+ conv_result = (uint32_t)(((buffer[i] & 0xffff) >> 4) / coe);
+ if (conv_result > 4095) {
+ conv_result = 4095;
+ }
+ result[i].value = conv_result;
+ result[i].millivolt = (float)result[i].value / 4096 * ref;
+ } else if (resolution == ADC_RESOLUTION_14B) {
+ conv_result = (uint32_t)(((buffer[i] & 0xffff) >> 2) / coe);
+ if (conv_result > 16383) {
+ conv_result = 16383;
+ }
+ result[i].value = conv_result;
+ result[i].millivolt = (float)result[i].value / 16384 * ref;
+ } else if (resolution == ADC_RESOLUTION_16B) {
+ conv_result = (uint32_t)((buffer[i] & 0xffff) / coe);
+ if (conv_result > 65535) {
+ conv_result = 65535;
+ }
+ result[i].value = conv_result;
+ result[i].millivolt = (int32_t)result[i].value / 65536.0 * ref;
+ } else {
+ }
+ }
+ } else {
+ for (uint16_t i = 0; i < count; i++) {
+ result[i].pos_chan = buffer[i] >> 21;
+ result[i].neg_chan = (buffer[i] >> 16) & 0x1F;
+
+ tmp = buffer[i];
+
+ if (tmp & 0x8000) {
+ tmp = ~tmp;
+ tmp += 1;
+ neg = 1;
+ }
+
+ if (resolution == ADC_RESOLUTION_12B) {
+ conv_result = (uint32_t)(((tmp & 0xffff) >> 4) / coe);
+ if (conv_result > 2047) {
+ conv_result = 2047;
+ }
+ result[i].value = conv_result;
+ result[i].millivolt = (float)result[i].value / 2048 * ref;
+ } else if (resolution == ADC_RESOLUTION_14B) {
+ conv_result = (uint32_t)(((tmp & 0xffff) >> 2) / coe);
+ if (conv_result > 8191) {
+ conv_result = 8191;
+ }
+ result[i].value = conv_result;
+ result[i].millivolt = (float)result[i].value / 8192 * ref;
+ } else if (resolution == ADC_RESOLUTION_16B) {
+ conv_result = (uint32_t)((tmp & 0xffff) / coe);
+ if (conv_result > 32767) {
+ conv_result = 32767;
+ }
+ result[i].value = conv_result;
+ result[i].millivolt = (float)result[i].value / 32768 * ref;
+ } else {
+ }
+
+ if (neg) {
+ result[i].value = -result[i].value;
+ result[i].millivolt = -result[i].millivolt;
+ }
+ }
+ }
+}
+
+void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval &= ~AON_GPADC_SEN_TEST_EN;
+ regval |= (0 << AON_GPADC_SEN_SEL_SHIFT);
+ regval &= ~AON_GPADC_CHIP_SEN_PU;
+ regval |= AON_GPADC_DWA_EN;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+ regval &= ~AON_GPADC_TSVBE_LOW;
+ regval |= (2 << AON_GPADC_DLY_SEL_SHIFT);
+ regval |= (0 << AON_GPADC_TEST_SEL_SHIFT);
+ regval &= ~AON_GPADC_TEST_EN;
+ regval |= AON_GPADC_TS_EN;
+ if (tsen_mod) {
+ regval |= AON_GPADC_TSEXT_SEL;
+ } else {
+ regval &= ~AON_GPADC_TSEXT_SEL;
+ }
+ regval |= (2 << AON_GPADC_PGA_VCM_SHIFT);
+ regval &= ~AON_GPADC_PGA_VCMI_EN;
+ regval |= (0 << AON_GPADC_PGA_OS_CAL_SHIFT);
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+ regval |= AON_GPADC_DITHER_EN;
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+ regval |= AON_GPADC_MIC2_DIFF;
+ putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+}
+
+float bflb_adc_tsen_get_temp(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ struct bflb_adc_result_s result;
+ uint32_t v0 = 0, v1 = 0;
+ float temp = 0;
+ uint32_t raw_data;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval |= (0 << 22);
+ regval |= GPIP_GPADC_FIFO_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+ regval &= ~AON_GPADC_TSVBE_LOW;
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+ bflb_adc_start_conversion(dev);
+ start_time = bflb_mtimer_get_time_ms();
+ while (bflb_adc_get_count(dev) == 0) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ raw_data = bflb_adc_read_raw(dev);
+ bflb_adc_parse_result(dev, &raw_data, &result, 1);
+ v0 = result.value;
+ regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+ regval |= GPIP_GPADC_FIFO_CLR;
+ putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+ regval |= AON_GPADC_TSVBE_LOW;
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+ bflb_adc_start_conversion(dev);
+ start_time = bflb_mtimer_get_time_ms();
+ while (bflb_adc_get_count(dev) == 0) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ raw_data = bflb_adc_read_raw(dev);
+ bflb_adc_parse_result(dev, &raw_data, &result, 1);
+ v1 = result.value;
+ if (v0 > v1) {
+ temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753;
+ } else {
+ temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753;
+ }
+
+ return temp;
+}
+
+void bflb_adc_vbat_enable(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+ regval |= AON_GPADC_VBAT_EN;
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+}
+
+void bflb_adc_vbat_disable(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+ regval &= ~AON_GPADC_VBAT_EN;
+ putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_auadc.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_auadc.c
new file mode 100644
index 00000000..8f813b50
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_auadc.c
@@ -0,0 +1,291 @@
+#include "bflb_auadc.h"
+#include "hardware/auadc_reg.h"
+
+int bflb_auadc_init(struct bflb_device_s *dev, const struct bflb_auadc_init_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AUADC_AUDPDM_TOP_OFFSET);
+ /* enable clk */
+ regval |= AUADC_AUDIO_CKG_EN;
+ /* sampling rate */
+ regval &= ~AUADC_ADC_RATE_MASK;
+ regval |= config->sampling_rate << AUADC_ADC_RATE_SHIFT;
+ putreg32(regval, reg_base + AUADC_AUDPDM_TOP_OFFSET);
+
+ /* disable ch0 and enable dma interface */
+ regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET);
+ regval &= ~AUADC_ADC_0_EN;
+ regval |= AUADC_ADC_ITF_EN;
+ putreg32(regval, reg_base + AUADC_AUDPDM_ITF_OFFSET);
+
+ /* pdm or adc input */
+ regval = getreg32(reg_base + AUADC_PDM_DAC_0_OFFSET);
+ if (config->input_mode == AUADC_INPUT_MODE_ADC) {
+ regval &= ~AUADC_ADC_0_SRC;
+ } else {
+ regval |= AUADC_ADC_0_SRC;
+ }
+ putreg32(regval, reg_base + AUADC_PDM_DAC_0_OFFSET);
+
+ /* pdm cfg */
+ regval = getreg32(reg_base + AUADC_PDM_PDM_0_OFFSET);
+ if (config->input_mode == AUADC_INPUT_MODE_PDM_L || config->input_mode == AUADC_INPUT_MODE_PDM_R) {
+ /* enable pdm */
+ regval |= AUADC_PDM_0_EN;
+ /* pdm_l or pdm_r input */
+ regval &= ~AUADC_ADC_0_PDM_SEL_MASK;
+ if (config->input_mode == AUADC_INPUT_MODE_PDM_L) {
+ regval |= 0 << AUADC_ADC_0_PDM_SEL_SHIFT;
+ } else if (config->input_mode == AUADC_INPUT_MODE_PDM_R) {
+ regval |= 1 << AUADC_ADC_0_PDM_SEL_SHIFT;
+ }
+ } else {
+ /* disable pdm */
+ regval &= ~AUADC_PDM_0_EN;
+ }
+ putreg32(regval, reg_base + AUADC_PDM_PDM_0_OFFSET);
+
+ regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+ /* audio osr configuration */
+ if (config->input_mode != AUADC_INPUT_MODE_ADC && (config->sampling_rate == AUADC_SAMPLING_RATE_32K || config->sampling_rate == AUADC_SAMPLING_RATE_48K)) {
+ /* osr 64 */
+ regval |= AUADC_AUDADC_AUDIO_OSR_SEL;
+ } else {
+ /* osr 128 */
+ regval &= ~AUADC_AUDADC_AUDIO_OSR_SEL;
+ }
+ putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+ /* fifo configuration */
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ /* data format */
+ regval &= ~AUADC_RX_DATA_MODE_MASK;
+ regval |= config->data_format << AUADC_RX_DATA_MODE_SHIFT;
+
+ /* fifo threshold */
+ regval &= ~AUADC_RX_TRG_LEVEL_MASK;
+ regval |= config->fifo_threshold << AUADC_RX_TRG_LEVEL_SHIFT;
+ regval &= ~AUADC_RX_DRQ_CNT_MASK;
+
+ /* disable record */
+ regval &= ~AUADC_RX_CH_EN;
+
+ /* 24bit sample */
+ regval &= ~AUADC_RX_DATA_RES_MASK;
+ regval |= 2 << AUADC_RX_DATA_RES_SHIFT;
+
+ /* disable fifo dma and int */
+ regval &= ~AUADC_RX_DRQ_EN;
+ regval &= ~AUADC_RXA_INT_EN;
+ regval &= ~AUADC_RXU_INT_EN;
+ regval &= ~AUADC_RXO_INT_EN;
+
+ /* clear fifo */
+ regval |= AUADC_RX_FIFO_FLUSH;
+ putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+ /* enable ch0 */
+ regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET);
+ regval |= AUADC_ADC_0_EN;
+ putreg32(regval, reg_base + AUADC_AUDPDM_ITF_OFFSET);
+
+ return 0;
+}
+
+int bflb_auadc_adc_init(struct bflb_device_s *dev, const struct bflb_auadc_adc_init_config_s *adc_analog_cfg)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ if (adc_analog_cfg->auadc_analog_en == false) {
+ /* disable analog and channel */
+ regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+ regval &= ~AUADC_AUDADC_PGA_PU;
+ regval &= ~AUADC_AUDADC_SDM_PU;
+ regval &= ~AUADC_AUDADC_CHANNEL_EN_MASK;
+ putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+ return 0;
+ }
+
+ /* power up, and SDM reset */
+ regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+ regval |= AUADC_AUDADC_PGA_PU;
+ regval |= AUADC_AUDADC_SDM_PU;
+ regval &= ~AUADC_AUDADC_CONV;
+ putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+ /* select analog channel */
+ regval &= ~AUADC_AUDADC_CHANNEL_SELP_MASK;
+ regval &= ~AUADC_AUDADC_CHANNEL_SELN_MASK;
+ regval |= adc_analog_cfg->adc_pga_posi_ch << AUADC_AUDADC_CHANNEL_SELP_SHIFT;
+ regval |= adc_analog_cfg->adc_pga_nega_ch << AUADC_AUDADC_CHANNEL_SELN_SHIFT;
+
+ /* PGA mode */
+ regval &= ~AUADC_AUDADC_PGA_MODE_MASK;
+ regval |= adc_analog_cfg->adc_pga_mode << AUADC_AUDADC_PGA_MODE_SHIFT;
+
+ /* PGA gain */
+ regval &= ~AUADC_AUDADC_PGA_GAIN_MASK;
+ regval |= (adc_analog_cfg->adc_pga_gain / 3) << AUADC_AUDADC_PGA_GAIN_SHIFT;
+
+ /* adc mode */
+ if (adc_analog_cfg->adc_mode == AUADC_ADC_MODE_AUDIO) {
+ regval &= ~AUADC_AUDADC_MEAS_FILTER_EN;
+ } else {
+ regval |= AUADC_AUDADC_MEAS_FILTER_EN;
+ }
+
+ /* measuring mode rate */
+ regval &= ~AUADC_AUDADC_MEAS_ODR_SEL_MASK;
+ regval |= adc_analog_cfg->adc_measure_rate << AUADC_AUDADC_MEAS_ODR_SEL_SHIFT;
+
+ /* enable analog channel */
+ regval &= ~AUADC_AUDADC_CHANNEL_EN_MASK;
+ if (adc_analog_cfg->adc_pga_mode == AUADC_ADC_PGA_MODE_AC_DIFFER || adc_analog_cfg->adc_pga_mode == AUADC_ADC_PGA_MODE_DC_DIFFER) {
+ regval |= 0x03 << AUADC_AUDADC_CHANNEL_EN_SHIFT;
+ } else {
+ regval |= 0x02 << AUADC_AUDADC_CHANNEL_EN_SHIFT;
+ }
+ putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+ /* SDM conversion start */
+ regval |= AUADC_AUDADC_CONV;
+ putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+ return 0;
+}
+
+int bflb_auadc_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ if (enable) {
+ regval |= AUADC_RX_DRQ_EN;
+ } else {
+ regval &= ~AUADC_RX_DRQ_EN;
+ }
+ putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+ return 0;
+}
+
+int bflb_auadc_int_mask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* fifo int */
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ regval &= ~int_sts;
+ putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+ return 0;
+}
+
+int bflb_auadc_int_unmask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* fifo int */
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ regval |= int_sts;
+ putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+ return 0;
+}
+
+int bflb_auadc_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ int32_t int_sts;
+
+ reg_base = dev->reg_base;
+ int_sts = 0;
+
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_STATUS_OFFSET);
+ if (regval & AUADC_RXO_INT) {
+ int_sts |= AUADC_INTSTS_FIFO_OVER;
+ }
+ if (regval & AUADC_RXU_INT) {
+ int_sts |= AUADC_INTSTS_FIFO_UNDER;
+ }
+ if (regval & AUADC_RXA_INT) {
+ int_sts |= AUADC_INTSTS_FIFO_AVAILABLE;
+ }
+
+ return int_sts;
+}
+
+int bflb_auadc_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+ int16_t volume_val;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case AUADC_CMD_RECORD_START:
+ /* record start */
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ regval |= AUADC_RX_CH_EN;
+ putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ break;
+
+ case AUADC_CMD_RECORD_STOP:
+ /* record stop */
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ regval &= ~AUADC_RX_CH_EN;
+ putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ break;
+
+ case AUADC_CMD_SET_VOLUME_VAL:
+ /* set volume value dB, arg range -191 to + 36, 0.5dB step, range -95.5dB to +18dB*/
+ volume_val = (uint16_t)((int16_t)arg * 2);
+ regval = getreg32(reg_base + AUADC_PDM_ADC_S0_OFFSET);
+ regval &= ~AUADC_ADC_S0_VOLUME_MASK;
+ regval |= (volume_val << AUADC_ADC_S0_VOLUME_SHIFT) & AUADC_ADC_S0_VOLUME_MASK;
+ putreg32(regval, reg_base + AUADC_PDM_ADC_S0_OFFSET);
+ break;
+
+ case AUADC_CMD_SET_PGA_GAIN_VAL:
+ /* set adc pga gain, range 6dB ~ 42dB, step by 3db */
+ volume_val = arg / 3;
+ regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+ regval &= ~AUADC_AUDADC_PGA_GAIN_MASK;
+ regval |= (volume_val << AUADC_AUDADC_PGA_GAIN_SHIFT) & AUADC_AUDADC_PGA_GAIN_MASK;
+ putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+ break;
+
+ case AUADC_CMD_CLEAR_RX_FIFO:
+ /* get rx fifo cnt */
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ regval |= AUADC_RX_FIFO_FLUSH;
+ putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+ break;
+
+ case AUADC_CMD_GET_RX_FIFO_CNT:
+ /* get rx fifo cnt */
+ regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_STATUS_OFFSET);
+ ret = (regval & AUADC_RXA_CNT_MASK) >> AUADC_RXA_CNT_SHIFT;
+ }
+
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_audac.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_audac.c
new file mode 100644
index 00000000..75202f4e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_audac.c
@@ -0,0 +1,360 @@
+#include "bflb_audac.h"
+#include "hardware/audac_reg.h"
+#include "hardware/dac_reg.h"
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define GLB_BASE ((uint32_t)0x20000000)
+#endif
+
+static volatile uint32_t g_audac_channel_mode = 0;
+
+int bflb_audac_init(struct bflb_device_s *dev, const struct bflb_audac_init_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* enable clk, enable dma interface, disable ch0 */
+ regval = getreg32(reg_base + AUDAC_0_OFFSET);
+ regval |= AUDAC_CKG_ENA;
+ regval |= AUDAC_DAC_ITF_EN;
+ regval |= AUDAC_DAC_0_EN;
+
+ /* set output mode and sampling rate */
+ regval &= ~AUDAC_AU_PWM_MODE_MASK;
+ if (config->output_mode != AUDAC_OUTPUT_MODE_PWM) {
+ regval |= (config->sampling_rate + 8) << AUDAC_AU_PWM_MODE_SHIFT;
+ } else {
+ regval |= config->sampling_rate << AUDAC_AU_PWM_MODE_SHIFT;
+ }
+ putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+ regval = getreg32(reg_base + AUDAC_1_OFFSET);
+ /* set dsm dither, scaling, and order */
+ regval &= ~AUDAC_DAC_DSM_SCALING_MODE_MASK;
+ regval |= 3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT;
+ regval &= ~AUDAC_DAC_DSM_ORDER_MASK;
+ regval |= 1 << AUDAC_DAC_DSM_ORDER_SHIFT;
+
+ /* set mixer */
+ regval &= ~AUDAC_DAC_MIX_SEL_MASK;
+ if (config->source_channels_num == AUDAC_SOURCE_CHANNEL_DUAL) {
+ regval |= config->mixer_mode << AUDAC_DAC_MIX_SEL_SHIFT;
+ }
+ putreg32(regval, reg_base + AUDAC_1_OFFSET);
+
+ regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ /* data format */
+ regval &= ~AUDAC_TX_DATA_MODE_MASK;
+ regval |= config->data_format;
+
+ /* fifo threshold */
+ regval &= ~AUDAC_TX_TRG_LEVEL_MASK;
+ regval |= (config->fifo_threshold << AUDAC_TX_TRG_LEVEL_SHIFT) & AUDAC_TX_TRG_LEVEL_MASK;
+ regval &= ~AUDAC_TX_DRQ_CNT_MASK;
+
+ /* dma disable */
+ regval &= ~AUDAC_TX_DRQ_EN;
+
+ /* source channels num */
+ regval &= ~AUDAC_TX_CH_EN_MASK;
+ g_audac_channel_mode = config->source_channels_num;
+
+ /* disable fifo int */
+ regval &= ~AUDAC_TXO_INT_EN;
+ regval &= ~AUDAC_TXU_INT_EN;
+ regval &= ~AUDAC_TXA_INT_EN;
+
+ /* clear fifo */
+ regval &= ~AUDAC_TX_FIFO_FLUSH;
+ putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+
+ /* enable zero delete */
+ regval = getreg32(reg_base + AUDAC_ZD_0_OFFSET);
+ regval |= AUDAC_ZD_EN;
+ regval &= ~AUDAC_ZD_TIME_MASK;
+ regval |= 512 << AUDAC_ZD_TIME_SHIFT;
+ putreg32(regval, reg_base + AUDAC_ZD_0_OFFSET);
+
+ /* disable volume interrupt */
+ regval = getreg32(reg_base + AUDAC_STATUS_OFFSET);
+ regval |= AUDAC_DAC_S0_INT_CLR;
+ putreg32(regval, reg_base + AUDAC_STATUS_OFFSET);
+
+ /* gpdac config */
+ reg_base = GLB_BASE;
+ if (config->output_mode != AUDAC_OUTPUT_MODE_PWM) {
+ /* Select Internal reference */
+ regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+ regval |= (GLB_GPDACA_RSTN_ANA | GLB_GPDACB_RSTN_ANA);
+ regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+ regval &= ~GLB_GPDAC_REF_SEL;
+
+ /* Select the clock and data from aupdac */
+ regval |= GLB_GPDAC_ANA_CLK_SEL;
+ if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_A) {
+ regval |= GLB_GPDAC_DAT_CHA_SEL;
+ }
+ if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_B) {
+ regval |= GLB_GPDAC_DAT_CHB_SEL;
+ }
+ putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+ if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_A) {
+ /* gpdac enable ch-A */
+ regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+ regval |= (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+ putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+ }
+
+ if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_B) {
+ /* gpdac enable ch-A */
+ regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET);
+ regval |= (GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN);
+ putreg32(regval, reg_base + GLB_GPDAC_BCTRL_OFFSET);
+ }
+ }
+
+ return 0;
+}
+
+int bflb_audac_volume_init(struct bflb_device_s *dev, const struct bflb_audac_volume_config_s *vol_cfg)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* enable volume update */
+ regval = getreg32(reg_base + AUDAC_S0_OFFSET);
+ regval |= AUDAC_DAC_S0_VOLUME_UPDATE;
+
+ if (vol_cfg->mute_ramp_en) {
+ /* mute ramp mode */
+ regval |= AUDAC_DAC_S0_MUTE_SOFTMODE;
+ regval &= ~AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK;
+ regval |= vol_cfg->mute_down_ramp_rate << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT;
+ regval &= ~AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK;
+ regval |= vol_cfg->mute_up_ramp_rate << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT;
+
+ } else {
+ /* mute directly mode */
+ regval &= ~AUDAC_DAC_S0_MUTE_SOFTMODE;
+ }
+
+ regval &= ~AUDAC_DAC_S0_CTRL_MODE_MASK;
+ if (vol_cfg->volume_update_mode == AUDAC_VOLUME_UPDATE_MODE_RAMP) {
+ /* ramp mode */
+ regval |= 2 << AUDAC_DAC_S0_CTRL_MODE_SHIFT;
+ regval &= ~AUDAC_DAC_S0_CTRL_RMP_RATE_MASK;
+ regval |= vol_cfg->volume_ramp_rate << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT;
+ } else if (vol_cfg->volume_update_mode == AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING) {
+ /* ramp and zero crossing mode */
+ regval |= 1 << AUDAC_DAC_S0_CTRL_MODE_SHIFT;
+ regval &= ~AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK;
+ regval |= vol_cfg->volume_ramp_rate << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT;
+ }
+ putreg32(regval, reg_base + AUDAC_S0_OFFSET);
+
+ return 0;
+}
+
+int bflb_audac_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ if (enable) {
+ regval |= AUDAC_TX_DRQ_EN;
+ } else {
+ regval &= ~AUDAC_TX_DRQ_EN;
+ }
+ putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+
+ return 0;
+}
+
+int bflb_audac_int_mask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ if (int_sts & AUDAC_INTSTS_VOLUME_RAMP) {
+ /* volume ramp done int */
+ regval = getreg32(reg_base + AUDAC_0_OFFSET);
+ regval &= ~(0x01 << 17);
+ putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+ int_sts &= ~AUDAC_INTSTS_VOLUME_RAMP;
+ }
+
+ if (int_sts) {
+ /* fifo int */
+ regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ regval &= ~int_sts;
+ putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ }
+
+ return 0;
+}
+
+int bflb_audac_int_unmask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ if (int_sts & AUDAC_INTSTS_VOLUME_RAMP) {
+ /* volume ramp done int */
+ regval = getreg32(reg_base + AUDAC_0_OFFSET);
+ regval |= (0x01 << 17);
+ putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+ int_sts &= ~AUDAC_INTSTS_VOLUME_RAMP;
+ }
+
+ if (int_sts) {
+ /* fifo int */
+ regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ regval |= int_sts;
+ putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ }
+
+ return 0;
+}
+
+int bflb_audac_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ int32_t int_sts;
+
+ reg_base = dev->reg_base;
+ int_sts = 0;
+
+ /* volume ramp done int */
+ regval = getreg32(reg_base + AUDAC_0_OFFSET);
+ if (regval & (0x01 << 17)) {
+ int_sts |= AUDAC_INTSTS_VOLUME_RAMP;
+ }
+
+ /* fifo int */
+ regval = getreg32(reg_base + AUDAC_FIFO_STATUS_OFFSET);
+ if (regval & AUDAC_TXO_INT) {
+ int_sts |= AUDAC_INTSTS_FIFO_OVER;
+ }
+ if (regval & AUDAC_TXU_INT) {
+ int_sts |= AUDAC_INTSTS_FIFO_UNDER;
+ }
+ if (regval & AUDAC_TXA_INT) {
+ int_sts |= AUDAC_INTSTS_FIFO_AVAILABLE;
+ }
+
+ return int_sts;
+}
+
+int bflb_audac_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint8_t ramp_int_en;
+
+ reg_base = dev->reg_base;
+
+ if (int_clear & AUDAC_INTSTS_VOLUME_RAMP) {
+ /* volume ramp done int */
+ regval = getreg32(reg_base + AUDAC_0_OFFSET);
+
+ if (regval & (0x01 << 17)) {
+ ramp_int_en = 0;
+ } else {
+ ramp_int_en = 1;
+ }
+
+ regval |= (0x01 << 17);
+ putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+ if (ramp_int_en) {
+ regval &= ~(0x01 << 17);
+ }
+ putreg32(regval, reg_base + AUDAC_0_OFFSET);
+ }
+
+ return 0;
+}
+
+int bflb_audac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+ int16_t volume_val;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case AUDAC_CMD_PLAY_START:
+ /* play start */
+ regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ regval &= ~AUDAC_TX_CH_EN_MASK;
+ regval |= g_audac_channel_mode << AUDAC_TX_CH_EN_SHIFT;
+ putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ g_audac_channel_mode = 0;
+ break;
+
+ case AUDAC_CMD_PLAY_STOP:
+ /* play stop */
+ regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ if (g_audac_channel_mode == 0) {
+ g_audac_channel_mode = (regval & AUDAC_TX_CH_EN_MASK) >> AUDAC_TX_CH_EN_SHIFT;
+ }
+ regval &= ~AUDAC_TX_CH_EN_MASK;
+ putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ break;
+
+ case AUDAC_CMD_SET_MUTE:
+ /* set mute, arg use true or false */
+ regval = getreg32(reg_base + AUDAC_S0_OFFSET);
+ if (arg) {
+ regval |= AUDAC_DAC_S0_MUTE;
+ } else {
+ regval &= ~AUDAC_DAC_S0_MUTE;
+ }
+ putreg32(regval, reg_base + AUDAC_S0_OFFSET);
+ break;
+
+ case AUDAC_CMD_SET_VOLUME_VAL:
+ /* set volume value dB, arg range -191 to + 36, 0.5dB step, range -95.5dB to +18dB*/
+ volume_val = (uint16_t)((int16_t)arg * 2);
+ regval = getreg32(reg_base + AUDAC_S0_OFFSET);
+ regval &= ~AUDAC_DAC_S0_VOLUME_MASK;
+ regval |= (volume_val << AUDAC_DAC_S0_VOLUME_SHIFT) & AUDAC_DAC_S0_VOLUME_MASK;
+ putreg32(regval, reg_base + AUDAC_S0_OFFSET);
+ break;
+
+ case AUDAC_CMD_CLEAR_TX_FIFO:
+ /* get tx fifo cnt */
+ regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ regval |= AUDAC_TX_FIFO_FLUSH;
+ putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+ break;
+
+ case AUDAC_CMD_GET_TX_FIFO_CNT:
+ /* get tx fifo cnt */
+ regval = getreg32(reg_base + AUDAC_FIFO_STATUS_OFFSET);
+ ret = (regval & AUDAC_TXA_CNT_MASK) >> AUDAC_TXA_CNT_SHIFT;
+ break;
+
+ default:
+ break;
+ }
+
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_cam.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_cam.c
new file mode 100644
index 00000000..31208312
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_cam.c
@@ -0,0 +1,624 @@
+#include "bflb_cam.h"
+#include "hardware/cam_reg.h"
+#if !defined(BL702)
+#include "hardware/cam_front_reg.h"
+#include "bflb_clock.h"
+#endif
+
+#if defined(BL616)
+#define CAM_FRONT_BASE 0x20050000
+#endif
+#if defined(BL808)
+#define CAM_FRONT_BASE 0x30010000
+#endif
+
+void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint8_t data_mode = 0;
+ uint16_t resolution_x, resolution_y;
+ uint32_t frame_size;
+#if !defined(BL702)
+ uint32_t threshold;
+#endif
+#if defined(BL808)
+ uint32_t tmpval;
+
+ if (config->input_source) {
+ tmpval = 0x15;
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+ regval |= CAM_FRONT_REG_ISP_DTSRC_SRC;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_ADJA_CTRL_2_OFFSET);
+ regval |= 1;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_ADJA_CTRL_2_OFFSET);
+ } else {
+ tmpval = 0x24;
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+ regval &= ~CAM_FRONT_REG_ISP_DTSRC_SRC;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+ }
+#endif
+
+ reg_base = dev->reg_base;
+ putreg32(config->output_bufaddr, reg_base + CAM_DVP2AXI_ADDR_START_OFFSET);
+ putreg32(config->resolution_y << 16 | config->resolution_x, reg_base + CAM_DVP2AXI_FRAM_EXM_OFFSET);
+ putreg32(data_mode, reg_base + CAM_DVP_DEBUG_OFFSET);
+
+ regval = getreg32(reg_base + CAM_DVP2AXI_HSYNC_CROP_OFFSET);
+#if defined(BL702)
+ if ((regval & 0xffff) > 2 * config->resolution_x) {
+ resolution_x = config->resolution_x;
+ } else {
+ resolution_x = ((regval & 0xffff) - (regval >> 16 & 0xffff)) / 2;
+ }
+#else
+ if ((regval & 0xffff) > config->resolution_x) {
+ resolution_x = config->resolution_x;
+ } else {
+ resolution_x = (regval & 0xffff) - (regval >> 16 & 0xffff);
+ }
+#endif
+ regval = getreg32(reg_base + CAM_DVP2AXI_VSYNC_CROP_OFFSET);
+ if ((regval & 0xffff) > config->resolution_y) {
+ resolution_y = config->resolution_y;
+ } else {
+ resolution_y = (regval & 0xffff) - (regval >> 16 & 0xffff);
+ }
+
+#if defined(BL616)
+ putreg32(0, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+#endif
+
+#if !defined(BL702)
+#if defined(BL808)
+ if (config->input_source != CAM_INPUT_SOURCE_CSI) {
+#endif
+ regval = bflb_clk_get_system_clock(BFLB_SYSTEM_PBCLK);
+ if (regval == 0) {
+ regval = 80;
+ }
+ threshold = (config->h_blank + 4 * config->resolution_x - 2 * config->resolution_x * (config->pixel_clock / 1000000) / regval) / 4;
+
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ regval &= ~CAM_FRONT_RG_DVPAS_FIFO_TH_MASK;
+ regval |= threshold << CAM_FRONT_RG_DVPAS_FIFO_TH_SHIFT;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+#if defined(BL808)
+ }
+#endif
+#endif
+
+ /* Set output format */
+ frame_size = resolution_x * resolution_y * 2;
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ if (config->with_mjpeg) {
+ regval &= ~CAM_REG_SW_MODE;
+ } else {
+ regval |= CAM_REG_SW_MODE;
+ }
+#if defined(BL702)
+ regval |= CAM_REG_INTERLV_MODE;
+ regval &= ~(CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN | CAM_REG_SUBSAMPLE_EVEN);
+#else
+ regval &= ~(CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_DVP_DATA_MODE_MASK | CAM_REG_DVP_DATA_BSEL | CAM_REG_V_SUBSAMPLE_EN | CAM_REG_V_SUBSAMPLE_POL);
+#endif
+ switch (config->input_format) {
+ case CAM_INPUT_FORMAT_YUV422_YUYV:
+#if defined(BL808)
+ if (config->output_format >= CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 && config->output_format <= CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+ tmpval = 0x23;
+ if (config->input_source) {
+ putreg32(0x18000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+ } else {
+ putreg32(0xa8000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+ }
+ putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_1_OFFSET);
+ putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_2_OFFSET);
+ putreg32(0x200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_3_OFFSET);
+ putreg32(0x20002ce, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_4_OFFSET);
+ putreg32(0xfe92ff50, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_5_OFFSET);
+ putreg32(0x38b0200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_6_OFFSET);
+ putreg32(0, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_7_OFFSET);
+
+ if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
+ data_mode = 1;
+ frame_size = resolution_x * resolution_y * 3;
+ break;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
+ data_mode = 2;
+ frame_size = resolution_x * resolution_y * 2;
+ putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ break;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
+ data_mode = 2;
+ frame_size = resolution_x * resolution_y * 2;
+ putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ break;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+ data_mode = 3;
+ frame_size = resolution_x * resolution_y * 4;
+ break;
+ }
+ }
+#endif
+ case CAM_INPUT_FORMAT_YUV422_YVYU:
+ if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_YUV422) {
+ data_mode = 0;
+ frame_size = resolution_x * resolution_y * 2;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
+#if defined(BL702)
+ regval |= CAM_REG_DROP_EN;
+#endif
+ data_mode = 4;
+ frame_size = resolution_x * resolution_y;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV422_UV) {
+#if defined(BL702)
+ regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN;
+#else
+ regval |= CAM_REG_DVP_DATA_BSEL;
+#endif
+ data_mode = 4;
+ frame_size = resolution_x * resolution_y;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV420_UV) {
+#if defined(BL702)
+ regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN;
+#else
+ regval |= CAM_REG_DVP_DATA_BSEL | CAM_REG_V_SUBSAMPLE_EN | CAM_REG_V_SUBSAMPLE_POL;
+#endif
+ data_mode = 4;
+ frame_size = resolution_x * resolution_y / 2;
+#if defined(BL616)
+ putreg32(1, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+#endif
+ }
+ break;
+
+ case CAM_INPUT_FORMAT_YUV422_UYVY:
+#if defined(BL808)
+ if (config->output_format >= CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 && config->output_format <= CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+ bflb_cam_swap_input_yu_order(dev, true);
+ tmpval = 0x23;
+ if (config->input_source) {
+ putreg32(0x18000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+ } else {
+ putreg32(0xa8000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+ }
+ putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_1_OFFSET);
+ putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_2_OFFSET);
+ putreg32(0x200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_3_OFFSET);
+ putreg32(0x20002ce, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_4_OFFSET);
+ putreg32(0xfe92ff50, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_5_OFFSET);
+ putreg32(0x38b0200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_6_OFFSET);
+ putreg32(0, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_7_OFFSET);
+
+ if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
+ data_mode = 1;
+ frame_size = resolution_x * resolution_y * 3;
+ break;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
+ data_mode = 2;
+ frame_size = resolution_x * resolution_y * 2;
+ putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ break;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
+ data_mode = 2;
+ frame_size = resolution_x * resolution_y * 2;
+ putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ break;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+ data_mode = 3;
+ frame_size = resolution_x * resolution_y * 4;
+ break;
+ }
+ }
+#endif
+ case CAM_INPUT_FORMAT_YUV422_VYUY:
+ if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_YUV422) {
+ data_mode = 0;
+ frame_size = resolution_x * resolution_y * 2;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
+#if defined(BL702)
+ regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN;
+#else
+ regval |= CAM_REG_DVP_DATA_BSEL;
+#endif
+ data_mode = 4;
+ frame_size = resolution_x * resolution_y;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV422_UV) {
+#if defined(BL702)
+ regval |= CAM_REG_DROP_EN;
+#endif
+ data_mode = 4;
+ frame_size = resolution_x * resolution_y;
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV420_UV) {
+#if defined(BL702)
+ regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN | CAM_REG_SUBSAMPLE_EVEN;
+#else
+ regval |= CAM_REG_V_SUBSAMPLE_EN;
+#endif
+ data_mode = 4;
+ frame_size = resolution_x * resolution_y / 2;
+#if defined(BL616)
+ putreg32(1, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+#endif
+ }
+ break;
+
+ case CAM_INPUT_FORMAT_GRAY:
+ if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
+ data_mode = 0;
+ frame_size = resolution_x * resolution_y;
+ }
+ break;
+
+ case CAM_INPUT_FORMAT_RGB565:
+ /* Same as CAM_INPUT_FORMAT_BGR565 */
+ case CAM_INPUT_FORMAT_BGR565:
+ if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_RGB565_OR_BGR565) {
+ data_mode = 0;
+ frame_size = resolution_x * resolution_y * 2;
+ }
+ break;
+
+ case CAM_INPUT_FORMAT_RGB888:
+ /* Same as CAM_INPUT_FORMAT_BGR888 */
+ case CAM_INPUT_FORMAT_BGR888:
+ if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
+ data_mode = 1;
+ frame_size = resolution_x * resolution_y * 3;
+#if !defined(BL702)
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
+ data_mode = 2;
+ frame_size = resolution_x * resolution_y * 2;
+ putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
+ data_mode = 2;
+ frame_size = resolution_x * resolution_y * 2;
+ putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+ /* Default A = 0 */
+ data_mode = 3;
+ frame_size = resolution_x * resolution_y * 4;
+#endif
+ }
+ break;
+
+ default:
+ break;
+ }
+#if !defined(BL702)
+ putreg32(frame_size, reg_base + CAM_DVP2AXI_FRAME_BCNT_OFFSET);
+ regval |= data_mode << CAM_REG_DVP_DATA_MODE_SHIFT;
+#endif
+ putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+
+ /* Set output buffer burst count */
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ regval = (regval & CAM_REG_XLEN_MASK) >> CAM_REG_XLEN_SHIFT;
+ switch (regval) {
+ case CAM_BURST_INCR1:
+#if defined(BL702)
+ regval = config->output_bufsize >> 2;
+ frame_size = frame_size >> 2;
+#else
+ regval = config->output_bufsize >> 3;
+#endif
+ break;
+
+ case CAM_BURST_INCR4:
+#if defined(BL702)
+ regval = config->output_bufsize >> 4;
+ frame_size = frame_size >> 4;
+#else
+ regval = config->output_bufsize >> 5;
+#endif
+ break;
+
+ case CAM_BURST_INCR8:
+#if defined(BL702)
+ regval = config->output_bufsize >> 5;
+ frame_size = frame_size >> 5;
+#else
+ regval = config->output_bufsize >> 6;
+#endif
+ break;
+
+ case CAM_BURST_INCR16:
+#if defined(BL702)
+ regval = config->output_bufsize >> 6;
+ frame_size = frame_size >> 6;
+#else
+ regval = config->output_bufsize >> 7;
+#endif
+ break;
+
+#if !defined(BL702)
+ case CAM_BURST_INCR32:
+ regval = config->output_bufsize >> 8;
+ break;
+
+ case CAM_BURST_INCR64:
+ regval = config->output_bufsize >> 9;
+ break;
+#endif
+
+ default:
+ regval = config->output_bufsize >> 7;
+ frame_size = frame_size >> 6;
+ break;
+ }
+ putreg32(regval, reg_base + CAM_DVP2AXI_MEM_BCNT_OFFSET);
+
+#if defined(BL702)
+ putreg32(frame_size, reg_base + CAM_DVP2AXI_FRAME_BCNT_0_OFFSET);
+#endif
+
+#if defined(BL808)
+ if (dev->idx < 4) {
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+ regval &= ~(0x3f << (dev->idx * 8));
+ regval |= tmpval << (dev->idx * 8);
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+ } else {
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET);
+ regval &= ~(0x3f << ((dev->idx - 4) * 8));
+ regval |= tmpval << ((dev->idx - 4) * 8);
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET);
+ }
+#endif
+
+#if !defined(BL702)
+#if defined(BL808)
+ if (config->input_source == 0) {
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ regval |= CAM_FRONT_RG_DVPAS_ENABLE;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ }
+#else
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ regval |= CAM_FRONT_RG_DVPAS_ENABLE;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+#endif
+#endif
+}
+
+void bflb_cam_start(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ regval |= CAM_REG_DVP_ENABLE;
+ putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+}
+
+void bflb_cam_stop(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ regval &= ~CAM_REG_DVP_ENABLE;
+ putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+}
+
+void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+#if defined(BL702)
+ regval = getreg32(reg_base + CAM_INT_CONTROL_OFFSET);
+#else
+ regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+#endif
+ if (mask) {
+ regval &= ~int_type;
+ } else {
+ regval |= int_type;
+ }
+#if defined(BL702)
+ putreg32(regval, reg_base + CAM_INT_CONTROL_OFFSET);
+#else
+ putreg32(regval, reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+#endif
+}
+
+void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type)
+{
+ putreg32(int_type, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
+}
+
+void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line)
+{
+ /* Get start_line ~ (end_line - 1), not include end_line */
+ putreg32(start_line << 16 | end_line, dev->reg_base + CAM_DVP2AXI_VSYNC_CROP_OFFSET);
+}
+
+void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel)
+{
+#if defined(BL702)
+ start_pixel = start_pixel * 2;
+ end_pixel = end_pixel * 2;
+#endif
+ /* Get start_pixel ~ (end_pixel - 1), not include end_pixel */
+ putreg32(start_pixel << 16 | end_pixel, dev->reg_base + CAM_DVP2AXI_HSYNC_CROP_OFFSET);
+}
+
+void bflb_cam_pop_one_frame(struct bflb_device_s *dev)
+{
+#if defined(BL702)
+ putreg32(3, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
+#else
+ putreg32(1, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
+#endif
+}
+
+#if !defined(BL702)
+void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t regval;
+
+ /* If image sensor output format is YUYV, it will be changed to UYVY */
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ if (enable) {
+ regval |= CAM_FRONT_RG_DVPAS_DA_ORDER;
+ } else {
+ regval &= ~CAM_FRONT_RG_DVPAS_DA_ORDER;
+ }
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+}
+
+void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid)
+{
+ /* For example: frame_count is 4, frame_valid is 0x14 (10100b). Third/fifth frame will be retained,
+ First/second/fourth frame will be dropped in every (4 + 1) frames */
+ putreg32(frame_count, dev->reg_base + CAM_DVP2AXI_FRAME_PERIOD_OFFSET);
+ putreg32(frame_valid, dev->reg_base + CAM_DVP2AXI_FRAME_VLD_OFFSET);
+}
+#endif
+
+uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+ regval &= CAM_FRAME_VALID_CNT_MASK;
+ return (regval >> CAM_FRAME_VALID_CNT_SHIFT);
+}
+
+uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ *pic = (uint8_t *)getreg32(reg_base + CAM_FRAME_START_ADDR0_OFFSET);
+#if defined(BL702)
+ return (getreg32(reg_base + CAM_FRAME_BYTE_CNT0_0_OFFSET));
+#else
+ return (getreg32(reg_base + CAM_DVP2AXI_FRAME_BCNT_OFFSET));
+#endif
+}
+
+uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev)
+{
+ return (getreg32(dev->reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET));
+}
+
+int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case CAM_CMD_SET_VSYNC_POLARITY:
+ /* Set vsync polarity, arg use @ref CAM_POLARITY */
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ if (arg) {
+ regval |= CAM_REG_FRAM_VLD_POL;
+ } else {
+ regval &= ~CAM_REG_FRAM_VLD_POL;
+ }
+ putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ break;
+
+ case CAM_CMD_SET_HSYNC_POLARITY:
+ /* Set hsync polarity, arg use @ref CAM_POLARITY */
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ if (arg) {
+ regval |= CAM_REG_LINE_VLD_POL;
+ } else {
+ regval &= ~CAM_REG_LINE_VLD_POL;
+ }
+ putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ break;
+
+ case CAM_CMD_SET_BURST:
+ /* Set burst length, arg use @ref CAM_BURST */
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ regval &= ~CAM_REG_XLEN_MASK;
+ regval |= (arg << CAM_REG_XLEN_SHIFT) & CAM_REG_XLEN_MASK;
+ putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ break;
+
+#if !defined(BL702)
+ case CAM_CMD_SET_RGBA8888_ALPHA:
+ /* Set alpha value of RGBA8888 output, arg is alpha */
+ regval = getreg32(reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ regval &= ~CAM_REG_ALPHA_MASK;
+ regval |= arg & CAM_REG_ALPHA_MASK;
+ putreg32(regval, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+ break;
+
+ case CAM_CMD_GET_FRAME_ID:
+ /* Get frame id */
+ *(uint16_t *)arg = getreg32(reg_base + CAM_FRAME_ID_STS01_OFFSET) & 0xffff;
+ break;
+#endif
+
+ case CAM_CMD_WRAP_MODE:
+ /* Wrap to output buffer start address, only effective in mjpeg mode, arg use ENABLE or DISABLE */
+ regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ if (arg) {
+ regval |= CAM_REG_HW_MODE_FWRAP;
+ } else {
+ regval &= ~CAM_REG_HW_MODE_FWRAP;
+ }
+ putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+ break;
+
+ case CAM_CMD_COUNT_TRIGGER_NORMAL_INT:
+ /* Set frame count to trigger normal interrupt, arg is frame count */
+#if defined(BL702)
+ regval = getreg32(reg_base + CAM_INT_CONTROL_OFFSET);
+ regval &= ~CAM_REG_FRAME_CNT_TRGR_INT_MASK;
+ regval |= arg << CAM_REG_FRAME_CNT_TRGR_INT_SHIFT;
+ putreg32(regval, reg_base + CAM_INT_CONTROL_OFFSET);
+#else
+ regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+ regval &= ~CAM_REG_FRAME_CNT_TRGR_INT_MASK;
+ regval |= arg & CAM_REG_FRAME_CNT_TRGR_INT_MASK;
+ putreg32(regval, reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+#endif
+ break;
+
+#if !defined(BL702)
+ case CAM_CMD_FRAME_ID_RESET:
+ /* Reset frame id */
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_ISP_ID_YUV_OFFSET);
+ regval |= CAM_FRONT_REG_YUV_IDGEN_RST;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_ISP_ID_YUV_OFFSET);
+ break;
+
+ case CAM_CMD_INVERSE_VSYNC_POLARITY:
+ /* Inverse vsync polarity */
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ regval |= CAM_FRONT_RG_DVPAS_VS_INV;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ break;
+
+ case CAM_CMD_INVERSE_HSYNC_POLARITY:
+ /* Inverse hsync polarity */
+ regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ regval |= CAM_FRONT_RG_DVPAS_HS_INV;
+ putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+ break;
+#endif
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_cks.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_cks.c
new file mode 100644
index 00000000..830702ae
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_cks.c
@@ -0,0 +1,34 @@
+#include "bflb_cks.h"
+#include "hardware/cks_reg.h"
+
+void bflb_cks_reset(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + CKS_CONFIG_OFFSET);
+ regval |= CKS_CR_CKS_CLR;
+ putreg32(regval, reg_base + CKS_CONFIG_OFFSET);
+}
+
+void bflb_cks_set_endian(struct bflb_device_s *dev, uint8_t endian)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ putreg32(endian << 1, reg_base + CKS_CONFIG_OFFSET);
+}
+
+uint16_t bflb_cks_compute(struct bflb_device_s *dev, uint8_t *data, uint32_t length)
+{
+ uint32_t reg_base;
+ uint32_t i;
+
+ reg_base = dev->reg_base;
+ for (i = 0; i < length; i++) {
+ putreg32(data[i], reg_base + CKS_DATA_IN_OFFSET);
+ }
+
+ return ((uint16_t)(getreg32(reg_base + CKS_OUT_OFFSET) & 0xffff));
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_clock.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_clock.c
new file mode 100644
index 00000000..e46bfd78
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_clock.c
@@ -0,0 +1,93 @@
+#include "bflb_clock.h"
+#if defined(BL702)
+#include "bl702_clock.h"
+#elif defined(BL702L)
+#include "bl702l_clock.h"
+#elif defined(BL606P)
+#include "bl606p_clock.h"
+#elif defined(BL808)
+#include "bl808_clock.h"
+#elif defined(BL616)
+#include "bl616_clock.h"
+#elif defined(WB03)
+#include "wb03_clock.h"
+#elif defined(BL628)
+#include "bl628_clock.h"
+#endif
+
+/****************************************************************************/ /**
+ * @brief get system clock
+ *
+ * @param type: BFLB_SYSTEM_XXX
+ *
+ * @return NONE
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION bflb_clk_get_system_clock(uint8_t type)
+{
+ switch (type) {
+ case BFLB_SYSTEM_ROOT_CLOCK:
+ return bflb_clock_get_root();
+ case BFLB_SYSTEM_CPU_CLK:
+ return bflb_clock_get_fclk();
+ case BFLB_SYSTEM_PBCLK:
+ return bflb_clock_get_bclk();
+ case BFLB_SYSTEM_XCLK:
+ return bflb_clock_get_xclk();
+ case BFLB_SYSTEM_32K_CLK:
+ return bflb_clock_get_f32k();
+ default:
+ return 0;
+ }
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief get peripheral clock
+ *
+ * @param type: BFLB_DEVICE_TYPE_XXX
+ * @param idx: peripheral index
+ *
+ * @return NONE
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
+{
+ switch (type) {
+ case BFLB_DEVICE_TYPE_ADC:
+ return bflb_clock_get_adc();
+ case BFLB_DEVICE_TYPE_DAC:
+ return bflb_clock_get_dac();
+ case BFLB_DEVICE_TYPE_UART:
+ return bflb_clock_get_uart();
+ case BFLB_DEVICE_TYPE_SPI:
+ return bflb_clock_get_spi();
+ case BFLB_DEVICE_TYPE_I2C:
+ return bflb_clock_get_i2c();
+ case BFLB_DEVICE_TYPE_PWM:
+ return bflb_clock_get_pwm();
+ case BFLB_DEVICE_TYPE_TIMER:
+ return bflb_clock_get_timer(idx);
+ case BFLB_DEVICE_TYPE_WDT:
+ return bflb_clock_get_wdt();
+ case BFLB_DEVICE_TYPE_FLASH:
+ return bflb_clock_get_flash();
+ case BFLB_DEVICE_TYPE_IR:
+ return bflb_clock_get_ir();
+ case BFLB_DEVICE_TYPE_PKA:
+ return bflb_clock_get_pka();
+ case BFLB_DEVICE_TYPE_SDH:
+ return bflb_clock_get_sdh();
+ case BFLB_DEVICE_TYPE_CAMERA:
+ return bflb_clock_get_cam();
+ case BFLB_DEVICE_TYPE_DBI:
+ return bflb_clock_get_dbi();
+ case BFLB_DEVICE_TYPE_PEC:
+ return bflb_clock_get_pec();
+ case BFLB_DEVICE_TYPE_I2S:
+ return bflb_clock_get_i2s();
+ default:
+ return 0;
+ }
+ return 0;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_common.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_common.c
new file mode 100644
index 00000000..17db99b7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_common.c
@@ -0,0 +1,258 @@
+#include "bflb_common.h"
+#include "bflb_core.h"
+
+void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n)
+{
+ const uint8_t *p = src;
+ uint8_t *q = dst;
+
+ while (n--) {
+ *q++ = *p++;
+ }
+
+ return dst;
+}
+
+uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n)
+{
+ const uint32_t *p = src;
+ uint32_t *q = dst;
+
+ while (n--) {
+ *q++ = *p++;
+ }
+
+ return dst;
+}
+
+void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n)
+{
+ uint32_t left, done, i = 0;
+ uint8_t *dst = (uint8_t *)pdst;
+ uint8_t *src = (uint8_t *)psrc;
+
+ if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) {
+ arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2);
+ left = n % 4;
+ done = n - left;
+
+ while (i < left) {
+ dst[done + i] = src[done + i];
+ i++;
+ }
+ } else {
+ arch_memcpy(dst, src, n);
+ }
+
+ return dst;
+}
+
+void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n)
+{
+ uint8_t *p = (uint8_t *)s;
+
+ while (n > 0) {
+ *p++ = (uint8_t)c;
+ --n;
+ }
+
+ return s;
+}
+
+uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n)
+{
+ uint32_t *q = dst;
+
+ while (n--) {
+ *q++ = val;
+ }
+
+ return dst;
+}
+
+int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n)
+{
+ const unsigned char *c1 = s1, *c2 = s2;
+ int d = 0;
+
+ while (n--) {
+ d = (int)*c1++ - (int)*c2++;
+
+ if (d) {
+ break;
+ }
+ }
+
+ return d;
+}
+
+
+// ---------------- POPULAR POLYNOMIALS ----------------
+// CCITT: x^16 + x^12 + x^5 + x^0 (0x1021,init 0x0000)
+// CRC-16: x^16 + x^15 + x^2 + x^0 (0x8005,init 0xFFFF)
+// we use 0x8005 here and
+
+const uint8_t chCRCHTalbe[] = {
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+ 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+ 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+ 0x00, 0xC1, 0x81, 0x40
+};
+
+const uint8_t chCRCLTalbe[] = {
+ 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
+ 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
+ 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
+ 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
+ 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
+ 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
+ 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
+ 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
+ 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
+ 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
+ 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
+ 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
+ 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
+ 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
+ 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
+ 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
+ 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
+ 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
+ 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
+ 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
+ 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
+ 0x41, 0x81, 0x80, 0x40
+};
+
+uint16_t bflb_soft_crc16(void *in, uint32_t len)
+{
+ uint8_t chCRCHi = 0xFF;
+ uint8_t chCRCLo = 0xFF;
+ uint16_t wIndex;
+ uint8_t *data = (uint8_t *)in;
+
+ while (len--) {
+ wIndex = chCRCLo ^ *data++;
+ chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
+ chCRCHi = chCRCLTalbe[wIndex];
+ }
+
+ return ((chCRCHi << 8) | chCRCLo);
+}
+
+/*
+x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1
+*/
+const uint32_t crc32Tab[256] = {
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+ 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+ 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+ 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
+ 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+ 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
+ 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+ 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+ 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+ 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+ 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+ 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+ 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+ 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+ 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+ 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+ 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+ 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+ 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+ 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+ 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+ 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+
+uint32_t bflb_soft_crc32_table(void *in, uint32_t len)
+{
+ uint32_t crc = 0;
+ uint8_t *data = (uint8_t *)in;
+
+ crc = crc ^ 0xffffffff;
+
+ while (len--) {
+ crc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8);
+ }
+
+ return crc ^ 0xffffffff;
+}
+
+/******************************************************************************
+* Name: CRC-32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
+* Poly: 0x4C11DB7
+* Init: 0xFFFFFFF
+* Refin: True
+* Refout: True
+* Xorout: 0xFFFFFFF
+* Alias: CRC_32/ADCCP
+* Use: WinRAR,ect.
+*****************************************************************************/
+uint32_t ATTR_TCM_SECTION bflb_soft_crc32_ex(uint32_t initial, void *in, uint32_t len)
+{
+ uint8_t i;
+ uint32_t crc = ~initial; // Initial value
+ uint8_t *data = (uint8_t *)in;
+
+ while (len--) {
+ crc ^= *data++; // crc ^= *data; data++;
+ for (i = 0; i < 8; ++i) {
+ if (crc & 1) {
+ crc = (crc >> 1) ^ 0xEDB88320; // 0xEDB88320= reverse 0x04C11DB7
+ } else {
+ crc = (crc >> 1);
+ }
+ }
+ }
+ return ~crc;
+}
+
+#if !defined(BL602) && !defined(BL702)
+uint32_t ATTR_TCM_SECTION bflb_soft_crc32(void *in, uint32_t len)
+{
+ return bflb_soft_crc32_ex(0, in, len);
+}
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_csi.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_csi.c
new file mode 100644
index 00000000..7237e2c3
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_csi.c
@@ -0,0 +1,143 @@
+#include "bflb_csi.h"
+#include "hardware/csi_reg.h"
+#include "hardware/dtsrc_reg.h"
+
+#define DTSRC_BASE 0x30012800
+
+static void bflb_csi_phy_config(struct bflb_device_s *dev, uint32_t tx_clk_escape, uint32_t data_rate)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ /* Unit: ns */
+ float TD_TERM_EN_MAX = 35 + 4 * (1e3) / data_rate;
+ uint32_t TD_TERM_EN = (TD_TERM_EN_MAX * data_rate / 2 / (1e3)) - 1;
+ float THS_SETTLE_MAX = 145 + 10 * (1e3) / data_rate;
+ /* THS_SETTLE = reg_time_hs_settle + reg_time_hs_term_en */
+ uint32_t THS_SETTLE = ((THS_SETTLE_MAX - TD_TERM_EN * 2 * (1e3) / data_rate) * data_rate / 2 / (1e3)) - 1;
+ uint32_t TCLK_TERM_EN_MAX = 38;
+ uint32_t TCLK_TERM_EN = (tx_clk_escape * TCLK_TERM_EN_MAX) / (1e3);
+ uint32_t TCLK_SETTLE_MAX = 300;
+ /* TCLK_SETTLE = reg_time_ck_settle + reg_time_ck_term_en */
+ uint32_t TCLK_SETTLE = ((TCLK_SETTLE_MAX - TCLK_TERM_EN * (1e3) / tx_clk_escape) * tx_clk_escape / (1e3)) - 1;
+
+ uint32_t ANA_TERM_EN = 0x8;
+
+ reg_base = dev->reg_base;
+ regval = TD_TERM_EN << CSI_REG_TIME_HS_TERM_EN_SHIFT & CSI_REG_TIME_HS_TERM_EN_MASK;
+ regval |= THS_SETTLE << CSI_REG_TIME_HS_SETTLE_SHIFT & CSI_REG_TIME_HS_SETTLE_MASK;
+ regval |= TCLK_TERM_EN << CSI_REG_TIME_CK_TERM_EN_SHIFT & CSI_REG_TIME_CK_TERM_EN_MASK;
+ regval |= TCLK_SETTLE << CSI_REG_TIME_CK_SETTLE_SHIFT & CSI_REG_TIME_CK_SETTLE_MASK;
+ putreg32(regval, reg_base + CSI_DPHY_CONFIG_1_OFFSET);
+
+ regval = getreg32(DTSRC_BASE + CSI_DPHY_CONFIG_2_OFFSET);
+ regval &= ~CSI_REG_ANA_TERM_EN_MASK;
+ regval |= ANA_TERM_EN << CSI_REG_ANA_TERM_EN_SHIFT & CSI_REG_ANA_TERM_EN_MASK;
+ putreg32(regval, reg_base + CSI_DPHY_CONFIG_2_OFFSET);
+}
+
+void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+ regval |= DTSRC_CR_SNSR_EN;
+ putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+
+ regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+ regval &= ~(CSI_DL0_ENABLE | CSI_DL1_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE | CSI_DL1_FORCERXMODE | CSI_RESET_N);
+ putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+ regval |= CSI_RESET_N;
+ putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+
+ regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
+ if (config->lane_number) {
+ regval |= CSI_CR_LANE_NUM;
+ } else {
+ regval &= ~CSI_CR_LANE_NUM;
+ }
+ regval |= CSI_CR_UNPACK_EN | CSI_CR_SYNC_SP_EN;
+ putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
+
+ bflb_csi_phy_config(dev, config->tx_clk_escape / 1000000, config->data_rate / 1000000);
+
+ regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+ regval |= CSI_DL0_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE;
+ if (config->lane_number) {
+ regval |= CSI_DL1_ENABLE | CSI_DL1_FORCERXMODE;
+ }
+ putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+
+ regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+ regval |= DTSRC_CR_ENABLE;
+ putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+}
+
+void bflb_csi_start(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
+ regval |= CSI_CR_CSI_EN;
+ putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
+}
+
+void bflb_csi_stop(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
+ regval &= ~CSI_CR_CSI_EN;
+ putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
+}
+
+void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock)
+{
+ uint32_t threshold;
+
+ threshold = (dsp_clock - pixel_clock) / 1000 * resolution_x / (dsp_clock / 1000) + 10;
+ putreg32(threshold, DTSRC_BASE + DTSRC_SNSR2DVP_WAIT_POS_OFFSET);
+}
+
+void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + CSI_INT_MASK_OFFSET);
+ if (mask) {
+ regval |= int_type;
+ } else {
+ regval &= ~int_type;
+ }
+ putreg32(regval, reg_base + CSI_INT_MASK_OFFSET);
+}
+
+void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type)
+{
+ putreg32(int_type, dev->reg_base + CSI_INT_CLEAR_OFFSET);
+}
+
+uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev)
+{
+ return(getreg32(dev->reg_base + CSI_INT_STATUS_OFFSET));
+}
+
+int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+
+ switch (cmd) {
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dac.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dac.c
new file mode 100644
index 00000000..5cdfa034
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dac.c
@@ -0,0 +1,160 @@
+#include "bflb_dac.h"
+#include "hardware/dac_reg.h"
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define DAC_GPIP_BASE ((uint32_t)0x40002000)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define DAC_GPIP_BASE ((uint32_t)0x20002000)
+#endif
+
+void bflb_dac_init(struct bflb_device_s *dev, uint8_t clk_div)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ /* dac reset */
+ regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+ regval &= ~GLB_GPDACA_RSTN_ANA;
+ putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+ regval &= ~GLB_GPDACB_RSTN_ANA;
+ putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+ regval |= (GLB_GPDACA_RSTN_ANA | GLB_GPDACB_RSTN_ANA);
+ putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+ regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+ regval &= ~GLB_GPDAC_REF_SEL;
+ putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+ regval = 0;
+ regval |= GPIP_GPDAC_EN;
+#ifdef GPIP_GPDAC_EN2
+ regval |= GPIP_GPDAC_EN2;
+#endif
+ regval |= (clk_div << GPIP_GPDAC_MODE_SHIFT);
+ putreg32(regval, DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET);
+
+ regval = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+ regval &= ~GPIP_GPDAC_DMA_TX_EN;
+ putreg32(regval, DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+}
+
+void bflb_dac_channel_enable(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ if (ch & DAC_CHANNEL_A) {
+ regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+ regval |= (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+ putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+ }
+
+ if (ch & DAC_CHANNEL_B) {
+ regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET);
+ regval |= (GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN);
+ putreg32(regval, reg_base + GLB_GPDAC_BCTRL_OFFSET);
+#ifdef GPIP_GPDAC_EN2
+ regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+ regval |= (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+ putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+#endif
+ }
+}
+
+void bflb_dac_channel_disable(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ if (ch & DAC_CHANNEL_A) {
+ regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+ regval &= ~(GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+ putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+ }
+
+ if (ch & DAC_CHANNEL_B) {
+ regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET);
+ regval &= ~(GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN);
+ putreg32(regval, reg_base + GLB_GPDAC_BCTRL_OFFSET);
+ }
+}
+
+void bflb_dac_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t regval1;
+ uint32_t regval2;
+ uint32_t reg_base;
+ uint8_t flag = 0;
+
+ reg_base = dev->reg_base;
+
+ regval1 = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET);
+ regval1 &= ~GPIP_GPDAC_CH_A_SEL_MASK;
+ regval1 &= ~GPIP_GPDAC_CH_B_SEL_MASK;
+
+ regval2 = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+ if (enable) {
+ if (getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET) & (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN)) {
+ regval1 |= (1 << GPIP_GPDAC_CH_A_SEL_SHIFT);
+ flag++;
+ }
+
+ if (getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET) & (GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN)) {
+ regval1 |= (1 << GPIP_GPDAC_CH_B_SEL_SHIFT);
+ flag++;
+ }
+
+ if (flag == 1) {
+ regval2 |= (0 << GPIP_GPDAC_DMA_FORMAT_SHIFT);
+ } else {
+ regval2 |= (1 << GPIP_GPDAC_DMA_FORMAT_SHIFT);
+ }
+ regval2 |= GPIP_GPDAC_DMA_TX_EN;
+ } else {
+ regval2 &= ~GPIP_GPDAC_DMA_TX_EN;
+ }
+ putreg32(regval2, DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+ putreg32(regval1, DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET);
+}
+
+void bflb_dac_set_value(struct bflb_device_s *dev, uint8_t ch, uint16_t value)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + GLB_GPDAC_DATA_OFFSET);
+
+ if (ch & DAC_CHANNEL_A) {
+ regval &= ~GLB_GPDAC_A_DATA_MASK;
+ regval |= (value << GLB_GPDAC_A_DATA_SHIFT);
+ }
+
+ if (ch & DAC_CHANNEL_B) {
+ regval &= ~GLB_GPDAC_B_DATA_MASK;
+ regval |= (value << GLB_GPDAC_B_DATA_SHIFT);
+ }
+
+ putreg32(regval, reg_base + GLB_GPDAC_DATA_OFFSET);
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dbi.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dbi.c
new file mode 100644
index 00000000..c102f40e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dbi.c
@@ -0,0 +1,799 @@
+#include "bflb_dbi.h"
+#include "bflb_clock.h"
+#include "hardware/dbi_reg.h"
+
+#if (DBI_YUV_SUPPORT)
+/* YUV to RGB parameter list, do not modify. */
+
+#define YUV_PRE_OFFSET_0 0
+#define YUV_PRE_OFFSET_1 0x180
+#define YUV_PRE_OFFSET_2 0x180
+
+#define YUV_POST_OFFSET_0 0
+#define YUV_POST_OFFSET_1 0
+#define YUV_POST_OFFSET_2 0
+
+#define YUV_MATRIX00 0x200
+#define YUV_MATRIX01 0
+#define YUV_MATRIX02 0x2ce
+
+#define YUV_MATRIX10 0x200
+#define YUV_MATRIX11 0xf50
+#define YUV_MATRIX12 0xe92
+
+#define YUV_MATRIX20 0x200
+#define YUV_MATRIX21 0x38b
+#define YUV_MATRIX22 0
+
+#endif
+
+void bflb_dbi_init(struct bflb_device_s *dev, const struct bflb_dbi_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t div;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+
+ /* disable DBI transaction */
+ regval &= ~DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* dbi work mode select */
+ regval &= ~DBI_CR_DBI_SEL_MASK;
+ regval |= config->dbi_mode << DBI_CR_DBI_SEL_SHIFT;
+
+ /* clock phase and polarity cfg */
+ switch (config->clk_mode) {
+ case DBI_CLOCK_MODE_0:
+ /* CPOL=0 CHPHA=0 */
+ regval &= ~DBI_CR_DBI_SCL_POL;
+ regval |= DBI_CR_DBI_SCL_PH;
+ break;
+ case DBI_CLOCK_MODE_1:
+ /* CPOL=0 CHPHA=1 */
+ regval &= ~DBI_CR_DBI_SCL_POL;
+ regval &= ~DBI_CR_DBI_SCL_PH;
+ break;
+ case DBI_CLOCK_MODE_2:
+ /* CPOL=1 CHPHA=0 */
+ regval |= DBI_CR_DBI_SCL_POL;
+ regval |= DBI_CR_DBI_SCL_PH;
+ break;
+ case DBI_CLOCK_MODE_3:
+ /* CPOL=1 CHPHA=1 */
+ regval |= DBI_CR_DBI_SCL_POL;
+ regval &= ~DBI_CR_DBI_SCL_PH;
+ break;
+ default:
+ break;
+ }
+
+ /* disable pixel data continuous transfer mode (CS) */
+ regval &= ~DBI_CR_DBI_CONT_EN;
+
+ /* disable dummy between command phase and data phase */
+ regval &= ~DBI_CR_DBI_DMY_EN;
+
+ /* CS will stay asserted before FIFO is empty */
+#if (DBI_QSPI_SUPPORT)
+ if (config->dbi_mode == DBI_MODE_EX_QSPI) {
+ /* The CS of the qspi must be asserted in a single transaction */
+ regval |= DBI_CR_DBI_CS_STRETCH;
+ } else
+#endif
+ {
+ /* Other modes don't care */
+ regval &= ~DBI_CR_DBI_CS_STRETCH;
+ }
+
+ /* enable command phase */
+ regval |= DBI_CR_DBI_CMD_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* clock cfg */
+ /* integer frequency segmentation by rounding */
+ div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_DBI, dev->idx) / 2 * 10 / config->clk_freq_hz + 5) / 10;
+ div = (div) ? (div - 1) : 0;
+ div = (div > 0xff) ? 0xff : div;
+ regval = 0;
+ regval |= div << DBI_CR_DBI_PRD_S_SHIFT;
+ regval |= div << DBI_CR_DBI_PRD_I_SHIFT;
+ regval |= div << DBI_CR_DBI_PRD_D_PH_0_SHIFT;
+ regval |= div << DBI_CR_DBI_PRD_D_PH_1_SHIFT;
+ putreg32(regval, reg_base + DBI_PRD_OFFSET);
+
+ /* dbi output pixel format cfg */
+ regval = getreg32(reg_base + DBI_PIX_CNT_OFFSET);
+ if (config->pixel_output_format == DBI_PIXEL_OUTPUT_FORMAT_RGB_565) {
+ regval &= ~DBI_CR_DBI_PIX_FORMAT;
+ } else {
+ regval |= DBI_CR_DBI_PIX_FORMAT;
+ }
+ putreg32(regval, reg_base + DBI_PIX_CNT_OFFSET);
+
+ /* dbi input pixel format */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ regval &= ~DBI_FIFO_FORMAT_MASK;
+ regval |= config->pixel_input_format << DBI_FIFO_FORMAT_SHIFT;
+
+ /* clear fifo */
+ regval |= DBI_TX_FIFO_CLR;
+
+ /* disable YUV mode */
+ regval &= ~DBI_FIFO_YUV_MODE;
+
+ /* disable dma mode */
+ regval &= ~DBI_DMA_TX_EN;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+ /* tx fifo threshold cfg */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+ regval &= ~DBI_TX_FIFO_TH_MASK;
+ regval |= (config->tx_fifo_threshold << DBI_TX_FIFO_TH_SHIFT) & DBI_TX_FIFO_TH_MASK;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+
+#if (DBI_QSPI_SUPPORT)
+ regval = getreg32(reg_base + DBI_QSPI_CONFIG_OFFSET);
+
+ /* cmd wire */
+ if (config->cmd_wire_mode) {
+ regval |= DBI_CR_QSPI_CMD_4B;
+ } else {
+ regval &= ~DBI_CR_QSPI_CMD_4B;
+ }
+
+ /* address wire */
+ if (config->addr_wire_mode) {
+ regval |= DBI_CR_QSPI_ADR_4B;
+ } else {
+ regval &= ~DBI_CR_QSPI_ADR_4B;
+ }
+
+ /* data/pixel wire */
+ if (config->data_wire_mode) {
+ regval |= DBI_CR_QSPI_DAT_4B;
+ } else {
+ regval &= ~DBI_CR_QSPI_DAT_4B;
+ }
+
+ putreg32(regval, reg_base + DBI_QSPI_CONFIG_OFFSET);
+#endif
+
+#if (DBI_YUV_SUPPORT)
+ /* YUV to RGB parameter list. */
+ regval = 0;
+ regval |= (YUV_PRE_OFFSET_0 << DBI_CR_Y2R_PRE_0_SHIFT) & DBI_CR_Y2R_PRE_0_MASK;
+ regval |= (YUV_PRE_OFFSET_1 << DBI_CR_Y2R_PRE_1_SHIFT) & DBI_CR_Y2R_PRE_1_MASK;
+ regval |= (YUV_PRE_OFFSET_2 << DBI_CR_Y2R_PRE_2_SHIFT) & DBI_CR_Y2R_PRE_2_MASK;
+ regval |= DBI_CR_Y2R_EN;
+ putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_0_OFFSET);
+
+ regval = 0;
+ regval |= (YUV_POST_OFFSET_0 << DBI_CR_Y2R_POS_0_SHIFT) & DBI_CR_Y2R_POS_0_MASK;
+ regval |= (YUV_POST_OFFSET_1 << DBI_CR_Y2R_POS_1_SHIFT) & DBI_CR_Y2R_POS_1_MASK;
+ regval |= (YUV_POST_OFFSET_2 << DBI_CR_Y2R_POS_2_SHIFT) & DBI_CR_Y2R_POS_2_MASK;
+ putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_1_OFFSET);
+
+ regval = 0;
+ regval |= (YUV_MATRIX00 << DBI_CR_Y2R_MTX_00_SHIFT) & DBI_CR_Y2R_MTX_00_MASK;
+ regval |= (YUV_MATRIX01 << DBI_CR_Y2R_MTX_01_SHIFT) & DBI_CR_Y2R_MTX_01_MASK;
+ regval |= ((YUV_MATRIX02 & 0x0ff) << DBI_CR_Y2R_MTX_02_L_SHIFT) & DBI_CR_Y2R_MTX_02_L_MASK;
+ putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_2_OFFSET);
+
+ regval = 0;
+ regval |= (((YUV_MATRIX02 & 0xf00) >> 8) << DBI_CR_Y2R_MTX_02_U_SHIFT) & DBI_CR_Y2R_MTX_02_U_MASK;
+ regval |= (YUV_MATRIX10 << DBI_CR_Y2R_MTX_10_SHIFT) & DBI_CR_Y2R_MTX_10_MASK;
+ regval |= (YUV_MATRIX11 << DBI_CR_Y2R_MTX_11_SHIFT) & DBI_CR_Y2R_MTX_11_MASK;
+ regval |= ((YUV_MATRIX12 & 0x00f) << DBI_CR_Y2R_MTX_12_L_SHIFT) & DBI_CR_Y2R_MTX_12_L_MASK;
+ putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_3_OFFSET);
+
+ regval = 0;
+ regval |= (((YUV_MATRIX12 & 0xff0) >> 4) << DBI_CR_Y2R_MTX_12_U_SHIFT) & DBI_CR_Y2R_MTX_12_U_MASK;
+ regval |= (YUV_MATRIX20 << DBI_CR_Y2R_MTX_20_SHIFT) & DBI_CR_Y2R_MTX_20_MASK;
+ regval |= (YUV_MATRIX21 << DBI_CR_Y2R_MTX_21_SHIFT) & DBI_CR_Y2R_MTX_21_MASK;
+ putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_4_OFFSET);
+
+ regval = 0;
+ regval |= (YUV_MATRIX22 << DBI_CR_Y2R_MTX_22_SHIFT) & DBI_CR_Y2R_MTX_22_MASK;
+ putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_5_OFFSET);
+#endif
+}
+
+void bflb_dbi_deinit(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* disable DBI transaction */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ regval &= ~DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* clear fifo */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ regval |= DBI_TX_FIFO_CLR;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+}
+
+#if DBI_QSPI_SUPPORT
+void bflb_dbi_qspi_set_addr(struct bflb_device_s *dev, uint8_t addr_byte_size, uint32_t addr_val)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ addr_byte_size = addr_byte_size ? (addr_byte_size - 1) : addr_byte_size;
+
+ /* set address size */
+ regval = getreg32(reg_base + DBI_QSPI_CONFIG_OFFSET);
+ regval &= ~DBI_CR_QSPI_ADR_BC_MASK;
+ regval |= (addr_byte_size << DBI_CR_QSPI_ADR_BC_SHIFT) & DBI_CR_QSPI_ADR_BC_MASK;
+ putreg32(regval, reg_base + DBI_QSPI_CONFIG_OFFSET);
+
+ /* set address value */
+ putreg32(addr_val, reg_base + DBI_QSPI_ADR_OFFSET);
+}
+#endif
+
+static void bflb_dbi_fill_fifo(struct bflb_device_s *dev, uint32_t words_cnt, uint32_t *data_buff)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t fifo_cnt;
+
+ reg_base = dev->reg_base;
+
+ for (; words_cnt > 0;) {
+ /* get fifo available count */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+ fifo_cnt = (regval & DBI_TX_FIFO_CNT_MASK) >> DBI_TX_FIFO_CNT_SHIFT;
+
+ if (fifo_cnt) {
+ fifo_cnt = (fifo_cnt > words_cnt) ? words_cnt : fifo_cnt;
+ words_cnt -= fifo_cnt;
+ } else {
+ continue;
+ }
+
+ /* fill fifo */
+ for (; fifo_cnt > 0; fifo_cnt--, data_buff++) {
+ putreg32(*data_buff, reg_base + DBI_FIFO_WDATA_OFFSET);
+ }
+ }
+}
+
+static uint32_t bflb_dbi_get_words_cnt_form_pixel(struct bflb_device_s *dev, uint32_t pixle_cnt)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t words_cnt;
+ uint8_t pixel_input_format;
+
+ reg_base = dev->reg_base;
+
+ /* get fifo input pixel_format */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ pixel_input_format = (regval & DBI_FIFO_FORMAT_MASK) >> DBI_FIFO_FORMAT_SHIFT;
+
+ switch (pixel_input_format) {
+ /* 32-bit/pixel format list */
+ case DBI_PIXEL_INPUT_FORMAT_NBGR_8888:
+ case DBI_PIXEL_INPUT_FORMAT_NRGB_8888:
+ case DBI_PIXEL_INPUT_FORMAT_BGRN_8888:
+ case DBI_PIXEL_INPUT_FORMAT_RGBN_8888:
+ words_cnt = pixle_cnt;
+ break;
+
+ /* 24-bit/pixel format list */
+ case DBI_PIXEL_INPUT_FORMAT_RGB_888:
+ case DBI_PIXEL_INPUT_FORMAT_BGR_888:
+ words_cnt = (pixle_cnt * 3 + 3) / 4;
+ break;
+
+ /* 16-bit/pixel format list */
+ case DBI_PIXEL_INPUT_FORMAT_BGR_565:
+ case DBI_PIXEL_INPUT_FORMAT_RGB_565:
+ words_cnt = (pixle_cnt + 1) / 2;
+ break;
+
+ default:
+ words_cnt = 0;
+ break;
+ }
+
+ return words_cnt;
+}
+
+int bflb_dbi_send_cmd_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* null */
+ if (data_len && data_buff == NULL) {
+ return 0;
+ }
+
+ /* disable DBI transaction */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ regval &= ~DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ if (((regval & DBI_CR_DBI_CMD_EN) == 0) && (data_len == 0)) {
+ /* There is no data or command phase, nothing to do */
+ return 0;
+ }
+
+ /* normal data mode */
+ regval &= ~DBI_CR_DBI_DAT_TP;
+
+ /* write mode */
+ regval |= DBI_CR_DBI_DAT_WR;
+
+ /* set data len */
+ if (data_len) {
+ regval |= DBI_CR_DBI_DAT_EN;
+ regval &= ~DBI_CR_DBI_DAT_BC_MASK;
+ regval |= ((data_len - 1) << DBI_CR_DBI_DAT_BC_SHIFT) & DBI_CR_DBI_DAT_BC_MASK;
+ } else {
+ regval &= ~DBI_CR_DBI_DAT_EN;
+ }
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* set cmd */
+ if (regval & DBI_CR_DBI_CMD_EN) {
+ regval = getreg32(reg_base + DBI_CMD_OFFSET);
+ regval &= ~DBI_CR_DBI_CMD_MASK;
+ regval |= cmd << DBI_CR_DBI_CMD_SHIFT;
+ putreg32(regval, reg_base + DBI_CMD_OFFSET);
+ }
+
+ /* clear fifo */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ regval |= DBI_TX_FIFO_CLR;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+ /* clear complete interrupt */
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ regval |= DBI_CR_DBI_END_CLR;
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+ /* first fill some data into the fifo */
+ if (data_len) {
+ if (data_len <= SPI_FIFO_NUM_MAX * 4) {
+ bflb_dbi_fill_fifo(dev, (data_len + 3) / 4, (uint32_t *)data_buff);
+ data_len = 0;
+ } else {
+ bflb_dbi_fill_fifo(dev, SPI_FIFO_NUM_MAX, (uint32_t *)data_buff);
+ data_len -= SPI_FIFO_NUM_MAX * 4;
+ }
+ }
+
+ /* trigger the transaction */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ regval |= DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* Fill the rest of the data into the fifo */
+ if (data_len) {
+ bflb_dbi_fill_fifo(dev, (data_len + 3) / 4, (uint32_t *)data_buff);
+ }
+
+ /* Wait transfer complete */
+ do {
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ } while ((regval & DBI_END_INT) == 0);
+
+ /* clear end int */
+ regval |= DBI_CR_DBI_END_CLR;
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+ return 0;
+}
+
+int bflb_dbi_send_cmd_read_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* disable DBI transaction */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ regval &= ~DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ if (((regval & DBI_CR_DBI_CMD_EN) == 0) && (data_len == 0)) {
+ /* There is no data or command phase, nothing to do */
+ return 0;
+ }
+
+ /* normal data mode */
+ regval &= ~DBI_CR_DBI_DAT_TP;
+
+ /* read mode */
+ regval &= ~DBI_CR_DBI_DAT_WR;
+
+ /* set data len */
+ if (data_len) {
+ regval |= DBI_CR_DBI_DAT_EN;
+ regval &= ~DBI_CR_DBI_DAT_BC_MASK;
+ regval |= ((data_len - 1) << DBI_CR_DBI_DAT_BC_SHIFT) & DBI_CR_DBI_DAT_BC_MASK;
+ } else {
+ regval &= ~DBI_CR_DBI_DAT_EN;
+ }
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* set cmd */
+ if (regval & DBI_CR_DBI_CMD_EN) {
+ regval = getreg32(reg_base + DBI_CMD_OFFSET);
+ regval &= ~DBI_CR_DBI_CMD_MASK;
+ regval |= cmd << DBI_CR_DBI_CMD_SHIFT;
+ putreg32(regval, reg_base + DBI_CMD_OFFSET);
+ }
+
+ /* clear fifo */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ regval |= DBI_TX_FIFO_CLR;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+ /* clear complete interrupt */
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ regval |= DBI_CR_DBI_END_CLR;
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+ /* trigger the transaction */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ regval |= DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* Wait transfer complete */
+ do {
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ } while ((regval & DBI_END_INT) == 0);
+
+ /* clear end int */
+ regval |= DBI_CR_DBI_END_CLR;
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+ /* Null pointer error */
+ if (data_buff == NULL) {
+ return 0;
+ }
+
+ /* copy data to buff */
+ regval = getreg32(reg_base + DBI_RDATA_0_OFFSET);
+ for (uint8_t i = 0; (data_len > 0) && (i < 4); i++, data_len--) {
+ *data_buff = (uint8_t)regval;
+ data_buff++;
+ regval >>= 8;
+ }
+ regval = getreg32(reg_base + DBI_RDATA_1_OFFSET);
+ for (uint8_t i = 0; (data_len > 0) && (i < 4); i++, data_len--) {
+ *data_buff = (uint8_t)regval;
+ data_buff++;
+ regval >>= 8;
+ }
+
+ return 0;
+}
+
+int bflb_dbi_send_cmd_pixel(struct bflb_device_s *dev, uint8_t cmd, uint32_t pixel_cnt, void *pixel_buff)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* disable DBI transaction */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ regval &= ~DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ if (((regval & DBI_CR_DBI_CMD_EN) == 0) && (pixel_cnt == 0)) {
+ /* There is no data or command phase, nothing to do */
+ return 0;
+ }
+
+ /* pixel mode */
+ regval |= DBI_CR_DBI_DAT_TP;
+
+ /* write mode */
+ regval |= DBI_CR_DBI_DAT_WR;
+
+ /* pixle data phase enable */
+ if (pixel_cnt) {
+ regval |= DBI_CR_DBI_DAT_EN;
+ } else {
+ regval &= ~DBI_CR_DBI_DAT_EN;
+ }
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* set cmd */
+ if (regval & DBI_CR_DBI_CMD_EN) {
+ regval = getreg32(reg_base + DBI_CMD_OFFSET);
+ regval &= ~DBI_CR_DBI_CMD_MASK;
+ regval |= cmd << DBI_CR_DBI_CMD_SHIFT;
+ putreg32(regval, reg_base + DBI_CMD_OFFSET);
+ }
+
+ /* pixel cnt */
+ if (pixel_cnt) {
+ regval = getreg32(reg_base + DBI_PIX_CNT_OFFSET);
+ regval &= ~DBI_CR_DBI_PIX_CNT_MASK;
+ regval |= ((pixel_cnt - 1) << DBI_CR_DBI_PIX_CNT_SHIFT) & DBI_CR_DBI_PIX_CNT_MASK;
+ putreg32(regval, reg_base + DBI_PIX_CNT_OFFSET);
+ }
+
+ /* clear fifo */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ regval |= DBI_TX_FIFO_CLR;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+ /* clear complete interrupt */
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ regval |= DBI_CR_DBI_END_CLR;
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+ /* trigger the transaction */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ regval |= DBI_CR_DBI_EN;
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+ /* No need to fill in fifo, for DMA mode */
+ if (pixel_buff == NULL) {
+ return 0;
+ }
+
+ /* fill the data into the fifo, can only be used in non-DMA mode */
+ bflb_dbi_fill_fifo(dev, bflb_dbi_get_words_cnt_form_pixel(dev, pixel_cnt), (uint32_t *)pixel_buff);
+
+ /* Wait transfer complete */
+ do {
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ } while ((regval & DBI_END_INT) == 0);
+
+ /* clear end int */
+ regval |= DBI_CR_DBI_END_CLR;
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+ return 0;
+}
+
+void bflb_dbi_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= DBI_DMA_TX_EN;
+ } else {
+ regval &= ~DBI_DMA_TX_EN;
+ }
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_dbi_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ if (mask) {
+ regval |= DBI_CR_DBI_TXF_MASK;
+ } else {
+ regval &= ~DBI_CR_DBI_TXF_MASK;
+ }
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+void bflb_dbi_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ if (mask) {
+ regval |= DBI_CR_DBI_END_MASK;
+ } else {
+ regval &= ~DBI_CR_DBI_END_MASK;
+ }
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+void bflb_dbi_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+ if (mask) {
+ regval |= DBI_CR_DBI_FER_MASK;
+ } else {
+ regval &= ~DBI_CR_DBI_FER_MASK;
+ }
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+uint32_t bflb_dbi_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t int_sts;
+
+ reg_base = dev->reg_base;
+ int_sts = 0;
+
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+
+ /* transfer completion interrupt */
+ if (regval & DBI_END_INT) {
+ int_sts |= DBI_INTSTS_TC;
+ }
+
+ /* fifo threshold interrupt */
+ if (regval & DBI_TXF_INT) {
+ int_sts |= SPI_INTSTS_TX_FIFO;
+ }
+
+ /* fifo error (underflow or overflow) interrupt */
+ if (regval & DBI_FER_INT) {
+ int_sts |= SPI_INTSTS_FIFO_ERR;
+ }
+
+ return int_sts;
+}
+
+void bflb_dbi_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+
+ /* transfer completion interrupt */
+ if (int_clear & DBI_INTCLR_TC) {
+ regval |= DBI_CR_DBI_END_CLR;
+ }
+
+ putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+int bflb_dbi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case DBI_CMD_CLEAR_TX_FIFO:
+ /* clear fifo */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ regval |= DBI_TX_FIFO_CLR;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case DBI_CMD_GET_TX_FIFO_CNT:
+ /* get fifo available count */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+ ret = (regval & DBI_TX_FIFO_CNT_MASK) >> DBI_TX_FIFO_CNT_SHIFT;
+ break;
+
+ case DBI_CMD_MASK_CMD_PHASE:
+ /* mask command phase, arg use true or false,
+ true: no command phase, false: command will be sent
+ don't-care if QSPI mode is selected (command always sent)
+ */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+#if (DBI_QSPI_SUPPORT)
+ /* the setting is not valid for the qspi mode */
+ if ((regval & DBI_CR_DBI_SEL_MASK) >> DBI_CR_DBI_SEL_SHIFT == DBI_MODE_EX_QSPI) {
+ break;
+ }
+#endif
+ if (arg) {
+ regval &= ~DBI_CR_DBI_CMD_EN;
+ } else {
+ regval |= DBI_CR_DBI_CMD_EN;
+ }
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+ break;
+
+ case DBI_CMD_CS_CONTINUE:
+ /* set CS continue mode, arg use true or false */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+ if (arg) {
+ regval |= DBI_CR_DBI_CONT_EN;
+ } else {
+ regval &= ~DBI_CR_DBI_CONT_EN;
+ }
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+ break;
+
+ case DBI_CMD_SET_DUMMY_CNT:
+ /* set dummy cycle(s) between command phase and data phase
+ arg range: 0 ~ 16,
+ don't-care if QSPI mode is selected (no dummy cycle)
+ */
+ regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+#if (DBI_QSPI_SUPPORT)
+ /* the setting is not valid for the qspi mode */
+ if ((regval & DBI_CR_DBI_SEL_MASK) >> DBI_CR_DBI_SEL_SHIFT == DBI_MODE_EX_QSPI) {
+ break;
+ }
+#endif
+ if (arg) {
+ regval |= DBI_CR_DBI_DMY_EN;
+ regval &= ~DBI_CR_DBI_DMY_CNT_MASK;
+ regval |= ((arg - 1) << DBI_CR_DBI_DMY_CNT_SHIFT) & DBI_CR_DBI_DMY_CNT_MASK;
+ } else {
+ regval &= ~DBI_CR_DBI_DMY_EN;
+ }
+ putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+ break;
+
+ case DBI_CMD_GET_SIZE_OF_PIXEL_CNT:
+ /* gets the pixel_data size(byte), arg: pixel number */
+ ret = bflb_dbi_get_words_cnt_form_pixel(dev, arg) * 4;
+ break;
+
+ case DBI_CMD_INPUT_PIXEL_FORMAT:
+ /* dbi input pixel format, arg use @ref DBI_PIXEL_INPUT_FORMAT */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ regval &= ~DBI_FIFO_FORMAT_MASK;
+ regval |= (arg << DBI_FIFO_FORMAT_SHIFT) & DBI_FIFO_FORMAT_MASK;
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case DBI_CMD_OUTPUT_PIXEL_FORMAT:
+ /* dbi output pixel format, arg use @ref DBI_PIXEL_OUTPUT_FORMAT */
+ regval = getreg32(reg_base + DBI_PIX_CNT_OFFSET);
+ if (arg == DBI_PIXEL_OUTPUT_FORMAT_RGB_565) {
+ regval &= ~DBI_CR_DBI_PIX_FORMAT;
+ } else if (arg == DBI_PIXEL_OUTPUT_FORMAT_RGB_888) {
+ regval |= DBI_CR_DBI_PIX_FORMAT;
+ }
+ putreg32(regval, reg_base + DBI_PIX_CNT_OFFSET);
+ break;
+
+#if (DBI_YUV_SUPPORT)
+ case DBI_CMD_YUV_TO_RGB_ENABLE:
+ /* yuv to rgb cfg, arg use true or false */
+ regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ if (arg) {
+ regval |= DBI_FIFO_YUV_MODE;
+ } else {
+ regval &= ~DBI_FIFO_YUV_MODE;
+ }
+ putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+ break;
+#endif
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dma.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dma.c
new file mode 100644
index 00000000..25a25327
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_dma.c
@@ -0,0 +1,455 @@
+#include "bflb_dma.h"
+#include "bflb_l1c.h"
+#include "hardware/dma_reg.h"
+
+struct bflb_dma_irq_callback {
+ void (*handler)(void *arg);
+ void *arg;
+};
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+const uint32_t dma_base[] = { 0x4000C000 };
+struct bflb_dma_irq_callback dma_callback[1][8];
+#elif defined(BL616)
+const uint32_t dma_base[] = { 0x2000C000 };
+struct bflb_dma_irq_callback dma_callback[1][4];
+#elif defined(BL606P) || defined(BL808)
+const uint32_t dma_base[] = { 0x2000C000, 0x20071000, 0x30001000 };
+struct bflb_dma_irq_callback dma_callback[3][8];
+#elif defined(BL628)
+const uint32_t dma_base[] = { 0x20081000 };
+struct bflb_dma_irq_callback dma_callback[1][8];
+#endif
+
+void dma0_isr(int irq, void *arg)
+{
+ uint32_t regval;
+
+ regval = getreg32(dma_base[0] + DMA_INTTCSTATUS_OFFSET);
+ putreg32(regval, dma_base[0] + DMA_INTTCCLEAR_OFFSET);
+
+ for (uint8_t i = 0; i < 8; i++) {
+ if (regval & (1 << i)) {
+ dma_callback[0][i].handler(dma_callback[0][i].arg);
+ }
+ }
+}
+
+#if defined(BL606P) || defined(BL808)
+void dma1_isr(int irq, void *arg)
+{
+ uint32_t regval;
+
+ regval = getreg32(dma_base[1] + DMA_INTTCSTATUS_OFFSET);
+ putreg32(regval, dma_base[1] + DMA_INTTCCLEAR_OFFSET);
+
+ for (uint8_t i = 0; i < 8; i++) {
+ if (regval & (1 << i)) {
+ dma_callback[1][i].handler(dma_callback[1][i].arg);
+ }
+ }
+}
+
+void dma2_isr(int irq, void *arg)
+{
+ uint32_t regval;
+
+ regval = getreg32(dma_base[2] + DMA_INTTCSTATUS_OFFSET);
+ putreg32(regval, dma_base[2] + DMA_INTTCCLEAR_OFFSET);
+
+ for (uint8_t i = 0; i < 8; i++) {
+ if (regval & (1 << i)) {
+ dma_callback[1][i].handler(dma_callback[2][i].arg);
+ }
+ }
+}
+#endif
+
+void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_channel_config_s *config)
+{
+ uint32_t regval;
+ uint32_t channel_base;
+
+ channel_base = dev->reg_base;
+
+ /* dma global enable */
+ regval = getreg32(dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
+ regval |= DMA_E;
+ putreg32(regval, dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
+
+ /* dma channel disable */
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ regval &= ~DMA_E;
+ putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+#if defined(BL602)
+ regval = 0;
+#else
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ regval &= DMA_DST_ADD_MODE | DMA_DST_MIN_MODE | DMA_FIX_CNT_MASK;
+#endif
+
+ if (config->src_addr_inc) {
+ regval |= DMA_SI;
+ }
+ if (config->dst_addr_inc) {
+ regval |= DMA_DI;
+ }
+
+ regval |= (config->src_width << DMA_SWIDTH_SHIFT);
+ regval |= (config->dst_width << DMA_DWIDTH_SHIFT);
+ regval |= (config->src_burst_count << DMA_SBSIZE_SHIFT);
+ regval |= (config->dst_burst_count << DMA_DBSIZE_SHIFT);
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ regval &= ~DMA_SRCPERIPHERAL_MASK;
+ regval &= ~DMA_DSTPERIPHERAL_MASK;
+ regval &= ~DMA_FLOWCNTRL_MASK;
+ regval &= ~DMA_LLICOUNTER_MASK;
+ regval |= (config->src_req << DMA_SRCPERIPHERAL_SHIFT);
+ regval |= (config->dst_req << DMA_DSTPERIPHERAL_SHIFT);
+ regval |= (config->direction << DMA_FLOWCNTRL_SHIFT);
+ putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+ /* enable dma error and tc interrupt */
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ regval |= (DMA_ITC | DMA_IE);
+ putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ regval &= ~DMA_I;
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+
+ /* clear irq status */
+ putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTTCCLEAR_OFFSET);
+ putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTERRCLR_OFFSET);
+
+#if (defined(BL606P) || defined(BL808)) && (defined(CPU_M0) || defined(CPU_LP))
+ bflb_irq_attach(31, dma0_isr, NULL);
+ bflb_irq_attach(32, dma1_isr, NULL);
+ bflb_irq_enable(31);
+ bflb_irq_enable(32);
+#elif (defined(BL606P) || defined(BL808)) && defined(CPU_D0)
+ bflb_irq_attach(40, dma2_isr, NULL);
+ bflb_irq_attach(41, dma2_isr, NULL);
+ bflb_irq_attach(42, dma2_isr, NULL);
+ bflb_irq_attach(43, dma2_isr, NULL);
+ bflb_irq_attach(44, dma2_isr, NULL);
+ bflb_irq_attach(45, dma2_isr, NULL);
+ bflb_irq_attach(46, dma2_isr, NULL);
+ bflb_irq_attach(47, dma2_isr, NULL);
+ bflb_irq_enable(40);
+ bflb_irq_enable(41);
+ bflb_irq_enable(42);
+ bflb_irq_enable(43);
+ bflb_irq_enable(44);
+ bflb_irq_enable(45);
+ bflb_irq_enable(46);
+ bflb_irq_enable(47);
+#else
+ bflb_irq_attach(dev->irq_num, dma0_isr, NULL);
+ bflb_irq_enable(dev->irq_num);
+#endif
+}
+
+void bflb_dma_lli_config(struct bflb_device_s *dev, struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t lli_count, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_offset, uint32_t last_transfer_len)
+{
+ uint32_t channel_base;
+ union bflb_dma_lli_control_s dma_ctrl_cfg;
+
+ channel_base = dev->reg_base;
+
+ dma_ctrl_cfg = (union bflb_dma_lli_control_s)getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+
+ dma_ctrl_cfg.bits.TransferSize = 4064;
+ dma_ctrl_cfg.bits.I = 0;
+
+ /* nbytes will be integer multiple of 4064*n or 4064*2*n or 4064*4*n,(n>0) */
+ for (uint32_t i = 0; i < lli_count; i++) {
+ lli_pool[i].src_addr = src_addr;
+ lli_pool[i].dst_addr = dst_addr;
+ lli_pool[i].nextlli = 0;
+
+ if (dma_ctrl_cfg.bits.SI) {
+ src_addr += transfer_offset;
+ }
+
+ if (dma_ctrl_cfg.bits.DI) {
+ dst_addr += transfer_offset;
+ }
+
+ if (i == lli_count - 1) {
+ dma_ctrl_cfg.bits.TransferSize = last_transfer_len;
+ dma_ctrl_cfg.bits.I = 1;
+ }
+
+ if (i) {
+ lli_pool[i - 1].nextlli = (uint32_t)(uintptr_t)&lli_pool[i];
+ }
+
+ lli_pool[i].control = dma_ctrl_cfg;
+ }
+}
+
+int bflb_dma_channel_lli_reload(struct bflb_device_s *dev, struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count, struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count)
+{
+ uint32_t channel_base;
+ uint32_t actual_transfer_offset = 0;
+ uint32_t actual_transfer_len = 0;
+ uint32_t last_transfer_len = 0;
+ uint32_t current_lli_count = 0;
+ uint32_t lli_count_used_offset = 0;
+ union bflb_dma_lli_control_s dma_ctrl_cfg;
+
+ channel_base = dev->reg_base;
+
+ dma_ctrl_cfg = (union bflb_dma_lli_control_s)getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+
+ switch (dma_ctrl_cfg.bits.SWidth) {
+ case DMA_DATA_WIDTH_8BIT:
+ actual_transfer_offset = 4064;
+ break;
+ case DMA_DATA_WIDTH_16BIT:
+ actual_transfer_offset = 4064 << 1;
+ break;
+ case DMA_DATA_WIDTH_32BIT:
+ actual_transfer_offset = 4064 << 2;
+ break;
+ default:
+ break;
+ }
+
+ for (size_t i = 0; i < count; i++) {
+ switch (dma_ctrl_cfg.bits.SWidth) {
+ case DMA_DATA_WIDTH_8BIT:
+ actual_transfer_len = transfer[i].nbytes;
+ break;
+ case DMA_DATA_WIDTH_16BIT:
+ if (transfer[i].nbytes % 2) {
+ return -1;
+ }
+ actual_transfer_len = transfer[i].nbytes >> 1;
+ break;
+ case DMA_DATA_WIDTH_32BIT:
+ if (transfer[i].nbytes % 4) {
+ return -1;
+ }
+ actual_transfer_len = transfer[i].nbytes >> 2;
+ break;
+
+ default:
+ break;
+ }
+
+ current_lli_count = actual_transfer_len / 4064 + 1;
+ last_transfer_len = actual_transfer_len % 4064;
+
+ /* The maximum transfer capacity of the last node is 4095 */
+ if (current_lli_count > 1 && last_transfer_len < (4095 - 4064)) {
+ current_lli_count--;
+ last_transfer_len += 4064;
+ }
+
+ bflb_dma_lli_config(dev, &lli_pool[lli_count_used_offset], current_lli_count, transfer[i].src_addr, transfer[i].dst_addr, actual_transfer_offset, last_transfer_len);
+ if (i) {
+ lli_pool[lli_count_used_offset - 1].nextlli = (uint32_t)(uintptr_t)&lli_pool[lli_count_used_offset];
+ }
+ lli_count_used_offset += current_lli_count;
+
+ if (lli_count_used_offset > max_lli_count) {
+ return -ENOMEM;
+ }
+ }
+
+ putreg32(lli_pool[0].src_addr, channel_base + DMA_CxSRCADDR_OFFSET);
+ putreg32(lli_pool[0].dst_addr, channel_base + DMA_CxDSTADDR_OFFSET);
+ putreg32(lli_pool[0].nextlli, channel_base + DMA_CxLLI_OFFSET);
+ putreg32(lli_pool[0].control.WORD, channel_base + DMA_CxCONTROL_OFFSET);
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+ /* clean cache, DMA does not pass through the cache */
+ bflb_l1c_dcache_clean_range((uint32_t *)(uintptr_t)lli_pool, sizeof(struct bflb_dma_channel_lli_pool_s) * lli_count_used_offset);
+#endif
+ return lli_count_used_offset;
+}
+
+void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
+ struct bflb_dma_channel_lli_pool_s *lli_pool,
+ uint32_t used_lli_count)
+{
+ uint32_t channel_base;
+
+ channel_base = dev->reg_base;
+
+ lli_pool[used_lli_count - 1].nextlli = (uint32_t)(uintptr_t)&lli_pool[0];
+
+ putreg32(lli_pool[0].nextlli, channel_base + DMA_CxLLI_OFFSET);
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+ /* clean cache, DMA does not pass through the cache */
+ bflb_l1c_dcache_clean_range((uint32_t *)lli_pool, sizeof(struct bflb_dma_channel_lli_pool_s) * used_lli_count);
+#endif
+}
+
+void bflb_dma_channel_start(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t channel_base;
+
+ channel_base = dev->reg_base;
+
+ /* dma channel enable */
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ regval |= DMA_E;
+ putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+}
+
+void bflb_dma_channel_stop(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t channel_base;
+
+ channel_base = dev->reg_base;
+
+ /* dma channel disable */
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ regval &= ~DMA_E;
+ putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+}
+
+bool bflb_dma_channel_isbusy(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t channel_base;
+
+ channel_base = dev->reg_base;
+
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ if (regval & (1 << 0)) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t channel_base;
+
+ channel_base = dev->reg_base;
+
+ if (mask) {
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ regval |= DMA_ITC;
+ putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ regval &= ~DMA_I;
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+ } else {
+ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+ regval &= ~DMA_ITC;
+ putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ regval |= DMA_I;
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+ }
+}
+
+void bflb_dma_channel_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg), void *arg)
+{
+ dma_callback[dev->idx][dev->sub_idx].handler = callback;
+ dma_callback[dev->idx][dev->sub_idx].arg = arg;
+
+ bflb_dma_channel_tcint_mask(dev, false);
+}
+
+void bflb_dma_channel_irq_detach(struct bflb_device_s *dev)
+{
+ dma_callback[dev->idx][dev->sub_idx].handler = NULL;
+ dma_callback[dev->idx][dev->sub_idx].arg = NULL;
+
+ bflb_dma_channel_tcint_mask(dev, true);
+}
+
+bool bflb_dma_channel_get_tcint_status(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+
+ regval = getreg32(dma_base[dev->idx] + DMA_INTTCSTATUS_OFFSET);
+ if (regval & (1 << dev->sub_idx)) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev)
+{
+ putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTTCCLEAR_OFFSET);
+}
+
+int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t regval;
+ uint32_t channel_base;
+
+ channel_base = dev->reg_base;
+
+ switch (cmd) {
+ case DMA_CMD_SET_SRCADDR_INCREMENT:
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ if (arg) {
+ regval |= DMA_SI;
+ } else {
+ regval &= ~DMA_SI;
+ }
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+ break;
+
+ case DMA_CMD_SET_DSTADDR_INCREMENT:
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ if (arg) {
+ regval |= DMA_DI;
+ } else {
+ regval &= ~DMA_DI;
+ }
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+ break;
+
+#if !defined(BL602)
+ case DMA_CMD_SET_ADD_MODE:
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ if (arg) {
+ regval |= DMA_DST_ADD_MODE;
+ } else {
+ regval &= ~DMA_DST_ADD_MODE;
+ }
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+ break;
+
+ case DMA_CMD_SET_REDUCE_MODE:
+ regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ if (arg) {
+ regval |= DMA_DST_MIN_MODE;
+ regval &= ~DMA_FIX_CNT_MASK;
+ regval |= (arg & 0x7) << DMA_FIX_CNT_SHIFT;
+ } else {
+ regval &= ~DMA_DST_MIN_MODE;
+ }
+ putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+ break;
+#endif
+ case DMA_CMD_SET_LLI_CONFIG:
+ arch_memcpy4((uint32_t *)(channel_base + DMA_CxSRCADDR_OFFSET), (uint32_t *)arg, 4);
+ break;
+ case DMA_CMD_GET_LLI_CONTROL:
+ return getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_ef_ctrl.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_ef_ctrl.c
new file mode 100644
index 00000000..3e858abc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_ef_ctrl.c
@@ -0,0 +1,932 @@
+#include "bflb_ef_ctrl.h"
+#include "hardware/ef_ctrl_reg.h"
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_EF_CTRL_BASE ((uint32_t)0x40007000)
+#elif defined(BL616) || defined(BL808) || defined(BL606P)
+#define BFLB_EF_CTRL_BASE ((uint32_t)0x20056000)
+#elif defined(BL628)
+#define BFLB_EF_CTRL_BASE ((uint32_t)0x2000C000)
+#endif
+
+#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24)
+#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8)
+#define EF_CTRL_OP_MODE_AUTO 0
+#define EF_CTRL_PARA_DFT 0
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EF_CLK 0
+#define EF_CTRL_SAHB_CLK 1
+#endif
+#define EF_CTRL_DFT_TIMEOUT_VAL (160 * 1000)
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EFUSE_R0_SIZE 128
+#elif defined(BL606P) || defined(BL808)
+#define EF_CTRL_EFUSE_R0_SIZE 128
+#define EF_CTRL_EFUSE_R1_SIZE 128
+#elif defined(BL616) || defined(BL628)
+#define EF_CTRL_EFUSE_R0_SIZE 512
+#else
+#define EF_CTRL_EFUSE_R0_SIZE 128
+#endif
+
+#ifndef BOOTROM
+#define EF_CTRL_LOAD_BEFORE_READ_R0 bflb_ef_ctrl_load_efuse_r0(dev)
+#define EF_CTRL_LOAD_BEFORE_READ_R1 bflb_ef_ctrl_load_efuse_r1(dev)
+#else
+#define EF_CTRL_LOAD_BEFORE_READ_R0
+#define EF_CTRL_LOAD_BEFORE_READ_R1
+#endif
+#define EF_CTRL_DATA0_CLEAR bflb_ef_ctrl_clear_data_reg0(dev)
+#define EF_CTRL_DATA1_CLEAR bflb_ef_ctrl_clear_data_reg1(dev)
+
+static int ATTR_TCM_SECTION bflb_ef_ctrl_busy(struct bflb_device_s *dev);
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+extern void bflb_efuse_switch_cpu_clock_save(void);
+extern void bflb_efuse_switch_cpu_clock_restore(void);
+#endif
+
+
+/****************************************************************************/ /**
+ * @brief Switch efuse region 0 control to AHB clock
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_switch_ahb_clk_r0(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+ uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+ while (bflb_ef_ctrl_busy(dev) == 1) {
+ timeout--;
+ if (timeout == 0) {
+ break;
+ }
+ }
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ /* Add delay for CLK to be stable */
+ arch_delay_us(4);
+}
+
+/****************************************************************************/ /**
+ * @brief Switch efuse region 1 control to AHB clock
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_switch_ahb_clk_r1(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+ uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+ while (bflb_ef_ctrl_busy(dev) == 1) {
+ timeout--;
+ if (timeout == 0) {
+ break;
+ }
+ }
+
+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+ so we select it(them) in ef_if_ctrl_0 */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_1_RW_POS) |
+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+ /* Add delay for CLK to be stable */
+ arch_delay_us(4);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Program efuse region 0
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r0(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ /* Select auto mode and select ef clock */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ /* Program */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (1 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (1 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ /* Add delay for POR to be stable */
+ arch_delay_us(4);
+
+ /* Trigger */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (1 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (1 << EF_CTRL_EF_IF_0_RW_POS) |
+ (1 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Program efuse region 1
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ /* Select auto mode and select ef clock */
+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+ so we select it(them) in ef_if_ctrl_0 */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_1_RW_POS) |
+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+ /* Program */
+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+ so we select it(them) in ef_if_ctrl_0 */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (1 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ /* Add delay for POR to be stable */
+ arch_delay_us(4);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+ (1 << EF_CTRL_EF_IF_1_RW_POS) |
+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+ (1 << EF_CTRL_EF_IF_1_RW_POS) |
+ (1 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Clear efuse region 0 data register
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_clear_data_reg0(struct bflb_device_s *dev)
+{
+ uint32_t *pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + 0x00);
+ uint32_t i = 0;
+
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+
+ /* Clear data */
+ for (i = 0; i < EF_CTRL_EFUSE_R0_SIZE / 4; i++) {
+ pefuse_start[i] = 0;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Clear efuse region 1 data register
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_clear_data_reg1(struct bflb_device_s *dev)
+{
+ uint32_t *pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + EF_CTRL_EFUSE_R0_SIZE);
+ uint32_t i = 0;
+
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+
+ /* Clear data */
+ for (i = 0; i < EF_CTRL_EFUSE_R1_SIZE / 4; i++) {
+ pefuse_start[i] = 0;
+ }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Load efuse region 0
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r0(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+ uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+ EF_CTRL_DATA0_CLEAR;
+
+ /* Trigger read */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (1 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ arch_delay_us(10);
+
+ /* Wait for efuse control idle */
+ do {
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+ timeout--;
+
+ if (timeout == 0) {
+ break;
+ }
+ } while ((reg_val & EF_CTRL_EF_IF_0_BUSY_MASK) || (!(reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK)));
+
+ /* Switch to AHB clock */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Load efuse region 0
+ *
+ * @param dev ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r1(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ EF_CTRL_DATA1_CLEAR;
+
+ /* Trigger read */
+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+ so we select it(them) in ef_if_ctrl_0 */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_1_RW_POS) |
+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_1_RW_POS) |
+ (1 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+ arch_delay_us(10);
+
+ /* Wait for efuse control idle */
+ do {
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+ } while (reg_val & EF_CTRL_EF_IF_1_BUSY_MASK);
+
+ do {
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+ } while (!(reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK));
+
+ /* Switch to AHB clock since often read efuse data after load */
+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+ so we select it(them) in ef_if_ctrl_0 */
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_0_RW_POS) |
+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+ (0 << EF_CTRL_EF_IF_1_RW_POS) |
+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+ putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Check efuse busy status
+ *
+ * @param dev ef control device pointer
+ *
+ * @return 1 for busy 0 for not
+ *
+*******************************************************************************/
+static int ATTR_TCM_SECTION bflb_ef_ctrl_busy(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ if (reg_val & EF_CTRL_EF_IF_0_BUSY_MASK) {
+ return 1;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Check efuse auto load done
+ *
+ * @param dev ef control device pointer
+ *
+ * @return 1 for auto load done 0 for not
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_ef_ctrl_autoload_done(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ // if (dev == NULL) {
+ // dev = bflb_device_get_by_name("ef_ctrl");
+ // }
+
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+ if (reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK) {
+ return 1;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief write data to efuse
+ *
+ * @param dev ef control device pointer
+ * @param offset: offset of efuse address to write
+ * @param pword: data pointer to buffer which is aligned to word
+ * @param count: count of data in words to write
+ * @param program: 1 for program to efuse,0 for not program now
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_write_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t program)
+{
+ uint32_t *pefuse_start = NULL;
+ uint32_t region0_count = 0, region1_count = 0;
+ uint32_t total_size = EF_CTRL_EFUSE_R0_SIZE;
+ uintptr_t irq_stat;
+
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ total_size += EF_CTRL_EFUSE_R1_SIZE;
+#else
+ (void)region1_count;
+#endif
+
+ if (offset > total_size || (offset + count * 4) > total_size || pword == NULL) {
+ return;
+ }
+
+ if (offset < EF_CTRL_EFUSE_R0_SIZE) {
+ if (offset + count * 4 <= EF_CTRL_EFUSE_R0_SIZE) {
+ region0_count = count;
+ } else {
+ region0_count = (EF_CTRL_EFUSE_R0_SIZE - offset) / 4;
+ region1_count = (offset + count * 4 - EF_CTRL_EFUSE_R0_SIZE) / 4;
+ }
+ } else {
+ region1_count = count;
+ }
+
+ // if (dev == NULL) {
+ // dev = bflb_device_get_by_name("ef_ctrl");
+ // }
+ pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + offset);
+
+ irq_stat = bflb_irq_save();
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_save();
+#endif
+ if (region0_count > 0) {
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+
+ arch_memcpy4(pefuse_start, pword, region0_count);
+ pefuse_start += region0_count;
+ pword += region0_count;
+
+ if (program) {
+ bflb_ef_ctrl_program_efuse_r0(dev);
+ arch_delay_us(100);
+ }
+ }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ if (region1_count > 0) {
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+
+ /* Add delay for CLK to be stable */
+ arch_delay_us(4);
+
+ arch_memcpy4(pefuse_start, pword, region1_count);
+
+ if (program) {
+ bflb_ef_ctrl_program_efuse_r1(dev);
+ arch_delay_us(100);
+ }
+ }
+#endif
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_restore();
+#endif
+
+ bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief Read data from efuse
+ *
+ * @param dev ef control device pointer
+ * @param offset: offset of efuse address to read
+ * @param pword: data pointer to buffer which is aligned to word
+ * @param count: count of data in words to read
+ * @param reload: 1 for reload before read,0 for not
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_read_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t reload)
+{
+ uint32_t *pefuse_start = NULL;
+ uint32_t region0_count = 0, region1_count = 0;
+ uint32_t total_size = EF_CTRL_EFUSE_R0_SIZE;
+ uintptr_t irq_stat;
+
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ total_size += EF_CTRL_EFUSE_R1_SIZE;
+#else
+ (void)region1_count;
+#endif
+
+ if (offset > total_size || (offset + count * 4) > total_size || pword == NULL) {
+ return;
+ }
+
+ if (offset < EF_CTRL_EFUSE_R0_SIZE) {
+ if (offset + count * 4 <= EF_CTRL_EFUSE_R0_SIZE) {
+ region0_count = count;
+ } else {
+ region0_count = (EF_CTRL_EFUSE_R0_SIZE - offset) / 4;
+ region1_count = (offset + count * 4 - EF_CTRL_EFUSE_R0_SIZE) / 4;
+ }
+ } else {
+ region1_count = count;
+ }
+
+ // if (dev == NULL) {
+ // dev = bflb_device_get_by_name("ef_ctrl");
+ // }
+ pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + offset);
+
+ irq_stat = bflb_irq_save();
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_save();
+#endif
+ if (region0_count > 0) {
+ if (reload) {
+ bflb_ef_ctrl_load_efuse_r0(dev);
+ } else {
+ bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+ }
+ arch_memcpy4(pword, pefuse_start, region0_count);
+ pword += region0_count;
+ pefuse_start += region0_count;
+ }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ if (region1_count > 0) {
+ if (reload) {
+ bflb_ef_ctrl_load_efuse_r1(dev);
+ } else {
+ bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+ }
+ arch_memcpy4(pword, pefuse_start, region0_count);
+ }
+#endif
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_restore();
+#endif
+
+ bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief Efuse read common trim value
+ *
+ * @param dev ef control device pointer
+ * @param name: Trim name
+ * @param trim: Trim data pointer
+ * @param reload: Reload efuse data before read
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_t *trim, uint8_t reload)
+{
+ uint32_t reg_val;
+ uint32_t i = 0;
+ const bflb_ef_ctrl_com_trim_cfg_t *trim_list = NULL;
+ uint32_t trim_list_len;
+ uintptr_t irq_stat;
+
+ // if (dev == NULL) {
+ // dev = bflb_device_get_by_name("ef_ctrl");
+ // }
+
+ irq_stat = bflb_irq_save();
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_save();
+#endif
+ if (reload) {
+ /* Trigger read data from efuse */
+ bflb_ef_ctrl_load_efuse_r0(dev);
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ bflb_ef_ctrl_load_efuse_r1(dev);
+#endif
+ }
+
+ trim->en = 0;
+ trim->parity = 0;
+ trim->empty = 1;
+ trim->len = 0;
+
+ trim_list_len = bflb_ef_ctrl_get_common_trim_list(&trim_list);
+
+ for (i = 0; i < trim_list_len; i++) {
+ if (arch_memcmp(name, trim_list[i].name, strlen(name)) == 0) {
+ /* switch clock */
+ if (trim_list[i].en_addr <= EF_CTRL_EFUSE_R0_SIZE) {
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+ }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ if (trim_list[i].en_addr > EF_CTRL_EFUSE_R0_SIZE) {
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+ }
+#endif
+ trim->len = trim_list[i].value_len;
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4);
+ if (reg_val & (1 << (trim_list[i].en_addr % 32))) {
+ trim->en = 1;
+ }
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4);
+ if (reg_val & (1 << (trim_list[i].parity_addr % 32))) {
+ trim->parity = 1;
+ }
+
+ if (((trim_list[i].value_addr % 32) + trim_list[i].value_len) > 32) {
+ uint64_t tmpval64 = (uint64_t)getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+ tmpval64 |= (((uint64_t)getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4 + 4)) << 32);
+ tmpval64 = tmpval64 >> (trim_list[i].value_addr % 32);
+ trim->value = (uint32_t)(tmpval64 & (((uint64_t)1 << trim_list[i].value_len) - 1));
+ } else {
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+ reg_val = reg_val >> (trim_list[i].value_addr % 32);
+ trim->value = reg_val & ((1 << trim_list[i].value_len) - 1);
+ }
+
+ if (trim->en == 0 && trim->parity == 0 && trim->value == 0) {
+ trim->empty = 1;
+ } else {
+ trim->empty = 0;
+ }
+
+ break;
+ }
+ }
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_restore();
+#endif
+ bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief Efuse write common trim value
+ *
+ * @param dev ef control device pointer
+ * @param name: Trim name
+ * @param trim: Trim data pointer
+ * @param program: program to efuse entity or not
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_write_common_trim(struct bflb_device_s *dev, char *name, uint32_t value, uint8_t program)
+{
+ uint32_t reg_val;
+ uint32_t i = 0;
+ uint8_t parity = 0;
+ const bflb_ef_ctrl_com_trim_cfg_t *trim_list = NULL;
+ uint32_t trim_list_len;
+ uintptr_t irq_stat;
+
+ // if (dev == NULL) {
+ // dev = bflb_device_get_by_name("ef_ctrl");
+ // }
+
+ trim_list_len = bflb_ef_ctrl_get_common_trim_list(&trim_list);
+
+ irq_stat = bflb_irq_save();
+ for (i = 0; i < trim_list_len; i++) {
+ if (memcmp(name, trim_list[i].name, strlen(name)) == 0) {
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_save();
+#endif
+ /* switch clock */
+ if (trim_list[i].en_addr <= EF_CTRL_EFUSE_R0_SIZE) {
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+ }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ if (trim_list[i].en_addr > EF_CTRL_EFUSE_R0_SIZE) {
+ /* Switch to AHB clock */
+ bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+ }
+#endif
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4);
+ reg_val |= (1 << (trim_list[i].en_addr % 32));
+ putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4, reg_val);
+
+ parity = bflb_ef_ctrl_get_trim_parity(value, trim_list[i].value_len);
+ if (parity) {
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4);
+ reg_val |= (1 << (trim_list[i].parity_addr % 32));
+ putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4, reg_val);
+ }
+
+ if (((trim_list[i].value_addr % 32) + trim_list[i].value_len) > 32) {
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+ reg_val |= (value << (trim_list[i].value_addr % 32));
+ putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4, reg_val);
+
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4) + 4;
+ reg_val |= (value >> (32 - (trim_list[i].value_addr % 32)));
+ putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4 + 4, reg_val);
+ } else {
+ reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+ reg_val |= (value << (trim_list[i].value_addr % 32));
+ putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4, reg_val);
+ }
+
+ if (program) {
+ /* program */
+ if (trim_list[i].en_addr <= EF_CTRL_EFUSE_R0_SIZE) {
+ bflb_ef_ctrl_program_efuse_r0(dev);
+ }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+ if (trim_list[i].en_addr > EF_CTRL_EFUSE_R0_SIZE) {
+ bflb_ef_ctrl_program_efuse_r1(dev);
+ }
+#endif
+ }
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_efuse_switch_cpu_clock_restore();
+#endif
+ break;
+ }
+ }
+ bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief Whether a value bits is all zero
+ *
+ * @param val: value to check
+ * @param start: start bit
+ * @param len: total length of bits to check
+ *
+ * @return 1 for all bits zero 0 for others
+ *
+*******************************************************************************/
+uint8_t ATTR_TCM_SECTION bflb_ef_ctrl_is_all_bits_zero(uint32_t val, uint8_t start, uint8_t len)
+{
+ uint32_t mask = 0;
+
+ val = (val >> start);
+
+ if (len >= 32) {
+ mask = 0xffffffff;
+ } else {
+ mask = (1 << len) - 1;
+ }
+
+ if ((val & mask) == 0) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Efuse Ctrl get zero bit count
+ *
+ * @param val: Value to count
+ *
+ * @return Zero bit count
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION bflb_ef_ctrl_get_byte_zero_cnt(uint8_t val)
+{
+ uint32_t cnt = 0;
+ uint32_t i = 0;
+
+ for (i = 0; i < 8; i++) {
+ if ((val & (1 << i)) == 0) {
+ cnt += 1;
+ }
+ }
+
+ return cnt;
+}
+
+/****************************************************************************/ /**
+ * @brief Analog Trim parity calculate
+ *
+ * @param val: Value of efuse trim data
+ * @param len: Length of bit to calculate
+ *
+ * @return Parity bit value
+ *
+*******************************************************************************/
+uint8_t ATTR_CLOCK_SECTION bflb_ef_ctrl_get_trim_parity(uint32_t val, uint8_t len)
+{
+ uint8_t cnt = 0;
+ uint8_t i = 0;
+
+ for (i = 0; i < len; i++) {
+ if (val & (1 << i)) {
+ cnt++;
+ }
+ }
+
+ return cnt & 0x01;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_emac.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_emac.c
new file mode 100644
index 00000000..f4d6809a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_emac.c
@@ -0,0 +1,879 @@
+/**
+ ******************************************************************************
+ * @file bflb_emac.c
+ * @version V1.0
+ * @date 2022-09-27
+ * @brief This file is the low hardware abstraction layer file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2022 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "bflb_emac.h"
+#include "bflb_clock.h"
+#include "bflb_l1c.h"
+#include "hardware/emac_reg.h"
+
+/* private definition */
+// #define TAG "EMAC_BD: "
+#define EMAC_TX_COMMON_FLAGS (EMAC_BD_TX_RD_MASK | EMAC_BD_TX_IRQ_MASK | EMAC_BD_TX_PAD_MASK | EMAC_BD_TX_CRC_MASK | EMAC_BD_TX_EOF_MASK)
+#define EMAC_RX_COMMON_FLAGS ((ETH_MAX_PACKET_SIZE << 16) | EMAC_BD_RX_IRQ_MASK)
+
+/**
+ * @brief Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern.
+ */
+struct bflb_emac_bd_desc_s {
+ uint32_t C_S_L; /*!< Buffer Descriptors(BD) control,status,length */
+ uint32_t Buffer; /*!< BD buffer address */
+};
+
+/**
+ * @brief emac handle type definition
+ * @param bd Tx descriptor header pointer
+ * @param tx_index_emac TX index: EMAC
+ * @param tx_index_cpu TX index: CPU/SW
+ * @param tx_buff_limit TX index max
+ * @param rsv0 rsv0
+ * @param rx_index_emac RX index: EMAC
+ * @param rx_index_cpu RX index: CPU/SW
+ * @param rx_buff_limit RX index max
+ * @param rsv1 rsv1
+ *
+ */
+struct bflb_emac_handle_s {
+ struct bflb_emac_bd_desc_s *bd;
+ uint8_t tx_index_emac;
+ uint8_t tx_index_cpu;
+ uint8_t tx_buff_limit;
+ uint8_t rsv0;
+ uint8_t rx_index_emac;
+ uint8_t rx_index_cpu;
+ uint8_t rx_buff_limit;
+ uint8_t rsv1;
+};
+
+static struct bflb_emac_handle_s eth_handle;
+static struct bflb_emac_handle_s *thiz = NULL;
+
+/**
+ *
+ * @brief get emac current active buffer describe index
+ * @param dev
+ * @param bdt @ref emac buffer descriptors type define
+ * @return uint32_t
+ *
+ */
+uint32_t bflb_emac_bd_get_cur_active(struct bflb_device_s *dev, uint8_t bdt)
+{
+ uint32_t bd = 0;
+ uint32_t reg_base;
+ reg_base = dev->reg_base;
+
+ bd = getreg32(reg_base + EMAC_TX_BD_NUM_OFFSET);
+
+ if (bdt == EMAC_BD_TYPE_TX) {
+ bd &= EMAC_TXBDPTR_MASK;
+ bd >>= EMAC_TXBDPTR_SHIFT;
+ }
+
+ if (bdt == EMAC_BD_TYPE_RX) {
+ bd &= EMAC_RXBDPTR_MASK;
+ bd >>= EMAC_RXBDPTR_SHIFT;
+ }
+
+ return bd;
+}
+/**
+ * @brief
+ *
+ * @param index
+ *
+ */
+void bflb_emac_bd_rx_enqueue(uint32_t index)
+{
+ thiz->rx_index_emac = index;
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ *
+ */
+void bflb_emac_bd_rx_on_err(uint32_t index)
+{
+ /* handle error */
+ if (thiz->bd[index].C_S_L & EMAC_BD_RX_OR_MASK) {
+ printf("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_RX_RE_MASK) {
+ printf("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_RX_DN_MASK) {
+ printf("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_RX_TL_MASK) {
+ printf("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_RX_CRC_MASK) {
+ printf("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_RX_LC_MASK) {
+ printf("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__);
+ }
+
+ thiz->bd[index].C_S_L &= ~0xff;
+ /* RX BD is ready for RX */
+ thiz->bd[index].C_S_L |= EMAC_BD_RX_E_MASK;
+}
+
+/**
+ * @brief this func will be called in ISR
+ *
+ * @param index
+ *
+ */
+void bflb_emac_bd_tx_dequeue(uint32_t index)
+{
+ struct bflb_emac_bd_desc_s *DMADesc;
+
+ thiz->tx_index_emac = index;
+ DMADesc = &thiz->bd[thiz->tx_index_emac];
+ /* release this tx BD to SW (HW will do this) */
+ DMADesc->C_S_L &= ~EMAC_BD_TX_RD_MASK;
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ * @return int
+ */
+void bflb_emac_bd_tx_on_err(uint32_t index)
+{
+ /* handle error */
+ if (thiz->bd[index].C_S_L & EMAC_BD_TX_UR_MASK) {
+ printf("%s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_TX_RTRY_MASK) {
+ printf("%s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_TX_RL_MASK) {
+ printf("%s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_TX_LC_MASK) {
+ printf("%s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_TX_DF_MASK) {
+ printf("%s:%d\r\n", __func__, __LINE__);
+ }
+
+ if (thiz->bd[index].C_S_L & EMAC_BD_TX_CS_MASK) {
+ printf("%s:%d\r\n", __func__, __LINE__);
+ }
+
+ thiz->bd[index].C_S_L &= ~0xff;
+}
+/**
+ * @brief
+ *
+ * @param none
+ * @return int
+ */
+int emac_bd_fragment_support(void)
+{
+#if defined(BL616) || defined(BL808)
+ return 1;
+#elif defined(BL702)
+ return 0;
+#elif defined(BL628)
+ return 1;
+#endif
+}
+/**
+ * @brief
+ *
+ * @param flags
+ * @param len
+ * @param data_in
+ * @return int
+ */
+int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
+{
+ uint32_t err = 0;
+ struct bflb_emac_bd_desc_s *DMADesc;
+ uint32_t tx_flags = EMAC_TX_COMMON_FLAGS;
+ DMADesc = &thiz->bd[thiz->tx_index_cpu];
+
+ if (flags & EMAC_FRAGMENT_PACKET) {
+ /* Fragment packet, clear EOF */
+ tx_flags &= ~EMAC_BD_TX_EOF_MASK;
+ }
+
+ if (DMADesc->C_S_L & EMAC_BD_TX_RD_MASK) {
+ /* no free BD, lost sync with DMA TX? */
+ err = 4;
+ //printf(TAG"%s:%d\n", __func__, __LINE__);
+ } else {
+#if defined(BL616)
+ __ASM volatile("fence");
+#endif
+ // printf("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in);
+ if (flags & EMAC_NOCOPY_PACKET) {
+ DMADesc->Buffer = (uint32_t)(uintptr_t)data_in;
+ } else {
+ // memcpy((void *)(uintptr_t)(DMADesc->Buffer), data_in, len);
+ arch_memcpy_fast((void *)(uintptr_t)(DMADesc->Buffer), data_in, len);
+ }
+
+#ifdef EMAC_DO_FLUSH_DATA
+#if defined(BL616)
+ bflb_l1c_dcache_invalidate_range((void *)DMADesc->Buffer, len);
+#endif
+#endif
+ DMADesc->C_S_L = tx_flags | (len << EMAC_BD_TX_LEN_SHIFT);
+
+ /* move to next TX BD */
+ if ((++thiz->tx_index_cpu) > thiz->tx_buff_limit) {
+ /* the last BD */
+ DMADesc->C_S_L |= EMAC_BD_TX_WR_MASK;
+ /* wrap back */
+ thiz->tx_index_cpu = 0;
+ }
+ }
+
+ return err;
+}
+
+/**
+ * @brief
+ *
+ * @param flags
+ * @param len
+ * @param data_out
+ * @return int
+ */
+int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out)
+{
+ uint32_t err = 0;
+ struct bflb_emac_bd_desc_s *DMADesc;
+
+ DMADesc = &thiz->bd[thiz->rx_index_cpu];
+
+ if (DMADesc->C_S_L & EMAC_BD_RX_E_MASK) {
+ /* current RX BD is empty */
+ err = 4;
+ *len = 0;
+ } else {
+ *len = (thiz->bd[thiz->rx_index_cpu].C_S_L & EMAC_BD_RX_LEN_MASK) >> EMAC_BD_RX_LEN_SHIFT;
+#ifdef EMAC_DO_FLUSH_DATA
+#if defined(BL616)
+ bflb_l1c_dcache_invalidate_range((void *)DMADesc->Buffer, *len);
+#endif
+#endif
+ if (data_out) {
+ // memcpy(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len);
+ arch_memcpy_fast(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len);
+ }
+
+ /* RX BD can be used for another receive */
+ DMADesc->C_S_L |= EMAC_BD_RX_E_MASK;
+
+ /* move to next RX BD */
+ if ((++thiz->rx_index_cpu) > thiz->rx_buff_limit) {
+ /* the last BD */
+ DMADesc->C_S_L |= EMAC_BD_RX_WR_MASK;
+ /* wrap back */
+ thiz->rx_index_cpu = thiz->tx_buff_limit + 1;
+ }
+ }
+
+ return err;
+}
+
+/**
+ * @brief bflb emac init
+ *
+ * @param dev
+ * @param config
+ *
+ */
+void bflb_emac_init(struct bflb_device_s *dev, const struct bflb_emac_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t reg_val;
+
+#if defined(BL616) || defined(BL808)
+#define GLB_EMAC_CLK_OUT_ADDRESS (0x20000390)
+#define GLB_UNGATE_CFG2_ADDRESS (0x20000588)
+
+ /* GLB select inside clock or Not */
+ reg_val = getreg32(GLB_EMAC_CLK_OUT_ADDRESS);
+ if (config->inside_clk == EMAC_CLK_USE_INTERNAL) {
+ reg_val |= (1 << 5);
+ reg_val |= (1 << 6);
+ reg_val &= ~(1 << 7);
+ reg_val |= (1 << 10);
+ } else {
+ reg_val &= ~(1 << 5);
+ reg_val &= ~(1 << 6);
+ reg_val &= ~(1 << 7);
+ }
+ putreg32(reg_val, GLB_EMAC_CLK_OUT_ADDRESS);
+
+ /* ungate emac clock */
+ reg_val = getreg32(GLB_UNGATE_CFG2_ADDRESS);
+ reg_val |= (1 << 23);
+ putreg32(reg_val, GLB_UNGATE_CFG2_ADDRESS);
+#elif defined(BL702)
+ /* enable audio clock and GLB select inside clock or Not */
+// #define PDS_AUDIO_PLL_EN_ADDRESS (0x4000E41C)
+#define GLB_UNGATE_CFG1_ADDRESS (0x40000024)
+#define GLB_CLOCK_CFG3_ADDRESS (0x4000000C)
+
+ // reg_val = getreg32(PDS_AUDIO_PLL_EN_ADDRESS);
+ // reg_val |= (1 << 7);
+ // putreg32(reg_val, PDS_AUDIO_PLL_EN_ADDRESS);
+
+ reg_val = getreg32(GLB_CLOCK_CFG3_ADDRESS);
+ if (config->inside_clk == EMAC_CLK_USE_INTERNAL) {
+ reg_val |= (1 << 5);
+ } else {
+ reg_val &= ~(1 << 5);
+ }
+ putreg32(reg_val, GLB_CLOCK_CFG3_ADDRESS);
+
+ /* ungate emac clock */
+ reg_val = getreg32(GLB_UNGATE_CFG1_ADDRESS);
+ reg_val |= (1 << 0x0d);
+ putreg32(reg_val, GLB_UNGATE_CFG1_ADDRESS);
+#endif
+
+ reg_base = dev->reg_base;
+ /* set mac defualt config , enable rmii and other*/
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ reg_val |= (EMAC_RMII_EN);
+ reg_val |= (EMAC_PRO);
+ reg_val |= (EMAC_BRO);
+ reg_val &= ~(EMAC_NOPRE);
+ reg_val |= (EMAC_PAD);
+ reg_val |= (EMAC_CRCEN);
+ reg_val &= ~(EMAC_HUGEN);
+ reg_val |= (EMAC_RECSMALL);
+ reg_val |= (EMAC_IFG);
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+
+ /* set inter frame gap defualt value */
+ reg_val = getreg32(reg_base + EMAC_IPGT_OFFSET);
+ reg_val &= ~(EMAC_IPGT_MASK);
+ reg_val |= (0x18) << EMAC_IPGT_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_IPGT_OFFSET);
+
+ /* set MII interface */
+ reg_val = getreg32(reg_base + EMAC_MIIMODE_OFFSET);
+ reg_val |= EMAC_MIINOPRE;
+ reg_val &= ~(EMAC_CLKDIV_MASK);
+ reg_val |= (config->mii_clk_div) << EMAC_CLKDIV_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_MIIMODE_OFFSET);
+
+ /* set collision */
+ reg_val = getreg32(reg_base + EMAC_COLLCONFIG_OFFSET);
+ reg_val &= ~(EMAC_MAXFL_MASK | EMAC_COLLVALID_MASK);
+ reg_val |= (0xf) << EMAC_MAXFL_SHIFT;
+ reg_val |= (0x10) << EMAC_COLLVALID_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_COLLCONFIG_OFFSET);
+
+ /* set frame length */
+ reg_val = getreg32(reg_base + EMAC_PACKETLEN_OFFSET);
+ reg_val &= ~(EMAC_MINFL_MASK | EMAC_MAXFL_MASK);
+ reg_val |= (config->min_frame_len) << EMAC_MINFL_SHIFT;
+ reg_val |= (config->max_frame_len) << EMAC_MAXFL_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_PACKETLEN_OFFSET);
+
+ /* set emac address */
+ reg_val = getreg32(reg_base + EMAC_MAC_ADDR0_OFFSET);
+ reg_val &= ~(EMAC_MAC_B2_MASK | EMAC_MAC_B3_MASK | EMAC_MAC_B4_MASK | EMAC_MAC_B5_MASK);
+ reg_val |= (config->mac_addr[5]) << EMAC_MAC_B5_SHIFT;
+ reg_val |= (config->mac_addr[4]) << EMAC_MAC_B4_SHIFT;
+ reg_val |= (config->mac_addr[3]) << EMAC_MAC_B3_SHIFT;
+ reg_val |= (config->mac_addr[2]) << EMAC_MAC_B2_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_MAC_ADDR0_OFFSET);
+ reg_val = getreg32(reg_base + EMAC_MAC_ADDR1_OFFSET);
+ reg_val &= ~(EMAC_MAC_B0_MASK | EMAC_MAC_B1_MASK);
+ reg_val |= (config->mac_addr[1]) << EMAC_MAC_B1_SHIFT;
+ reg_val |= (config->mac_addr[0]) << EMAC_MAC_B0_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_MAC_ADDR1_OFFSET);
+}
+
+/**
+ * @brief bflb emac deinit
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_deinit(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t reg_val;
+
+ reg_base = dev->reg_base;
+
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ reg_val &= ~(EMAC_TX_EN | EMAC_RX_EN);
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac interrupt enable
+ *
+ * @param dev
+ * @param flag
+ * @param enable
+ *
+ */
+void bflb_emac_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t reg_val_mask; // reg_val_en;
+
+ reg_base = dev->reg_base;
+ reg_val_mask = getreg32(reg_base + EMAC_INT_MASK_OFFSET);
+ if (enable) {
+ reg_val_mask &= ~(flag);
+ } else {
+ reg_val_mask |= (flag);
+ }
+ putreg32(reg_val_mask, reg_base + EMAC_INT_MASK_OFFSET);
+};
+
+/**
+ * @brief bflb emac interrupt clear
+ *
+ * @param dev
+ * @param flag
+ *
+ */
+void bflb_emac_int_clear(struct bflb_device_s *dev, uint32_t flag)
+{
+ putreg32(flag, dev->reg_base + EMAC_INT_SOURCE_OFFSET);
+}
+
+/**
+ * @brief bflb emac get interrupt status
+ *
+ * @param dev
+ * @return uint32_t
+ */
+uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t reg_sts_val, reg_mask_val;
+
+ reg_base = dev->reg_base;
+ reg_sts_val = getreg32(reg_base + EMAC_INT_SOURCE_OFFSET);
+ reg_mask_val = getreg32(reg_base + EMAC_INT_MASK_OFFSET);
+
+ return (reg_sts_val & (~reg_mask_val));
+}
+
+/**
+ * @brief emac dma description list init
+ *
+ * @param reg_base
+ * @param handle
+ * @param tx_buff
+ * @param tx_buff_cnt
+ * @param rx_buff
+ * @param rx_buff_cnt
+ *
+ */
+static void emac_dma_desc_list_init(uint32_t reg_base, struct bflb_emac_handle_s *handle, uint8_t *tx_buff, uint32_t tx_buff_cnt, uint8_t *rx_buff, uint32_t rx_buff_cnt)
+{
+ uint32_t i = 0;
+
+ /* Set the Ethernet handler env */
+ handle->bd = (struct bflb_emac_bd_desc_s *)(uintptr_t)(reg_base + EMAC_DMA_DESC_OFFSET);
+ handle->tx_index_emac = 0;
+ handle->tx_index_cpu = 0;
+ handle->tx_buff_limit = tx_buff_cnt - 1;
+ /* The receive descriptors' address starts right after the last transmit BD. */
+ handle->rx_index_emac = tx_buff_cnt;
+ handle->rx_index_cpu = tx_buff_cnt;
+ handle->rx_buff_limit = tx_buff_cnt + rx_buff_cnt - 1;
+
+ /* Fill each DMARxDesc descriptor with the right values */
+ for (i = 0; i < tx_buff_cnt; i++) {
+ /* Get the pointer on the ith member of the Tx Desc list */
+ handle->bd[i].Buffer = (NULL == tx_buff) ? 0 : (uint32_t)(uintptr_t)(tx_buff + (ETH_MAX_PACKET_SIZE * i));
+ handle->bd[i].C_S_L = 0;
+ }
+
+ /* For the last TX DMA Descriptor, it should be wrap back */
+ handle->bd[handle->tx_buff_limit].C_S_L |= EMAC_BD_TX_WR_MASK;
+
+ for (i = tx_buff_cnt; i < (tx_buff_cnt + rx_buff_cnt); i++) {
+ /* Get the pointer on the ith member of the Rx Desc list */
+ handle->bd[i].Buffer = (NULL == rx_buff) ? 0 : (uint32_t)(uintptr_t)(rx_buff + (ETH_MAX_PACKET_SIZE * (i - tx_buff_cnt)));
+ handle->bd[i].C_S_L = (ETH_MAX_PACKET_SIZE << 16) | EMAC_BD_RX_IRQ_MASK | EMAC_BD_RX_E_MASK;
+ }
+
+ /* For the last RX DMA Descriptor, it should be wrap back */
+ handle->bd[handle->rx_buff_limit].C_S_L |= EMAC_BD_RX_WR_MASK;
+
+ /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/
+ putreg32(tx_buff_cnt, reg_base + EMAC_TX_BD_NUM_OFFSET);
+}
+
+/**
+ * @brief emac buffer description init
+ *
+ * @param eth_tx_buff
+ * @param tx_buf_count
+ * @param eth_rx_buff
+ * @param rx_buf_count
+ *
+ */
+void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count)
+{
+ thiz = ð_handle;
+ uint32_t reg_base;
+ reg_base = dev->reg_base;
+ /* init the BDs in emac with buffer address */
+ emac_dma_desc_list_init(reg_base, thiz, (uint8_t *)eth_tx_buff, tx_buf_count, (uint8_t *)eth_rx_buff, rx_buf_count);
+}
+
+/**
+ * @brief bflb emac phy register read
+ *
+ * @param dev
+ * @param phy_reg
+ * @param phy_reg_val
+ * @return int
+ *
+ */
+int bflb_emac_phy_reg_read(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t *phy_reg_val)
+{
+ uint32_t reg_val;
+
+ /* Set Register Address */
+ reg_val = getreg32(dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+ reg_val &= ~(EMAC_RGAD_MASK);
+ reg_val |= ((uint32_t)phy_reg << EMAC_RGAD_SHIFT);
+ putreg32(reg_val, dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+
+ /* Trigger read */
+ reg_val = getreg32(dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+ reg_val |= (EMAC_RSTAT);
+ putreg32(reg_val, dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+
+ do {
+ reg_val = getreg32(dev->reg_base + EMAC_MIISTATUS_OFFSET);
+ bflb_mtimer_delay_us(16);
+ } while ((reg_val & (EMAC_MIIM_BUSY)) != 0);
+
+ *phy_reg_val = getreg32(dev->reg_base + EMAC_MIIRX_DATA_OFFSET);
+
+ return 0;
+}
+
+/**
+ * @brief bflb emac phy register write
+ *
+ * @param dev
+ * @param phy_reg
+ * @param phy_reg_val
+ * @return int
+ *
+ */
+int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t phy_reg_val)
+{
+ uint32_t reg_val;
+
+ /* Set Register Address */
+ reg_val = getreg32(dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+ reg_val &= ~(EMAC_RGAD_MASK);
+ reg_val |= ((uint32_t)phy_reg << EMAC_RGAD_SHIFT);
+ putreg32(reg_val, dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+
+ /* Set Write data */
+ putreg32(phy_reg_val, dev->reg_base + EMAC_MIITX_DATA_OFFSET);
+
+ /* Trigger write */
+ reg_val = getreg32(dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+ reg_val |= (EMAC_WCTRLDATA);
+ putreg32(reg_val, dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+
+ do {
+ reg_val = getreg32(dev->reg_base + EMAC_MIISTATUS_OFFSET);
+ bflb_mtimer_delay_us(16);
+ } while ((reg_val & (EMAC_MIIM_BUSY)) != 0);
+
+ return 0;
+}
+
+/**
+ * @brief bflb emac feature control
+ *
+ * @param dev
+ * @param cmd
+ * @param arg
+ * @return int
+ *
+ */
+int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_val;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ switch (cmd) {
+ case EMAC_CMD_NO_PREAMBLE_MODE:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_NOPRE;
+ } else {
+ reg_val &= ~(EMAC_NOPRE);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_EN_PROMISCUOUS:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_PRO;
+ } else {
+ reg_val &= ~(EMAC_PRO);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_FRAME_GAP_CHECK:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_IFG;
+ } else {
+ reg_val &= ~(EMAC_IFG);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_FULL_DUPLEX:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_FULLD;
+ } else {
+ reg_val &= ~(EMAC_FULLD);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_EN_TX_CRC_FIELD:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_CRCEN;
+ } else {
+ reg_val &= ~(EMAC_CRCEN);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_RECV_HUGE_FRAMES:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_HUGEN;
+ } else {
+ reg_val &= ~(EMAC_HUGEN);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_EN_AUTO_PADDING:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_PAD;
+ } else {
+ reg_val &= ~(EMAC_PAD);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_RECV_SMALL_FRAME:
+ reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+ if (arg) {
+ reg_val |= EMAC_RECSMALL;
+ } else {
+ reg_val &= ~(EMAC_RECSMALL);
+ }
+ putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+ break;
+
+ case EMAC_CMD_SET_PHY_ADDRESS:
+ reg_val = getreg32(reg_base + EMAC_MIIADDRESS_OFFSET);
+ reg_val &= ~(EMAC_FIAD_MASK);
+ reg_val |= (uint32_t)(arg << EMAC_FIAD_SHIFT);
+ putreg32(reg_val, reg_base + EMAC_MIIADDRESS_OFFSET);
+ break;
+
+ case EMAC_CMD_SET_MAXRET:
+ reg_val = getreg32(reg_base + EMAC_COLLCONFIG_OFFSET);
+ reg_val &= ~(EMAC_MAXFL_MASK);
+ reg_val |= (arg) << EMAC_MAXFL_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_COLLCONFIG_OFFSET);
+ break;
+
+ case EMAC_CMD_SET_COLLVALID:
+ reg_val = getreg32(reg_base + EMAC_COLLCONFIG_OFFSET);
+ reg_val &= ~(EMAC_COLLVALID_MASK);
+ reg_val |= (arg) << EMAC_COLLVALID_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_COLLCONFIG_OFFSET);
+ break;
+
+ case EMAC_CMD_SET_PACKET_GAP:
+ reg_val = getreg32(reg_base + EMAC_IPGT_OFFSET);
+ reg_val &= ~(EMAC_IPGT_MASK);
+ reg_val |= (arg) << EMAC_IPGT_SHIFT;
+ putreg32(reg_val, reg_base + EMAC_IPGT_OFFSET);
+ break;
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
+
+/**
+ * @brief bflb emac stop
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_stop(struct bflb_device_s *dev)
+{
+ /* disable emac */
+ uint32_t reg_val;
+
+ reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+ reg_val &= ~(EMAC_TX_EN | EMAC_RX_EN);
+ putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac start
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_start(struct bflb_device_s *dev)
+{
+ /* enable emac */
+ uint32_t reg_val;
+
+ reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+ reg_val |= (EMAC_TX_EN | EMAC_RX_EN);
+ putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac start tx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_start_tx(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+ reg_val |= (EMAC_TX_EN);
+ putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac stop tx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_stop_tx(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+ reg_val &= ~(EMAC_TX_EN);
+ putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac start rx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_start_rx(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+ reg_val |= (EMAC_RX_EN);
+ putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac stop rx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_stop_rx(struct bflb_device_s *dev)
+{
+ uint32_t reg_val;
+
+ reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+ reg_val &= ~(EMAC_RX_EN);
+ putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_flash.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_flash.c
new file mode 100644
index 00000000..6229cfeb
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_flash.c
@@ -0,0 +1,809 @@
+
+#if defined(BL616)
+#include "bl616_memorymap.h"
+#include "bl616_glb.h"
+#include "bl616_ef_cfg.h"
+#elif defined(BL606P)
+#include "bl606p_memorymap.h"
+#include "bl606p_glb.h"
+#elif defined(BL808)
+#include "bl808_memorymap.h"
+#include "bl808_glb.h"
+#elif defined(BL702L)
+#include "bl702l_glb.h"
+#include "bl702l_ef_ctrl.h"
+#elif defined(BL602)
+#include "bl602_glb.h"
+#include "bl602_sflash_ext.h"
+#include "bl602_xip_sflash_ext.h"
+#include "bl602_sf_cfg_ext.h"
+#elif defined(BL702)
+#include "bl702_glb.h"
+#include "bl702_xip_sflash_ext.h"
+#include "bl702_sf_cfg_ext.h"
+#endif
+#include "bflb_xip_sflash.h"
+#include "bflb_sf_cfg.h"
+#include "bflb_flash.h"
+#include "hardware/sf_ctrl_reg.h"
+
+#if defined(BL616)
+static uint32_t flash1_size = 4 * 1024 * 1024;
+static uint32_t flash2_size = 2 * 1024 * 1024;
+static uint32_t g_jedec_id2 = 0;
+#endif
+static uint32_t g_jedec_id = 0;
+static spi_flash_cfg_type g_flash_cfg = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc8,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 0,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = 0x11,
+ .clk_delay = 0,
+ .clk_invert = 0x03,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+#if defined(BL616)
+static spi_flash_cfg_type g_flash2_cfg = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc8,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 0,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = 0x10,
+ .clk_delay = 0,
+ .clk_invert = 0x03,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static bflb_efuse_device_info_type deviceInfo;
+#endif
+
+#if defined(BL616)
+uint32_t bflb_flash2_get_jedec_id(void)
+{
+ uint32_t jid = 0;
+
+ jid = ((g_jedec_id2 & 0xff) << 16) + (g_jedec_id2 & 0xff00) + ((g_jedec_id2 & 0xff0000) >> 16);
+ return jid;
+}
+#endif
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL702L)
+static int flash_get_clock_delay(spi_flash_cfg_type *cfg)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+ /* bit0-3 for clk delay */
+ if (regval & SF_CTRL_SF_IF_READ_DLY_EN) {
+ cfg->clk_delay = ((regval & SF_CTRL_SF_IF_READ_DLY_N_MASK) >> SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1;
+ } else {
+ cfg->clk_delay = 0;
+ }
+ cfg->clk_invert = 0;
+ /* bit0 for clk invert */
+ cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_OUT_INV_SEL) ? 1 : 0) << 0);
+ /* bit1 for rx clk invert */
+ cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_SF_RX_INV_SEL) ? 1 : 0) << 1);
+
+ regval = getreg32(reg_base + SF_CTRL_SF_IF_IO_DLY_1_OFFSET);
+ /* bit4-6 for do delay */
+ cfg->clk_delay |= (((regval & SF_CTRL_SF_IO_0_DO_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DO_DLY_SEL_SHIFT) << 4);
+ /* bit2-4 for di delay */
+ cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_DI_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DI_DLY_SEL_SHIFT) << 2);
+ /* bit5-7 for oe delay */
+ cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_OE_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_OE_DLY_SEL_SHIFT) << 5);
+
+ return 0;
+}
+#endif
+
+static void ATTR_TCM_SECTION flash_set_qspi_enable(spi_flash_cfg_type *p_flash_cfg)
+{
+ if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
+ bflb_sflash_qspi_enable(p_flash_cfg);
+ }
+}
+
+static void ATTR_TCM_SECTION flash_set_l1c_wrap(spi_flash_cfg_type *p_flash_cfg)
+{
+ if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
+ L1C_Set_Wrap(ENABLE);
+ bflb_sflash_set_burst_wrap(p_flash_cfg);
+ } else {
+ L1C_Set_Wrap(DISABLE);
+ bflb_sflash_disable_burst_wrap(p_flash_cfg);
+ }
+}
+
+/**
+ * @brief flash_config_init
+ *
+ * @return int
+ */
+static int ATTR_TCM_SECTION flash_config_init(spi_flash_cfg_type *p_flash_cfg, uint8_t *jedec_id)
+{
+ int ret = -1;
+ uint8_t is_aes_enable = 0;
+ uint32_t jid = 0;
+ uint32_t offset = 0;
+ uintptr_t flag;
+
+ flag = bflb_irq_save();
+ bflb_xip_sflash_opt_enter(&is_aes_enable);
+ bflb_xip_sflash_state_save(p_flash_cfg, &offset, 0, 0);
+ bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jid);
+ arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
+ jid &= 0xFFFFFF;
+ g_jedec_id = jid;
+ ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jid, p_flash_cfg, 0, 0);
+ if (ret == 0) {
+ p_flash_cfg->mid = (jid & 0xff);
+ }
+
+ // p_flash_cfg->io_mode = 0x11;
+ // p_flash_cfg->c_read_support = 0x00;
+
+ /* Set flash controler from p_flash_cfg */
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+ bflb_flash_set_cmds(p_flash_cfg);
+#endif
+ flash_set_qspi_enable(p_flash_cfg);
+ flash_set_l1c_wrap(p_flash_cfg);
+#if defined(BL602)
+ bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, 0, 0);
+#else
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, 0, 0);
+#endif
+ bflb_xip_sflash_opt_exit(is_aes_enable);
+ bflb_irq_restore(flag);
+
+ return ret;
+}
+
+#if defined(BL616)
+/**
+ * @brief flash2 init
+ *
+ * @return int
+ */
+static int ATTR_TCM_SECTION flash2_init(void)
+{
+ int stat = -1;
+ uint32_t ret = 0;
+ uint32_t jid = 0;
+
+ struct sf_ctrl_bank2_cfg sf_bank2_cfg;
+ struct sf_ctrl_cmds_cfg cmds_cfg;
+
+ sf_bank2_cfg.sbus2_select = 1;
+ sf_bank2_cfg.bank2_rx_clk_invert_src = 0;
+ sf_bank2_cfg.bank2_rx_clk_invert_sel = 0;
+ sf_bank2_cfg.bank2_delay_src = 0;
+ sf_bank2_cfg.bank2_clk_delay = 1;
+ sf_bank2_cfg.do_delay = 0;
+ sf_bank2_cfg.di_delay = 0;
+ sf_bank2_cfg.oe_delay = 0;
+ sf_bank2_cfg.remap = SF_CTRL_REMAP_4MB;
+ sf_bank2_cfg.remap_lock = 1;
+
+ cmds_cfg.ack_latency = 1;
+ cmds_cfg.cmds_core_en = 1;
+ cmds_cfg.cmds_en = 1;
+ cmds_cfg.cmds_wrap_mode = 1;
+ cmds_cfg.cmds_wrap_len = SF_CTRL_WRAP_LEN_4096;
+
+ if (deviceInfo.memoryInfo == 0) {
+ /* memoryInfo==0, external flash */
+ flash1_size = 64 * 1024 * 1024;
+ flash2_size = 0;
+ } else if (deviceInfo.memoryInfo == 1) {
+ flash1_size = 2 * 1024 * 1024;
+ flash2_size = 0;
+ } else if (deviceInfo.memoryInfo == 2) {
+ flash1_size = 4 * 1024 * 1024;
+ flash2_size = 0;
+ } else if (deviceInfo.memoryInfo == 3) {
+ /* memoryInfo==3, embedded 4MB+2MB flash */
+ flash1_size = 4 * 1024 * 1024;
+ flash2_size = 2 * 1024 * 1024;
+ } else {
+ flash1_size = 8 * 1024 * 1024;
+ flash2_size = 0;
+ }
+
+ if (flash2_size > 0) {
+ bflb_sf_cfg_sbus2_flash_init(SF_IO_EMB_SWAP_IO3IO0_AND_SF2, &sf_bank2_cfg);
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ ret = bflb_sf_cfg_flash_identify_ext(0, SF_IO_EMB_SWAP_IO3IO0_AND_SF2, 0, &g_flash2_cfg, 0, SF_CTRL_FLASH_BANK1);
+ if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) {
+ return -1;
+ }
+ g_flash2_cfg.io_mode = 0x11;
+ g_flash2_cfg.c_read_support = 0;
+ g_flash2_cfg.c_read_mode = 0xff;
+ bflb_sflash_get_jedecid(&g_flash2_cfg, (uint8_t *)&jid);
+ jid &= 0xFFFFFF;
+ g_jedec_id2 = jid;
+
+ bflb_sf_ctrl_cmds_set(&cmds_cfg, SF_CTRL_FLASH_BANK1);
+ stat = bflb_sflash_xip_read_enable(&g_flash2_cfg, (g_flash2_cfg.io_mode & 0xf), 0, SF_CTRL_FLASH_BANK1);
+ if (0 != stat) {
+ return -1;
+ }
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ }
+
+ return 0;
+}
+#endif
+
+/**
+ * @brief multi flash adapter
+ *
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_init(void)
+{
+ int ret = -1;
+ uint32_t jedec_id = 0;
+#if defined(BL602) || defined(BL702)
+ uint8_t clk_delay = 1;
+ uint8_t clk_invert = 1;
+ uintptr_t flag;
+#endif
+
+#if defined(BL616)
+ bflb_ef_ctrl_get_device_info(&deviceInfo);
+#endif
+
+#if defined(BL602) || defined(BL702)
+ flag = bflb_irq_save();
+#if defined(BL602)
+ bflb_sflash_cache_flush();
+#else
+ L1C_Cache_Flush();
+#endif
+ bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
+#if defined(BL602)
+ bflb_sflash_cache_flush();
+#else
+ L1C_Cache_Flush();
+#endif
+ bflb_irq_restore(flag);
+ if (g_flash_cfg.mid != 0xff && g_flash_cfg.mid != 0x00) {
+ return 0;
+ }
+ clk_delay = g_flash_cfg.clk_delay;
+ clk_invert = g_flash_cfg.clk_invert;
+ g_flash_cfg.io_mode &= 0x0f;
+
+ ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
+
+ g_flash_cfg.clk_delay = clk_delay;
+ g_flash_cfg.clk_invert = clk_invert;
+#else
+ jedec_id = GLB_Get_Flash_Id_Value();
+ if (jedec_id != 0) {
+ ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
+ if (ret == 0) {
+ g_jedec_id = jedec_id;
+ g_flash_cfg.io_mode &= 0x0f;
+ flash_get_clock_delay(&g_flash_cfg);
+#if defined(BL616)
+ flash2_init();
+#endif
+ return 0;
+ }
+ }
+
+ g_flash_cfg.io_mode &= 0x0f;
+ ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
+
+ g_flash_cfg.io_mode &= 0x0f;
+ flash_get_clock_delay(&g_flash_cfg);
+ GLB_Set_Flash_Id_Value(g_jedec_id);
+#endif
+
+#if defined(BL616)
+ flash2_init();
+#endif
+
+ return ret;
+}
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+void ATTR_TCM_SECTION bflb_flash_set_cmds(spi_flash_cfg_type *p_flash_cfg)
+{
+ struct sf_ctrl_cmds_cfg cmds_cfg;
+
+ cmds_cfg.ack_latency = 1;
+ cmds_cfg.cmds_core_en = 1;
+ cmds_cfg.cmds_en = 1;
+ cmds_cfg.cmds_wrap_mode = 1;
+ cmds_cfg.cmds_wrap_len = 9;
+
+ if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
+ cmds_cfg.cmds_wrap_mode = 2;
+ cmds_cfg.cmds_wrap_len = 2;
+ }
+ bflb_sf_ctrl_cmds_set(&cmds_cfg, 0);
+}
+#endif
+
+uint32_t bflb_flash_get_jedec_id(void)
+{
+ uint32_t jid = 0;
+
+ jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
+ return jid;
+}
+
+void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
+{
+ *cfg_addr = (uint8_t *)&g_flash_cfg;
+ *len = sizeof(spi_flash_cfg_type);
+}
+
+void ATTR_TCM_SECTION bflb_flash_set_iomode(uint8_t iomode)
+{
+ uintptr_t flag = 0;
+ uint8_t is_aes_enable = 0;
+ uint32_t offset = 0;
+
+ flag = bflb_irq_save();
+ bflb_xip_sflash_opt_enter(&is_aes_enable);
+ bflb_xip_sflash_state_save(&g_flash_cfg, &offset, 0, 0);
+
+ g_flash_cfg.io_mode &= ~0x1f;
+ if (iomode&4) {
+ g_flash_cfg.io_mode |= iomode;
+ } else {
+ g_flash_cfg.io_mode |= 0x10;
+ g_flash_cfg.io_mode |= iomode;
+ }
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+ bflb_flash_set_cmds(&g_flash_cfg);
+#endif
+ flash_set_qspi_enable(&g_flash_cfg);
+ flash_set_l1c_wrap(&g_flash_cfg);
+#if defined(BL602)
+ bflb_xip_sflash_state_restore_ext(&g_flash_cfg, offset, 0, 0);
+#else
+ bflb_xip_sflash_state_restore(&g_flash_cfg, offset, 0, 0);
+#endif
+ bflb_xip_sflash_opt_exit(is_aes_enable);
+ bflb_irq_restore(flag);
+}
+
+ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void)
+{
+ return bflb_sf_ctrl_get_flash_image_offset(0, 0);
+}
+
+/**
+ * @brief erase flash via sbus
+ *
+ * @param flash absolute startaddr
+ * @param flash absolute endaddr
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len)
+{
+ int stat = -1;
+ uintptr_t flag;
+
+#if defined(BL616)
+ if ((startaddr + len) > (flash1_size + flash2_size)) {
+ return -ENOMEM;
+ } else if ((startaddr + len) <= flash1_size) {
+ flag = bflb_irq_save();
+ stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
+ bflb_irq_restore(flag);
+ } else if (startaddr >= flash1_size) {
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ stat = bflb_sflash_erase(&g_flash2_cfg, startaddr, startaddr + len - 1);
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ } else {
+ flag = bflb_irq_save();
+ stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, flash1_size - startaddr, 0, 0);
+ bflb_irq_restore(flag);
+ if (stat != 0) {
+ return stat;
+ }
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ stat = bflb_sflash_erase(&g_flash2_cfg, flash1_size, startaddr + len - flash1_size - 1);
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ }
+#else
+ if (startaddr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
+ return -ENOMEM;
+ }
+
+ flag = bflb_irq_save();
+#if defined(BL602)
+ stat = bflb_xip_sflash_erase_need_lock_ext(&g_flash_cfg, startaddr, startaddr+len-1, 0, 0);
+#elif defined(BL702)
+ uint8_t aes_enabled = 0;
+ bflb_xip_sflash_opt_enter(&aes_enabled);
+ stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
+ bflb_xip_sflash_opt_exit(aes_enabled);
+#else
+ stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
+#endif
+ bflb_irq_restore(flag);
+#endif
+
+ return stat;
+}
+
+/**
+ * @brief write flash data via sbus
+ *
+ * @param flash absolute addr
+ * @param data
+ * @param len
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len)
+{
+ int stat = -1;
+ uintptr_t flag;
+
+#if defined(BL616)
+ if ((addr + len) > (flash1_size + flash2_size)) {
+ return -ENOMEM;
+ } else if ((addr + len) <= flash1_size) {
+ flag = bflb_irq_save();
+ stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+ bflb_irq_restore(flag);
+ } else if (addr >= flash1_size) {
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, addr, data, len);
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ } else {
+ flag = bflb_irq_save();
+ stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
+ bflb_irq_restore(flag);
+ if (stat != 0) {
+ return stat;
+ }
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ }
+#else
+ if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
+ return -ENOMEM;
+ }
+
+ flag = bflb_irq_save();
+#if defined(BL602)
+ stat = bflb_xip_sflash_write_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
+#elif defined(BL702)
+ uint8_t aes_enabled = 0;
+ bflb_xip_sflash_opt_enter(&aes_enabled);
+ stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+ bflb_xip_sflash_opt_exit(aes_enabled);
+#else
+ stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+#endif
+ bflb_irq_restore(flag);
+#endif
+
+ return stat;
+}
+
+/**
+ * @brief read flash data via sbus
+ *
+ * @param flash absolute addr
+ * @param data
+ * @param len
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
+{
+ int stat = -1;
+ uintptr_t flag;
+
+#if defined(BL616)
+ if ((addr + len) > (flash1_size + flash2_size)) {
+ return -ENOMEM;
+ } else if ((addr + len) <= flash1_size) {
+ flag = bflb_irq_save();
+ stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+ bflb_irq_restore(flag);
+ } else if (addr >= flash1_size) {
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, addr, data, len);
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ } else {
+ flag = bflb_irq_save();
+ stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
+ bflb_irq_restore(flag);
+ if (stat != 0) {
+ return stat;
+ }
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ }
+#else
+ if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
+ return -ENOMEM;
+ }
+
+ flag = bflb_irq_save();
+#if defined(BL602)
+ stat = bflb_xip_sflash_read_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
+#elif defined(BL702)
+ uint8_t aes_enabled = 0;
+ bflb_xip_sflash_opt_enter(&aes_enabled);
+ stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+ bflb_xip_sflash_opt_exit(aes_enabled);
+#else
+ stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+#endif
+ bflb_irq_restore(flag);
+#endif
+
+ return stat;
+}
+
+int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
+{
+ uint8_t is_aes_enable = 0;
+ uint32_t tmp[1];
+ int stat;
+
+ bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+
+ bflb_xip_sflash_opt_enter(&is_aes_enable);
+ /* To make it simple, exit cont read anyway */
+ bflb_sflash_reset_continue_read(&g_flash_cfg);
+
+ if (g_flash_cfg.c_read_support == 0) {
+ cont_read = 0;
+ }
+
+ if (cont_read == 1) {
+ stat = bflb_sflash_read(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+
+ if (0 != stat) {
+ bflb_xip_sflash_opt_exit(is_aes_enable);
+ return -1;
+ }
+ }
+
+#if defined(BL602) || defined(BL702)
+#if defined(BL602)
+ bflb_sflash_cache_enable_set(0xf);
+#else
+ L1C_Cache_Enable_Set(0xf);
+#endif
+
+ if (cache_enable) {
+ bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
+ bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
+ }
+#if defined(BL602)
+ bflb_sflash_cache_enable_set(cache_way_disable);
+#else
+ L1C_Cache_Enable_Set(cache_way_disable);
+#endif
+#else
+ bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
+ bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
+#endif
+
+ bflb_xip_sflash_opt_exit(is_aes_enable);
+
+ return 0;
+}
+
+void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
+{
+ uint8_t hw_key_enable = 0;
+
+ if (config->key == NULL) {
+ hw_key_enable = 1;
+ }
+
+ bflb_sf_ctrl_aes_set_key_be(config->region, (uint8_t *)config->key, config->keybits);
+ bflb_sf_ctrl_aes_set_iv_be(config->region, (uint8_t *)config->iv, config->start_addr);
+ bflb_sf_ctrl_aes_set_region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable);
+}
+
+void bflb_flash_aes_enable(void)
+{
+ bflb_sf_ctrl_aes_enable();
+}
+
+void bflb_flash_aes_disable(void)
+{
+ bflb_sf_ctrl_aes_disable();
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_gpio.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_gpio.c
new file mode 100644
index 00000000..cd8f5282
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_gpio.c
@@ -0,0 +1,447 @@
+#include "bflb_gpio.h"
+#include "hardware/gpio_reg.h"
+
+void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset)
+{
+ uint32_t cfg = 0;
+ uint32_t reg_base;
+ uint32_t cfg_address;
+ uint8_t drive;
+ uint8_t function;
+ uint16_t mode;
+
+ reg_base = dev->reg_base;
+
+ function = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT;
+ mode = (cfgset & GPIO_MODE_MASK);
+ drive = (cfgset & GPIO_DRV_MASK) >> GPIO_DRV_SHIFT;
+
+#if defined(BL616)
+ /* disable muxed to be xtal32k */
+ if (pin == GPIO_PIN_16) {
+ *(volatile uint32_t *)(0x2000f000 + 0x38) &= ~(1 << 20);
+ } else if (pin == GPIO_PIN_17) {
+ *(volatile uint32_t *)(0x2000f000 + 0x38) &= ~(1 << 21);
+ }
+#endif
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ uint32_t regval;
+ uint8_t is_odd = 0;
+
+ regval = getreg32(reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+ regval &= ~(1 << (pin & 0x1f));
+ putreg32(regval, reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+
+ is_odd = (pin % 2);
+
+ cfg_address = reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4);
+ cfg = getreg32(cfg_address);
+ cfg &= ~(0xffff << (16 * is_odd));
+
+ regval = getreg32(reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+ if (mode == GPIO_INPUT) {
+ cfg |= (1 << (is_odd * 16 + 0));
+ regval &= ~(1 << (pin & 0x1f));
+ function = 11;
+ } else if (mode == GPIO_OUTPUT) {
+ regval |= (1 << (pin & 0x1f));
+ function = 11;
+#if defined(BL702L)
+ if (function == 22) {
+ regval &= ~(1 << (pin & 0x1f));
+ }
+#endif
+ } else if (mode == GPIO_ANALOG) {
+ regval &= ~(1 << (pin & 0x1f));
+ function = 10;
+ } else if (mode == GPIO_ALTERNATE) {
+ cfg |= (1 << (is_odd * 16 + 0));
+#if defined(BL702L)
+ if (function == 22) {
+ cfg &= ~(1 << (is_odd * 16 + 0));
+ }
+#endif
+ regval &= ~(1 << (pin & 0x1f));
+ } else {
+ }
+ putreg32(regval, reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+
+ if (cfgset & GPIO_PULLUP) {
+ cfg |= (1 << (is_odd * 16 + 4));
+ } else if (cfgset & GPIO_PULLDOWN) {
+ cfg |= (1 << (is_odd * 16 + 5));
+ } else {
+ }
+
+ if (cfgset & GPIO_SMT_EN) {
+ cfg |= (1 << (is_odd * 16 + 1));
+ }
+
+ cfg |= (drive << (is_odd * 16 + 2));
+ cfg |= (function << (is_odd * 16 + 8));
+#if defined(BL702L)
+ /* configure output mode:set and clr mode */
+ if ((function != 22) || (function != 21)) {
+ cfg |= (1 << (is_odd * 16 + 15));
+ }
+#endif
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+ cfg = 0;
+ cfg |= GLB_REG_GPIO_0_INT_MASK;
+
+ if (mode == GPIO_INPUT) {
+ cfg |= GLB_REG_GPIO_0_IE;
+ function = 11;
+ } else if (mode == GPIO_OUTPUT) {
+ cfg |= GLB_REG_GPIO_0_OE;
+ function = 11;
+ } else if (mode == GPIO_ANALOG) {
+ function = 10;
+ } else if (mode == GPIO_ALTERNATE) {
+ cfg |= GLB_REG_GPIO_0_IE;
+ } else {
+ }
+
+ if (cfgset & GPIO_PULLUP) {
+ cfg |= GLB_REG_GPIO_0_PU;
+ } else if (cfgset & GPIO_PULLDOWN) {
+ cfg |= GLB_REG_GPIO_0_PD;
+ } else {
+ }
+
+ if (cfgset & GPIO_SMT_EN) {
+ cfg |= GLB_REG_GPIO_0_SMT;
+ }
+
+ cfg |= (drive << GLB_REG_GPIO_0_DRV_SHIFT);
+ cfg |= (function << GLB_REG_GPIO_0_FUNC_SEL_SHIFT);
+
+ /* configure output mode:set and clr mode */
+ cfg |= 0x1 << GLB_REG_GPIO_0_MODE_SHIFT;
+#endif
+ putreg32(cfg, cfg_address);
+}
+
+void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin)
+{
+ bflb_gpio_init(dev, pin, GPIO_INPUT | GPIO_FLOAT);
+}
+
+void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602)
+ uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+ putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+#elif defined(BL702L)
+ uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
+ putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG138_OFFSET + ((pin >> 5) << 2));
+#endif
+}
+
+void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602)
+ uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+ putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+#elif defined(BL702L)
+ uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
+ putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG140_OFFSET + ((pin >> 5) << 2));
+#endif
+}
+
+bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET) & (1 << pin));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_REG_GPIO_0_I);
+#endif
+}
+
+void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ putreg32(val, dev->reg_base + GLB_GPIO_CFG136_OFFSET);
+#endif
+}
+
+void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL33_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ putreg32(val, dev->reg_base + GLB_GPIO_CFG137_OFFSET);
+#endif
+}
+
+uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ return (getreg32(dev->reg_base + GLB_GPIO_CFG128_OFFSET));
+#endif
+}
+
+uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL31_OFFSET));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ return (getreg32(dev->reg_base + GLB_GPIO_CFG129_OFFSET));
+#endif
+}
+
+void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode)
+{
+ uint32_t reg_base;
+ uint32_t cfg_address;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ bflb_gpio_init(dev, pin, GPIO_INPUT | GPIO_FLOAT);
+
+ bflb_gpio_int_mask(dev, pin, true);
+ bflb_gpio_int_clear(dev, pin);
+
+#if defined(BL702) || defined(BL602)
+ cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 10) << 2);
+ regval = getreg32(cfg_address);
+ regval &= ~(0x07 << ((pin % 10) * 3));
+ regval |= (trig_mode << ((pin % 10) * 3));
+#elif defined(BL702L)
+ cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 8) << 2);
+ regval = getreg32(cfg_address);
+ regval &= ~(0x0f << ((pin % 8) * 4));
+ regval |= (trig_mode << ((pin % 8) * 4));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+ regval = getreg32(cfg_address);
+ regval &= ~GLB_REG_GPIO_0_INT_MODE_SET_MASK;
+ regval |= (trig_mode << GLB_REG_GPIO_0_INT_MODE_SET_SHIFT);
+#endif
+ putreg32(regval, cfg_address);
+}
+
+void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t cfg_address;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ cfg_address = reg_base + GLB_GPIO_INT_MASK1_OFFSET;
+
+ regval = getreg32(cfg_address);
+ if (mask) {
+ regval |= (1 << pin);
+ } else {
+ regval &= ~(1 << pin);
+ }
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+
+ regval = getreg32(cfg_address);
+ if (mask) {
+ regval |= GLB_REG_GPIO_0_INT_MASK;
+ } else {
+ regval &= ~GLB_REG_GPIO_0_INT_MASK;
+ }
+#endif
+ putreg32(regval, cfg_address);
+}
+
+bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ return (getreg32(dev->reg_base + GLB_GPIO_INT_STAT1_OFFSET) & (1 << pin));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_GPIO_0_INT_STAT);
+#endif
+}
+
+void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin)
+{
+ uint32_t reg_base;
+ uint32_t cfg_address;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ cfg_address = reg_base + GLB_GPIO_INT_CLR1_OFFSET;
+
+ regval = getreg32(cfg_address);
+ regval |= (1 << pin);
+ putreg32(regval, cfg_address);
+ regval &= ~(1 << pin);
+ putreg32(regval, cfg_address);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+
+ regval = getreg32(cfg_address);
+ regval |= GLB_REG_GPIO_0_INT_CLR;
+ putreg32(regval, cfg_address);
+ regval &= ~GLB_REG_GPIO_0_INT_CLR;
+ putreg32(regval, cfg_address);
+#endif
+}
+
+void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint8_t sig;
+ uint8_t sig_pos;
+
+ reg_base = dev->reg_base;
+#if defined(BL702) || defined(BL602)
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+ regval = getreg32(reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+
+ sig = pin % 8;
+ sig_pos = sig << 2;
+
+ regval &= (~(0x0f << sig_pos));
+ regval |= (uart_func << sig_pos);
+
+ for (uint8_t i = 0; i < 8; i++) {
+ /* reset other sigs which are the same with uart_func */
+ sig_pos = i << 2;
+ if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+ regval &= (~(0x0f << sig_pos));
+ regval |= (0x0f << sig_pos);
+ }
+ }
+
+ putreg32(regval, reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+#elif defined(BL702L)
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+ regval = getreg32(reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+
+ sig = pin % 4;
+ sig_pos = sig << 2;
+
+ regval &= (~(0x0f << sig_pos));
+ regval |= (uart_func << sig_pos);
+
+ for (uint8_t i = 0; i < 4; i++) {
+ /* reset other sigs which are the same with uart_func */
+ sig_pos = i << 2;
+ if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+ regval &= (~(0x0f << sig_pos));
+ regval |= (0x0f << sig_pos);
+ }
+ }
+
+ putreg32(regval, reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+#define GLB_UART_CFG1_OFFSET (0x154)
+#define GLB_UART_CFG2_OFFSET (0x158)
+ uint32_t regval2;
+ sig = pin % 12;
+
+ if (sig < 8) {
+ sig_pos = sig << 2;
+
+ regval = getreg32(reg_base + GLB_UART_CFG1_OFFSET);
+ regval &= (~(0x0f << sig_pos));
+ regval |= (uart_func << sig_pos);
+
+ for (uint8_t i = 0; i < 8; i++) {
+ /* reset other sigs which are the same with uart_func */
+ sig_pos = i << 2;
+ if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+ regval &= (~(0x0f << sig_pos));
+ regval |= (0x0f << sig_pos);
+ }
+ }
+ regval2 = getreg32(reg_base + GLB_UART_CFG2_OFFSET);
+
+ for (uint8_t i = 8; i < 12; i++) {
+ /* reset other sigs which are the same with uart_func */
+ sig_pos = (i - 8) << 2;
+ if (((regval2 & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+ regval2 &= (~(0x0f << sig_pos));
+ regval2 |= (0x0f << sig_pos);
+ }
+ }
+ putreg32(regval, reg_base + GLB_UART_CFG1_OFFSET);
+ putreg32(regval2, reg_base + GLB_UART_CFG2_OFFSET);
+ } else {
+ sig_pos = (sig - 8) << 2;
+
+ regval = getreg32(reg_base + GLB_UART_CFG2_OFFSET);
+ regval &= (~(0x0f << sig_pos));
+ regval |= (uart_func << sig_pos);
+
+ for (uint8_t i = 8; i < 12; i++) {
+ /* reset other sigs which are the same with uart_func */
+ sig_pos = (i - 8) << 2;
+ if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+ regval &= (~(0x0f << sig_pos));
+ regval |= (0x0f << sig_pos);
+ }
+ }
+ regval2 = getreg32(reg_base + GLB_UART_CFG1_OFFSET);
+
+ for (uint8_t i = 0; i < 8; i++) {
+ /* reset other sigs which are the same with uart_func */
+ sig_pos = i << 2;
+ if (((regval2 & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+ regval2 &= (~(0x0f << sig_pos));
+ regval2 |= (0x0f << sig_pos);
+ }
+ }
+ putreg32(regval, reg_base + GLB_UART_CFG2_OFFSET);
+ putreg32(regval2, reg_base + GLB_UART_CFG1_OFFSET);
+ }
+#endif
+ bflb_gpio_init(dev, pin, (7 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+}
+
+#if defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+void bflb_gpio_iso11898_init(struct bflb_device_s *dev, uint8_t pin, uint8_t iso11898_func)
+{
+ bflb_gpio_uart_init(dev, pin, iso11898_func);
+}
+#endif
+
+int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+ uint8_t pin = arg;
+
+ reg_base = dev->reg_base;
+ switch (cmd) {
+ case GPIO_CMD_GET_GPIO_FUN:
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ if ((pin % 2)) {
+ regval = getreg32(reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4)) & GLB_REG_GPIO_0_FUNC_SEL_MASK;
+ regval >>= GLB_REG_GPIO_0_FUNC_SEL_SHIFT;
+ } else {
+ regval = getreg32(reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4)) & GLB_REG_GPIO_1_FUNC_SEL_MASK;
+ regval >>= GLB_REG_GPIO_1_FUNC_SEL_SHIFT;
+ }
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+ regval = getreg32(reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_REG_GPIO_0_FUNC_SEL_MASK;
+ regval >>= GLB_REG_GPIO_0_FUNC_SEL_SHIFT;
+#endif
+ return regval;
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_i2c.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_i2c.c
new file mode 100644
index 00000000..a82ef5fd
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_i2c.c
@@ -0,0 +1,456 @@
+#include "bflb_i2c.h"
+#include "bflb_clock.h"
+#include "hardware/i2c_reg.h"
+
+#define PUT_UINT32_LE(field, value) \
+ do { \
+ (field)[0] = (uint8_t)((value) >> 0); \
+ (field)[1] = (uint8_t)((value) >> 8); \
+ (field)[2] = (uint8_t)((value) >> 16); \
+ (field)[3] = (uint8_t)((value) >> 24); \
+ } while (0)
+
+static void bflb_i2c_addr_config(struct bflb_device_s *dev, uint16_t slaveaddr, uint16_t subaddr, uint8_t subaddr_size, bool is_addr_10bit)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+
+ if (subaddr_size > 0) {
+ regval |= I2C_CR_I2C_SUB_ADDR_EN;
+ regval &= ~I2C_CR_I2C_SUB_ADDR_BC_MASK;
+ regval |= ((subaddr_size - 1) << I2C_CR_I2C_SUB_ADDR_BC_SHIFT);
+ } else {
+ regval &= ~I2C_CR_I2C_SUB_ADDR_EN;
+ }
+
+ regval &= ~I2C_CR_I2C_SLV_ADDR_MASK;
+ regval |= (slaveaddr << I2C_CR_I2C_SLV_ADDR_SHIFT);
+#if !defined(BL602) && !defined(BL702)
+ if (is_addr_10bit) {
+ regval |= I2C_CR_I2C_10B_ADDR_EN;
+ } else {
+ regval &= ~I2C_CR_I2C_10B_ADDR_EN;
+ }
+#endif
+ regval &= ~I2C_CR_I2C_SCL_SYNC_EN;
+ putreg32(subaddr, reg_base + I2C_SUB_ADDR_OFFSET);
+ putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static inline void bflb_i2c_set_dir(struct bflb_device_s *dev, bool is_in)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+
+ if (is_in) {
+ regval |= I2C_CR_I2C_PKT_DIR;
+ } else {
+ regval &= ~I2C_CR_I2C_PKT_DIR;
+ }
+ putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static inline void bflb_i2c_set_datalen(struct bflb_device_s *dev, uint16_t data_len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+ regval &= ~I2C_CR_I2C_PKT_LEN_MASK;
+ regval |= ((data_len - 1) << I2C_CR_I2C_PKT_LEN_SHIFT) & I2C_CR_I2C_PKT_LEN_MASK;
+ putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static void bflb_i2c_set_frequence(struct bflb_device_s *dev, uint32_t freq)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint32_t phase;
+
+ reg_base = dev->reg_base;
+
+ phase = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2C, dev->idx) / (freq * 4) - 1;
+
+ regval = phase << I2C_CR_I2C_PRD_S_PH_0_SHIFT;
+ regval |= phase << I2C_CR_I2C_PRD_S_PH_1_SHIFT;
+ regval |= phase << I2C_CR_I2C_PRD_S_PH_2_SHIFT;
+ regval |= phase << I2C_CR_I2C_PRD_S_PH_3_SHIFT;
+
+ putreg32(regval, reg_base + I2C_PRD_START_OFFSET);
+ putreg32(regval, reg_base + I2C_PRD_STOP_OFFSET);
+ putreg32(regval, reg_base + I2C_PRD_DATA_OFFSET);
+}
+
+static inline bool bflb_i2c_isbusy(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_BUS_BUSY_OFFSET);
+
+ if (regval & I2C_STS_I2C_BUS_BUSY) {
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool bflb_i2c_isend(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+
+ if (regval & I2C_END_INT) {
+ return true;
+ }
+
+ return false;
+}
+
+static inline void bflb_i2c_enable(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+ regval |= I2C_CR_I2C_M_EN;
+ putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static inline void bflb_i2c_disable(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+ regval &= ~I2C_CR_I2C_M_EN;
+ putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+ /* Clear I2C fifo */
+ regval = getreg32(reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+ regval |= I2C_TX_FIFO_CLR;
+ regval |= I2C_RX_FIFO_CLR;
+ putreg32(regval, reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+ /* Clear I2C interrupt status */
+ regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+ regval |= I2C_CR_I2C_END_CLR;
+ regval |= I2C_CR_I2C_NAK_CLR;
+ regval |= I2C_CR_I2C_ARB_CLR;
+ putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+static inline bool bflb_i2c_isenable(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+ if (regval & I2C_CR_I2C_M_EN) {
+ return true;
+ }
+
+ return false;
+}
+
+static int bflb_i2c_write_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+ uint32_t reg_base;
+ uint32_t temp = 0;
+ uint8_t *tmp_buf;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ tmp_buf = data;
+ while (len >= 4) {
+ for (uint8_t i = 0; i < 4; i++) {
+ temp += (tmp_buf[i] << ((i % 4) * 8));
+ }
+ tmp_buf += 4;
+ len -= 4;
+ start_time = bflb_mtimer_get_time_ms();
+ while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_TX_FIFO_CNT_MASK) == 0) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ putreg32(temp, reg_base + I2C_FIFO_WDATA_OFFSET);
+ if (!bflb_i2c_isenable(dev)) {
+ bflb_i2c_enable(dev);
+ }
+ temp = 0;
+ }
+
+ if (len > 0) {
+ for (uint8_t i = 0; i < len; i++) {
+ temp += (tmp_buf[i] << ((i % 4) * 8));
+ }
+ start_time = bflb_mtimer_get_time_ms();
+ while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_TX_FIFO_CNT_MASK) == 0) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ putreg32(temp, reg_base + I2C_FIFO_WDATA_OFFSET);
+ if (!bflb_i2c_isenable(dev)) {
+ bflb_i2c_enable(dev);
+ }
+ }
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev)) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ bflb_i2c_disable(dev);
+
+ return 0;
+}
+
+static int bflb_i2c_read_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+ uint32_t reg_base;
+ uint32_t temp = 0;
+ uint8_t *tmp_buf;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ tmp_buf = data;
+
+ bflb_i2c_enable(dev);
+
+ while (len >= 4) {
+ start_time = bflb_mtimer_get_time_ms();
+ while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_RX_FIFO_CNT_MASK) == 0) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ temp = getreg32(reg_base + I2C_FIFO_RDATA_OFFSET);
+ PUT_UINT32_LE(tmp_buf, temp);
+ tmp_buf += 4;
+ len -= 4;
+ }
+
+ if (len > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_RX_FIFO_CNT_MASK) == 0) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ temp = getreg32(reg_base + I2C_FIFO_RDATA_OFFSET);
+
+ for (uint8_t i = 0; i < len; i++) {
+ tmp_buf[i] = (temp >> (i * 8)) & 0xff;
+ }
+ }
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev)) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ bflb_i2c_disable(dev);
+
+ return 0;
+}
+
+void bflb_i2c_init(struct bflb_device_s *dev, uint32_t frequency)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ bflb_i2c_disable(dev);
+
+ regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+
+ regval |= (I2C_CR_I2C_END_MASK |
+ I2C_CR_I2C_TXF_MASK |
+ I2C_CR_I2C_RXF_MASK |
+ I2C_CR_I2C_NAK_MASK |
+ I2C_CR_I2C_ARB_MASK |
+ I2C_CR_I2C_FER_MASK);
+
+ putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+
+ bflb_i2c_set_frequence(dev, frequency);
+}
+
+void bflb_i2c_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ bflb_i2c_disable(dev);
+
+ regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+
+ regval |= (I2C_CR_I2C_END_MASK |
+ I2C_CR_I2C_TXF_MASK |
+ I2C_CR_I2C_RXF_MASK |
+ I2C_CR_I2C_NAK_MASK |
+ I2C_CR_I2C_ARB_MASK |
+ I2C_CR_I2C_FER_MASK);
+
+ putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+void bflb_i2c_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= I2C_DMA_TX_EN;
+ } else {
+ regval &= ~I2C_DMA_TX_EN;
+ }
+ putreg32(regval, reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_i2c_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= I2C_DMA_RX_EN;
+ } else {
+ regval &= ~I2C_DMA_RX_EN;
+ }
+ putreg32(regval, reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+}
+
+int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, int count)
+{
+ uint16_t subaddr = 0;
+ uint16_t subaddr_size = 0;
+ bool is_addr_10bit = false;
+ int ret = 0;
+
+ bflb_i2c_disable(dev);
+
+ for (uint16_t i = 0; i < count; i++) {
+ if (msgs[i].flags & I2C_M_TEN) {
+ is_addr_10bit = true;
+ } else {
+ is_addr_10bit = false;
+ }
+ if (msgs[i].flags & I2C_M_NOSTOP) {
+ subaddr = 0;
+ for (uint8_t j = 0; j < msgs[i].length; j++) {
+ subaddr += msgs[i].buffer[j] << (j * 8);
+ }
+ subaddr_size = msgs[i].length;
+ bflb_i2c_addr_config(dev, msgs[i].addr, subaddr, subaddr_size, is_addr_10bit);
+ i++;
+ } else {
+ subaddr = 0;
+ subaddr_size = 0;
+ bflb_i2c_addr_config(dev, msgs[i].addr, subaddr, subaddr_size, is_addr_10bit);
+ }
+
+ if (msgs[i].length > 256) {
+ return -EINVAL;
+ }
+ bflb_i2c_set_datalen(dev, msgs[i].length);
+ if (msgs[i].flags & I2C_M_READ) {
+ bflb_i2c_set_dir(dev, 1);
+ if ((msgs[i].flags & I2C_M_DMA) == 0) {
+ ret = bflb_i2c_read_bytes(dev, msgs[i].buffer, msgs[i].length);
+ if (ret < 0) {
+ return ret;
+ }
+ } else {
+ bflb_i2c_enable(dev);
+ }
+ } else {
+ bflb_i2c_set_dir(dev, 0);
+ if ((msgs[i].flags & I2C_M_DMA) == 0) {
+ ret = bflb_i2c_write_bytes(dev, msgs[i].buffer, msgs[i].length);
+ if (ret < 0) {
+ return ret;
+ }
+ } else {
+ bflb_i2c_enable(dev);
+ }
+ }
+ }
+
+ return 0;
+}
+
+void bflb_i2c_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+ regval &= ~((int_type & 0xff) << 8);
+ if (mask) {
+ regval |= (int_type & 0xff) << 8;
+ }
+ putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+void bflb_i2c_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+ regval |= (int_clear & 0xff) << 16;
+ putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ return (getreg32(reg_base + I2C_INT_STS_OFFSET) & 0xff);
+}
+
+int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ switch (cmd) {
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_i2s.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_i2s.c
new file mode 100644
index 00000000..95b1074a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_i2s.c
@@ -0,0 +1,341 @@
+#include "bflb_i2s.h"
+#include "bflb_clock.h"
+#include "hardware/i2s_reg.h"
+
+void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t div;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+ /* disable I2S */
+ regval &= ~I2S_CR_I2S_M_EN;
+ regval &= ~I2S_CR_I2S_S_EN;
+ regval &= ~I2S_CR_I2S_TXD_EN;
+ regval &= ~I2S_CR_I2S_TXD_EN;
+ putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+
+ if (config->channel_mode == I2S_CHANNEL_MODE_NUM_1) {
+ /* Mono mode */
+ regval |= I2S_CR_MONO_MODE;
+ regval &= ~I2S_CR_FS_CH_CNT_MASK;
+ } else {
+ regval &= ~I2S_CR_MONO_MODE;
+ regval &= ~I2S_CR_FS_CH_CNT_MASK;
+ regval |= (config->channel_mode - 1) << I2S_CR_FS_CH_CNT_SHIFT;
+ }
+
+ /* disable mute */
+ regval &= ~I2S_CR_MUTE_MODE;
+
+ if (config->format_mode == I2S_MODE_DSP_SHORT_FRAME_SYNC) {
+ /* dsp modeA/B short frame sync, there is only one bclk cycle */
+ regval |= I2S_CR_FS_1T_MODE;
+ } else {
+ regval &= ~I2S_CR_FS_1T_MODE;
+ }
+
+ /* frame/data width */
+ regval &= ~I2S_CR_FRAME_SIZE_MASK;
+ regval &= ~I2S_CR_DATA_SIZE_MASK;
+ regval |= config->frame_width << I2S_CR_FRAME_SIZE_SHIFT;
+ regval |= config->data_width << I2S_CR_DATA_SIZE_SHIFT;
+
+ if (config->format_mode == I2S_MODE_LEFT_JUSTIFIED) {
+ /* left justified*/
+ regval &= ~I2S_CR_I2S_MODE_MASK;
+ } else if (config->format_mode == I2S_MODE_RIGHT_JUSTIFIED) {
+ /* right justified*/
+ regval &= ~I2S_CR_I2S_MODE_MASK;
+ regval |= 1 << I2S_CR_I2S_MODE_SHIFT;
+ } else {
+ /* dsp mode */
+ regval &= ~I2S_CR_I2S_MODE_MASK;
+ regval |= 2 << I2S_CR_I2S_MODE_SHIFT;
+ }
+
+ /* fs_offset_cycle */
+ if (config->fs_offset_cycle) {
+ regval |= I2S_CR_OFS_EN;
+ regval &= ~I2S_CR_OFS_CNT_MASK;
+ regval |= ((config->fs_offset_cycle - 1) << I2S_CR_OFS_CNT_SHIFT) & I2S_CR_OFS_CNT_MASK;
+ } else {
+ regval &= ~I2S_CR_OFS_EN;
+ }
+
+ /* rx mono mode L-channel */
+ regval &= ~I2S_CR_MONO_RX_CH;
+ /* MSB */
+ regval &= ~I2S_CR_ENDIAN;
+
+ putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+
+ /* integer frequency segmentation by rounding */
+ div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2S, dev->idx) / 2 * 10 / config->bclk_freq_hz + 5) / 10;
+ div = (div) ? (div - 1) : 0;
+ div = (div > 0xfff) ? 0xfff : div;
+
+ /* bclk timing config */
+ regval = getreg32(reg_base + I2S_BCLK_CONFIG_OFFSET);
+ regval &= ~I2S_CR_BCLK_DIV_L_MASK;
+ regval &= ~I2S_CR_BCLK_DIV_H_MASK;
+ regval |= div << I2S_CR_BCLK_DIV_L_SHIFT;
+ regval |= div << I2S_CR_BCLK_DIV_H_SHIFT;
+ putreg32(regval, reg_base + I2S_BCLK_CONFIG_OFFSET);
+
+ /* fifo threshold config */
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_1_OFFSET);
+ regval &= ~I2S_TX_FIFO_TH_MASK;
+ regval &= ~I2S_RX_FIFO_TH_MASK;
+ regval |= (config->tx_fifo_threshold << I2S_TX_FIFO_TH_SHIFT) & I2S_TX_FIFO_TH_MASK;
+ regval |= (config->tx_fifo_threshold << I2S_RX_FIFO_TH_SHIFT) & I2S_RX_FIFO_TH_MASK;
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_1_OFFSET);
+
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ /* 32bit to 24bit */
+ regval &= ~I2S_CR_FIFO_24B_LJ;
+ /* Exchange L/R channel data */
+ regval &= ~I2S_CR_FIFO_LR_EXCHG;
+ /* Each FIFO entry contains both L/R channel data */
+ regval &= ~I2S_CR_FIFO_LR_MERGE;
+ /* disable dma */
+ regval &= ~I2S_DMA_TX_EN;
+ regval &= ~I2S_DMA_RX_EN;
+ /* clean fifo */
+ regval |= I2S_TX_FIFO_CLR;
+ regval |= I2S_RX_FIFO_CLR;
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+
+ regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
+ /* disable deglitch */
+ regval &= ~I2S_CR_DEG_EN;
+ /* disable inverse signal */
+ regval &= ~I2S_CR_I2S_BCLK_INV;
+ regval &= ~I2S_CR_I2S_FS_INV;
+ regval &= ~I2S_CR_I2S_RXD_INV;
+ regval &= ~I2S_CR_I2S_TXD_INV;
+ putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
+
+ /* enable I2S, but disable tx and rx */
+ regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+ if (config->role == I2S_ROLE_MASTER) {
+ regval |= I2S_CR_I2S_M_EN;
+ } else {
+ regval |= I2S_CR_I2S_S_EN;
+ }
+ putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+}
+
+void bflb_i2s_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ /* disable I2S */
+ regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+ regval &= ~I2S_CR_I2S_S_EN;
+ regval &= ~I2S_CR_I2S_M_EN;
+ putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+}
+
+void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= I2S_DMA_TX_EN;
+ } else {
+ regval &= ~I2S_DMA_TX_EN;
+ }
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= I2S_DMA_RX_EN;
+ } else {
+ regval &= ~I2S_DMA_RX_EN;
+ }
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
+ if (mask) {
+ regval |= I2S_CR_I2S_TXF_MASK;
+ } else {
+ regval &= ~I2S_CR_I2S_TXF_MASK;
+ }
+ putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
+}
+
+void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
+ if (mask) {
+ regval |= I2S_CR_I2S_RXF_MASK;
+ } else {
+ regval &= ~I2S_CR_I2S_RXF_MASK;
+ }
+ putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
+}
+
+void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
+ if (mask) {
+ regval |= I2S_CR_I2S_FER_MASK;
+ } else {
+ regval &= ~I2S_CR_I2S_FER_MASK;
+ }
+ putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
+}
+
+uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t int_status;
+ uint32_t int_mask;
+
+ reg_base = dev->reg_base;
+
+ int_status = getreg32(reg_base + I2S_INT_STS_OFFSET) & 0x1f;
+
+ int_mask = (getreg32(reg_base + I2S_INT_STS_OFFSET) >> 8) & 0x1f;
+
+ return (int_status & ~int_mask);
+}
+
+int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case I2S_CMD_CLEAR_TX_FIFO:
+ /* clear tx fifo */
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ regval |= I2S_TX_FIFO_CLR;
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case I2S_CMD_CLEAR_RX_FIFO:
+ /* clear rx fifo */
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ regval |= I2S_RX_FIFO_CLR;
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case I2S_CMD_RX_DEGLITCH:
+ /* set rx deglitch, arg: deglitch cycle count (unit: cycle of I2S kernel clock) */
+ regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
+ if (arg) {
+ regval |= I2S_CR_DEG_EN;
+ regval &= ~I2S_CR_DEG_CNT_MASK;
+ regval |= (arg << I2S_CR_DEG_CNT_SHIFT) & I2S_CR_DEG_CNT_MASK;
+ } else {
+ regval &= ~I2S_CR_DEG_EN;
+ }
+ putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
+ break;
+
+ case I2S_CMD_DATA_ENABLE:
+ /* data enable, arg: use @ref I2S_CMD_DATA_ENABLE_TYPE */
+ regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+ /* enable tx data signal */
+ if (arg & I2S_CMD_DATA_ENABLE_TX) {
+ regval |= I2S_CR_I2S_TXD_EN;
+ } else {
+ regval &= ~I2S_CR_I2S_TXD_EN;
+ }
+ /* enable rx data signal */
+ if (arg & I2S_CMD_DATA_ENABLE_RX) {
+ regval |= I2S_CR_I2S_RXD_EN;
+ } else {
+ regval &= ~I2S_CR_I2S_RXD_EN;
+ }
+ putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+ break;
+
+ case I2S_CMD_CHANNEL_LR_MERGE:
+ /* Each FIFO entry contains both L/R channel data ,
+ can only be enabled if data size is 8 or 16 bits,
+ arg use true or false */
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ if (arg) {
+ regval |= I2S_CR_FIFO_LR_MERGE;
+ } else {
+ regval &= ~I2S_CR_FIFO_LR_MERGE;
+ }
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case I2S_CMD_CHANNEL_LR_EXCHG:
+ /* The position of L/R channel data within each entry is exchanged,
+ can only be enabled if data size is 8 or 16 bits and I2S_CMD_CHANNEL_LR_MERGE is enabled,
+ arg use true or false */
+ regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ if (arg) {
+ regval |= I2S_CR_FIFO_LR_EXCHG;
+ } else {
+ regval &= ~I2S_CR_FIFO_LR_EXCHG;
+ }
+ putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case I2S_CMD_MUTE:
+ /* Enable mute, arg use true or false */
+ regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+ if (arg) {
+ regval |= I2S_CR_MUTE_MODE;
+ } else {
+ regval &= ~I2S_CR_MUTE_MODE;
+ }
+ putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+ break;
+
+ case I2S_CMD_BIT_REVERSE:
+ /* Data endian (bit reverse), arg use true or false, true: MSB goes out first, false: LSB goes out first*/
+ regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+ if (arg) {
+ regval |= I2S_CR_MUTE_MODE;
+ } else {
+ regval &= ~I2S_CR_MUTE_MODE;
+ }
+ putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+ break;
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_ir.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_ir.c
new file mode 100644
index 00000000..345adb85
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_ir.c
@@ -0,0 +1,637 @@
+#include "bflb_ir.h"
+#include "bflb_clock.h"
+#include "hardware/ir_reg.h"
+
+#define DIVIDE_ROUND(a, b) ((2 * a + b) / (2 * b))
+
+#if !defined(BL616)
+void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t ir_clock;
+ struct bflb_ir_tx_config_s *tx_config = (struct bflb_ir_tx_config_s *)config;
+
+#if defined(BL602) || defined(BL702)
+ *(uint32_t *)0x40000224 |= 1 << 31;
+#else
+ *(uint32_t *)0x20000144 |= 1 << 31;
+#endif
+
+ if (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0)) {
+ ir_clock = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0);
+ } else {
+ ir_clock = 2000000;
+ }
+
+ if (tx_config->tx_mode == IR_TX_NEC) {
+ tx_config->data_bits = 32;
+ tx_config->tail_inverse = 0;
+ tx_config->tail_enable = 1;
+ tx_config->head_inverse = 0;
+ tx_config->head_enable = 1;
+ tx_config->logic1_inverse = 0;
+ tx_config->logic0_inverse = 0;
+ tx_config->data_enable = 1;
+ tx_config->swm_enable = 0;
+ tx_config->output_modulation = 1;
+ tx_config->output_inverse = 0;
+ tx_config->freerun_enable = 0;
+ tx_config->continue_enable = 0;
+ tx_config->fifo_width = IR_TX_FIFO_WIDTH_32BIT;
+ tx_config->fifo_threshold = 0;
+ tx_config->logic0_pulse_width_1 = 0;
+ tx_config->logic0_pulse_width_0 = 0;
+ tx_config->logic1_pulse_width_1 = 2;
+ tx_config->logic1_pulse_width_0 = 0;
+ tx_config->head_pulse_width_1 = 7;
+ tx_config->head_pulse_width_0 = 15;
+ tx_config->tail_pulse_width_1 = 0;
+ tx_config->tail_pulse_width_0 = 0;
+ tx_config->pulse_width_unit = (ir_clock * 10 / 17777 - 1) & 0xfff;
+ } else if (tx_config->tx_mode == IR_TX_RC5) {
+ tx_config->data_bits = 13;
+ tx_config->tail_inverse = 0;
+ tx_config->tail_enable = 0;
+ tx_config->head_inverse = 1;
+ tx_config->head_enable = 1;
+ tx_config->logic1_inverse = 1;
+ tx_config->logic0_inverse = 0;
+ tx_config->data_enable = 1;
+ tx_config->swm_enable = 0;
+ tx_config->output_modulation = 1;
+ tx_config->output_inverse = 0;
+ tx_config->freerun_enable = 0;
+ tx_config->continue_enable = 0;
+ tx_config->fifo_width = IR_TX_FIFO_WIDTH_32BIT;
+ tx_config->fifo_threshold = 0;
+ tx_config->logic0_pulse_width_1 = 0;
+ tx_config->logic0_pulse_width_0 = 0;
+ tx_config->logic1_pulse_width_1 = 0;
+ tx_config->logic1_pulse_width_0 = 0;
+ tx_config->head_pulse_width_1 = 0;
+ tx_config->head_pulse_width_0 = 0;
+ tx_config->tail_pulse_width_1 = 0;
+ tx_config->tail_pulse_width_0 = 0;
+ tx_config->pulse_width_unit = (ir_clock * 10 / 11248 - 1) & 0xfff;
+ } else if (tx_config->tx_mode == IR_TX_SWM) {
+ tx_config->swm_enable = 1;
+ tx_config->output_modulation = 1;
+ tx_config->output_inverse = 0;
+ tx_config->fifo_width = IR_TX_FIFO_WIDTH_32BIT;
+ tx_config->fifo_threshold = 0;
+ }
+
+ if (tx_config->tx_mode != IR_TX_CUSTOMIZE) {
+ tx_config->modu_width_1 = ((ir_clock / 11310 + 5) / 10 - 1) & 0xff;
+ tx_config->modu_width_0 = ((ir_clock / 5655 + 5) / 10 - 1) & 0xff;
+ } else {
+ if (tx_config->output_modulation != 0 && tx_config->freerun_enable != 0) {
+ tx_config->continue_enable = 0;
+ if (tx_config->tail_pulse_width_1 < 5) {
+ tx_config->tail_pulse_width_1 = 5;
+ }
+ if (tx_config->tail_pulse_width_0 < 5) {
+ tx_config->tail_pulse_width_0 = 5;
+ }
+ }
+ }
+
+ reg_base = dev->reg_base;
+ regval = (tx_config->pulse_width_unit & 0xfff) | tx_config->modu_width_1 << 16 | tx_config->modu_width_0 << 24;
+ putreg32(regval, reg_base + IRTX_PULSE_WIDTH_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+ regval = getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET);
+ regval &= ~IR_TX_FIFO_TH_MASK;
+ regval |= tx_config->fifo_threshold << IR_TX_FIFO_TH_SHIFT;
+ putreg32(regval, reg_base + IR_FIFO_CONFIG_1_OFFSET);
+#endif
+
+ regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+#if defined(BL602) || defined(BL702)
+ regval &= ~(IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV);
+#else
+ regval &= ~(IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV | IR_CR_IRTX_FRM_FRAME_SIZE_MASK);
+#endif
+ if (tx_config->swm_enable) {
+ regval |= IR_CR_IRTX_SWM_EN;
+ }
+ if (tx_config->output_modulation) {
+ regval |= IR_CR_IRTX_MOD_EN;
+ }
+ if (tx_config->output_inverse) {
+ regval |= IR_CR_IRTX_OUT_INV;
+ }
+#if !defined(BL602) && !defined(BL702)
+ regval |= (tx_config->fifo_width & 0x3) << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT;
+#endif
+ if (tx_config->tx_mode == IR_TX_SWM) {
+ putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+ return;
+ }
+#if defined(BL602) || defined(BL702)
+ regval &= IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV;
+#else
+ regval &= IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV | IR_CR_IRTX_FRM_FRAME_SIZE_MASK;
+#endif
+ regval |= (tx_config->data_bits - 1) << IR_CR_IRTX_DATA_NUM_SHIFT;
+ if (tx_config->tail_inverse) {
+ regval |= IR_CR_IRTX_TAIL_HL_INV;
+ }
+ if (tx_config->tail_enable) {
+ regval |= IR_CR_IRTX_TAIL_EN;
+ }
+ if (tx_config->head_inverse) {
+ regval |= IR_CR_IRTX_HEAD_HL_INV;
+ }
+ if (tx_config->head_enable) {
+ regval |= IR_CR_IRTX_HEAD_EN;
+ }
+ if (tx_config->logic1_inverse) {
+ regval |= IR_CR_IRTX_LOGIC1_HL_INV;
+ }
+ if (tx_config->logic0_inverse) {
+ regval |= IR_CR_IRTX_LOGIC0_HL_INV;
+ }
+ if (tx_config->data_enable) {
+ regval |= IR_CR_IRTX_DATA_EN;
+ }
+#if !defined(BL602) && !defined(BL702)
+ if (tx_config->freerun_enable) {
+ regval |= IR_CR_IRTX_FRM_EN;
+ }
+ if (tx_config->continue_enable) {
+ regval |= IR_CR_IRTX_FRM_CONT_EN;
+ }
+#endif
+ putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+#if defined(BL602) || defined(BL702)
+ regval = (tx_config->tail_pulse_width_1 & 0xf) << 28 | \
+ (tx_config->tail_pulse_width_0 & 0xf) << 24 | \
+ (tx_config->head_pulse_width_1 & 0xf) << 20 | \
+ (tx_config->head_pulse_width_0 & 0xf) << 16 | \
+ (tx_config->logic1_pulse_width_1 & 0xf) << 12 | \
+ (tx_config->logic1_pulse_width_0 & 0xf) << 8 | \
+ (tx_config->logic0_pulse_width_1 & 0xf) << 4 | \
+ (tx_config->logic0_pulse_width_0 & 0xf);
+ putreg32(regval, reg_base + IRTX_PW_OFFSET);
+#else
+ regval = tx_config->logic0_pulse_width_0 | tx_config->logic0_pulse_width_1 << 8 | \
+ tx_config->logic1_pulse_width_0 << 16 | tx_config->logic1_pulse_width_1 << 24;
+ putreg32(regval, reg_base + IRTX_PW_0_OFFSET);
+
+ regval = tx_config->head_pulse_width_0 | tx_config->head_pulse_width_1 << 8 | \
+ tx_config->tail_pulse_width_0 << 16 | tx_config->tail_pulse_width_1 << 24;
+ putreg32(regval, reg_base + IRTX_PW_1_OFFSET);
+#endif
+}
+
+void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+#if !defined(BL602) && !defined(BL702)
+ uint32_t i = 0;
+#endif
+
+ bflb_ir_txint_clear(dev);
+
+ reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+ putreg32(data[0], reg_base + IRTX_DATA_WORD0_OFFSET);
+ if (length > 1) {
+ putreg32(data[1], reg_base + IRTX_DATA_WORD1_OFFSET);
+ }
+#endif
+
+ regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+ regval |= IR_CR_IRTX_EN;
+ putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+ if ((regval & IR_CR_IRTX_FRM_EN) == 0) {
+ length = length < 4 ? length : 4;
+ }
+ while(i < length){
+ if (bflb_ir_get_txfifo_cnt(dev) > 0) {
+ putreg32(data[i], reg_base + IR_FIFO_WDATA_OFFSET);
+ i++;
+ }
+ }
+
+ if ((getreg32(reg_base + IRTX_CONFIG_OFFSET) & IR_CR_IRTX_FRM_EN) == 0) {
+ while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
+ /* Waiting for sending */
+ }
+ } else {
+ while(bflb_ir_get_txfifo_cnt(dev) < 4){
+ /* Waiting for sending */
+ }
+ }
+#else
+ while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
+ /* Waiting for sending */
+ }
+#endif
+
+ regval &= ~IR_CR_IRTX_EN;
+ putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+ bflb_ir_txint_clear(dev);
+}
+
+void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint16_t min_data = data[0];
+#if defined(BL602) || defined(BL702)
+ uint32_t count = (length + 7) / 8;
+#else
+ uint32_t count = (length + 3) / 4;
+#endif
+ uint32_t pwval = 0;
+ uint32_t i, j;
+
+ if (length > 128) {
+ length = 128;
+ }
+
+ bflb_ir_txint_clear(dev);
+
+ /* Search for min value */
+ for (i = 1; i < length; i++) {
+ if (min_data > data[i] && data[i] != 0) {
+ min_data = data[i];
+ }
+ }
+
+ /* Set min value as pulse width unit */
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRTX_PULSE_WIDTH_OFFSET);
+ regval &= ~IR_CR_IRTX_PW_UNIT_MASK;
+ regval |= min_data << IR_CR_IRTX_PW_UNIT_SHIFT;
+ putreg32(regval, reg_base + IRTX_PULSE_WIDTH_OFFSET);
+
+#if defined(BL602) || defined(BL702)
+ /* Set tx SWM pulse width data as multiples of pulse width unit */
+ for (i = 0; i < count; i++) {
+ pwval = 0;
+
+ if (i < count - 1) {
+ for (j = 0; j < 8; j++) {
+ regval = ((2 * data[j + i * 8] + min_data) / (2 * min_data) - 1) & 0xf;
+ pwval |= regval << (4 * j);
+ }
+
+ putreg32(pwval, reg_base + IRTX_SWM_PW_0_OFFSET + i * 4);
+ } else {
+ for (j = 0; j < length % 8; j++) {
+ regval = ((2 * data[j + i * 8] + min_data) / (2 * min_data) - 1) & 0xf;
+ pwval |= regval << (4 * j);
+ }
+
+ putreg32(pwval, reg_base + IRTX_SWM_PW_0_OFFSET + i * 4);
+ }
+ }
+#endif
+
+ regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+ regval &= ~IR_CR_IRTX_DATA_NUM_MASK;
+ regval |= (length - 1) << IR_CR_IRTX_DATA_NUM_SHIFT;
+ regval |= IR_CR_IRTX_EN;
+ putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+ /* Calculate tx SWM pulse width data as multiples of pulse width unit */
+ for (i = 0; i < count; i++) {
+ pwval = 0;
+
+ if (i < count - 1) {
+ /* Put every four pulse width together as a 32-bit value to tx fifo */
+ for (j = 0; j < 4; j++) {
+ /* Every pulse width divided by pulse width unit */
+ regval = (DIVIDE_ROUND(data[j + i * 4], min_data) - 1) & 0xff;
+ /* Tx fifo 32-bit value: pwval[7:0]:first pulse width, pwval[15:8]:second pulse width... */
+ pwval |= regval << (8 * j);
+ }
+ } else {
+ /* Deal with pulse width data remained which is less than 4 */
+ for (j = 0; j < length % 4; j++) {
+ regval = (DIVIDE_ROUND(data[j + i * 4], min_data) - 1) & 0xff;
+ pwval |= regval << (8 * j);
+ }
+ }
+
+ /* Write to tx fifo */
+ while(bflb_ir_get_txfifo_cnt(dev) == 0){}
+ putreg32(pwval, reg_base + IR_FIFO_WDATA_OFFSET);
+ }
+#endif
+
+ while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
+ /* Waiting for sending */
+ }
+
+ regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+ regval &= ~IR_CR_IRTX_EN;
+ putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+ bflb_ir_txint_clear(dev);
+}
+
+void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+ if (enable) {
+ regval |= IR_CR_IRTX_EN;
+ } else {
+ regval &= ~IR_CR_IRTX_EN;
+ }
+ putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+}
+
+void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRTX_INT_STS_OFFSET);
+ if (mask) {
+ regval |= (int_type & 0x7) << 8;
+ } else {
+ regval &= ~((int_type & 0x7) << 8);
+ }
+ putreg32(regval, reg_base + IRTX_INT_STS_OFFSET);
+}
+
+void bflb_ir_txint_clear(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRTX_INT_STS_OFFSET);
+ regval |= IR_CR_IRTX_END_CLR;
+ putreg32(regval, reg_base + IRTX_INT_STS_OFFSET);
+}
+
+uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ return (getreg32(reg_base + IRTX_INT_STS_OFFSET) & 0x7);
+}
+
+#if !defined(BL602) && !defined(BL702)
+void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IR_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= IRTX_DMA_EN;
+ } else {
+ regval &= ~IRTX_DMA_EN;
+ }
+ putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
+}
+
+uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ return ((getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET) & IR_TX_FIFO_CNT_MASK) >> IR_TX_FIFO_CNT_SHIFT);
+}
+
+void bflb_ir_txfifo_clear(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IR_FIFO_CONFIG_0_OFFSET);
+ regval |= IR_TX_FIFO_CLR;
+ putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
+}
+#endif
+#endif
+
+#if !defined(BL702L)
+void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t ir_clock;
+ uint16_t data_threshold, end_threshold;
+
+ if (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0)) {
+ ir_clock = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0);
+ } else {
+ ir_clock = 2000000;
+ }
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+ regval &= ~IR_CR_IRRX_MODE_MASK;
+ regval |= (config->rx_mode & 0x3) << IR_CR_IRRX_MODE_SHIFT;
+ if (config->input_inverse) {
+ regval |= IR_CR_IRRX_IN_INV;
+ } else {
+ regval &= ~IR_CR_IRRX_IN_INV;
+ }
+ if (!config->deglitch_enable) {
+ regval &= ~IR_CR_IRRX_DEG_EN;
+ } else {
+ regval |= IR_CR_IRRX_DEG_EN;
+ regval &= ~IR_CR_IRRX_DEG_CNT_MASK;
+ regval |= config->deglitch_cnt << IR_CR_IRRX_DEG_CNT_SHIFT;
+ }
+ putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+ if (config->rx_mode == IR_RX_NEC) {
+ data_threshold = (ir_clock / 588 - 1) & 0xffff;
+ end_threshold = (ir_clock / 222 - 1) & 0xffff;
+ } else if (config->rx_mode == IR_RX_RC5) {
+ data_threshold = (ir_clock / 750 - 1) & 0xffff;
+ end_threshold = (ir_clock / 400 - 1) & 0xffff;
+ } else {
+ data_threshold = config->data_threshold;
+ end_threshold = config->end_threshold;
+ }
+ regval = getreg32(reg_base + IRRX_PW_CONFIG_OFFSET);
+ regval = end_threshold << IR_CR_IRRX_END_TH_SHIFT | data_threshold;
+ putreg32(regval, reg_base + IRRX_PW_CONFIG_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+ regval = getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET);
+ regval &= ~IR_RX_FIFO_TH_MASK;
+ regval |= config->fifo_threshold << IR_RX_FIFO_TH_SHIFT;
+ putreg32(regval, reg_base + IR_FIFO_CONFIG_1_OFFSET);
+#endif
+}
+
+uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ bflb_ir_rxint_clear(dev);
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+ regval |= IR_CR_IRRX_EN;
+ putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+ while((bflb_ir_get_rxint_status(dev) & IR_RX_INTSTS_END) == 0){
+ /* Waiting for receiving */
+ }
+
+ regval &= ~IR_CR_IRRX_EN;
+ putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+ bflb_ir_rxint_clear(dev);
+
+ regval = getreg32(reg_base + IRRX_DATA_COUNT_OFFSET) & IR_STS_IRRX_DATA_CNT_MASK;
+ if (regval <= 32) {
+ *data = getreg32(reg_base + IRRX_DATA_WORD0_OFFSET);
+ } else {
+ *data = getreg32(reg_base + IRRX_DATA_WORD0_OFFSET) | (uint64_t)getreg32(reg_base + IRRX_DATA_WORD1_OFFSET) << 32;
+ }
+
+ return regval;
+}
+
+uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t i = 0;
+
+ bflb_ir_rxint_clear(dev);
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+ regval |= IR_CR_IRRX_EN;
+ putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+ while((bflb_ir_get_rxint_status(dev) & IR_RX_INTSTS_END) == 0){
+ if (bflb_ir_get_rxfifo_cnt(dev) != 0 && i < length) {
+#if defined(BL602) || defined(BL702)
+ data[i] = getreg32(reg_base + IRRX_SWM_FIFO_RDATA_OFFSET);
+#else
+ data[i] = getreg32(reg_base + IR_FIFO_RDATA_OFFSET);
+#endif
+ i++;
+ }
+ }
+
+ regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+ regval &= ~IR_CR_IRRX_EN;
+ putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+ bflb_ir_rxint_clear(dev);
+
+ return(getreg32(reg_base + IRRX_DATA_COUNT_OFFSET) & IR_STS_IRRX_DATA_CNT_MASK);
+}
+
+void bflb_ir_rx_enable(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+ if (enable) {
+ regval |= IR_CR_IRRX_EN;
+ } else {
+ regval &= ~IR_CR_IRRX_EN;
+ }
+ putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+}
+
+void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRRX_INT_STS_OFFSET);
+ if (mask) {
+ regval |= (int_type & 0x7) << 8;
+ } else {
+ regval &= ~((int_type & 0x7) << 8);
+ }
+ putreg32(regval, reg_base + IRRX_INT_STS_OFFSET);
+}
+
+void bflb_ir_rxint_clear(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + IRRX_INT_STS_OFFSET);
+ regval |= IR_CR_IRRX_END_CLR;
+ putreg32(regval, reg_base + IRRX_INT_STS_OFFSET);
+}
+
+uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ return (getreg32(reg_base + IRRX_INT_STS_OFFSET) & 0x7);
+}
+
+uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+ return ((getreg32(reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET) & IR_RX_FIFO_CNT_MASK) >> IR_RX_FIFO_CNT_SHIFT);
+#else
+ return ((getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET) & IR_RX_FIFO_CNT_MASK) >> IR_RX_FIFO_CNT_SHIFT);
+#endif
+}
+
+void bflb_ir_rxfifo_clear(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+ regval = getreg32(reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET);
+ regval |= IR_RX_FIFO_CLR;
+ putreg32(regval, reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET);
+#else
+ regval = getreg32(reg_base + IR_FIFO_CONFIG_0_OFFSET);
+ regval |= IR_RX_FIFO_CLR;
+ putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
+#endif
+}
+#endif
+
+int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ switch (cmd) {
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_irq.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_irq.c
new file mode 100644
index 00000000..7e423b36
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_irq.c
@@ -0,0 +1,130 @@
+#include "bflb_irq.h"
+#include "bflb_core.h"
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#include
+#else
+#include
+#endif
+
+extern struct bflb_irq_info_s g_irqvector[];
+
+static void irq_unexpected_isr(int irq, void *arg)
+{
+ printf("irq :%d unregistered\r\n", irq);
+}
+
+void bflb_irq_initialize(void)
+{
+ int i;
+
+ /* Point all interrupt vectors to the unexpected interrupt */
+ for (i = 0; i < CONFIG_IRQ_NUM; i++) {
+ g_irqvector[i].handler = irq_unexpected_isr;
+ g_irqvector[i].arg = NULL;
+ }
+}
+
+ATTR_TCM_SECTION uintptr_t bflb_irq_save(void)
+{
+ uintptr_t oldstat;
+
+ /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */
+
+ asm volatile("csrrc %0, mstatus, %1"
+ : "=r"(oldstat)
+ : "r"(MSTATUS_MIE));
+ return oldstat;
+}
+
+ATTR_TCM_SECTION void bflb_irq_restore(uintptr_t flags)
+{
+ /* Write flags to mstatus */
+
+ asm volatile("csrw mstatus, %0"
+ : /* no output */
+ : "r"(flags));
+}
+
+int bflb_irq_attach(int irq, irq_callback isr, void *arg)
+{
+ if (irq > CONFIG_IRQ_NUM) {
+ return -EINVAL;
+ }
+ g_irqvector[irq].handler = isr;
+ g_irqvector[irq].arg = arg;
+ return 0;
+}
+
+int bflb_irq_detach(int irq)
+{
+ if (irq > CONFIG_IRQ_NUM) {
+ return -EINVAL;
+ }
+ g_irqvector[irq].handler = irq_unexpected_isr;
+ g_irqvector[irq].arg = NULL;
+ return 0;
+}
+
+void bflb_irq_enable(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ putreg8(1, CLIC_HART0_BASE + CLIC_INTIE_OFFSET + irq);
+#else
+#if (defined(BL808) || defined(BL606P)) && defined(CPU_D0)
+ if (csi_vic_get_prio(irq) == 0) {
+ csi_vic_set_prio(irq, 1);
+ }
+#endif
+ csi_vic_enable_irq(irq);
+#endif
+}
+
+void bflb_irq_disable(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ putreg8(0, CLIC_HART0_BASE + CLIC_INTIE_OFFSET + irq);
+#else
+ csi_vic_disable_irq(irq);
+#endif
+}
+
+void bflb_irq_set_pending(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ putreg8(1, CLIC_HART0_BASE + CLIC_INTIP_OFFSET + irq);
+#else
+ csi_vic_set_pending_irq(irq);
+#endif
+}
+
+void bflb_irq_clear_pending(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ putreg8(0, CLIC_HART0_BASE + CLIC_INTIP_OFFSET + irq);
+#else
+ csi_vic_clear_pending_irq(irq);
+#endif
+}
+
+void bflb_irq_set_nlbits(uint8_t nlbits)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ uint8_t clicCfg = getreg8(CLIC_HART0_BASE + CLIC_CFG_OFFSET);
+ putreg8((clicCfg & 0xe1) | ((nlbits & 0xf) << 1), CLIC_HART0_BASE + CLIC_CFG_OFFSET);
+#else
+#if !defined(CPU_D0)
+ CLIC->CLICCFG = ((nlbits & 0xf) << 1) | 1;
+#endif
+#endif
+}
+
+void bflb_irq_set_priority(int irq, uint8_t preemptprio, uint8_t subprio)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ uint8_t nlbits = getreg8(CLIC_HART0_BASE + CLIC_CFG_OFFSET) >> 1 & 0xf;
+ uint8_t clicIntCfg = getreg8(CLIC_HART0_BASE + CLIC_INTCFG_OFFSET + irq);
+ putreg8((clicIntCfg & 0xf) | (preemptprio << (8 - nlbits)) | ((subprio & (0xf >> nlbits)) << 4), CLIC_HART0_BASE + CLIC_INTCFG_OFFSET + irq);
+#else
+ csi_vic_set_prio(irq, preemptprio);
+#endif
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_iso11898.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_iso11898.c
new file mode 100644
index 00000000..f9265165
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_iso11898.c
@@ -0,0 +1,366 @@
+#include "bflb_iso11898.h"
+#include "hardware/iso11898_reg.h"
+
+void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ /* first enter reset mode */
+ regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+ regval |= ISO11898_RESET_REQUEST;
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+ /* force using PeliISO11898 not BasicISO11898 */
+ regval = getreg32(reg_base + ISO11898_CLOCK_DIVIDER_OFFSET);
+ regval |= ISO11898_CAN_MODE;
+ putreg32(regval, reg_base + ISO11898_CLOCK_DIVIDER_OFFSET);
+
+ /* config prescale and synchronisation_jump_width */
+ regval = getreg32(reg_base + ISO11898_BUS_TIMING_0_OFFSET);
+ regval &= ~ISO11898_BAUD_RATE_PRESCALER_MASK;
+ regval |= (config->prescaler << ISO11898_BAUD_RATE_PRESCALER_SHIFT);
+ regval &= ~ISO11898_SYNC_JUMP_WIDTH_MASK;
+ regval |= (config->sjw << ISO11898_SYNC_JUMP_WIDTH_SHIFT);
+ putreg32(regval, reg_base + ISO11898_BUS_TIMING_0_OFFSET);
+
+ /* config samping and bit_segment_1/2 */
+ regval = getreg32(reg_base + ISO11898_BUS_TIMING_1_OFFSET);
+ if (config->sample == ISO11898_SAMPLE_SINGLE) {
+ regval &= ~ISO11898_SAMPLING;
+ } else {
+ regval |= ISO11898_SAMPLING;
+ }
+ regval &= ~ISO11898_TIME_SEGMENT_1_MASK;
+ regval |= (config->bs1 << ISO11898_TIME_SEGMENT_1_SHIFT);
+ regval &= ~ISO11898_TIME_SEGMENT_2_MASK;
+ regval |= (config->bs2 << ISO11898_TIME_SEGMENT_2_SHIFT);
+ putreg32(regval, reg_base + ISO11898_BUS_TIMING_1_OFFSET);
+
+ /* config mode */
+ regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+ if (config->mode == ISO11898_MODE_NORMAL) {
+ regval &= ~ISO11898_LISTEN_ONLY;
+ regval &= ~ISO11898_SELF_TEST;
+ } else if (config->mode == ISO11898_MODE_LOOPBACK) {
+ regval &= ~ISO11898_LISTEN_ONLY;
+ regval |= ISO11898_SELF_TEST;
+ } else if (config->mode == ISO11898_MODE_SILENT) {
+ regval |= ISO11898_LISTEN_ONLY;
+ regval &= ~ISO11898_SELF_TEST;
+ } else if (config->mode == ISO11898_MODE_SILENT_LOOPBACK) {
+ regval |= ISO11898_LISTEN_ONLY;
+ regval |= ISO11898_SELF_TEST;
+ } else {
+ }
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+ /* last leave reset mode */
+ regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+ regval &= ~ISO11898_RESET_REQUEST;
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+}
+
+void bflb_iso11898_deinit(struct bflb_device_s *dev)
+{
+}
+
+void bflb_iso11898_abort_send(struct bflb_device_s *dev)
+{
+ putreg32(ISO11898_ABORT_TRANSMISSION, dev->reg_base + ISO11898_COMMAND_OFFSET);
+}
+
+int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t data_base_addr;
+ uint8_t mode;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_TX_AVAILABLE)) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > timeout) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* config frame information register */
+ regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
+ regval &= ~ISO11898_FRAME_INFORMATION_DLC_MASK;
+ regval |= (msg->dlc << ISO11898_FRAME_INFORMATION_DLC_SHIFT);
+ if (msg->id_type == ISO11898_ID_STANDARD) {
+ regval &= ~ISO11898_FRAME_INFORMATION_FF;
+ } else {
+ regval |= ISO11898_FRAME_INFORMATION_FF;
+ }
+ if (msg->rtr == ISO11898_RTR_DATA) {
+ regval &= ~ISO11898_FRAME_INFORMATION_RTR;
+ } else {
+ regval |= ISO11898_FRAME_INFORMATION_RTR;
+ }
+ putreg32(regval, reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
+
+ /* config id */
+ if (msg->id_type == ISO11898_ID_STANDARD) {
+ putreg32(msg->std_id >> (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT), reg_base + ISO11898_SFF_ID1_OFFSET);
+ putreg32(msg->std_id << ISO11898_SFF_ID2_BIT20_18_SHIFT, reg_base + ISO11898_SFF_ID2_OFFSET);
+ data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET;
+ } else {
+ putreg32(msg->ext_id >> 21, reg_base + ISO11898_EFF_ID1_OFFSET);
+ putreg32(msg->ext_id >> 13, reg_base + ISO11898_EFF_ID2_OFFSET);
+ putreg32(msg->ext_id >> 5, reg_base + ISO11898_EFF_ID3_OFFSET);
+ putreg32(msg->ext_id << ISO11898_EFF_ID4_BIT4_0_SHIFT, reg_base + ISO11898_EFF_ID4_OFFSET);
+ data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET;
+ }
+
+ /* move data from user buff to registers */
+ for (uint32_t i = 0; i < msg->dlc; i++) {
+ *((uint32_t *)data_base_addr + i) = msg->data[i];
+ }
+
+ /* trig a request for transmit */
+ mode = bflb_iso11898_get_mode(dev);
+ if (mode == ISO11898_MODE_SILENT_LOOPBACK || mode == ISO11898_MODE_LOOPBACK) {
+ putreg32(ISO11898_SELF_REQUEST, reg_base + ISO11898_COMMAND_OFFSET);
+ } else if (mode == ISO11898_MODE_NORMAL) {
+ putreg32(ISO11898_TRANSMIT_REQUEST, reg_base + ISO11898_COMMAND_OFFSET);
+ } else {
+ return -2;
+ }
+ return 0;
+}
+
+int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout)
+{
+ uint32_t reg_base;
+ uint32_t regval, regval2, regval3, regval4;
+ uint32_t data_base_addr;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_RX_NOT_EMPTY)) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > timeout) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* read information register */
+ regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
+ msg->dlc = (uint8_t)((regval & ISO11898_FRAME_INFORMATION_DLC_MASK) >> ISO11898_FRAME_INFORMATION_DLC_SHIFT);
+ if (regval & ISO11898_FRAME_INFORMATION_FF) {
+ msg->id_type = ISO11898_ID_EXTENDED;
+ } else {
+ msg->id_type = ISO11898_ID_STANDARD;
+ }
+ if (regval & ISO11898_FRAME_INFORMATION_RTR) {
+ msg->rtr = ISO11898_RTR_REMOTE;
+ } else {
+ msg->rtr = ISO11898_RTR_DATA;
+ }
+
+ /* receive with 11 or 29 bits ID */
+ if (msg->id_type == ISO11898_ID_STANDARD) {
+ regval = getreg32(reg_base + ISO11898_SFF_ID1_OFFSET);
+ regval &= ISO11898_SFF_ID1_BIT28_21_MASK;
+ regval <<= (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT);
+ regval2 = getreg32(reg_base + ISO11898_SFF_ID2_OFFSET);
+ regval2 &= ISO11898_SFF_ID2_BIT20_18_MASK;
+ regval2 >>= ISO11898_SFF_ID2_BIT20_18_SHIFT;
+ msg->std_id = regval | regval2;
+ data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET;
+ } else {
+ regval = getreg32(reg_base + ISO11898_EFF_ID1_OFFSET);
+ regval &= ISO11898_EFF_ID1_BIT28_21_MASK;
+ regval <<= 21;
+ regval2 = getreg32(reg_base + ISO11898_EFF_ID2_OFFSET);
+ regval2 &= ISO11898_EFF_ID2_BIT20_13_MASK;
+ regval2 <<= 13;
+ regval3 = getreg32(reg_base + ISO11898_EFF_ID3_OFFSET);
+ regval3 &= ISO11898_EFF_ID3_BIT12_5_MASK;
+ regval3 <<= 5;
+ regval4 = getreg32(reg_base + ISO11898_EFF_ID4_OFFSET);
+ regval4 &= ISO11898_EFF_ID4_BIT4_0_MASK;
+ regval4 >>= ISO11898_EFF_ID4_BIT4_0_SHIFT;
+ msg->ext_id = regval | regval2 | regval3 | regval4;
+ data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET;
+ }
+
+ /* move data from registers to user buff */
+ for (uint32_t i = 0; i < msg->dlc; i++) {
+ msg->data[i] = (uint8_t)(*((uint32_t *)data_base_addr + i));
+ }
+ putreg32(ISO11898_RELEASE_RECEIVE_BUFFER, reg_base + ISO11898_COMMAND_OFFSET);
+ return 0;
+}
+
+uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev)
+{
+ return getreg32(dev->reg_base + ISO11898_STATUS_OFFSET) & 0xff;
+}
+
+void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ /* first enter reset mode */
+ regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+ regval |= ISO11898_RESET_REQUEST;
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+ /* config mode */
+ regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+ if (mode == ISO11898_MODE_NORMAL) {
+ regval &= ~ISO11898_LISTEN_ONLY;
+ regval &= ~ISO11898_SELF_TEST;
+ } else if (mode == ISO11898_MODE_LOOPBACK) {
+ regval &= ~ISO11898_LISTEN_ONLY;
+ regval |= ISO11898_SELF_TEST;
+ } else if (mode == ISO11898_MODE_SILENT) {
+ regval |= ISO11898_LISTEN_ONLY;
+ regval &= ~ISO11898_SELF_TEST;
+ } else if (mode == ISO11898_MODE_SILENT_LOOPBACK) {
+ regval |= ISO11898_LISTEN_ONLY;
+ regval |= ISO11898_SELF_TEST;
+ } else {
+ }
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+ /* last leave reset mode */
+ regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+ regval &= ~ISO11898_RESET_REQUEST;
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+}
+
+uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint8_t silent, loopback;
+
+ regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET);
+ if (regval & ISO11898_SELF_TEST) {
+ loopback = 1;
+ } else {
+ loopback = 0;
+ }
+ if (regval & ISO11898_LISTEN_ONLY) {
+ silent = 1;
+ } else {
+ silent = 0;
+ }
+ if (loopback && silent) {
+ return ISO11898_MODE_SILENT_LOOPBACK;
+ } else if (!loopback && silent) {
+ return ISO11898_MODE_SILENT;
+ } else if (loopback && !silent) {
+ return ISO11898_MODE_LOOPBACK;
+ } else {
+ return ISO11898_MODE_NORMAL;
+ }
+}
+
+void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint8_t mode;
+
+ reg_base = dev->reg_base;
+ /* first save mode */
+ mode = bflb_iso11898_get_mode(dev);
+
+ /* enter reset mode */
+ regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+ regval |= ISO11898_RESET_REQUEST;
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+ /* config filter type */
+ regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET);
+ if (filter->filter_type == ISO11898_FILTER_TYPE_SINGLE) {
+ regval |= ISO11898_FILTER_TYPE;
+ } else {
+ regval &= ~ISO11898_FILTER_TYPE;
+ }
+ putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+ /* config filter code and mask */
+ putreg32(filter->code0, reg_base + ISO11898_ACCEPTANCE_CODE_0_OFFSET);
+ putreg32(filter->code1, reg_base + ISO11898_ACCEPTANCE_CODE_1_OFFSET);
+ putreg32(filter->code2, reg_base + ISO11898_ACCEPTANCE_CODE_2_OFFSET);
+ putreg32(filter->code3, reg_base + ISO11898_ACCEPTANCE_CODE_3_OFFSET);
+ putreg32(filter->mask0, reg_base + ISO11898_ACCEPTANCE_MASK_0_OFFSET);
+ putreg32(filter->mask1, reg_base + ISO11898_ACCEPTANCE_MASK_1_OFFSET);
+ putreg32(filter->mask2, reg_base + ISO11898_ACCEPTANCE_MASK_2_OFFSET);
+ putreg32(filter->mask3, reg_base + ISO11898_ACCEPTANCE_MASK_3_OFFSET);
+
+ /* restore saved mode */
+ bflb_iso11898_set_mode(dev, mode);
+}
+
+void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+ if (mask) {
+ regval &= ~ISO11898_TRANSMIT_INT_EN;
+ } else {
+ regval |= ISO11898_TRANSMIT_INT_EN;
+ }
+
+ putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+}
+
+void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+ if (mask) {
+ regval &= ~ISO11898_RECEIVE_INT_EN;
+ } else {
+ regval |= ISO11898_RECEIVE_INT_EN;
+ }
+
+ putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+}
+
+void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+ if (mask) {
+ regval &= ~ISO11898_ERROR_INT_EN;
+ regval &= ~ISO11898_DATA_OVERRUN_INT_EN;
+ regval &= ~ISO11898_ERROR_PASSIVE_INT_EN;
+ regval &= ~ISO11898_ARB_LOST_INT_EN;
+ regval &= ~ISO11898_BUS_ERROR_INT_EN;
+ } else {
+ regval |= ISO11898_ERROR_INT_EN;
+ regval |= ISO11898_DATA_OVERRUN_INT_EN;
+ regval |= ISO11898_ERROR_PASSIVE_INT_EN;
+ regval |= ISO11898_ARB_LOST_INT_EN;
+ regval |= ISO11898_BUS_ERROR_INT_EN;
+ }
+
+ putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+}
+
+uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev)
+{
+ return getreg32(dev->reg_base + ISO11898_INTERRUPT_OFFSET);
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_kys.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_kys.c
new file mode 100644
index 00000000..95fa9637
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_kys.c
@@ -0,0 +1,217 @@
+/**
+ ******************************************************************************
+ * @file bflb_kys.c
+ * @version V1.0
+ * @date 2022-11-17
+ * @brief This file is the low hardware abstraction layer file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2022 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "bflb_core.h"
+#include "bflb_kys.h"
+#include "bflb_clock.h"
+#include "bflb_l1c.h"
+#include "hardware/kys_reg.h"
+
+/**
+ * @brief keyscan init
+ *
+ * @param dev
+ * @param config
+ */
+void bflb_kys_init(struct bflb_device_s *dev, const struct bflb_kys_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t reg_val;
+
+ reg_base = dev->reg_base;
+ /* disable kys */
+ reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+ reg_val &= ~(KYS_KS_EN_MASK);
+ putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+
+ /* mask all interrupt before init */
+ reg_val = getreg32(reg_base + KYS_KS_INT_EN_OFFSET);
+#if defined(BL702)
+ reg_val &= ~(KYS_KS_INT_EN_MASK);
+#else
+ reg_val &= ~(KYS_KS_DONE_INT_EN_MASK |
+ KYS_KEYFIFO_FULL_INT_EN_MASK |
+ KYS_KEYFIFO_HALF_INT_EN_MASK |
+ KYS_KEYFIFO_QUARTER_INT_EN_MASK |
+ KYS_KEYFIFO_NONEMPTY_INT_EN_MASK |
+ KYS_GHOST_INT_EN_MASK);
+#endif
+
+ /* kys init */
+ reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+
+ reg_val &= ~(KYS_COL_NUM_MASK |
+ KYS_ROW_NUM_MASK |
+#if defined(BL702L)
+ KYS_FIFO_MODE_MASK |
+#endif
+ KYS_RC_EXT_MASK |
+ KYS_GHOST_EN_MASK |
+ KYS_DEG_EN_MASK |
+ KYS_DEG_CNT_MASK);
+ reg_val |= ((config->col - 1) << KYS_COL_NUM_SHIFT);
+ reg_val |= ((config->row - 1) << KYS_ROW_NUM_SHIFT);
+ reg_val |= ((config->idle_duration) << KYS_RC_EXT_SHIFT);
+ reg_val |= (config->ghost_en << KYS_GHOST_EN_SHIFT);
+ reg_val |= (config->deglitch_en << KYS_DEG_EN_SHIFT);
+ reg_val |= (config->deglitch_cnt << KYS_DEG_CNT_SHIFT);
+#if defined(BL702L)
+ reg_val |= (0x1 << KYS_FIFO_MODE_SHIFT);
+#endif
+ putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+}
+
+/**
+ * @brief keyscan enable
+ *
+ */
+void bflb_kys_enable(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t reg_val;
+
+ reg_base = dev->reg_base;
+ reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+ reg_val |= (0x1 << KYS_KS_EN_SHIFT);
+ putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+}
+
+/**
+ * @brief keyscan disable
+ *
+ */
+void bflb_kys_disable(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t reg_val;
+
+ reg_base = dev->reg_base;
+
+ reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+ reg_val &= ~(KYS_KS_EN_MASK);
+ putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+}
+
+/**
+ * @brief keyscan interrupt enable
+ *
+ * @param dev
+ * @param flag interrupt flag @KEYSCAN_INT_EN define
+ * @param enable enable or disable interrupt
+ */
+void bflb_kys_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t reg_val_en;
+
+ reg_base = dev->reg_base;
+ reg_val_en = getreg32(reg_base + KYS_KS_INT_EN_OFFSET);
+
+ if (enable) {
+ reg_val_en |= (flag);
+ } else {
+ reg_val_en &= ~(flag);
+ }
+ putreg32(reg_val_en, reg_base + KYS_KS_INT_EN_OFFSET);
+}
+
+/**
+ * @brief keyscan interrupt clear flag
+ *
+ * @param dev
+ * @param flag
+ */
+void bflb_kys_int_clear(struct bflb_device_s *dev, uint32_t flag)
+{
+ putreg32(flag, dev->reg_base + KYS_KEYCODE_CLR_OFFSET);
+}
+/**
+ * @brief keyscan get interrupt status
+ *
+ * @param dev
+ * @return uint32_t
+ */
+uint32_t bflb_kys_get_int_status(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t reg_sts_val, reg_mask_val;
+
+ reg_base = dev->reg_base;
+ reg_sts_val = getreg32(reg_base + KYS_KS_INT_STS_OFFSET);
+ reg_mask_val = getreg32(reg_base + KYS_KS_INT_EN_OFFSET);
+
+ return (reg_sts_val & (reg_mask_val));
+}
+
+#if defined(BL702L)
+/**
+ * @brief get keyscan keycode index in fifo
+ *
+ * @param dev
+ * @param fifo_head
+ * @param fifo_tail
+ * @param fifo_valid_cnt
+ *
+ */
+void bflb_kys_get_fifo_info(struct bflb_device_s *dev, uint8_t *fifo_head, uint8_t *fifo_tail, uint8_t *fifo_valid_cnt)
+{
+ uint32_t reg_base;
+ uint32_t reg_val;
+
+ reg_base = dev->reg_base;
+ reg_val = getreg32(reg_base + KYS_KEYFIFO_IDX_OFFSET);
+
+ *fifo_head = (uint8_t)(reg_val & 0x7);
+ *fifo_tail = (uint8_t)((reg_val & 0x700) >> 8);
+ *fifo_valid_cnt = (uint8_t)((reg_val & 0xf0000) >> 16);
+}
+
+#endif
+/**
+ * @brief get keyscan keycode value
+ *
+ * @param dev
+ * @param index
+ * @return uint8_t
+ */
+uint8_t bflb_kys_read_keyvalue(struct bflb_device_s *dev, uint8_t index)
+{
+#if defined(BL702L)
+ return (uint8_t)(getreg32(dev->reg_base + KYS_KEYFIFO_VALUE_OFFSET) & 0xff);
+#endif
+#if defined(BL702)
+ return (uint8_t)((getreg32(dev->reg_base + KYS_KEYFIFO_VALUE_OFFSET) >> (index * 8)) & 0xff);
+#endif
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_l1c.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_l1c.c
new file mode 100644
index 00000000..4e377e9f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_l1c.c
@@ -0,0 +1,188 @@
+#include "bflb_l1c.h"
+
+#if (defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)) && !defined(CPU_LP)
+#include "csi_core.h"
+void bflb_l1c_icache_enable(void)
+{
+ csi_icache_enable();
+}
+
+void bflb_l1c_icache_disable(void)
+{
+ csi_icache_disable();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_icache_invalid_all(void)
+{
+ csi_icache_invalid();
+}
+
+void bflb_l1c_dcache_enable(void)
+{
+ csi_dcache_enable();
+}
+
+void bflb_l1c_dcache_disable(void)
+{
+ csi_dcache_disable();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_all(void)
+{
+ csi_dcache_clean();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_all(void)
+{
+ csi_dcache_invalid();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_invalidate_all(void)
+{
+ csi_dcache_clean_invalid();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
+{
+ csi_dcache_clean_range(addr, size);
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size)
+{
+ csi_dcache_invalid_range(addr, size);
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size)
+{
+ csi_dcache_clean_invalid_range(addr, size);
+}
+#else
+
+#if defined(BL702) || defined(BL702L)
+extern void L1C_Cache_Enable_Set(uint8_t wayDisable);
+extern void L1C_Cache_Flush(void);
+#endif
+
+void bflb_l1c_icache_enable(void)
+{
+}
+
+void bflb_l1c_icache_disable(void)
+{
+#if defined(BL702) || defined(BL702L)
+ L1C_Cache_Enable_Set(0x0f);
+#endif
+}
+
+void bflb_l1c_icache_invalid_all(void)
+{
+}
+
+void bflb_l1c_dcache_enable(void)
+{
+}
+
+void bflb_l1c_dcache_disable(void)
+{
+}
+
+void bflb_l1c_dcache_clean_all(void)
+{
+}
+
+void bflb_l1c_dcache_invalidate_all(void)
+{
+#if defined(BL702) || defined(BL702L)
+ L1C_Cache_Flush();
+#endif
+}
+
+void bflb_l1c_dcache_clean_invalidate_all(void)
+{
+#if defined(BL702) || defined(BL702L)
+ L1C_Cache_Flush();
+#endif
+}
+
+void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
+{
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size)
+{
+#if defined(BL702) || defined(BL702L)
+ L1C_Cache_Flush();
+#endif
+}
+
+#if defined(BL702) || defined(BL702L)
+/****************************************************************************/ /**
+ * @brief L1C cache write set
+ *
+ * @param wt_en: L1C write through enable
+ * @param wb_en: L1C write back enable
+ * @param wa_en: L1C write allocate enable
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
+{
+ uint32_t regval = 0;
+
+ regval = getreg32(0x40009000 + 0x0);
+
+ if (wt_en) {
+ regval |= (1<<4);
+ } else {
+ regval &= ~(1<<4);
+ }
+
+ if (wb_en) {
+ regval |= (1<<5);
+ } else {
+ regval &= ~(1<<5);
+ }
+
+ if (wa_en) {
+ regval |= (1<<6);
+ } else {
+ regval &= ~(1<<6);
+ }
+
+ putreg32(regval, 0x40009000+0x0);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Get hit count
+ *
+ * @param hit_count_low: hit count low 32 bits pointer
+ * @param hit_count_high: hit count high 32 bits pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high)
+{
+ *hit_count_low = getreg32(0x40009000 + 0x4);
+ *hit_count_high = getreg32(0x40009000 + 0x8);
+}
+
+/****************************************************************************/ /**
+ * @brief Get miss count
+ *
+ * @param None
+ *
+ * @return Miss count
+ *
+*******************************************************************************/
+__WEAK
+uint32_t ATTR_TCM_SECTION bflb_l1c_miss_count_get(void)
+{
+ return getreg32(0x40009000 + 0xC);
+}
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_mjpeg.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_mjpeg.c
new file mode 100644
index 00000000..0414102e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_mjpeg.c
@@ -0,0 +1,569 @@
+#include "bflb_mjpeg.h"
+#include "hardware/mjpeg_reg.h"
+
+static void bflb_mjpeg_set_yuv422_interleave_order(struct bflb_device_s *dev, uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
+ regval &= ~MJPEG_REG_Y0_ORDER_MASK;
+ regval &= ~MJPEG_REG_U0_ORDER_MASK;
+ regval &= ~MJPEG_REG_Y1_ORDER_MASK;
+ regval &= ~MJPEG_REG_V0_ORDER_MASK;
+
+ regval |= (y0 << MJPEG_REG_Y0_ORDER_SHIFT);
+ regval |= (u0 << MJPEG_REG_U0_ORDER_SHIFT);
+ regval |= (y1 << MJPEG_REG_Y1_ORDER_SHIFT);
+ regval |= (v0 << MJPEG_REG_V0_ORDER_SHIFT);
+
+ putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
+}
+
+static void bflb_mjpeg_set_framesize(struct bflb_device_s *dev, uint16_t x, uint16_t y)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = 0;
+ regval |= (x << MJPEG_REG_FRAME_WBLK_SHIFT);
+ regval |= (y << MJPEG_REG_FRAME_HBLK_SHIFT);
+ putreg32(regval, reg_base + MJPEG_FRAME_SIZE_OFFSET);
+}
+
+void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s *config)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint16_t blocks;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_ENABLE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+
+ regval = 0;
+ regval |= (3 << MJPEG_REG_W_XLEN_SHIFT); /* burst count 16 increment */
+ regval |= MJPEG_REG_READ_FWRAP;
+ regval |= MJPEG_REG_MJPEG_BIT_ORDER;
+
+ switch (config->format) {
+ case MJPEG_FORMAT_YUV422_YUYV:
+ regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+ bflb_mjpeg_set_yuv422_interleave_order(dev, 0, 1, 2, 3);
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+ break;
+ case MJPEG_FORMAT_YUV422_YVYU:
+ regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+ bflb_mjpeg_set_yuv422_interleave_order(dev, 0, 3, 2, 1);
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+ break;
+ case MJPEG_FORMAT_YUV422_UYVY:
+ regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+ bflb_mjpeg_set_yuv422_interleave_order(dev, 1, 0, 3, 2);
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+ break;
+ case MJPEG_FORMAT_YUV422_VYUY:
+ regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+ bflb_mjpeg_set_yuv422_interleave_order(dev, 1, 2, 3, 0);
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+ break;
+ case MJPEG_FORMAT_YUV422SP_NV16:
+ regval |= (2 << MJPEG_REG_YUV_MODE_SHIFT);
+ regval |= MJPEG_REG_ORDER_U_EVEN;
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+ break;
+ case MJPEG_FORMAT_YUV422SP_NV61:
+ regval |= (2 << MJPEG_REG_YUV_MODE_SHIFT);
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+ break;
+ case MJPEG_FORMAT_YUV420SP_NV12:
+ regval |= (0 << MJPEG_REG_YUV_MODE_SHIFT);
+ regval |= MJPEG_REG_ORDER_U_EVEN;
+
+ if (config->resolution_x % 16) {
+ regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
+ }
+
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 15) >> 4);
+ break;
+ case MJPEG_FORMAT_YUV420SP_NV21:
+ regval |= (0 << MJPEG_REG_YUV_MODE_SHIFT);
+
+ if (config->resolution_x % 16) {
+ regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
+ }
+
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 15) >> 3);
+ break;
+ case MJPEG_FORMAT_GRAY:
+ regval |= (1 << MJPEG_REG_YUV_MODE_SHIFT);
+
+ if (config->resolution_x % 16) {
+ regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
+ }
+
+ if (config->resolution_y % 16) {
+ regval |= MJPEG_REG_LAST_HF_HBLK_DMY;
+ }
+
+ bflb_mjpeg_set_framesize(dev, (config->resolution_x + 7) >> 3, (config->resolution_y + 7) >> 3);
+ break;
+
+ default:
+ break;
+ }
+
+ putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_WAIT_CYCLE_MASK;
+ regval |= (0x100 << MJPEG_REG_MJPEG_WAIT_CYCLE_SHIFT);
+ regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_SWAP_MODE_OFFSET);
+ regval &= ~MJPEG_REG_W_SWAP_MODE;
+ putreg32(regval, reg_base + MJPEG_SWAP_MODE_OFFSET);
+
+ putreg32(config->input_bufaddr0, reg_base + MJPEG_YY_FRAME_ADDR_OFFSET);
+ putreg32(config->input_bufaddr1, reg_base + MJPEG_UV_FRAME_ADDR_OFFSET);
+
+ blocks = config->rows / 8;
+
+ switch (config->format) {
+ case MJPEG_FORMAT_YUV422_YUYV:
+ case MJPEG_FORMAT_YUV422_YVYU:
+ case MJPEG_FORMAT_YUV422_UYVY:
+ case MJPEG_FORMAT_YUV422_VYUY:
+ putreg32((0 << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET); /* uv << 16 + yy */
+ break;
+ case MJPEG_FORMAT_YUV422SP_NV16:
+ case MJPEG_FORMAT_YUV422SP_NV61:
+ putreg32((blocks << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET);
+ break;
+ case MJPEG_FORMAT_YUV420SP_NV12:
+ case MJPEG_FORMAT_YUV420SP_NV21:
+ putreg32((blocks << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET);
+ break;
+ case MJPEG_FORMAT_GRAY:
+ putreg32((0 << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET);
+ break;
+
+ default:
+ break;
+ }
+
+ putreg32(config->output_bufaddr, reg_base + MJPEG_JPEG_FRAME_ADDR_OFFSET);
+ putreg32(config->output_bufsize / 128, reg_base + MJPEG_JPEG_STORE_MEMORY_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+ regval &= ~MJPEG_REG_INT_NORMAL_EN;
+ regval &= ~MJPEG_REG_INT_CAM_EN;
+ regval &= ~MJPEG_REG_INT_MEM_EN;
+ regval &= ~MJPEG_REG_INT_FRAME_EN;
+ regval &= ~MJPEG_REG_INT_IDLE_EN;
+ regval &= ~MJPEG_REG_INT_SWAP_EN;
+ regval &= ~MJPEG_REG_FRAME_CNT_TRGR_INT_MASK;
+ regval |= (1 << MJPEG_REG_FRAME_CNT_TRGR_INT_SHIFT); /* trigger int with one frame */
+ putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
+ regval &= ~MJPEG_REG_HEAD_BYTE_MASK;
+ regval &= ~MJPEG_REG_TAIL_EXP;
+ putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
+
+ /* Clear interrupt */
+ putreg32(0x3F00, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
+
+ static uint16_t q_table_50_y[64] = {
+ 16, 11, 10, 16, 24, 40, 51, 61,
+ 12, 12, 14, 19, 26, 58, 60, 55,
+ 14, 13, 16, 24, 40, 57, 69, 56,
+ 14, 17, 22, 29, 51, 87, 80, 62,
+ 18, 22, 37, 56, 68, 109, 103, 77,
+ 24, 35, 55, 64, 81, 104, 113, 92,
+ 49, 64, 78, 87, 103, 121, 120, 101,
+ 72, 92, 95, 98, 112, 100, 103, 99
+ };
+
+ static uint16_t q_table_50_uv[64] = {
+ 17, 18, 24, 47, 99, 99, 99, 99,
+ 18, 21, 26, 66, 99, 99, 99, 99,
+ 24, 26, 56, 99, 99, 99, 99, 99,
+ 47, 66, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99
+ };
+
+ uint16_t tmp_table_y[64] = { 0 };
+ uint16_t tmp_table_uv[64] = { 0 };
+
+ if (config->input_yy_table) {
+ bflb_mjpeg_calculate_quantize_table(config->quality, config->input_yy_table, tmp_table_y);
+ } else {
+ bflb_mjpeg_calculate_quantize_table(config->quality, q_table_50_y, tmp_table_y);
+ }
+ if (config->input_uv_table) {
+ bflb_mjpeg_calculate_quantize_table(config->quality, config->input_uv_table, tmp_table_uv);
+ } else {
+ bflb_mjpeg_calculate_quantize_table(config->quality, q_table_50_uv, tmp_table_uv);
+ }
+
+ bflb_mjpeg_fill_quantize_table(dev, tmp_table_y, tmp_table_uv);
+}
+
+void bflb_mjpeg_start(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
+ regval |= MJPEG_REG_MJPEG_ENABLE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+}
+
+void bflb_mjpeg_stop(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_ENABLE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+}
+
+void bflb_mjpeg_sw_run(struct bflb_device_s *dev, uint8_t frame_count)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_SW_KICK_MODE;
+ regval &= ~MJPEG_REG_SW_FRAME_MASK;
+ regval |= (frame_count << MJPEG_REG_SW_FRAME_SHIFT);
+ regval |= MJPEG_REG_MJPEG_SW_MODE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval |= MJPEG_REG_MJPEG_SW_RUN;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_SW_RUN;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_kick_run(struct bflb_device_s *dev, uint16_t kick_count)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval |= MJPEG_REG_SW_KICK_MODE;
+ regval &= ~MJPEG_REG_SW_FRAME_MASK;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval |= MJPEG_REG_MJPEG_SW_MODE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_YUV_MEM_SW_OFFSET);
+ regval &= ~MJPEG_REG_SW_KICK_HBLK_MASK;
+ regval |= (kick_count << MJPEG_REG_SW_KICK_HBLK_SHIFT);
+ putreg32(regval, reg_base + MJPEG_YUV_MEM_SW_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval |= MJPEG_REG_MJPEG_SW_RUN;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_SW_RUN;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_kick_stop(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_SW_KICK_MODE;
+ regval &= ~MJPEG_REG_SW_FRAME_MASK;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval |= MJPEG_REG_MJPEG_SW_MODE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_kick(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval |= MJPEG_REG_SW_KICK;
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+
+ if (mask) {
+ regval &= ~MJPEG_REG_INT_NORMAL_EN;
+ } else {
+ regval |= MJPEG_REG_INT_NORMAL_EN;
+ }
+
+ putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
+}
+
+void bflb_mjpeg_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+
+ if (mask) {
+ regval &= ~MJPEG_REG_INT_CAM_EN;
+ regval &= ~MJPEG_REG_INT_MEM_EN;
+ regval &= ~MJPEG_REG_INT_FRAME_EN;
+ regval &= ~MJPEG_REG_INT_IDLE_EN;
+ regval &= ~MJPEG_REG_INT_SWAP_EN;
+ } else {
+ regval |= MJPEG_REG_INT_CAM_EN;
+ regval |= MJPEG_REG_INT_MEM_EN;
+ regval |= MJPEG_REG_INT_FRAME_EN;
+ regval |= MJPEG_REG_INT_IDLE_EN;
+ regval |= MJPEG_REG_INT_SWAP_EN;
+ }
+
+ putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
+}
+
+uint32_t bflb_mjpeg_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+ regval &= 0xf0;
+
+ return regval;
+}
+
+void bflb_mjpeg_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg32(int_clear, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
+}
+
+uint8_t bflb_mjpeg_get_frame_count(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ return ((getreg32(reg_base + MJPEG_CONTROL_3_OFFSET) & MJPEG_FRAME_VALID_CNT_MASK) >> MJPEG_FRAME_VALID_CNT_SHIFT);
+}
+
+void bflb_mjpeg_pop_one_frame(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg32(1, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
+}
+
+uint32_t bflb_mjpeg_get_frame_info(struct bflb_device_s *dev, uint8_t **pic)
+{
+ uint32_t bytes;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ *pic = (uint8_t *)getreg32(reg_base + MJPEG_START_ADDR0_OFFSET);
+ bytes = (getreg32(reg_base + MJPEG_BIT_CNT0_OFFSET) + 7) >> 3;
+
+ return bytes;
+}
+
+void bflb_mjpeg_calculate_quantize_table(uint8_t quality, uint16_t *input_table, uint16_t *output_table)
+{
+ uint32_t scale_factor, i;
+
+ if (quality == 0) {
+ quality = 1;
+ } else if (quality > 100) {
+ quality = 100;
+ }
+
+ if (quality < 50) {
+ scale_factor = 5000000 / quality;
+ } else {
+ scale_factor = 200000 - quality * 2000;
+ }
+
+ for (i = 0; i < 64; i++) {
+ output_table[i] = (input_table[i] * scale_factor + 50000) / 100000;
+
+ if (output_table[i] == 0) {
+ output_table[i] = 1;
+ } else if (output_table[i] > 0xff) {
+ output_table[i] = 0xff;
+ }
+ }
+}
+
+void bflb_mjpeg_fill_quantize_table(struct bflb_device_s *dev, uint16_t *input_yy, uint16_t *input_uv)
+{
+#define MJPEG_Q_PARAM_00_OFFSET (0x400)
+#define MJPEG_Q_PARAM_40_OFFSET (0x480)
+
+ uint8_t i, j;
+ uint16_t tmp1;
+ uint16_t tmp2;
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ for (i = 0; i < 8; i++) {
+ for (j = 0; j < 4; j++) {
+ tmp1 = 2048 / input_yy[16 * j + i];
+ tmp2 = 2048 / input_yy[16 * j + i + 8];
+
+ if (20480 / input_yy[16 * j + i] % 10 > 4) {
+ tmp1++;
+ }
+
+ if (20480 / input_yy[16 * j + i + 8] % 10 > 4) {
+ tmp2++;
+ }
+
+ putreg32(tmp1 | tmp2 << 16, reg_base + MJPEG_Q_PARAM_00_OFFSET + (i * 4 + j) * 4);
+ }
+ }
+
+ for (i = 0; i < 8; i++) {
+ for (j = 0; j < 4; j++) {
+ tmp1 = 2048 / input_uv[16 * j + i];
+ tmp2 = 2048 / input_uv[16 * j + i + 8];
+
+ if (20480 / input_uv[16 * j + i] % 10 > 4) {
+ tmp1++;
+ }
+
+ if (20480 / input_uv[16 * j + i + 8] % 10 > 4) {
+ tmp2++;
+ }
+
+ putreg32(tmp1 | tmp2 << 16, reg_base + MJPEG_Q_PARAM_40_OFFSET + (i * 4 + j) * 4);
+ }
+ }
+
+ regval = getreg32(reg_base + MJPEG_Q_ENC_OFFSET);
+ regval |= MJPEG_REG_Q_SRAM_SW;
+ putreg32(regval, reg_base + MJPEG_Q_ENC_OFFSET);
+}
+
+void bflb_mjpeg_fill_jpeg_header_tail(struct bflb_device_s *dev, uint8_t *header, uint32_t header_len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ arch_memcpy_fast((void *)(reg_base + 0x800), header, header_len);
+
+ regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
+ regval &= ~MJPEG_REG_HEAD_BYTE_MASK;
+ regval |= (header_len << MJPEG_REG_HEAD_BYTE_SHIFT);
+ regval |= MJPEG_REG_TAIL_EXP;
+ putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
+}
+
+void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, uint8_t uv)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+ regval &= ~MJPEG_REG_YY_DVP2AXI_SEL_MASK;
+ regval &= ~MJPEG_REG_UV_DVP2AXI_SEL_MASK;
+ regval |= (yy << MJPEG_REG_YY_DVP2AXI_SEL_SHIFT);
+ regval |= (uv << MJPEG_REG_UV_DVP2AXI_SEL_SHIFT);
+ putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+int bflb_mjpeg_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case MJPEG_CMD_SET_INPUTADDR0:
+ putreg32(arg, reg_base + MJPEG_YY_FRAME_ADDR_OFFSET);
+ break;
+ case MJPEG_CMD_SET_INPUTADDR1:
+ putreg32(arg, reg_base + MJPEG_UV_FRAME_ADDR_OFFSET);
+ break;
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_mtimer.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_mtimer.c
new file mode 100644
index 00000000..27b09d5b
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_mtimer.c
@@ -0,0 +1,123 @@
+#include "bflb_mtimer.h"
+#include "bflb_core.h"
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#include
+#else
+#include
+#endif
+
+static void (*systick_callback)(void);
+static uint64_t current_set_ticks = 0;
+
+static void systick_isr(int irq, void *arg)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ *(volatile uint64_t *)(CLIC_CTRL_BASE + CLIC_MTIMECMP_OFFSET) += current_set_ticks;
+#else
+ csi_coret_config(current_set_ticks, 7);
+#endif
+ systick_callback();
+}
+
+void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void))
+{
+ bflb_irq_disable(7);
+
+ current_set_ticks = ticks;
+ systick_callback = interruptfun;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ *(volatile uint64_t *)(CLIC_CTRL_BASE + CLIC_MTIMECMP_OFFSET) = (*(volatile uint64_t *)(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET)) + ticks;
+#else
+ csi_coret_config_use(ticks, 7);
+#endif
+
+ bflb_irq_attach(7, systick_isr, NULL);
+ bflb_irq_enable(7);
+}
+
+__WEAK uint32_t ATTR_TCM_SECTION bflb_mtimer_get_freq(void)
+{
+ return 1 * 1000 * 1000;
+}
+
+uint64_t ATTR_TCM_SECTION bflb_mtimer_get_time_us()
+{
+ volatile uint64_t tmp_low, tmp_high, tmp_low1, tmp_high1;
+
+ do {
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ tmp_high = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET + 4);
+ tmp_low = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET);
+ tmp_low1 = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET);
+ tmp_high1 = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET + 4);
+#else
+ tmp_high = (uint64_t)csi_coret_get_valueh();
+ tmp_low = (uint64_t)csi_coret_get_value();
+ tmp_low1 = (uint64_t)csi_coret_get_value();
+ tmp_high1 = (uint64_t)csi_coret_get_valueh();
+#endif
+ } while (tmp_low > tmp_low1 || tmp_high != tmp_high1);
+#ifdef CONFIG_MTIMER_CUSTOM_FREQUENCE
+ return ((uint64_t)(((tmp_high1 << 32) + tmp_low1)) * ((uint64_t)(1 * 1000 * 1000)) / bflb_mtimer_get_freq());
+#else
+ return (uint64_t)(((tmp_high1 << 32) + tmp_low1));
+#endif
+}
+
+uint32_t ATTR_TCM_SECTION __attribute__((weak)) __div64_32(uint64_t *n, uint32_t base)
+{
+ uint64_t rem = *n;
+ uint64_t b = base;
+ uint64_t res, d = 1;
+ uint32_t high = rem >> 32;
+
+ res = 0;
+ if (high >= base) {
+ high /= base;
+ res = (uint64_t) high << 32;
+ rem -= (uint64_t) (high*base) << 32;
+ }
+ while ((int64_t)b > 0 && b < rem) {
+ b = b+b;
+ d = d+d;
+ }
+
+ do {
+ if (rem >= b) {
+ rem -= b;
+ res += d;
+ }
+ b >>= 1;
+ d >>= 1;
+ } while (d);
+
+ *n = res;
+ return rem;
+}
+
+uint64_t ATTR_TCM_SECTION bflb_mtimer_get_time_ms()
+{
+#ifdef BFLB_BOOT2
+ uint64_t ret = bflb_mtimer_get_time_us();
+ __div64_32(&ret, 1000);
+ return ret;
+#else
+ return bflb_mtimer_get_time_us() / 1000;
+#endif
+}
+
+void ATTR_TCM_SECTION bflb_mtimer_delay_us(uint32_t time)
+{
+ uint64_t start_time = bflb_mtimer_get_time_us();
+
+ while (bflb_mtimer_get_time_us() - start_time < time) {
+ }
+}
+
+void ATTR_TCM_SECTION bflb_mtimer_delay_ms(uint32_t time)
+{
+ uint64_t start_time = bflb_mtimer_get_time_ms();
+
+ while (bflb_mtimer_get_time_ms() - start_time < time) {
+ }
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_pwm_v1.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_pwm_v1.c
new file mode 100644
index 00000000..766c6e92
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_pwm_v1.c
@@ -0,0 +1,278 @@
+#include "bflb_pwm_v1.h"
+#include "bflb_clock.h"
+#include "hardware/pwm_v1_reg.h"
+
+void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struct bflb_pwm_v1_channel_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ /* stop pwm */
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval |= PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval &= PWM_STS_TOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval == 0);
+
+ /* config clock source and dividor */
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval &= ~PWM_REG_CLK_SEL_MASK;
+ if (config->clk_source == BFLB_SYSTEM_XCLK) {
+ regval |= (0 << PWM_REG_CLK_SEL_SHIFT);
+ } else if (config->clk_source == BFLB_SYSTEM_PBCLK) {
+ regval |= (1 << PWM_REG_CLK_SEL_SHIFT);
+ } else if (config->clk_source == BFLB_SYSTEM_32K_CLK) {
+ regval |= (2 << PWM_REG_CLK_SEL_SHIFT);
+ } else {
+ }
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+ regval = getreg32(reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20);
+ regval &= ~PWM_CLK_DIV_MASK;
+ regval |= (uint32_t)config->clk_div << PWM_CLK_DIV_SHIFT;
+ putreg32(regval, reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20);
+
+ /* config pwm period */
+ regval = getreg32(reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+ regval &= ~PWM_PERIOD_MASK;
+ regval |= (uint32_t)config->period << PWM_PERIOD_SHIFT;
+ putreg32(regval, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+}
+
+void bflb_pwm_v1_channel_deinit(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ /* stop pwmx */
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval |= PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval &= PWM_STS_TOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval == 0);
+
+ /* restore pwmx_clkdiv register with default value */
+ putreg32(0, reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20);
+
+ /* restore pwmx_thre1 register with default value */
+ putreg32(0, reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
+
+ /* restore pwmx_thre2 register with default value */
+ putreg32(0, reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
+
+ /* restore pwmx_period register with default value */
+ putreg32(0, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+
+ /* restore pwmx_config register with default value */
+ regval = PWM_STOP_MODE;
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+ /* restore pwmx_interrupt register with default value */
+ putreg32(0, reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+
+ /* clear all interrupt */
+ putreg32(0xFFFFFFFF, reg_base + PWM_INT_CONFIG_OFFSET);
+}
+
+void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t start_time;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval &= ~PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval &= PWM_STS_TOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval != 0);
+}
+
+void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t start_time;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval |= PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ regval &= PWM_STS_TOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval == 0);
+}
+
+void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t period)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+ regval &= ~PWM_PERIOD_MASK;
+ regval |= (uint32_t)period << PWM_PERIOD_SHIFT;
+ putreg32(regval, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+}
+
+void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
+ regval &= ~PWM_THRE1_MASK;
+ regval |= low_threhold;
+ putreg32(regval, reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
+
+ regval = getreg32(reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
+ regval &= ~PWM_THRE2_MASK;
+ regval |= high_threhold;
+ putreg32(regval, reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
+}
+
+void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+ if (enable) {
+ regval |= PWM_INT_ENABLE;
+ } else {
+ regval &= ~PWM_INT_ENABLE;
+ }
+ putreg32(regval, reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+}
+
+uint32_t bflb_pwm_v1_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET);
+ return (regval);
+}
+
+void bflb_pwm_v1_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t timeout_count = 160 * 1000;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET);
+ regval |= int_clear;
+ putreg32(regval, dev->reg_base + PWM_INT_CONFIG_OFFSET);
+ do {
+ regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET);
+ timeout_count--;
+ if (timeout_count == 0) {
+ break;
+ }
+ } while (regval & (int_clear >> PWM_INT_CLEAR_SHIFT));
+
+ regval &= ~int_clear;
+ putreg32(regval, dev->reg_base + PWM_INT_CONFIG_OFFSET);
+}
+
+int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ switch (cmd) {
+ case PWM_CMD_SET_STOP_MODE:
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ if (arg == PWM_STOP_MODE_ABRUPT) {
+ regval &= ~PWM_STOP_MODE;
+ } else {
+ regval |= PWM_STOP_MODE;
+ }
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ break;
+
+ case PWM_CMD_SET_OUT_INVERT:
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ if (arg) {
+ regval |= PWM_OUT_INV;
+ } else {
+ regval &= ~PWM_OUT_INV;
+ }
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ break;
+
+ case PWM_CMD_SET_SW_MODE:
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ if (arg) {
+ regval |= PWM_SW_MODE;
+ } else {
+ regval &= ~PWM_SW_MODE;
+ }
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ break;
+
+ case PWM_CMD_SET_SW_FORCE_VALUE:
+ regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ if (arg) {
+ regval |= PWM_SW_FORCE_VAL;
+ } else {
+ regval &= ~PWM_SW_FORCE_VAL;
+ }
+ putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+ break;
+
+ case PWM_CMD_SET_REPT_COUNT:
+ regval = getreg32(reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+ regval &= ~(PWM_INT_PERIOD_CNT_MASK);
+ regval |= (arg << PWM_INT_PERIOD_CNT_SHIFT);
+ putreg32(regval, reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+ break;
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_pwm_v2.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_pwm_v2.c
new file mode 100644
index 00000000..c70164da
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_pwm_v2.c
@@ -0,0 +1,388 @@
+#include "bflb_pwm_v2.h"
+#include "bflb_clock.h"
+#include "hardware/pwm_v2_reg.h"
+
+void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ /* stop pwm */
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval |= PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval &= PWM_STS_STOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval == 0);
+
+ /* config clock source and dividor */
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval &= ~PWM_REG_CLK_SEL_MASK;
+ if (config->clk_source == BFLB_SYSTEM_XCLK) {
+ regval |= (0 << PWM_REG_CLK_SEL_SHIFT);
+ } else if (config->clk_source == BFLB_SYSTEM_PBCLK) {
+ regval |= (1 << PWM_REG_CLK_SEL_SHIFT);
+ } else if (config->clk_source == BFLB_SYSTEM_32K_CLK) {
+ regval |= (2 << PWM_REG_CLK_SEL_SHIFT);
+ } else {
+ }
+ regval &= ~PWM_CLK_DIV_MASK;
+ regval |= (uint32_t)config->clk_div << PWM_CLK_DIV_SHIFT;
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+ /* config pwm period */
+ regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+ regval &= ~PWM_PERIOD_MASK;
+ regval |= (uint32_t)config->period << PWM_PERIOD_SHIFT;
+ putreg32(regval, reg_base + PWM_MC0_PERIOD_OFFSET);
+}
+
+void bflb_pwm_v2_deinit(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ /* stop pwm */
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval |= PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval &= PWM_STS_STOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval == 0);
+
+ /* restore pwm_mc0_config0 register with default value */
+ regval = PWM_STS_STOP | PWM_STOP_MODE | PWM_STOP_EN | PWM_ADC_TRG_SRC_MASK;
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+ /* restore pwm_mc0_config1 register with default value */
+ regval = PWM_CH3_NPL | PWM_CH3_PPL | PWM_CH2_NPL | PWM_CH2_PPL;
+ regval |= PWM_CH1_NPL | PWM_CH1_PPL | PWM_CH0_NPL | PWM_CH0_PPL;
+ regval |= PWM_CH3_NSI | PWM_CH2_NSI | PWM_CH1_NSI | PWM_CH0_NSI;
+ putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+
+ /* restore pwm_mc0_period register with default value */
+ putreg32(0, reg_base + PWM_MC0_PERIOD_OFFSET);
+
+ /* restore pwm_mc0_dead_time register with default value */
+ putreg32(0, reg_base + PWM_MC0_DEAD_TIME_OFFSET);
+
+ /* restore pwm_mc0_chx_thre(x=0...3) register with default value */
+ putreg32(0, reg_base + PWM_MC0_CH0_THRE_OFFSET);
+ putreg32(1, reg_base + PWM_MC0_CH1_THRE_OFFSET);
+ putreg32(2, reg_base + PWM_MC0_CH2_THRE_OFFSET);
+ putreg32(3, reg_base + PWM_MC0_CH3_THRE_OFFSET);
+
+ /* restore pwm_mc0_int_mask register with default value */
+ putreg32(0xFFFFFFFF, reg_base + PWM_MC0_INT_MASK_OFFSET);
+ /* clear all interrupt */
+ putreg32(0xFFFFFFFF, reg_base + PWM_MC0_INT_CLEAR_OFFSET);
+ /* restore pwm_mc0_int_en register with default value */
+ putreg32(0xFFFFFFFF, reg_base + PWM_MC0_INT_EN_OFFSET);
+}
+
+void bflb_pwm_v2_set_period(struct bflb_device_s *dev, uint16_t period)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+ regval &= ~PWM_PERIOD_MASK;
+ regval |= (uint32_t)period << PWM_PERIOD_SHIFT;
+ putreg32(regval, reg_base + PWM_MC0_PERIOD_OFFSET);
+}
+
+void bflb_pwm_v2_start(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval &= ~PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval &= PWM_STS_STOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval != 0);
+}
+
+void bflb_pwm_v2_stop(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval |= PWM_STOP_EN;
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+ start_time = bflb_mtimer_get_time_ms();
+ do {
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval &= PWM_STS_STOP;
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return;
+ }
+ } while (regval == 0);
+}
+
+float bflb_pwm_v2_get_frequency(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t tmp;
+ float src, div, period;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ /* get clock source frequency */
+ tmp = (regval & PWM_REG_CLK_SEL_MASK) >> PWM_REG_CLK_SEL_SHIFT;
+ switch (tmp) {
+ case 0:
+ src = (float)bflb_clk_get_system_clock(0); /* TODO: because this function has not been implemented */
+ break;
+ case 1:
+ src = (float)bflb_clk_get_system_clock(1); /* TODO: because this function has not been implemented */
+ break;
+ case 2:
+ src = (float)bflb_clk_get_system_clock(2); /* TODO: because this function has not been implemented */
+ break;
+ default:
+ src = 0.0f;
+ break;
+ }
+ /* get clock dividor */
+ tmp = (regval & PWM_CLK_DIV_MASK) >> PWM_CLK_DIV_SHIFT;
+ div = tmp ? (float)tmp : 1.0f;
+ /* get pwm period count */
+ regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+ tmp = (regval & PWM_PERIOD_MASK) >> PWM_PERIOD_SHIFT;
+ period = (float)tmp;
+ /* calculate freaueny */
+ return (src / div / period);
+}
+
+void bflb_pwm_v2_channel_init(struct bflb_device_s *dev, uint8_t ch, struct bflb_pwm_v2_channel_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+ if (config->positive_polarity == PWM_POLARITY_ACTIVE_LOW) {
+ regval &= ~(PWM_CH0_PPL << ch * 2);
+ } else {
+ regval |= (PWM_CH0_PPL << ch * 2);
+ }
+ if (config->negative_polarity == PWM_POLARITY_ACTIVE_LOW) {
+ regval &= ~(PWM_CH0_NPL << ch * 2);
+ } else {
+ regval |= (PWM_CH0_NPL << ch * 2);
+ }
+ if (config->positive_stop_state == PWM_STATE_ACTIVE) {
+ regval |= (PWM_CH0_PSI << ch * 4);
+ } else {
+ regval &= ~(PWM_CH0_PSI << ch * 4);
+ }
+ if (config->negative_stop_state == PWM_STATE_INACTIVE) {
+ regval &= ~(PWM_CH0_NSI << ch * 4);
+ } else {
+ regval |= (PWM_CH0_NSI << ch * 4);
+ }
+ if (config->positive_brake_state == PWM_STATE_ACTIVE) {
+ regval |= (PWM_CH0_PBS << ch * 2);
+ } else {
+ regval &= ~(PWM_CH0_PBS << ch * 2);
+ }
+ if (config->negative_brake_state == PWM_STATE_ACTIVE) {
+ regval |= (PWM_CH0_NBS << ch * 2);
+ } else {
+ regval &= ~(PWM_CH0_NBS << ch * 2);
+ }
+ putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+ regval = getreg32(reg_base + PWM_MC0_DEAD_TIME_OFFSET);
+ regval &= ~(PWM_CH0_DTG_MASK << ch * 8);
+ regval |= ((uint32_t)config->dead_time << ch * 8);
+ putreg32(regval, reg_base + PWM_MC0_DEAD_TIME_OFFSET);
+}
+
+void bflb_pwm_v2_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold)
+{
+ uint32_t regval;
+
+ regval = ((uint32_t)high_threhold << 16) | low_threhold;
+ putreg32(regval, dev->reg_base + PWM_MC0_CH0_THRE_OFFSET + ch * 4);
+}
+
+void bflb_pwm_v2_channel_positive_start(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+ regval |= (PWM_CH0_PEN << 4 * ch);
+ putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_channel_negative_start(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+ regval |= (PWM_CH0_NEN << 4 * ch);
+ putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_channel_positive_stop(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+ regval &= ~(PWM_CH0_PEN << 4 * ch);
+ putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_channel_negative_stop(struct bflb_device_s *dev, uint8_t ch)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+ regval &= ~(PWM_CH0_NEN << 4 * ch);
+ putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_int_enable(struct bflb_device_s *dev, uint32_t int_en, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval_mask, regval_en;
+
+ reg_base = dev->reg_base;
+ regval_mask = getreg32(reg_base + PWM_MC0_INT_MASK_OFFSET);
+ regval_en = getreg32(reg_base + PWM_MC0_INT_EN_OFFSET);
+ if (enable) {
+ regval_mask &= ~int_en;
+ regval_en |= int_en;
+ } else {
+ regval_mask |= int_en;
+ regval_en &= ~int_en;
+ }
+ putreg32(regval_mask, reg_base + PWM_MC0_INT_MASK_OFFSET);
+ putreg32(regval_en, reg_base + PWM_MC0_INT_EN_OFFSET);
+}
+
+void bflb_pwm_v2_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ putreg32(int_clear, dev->reg_base + PWM_MC0_INT_CLEAR_OFFSET);
+}
+
+uint32_t bflb_pwm_v2_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval_sts, regval_mask, regval_en;
+
+ reg_base = dev->reg_base;
+ regval_sts = getreg32(reg_base + PWM_MC0_INT_STS_OFFSET);
+ regval_mask = getreg32(reg_base + PWM_MC0_INT_MASK_OFFSET);
+ regval_en = getreg32(reg_base + PWM_MC0_INT_EN_OFFSET);
+ return (regval_sts & ~regval_mask & regval_en);
+}
+
+int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ switch (cmd) {
+ case PWM_CMD_SET_EXT_BRAKE_POLARITY:
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ if (arg == PWM_POLARITY_ACTIVE_HIGH) {
+ regval |= PWM_EXT_BREAK_PL;
+ } else {
+ regval &= ~PWM_EXT_BREAK_PL;
+ }
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+ break;
+
+ case PWM_CMD_SET_EXT_BRAKE_ENABLE:
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ if (arg == true) {
+ regval |= PWM_EXT_BREAK_EN;
+ } else {
+ regval &= ~PWM_EXT_BREAK_EN;
+ }
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+ break;
+
+ case PWM_CMD_SET_SW_BRAKE_ENABLE:
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ if (arg == true) {
+ regval |= PWM_SW_BREAK_EN;
+ } else {
+ regval &= ~PWM_SW_BREAK_EN;
+ }
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+ break;
+
+ case PWM_CMD_SET_STOP_ON_REPT:
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ if (arg == true) {
+ regval |= PWM_STOP_ON_REPT;
+ } else {
+ regval &= ~PWM_STOP_ON_REPT;
+ }
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+ break;
+
+ case PWM_CMD_SET_REPT_COUNT:
+ regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+ regval &= ~(PWM_INT_PERIOD_CNT_MASK);
+ regval |= (arg << PWM_INT_PERIOD_CNT_SHIFT);
+ putreg32(regval, reg_base + PWM_MC0_PERIOD_OFFSET);
+ break;
+
+ case PWM_CMD_SET_TRIG_ADC_SRC:
+ regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+ regval &= ~(PWM_ADC_TRG_SRC_MASK);
+ regval |= (arg << PWM_ADC_TRG_SRC_SHIFT);
+ putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+ break;
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_rtc.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_rtc.c
new file mode 100644
index 00000000..6287a8a7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_rtc.c
@@ -0,0 +1,76 @@
+#include "bflb_rtc.h"
+#include "hardware/rtc_reg.h"
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_RTC_BASE 0x4000F000
+#elif defined(BL808) || defined(BL606P) || defined(BL616)
+#define BFLB_RTC_BASE 0x2000F000
+#elif defined(BL628)
+#define BFLB_RTC_BASE 0x2008F000
+#endif
+
+void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t comp_l, comp_h;
+
+ reg_base = BFLB_RTC_BASE;
+
+ /* Clear & Disable RTC counter */
+ regval = getreg32(reg_base + HBN_CTL_OFFSET);
+ regval &= ~HBN_RTC_CTL_MASK;
+ putreg32(regval, reg_base + HBN_CTL_OFFSET);
+
+ /* Tigger RTC val read */
+ regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET);
+ regval |= HBN_RTC_TIME_LATCH;
+ putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+ regval &= ~HBN_RTC_TIME_LATCH;
+ putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+
+ /* Read RTC val */
+ comp_l = getreg32(reg_base + HBN_RTC_TIME_L_OFFSET);
+ comp_h = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff;
+
+ /* calculate RTC Comp time */
+ comp_l += (uint32_t)(time & 0xFFFFFFFF);
+ comp_h += (uint32_t)((time >> 32) & 0xFFFFFFFF);
+
+ /* Set RTC Comp time */
+ putreg32(comp_l, reg_base + HBN_TIME_L_OFFSET);
+ putreg32(comp_h, reg_base + HBN_TIME_H_OFFSET);
+
+ regval = getreg32(reg_base + HBN_CTL_OFFSET);
+ regval |= HBN_RTC_DLY_OPTION;
+ regval |= (0x01 << 1);
+ putreg32(regval, reg_base + HBN_CTL_OFFSET);
+
+ /* Enable RTC Counter */
+ regval = getreg32(reg_base + HBN_CTL_OFFSET);
+ regval |= (1 << 0);
+ putreg32(regval, reg_base + HBN_CTL_OFFSET);
+}
+
+uint64_t bflb_rtc_get_time(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint64_t time_l;
+ uint64_t time_h;
+
+ reg_base = BFLB_RTC_BASE;
+
+ /* Tigger RTC val read */
+ regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET);
+ regval |= HBN_RTC_TIME_LATCH;
+ putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+ regval &= ~HBN_RTC_TIME_LATCH;
+ putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+
+ /* Read RTC val */
+ time_l = getreg32(reg_base + HBN_RTC_TIME_L_OFFSET);
+ time_h = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff;
+
+ return (((uint64_t)time_h << 32) | (uint64_t)time_l);
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sdio2.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sdio2.c
new file mode 100644
index 00000000..114023a5
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sdio2.c
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file bflb_sdio2.c
+ * @version V1.0
+ * @date 2022-10-12
+ * @brief This file is the low hardware abstraction layer file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2022 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "../include/bflb_sdio2.h"
+#include "../include/hardware/sdio2_reg.h"
+
+//#define SDIO2_DRV_DBG(a, ...) printf(a, ##__VA_ARGS__)
+#define SDIO2_DRV_DBG(a, ...)
+#ifndef BOOTROM
+#define SDIO2_DRV_ERR(a, ...) printf("[Error]:" a, ##__VA_ARGS__)
+#else
+extern void bflb_bootrom_printf(char *fmt, ...);
+#define SDIO2_DRV_ERR(a, ...) bflb_bootrom_printf("[Error]:" a, ##__VA_ARGS__)
+#endif
+#define SDU_INT_HOST 0
+
+static uintptr_t local_tx_buf[SDIO2_MAX_PORT_NUM][SDIO2_BYTE_PER_BUF / sizeof(uintptr_t)] ATTR_NOCACHE_RAM_SECTION;
+static uintptr_t local_rx_buf[SDIO2_MAX_PORT_NUM][SDIO2_BYTE_PER_BUF / sizeof(uintptr_t)] ATTR_NOCACHE_RAM_SECTION;
+
+/****************************************************************************/ /**
+ * @brief Get sdio2 block size
+ *
+ * @param dev SDIO device pointer
+ *
+ * @return Block size
+ *
+*******************************************************************************/
+uint32_t bflb_sdio2_get_block_size(struct bflb_device_s *dev)
+{
+ uint16_t blk_size = 0;
+ uint32_t reg_base = dev->reg_base;
+
+ blk_size = getreg8(reg_base + SDIO2_FN1_BLK_SIZE_0_OFFSET);
+ blk_size |= ((getreg8(reg_base + SDIO2_FN1_BLK_SIZE_1_OFFSET) & SDIO2_FN1_BLK_SIZE_1_MASK) << 8);
+
+ return blk_size;
+}
+
+/****************************************************************************/ /**
+ * @brief sdio2 init
+ *
+ * @param dev: SDIO device pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_init(struct bflb_device_s *dev)
+{
+ uint32_t reg_base = dev->reg_base;
+ uint32_t regval = 0;
+
+ putreg16(0, reg_base + SDIO2_RD_BIT_MAP_OFFSET);
+ putreg16(0, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+
+ /* toggle SDIO_CCR_CIC_DnLdOvr on WL_SDIO_CCR_CARD_INT_CAUSE */
+ putreg8(SDIO2_CCR_CIC_DnLdOvr, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+ putreg8(0, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+
+ if (1) {
+ /* multiport */
+ regval = getreg32(reg_base + SDIO2_CONFIG2_OFFSET);
+ putreg32(regval | SDIO2_CONFIG2_MSK, reg_base + SDIO2_CONFIG2_OFFSET);
+ regval = getreg8(reg_base + SDIO2_CONFIG_OFFSET);
+ putreg8(regval | 0x00000010, reg_base + SDIO2_CONFIG_OFFSET);
+ }
+
+ /* unmask the interrupts */
+ putreg8(SDIO2_CCR_CIM_MASK, reg_base + SDIO2_CARD_INT_MASK_OFFSET);
+ /* select interrupt reset mode */
+ putreg8(0, reg_base + SDIO2_CARD_INT_MODE_OFFSET);
+
+ bflb_sdio2_tx_rx_queue_init(dev);
+
+ bflb_irq_attach(dev->irq_num, bflb_sdio2_isr, dev);
+ bflb_irq_enable(dev->irq_num);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief SDIO2 tx and rx queue init
+ *
+ * @param dev: SDIO device pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_tx_rx_queue_init(struct bflb_device_s *dev)
+{
+ uint32_t reg_base = dev->reg_base;
+ uint16_t wr_bit_map = getreg16(reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+
+ for (uint8_t i = 0; i < SDIO2_MAX_PORT_NUM; i++) {
+ if (!(wr_bit_map & (1 << i))) {
+ /* attach new buffer */
+ putreg8(i, reg_base + SDIO2_WRITE_INDEX_OFFSET);
+ putreg32((uint32_t)&local_rx_buf[i][0], reg_base + SDIO2_SQ_WRITE_BASE_OFFSET);
+ putreg16(1 << i, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+#if SDU_INT_HOST
+ putreg8((SDIO2_CCR_CS_ReadCISRdy | SDIO2_CCR_CS_DnLdRdy | SDIO2_CCR_CS_IORdy),
+ reg_base + SDIO2_CARD_TO_HOST_EVENT_OFFSET);
+#endif
+ }
+ }
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief SDIO2 check host ready
+ *
+ * @param dev: SDIO device pointer
+ *
+ * @return 1 for host ready, 0 for not
+ *
+*******************************************************************************/
+int bflb_sdio2_check_host_ready(struct bflb_device_s *dev)
+{
+ uint32_t reg_base = dev->reg_base;
+ uint32_t regval = 0;
+
+ regval = getreg8(reg_base + SDIO2_SCRATCH_OFFSET);
+
+ if (regval != 0) {
+ return 1;
+
+ } else {
+ return 0;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief SDIO2 send data,this function can be in user app context
+ *
+ * @param dev: SDIO device pointer
+ * @param qos: qos number for this data buffer to send
+ * @param buff: data buffer pointer
+ * @param len: data length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_send_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int len)
+{
+ uint32_t reg_base = dev->reg_base;
+ uint16_t rd_bit_map = getreg16(reg_base + SDIO2_RD_BIT_MAP_OFFSET);
+ static uint8_t curr_upld_port = 0;
+
+ if (rd_bit_map & (1 << curr_upld_port)) {
+ return -1;
+ }
+ arch_memcpy_fast(local_tx_buf[curr_upld_port], buff, len);
+ SDIO2_DRV_DBG("Copy port=%d,index=%d\r\n",curr_upld_port,local_tx_buf[curr_upld_port][0]);
+ putreg8(curr_upld_port, reg_base + SDIO2_READ_INDEX_OFFSET);
+ putreg16(SDIO2_BYTE_PER_BUF, reg_base + SDIO2_RD_LEN_OFFSET + curr_upld_port * 2);
+ putreg32((uint32_t)&local_tx_buf[curr_upld_port][0], reg_base + SDIO2_SQ_READ_BASE_OFFSET);
+ putreg16(1 << curr_upld_port, reg_base + SDIO2_RD_BIT_MAP_OFFSET);
+#if SDU_INT_HOST
+ putreg8(SDIO2_CCR_CS_UpLdRdy, reg_base + SDIO2_CARD_TO_HOST_EVENT_OFFSET);
+#endif
+ curr_upld_port++;
+ if(curr_upld_port == SDIO2_MAX_PORT_NUM){
+ curr_upld_port = 0;
+ }
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief SDIO2 receive data,this function can be in user app context
+ *
+ * @param dev: SDIO device pointer
+ * @param qos: qos number for this data buffer to receive
+ * @param buff: data buffer pointer
+ * @param len: data length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_recv_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int *len)
+{
+ static uint16_t curr_dnld_port = 0;
+ uint32_t reg_base = dev->reg_base;
+ uint16_t wr_bit_map = getreg16(reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+ uint8_t crcerror = 0;
+#if 0
+ uint8_t card_status = 0;
+
+ /* get card status */
+ card_status = getreg8(reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+#endif
+
+ /* get erro */
+ crcerror = getreg8(reg_base + SDIO2_HOST_TRANS_STATUS_OFFSET);
+
+#if 0
+ if (!(card_status & SDIO2_CCR_CIC_DnLdOvr)){
+ SDIO2_DRV_DBG("No data come from host\r\n");
+ return -1;
+ }
+#endif
+ if (crcerror & SDIO2_CCR_HOST_INT_DnLdCRC_err) {
+ SDIO2_DRV_ERR("RX CRC error\r\n");
+ }
+
+ if (!(wr_bit_map & (1 << curr_dnld_port))) {
+ arch_memcpy_fast(buff, local_rx_buf[curr_dnld_port], SDIO2_BYTE_PER_BUF);
+ SDIO2_DRV_DBG("Copy port=%d,index=%d\r\n",curr_dnld_port,buff[0]);
+ *len = SDIO2_BYTE_PER_BUF;
+ /* attach new buffer */
+ putreg8(curr_dnld_port, reg_base + SDIO2_WRITE_INDEX_OFFSET);
+ putreg32((uint32_t)&local_rx_buf[curr_dnld_port][0], reg_base + SDIO2_SQ_WRITE_BASE_OFFSET);
+ putreg16(1 << curr_dnld_port, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+#if SDU_INT_HOST
+ putreg8((SDIO2_CCR_CS_ReadCISRdy | SDIO2_CCR_CS_DnLdRdy | SDIO2_CCR_CS_IORdy),
+ reg_base + SDIO2_CARD_TO_HOST_EVENT_OFFSET);
+#endif
+ /* go to next */
+ curr_dnld_port++;
+ if (curr_dnld_port == SDIO2_MAX_PORT_NUM) {
+ curr_dnld_port = 0;
+ }
+ return 0;
+ }else{
+ return -1;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief sdio2 irq handler
+ *
+ * @param irq: sdio3 interrupt type
+ * @param arg: arg for callback
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_sdio2_isr(int irq, void *arg)
+{
+ struct bflb_device_s *dev = (struct bflb_device_s *)arg;
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+ uint8_t crcerror = 0;
+
+ reg_base = dev->reg_base;
+ regval = getreg8(reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+
+ /* clear interrupt */
+ putreg8(~regval | SDIO2_CCR_CIC_PwrUp, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+ /* get erro */
+ crcerror = getreg8(reg_base + SDIO2_HOST_TRANS_STATUS_OFFSET);
+
+ if ((regval & SDIO2_CCR_CIC_UpLdOvr)) {
+ SDIO2_DRV_DBG("TX interrupt come\r\n");
+ }
+
+ if ((regval & SDIO2_CCR_CIC_DnLdOvr) &&
+ !(crcerror & SDIO2_CCR_HOST_INT_DnLdCRC_err)) {
+ SDIO2_DRV_DBG("RX interrupt come\r\n");
+ }
+
+ if (crcerror & SDIO2_CCR_HOST_INT_DnLdCRC_err) {
+ SDIO2_DRV_ERR("RX CRC error\r\n");
+ }
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_aes.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_aes.c
new file mode 100644
index 00000000..ca2117e3
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_aes.c
@@ -0,0 +1,392 @@
+#include "bflb_sec_aes.h"
+#include "hardware/sec_eng_reg.h"
+
+#define CONFIG_BFLB_AES_USE_BE
+
+#define BFLB_PUT_LE32(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+#define BFLB_PUT_BE32(p) ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3]))
+
+volatile uint8_t hw_key_sel = 1;
+
+void bflb_aes_init(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+#ifdef CONFIG_BFLB_AES_USE_BE
+ putreg32(0x1f, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#else
+ putreg32(0x10, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#endif
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_AES_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_set_hwkey(uint8_t keysel)
+{
+ hw_key_sel = keysel;
+}
+
+void bflb_aes_set_mode(struct bflb_device_s *dev, uint8_t mode)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_0_BLOCK_MODE_MASK;
+ regval |= (mode << SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT);
+
+ if (mode == AES_MODE_CTR) {
+ regval |= SEC_ENG_SE_AES_0_DEC_KEY_SEL;
+ } else {
+ regval &= ~SEC_ENG_SE_AES_0_DEC_KEY_SEL; /* clear key to set new key */
+ }
+
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_setkey(struct bflb_device_s *dev, const uint8_t *key, uint16_t keybits)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint8_t mode;
+ uint8_t *temp_key = (uint8_t *)key;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
+
+ regval &= ~SEC_ENG_SE_AES_0_MODE_MASK;
+ regval &= ~SEC_ENG_SE_AES_0_HW_KEY_EN;
+ if (key == NULL) {
+ regval |= SEC_ENG_SE_AES_0_HW_KEY_EN;
+ }
+
+ if (keybits == 128) {
+ regval |= (0 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+ } else if (keybits == 192) {
+ regval |= (2 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+ } else if (keybits == 256) {
+ regval |= (1 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+ } else {
+ regval |= (3 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+ }
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+ if (key == NULL) {
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_KEY_SEL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_0_KEY_SEL_MASK;
+ regval |= (hw_key_sel << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_KEY_SEL_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_1_KEY_SEL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_1_KEY_SEL_MASK;
+ regval |= (hw_key_sel << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_1_KEY_SEL_OFFSET);
+ } else {
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_0_OFFSET);
+ temp_key += 4;
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_1_OFFSET);
+ temp_key += 4;
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_2_OFFSET);
+ temp_key += 4;
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_3_OFFSET);
+ temp_key += 4;
+
+ if (keybits == 192) {
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_4_OFFSET);
+ temp_key += 4;
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_5_OFFSET);
+ temp_key += 4;
+ } else if ((keybits == 256) || (mode == AES_MODE_XTS)) {
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_4_OFFSET);
+ temp_key += 4;
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_5_OFFSET);
+ temp_key += 4;
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_6_OFFSET);
+ temp_key += 4;
+ putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_7_OFFSET);
+ temp_key += 4;
+ }
+ }
+}
+
+int bflb_aes_encrypt(struct bflb_device_s *dev,
+ const uint8_t *input,
+ const uint8_t *iv,
+ uint8_t *output,
+ uint32_t len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint64_t start_time;
+ uint8_t mode;
+ uint8_t *temp_iv = (uint8_t *)iv;
+
+ reg_base = dev->reg_base;
+
+ if (len % 16) {
+ return -EINVAL;
+ }
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
+ if (temp_iv) {
+ regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
+ } else {
+ regval |= SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select last iv */
+ }
+ regval &= ~SEC_ENG_SE_AES_0_DEC_EN; /* Set AES encryption */
+ regval &= ~SEC_ENG_SE_AES_0_MSG_LEN_MASK;
+ regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
+ regval |= ((len / 16) << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+ mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
+
+ if (temp_iv) {
+ if (mode == AES_MODE_XTS) {
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+ temp_iv += 4;
+ } else {
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+ temp_iv += 4;
+ }
+ }
+
+ /* Set input and output address */
+ putreg32((uint32_t)input, reg_base + SEC_ENG_SE_AES_0_MSA_OFFSET);
+ putreg32((uint32_t)output, reg_base + SEC_ENG_SE_AES_0_MDA_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_AES_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+int bflb_aes_decrypt(struct bflb_device_s *dev,
+ const uint8_t *input,
+ const uint8_t *iv,
+ uint8_t *output,
+ uint32_t len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint64_t start_time;
+ uint8_t mode;
+ uint8_t *temp_iv = (uint8_t *)iv;
+
+ reg_base = dev->reg_base;
+
+ if (len % 16) {
+ return -EINVAL;
+ }
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
+ if (temp_iv) {
+ regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
+ } else {
+ regval |= SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select last iv */
+ }
+ regval |= SEC_ENG_SE_AES_0_DEC_EN; /* Set AES decryption */
+ regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
+ regval &= ~SEC_ENG_SE_AES_0_MSG_LEN_MASK;
+ regval |= ((len / 16) << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+ mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
+
+ if (temp_iv) {
+ if (mode == AES_MODE_XTS) {
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+ temp_iv += 4;
+ } else {
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+ temp_iv += 4;
+ putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+ temp_iv += 4;
+ }
+ }
+
+ /* Set input and output address */
+ putreg32((uint32_t)input, reg_base + SEC_ENG_SE_AES_0_MSA_OFFSET);
+ putreg32((uint32_t)output, reg_base + SEC_ENG_SE_AES_0_MDA_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_AES_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+void bflb_aes_link_init(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+#ifdef CONFIG_BFLB_AES_USE_BE
+ putreg32(0x1f, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#else
+ putreg32(0x10, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#endif
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_AES_0_LINK_MODE;
+ regval |= SEC_ENG_SE_AES_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_link_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_0_LINK_MODE;
+ regval &= ~SEC_ENG_SE_AES_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+int bflb_aes_link_update(struct bflb_device_s *dev,
+ uint32_t link_addr,
+ const uint8_t *input,
+ uint8_t *output,
+ uint32_t len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint64_t start_time;
+
+ reg_base = dev->reg_base;
+
+ if ((len % 16) || ((link_addr & 0x03))) {
+ return -EINVAL;
+ }
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+ /* Set link address */
+ putreg32(link_addr, reg_base + SEC_ENG_SE_AES_0_LINK_OFFSET);
+
+ /* Change source buffer address and destination buffer address */
+ *(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)input;
+ *(uint32_t *)(uintptr_t)(link_addr + 8) = (uint32_t)(uintptr_t)output;
+
+ /* Set data length */
+ *((uint16_t *)(uintptr_t)link_addr + 1) = len / 16;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_AES_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+void bflb_group0_request_aes_access(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+ if (((regval >> 2) & 0x03) == 0x03) {
+ putreg32(0x02, reg_base + SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+ if (((regval >> 2) & 0x03) == 0x01) {
+ }
+ }
+}
+
+void bflb_group0_release_aes_access(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg32(0x06, reg_base + SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET);
+}
+
+void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_AES_0_SBOOT_OFFSET);
+ regval |= (source << 0);
+ putreg32(0x02, reg_base + SEC_ENG_SE_AES_0_SBOOT_OFFSET);
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_irq.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_irq.c
new file mode 100644
index 00000000..99f2d296
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_irq.c
@@ -0,0 +1,176 @@
+#include "bflb_sec_irq.h"
+#include "hardware/sec_eng_reg.h"
+
+struct bflb_sec_irq_callback {
+ void (*handler)(void *arg);
+ void *arg;
+};
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define BFLB_SEC_ENG_BASE ((uint32_t)0x40004000)
+#elif defined(BL616) || defined(BL606P) || defined(BL808)
+#define BFLB_SEC_ENG_BASE ((uint32_t)0x20004000)
+#elif defined(BL628)
+#define BFLB_SEC_ENG_BASE ((uint32_t)0x20080000)
+#endif
+
+struct bflb_sec_irq_callback sec_eng_callback[6];
+
+void sec_eng_isr(int irq, void *arg)
+{
+ uint32_t regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ if (regval & SEC_ENG_SE_AES_0_INT) {
+ regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].handler) {
+ sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].arg);
+ }
+ }
+
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ if (regval & SEC_ENG_SE_SHA_0_INT) {
+ regval |= SEC_ENG_SE_SHA_0_INT_CLR_1T;
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].handler) {
+ sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].arg);
+ }
+ }
+
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+ if (regval & SEC_ENG_SE_PKA_0_INT) {
+ regval |= SEC_ENG_SE_PKA_0_INT_CLR_1T;
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+ if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].handler) {
+ sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].arg);
+ }
+ }
+
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ if (regval & SEC_ENG_SE_TRNG_0_INT) {
+ regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].handler) {
+ sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].arg);
+ }
+ }
+
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+ if (regval & SEC_ENG_SE_GMAC_0_INT) {
+ regval |= SEC_ENG_SE_GMAC_0_INT_CLR_1T;
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+ if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].handler) {
+ sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].arg);
+ }
+ }
+}
+
+void bflb_sec_int_mask(uint8_t sec_type, bool mask)
+{
+ uint32_t regval;
+
+ switch (sec_type) {
+ case BFLB_SEC_ENG_IRQ_TYPE_AES:
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ if (mask) {
+ regval |= SEC_ENG_SE_AES_0_INT_MASK;
+ } else {
+ regval &= ~SEC_ENG_SE_AES_0_INT_MASK;
+ }
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+ break;
+ case BFLB_SEC_ENG_IRQ_TYPE_SHA:
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ if (mask) {
+ regval |= SEC_ENG_SE_SHA_0_INT_MASK;
+ } else {
+ regval &= ~SEC_ENG_SE_SHA_0_INT_MASK;
+ }
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ break;
+ case BFLB_SEC_ENG_IRQ_TYPE_PKA:
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+ if (mask) {
+ regval |= SEC_ENG_SE_PKA_0_INT_MASK;
+ } else {
+ regval &= ~SEC_ENG_SE_PKA_0_INT_MASK;
+ }
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+ break;
+ case BFLB_SEC_ENG_IRQ_TYPE_TRNG:
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ if (mask) {
+ regval |= SEC_ENG_SE_TRNG_0_INT_MASK;
+ } else {
+ regval &= ~SEC_ENG_SE_TRNG_0_INT_MASK;
+ }
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ break;
+ case BFLB_SEC_ENG_IRQ_TYPE_GMAC:
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+ if (mask) {
+ regval |= SEC_ENG_SE_GMAC_0_INT_MASK;
+ } else {
+ regval &= ~SEC_ENG_SE_GMAC_0_INT_MASK;
+ }
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+ break;
+ case BFLB_SEC_ENG_IRQ_TYPE_CDET:
+ regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_CDET_0_CTRL_0_OFFSET);
+ if (mask) {
+ regval |= SEC_ENG_SE_CDET_0_INT_MASK;
+ } else {
+ regval &= ~SEC_ENG_SE_CDET_0_INT_MASK;
+ }
+ putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_CDET_0_CTRL_0_OFFSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void bflb_sec_irq_attach(uint8_t sec_type, void (*callback)(void *arg), void *arg)
+{
+ sec_eng_callback[sec_type].handler = callback;
+ sec_eng_callback[sec_type].arg = arg;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+ bflb_irq_attach(25, sec_eng_isr, NULL);
+ bflb_irq_attach(26, sec_eng_isr, NULL);
+ bflb_irq_attach(27, sec_eng_isr, NULL);
+ bflb_irq_attach(28, sec_eng_isr, NULL);
+ bflb_irq_attach(29, sec_eng_isr, NULL);
+ bflb_irq_attach(30, sec_eng_isr, NULL);
+ bflb_irq_enable(25);
+ bflb_irq_enable(26);
+ bflb_irq_enable(27);
+ bflb_irq_enable(28);
+ bflb_irq_enable(29);
+ bflb_irq_enable(30);
+#elif (defined(BL606P) || defined(BL808)) && (defined(CPU_M0) || defined(CPU_LP))
+ bflb_irq_attach(25, sec_eng_isr, NULL);
+ bflb_irq_attach(26, sec_eng_isr, NULL);
+ bflb_irq_attach(27, sec_eng_isr, NULL);
+ bflb_irq_attach(28, sec_eng_isr, NULL);
+ bflb_irq_enable(25);
+ bflb_irq_enable(26);
+ bflb_irq_enable(27);
+ bflb_irq_enable(28);
+#elif defined(BL616) || defined(BL628)
+ bflb_irq_attach(25, sec_eng_isr, NULL);
+ bflb_irq_attach(26, sec_eng_isr, NULL);
+ bflb_irq_attach(27, sec_eng_isr, NULL);
+ bflb_irq_attach(28, sec_eng_isr, NULL);
+ bflb_irq_enable(25);
+ bflb_irq_enable(26);
+ bflb_irq_enable(27);
+ bflb_irq_enable(28);
+#endif
+ bflb_sec_int_mask(sec_type, false);
+}
+
+void bflb_sec_irq_detach(uint8_t sec_type)
+{
+ sec_eng_callback[sec_type].handler = NULL;
+ sec_eng_callback[sec_type].arg = NULL;
+ bflb_sec_int_mask(sec_type, true);
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_sha.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_sha.c
new file mode 100644
index 00000000..8fd8f83b
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_sha.c
@@ -0,0 +1,880 @@
+#include "bflb_sec_sha.h"
+#include "hardware/sec_eng_reg.h"
+
+#define PUT_UINT32_BE(n, b, i) \
+ { \
+ (b)[(i)] = (uint8_t)((n) >> 24); \
+ (b)[(i) + 1] = (uint8_t)((n) >> 16); \
+ (b)[(i) + 2] = (uint8_t)((n) >> 8); \
+ (b)[(i) + 3] = (uint8_t)((n)); \
+ }
+#define PUT_UINT32(n, b, i) \
+ { \
+ (b)[(i) + 3] = (uint8_t)((n) >> 24); \
+ (b)[(i) + 2] = (uint8_t)((n) >> 16); \
+ (b)[(i) + 1] = (uint8_t)((n) >> 8); \
+ (b)[(i) + 0] = (uint8_t)((n)); \
+ }
+#define PUT_UINT64_BE(n, b, i) \
+ { \
+ (b)[(i)] = (uint8_t)((n) >> 56); \
+ (b)[(i) + 1] = (uint8_t)((n) >> 48); \
+ (b)[(i) + 2] = (uint8_t)((n) >> 40); \
+ (b)[(i) + 3] = (uint8_t)((n) >> 32); \
+ (b)[(i) + 4] = (uint8_t)((n) >> 24); \
+ (b)[(i) + 5] = (uint8_t)((n) >> 16); \
+ (b)[(i) + 6] = (uint8_t)((n) >> 8); \
+ (b)[(i) + 7] = (uint8_t)((n)); \
+ }
+
+void bflb_sha_init(struct bflb_device_s *dev, uint8_t mode)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_SHA_0_MODE_EXT_MASK;
+ regval &= ~SEC_ENG_SE_SHA_0_MODE_MASK;
+ regval |= (mode << SEC_ENG_SE_SHA_0_MODE_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha1_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ arch_memset(ctx, 0, sizeof(struct bflb_sha1_ctx_s));
+ ctx->sha_padding[0] = 0x80;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_SHA_0_EN;
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha256_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx)
+{
+ return bflb_sha1_start(dev, (struct bflb_sha1_ctx_s *)ctx);
+}
+
+void bflb_sha512_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ arch_memset(ctx, 0, sizeof(struct bflb_sha512_ctx_s));
+ ctx->sha_padding[0] = 0x80;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_SHA_0_EN;
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, const uint8_t *input, uint32_t len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint32_t fill;
+ uint32_t left;
+ uint64_t start_time;
+
+ if (len == 0) {
+ return 0;
+ }
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ if (ctx->sha_feed) {
+ regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+ } else {
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ }
+
+ left = ctx->total[0] & 0x3F;
+ fill = 64 - left;
+
+ ctx->total[0] += len;
+ ctx->total[0] &= 0xFFFFFFFF;
+
+ if (ctx->total[0] < len) {
+ ctx->total[1]++;
+ }
+
+ if (left && len >= fill) {
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+ putreg32((uint32_t)ctx->sha_buf, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+ regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+ regval |= (1 << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ ctx->sha_feed = 1;
+ input += fill;
+ len -= fill;
+ left = 0;
+ }
+
+ fill = len / 64;
+ len = len % 64;
+
+ if (fill > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* SHA need set se_sha_sel to 1 to keep the last sha state */
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ if (ctx->sha_feed) {
+ regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+ } else {
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ }
+ /* Fill data */
+ putreg32((uintptr_t)input, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+ regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+ regval |= (fill << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ input += (fill * 64);
+ ctx->sha_feed = 1;
+ }
+
+ if (len > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Copy left data into temp buffer */
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+ }
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, const uint8_t *input, uint32_t len)
+{
+ return bflb_sha1_update(dev, (struct bflb_sha1_ctx_s *)ctx, input, len);
+}
+
+int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint64_t len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint32_t fill;
+ uint32_t left;
+ uint64_t start_time;
+
+ if (len == 0) {
+ return 0;
+ }
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ if (ctx->sha_feed) {
+ regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+ } else {
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ }
+
+ left = ctx->total[0] & 0x7F;
+ fill = 128 - left;
+
+ ctx->total[0] += (uint64_t)len;
+
+ if (ctx->total[0] < (uint64_t)len) {
+ ctx->total[1]++;
+ }
+
+ if (left && len >= fill) {
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+ putreg32((uint32_t)ctx->sha_buf, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+ regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+ regval |= (1 << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ ctx->sha_feed = 1;
+ input += fill;
+ len -= fill;
+ left = 0;
+ }
+
+ fill = len / 128;
+ len = len % 128;
+
+ if (fill > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* SHA need set se_sha_sel to 1 to keep the last sha state */
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ if (ctx->sha_feed) {
+ regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+ } else {
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ }
+ /* Fill data */
+ putreg32((uintptr_t)input, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+ regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+ regval |= (fill << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ input += (fill * 128);
+ ctx->sha_feed = 1;
+ }
+
+ if (len > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Copy left data into temp buffer */
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+ }
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, uint8_t *output)
+{
+ uint32_t last, padn;
+ uint32_t high, low;
+ uint8_t msgLen[8];
+ uint32_t regval;
+ uint32_t reg_base;
+ uint8_t mode;
+ uint8_t *p = (uint8_t *)output;
+
+ reg_base = dev->reg_base;
+
+ high = (ctx->total[0] >> 29) | (ctx->total[1] << 3);
+ low = (ctx->total[0] << 3);
+
+ PUT_UINT32_BE(high, msgLen, 0);
+ PUT_UINT32_BE(low, msgLen, 4);
+
+ last = ctx->total[0] & 0x3F;
+ padn = (last < 56) ? (56 - last) : (120 - last);
+
+ bflb_sha1_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+ arch_memcpy_fast(ctx->sha_padding, msgLen, 8);
+ bflb_sha1_update(dev, ctx, (uint8_t *)ctx->sha_padding, 8);
+
+ /* Copy SHA value */
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+
+ mode = (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_MODE_MASK) >> SEC_ENG_SE_SHA_0_MODE_SHIFT;
+
+ if ((mode == SHA_MODE_SHA224) || (mode == SHA_MODE_SHA256)) {
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+
+ if (mode == SHA_MODE_SHA256) {
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ }
+ }
+
+ /* Disable SHA engine*/
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ regval &= ~SEC_ENG_SE_SHA_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output)
+{
+ return bflb_sha1_finish(dev, (struct bflb_sha1_ctx_s *)ctx, output);
+}
+
+void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output)
+{
+ uint64_t last, padn;
+ uint64_t high, low;
+ uint8_t msgLen[16];
+ uint8_t mode;
+ uint32_t regval;
+ uint32_t reg_base;
+ uint8_t *p = (uint8_t *)output;
+
+ reg_base = dev->reg_base;
+
+ high = (ctx->total[0] >> 61) | (ctx->total[1] << 3);
+ low = (ctx->total[0] << 3);
+
+ PUT_UINT64_BE(high, msgLen, 0);
+ PUT_UINT64_BE(low, msgLen, 8);
+
+ last = ctx->total[0] & 0x7F;
+ padn = (last < 112) ? (112 - last) : (240 - last);
+
+ bflb_sha512_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+ arch_memcpy_fast(ctx->sha_padding, msgLen, 16);
+ bflb_sha512_update(dev, ctx, (uint8_t *)ctx->sha_padding, 16);
+
+ /* Copy SHA value */
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+
+ mode = (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_MODE_MASK) >> SEC_ENG_SE_SHA_0_MODE_SHIFT;
+
+ if ((mode == SHA_MODE_SHA512) || (mode == SHA_MODE_SHA384) || (mode == SHA_MODE_SHA512T256)) {
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+
+ if ((mode == SHA_MODE_SHA512) || (mode == SHA_MODE_SHA384)) {
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+
+ if (mode == SHA_MODE_SHA512) {
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET);
+ *p++ = (regval & 0xff);
+ *p++ = ((regval >> 8) & 0xff);
+ *p++ = ((regval >> 16) & 0xff);
+ *p++ = ((regval >> 24) & 0xff);
+ }
+ }
+ }
+
+ /* Disable SHA engine*/
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+ regval &= ~SEC_ENG_SE_SHA_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha_link_init(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_SHA_0_EN;
+ regval |= SEC_ENG_SE_SHA_0_LINK_MODE;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha_link_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval &= ~SEC_ENG_SE_SHA_0_EN;
+ regval &= ~SEC_ENG_SE_SHA_0_LINK_MODE;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_link_ctx_s *ctx, struct bflb_sha_link_s *link)
+{
+ arch_memset(ctx, 0, sizeof(struct bflb_sha1_link_ctx_s));
+ ctx->sha_padding[0] = 0x80;
+ ctx->link_addr = (uint32_t)(uintptr_t)link;
+}
+
+void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_link_ctx_s *ctx, struct bflb_sha_link_s *link)
+{
+ return bflb_sha1_link_start(dev, (struct bflb_sha1_link_ctx_s *)ctx, link);
+}
+
+void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_link_ctx_s *ctx, struct bflb_sha_link_s *link)
+{
+ arch_memset(ctx, 0, sizeof(struct bflb_sha512_link_ctx_s));
+ ctx->sha_padding[0] = 0x80;
+ ctx->link_addr = (uint32_t)(uintptr_t)link;
+}
+
+int bflb_sha1_link_update(struct bflb_device_s *dev,
+ struct bflb_sha1_link_ctx_s *ctx,
+ const uint8_t *input,
+ uint32_t len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint32_t fill;
+ uint32_t left;
+ uint64_t start_time;
+
+ if (len == 0) {
+ return 0;
+ }
+
+ reg_base = dev->reg_base;
+
+ /* Set link address */
+ putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+ left = ctx->total[0] & 0x3F;
+ fill = 64 - left;
+
+ ctx->total[0] += len;
+ ctx->total[0] &= 0xFFFFFFFF;
+
+ if (ctx->total[0] < len) {
+ ctx->total[1]++;
+ }
+
+ if (left && len >= fill) {
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+ /* Set data source address */
+ *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
+
+ /* Set data length */
+ *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = 1;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ /* Choose accumulating last hash in the next time */
+ *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+ input += fill;
+ len -= fill;
+ left = 0;
+ }
+
+ fill = len / 64;
+ len = len % 64;
+
+ if (fill > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Fill data */
+ *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)input;
+ *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = fill;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ input += (fill * 64);
+ /* Choose accumulating last hash in the next time */
+ *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+ }
+
+ if (len > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Copy left data into temp buffer */
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+ }
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+int bflb_sha256_link_update(struct bflb_device_s *dev,
+ struct bflb_sha256_link_ctx_s *ctx,
+ const uint8_t *input,
+ uint32_t len)
+{
+ return bflb_sha1_link_update(dev, (struct bflb_sha1_link_ctx_s *)ctx, input, len);
+}
+
+int bflb_sha512_link_update(struct bflb_device_s *dev,
+ struct bflb_sha512_link_ctx_s *ctx,
+ const uint8_t *input,
+ uint64_t len)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint32_t fill;
+ uint32_t left;
+ uint64_t start_time;
+
+ if (len == 0) {
+ return 0;
+ }
+
+ reg_base = dev->reg_base;
+
+ /* Set link address */
+ putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+ left = ctx->total[0] & 0x7F;
+ fill = 128 - left;
+
+ ctx->total[0] += len;
+
+ if (ctx->total[0] < len) {
+ ctx->total[1]++;
+ }
+
+ if (left && len >= fill) {
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+ /* Set data source address */
+ *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
+
+ /* Set data length */
+ *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = 1;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ /* Choose accumulating last hash in the next time */
+ *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+ input += fill;
+ len -= fill;
+ left = 0;
+ }
+
+ fill = len / 128;
+ len = len % 128;
+
+ if (fill > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Fill data */
+ *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)input;
+ *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = fill;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+ regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+ input += (fill * 128);
+ /* Choose accumulating last hash in the next time */
+ *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+ }
+
+ if (len > 0) {
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Copy left data into temp buffer */
+ arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+ }
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+void bflb_sha1_link_finish(struct bflb_device_s *dev,
+ struct bflb_sha1_link_ctx_s *ctx,
+ uint8_t *output)
+{
+ uint32_t last, padn;
+ uint32_t high, low;
+ uint8_t msgLen[8];
+
+ uint32_t reg_base;
+ uint32_t sha_mode = (*(uint32_t *)(uintptr_t)ctx->link_addr) >> 2 & 0x7;
+
+ reg_base = dev->reg_base;
+
+ /* Set link address */
+ putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+ high = (ctx->total[0] >> 29) | (ctx->total[1] << 3);
+ low = (ctx->total[0] << 3);
+
+ PUT_UINT32_BE(high, msgLen, 0);
+ PUT_UINT32_BE(low, msgLen, 4);
+
+ last = ctx->total[0] & 0x3F;
+ padn = (last < 56) ? (56 - last) : (120 - last);
+
+ bflb_sha1_link_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+ bflb_sha1_link_update(dev, ctx, msgLen, 8);
+
+ /* Get result according to SHA mode,result is placed in (link address + offset:8) */
+ switch (sha_mode) {
+ case 0:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 32);
+ break;
+
+ case 1:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 28);
+ break;
+
+ case 2:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 20);
+ break;
+
+ case 3:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 20);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Choose new hash in the next time */
+ *((uint32_t *)(uintptr_t)ctx->link_addr) &= ~0x40;
+}
+
+void bflb_sha256_link_finish(struct bflb_device_s *dev,
+ struct bflb_sha256_link_ctx_s *ctx,
+ uint8_t *output)
+{
+ return bflb_sha1_link_finish(dev, (struct bflb_sha1_link_ctx_s *)ctx, output);
+}
+
+void bflb_sha512_link_finish(struct bflb_device_s *dev,
+ struct bflb_sha512_link_ctx_s *ctx,
+ uint8_t *output)
+{
+ uint64_t last, padn;
+ uint64_t high, low;
+ uint8_t msgLen[16];
+
+ uint32_t reg_base;
+ uint32_t sha_mode = (*(uint32_t *)(uintptr_t)ctx->link_addr) >> 2 & 0x7;
+
+ reg_base = dev->reg_base;
+
+ /* Set link address */
+ putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+ high = (ctx->total[0] >> 61) | (ctx->total[1] << 3);
+ low = (ctx->total[0] << 3);
+
+ PUT_UINT64_BE(high, msgLen, 0);
+ PUT_UINT64_BE(low, msgLen, 8);
+
+ last = ctx->total[0] & 0x7F;
+ padn = (last < 112) ? (112 - last) : (240 - last);
+
+ bflb_sha512_link_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+ bflb_sha512_link_update(dev, ctx, msgLen, 16);
+
+ /* Get result according to SHA mode,result is placed in (link address + offset:8) */
+ switch (sha_mode) {
+ case 4:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 64);
+ break;
+
+ case 5:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 48);
+ break;
+
+ case 6:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 28);
+ break;
+
+ case 7:
+ arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 32);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Choose new hash in the next time */
+ *((uint32_t *)(uintptr_t)ctx->link_addr) &= ~0x40;
+}
+
+void bflb_group0_request_sha_access(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+ if ((regval & 0x03) == 0x03) {
+ putreg32(0x02, reg_base + SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+ if ((regval & 0x03) == 0x01) {
+ }
+ }
+}
+
+void bflb_group0_release_sha_access(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg32(0x06, reg_base + SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET);
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_trng.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_trng.c
new file mode 100644
index 00000000..53584857
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_sec_trng.c
@@ -0,0 +1,172 @@
+#include "bflb_sec_trng.h"
+#include "hardware/sec_eng_reg.h"
+
+#define BFLB_PUT_LE32TOBYTES(p, val) \
+ { \
+ p[0] = val & 0xff; \
+ p[1] = (val >> 8) & 0xff; \
+ p[2] = (val >> 16) & 0xff; \
+ p[3] = (val >> 24) & 0xff; \
+ }
+
+int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32])
+{
+ uint32_t regval;
+ uint32_t reg_base;
+ uint64_t start_time;
+ uint8_t *p = (uint8_t *)data;
+
+ reg_base = dev->reg_base;
+
+ /* enable trng */
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval |= SEC_ENG_SE_TRNG_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ /* busy will be set to 1 after trigger, the gap is 1T */
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET) & SEC_ENG_SE_TRNG_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval |= SEC_ENG_SE_TRNG_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ /* busy will be set to 1 after trigger, the gap is 1T */
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+ __ASM volatile("nop");
+
+ start_time = bflb_mtimer_get_time_ms();
+ while (getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET) & SEC_ENG_SE_TRNG_0_BUSY) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* copy trng value */
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET));
+ p += 4;
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET));
+ p += 4;
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET));
+ p += 4;
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET));
+ p += 4;
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET));
+ p += 4;
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET));
+ p += 4;
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET));
+ p += 4;
+ BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET));
+ p += 4;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval &= ~SEC_ENG_SE_TRNG_0_TRIG_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval |= SEC_ENG_SE_TRNG_0_DOUT_CLR_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval &= ~SEC_ENG_SE_TRNG_0_DOUT_CLR_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ /* disable trng */
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval &= ~SEC_ENG_SE_TRNG_0_EN;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+ regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+ putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+ return 0;
+}
+
+int bflb_trng_readlen(uint8_t *data, uint32_t len)
+{
+ struct bflb_device_s *trng;
+
+ uint8_t tmp_buf[32];
+ uint32_t readlen = 0;
+ uint32_t i = 0, cnt = 0;
+
+ trng = bflb_device_get_by_name("trng");
+
+ while (readlen < len) {
+ if (bflb_trng_read(trng, tmp_buf) != 0) {
+ return -ETIMEDOUT;
+ }
+
+ cnt = len - readlen;
+
+ if (cnt > sizeof(tmp_buf)) {
+ cnt = sizeof(tmp_buf);
+ }
+
+ for (i = 0; i < cnt; i++) {
+ data[readlen + i] = tmp_buf[i];
+ }
+
+ readlen += cnt;
+ }
+
+ return 0;
+}
+
+long random(void)
+{
+ uint32_t data[8];
+ struct bflb_device_s *trng;
+
+ trng = bflb_device_get_by_name("trng");
+ bflb_trng_read(trng, (uint8_t *)data);
+
+ return data[0];
+}
+
+void bflb_group0_request_trng_access(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+ if (((regval >> 4) & 0x03) == 0x03) {
+ putreg32(0x04, reg_base + SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET);
+
+ regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+ if (((regval >> 4) & 0x03) == 0x01) {
+ }
+ }
+}
+
+void bflb_group0_release_trng_access(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg32(0x06, reg_base + SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET);
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_spi.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_spi.c
new file mode 100644
index 00000000..de9da259
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_spi.c
@@ -0,0 +1,587 @@
+#include "bflb_spi.h"
+#include "bflb_clock.h"
+#include "hardware/spi_reg.h"
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define GLB_SPI_MODE_ADDRESS 0x40000080
+#elif defined(BL606P) || defined(BL808) || defined(BL616) || defined(BL628)
+#define GLB_SPI_MODE_ADDRESS 0x20000510
+#endif
+
+void bflb_spi_init(struct bflb_device_s *dev, const struct bflb_spi_config_s *config)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+ uint32_t div;
+
+ /* GLB select master or slave mode */
+ regval = getreg32(GLB_SPI_MODE_ADDRESS);
+ if (config->role == SPI_ROLE_MASTER) {
+ regval |= 1 << 12;
+ } else {
+ regval &= ~(1 << 12);
+ }
+ putreg32(regval, GLB_SPI_MODE_ADDRESS);
+
+ reg_base = dev->reg_base;
+ /* integer frequency segmentation by rounding */
+ div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_SPI, dev->idx) / 2 * 10 / config->freq + 5) / 10;
+ div = (div) ? (div - 1) : 0;
+ div = (div > 0xff) ? 0xff : div;
+
+ regval = 0;
+ regval |= div << SPI_CR_SPI_PRD_D_PH_0_SHIFT;
+ regval |= div << SPI_CR_SPI_PRD_D_PH_1_SHIFT;
+ regval |= div << SPI_CR_SPI_PRD_S_SHIFT;
+ regval |= div << SPI_CR_SPI_PRD_P_SHIFT;
+ putreg32(regval, reg_base + SPI_PRD_0_OFFSET);
+
+ regval = getreg32(reg_base + SPI_PRD_1_OFFSET);
+ regval &= ~SPI_CR_SPI_PRD_I_MASK;
+ regval |= (div) << SPI_CR_SPI_PRD_I_SHIFT;
+ putreg32(regval, reg_base + SPI_PRD_1_OFFSET);
+
+ /* Disable deglitch and disenable continue function */
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ regval &= ~SPI_CR_SPI_DEG_EN;
+ regval &= ~SPI_CR_SPI_DEG_CNT_MASK;
+ regval &= ~SPI_CR_SPI_M_CONT_EN;
+ regval &= ~SPI_CR_SPI_RXD_IGNR_EN;
+
+ /* Byte-inverse and Bit-inverse */
+ if (config->byte_order == SPI_BYTE_LSB) {
+ regval &= ~SPI_CR_SPI_BYTE_INV;
+ } else {
+ regval |= SPI_CR_SPI_BYTE_INV;
+ }
+ if (config->bit_order == SPI_BIT_LSB) {
+ regval |= SPI_CR_SPI_BIT_INV;
+ } else {
+ regval &= ~SPI_CR_SPI_BIT_INV;
+ }
+
+ /* clk phase and polarity cfg */
+ switch (config->mode) {
+ case SPI_MODE0:
+ /* CPOL=0 CHPHA=0 */
+ regval &= ~SPI_CR_SPI_SCLK_POL;
+ regval |= SPI_CR_SPI_SCLK_PH;
+ break;
+ case SPI_MODE1:
+ /* CPOL=0 CHPHA=1 */
+ regval &= ~SPI_CR_SPI_SCLK_POL;
+ regval &= ~SPI_CR_SPI_SCLK_PH;
+ break;
+ case SPI_MODE2:
+ /* CPOL=1 CHPHA=0 */
+ regval |= SPI_CR_SPI_SCLK_POL;
+ regval |= SPI_CR_SPI_SCLK_PH;
+ break;
+ case SPI_MODE3:
+ /* CPOL=1 CHPHA=1 */
+ regval |= SPI_CR_SPI_SCLK_POL;
+ regval &= ~SPI_CR_SPI_SCLK_PH;
+ break;
+ default:
+ break;
+ }
+
+ /* data frame size cfg */
+ regval &= ~SPI_CR_SPI_FRAME_SIZE_MASK;
+ regval |= (config->data_width - 1) << SPI_CR_SPI_FRAME_SIZE_SHIFT;
+
+ /* disable SPI */
+ regval &= ~SPI_CR_SPI_S_EN;
+ regval &= ~SPI_CR_SPI_M_EN;
+
+ putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+
+ /* clear fifo and close dma */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ regval |= SPI_TX_FIFO_CLR;
+ regval |= SPI_RX_FIFO_CLR;
+ regval &= ~SPI_DMA_TX_EN;
+ regval &= ~SPI_DMA_RX_EN;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+ /* fifo threshold cfg */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+ regval &= ~SPI_TX_FIFO_TH_MASK;
+ regval &= ~SPI_RX_FIFO_TH_MASK;
+ regval |= (config->tx_fifo_threshold << SPI_TX_FIFO_TH_SHIFT) & SPI_TX_FIFO_TH_MASK;
+ regval |= (config->rx_fifo_threshold << SPI_RX_FIFO_TH_SHIFT) & SPI_RX_FIFO_TH_MASK;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+
+ /* enable spi */
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ if (config->role == SPI_ROLE_MASTER) {
+ regval |= SPI_CR_SPI_M_EN;
+ regval &= ~SPI_CR_SPI_S_EN;
+ } else {
+ regval |= SPI_CR_SPI_S_EN;
+ regval &= ~SPI_CR_SPI_M_EN;
+ }
+ putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+}
+
+void bflb_spi_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ /* disable SPI */
+ regval = getreg32(dev->reg_base + SPI_CONFIG_OFFSET);
+ regval &= ~SPI_CR_SPI_S_EN;
+ regval &= ~SPI_CR_SPI_M_EN;
+ putreg32(regval, dev->reg_base + SPI_CONFIG_OFFSET);
+}
+
+void bflb_spi_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= SPI_DMA_TX_EN;
+ } else {
+ regval &= ~SPI_DMA_TX_EN;
+ }
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_spi_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= SPI_DMA_RX_EN;
+ } else {
+ regval &= ~SPI_DMA_RX_EN;
+ }
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+}
+
+/* Read and write a frame of data */
+ATTR_TCM_SECTION uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t data)
+{
+ uint32_t reg_base = dev->reg_base;
+ uint32_t regval;
+ uint8_t fifo_cnt;
+
+#if 0
+ /* Wait for tx FIFO to be empty */
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+ do {
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+ fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+ } while (fifo_cnt < SPI_FIFO_BYTE_NUM_MAX);
+#else
+ do {
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+ fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+ } while (fifo_cnt < SPI_FIFO_WORD_NUM_MAX);
+#endif
+
+ /* Wait for SPI to idle */
+ do {
+ regval = getreg32(reg_base + SPI_BUS_BUSY_OFFSET);
+ } while (regval);
+
+ /* clear fifo */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ regval |= SPI_TX_FIFO_CLR;
+ regval |= SPI_RX_FIFO_CLR;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+#endif
+
+ /* wtire data to fifo */
+ putreg32(data, reg_base + SPI_FIFO_WDATA_OFFSET);
+
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+
+ /* get frame size */
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ uint8_t frame_size = ((regval & SPI_CR_SPI_FRAME_SIZE_MASK) >> SPI_CR_SPI_FRAME_SIZE_SHIFT) + 1;
+ if (frame_size == 3) {
+ frame_size = 4;
+ }
+
+ /* Wait for rx data */
+ do {
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+ fifo_cnt = (regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT;
+ } while (fifo_cnt < frame_size);
+#else
+
+ /* Wait for rx data */
+ do {
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+ fifo_cnt = (regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT;
+ } while (fifo_cnt == 0);
+#endif
+
+ regval = getreg32(reg_base + SPI_FIFO_RDATA_OFFSET);
+
+ return regval;
+}
+
+/* read and write data */
+ATTR_TCM_SECTION int bflb_spi_poll_exchange(struct bflb_device_s *dev, const void *txbuffer, void *rxbuffer, size_t nbytes)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+ uint32_t tx_cnt;
+ uint8_t fifo_cnt, frame_size;
+
+ /* get frame size */
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ frame_size = ((regval & SPI_CR_SPI_FRAME_SIZE_MASK) >> SPI_CR_SPI_FRAME_SIZE_SHIFT) + 1;
+ if (frame_size == 3) {
+ frame_size = 4;
+ }
+
+ nbytes /= frame_size;
+ tx_cnt = nbytes;
+
+#if 0
+ /* Wait for tx FIFO to be empty */
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+ do {
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+ fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+ } while (fifo_cnt < SPI_FIFO_BYTE_NUM_MAX);
+#else
+ do {
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+ fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+ } while (fifo_cnt < SPI_FIFO_WORD_NUM_MAX);
+#endif
+
+ /* Wait for SPI to idle */
+ do {
+ regval = getreg32(reg_base + SPI_BUS_BUSY_OFFSET);
+ } while (regval);
+
+ /* clear fifo */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ regval |= SPI_TX_FIFO_CLR;
+ regval |= SPI_RX_FIFO_CLR;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+#endif
+
+ /* clear fifo */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ regval |= SPI_TX_FIFO_CLR;
+ regval |= SPI_RX_FIFO_CLR;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+ /* get tx fifo cnt */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+ fifo_cnt = ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT) / frame_size;
+#else
+ fifo_cnt = ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT);
+#endif
+
+ /* first fill tx fifo */
+ fifo_cnt = fifo_cnt > nbytes ? nbytes : fifo_cnt;
+ tx_cnt -= fifo_cnt;
+ if (txbuffer != NULL) {
+ /* Send valid data */
+ for (; fifo_cnt > 0; fifo_cnt--) {
+ switch (frame_size) {
+ case 1:
+ regval = *(uint8_t *)txbuffer;
+ putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+ txbuffer += 1;
+ break;
+ case 2:
+ regval = *(uint16_t *)txbuffer;
+ putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+ txbuffer += 2;
+ break;
+ case 3:
+ case 4:
+ regval = *(uint32_t *)txbuffer;
+ putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+ txbuffer += 4;
+ break;
+ default:
+ break;
+ }
+ }
+ } else {
+ /* Send idle Data */
+ for (; fifo_cnt > 0; fifo_cnt--) {
+ putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+ }
+ }
+
+ /* read and write rest of the data */
+ for (; nbytes > 0;) {
+ /* get rx fifo cnt */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+ fifo_cnt = ((regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT) / frame_size;
+#else
+ fifo_cnt = ((regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT);
+#endif
+ if (fifo_cnt) {
+ fifo_cnt = fifo_cnt > nbytes ? nbytes : fifo_cnt;
+ nbytes -= fifo_cnt;
+ } else {
+ }
+
+ /* read and write data */
+ for (; fifo_cnt > 0; fifo_cnt--) {
+ regval = getreg32(reg_base + SPI_FIFO_RDATA_OFFSET);
+ switch (frame_size) {
+ case 1:
+ if (rxbuffer) {
+ *((uint8_t *)rxbuffer) = (uint8_t)regval;
+ rxbuffer += 1;
+ }
+ if (tx_cnt) {
+ if (txbuffer) {
+ regval = *(uint8_t *)txbuffer;
+ putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+ txbuffer++;
+ } else {
+ putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+ }
+ tx_cnt--;
+ }
+ break;
+ case 2:
+ if (rxbuffer) {
+ *((uint16_t *)rxbuffer) = (uint16_t)regval;
+ rxbuffer += 2;
+ }
+ if (tx_cnt) {
+ if (txbuffer) {
+ regval = *(uint16_t *)txbuffer;
+ putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+ txbuffer += 2;
+ } else {
+ putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+ }
+ tx_cnt--;
+ }
+ break;
+ case 3:
+ /* discard the high 8 bits of data when 24bit-frame */
+ case 4:
+ if (rxbuffer) {
+ *((uint32_t *)rxbuffer) = (uint32_t)regval;
+ rxbuffer += 4;
+ }
+ if (tx_cnt) {
+ if (txbuffer) {
+ regval = *(uint32_t *)txbuffer;
+ putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+ txbuffer += 4;
+ } else {
+ putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+ }
+ tx_cnt--;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ return 0;
+}
+
+void bflb_spi_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+ if (mask) {
+ regval |= SPI_CR_SPI_TXF_MASK;
+ } else {
+ regval &= ~SPI_CR_SPI_TXF_MASK;
+ }
+ putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+ if (mask) {
+ regval |= SPI_CR_SPI_RXF_MASK;
+ } else {
+ regval &= ~SPI_CR_SPI_RXF_MASK;
+ }
+ putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+void bflb_spi_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+ if (mask) {
+ regval |= SPI_CR_SPI_END_MASK;
+ } else {
+ regval &= ~SPI_CR_SPI_END_MASK;
+ }
+ putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+ if (mask) {
+ regval |= SPI_CR_SPI_STO_MASK;
+ regval |= SPI_CR_SPI_TXU_MASK;
+ regval |= SPI_CR_SPI_FER_MASK;
+ } else {
+ regval &= ~SPI_CR_SPI_STO_MASK;
+ regval &= ~SPI_CR_SPI_TXU_MASK;
+ regval &= ~SPI_CR_SPI_FER_MASK;
+ }
+ putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+uint32_t bflb_spi_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t int_status;
+ uint32_t int_mask;
+
+ reg_base = dev->reg_base;
+ int_status = getreg32(reg_base + SPI_INT_STS_OFFSET) & 0x1f;
+ int_mask = getreg32(reg_base + SPI_INT_STS_OFFSET) >> 8 & 0x1f;
+ return (int_status & ~int_mask);
+}
+
+void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+ regval |= int_clear;
+ putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+bool bflb_spi_isbusy(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ /* check tx fifo */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+ if ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT < SPI_FIFO_BYTE_NUM_MAX) {
+ return true;
+ }
+#else
+ if ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT < SPI_FIFO_WORD_NUM_MAX) {
+ return true;
+ }
+#endif
+
+ /* check busy bit */
+ regval = getreg32(reg_base + SPI_BUS_BUSY_OFFSET);
+ if (regval) {
+ return true;
+ }
+
+ return false;
+}
+
+int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case SPI_CMD_SET_DATA_WIDTH:
+ /* set data width, arg use @ref SPI_DATA_WIDTH, must clear fifo */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ regval |= SPI_TX_FIFO_CLR;
+ regval |= SPI_RX_FIFO_CLR;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ regval &= ~SPI_CR_SPI_FRAME_SIZE_MASK;
+ regval |= (arg - 1) << SPI_CR_SPI_FRAME_SIZE_SHIFT;
+ putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+ break;
+
+ case SPI_CMD_GET_DATA_WIDTH:
+ /* set data width, arg use @ref SPI_DATA_WIDTH */
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ regval &= SPI_CR_SPI_FRAME_SIZE_MASK;
+ regval >>= SPI_CR_SPI_FRAME_SIZE_SHIFT;
+ *(uint32_t *)arg = regval;
+ break;
+
+ case SPI_CMD_CLEAR_TX_FIFO:
+ /* clear tx fifo */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ regval |= SPI_TX_FIFO_CLR;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case SPI_CMD_CLEAR_RX_FIFO:
+ /* clear rx fifo */
+ regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ regval |= SPI_RX_FIFO_CLR;
+ putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case SPI_CMD_SET_CS_INTERVAL:
+ /* set CS continue mode, arg use true or false */
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ if (arg) {
+ regval |= SPI_CR_SPI_M_CONT_EN;
+ } else {
+ regval &= ~SPI_CR_SPI_M_CONT_EN;
+ }
+ putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+ break;
+
+ case SPI_CMD_RX_IGNORE:
+ /* set rx ignore, start: arg[20:16], stop: arg[4:0] */
+ regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+ if (arg) {
+ regval |= SPI_CR_SPI_RXD_IGNR_EN;
+ putreg32(arg, reg_base + SPI_RXD_IGNR_OFFSET);
+ } else {
+ regval &= ~SPI_CR_SPI_RXD_IGNR_EN;
+ }
+ putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+ break;
+
+ default:
+ ret = -EPERM;
+ break;
+ }
+
+ return ret;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_spi_psram.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_spi_psram.c
new file mode 100644
index 00000000..566663ae
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_spi_psram.c
@@ -0,0 +1,774 @@
+/**
+ ******************************************************************************
+ * @file bflb_spi_psram.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bflb_spi_psram.h"
+#include "bflb_l1c.h"
+
+/** @addtogroup BFLB_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup PSRAM
+ * @{
+ */
+
+/** @defgroup PSRAM_Private_Macros
+ * @{
+ */
+
+/*@} end of group PSRAM_Private_Macros */
+
+/** @defgroup PSRAM_Private_Types
+ * @{
+ */
+
+/*@} end of group PSRAM_Private_Types */
+
+/** @defgroup PSRAM_Private_Variables
+ * @{
+ */
+
+/*@} end of group PSRAM_Private_Variables */
+
+/** @defgroup PSRAM_Global_Variables
+ * @{
+ */
+
+/*@} end of group PSRAM_Global_Variables */
+
+/** @defgroup PSRAM_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group PSRAM_Private_Fun_Declaration */
+
+/** @defgroup PSRAM_Private_Functions
+ * @{
+ */
+
+/*@} end of group PSRAM_Private_Functions */
+
+/** @defgroup PSRAM_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Init serial psram control interface
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param cmds_cfg: Serial Serial Flash controller configuration pointer
+ * @param sf_ctrl_psram_cfg: Serial psram controller configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg,
+ struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg)
+{
+ bflb_sf_ctrl_psram_init(sf_ctrl_psram_cfg);
+ bflb_sf_ctrl_cmds_set(cmds_cfg, 0);
+
+#if defined(BL702L)
+ bflb_sf_ctrl_burst_toggle_set(psram_cfg->burst_toggle_en, psram_cfg->ctrl_mode);
+#endif
+ bflb_psram_setdrivestrength(psram_cfg);
+ bflb_psram_setburstwrap(psram_cfg);
+}
+
+/****************************************************************************/ /**
+ * @brief Read psram register
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param reg_value: Register value pointer to store data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
+{
+ uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+ psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ }
+
+ psram_cmd.cmd_buf[0] = (psram_cfg->read_reg_cmd) << 24;
+ psram_cmd.rw_flag = SF_CTRL_READ;
+ psram_cmd.addr_size = 3;
+ psram_cmd.dummy_clks = psram_cfg->read_reg_dmy_clk;
+ psram_cmd.nb_data = 1;
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return;
+ }
+ }
+
+ arch_memcpy(reg_value, psram_ctrl_buf, 1);
+}
+
+/****************************************************************************/ /**
+ * @brief Write psram register
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param reg_value: Register value pointer storing data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
+{
+ uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ arch_memcpy(psram_ctrl_buf, reg_value, 1);
+
+ if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+ psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ }
+
+ psram_cmd.cmd_buf[0] = (psram_cfg->write_reg_cmd) << 24;
+ psram_cmd.rw_flag = SF_CTRL_WRITE;
+ psram_cmd.addr_size = 3;
+ psram_cmd.nb_data = 1;
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief Set psram driver strength
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg)
+{
+ uint32_t stat = 0;
+
+ bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+ if ((stat & 0x3) == psram_cfg->drive_strength) {
+ return 0;
+ }
+
+ stat &= (~0x3);
+ stat |= psram_cfg->drive_strength;
+
+ bflb_psram_writereg(psram_cfg, (uint8_t *)&stat);
+ /* Wait for write done */
+
+ bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+ if ((stat & 0x3) == psram_cfg->drive_strength) {
+ return 0;
+ }
+
+ return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief Set psram burst wrap size
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg)
+{
+ uint32_t stat = 0;
+
+ bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+ if (((stat >> 5) & 0x3) == psram_cfg->burst_length) {
+ return 0;
+ }
+
+ stat &= (~(0x3 << 5));
+ stat |= (psram_cfg->burst_length << 5);
+
+ bflb_psram_writereg(psram_cfg, (uint8_t *)&stat);
+ /* Wait for write done */
+
+ bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+ if (((stat >> 5) & 0x3) == psram_cfg->burst_length) {
+ return 0;
+ }
+
+ return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief Get psram ID
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param data: Data pointer to store read data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data)
+{
+ uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ psram_cmd.cmd_buf[0] = (psram_cfg->read_id_cmd) << 24;
+ psram_cmd.rw_flag = SF_CTRL_READ;
+ psram_cmd.addr_size = 3;
+ psram_cmd.dummy_clks = psram_cfg->read_id_dmy_clk;
+ psram_cmd.nb_data = 8;
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return;
+ }
+ }
+
+ arch_memcpy(data, psram_ctrl_buf, 8);
+}
+
+/****************************************************************************/ /**
+ * @brief Psram enter quad mode
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg)
+{
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+ uint32_t timeout = 0;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ psram_cmd.cmd_buf[0] = (psram_cfg->enter_quad_mode_cmd) << 24;
+ psram_cmd.rw_flag = SF_CTRL_READ;
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Psram exit quad mode
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg)
+{
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+ uint32_t timeout = 0;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+
+ psram_cmd.cmd_buf[0] = (psram_cfg->exit_quad_mode_cmd) << 24;
+ psram_cmd.rw_flag = SF_CTRL_READ;
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Psram toggle burst length
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param ctrl_mode: Psram ctrl mode type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
+{
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+ uint32_t timeout = 0;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ if (ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+ psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ }
+
+ psram_cmd.cmd_buf[0] = (psram_cfg->burst_toggle_cmd) << 24;
+ psram_cmd.rw_flag = SF_CTRL_READ;
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Psram software reset
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param ctrl_mode: Psram ctrl mode type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
+{
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+ uint32_t timeout = 0;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ if (ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+ psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ }
+
+ /* Reset enable */
+ psram_cmd.cmd_buf[0] = (psram_cfg->reset_enable_cmd) << 24;
+ /* rw_flag don't care */
+ psram_cmd.rw_flag = SF_CTRL_READ;
+ /* Wait for write done */
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ /* Reset */
+ psram_cmd.cmd_buf[0] = (psram_cfg->reset_cmd) << 24;
+ /* rw_flag don't care */
+ psram_cmd.rw_flag = SF_CTRL_READ;
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ arch_delay_us(50);
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Psram set IDbus config
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param io_mode: Psram ctrl mode type
+ * @param addr: Address to read/write
+ * @param len: Data length to read/write
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg,
+ uint8_t io_mode, uint32_t addr, uint32_t len)
+{
+ uint8_t cmd, dummy_clks;
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+ uint8_t cmd_valid = 1;
+
+ bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB);
+
+ /* read mode cache set */
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ if (SF_CTRL_NIO_MODE == io_mode) {
+ cmd = psram_cfg->f_read_cmd;
+ dummy_clks = psram_cfg->f_read_dmy_clk;
+ } else if (SF_CTRL_QIO_MODE == io_mode) {
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = psram_cfg->f_read_quad_cmd;
+ dummy_clks = psram_cfg->f_read_quad_dmy_clk;
+ } else {
+ return -1;
+ }
+
+ /* prepare command */
+ psram_cmd.rw_flag = SF_CTRL_READ;
+ psram_cmd.addr_size = 3;
+ psram_cmd.cmd_buf[0] = (cmd << 24) | addr;
+ psram_cmd.dummy_clks = dummy_clks;
+ psram_cmd.nb_data = len;
+ bflb_sf_ctrl_psram_read_set(&psram_cmd, cmd_valid);
+
+ /* write mode cache set */
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ if (SF_CTRL_NIO_MODE == io_mode) {
+ cmd = psram_cfg->write_cmd;
+ } else if (SF_CTRL_QIO_MODE == io_mode) {
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = psram_cfg->quad_write_cmd;
+ } else {
+ return -1;
+ }
+
+ dummy_clks = 0;
+
+ /* prepare command */
+ psram_cmd.rw_flag = SF_CTRL_WRITE;
+ psram_cmd.addr_size = 3;
+ psram_cmd.cmd_buf[0] = (cmd << 24) | addr;
+ psram_cmd.dummy_clks = dummy_clks;
+ psram_cmd.nb_data = len;
+ bflb_sf_ctrl_psram_write_set(&psram_cmd, cmd_valid);
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Set cache write to psram with cache
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param io_mode: Psram controller interface mode
+ * @param wt_en: Psram cache write through enable
+ * @param wb_en: Psram cache write back enable
+ * @param wa_en: Psram cache write allocate enable
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
+ uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
+{
+ int stat = -1;
+
+ /* Cache now only support 32 bytes read */
+ stat = bflb_psram_set_idbus_cfg(psram_cfg, io_mode, 0, 32);
+
+ if (0 != stat) {
+ return stat;
+ }
+
+ bflb_l1c_cache_write_set(wt_en, wb_en, wa_en);
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Write psram one region
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param io_mode: Write mode: SPI mode or QPI mode
+ * @param addr: Start address to be write
+ * @param data: Data pointer to be write
+ * @param len: Data length to be write
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
+ uint32_t addr, uint8_t *data, uint32_t len)
+{
+ uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+ uint32_t i = 0, cur_len = 0;
+ uint32_t burst_len = 512;
+ uint8_t cmd;
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ if (SF_CTRL_NIO_MODE == io_mode) {
+ cmd = psram_cfg->write_cmd;
+ } else if (SF_CTRL_QIO_MODE == io_mode) {
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = psram_cfg->quad_write_cmd;
+ } else {
+ return -1;
+ }
+
+ /* Prepare command */
+ psram_cmd.rw_flag = SF_CTRL_WRITE;
+ psram_cmd.addr_size = 3;
+
+ if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) {
+ burst_len = 16;
+ } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) {
+ burst_len = 32;
+ } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) {
+ burst_len = 64;
+ } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) {
+ burst_len = 512;
+ }
+
+ for (i = 0; i < len;) {
+ /* Get current programmed length within page size */
+ cur_len = burst_len - addr % burst_len;
+
+ if (cur_len > len - i) {
+ cur_len = len - i;
+ }
+
+ /* Prepare command */
+ arch_memcpy_fast(psram_ctrl_buf, data, cur_len);
+ psram_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+ psram_cmd.nb_data = cur_len;
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ /* Adjust address and programmed length */
+ addr += cur_len;
+ i += cur_len;
+ data += cur_len;
+
+ /* Wait for write done */
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Read data from psram
+ *
+ * @param psram_cfg: Serial psram parameter configuration pointer
+ * @param io_mode: IoMode: psram controller interface mode
+ * @param addr: Psram read start address
+ * @param data: Data pointer to store data read from psram
+ * @param len: Data length to read
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
+ uint32_t addr, uint8_t *data, uint32_t len)
+{
+ uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+ uint32_t cur_len, i;
+ uint32_t burst_len = 512;
+ uint32_t timeout = 0;
+ uint8_t cmd, dummy_clks;
+ struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+ if (((uint32_t)&psram_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+ } else {
+ arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+ }
+
+ if (SF_CTRL_NIO_MODE == io_mode) {
+ cmd = psram_cfg->f_read_cmd;
+ dummy_clks = psram_cfg->f_read_dmy_clk;
+ } else if (SF_CTRL_QIO_MODE == io_mode) {
+ psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = psram_cfg->f_read_quad_cmd;
+ dummy_clks = psram_cfg->f_read_quad_dmy_clk;
+ } else {
+ return -1;
+ }
+
+ /* Prepare command */
+ psram_cmd.rw_flag = SF_CTRL_READ;
+ psram_cmd.addr_size = 3;
+ psram_cmd.dummy_clks = dummy_clks;
+
+ if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) {
+ burst_len = 16;
+ } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) {
+ burst_len = 32;
+ } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) {
+ burst_len = 64;
+ } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) {
+ burst_len = 512;
+ }
+
+ /* Read data */
+ for (i = 0; i < len;) {
+ /* Prepare command */
+ psram_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+ cur_len = burst_len - addr % burst_len;
+
+ if (cur_len > len - i) {
+ cur_len = len - i;
+ }
+
+ if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
+ cur_len = NOR_FLASH_CTRL_BUF_SIZE;
+ psram_cmd.nb_data = cur_len;
+ } else {
+ /* Make sf_ctrl word read */
+ psram_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
+ }
+
+ bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ arch_memcpy_fast(data, psram_ctrl_buf, cur_len);
+
+ addr += cur_len;
+ i += cur_len;
+ data += cur_len;
+ }
+
+ return 0;
+}
+
+/*@} end of group PSRAM_Public_Functions */
+
+/*@} end of group PSRAM */
+
+/*@} end of group BFLB_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_timer.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_timer.c
new file mode 100644
index 00000000..7e93a146
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_timer.c
@@ -0,0 +1,292 @@
+#include "bflb_timer.h"
+#include "bflb_gpio.h"
+#include "hardware/timer_reg.h"
+
+void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s *config)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ /* Disable timer */
+ regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+ regval &= ~(1 << (dev->idx + 1));
+ putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+
+ /* Timer interrupr clear */
+ bflb_timer_compint_clear(dev, TIMER_COMP_ID_0);
+ bflb_timer_compint_clear(dev, TIMER_COMP_ID_1);
+ bflb_timer_compint_clear(dev, TIMER_COMP_ID_2);
+
+ /* Configure clock source */
+ regval = getreg32(reg_base + TIMER_TCCR_OFFSET);
+ if (dev->idx == 0) {
+ regval &= ~TIMER_CS_0_MASK;
+ regval |= (config->clock_source << TIMER_CS_0_SHIFT);
+ } else {
+ regval &= ~TIMER_CS_1_MASK;
+ regval |= (config->clock_source << TIMER_CS_1_SHIFT);
+ }
+ putreg32(regval, reg_base + TIMER_TCCR_OFFSET);
+
+ /* Configure clock div */
+ regval = getreg32(reg_base + TIMER_TCDR_OFFSET);
+ regval &= ~(0xff << (TIMER_TCDR0_SHIFT + 8 * dev->idx));
+ regval |= (config->clock_div << (TIMER_TCDR0_SHIFT + 8 * dev->idx));
+ putreg32(regval, reg_base + TIMER_TCDR_OFFSET);
+
+ /* Configure counter mode */
+ regval = getreg32(reg_base + TIMER_TCMR_OFFSET);
+ if (config->counter_mode == TIMER_COUNTER_MODE_PROLOAD) {
+ regval &= ~(1 << (1 + dev->idx));
+ } else {
+ regval |= (1 << (1 + dev->idx));
+ }
+ putreg32(regval, reg_base + TIMER_TCMR_OFFSET);
+
+ /* Configure preload trigger source */
+ regval = getreg32(reg_base + TIMER_TPLCR0_OFFSET + 4 * dev->idx);
+ regval &= ~TIMER_TPLCR0_MASK;
+ if (config->trigger_comp_id != TIMER_COMP_NONE) {
+ regval |= ((config->trigger_comp_id + 1) << TIMER_TPLCR0_SHIFT);
+ }
+ putreg32(regval, reg_base + TIMER_TPLCR0_OFFSET + 4 * dev->idx);
+
+ if (config->counter_mode == TIMER_COUNTER_MODE_PROLOAD) {
+ bflb_timer_set_preloadvalue(dev, config->preload_val);
+ }
+
+ if (config->trigger_comp_id < TIMER_COMP_ID_1) {
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, false);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, true);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, true);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, 0xffffffff);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff);
+ } else if (config->trigger_comp_id < TIMER_COMP_ID_2) {
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, false);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, false);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, true);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, config->comp1_val - 2);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff);
+ } else if (config->trigger_comp_id < TIMER_COMP_NONE) {
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, false);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, false);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, false);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, config->comp1_val - 2);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, config->comp2_val - 2);
+ } else {
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, true);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, true);
+ bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, true);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, 0xffffffff);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, 0xffffffff);
+ bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff);
+ }
+}
+
+void bflb_timer_deinit(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+ regval &= ~(1 << (dev->idx + 1));
+ putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+}
+
+void bflb_timer_start(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+ regval |= (1 << (dev->idx + 1));
+ putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+}
+
+void bflb_timer_stop(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+ regval &= ~(1 << (dev->idx + 1));
+ putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+}
+
+void bflb_timer_set_preloadvalue(struct bflb_device_s *dev, uint32_t val)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg32(val, reg_base + TIMER_TPLVR0_OFFSET + 4 * dev->idx);
+}
+
+void bflb_timer_set_compvalue(struct bflb_device_s *dev, uint8_t cmp_no, uint32_t val)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg32(val, reg_base + TIMER_TMR0_0_OFFSET + 0x0c * dev->idx + 4 * cmp_no);
+}
+
+uint32_t bflb_timer_get_compvalue(struct bflb_device_s *dev, uint8_t cmp_no)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ return getreg32(reg_base + TIMER_TMR0_0_OFFSET + 0x0c * dev->idx + 4 * cmp_no);
+}
+
+uint32_t bflb_timer_get_countervalue(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ return getreg32(reg_base + TIMER_TCR0_OFFSET + 4 * dev->idx);
+}
+
+void bflb_timer_compint_mask(struct bflb_device_s *dev, uint8_t cmp_no, bool mask)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + TIMER_TIER0_OFFSET + 4 * dev->idx);
+ if (mask) {
+ regval &= ~(1 << cmp_no);
+ } else {
+ regval |= (1 << cmp_no);
+ }
+ putreg32(regval, reg_base + TIMER_TIER0_OFFSET + 4 * dev->idx);
+}
+
+bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + TIMER_TSR0_OFFSET + 4 * dev->idx);
+
+ if (regval & (1 << cmp_no)) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx);
+ regval |= (1 << cmp_no);
+ putreg32(regval, reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx);
+}
+
+#if !defined(BL702) && !defined(BL602)
+void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+#if defined(BL702L)
+ regval = getreg32(0x20000000 + 0xc);
+ regval &= ~(0x3 << 14);
+ switch (config->pin & 0x03) {
+ case 0:
+ regval &= ~(1 << 10);
+ regval |= (0 << 14);
+ break;
+ case 1:
+ regval &= ~(1 << 11);
+ regval |= (1 << 14);
+ break;
+ case 2:
+ regval &= ~(1 << 12);
+ regval |= (2 << 14);
+ break;
+ case 3:
+ regval &= ~(1 << 13);
+ regval |= (3 << 14);
+ break;
+
+ default:
+ break;
+ }
+ putreg32(regval, 0x20000000 + 0xc);
+ struct bflb_device_s *gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, config->pin, (0 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1);
+#else
+ regval = getreg32(0x20000000 + 0x258);
+ regval &= ~(3 << 12);
+ switch (config->pin & 0x03) {
+ case 0:
+ regval &= ~(1 << 8);
+ regval |= (0 << 12);
+ break;
+ case 1:
+ regval &= ~(1 << 9);
+ regval |= (1 << 12);
+ break;
+ case 2:
+ regval &= ~(1 << 10);
+ regval |= (2 << 12);
+ break;
+ case 3:
+ regval &= ~(1 << 11);
+ regval |= (3 << 12);
+ break;
+
+ default:
+ break;
+ }
+ putreg32(regval, 0x20000000 + 0x258);
+ struct bflb_device_s *gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, config->pin, (31 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1);
+#endif
+
+ regval = getreg32(reg_base + TIMER_GPIO_OFFSET);
+ /* polarity: 1->neg, 0->pos */
+ if (config->polarity == TIMER_CAPTURE_POLARITY_NEGATIVE) {
+ regval |= (1 << (5 + dev->idx));
+ } else {
+ regval &= ~(1 << (5 + dev->idx));
+ }
+ regval |= TIMER0_GPIO_EN;
+ putreg32(regval, reg_base + TIMER_GPIO_OFFSET);
+}
+
+uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t lat1 = 0;
+ uint32_t lat2 = 0;
+ reg_base = dev->reg_base;
+
+ do {
+ lat1 = getreg32(reg_base + TIMER_GPIO_LAT1_OFFSET);
+ lat2 = getreg32(reg_base + TIMER_GPIO_LAT2_OFFSET);
+ } while (!(getreg32(reg_base + TIMER_GPIO_OFFSET) & TIMER_GPIO_LAT_OK) || (lat1 >= lat2));
+
+ return (lat2 - lat1);
+}
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_uart.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_uart.c
new file mode 100644
index 00000000..acd93c1e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_uart.c
@@ -0,0 +1,719 @@
+#include "bflb_uart.h"
+#include "bflb_clock.h"
+#include "hardware/uart_reg.h"
+
+void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *config)
+{
+ uint32_t div = 0;
+ uint32_t tx_cfg;
+ uint32_t rx_cfg;
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ /* Cal the baud rate divisor */
+ div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_UART, dev->idx) * 10 / config->baudrate + 5) / 10;
+
+ tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ tx_cfg &= ~UART_CR_UTX_EN;
+ rx_cfg &= ~UART_CR_URX_EN;
+ putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+
+ putreg32(((div - 1) << 0x10) | ((div - 1) & 0xFFFF), reg_base + UART_BIT_PRD_OFFSET);
+
+ /* configure parity type */
+
+ tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+ switch (config->parity) {
+ case UART_PARITY_NONE:
+ tx_cfg &= ~UART_CR_UTX_PRT_EN;
+ rx_cfg &= ~UART_CR_URX_PRT_EN;
+ break;
+ case UART_PARITY_ODD:
+ tx_cfg |= UART_CR_UTX_PRT_EN;
+ tx_cfg |= UART_CR_UTX_PRT_SEL;
+ rx_cfg |= UART_CR_URX_PRT_EN;
+ rx_cfg |= UART_CR_URX_PRT_SEL;
+ break;
+ case UART_PARITY_EVEN:
+ tx_cfg |= UART_CR_UTX_PRT_EN;
+ tx_cfg &= ~UART_CR_UTX_PRT_SEL;
+ rx_cfg |= UART_CR_URX_PRT_EN;
+ rx_cfg &= ~UART_CR_URX_PRT_SEL;
+ break;
+ default:
+ break;
+ }
+
+ /* Configure data bits */
+ tx_cfg &= ~UART_CR_UTX_BIT_CNT_D_MASK;
+ tx_cfg |= (config->data_bits + 4) << UART_CR_UTX_BIT_CNT_D_SHIFT;
+ rx_cfg &= ~UART_CR_URX_BIT_CNT_D_MASK;
+ rx_cfg |= (config->data_bits + 4) << UART_CR_URX_BIT_CNT_D_SHIFT;
+
+ /* Configure tx stop bits */
+ tx_cfg &= ~UART_CR_UTX_BIT_CNT_P_MASK;
+ tx_cfg |= config->stop_bits << UART_CR_UTX_BIT_CNT_P_SHIFT;
+
+ /* Configure tx cts flow control function */
+ if (config->flow_ctrl & UART_FLOWCTRL_CTS) {
+ tx_cfg |= UART_CR_UTX_CTS_EN;
+ } else {
+ tx_cfg &= ~UART_CR_UTX_CTS_EN;
+ }
+
+ rx_cfg &= ~UART_CR_URX_DEG_EN;
+
+ /* Write back */
+ putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+#if defined(BL602)
+ regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ regval &= ~UART_CR_URX_RTS_SW_MODE;
+ putreg32(regval, reg_base + UART_URX_CONFIG_OFFSET);
+
+#else
+ regval = getreg32(reg_base + UART_SW_MODE_OFFSET);
+ regval &= ~UART_CR_URX_RTS_SW_MODE;
+ putreg32(regval, reg_base + UART_SW_MODE_OFFSET);
+#endif
+ regval = getreg32(reg_base + UART_DATA_CONFIG_OFFSET);
+ regval &= ~UART_CR_UART_BIT_INV;
+ putreg32(regval, reg_base + UART_DATA_CONFIG_OFFSET);
+
+ /* Enable tx free run mode */
+ regval = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ regval |= UART_CR_UTX_FRM_EN;
+ putreg32(regval, reg_base + UART_UTX_CONFIG_OFFSET);
+
+ /* Configure FIFO thresholds */
+ regval = getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET);
+ regval &= ~UART_TX_FIFO_TH_MASK;
+ regval &= ~UART_RX_FIFO_TH_MASK;
+ regval |= (config->tx_fifo_threshold << UART_TX_FIFO_TH_SHIFT) & UART_TX_FIFO_TH_MASK;
+ regval |= (config->rx_fifo_threshold << UART_RX_FIFO_TH_SHIFT) & UART_RX_FIFO_TH_MASK;
+ putreg32(regval, reg_base + UART_FIFO_CONFIG_1_OFFSET);
+
+ /* Clear FIFO */
+ regval = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+ regval |= UART_TX_FIFO_CLR;
+ regval |= UART_RX_FIFO_CLR;
+ regval &= ~UART_DMA_TX_EN;
+ regval &= ~UART_DMA_RX_EN;
+ putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+
+ putreg32(0xFFFFFFFF, reg_base + UART_INT_MASK_OFFSET);
+
+ /* Enable UART tx rx unit */
+ tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ tx_cfg |= UART_CR_UTX_EN;
+ rx_cfg |= UART_CR_URX_EN;
+ putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_deinit(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t tx_cfg;
+ uint32_t rx_cfg;
+
+ reg_base = dev->reg_base;
+ tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ tx_cfg &= ~UART_CR_UTX_EN;
+ rx_cfg &= ~UART_CR_URX_EN;
+ putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_enable(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t tx_cfg;
+ uint32_t rx_cfg;
+
+ reg_base = dev->reg_base;
+ tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ tx_cfg |= UART_CR_UTX_EN;
+ rx_cfg |= UART_CR_URX_EN;
+ putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_disable(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t tx_cfg;
+ uint32_t rx_cfg;
+
+ reg_base = dev->reg_base;
+ tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ tx_cfg &= ~UART_CR_UTX_EN;
+ rx_cfg &= ~UART_CR_URX_EN;
+ putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= UART_DMA_TX_EN;
+ } else {
+ regval &= ~UART_DMA_TX_EN;
+ }
+ putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+ uint32_t reg_base;
+ uint32_t regval;
+
+ reg_base = dev->reg_base;
+ regval = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+ if (enable) {
+ regval |= UART_DMA_RX_EN;
+ } else {
+ regval &= ~UART_DMA_RX_EN;
+ }
+ putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+}
+
+ATTR_TCM_SECTION int bflb_uart_putchar(struct bflb_device_s *dev, int ch)
+{
+ uint64_t start_time;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ start_time = bflb_mtimer_get_time_ms();
+ while ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == 0) {
+ if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+ return -ETIMEDOUT;
+ }
+ }
+ putreg8(ch, reg_base + UART_FIFO_WDATA_OFFSET);
+ return 0;
+}
+
+ATTR_TCM_SECTION int bflb_uart_getchar(struct bflb_device_s *dev)
+{
+ int ch = -1;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0) {
+ ch = getreg8(reg_base + UART_FIFO_RDATA_OFFSET);
+ }
+
+ return ch;
+}
+
+ATTR_TCM_SECTION int bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+ int ret;
+ for (uint32_t i = 0; i < len; i++) {
+ ret = bflb_uart_putchar(dev, data[i]);
+ if (ret < 0) {
+ return ret;
+ }
+ }
+ return 0;
+}
+
+ATTR_TCM_SECTION int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+ int ch = -1;
+ uint32_t count = 0;
+
+ while (count < len) {
+ if ((ch = bflb_uart_getchar(dev)) < 0) {
+ break;
+ }
+ data[count] = ch;
+ count++;
+ }
+ return count;
+}
+
+bool bflb_uart_txready(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) != 0) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+bool bflb_uart_txempty(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == (UART_TX_FIFO_CNT_MASK >> 1) + 1) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+bool bflb_uart_rxavailable(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ return ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0);
+}
+
+void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t int_mask;
+
+ reg_base = dev->reg_base;
+ int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ if (mask) {
+ int_mask |= UART_CR_UTX_FIFO_MASK;
+ } else {
+ int_mask &= ~UART_CR_UTX_FIFO_MASK;
+ }
+ putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+}
+
+void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t int_mask;
+
+ reg_base = dev->reg_base;
+ int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ if (mask) {
+ int_mask |= UART_CR_URX_FIFO_MASK;
+ int_mask |= UART_CR_URX_RTO_MASK;
+ } else {
+ int_mask &= ~UART_CR_URX_FIFO_MASK;
+ int_mask &= ~UART_CR_URX_RTO_MASK;
+ }
+ putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+}
+
+void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+ uint32_t reg_base;
+ uint32_t int_mask;
+
+ reg_base = dev->reg_base;
+ int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ if (mask) {
+ int_mask |= UART_CR_URX_PCE_MASK;
+ int_mask |= UART_CR_UTX_FER_MASK;
+ int_mask |= UART_CR_URX_FER_MASK;
+#if !defined(BL602)
+ int_mask |= UART_CR_URX_LSE_MASK;
+#endif
+ } else {
+ int_mask &= ~UART_CR_URX_PCE_MASK;
+ int_mask &= ~UART_CR_UTX_FER_MASK;
+ int_mask &= ~UART_CR_URX_FER_MASK;
+#if !defined(BL602)
+ int_mask &= ~UART_CR_URX_LSE_MASK;
+#endif
+ }
+ putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+}
+
+uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+ uint32_t int_status;
+ uint32_t int_mask;
+
+ reg_base = dev->reg_base;
+ int_status = getreg32(reg_base + UART_INT_STS_OFFSET);
+ int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ return (int_status & ~int_mask);
+}
+
+void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+ putreg32(int_clear, reg_base + UART_INT_CLEAR_OFFSET);
+}
+
+int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+ int ret = 0;
+ uint32_t reg_base;
+ uint32_t tmp;
+ uint32_t tx_tmp;
+ uint32_t rx_tmp;
+ uint32_t int_mask;
+
+ reg_base = dev->reg_base;
+
+ switch (cmd) {
+ case UART_CMD_SET_BAUD_RATE:
+ /* Cal the baud rate divisor */
+ tmp = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_UART, dev->idx) * 10 / arg + 5) / 10;
+
+ putreg32(((tmp - 1) << 0x10) | ((tmp - 1) & 0xFFFF), reg_base + UART_BIT_PRD_OFFSET);
+ break;
+
+ case UART_CMD_SET_DATA_BITS:
+ /* Set data bits */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+ tx_tmp &= ~UART_CR_UTX_BIT_CNT_D_MASK;
+ tx_tmp |= (arg + 4) << UART_CR_UTX_BIT_CNT_D_SHIFT;
+
+ rx_tmp &= ~UART_CR_URX_BIT_CNT_D_MASK;
+ rx_tmp |= (arg + 4) << UART_CR_URX_BIT_CNT_D_SHIFT;
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ break;
+
+ case UART_CMD_SET_STOP_BITS:
+ /* Set stop bits */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+ tx_tmp &= ~UART_CR_UTX_BIT_CNT_P_MASK;
+ tx_tmp |= arg << UART_CR_UTX_BIT_CNT_P_SHIFT;
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ break;
+
+ case UART_CMD_SET_PARITY_BITS:
+ /* Set parity mode */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+ if (arg == UART_PARITY_NONE) {
+ tx_tmp &= ~UART_CR_UTX_PRT_EN;
+ rx_tmp &= ~UART_CR_URX_PRT_EN;
+ } else if (arg == UART_PARITY_ODD) {
+ tx_tmp |= UART_CR_UTX_PRT_EN;
+ tx_tmp |= UART_CR_UTX_PRT_SEL;
+ rx_tmp |= UART_CR_URX_PRT_EN;
+ rx_tmp |= UART_CR_URX_PRT_SEL;
+ } else if (arg == UART_PARITY_EVEN) {
+ tx_tmp |= UART_CR_UTX_PRT_EN;
+ tx_tmp &= ~UART_CR_UTX_PRT_SEL;
+ rx_tmp |= UART_CR_URX_PRT_EN;
+ rx_tmp &= ~UART_CR_URX_PRT_SEL;
+ }
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ break;
+
+ case UART_CMD_CLR_TX_FIFO:
+ /* Clear tx fifo */
+ tmp = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+ tmp |= UART_TX_FIFO_CLR;
+ putreg32(tmp, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case UART_CMD_CLR_RX_FIFO:
+ /* Clear rx fifo */
+ tmp = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+ tmp |= UART_RX_FIFO_CLR;
+ putreg32(tmp, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+ break;
+
+ case UART_CMD_SET_RTO_VALUE:
+ /* Set rx time-out value */
+ putreg32(arg, reg_base + UART_URX_RTO_TIMER_OFFSET);
+ break;
+
+ case UART_CMD_SET_RTS_VALUE:
+#if defined(BL602)
+#else
+ /* Set rx rts output software control value */
+ tmp = getreg32(reg_base + UART_SW_MODE_OFFSET);
+ tmp &= ~UART_CR_URX_RTS_SW_VAL;
+ if (arg) {
+ tmp |= UART_CR_URX_RTS_SW_VAL;
+ }
+ putreg32(tmp, reg_base + UART_SW_MODE_OFFSET);
+#endif
+ break;
+
+ case UART_CMD_GET_TX_FIFO_CNT:
+ /* Get tx fifo count */
+ return (getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) >> UART_TX_FIFO_CNT_SHIFT;
+
+ case UART_CMD_GET_RX_FIFO_CNT:
+ /* Get rx fifo count */
+ return (getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) >> UART_RX_FIFO_CNT_SHIFT;
+
+ case UART_CMD_SET_AUTO_BAUD:
+ /* Set auto baudrate detection */
+ tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ rx_tmp = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ tmp &= ~UART_CR_URX_ABR_EN;
+ if (arg == UART_AUTO_BAUD_0X55) {
+ tmp |= UART_CR_URX_ABR_EN;
+#if !defined(BL602) && !defined(BL702)
+ rx_tmp &= ~UART_CR_URX_AD5_MASK;
+#endif
+ } else {
+ tmp |= UART_CR_URX_ABR_EN;
+#if !defined(BL602) && !defined(BL702)
+ rx_tmp &= ~UART_CR_URX_ADS_MASK;
+#endif
+ }
+
+ putreg32(tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ putreg32(rx_tmp, reg_base + UART_INT_MASK_OFFSET);
+ break;
+
+ case UART_CMD_GET_AUTO_BAUD:
+ /* Get auto baudrate detection count value */
+ tmp = getreg32(reg_base + UART_STS_URX_ABR_PRD_OFFSET);
+ if (arg == UART_AUTO_BAUD_START) {
+ return (tmp & UART_STS_URX_ABR_PRD_START_MASK);
+ } else {
+ return ((tmp & UART_STS_URX_ABR_PRD_0X55_MASK) >> UART_STS_URX_ABR_PRD_0X55_SHIFT);
+ }
+#if !defined(BL602)
+ case UART_CMD_SET_BREAK_VALUE:
+ /* Set lin mode break value */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+ tx_tmp &= ~UART_CR_UTX_BIT_CNT_B_MASK;
+ tx_tmp |= arg << UART_CR_UTX_BIT_CNT_B_SHIFT;
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ break;
+
+ case UART_CMD_SET_TX_LIN_VALUE:
+ /* Set tx lin mode */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ tx_tmp &= ~UART_CR_UTX_LIN_EN;
+ if (arg) {
+ tx_tmp |= UART_CR_UTX_LIN_EN;
+ }
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ break;
+
+ case UART_CMD_SET_RX_LIN_VALUE:
+ /* Set rx lin mode */
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ rx_tmp &= ~UART_CR_URX_LIN_EN;
+ if (arg) {
+ rx_tmp |= UART_CR_URX_LIN_EN;
+ }
+
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ break;
+#endif
+ case UART_CMD_SET_TX_RX_EN:
+ /* Set tx and rx enable */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ tx_tmp &= ~UART_CR_UTX_EN;
+ rx_tmp &= ~UART_CR_URX_EN;
+ if (arg) {
+ tx_tmp |= UART_CR_UTX_EN;
+ rx_tmp |= UART_CR_URX_EN;
+ }
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ break;
+#if !defined(BL602) && !defined(BL702)
+ case UART_CMD_SET_TX_RS485_EN:
+ /* Set tx rs485 transceiver enable */
+ tx_tmp = getreg32(reg_base + UART_UTX_RS485_CFG_OFFSET);
+ tx_tmp &= ~UART_CR_UTX_RS485_EN;
+
+ if (arg) {
+ tx_tmp |= UART_CR_UTX_RS485_EN;
+ }
+
+ putreg32(tx_tmp, reg_base + UART_UTX_RS485_CFG_OFFSET);
+ break;
+
+ case UART_CMD_SET_TX_RS485_POLARITY:
+ /* Set tx rs485 de pin polarity */
+ tx_tmp = getreg32(reg_base + UART_UTX_RS485_CFG_OFFSET);
+ tx_tmp &= ~UART_CR_UTX_RS485_POL;
+
+ if (arg) {
+ tx_tmp |= UART_CR_UTX_RS485_POL;
+ }
+
+ putreg32(tx_tmp, reg_base + UART_UTX_RS485_CFG_OFFSET);
+ break;
+
+ case UART_CMD_SET_ABR_ALLOWABLE_ERROR:
+ /* Set auto baudrate detection mode pulse-width tolerance value for codeword 0x55 */
+ rx_tmp = getreg32(reg_base + UART_URX_ABR_PW_TOL_OFFSET);
+ rx_tmp &= ~UART_CR_URX_ABR_PW_TOL_MASK;
+ rx_tmp |= arg << UART_CR_URX_ABR_PW_TOL_SHIFT;
+
+ putreg32(rx_tmp, reg_base + UART_URX_ABR_PW_TOL_OFFSET);
+ break;
+#endif
+ case UART_CMD_SET_SW_RTS_CONTROL:
+#if defined(BL602)
+ if (arg) {
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ rx_tmp |= UART_CR_URX_RTS_SW_MODE;
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ } else {
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ rx_tmp &= ~UART_CR_URX_RTS_SW_MODE;
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ }
+#else
+ if (arg) {
+ rx_tmp = getreg32(reg_base + UART_SW_MODE_OFFSET);
+ rx_tmp |= UART_CR_URX_RTS_SW_MODE;
+ putreg32(rx_tmp, reg_base + UART_SW_MODE_OFFSET);
+
+ } else {
+ rx_tmp = getreg32(reg_base + UART_SW_MODE_OFFSET);
+ rx_tmp &= ~UART_CR_URX_RTS_SW_MODE;
+ putreg32(rx_tmp, reg_base + UART_SW_MODE_OFFSET);
+ }
+#endif
+ break;
+#if !defined(BL702L)
+ case UART_CMD_IR_CONFIG: {
+ struct bflb_uart_ir_config_s *ir_config = (struct bflb_uart_ir_config_s *)arg;
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+ if (ir_config->tx_en) {
+ tx_tmp |= UART_CR_UTX_IR_EN;
+ } else {
+ tx_tmp &= ~UART_CR_UTX_IR_EN;
+ }
+ if (ir_config->tx_inverse) {
+ tx_tmp |= UART_CR_UTX_IR_INV;
+ } else {
+ tx_tmp &= ~UART_CR_UTX_IR_INV;
+ }
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+ if (ir_config->rx_en) {
+ rx_tmp |= UART_CR_URX_IR_EN;
+ } else {
+ rx_tmp &= ~UART_CR_URX_IR_EN;
+ }
+ if (ir_config->rx_inverse) {
+ rx_tmp |= UART_CR_URX_IR_INV;
+ } else {
+ rx_tmp &= ~UART_CR_URX_IR_INV;
+ }
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ /* Configure tx ir pulse start and stop position */
+ putreg32((ir_config->tx_pluse_stop << 16) | ir_config->tx_pluse_start, reg_base + UART_UTX_IR_POSITION_OFFSET);
+ /* Configure rx ir pulse start position */
+ putreg32(ir_config->rx_pluse_start, reg_base + UART_URX_IR_POSITION_OFFSET);
+ } break;
+#endif
+ case UART_CMD_SET_TX_FREERUN:
+ /* Set tx freerun */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+ if (arg) {
+ tx_tmp |= UART_CR_UTX_FRM_EN;
+ } else {
+ tx_tmp &= ~UART_CR_UTX_FRM_EN;
+ }
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ break;
+ case UART_CMD_SET_TX_END_INTERRUPT:
+ /* Set tx end interrupt */
+ int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ if (arg) {
+ int_mask &= ~UART_CR_UTX_END_MASK;
+ } else {
+ int_mask |= UART_CR_UTX_END_MASK;
+ }
+ putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+ break;
+ case UART_CMD_SET_RX_END_INTERRUPT:
+ /* Set rx end interrupt */
+ int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ if (arg) {
+ int_mask &= ~UART_CR_URX_END_MASK;
+ } else {
+ int_mask |= UART_CR_URX_END_MASK;
+ }
+ putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+ break;
+ case UART_CMD_SET_TX_TRANSFER_LEN:
+ /* Set tx transfer length */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+ tx_tmp |= ((arg - 1) << UART_CR_UTX_LEN_SHIFT);
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ break;
+ case UART_CMD_SET_RX_TRANSFER_LEN:
+ /* Set rx transfer length */
+ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+ rx_tmp |= ((arg - 1) << UART_CR_URX_LEN_SHIFT);
+
+ putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+ break;
+ case UART_CMD_SET_TX_EN:
+ /* Set tx enable */
+ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+ if (arg) {
+ tx_tmp |= UART_CR_UTX_EN;
+ } else {
+ tx_tmp &= ~UART_CR_UTX_EN;
+ }
+
+ putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+ break;
+#if !defined(BL602) && !defined(BL702)
+ case UART_CMD_SET_BCR_END_INTERRUPT:
+ /* Set bcr value */
+ int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+ int_mask &= ~UART_CR_URX_BCR_MASK;
+ putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+
+ rx_tmp = getreg32(reg_base + UART_URX_BCR_INT_CFG_OFFSET);
+ rx_tmp &= ~UART_CR_URX_BCR_VALUE_MASK;
+ rx_tmp |= (arg << UART_CR_URX_BCR_VALUE_SHIFT);
+ putreg32(rx_tmp, reg_base + UART_URX_BCR_INT_CFG_OFFSET);
+ break;
+ case UART_CMD_GET_BCR_COUNT:
+ /* Get bcr value */
+ rx_tmp = getreg32(reg_base + UART_URX_BCR_INT_CFG_OFFSET);
+ return ((rx_tmp & UART_STS_URX_BCR_COUNT_MASK) >> UART_STS_URX_BCR_COUNT_SHIFT);
+ break;
+#endif
+ default:
+ ret = -EPERM;
+ break;
+ }
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_usb_v1.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_usb_v1.c
new file mode 100644
index 00000000..88d90c9d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_usb_v1.c
@@ -0,0 +1,584 @@
+#include "bflb_core.h"
+#include "bflb_gpio.h"
+#include "usbd_core.h"
+#include "hardware/usb_v1_reg.h"
+
+#define BL702_USB_BASE ((uint32_t)0x4000D800)
+#define BL702_GLB_BASE ((uint32_t)0x40000000)
+
+#define GLB_USB_XCVR_OFFSET (0x228) /* usb_xcvr */
+#define GLB_USB_XCVR_CONFIG_OFFSET (0x22C) /* usb_xcvr_config */
+
+/* 0x228 : usb_xcvr */
+#define GLB_USB_LDO_VFB_SHIFT (0U)
+#define GLB_USB_LDO_VFB_MASK (0x7 << GLB_USB_LDO_VFB_SHIFT)
+#define GLB_PU_USB_LDO (1 << 3U)
+#define GLB_USB_ROUT_NMOS_SHIFT (4U)
+#define GLB_USB_ROUT_NMOS_MASK (0x7 << GLB_USB_ROUT_NMOS_SHIFT)
+#define GLB_USB_ROUT_PMOS_SHIFT (8U)
+#define GLB_USB_ROUT_PMOS_MASK (0x7 << GLB_USB_ROUT_PMOS_SHIFT)
+#define GLB_USB_OEB_SEL (1 << 12U)
+#define GLB_USB_OEB_REG (1 << 13U)
+#define GLB_USB_OEB (1 << 14U)
+#define GLB_USB_DATA_CONVERT (1 << 16U)
+#define GLB_USB_ENUM (1 << 20U)
+#define GLB_USB_SPD (1 << 21U)
+#define GLB_USB_SUS (1 << 22U)
+#define GLB_PU_USB (1 << 23U)
+#define GLB_USB_BD (1 << 24U)
+#define GLB_USB_VIM (1 << 25U)
+#define GLB_USB_VIP (1 << 26U)
+#define GLB_USB_RCV (1 << 27U)
+
+/* 0x22C : usb_xcvr_config */
+#define GLB_USB_V_HYS_M_SHIFT (0U)
+#define GLB_USB_V_HYS_M_MASK (0x3 << GLB_USB_V_HYS_M_SHIFT)
+#define GLB_USB_V_HYS_P_SHIFT (2U)
+#define GLB_USB_V_HYS_P_MASK (0x3 << GLB_USB_V_HYS_P_SHIFT)
+#define GLB_USB_BD_VTH_SHIFT (4U)
+#define GLB_USB_BD_VTH_MASK (0x7 << GLB_USB_BD_VTH_SHIFT)
+#define GLB_REG_USB_USE_XCVR (1 << 7U)
+#define GLB_USB_STR_DRV_SHIFT (8U)
+#define GLB_USB_STR_DRV_MASK (0x7 << GLB_USB_STR_DRV_SHIFT)
+#define GLB_REG_USB_USE_CTRL (1 << 11U)
+#define GLB_USB_RES_PULLUP_TUNE_SHIFT (12U)
+#define GLB_USB_RES_PULLUP_TUNE_MASK (0x7 << GLB_USB_RES_PULLUP_TUNE_SHIFT)
+#define GLB_USB_SLEWRATE_M_FALL_SHIFT (16U)
+#define GLB_USB_SLEWRATE_M_FALL_MASK (0x7 << GLB_USB_SLEWRATE_M_FALL_SHIFT)
+#define GLB_USB_SLEWRATE_M_RISE_SHIFT (20U)
+#define GLB_USB_SLEWRATE_M_RISE_MASK (0x7 << GLB_USB_SLEWRATE_M_RISE_SHIFT)
+#define GLB_USB_SLEWRATE_P_FALL_SHIFT (24U)
+#define GLB_USB_SLEWRATE_P_FALL_MASK (0x7 << GLB_USB_SLEWRATE_P_FALL_SHIFT)
+#define GLB_USB_SLEWRATE_P_RISE_SHIFT (28U)
+#define GLB_USB_SLEWRATE_P_RISE_MASK (0x7 << GLB_USB_SLEWRATE_P_RISE_SHIFT)
+
+#define USB_NUM_BIDIR_ENDPOINTS 9
+
+/* Endpoint state */
+struct bl_ep_state {
+ uint16_t ep_mps; /* Endpoint max packet size */
+ uint8_t ep_type; /* Endpoint type */
+ uint8_t ep_stalled; /* Endpoint stall flag */
+ uint8_t ep_enable; /* Endpoint enable */
+ uint8_t *xfer_buf;
+ uint32_t xfer_len;
+ uint32_t actual_xfer_len;
+};
+
+struct bl_udc {
+ struct usb_setup_packet setup;
+ struct bl_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters */
+ struct bl_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
+} g_bl_udc;
+
+void USBD_IRQHandler(int irq, void *arg);
+
+static void bflb_usb_mem2fifo(uint8_t ep_idx, uint8_t *data, uint32_t length)
+{
+ uint32_t fifo_addr = BL702_USB_BASE + USB_EP0_TX_FIFO_WDATA_OFFSET + ep_idx * 0x10;
+
+ uint8_t *p = (uint8_t *)fifo_addr;
+ uint8_t *q = data;
+
+ while (length--) {
+ *p = *q++;
+ }
+}
+
+static void bflb_usb_fifo2mem(uint8_t ep_idx, uint8_t *data, uint32_t length)
+{
+ uint32_t fifo_addr = BL702_USB_BASE + USB_EP0_RX_FIFO_RDATA_OFFSET + ep_idx * 0x10;
+
+ uint8_t *p = (uint8_t *)fifo_addr;
+ uint8_t *q = data;
+
+ while (length--) {
+ *q++ = *p;
+ }
+}
+
+static void bflb_usb_xcvr_config(void)
+{
+ uint32_t regval;
+
+ regval = getreg32(BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+ regval |= GLB_PU_USB;
+ putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+
+ regval = getreg32(BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+ regval &= ~GLB_USB_SUS;
+ regval |= GLB_USB_SPD; /* 0 for 1.1 ls,1 for 1.1 fs */
+ regval &= ~GLB_USB_DATA_CONVERT;
+ regval &= ~GLB_USB_OEB_SEL;
+ regval &= ~GLB_USB_ROUT_PMOS_MASK;
+ regval &= ~GLB_USB_ROUT_NMOS_MASK;
+ regval |= (3 << GLB_USB_ROUT_PMOS_SHIFT);
+ regval |= (3 << GLB_USB_ROUT_NMOS_SHIFT);
+ putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+
+ regval = 0;
+ regval |= (2 << GLB_USB_V_HYS_M_SHIFT);
+ regval |= (2 << GLB_USB_V_HYS_P_SHIFT);
+ regval |= (7 << GLB_USB_BD_VTH_SHIFT);
+ regval |= GLB_REG_USB_USE_XCVR;
+ regval |= GLB_REG_USB_USE_CTRL;
+ regval |= (0 << GLB_USB_STR_DRV_SHIFT);
+ regval |= (5 << GLB_USB_RES_PULLUP_TUNE_SHIFT);
+ regval |= (2 << GLB_USB_SLEWRATE_M_FALL_SHIFT);
+ regval |= (2 << GLB_USB_SLEWRATE_M_RISE_SHIFT);
+ regval |= (2 << GLB_USB_SLEWRATE_P_FALL_SHIFT);
+ regval |= (2 << GLB_USB_SLEWRATE_P_RISE_SHIFT);
+ putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_CONFIG_OFFSET);
+
+ regval = getreg32(BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+ regval |= GLB_USB_ENUM;
+ putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+}
+
+static void bflb_usb_ep0_size(uint8_t ep_mps)
+{
+ uint32_t regval;
+
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval &= ~USB_CR_USB_EP0_SW_SIZE_MASK;
+ regval |= (ep_mps << USB_CR_USB_EP0_SW_SIZE_SHIFT);
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+}
+
+static void bflb_usb_ep_config(uint8_t ep_idx, uint8_t ep_type, uint8_t dir, uint16_t ep_mps)
+{
+ uint32_t regval;
+
+ regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+ regval &= ~USB_CR_EP1_SIZE_MASK;
+ regval &= ~USB_CR_EP1_TYPE_MASK;
+ regval &= ~USB_CR_EP1_DIR_MASK;
+ regval |= (ep_mps << USB_CR_EP1_SIZE_SHIFT);
+ regval |= (dir << USB_CR_EP1_DIR_SHIFT);
+ regval |= (ep_type << USB_CR_EP1_TYPE_SHIFT);
+ putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+}
+
+static void bflb_usb_ep_set_nak(uint8_t ep_idx)
+{
+ uint32_t regval;
+
+ if (ep_idx == 0) {
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+ regval |= USB_CR_USB_EP0_SW_NACK_IN;
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+ } else {
+ regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+ regval |= USB_CR_EP1_NACK;
+ regval &= ~USB_CR_EP1_STALL;
+ putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+ }
+}
+
+static void bflb_usb_ep_set_ready(uint8_t ep_idx)
+{
+ uint32_t regval;
+
+ if (ep_idx == 0) {
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval |= USB_CR_USB_EP0_SW_RDY;
+ regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+ regval |= USB_CR_USB_EP0_SW_NACK_IN;
+ regval &= ~USB_CR_USB_EP0_SW_STALL;
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+ } else {
+ regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+ regval |= USB_CR_EP1_RDY;
+ regval |= USB_CR_EP1_NACK;
+ regval &= ~USB_CR_EP1_STALL;
+ putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+ }
+}
+
+static uint16_t bflb_usb_get_rxcount(uint8_t ep_idx)
+{
+ return (getreg32(BL702_USB_BASE + USB_EP0_FIFO_STATUS_OFFSET + 0x10 * ep_idx) & USB_EP0_RX_FIFO_CNT_MASK) >> USB_EP0_RX_FIFO_CNT_SHIFT;
+}
+
+// static uint16_t bflb_usb_get_txcount(uint8_t ep_idx)
+// {
+// return (getreg32(BL702_USB_BASE + USB_EP0_FIFO_STATUS_OFFSET + 0x10 * ep_idx) & USB_EP0_TX_FIFO_CNT_MASK) >> USB_EP0_TX_FIFO_CNT_SHIFT;
+// }
+
+static bool bflb_usb_ep_isbusy(uint8_t ep_idx)
+{
+ uint32_t regval;
+
+ if (ep_idx == 0) {
+ regval = (getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET) & USB_STS_USB_EP0_SW_RDY);
+ } else {
+ regval = (getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1)) & USB_STS_EP1_RDY);
+ }
+ return regval ? true : false;
+}
+
+static uint32_t bflb_usb_get_intstatus(void)
+{
+ uint32_t regval;
+
+ regval = getreg32(BL702_USB_BASE + USB_INT_STS_OFFSET);
+ regval &= ~getreg32(BL702_USB_BASE + USB_INT_MASK_OFFSET);
+ regval &= getreg32(BL702_USB_BASE + USB_INT_EN_OFFSET);
+ return regval;
+}
+
+static void bflb_usb_int_clear(uint32_t int_clear)
+{
+ uint32_t regval;
+ regval = getreg32(BL702_USB_BASE + USB_INT_CLEAR_OFFSET);
+ regval |= int_clear;
+ putreg32(regval, BL702_USB_BASE + USB_INT_CLEAR_OFFSET);
+}
+
+int usb_dc_init(void)
+{
+ uint32_t regval;
+
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+
+ bflb_usb_xcvr_config();
+
+ /* disable USB first */
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval &= ~USB_CR_USB_EN;
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+ /* USB ep0 config */
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval |= USB_CR_USB_EP0_SW_CTRL;
+ regval &= ~USB_CR_USB_EP0_SW_ADDR_MASK;
+ regval &= ~USB_CR_USB_EP0_SW_SIZE_MASK;
+ regval |= (64 << USB_CR_USB_EP0_SW_SIZE_SHIFT);
+ regval |= USB_CR_USB_EP0_SW_NACK_IN;
+ regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+ regval &= ~USB_CR_USB_ROM_DCT_EN;
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+ regval = 0;
+ regval |= USB_CR_USB_RESET_EN;
+ regval |= USB_CR_EP0_SETUP_DONE_EN;
+ regval |= USB_CR_EP0_IN_DONE_EN;
+ regval |= USB_CR_EP0_OUT_DONE_EN;
+ regval |= USB_CR_USB_REND_EN;
+ putreg32(regval, BL702_USB_BASE + USB_INT_EN_OFFSET);
+
+ regval = 0xffffffff;
+ regval &= ~USB_CR_USB_RESET_MASK;
+ regval &= ~USB_CR_EP0_SETUP_DONE_MASK;
+ regval &= ~USB_CR_EP0_IN_DONE_MASK;
+ regval &= ~USB_CR_EP0_OUT_DONE_MASK;
+ regval &= ~USB_CR_USB_REND_MASK;
+ putreg32(regval, BL702_USB_BASE + USB_INT_MASK_OFFSET);
+
+ putreg32(0xffffffff, BL702_USB_BASE + USB_INT_CLEAR_OFFSET);
+
+ bflb_irq_attach(37, USBD_IRQHandler, NULL);
+ bflb_irq_enable(37);
+
+ /* enable usb */
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval |= USB_CR_USB_EN;
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+ return 0;
+}
+
+int usbd_set_address(const uint8_t addr)
+{
+ uint32_t regval;
+
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval &= ~USB_CR_USB_EP0_SW_ADDR_MASK;
+ regval |= (addr << USB_CR_USB_EP0_SW_ADDR_SHIFT);
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+ return 0;
+}
+
+uint8_t usbd_get_port_speed(const uint8_t port)
+{
+ return USB_SPEED_FULL;
+}
+
+int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
+{
+ uint8_t ep;
+ uint8_t ep_type;
+ uint8_t dir;
+ uint32_t regval;
+
+ ep = ep_cfg->ep_addr;
+
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (ep_idx > USB_NUM_BIDIR_ENDPOINTS) {
+ return -1;
+ }
+
+ if (USB_EP_DIR_IS_OUT(ep)) {
+ g_bl_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+ g_bl_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
+ g_bl_udc.out_ep[ep_idx].ep_enable = 1U;
+ dir = 2;
+ } else {
+ g_bl_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+ g_bl_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
+ g_bl_udc.in_ep[ep_idx].ep_enable = 1U;
+ dir = 1;
+ }
+
+ if (ep_idx != 0) {
+ switch (ep_cfg->ep_type) {
+ case 1:
+ ep_type = 2;
+ break;
+ case 2:
+ ep_type = 4;
+ break;
+ case 3:
+ ep_type = 0;
+ break;
+
+ default:
+ ep_type = 4;
+ break;
+ }
+ bflb_usb_ep_config(ep_idx, ep_type, dir, ep_cfg->ep_mps);
+
+ regval = getreg32(BL702_USB_BASE + USB_INT_EN_OFFSET);
+ regval |= (1 << (9 + ep_idx * 2));
+ putreg32(regval, BL702_USB_BASE + USB_INT_EN_OFFSET);
+
+ regval = getreg32(BL702_USB_BASE + USB_INT_MASK_OFFSET);
+ regval &= ~(1 << (9 + ep_idx * 2));
+ putreg32(regval, BL702_USB_BASE + USB_INT_MASK_OFFSET);
+
+ bflb_usb_ep_set_nak(ep_idx);
+ }
+ return 0;
+}
+
+int usbd_ep_close(const uint8_t ep)
+{
+ return 0;
+}
+
+int usbd_ep_set_stall(const uint8_t ep)
+{
+ uint32_t regval;
+
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (ep_idx == 0) {
+ regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+ regval |= USB_CR_USB_EP0_SW_RDY;
+ regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+ regval |= USB_CR_USB_EP0_SW_NACK_IN;
+ regval |= USB_CR_USB_EP0_SW_STALL;
+ putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+ } else {
+ regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+ regval |= USB_CR_EP1_STALL;
+ putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+ }
+
+ return 0;
+}
+
+int usbd_ep_clear_stall(const uint8_t ep)
+{
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (ep_idx == 0) {
+ } else {
+ bflb_usb_ep_set_ready(ep_idx);
+ }
+
+ return 0;
+}
+
+int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
+{
+ return 0;
+}
+
+int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
+{
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (!data && data_len) {
+ return -1;
+ }
+
+ if (!g_bl_udc.in_ep[ep_idx].ep_enable) {
+ return -2;
+ }
+
+ g_bl_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
+ g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+ g_bl_udc.in_ep[ep_idx].actual_xfer_len = 0;
+
+ data_len = MIN(data_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+
+ if (ep_idx == 0) {
+ if (data_len == 1) {
+ bflb_usb_ep0_size(1);
+ } else {
+ bflb_usb_ep0_size(g_bl_udc.in_ep[ep_idx].ep_mps);
+ }
+ }
+
+ bflb_usb_mem2fifo(ep_idx, g_bl_udc.in_ep[ep_idx].xfer_buf, data_len);
+ bflb_usb_ep_set_ready(ep_idx);
+
+ return 0;
+}
+
+int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
+{
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (!data && data_len) {
+ return -1;
+ }
+
+ if (!g_bl_udc.out_ep[ep_idx].ep_enable) {
+ return -2;
+ }
+
+ g_bl_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data;
+ g_bl_udc.out_ep[ep_idx].xfer_len = data_len;
+ g_bl_udc.out_ep[ep_idx].actual_xfer_len = 0;
+ bflb_usb_ep_set_ready(ep_idx);
+
+ return 0;
+}
+
+void USBD_IRQHandler(int irq, void *arg)
+{
+ uint32_t regval;
+ uint32_t intstatus;
+ uint16_t rx_count;
+ uint16_t tx_count;
+
+ intstatus = bflb_usb_get_intstatus();
+ bflb_usb_int_clear(intstatus);
+
+ for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
+ if (intstatus & (1 << (9 + 2 * ep_idx))) {
+ if (g_bl_udc.in_ep[ep_idx].ep_enable) {
+ tx_count = MIN(g_bl_udc.in_ep[ep_idx].xfer_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+ g_bl_udc.in_ep[ep_idx].xfer_buf += tx_count;
+ g_bl_udc.in_ep[ep_idx].xfer_len -= tx_count;
+ g_bl_udc.in_ep[ep_idx].actual_xfer_len += tx_count;
+
+ if (g_bl_udc.in_ep[ep_idx].xfer_len == 0) {
+ usbd_event_ep_in_complete_handler(ep_idx | 0x80, g_bl_udc.in_ep[ep_idx].actual_xfer_len);
+ } else {
+ tx_count = MIN(g_bl_udc.in_ep[ep_idx].xfer_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+ bflb_usb_mem2fifo(ep_idx, g_bl_udc.in_ep[ep_idx].xfer_buf, tx_count);
+ bflb_usb_ep_set_ready(ep_idx);
+ }
+ } else {
+ while (bflb_usb_ep_isbusy(ep_idx)) {
+ }
+
+ rx_count = bflb_usb_get_rxcount(ep_idx);
+ bflb_usb_fifo2mem(ep_idx, g_bl_udc.out_ep[ep_idx].xfer_buf, rx_count);
+
+ g_bl_udc.out_ep[ep_idx].xfer_buf += rx_count;
+ g_bl_udc.out_ep[ep_idx].xfer_len -= rx_count;
+ g_bl_udc.out_ep[ep_idx].actual_xfer_len += rx_count;
+
+ if ((rx_count < g_bl_udc.out_ep[ep_idx].ep_mps) ||
+ (g_bl_udc.out_ep[ep_idx].xfer_len == 0)) {
+ usbd_event_ep_out_complete_handler(ep_idx, g_bl_udc.out_ep[ep_idx].actual_xfer_len);
+ } else {
+ bflb_usb_ep_set_ready(ep_idx);
+ }
+ }
+ }
+ }
+
+ if (intstatus & USB_EP0_SETUP_DONE_INT) {
+ while (bflb_usb_ep_isbusy(0)) {
+ }
+
+ rx_count = bflb_usb_get_rxcount(0);
+ if (rx_count != 8) {
+ printf("setup fail\r\n");
+ return;
+ }
+ bflb_usb_fifo2mem(0, (uint8_t *)&g_bl_udc.setup, 8);
+ usbd_event_ep0_setup_complete_handler((uint8_t *)&g_bl_udc.setup);
+ }
+ if (intstatus & USB_EP0_IN_DONE_INT) {
+ tx_count = MIN(g_bl_udc.in_ep[0].xfer_len, g_bl_udc.in_ep[0].ep_mps);
+ g_bl_udc.in_ep[0].xfer_buf += tx_count;
+ g_bl_udc.in_ep[0].xfer_len -= tx_count;
+ g_bl_udc.in_ep[0].actual_xfer_len += tx_count;
+
+ usbd_event_ep_in_complete_handler(0 | 0x80, g_bl_udc.in_ep[0].actual_xfer_len);
+
+ if (g_bl_udc.setup.wLength == 0) {
+ /* In status, start reading setup */
+ bflb_usb_ep_set_ready(0);
+ } else if (g_bl_udc.setup.wLength && ((g_bl_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
+ /* In status, start reading setup */
+ bflb_usb_ep_set_ready(0);
+ }
+ }
+ if (intstatus & USB_EP0_OUT_DONE_INT) {
+ while (bflb_usb_ep_isbusy(0)) {
+ }
+
+ rx_count = bflb_usb_get_rxcount(0);
+
+ bflb_usb_fifo2mem(0, g_bl_udc.out_ep[0].xfer_buf, rx_count);
+ g_bl_udc.out_ep[0].xfer_buf += rx_count;
+ g_bl_udc.out_ep[0].xfer_len -= rx_count;
+ g_bl_udc.out_ep[0].actual_xfer_len += rx_count;
+
+ usbd_event_ep_out_complete_handler(0, g_bl_udc.out_ep[0].actual_xfer_len);
+
+ if (rx_count == 0) {
+ /* Out status, start reading setup */
+ bflb_usb_ep_set_ready(0);
+ }
+ }
+
+ if (intstatus & USB_RESET_INT) {
+ memset(&g_bl_udc, 0, sizeof(g_bl_udc));
+
+ regval = 0;
+ regval |= USB_CR_EP0_SETUP_DONE_EN;
+ regval |= USB_CR_EP0_IN_DONE_EN;
+ regval |= USB_CR_EP0_OUT_DONE_EN;
+ regval |= USB_CR_USB_REND_EN;
+ putreg32(regval, BL702_USB_BASE + USB_INT_EN_OFFSET);
+
+ regval = 0xffffffff;
+ regval &= ~USB_CR_USB_RESET_MASK;
+ regval &= ~USB_CR_EP0_SETUP_DONE_MASK;
+ regval &= ~USB_CR_EP0_IN_DONE_MASK;
+ regval &= ~USB_CR_EP0_OUT_DONE_MASK;
+ regval &= ~USB_CR_USB_REND_MASK;
+ putreg32(regval, BL702_USB_BASE + USB_INT_MASK_OFFSET);
+
+ usbd_event_reset_handler();
+ }
+ if (intstatus & USB_REND_INT) {
+ bflb_usb_ep_set_ready(0);
+ }
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_usb_v2.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_usb_v2.c
new file mode 100644
index 00000000..497f928f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_usb_v2.c
@@ -0,0 +1,1073 @@
+#include "bflb_core.h"
+#include "usbd_core.h"
+#include "usbh_core.h"
+#include "hardware/usb_v2_reg.h"
+
+// #define CONFIG_USB_PINGPONG_ENABLE
+
+#define BLFB_USB_BASE ((uint32_t)0x20072000)
+#define BFLB_PDS_BASE ((uint32_t)0x2000e000)
+
+#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */
+#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */
+
+/* 0x500 : usb_ctl */
+#define PDS_REG_USB_SW_RST_N (1 << 0U)
+#define PDS_REG_USB_EXT_SUSP_N (1 << 1U)
+#define PDS_REG_USB_WAKEUP (1 << 2U)
+#define PDS_REG_USB_L1_WAKEUP (1 << 3U)
+#define PDS_REG_USB_DRVBUS_POL (1 << 4U)
+#define PDS_REG_USB_IDDIG (1 << 5U)
+
+/* 0x504 : usb_phy_ctrl */
+#define PDS_REG_USB_PHY_PONRST (1 << 0U)
+#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U)
+#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U)
+#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT)
+#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U)
+#define PDS_REG_USB_PHY_PLLALIV (1 << 5U)
+#define PDS_REG_PU_USB20_PSW (1 << 6U)
+
+#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C)
+#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710)
+
+void USBD_IRQHandler(int irq, void *arg);
+
+extern void USBH_IRQHandler();
+
+static void bflb_usb_phy_init(void)
+{
+ uint32_t regval;
+
+ /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */
+ /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
+ /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */
+ /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */
+ /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */
+ /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */
+ /* #1.2ms; wait UCLK */
+ /* wait(soc616_b0.usb_uclk); */
+
+ regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+ regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK;
+ putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+
+ regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+ regval |= PDS_REG_PU_USB20_PSW;
+ putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+
+ regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+ regval |= PDS_REG_USB_PHY_PONRST;
+ putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+
+ /* greater than 5T */
+ bflb_mtimer_delay_us(1);
+
+ regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+ regval &= ~PDS_REG_USB_SW_RST_N;
+ putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+ /* greater than 5T */
+ bflb_mtimer_delay_us(1);
+
+ regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+ regval |= PDS_REG_USB_EXT_SUSP_N;
+ putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+ /* wait UCLK 1.2ms */
+ bflb_mtimer_delay_ms(3);
+
+ regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+ regval |= PDS_REG_USB_SW_RST_N;
+ putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+ bflb_mtimer_delay_ms(2);
+}
+
+void usb_hc_low_level_init(void)
+{
+ uint32_t regval;
+
+ bflb_usb_phy_init();
+
+ bflb_irq_attach(37, USBH_IRQHandler, NULL);
+ bflb_irq_enable(37);
+
+ /* enable device-A for host */
+ regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+ regval &= ~PDS_REG_USB_IDDIG;
+ putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+ regval |= USB_A_BUS_DROP_HOV;
+ regval &= ~USB_A_BUS_REQ_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+
+ bflb_mtimer_delay_ms(10);
+
+ /* enable vbus and bus control */
+ regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+ regval &= ~USB_A_BUS_DROP_HOV;
+ regval |= USB_A_BUS_REQ_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+ regval |= USB_MDEV_INT;
+ regval |= USB_MOTG_INT;
+ regval &= ~USB_MHC_INT;
+ putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+}
+
+uint8_t usbh_get_port_speed(const uint8_t port)
+{
+ uint8_t speed = 3;
+
+ speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
+
+ if (speed == 0) {
+ return USB_SPEED_FULL;
+ } else if (speed == 1) {
+ return USB_SPEED_LOW;
+ } else if (speed == 2) {
+ return USB_SPEED_HIGH;
+ }
+ return USB_SPEED_HIGH;
+}
+
+#define USB_FIFO_F0 0
+#define USB_FIFO_F1 1
+#define USB_FIFO_F2 2
+#define USB_FIFO_F3 3
+#define USB_FIFO_CXF 0xff
+
+#define USB_FIFO_DIR_OUT 0
+#define USB_FIFO_DIR_IN 1
+#define USB_FIFO_DIR_BID 2
+
+#define USB_VDMA_DIR_FIFO2MEM 0
+#define USB_VDMA_DIR_MEM2FIFO 1
+
+#define USB_NUM_BIDIR_ENDPOINTS 5
+
+/* Endpoint state */
+struct bl_ep_state {
+ uint16_t ep_mps; /* Endpoint max packet size */
+ uint8_t ep_type; /* Endpoint type */
+ uint8_t ep_stalled; /* Endpoint stall flag */
+ uint8_t ep_enable; /* Endpoint enable */
+ bool ep_active;
+ uint8_t *xfer_buf;
+ uint32_t xfer_len;
+ uint32_t actual_xfer_len;
+};
+
+struct bl_udc {
+ struct bl_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters */
+ struct bl_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
+} g_bl_udc;
+
+static void bflb_usb_reset_fifo(uint8_t fifo)
+{
+ uint32_t regval;
+
+ if (fifo == USB_FIFO_CXF) {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+ regval |= USB_CX_CLR;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+ } else {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo);
+ regval |= USB_FFRST0_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo);
+ }
+}
+
+static void bflb_usb_get_setup_packet(uint32_t setup[2])
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+ regval |= USB_ACC_CXF_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+
+ setup[0] = getreg32(BLFB_USB_BASE + USB_DMA_CPS3_OFFSET);
+ setup[1] = getreg32(BLFB_USB_BASE + USB_DMA_CPS3_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+ regval &= ~USB_ACC_CXF_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+}
+
+static void bflb_usb_set_ep_fifomap(uint8_t ep_idx, uint8_t fifo)
+{
+ uint32_t regval;
+
+ if (ep_idx < 5) {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_EPMAP0_OFFSET);
+ regval &= ~(0xff << ((ep_idx - 1) * 8));
+ regval |= (fifo << ((ep_idx - 1) * 8));
+ regval |= (fifo << ((ep_idx - 1) * 8 + 4));
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_EPMAP0_OFFSET);
+ } else {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_EPMAP1_OFFSET);
+ regval &= ~(0xff << ((ep_idx - 4 - 1) * 8));
+ regval |= (fifo << ((ep_idx - 4 - 1) * 8));
+ regval |= (fifo << ((ep_idx - 4 - 1) * 8 + 4));
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_EPMAP1_OFFSET);
+ }
+}
+
+static void bflb_usb_set_fifo_epmap(uint8_t fifo, uint8_t ep_idx, uint8_t dir)
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_FMAP_OFFSET);
+ regval &= ~(0x3f << (fifo * 8));
+ regval |= (ep_idx << (fifo * 8));
+ regval |= (dir << (fifo * 8 + 4));
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_FMAP_OFFSET);
+}
+
+static void bflb_usb_set_outep_mps(uint8_t ep_idx, uint16_t ep_mps)
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+ regval &= ~USB_MAXPS_OEP1_MASK;
+ regval |= ep_mps;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static void bflb_usb_set_inep_mps(uint8_t ep_idx, uint16_t ep_mps)
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+ regval &= ~USB_MAXPS_IEP1_MASK;
+ regval |= ep_mps;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static uint8_t bflb_usb_get_fifo_ep(uint8_t fifo)
+{
+ uint32_t regval;
+
+ regval = (getreg32(BLFB_USB_BASE + USB_DEV_FMAP_OFFSET) & (0xf << (fifo * 8)));
+ regval >>= (fifo * 8);
+ return regval;
+}
+
+static void bflb_usb_fifo_config(uint8_t fifo, uint8_t ep_type, uint16_t block_size, uint8_t block_num, bool fifo_en)
+{
+ uint32_t regval;
+
+ if (fifo < 4) {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_FCFG_OFFSET);
+ regval &= ~(0x3f << (fifo * 8));
+ regval |= (ep_type << (fifo * 8 + 0));
+ regval |= ((block_num - 1) << (fifo * 8 + 2));
+ if (block_size == 1024) {
+ regval |= (1 << (fifo * 8 + 4));
+ }
+
+ if (fifo_en) {
+ regval |= (1 << (fifo * 8 + 5));
+ }
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_FCFG_OFFSET);
+ }
+}
+
+static void bflb_usb_vdma_start_write(uint8_t fifo, const uint8_t *data, uint32_t len)
+{
+ uint32_t regval;
+
+ if (fifo == USB_FIFO_CXF) {
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+ regval &= ~USB_VDMA_LEN_CXF_MASK;
+ regval &= ~USB_VDMA_IO_CXF;
+ regval |= USB_VDMA_TYPE_CXF;
+ regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+
+ putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_CXFPS2_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+ regval |= USB_VDMA_START_CXF;
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+ } else {
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+ regval &= ~USB_VDMA_LEN_CXF_MASK;
+ regval &= ~USB_VDMA_IO_CXF;
+ regval |= USB_VDMA_TYPE_CXF;
+ regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+
+ putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8);
+
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+ regval |= USB_VDMA_START_CXF;
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+ }
+}
+
+static void bflb_usb_vdma_start_read(uint8_t fifo, uint8_t *data, uint32_t len)
+{
+ uint32_t regval;
+
+ if (fifo == USB_FIFO_CXF) {
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+ regval &= ~USB_VDMA_LEN_CXF_MASK;
+ regval &= ~USB_VDMA_IO_CXF;
+ regval &= ~USB_VDMA_TYPE_CXF;
+ regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+
+ putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_CXFPS2_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+ regval |= USB_VDMA_START_CXF;
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+ } else {
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+ regval &= ~USB_VDMA_LEN_CXF_MASK;
+ regval &= ~USB_VDMA_IO_CXF;
+ regval &= ~USB_VDMA_TYPE_CXF;
+ regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+
+ putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8);
+
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+ regval |= USB_VDMA_START_CXF;
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+ }
+}
+
+static uint32_t bflb_usb_vdma_get_remain_size(uint8_t fifo)
+{
+ uint32_t regval;
+
+ if (fifo == USB_FIFO_CXF) {
+ regval = (getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET) & USB_VDMA_LEN_CXF_MASK);
+ regval >>= USB_VDMA_LEN_CXF_SHIFT;
+
+ } else {
+ regval = (getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8) & USB_VDMA_LEN_CXF_MASK);
+ regval >>= USB_VDMA_LEN_CXF_SHIFT;
+ }
+
+ return regval;
+}
+
+static inline void bflb_usb_control_transfer_done(void)
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+ regval |= USB_CX_DONE;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+}
+
+static inline void bflb_usb_set_mult(uint8_t ep_idx, uint8_t mult)
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+ regval &= ~USB_TX_NUM_HBW_IEP1_MASK;
+ regval |= (mult << USB_TX_NUM_HBW_IEP1_SHIFT);
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static inline void bflb_usb_send_zlp(uint8_t ep_idx)
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+ regval |= USB_TX0BYTE_IEP1;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static inline uint32_t bflb_usb_get_tx_zlp_intstatus(void)
+{
+ return getreg32(BLFB_USB_BASE + USB_DEV_TXZ_OFFSET);
+}
+
+static inline uint32_t bflb_usb_get_rx_zlp_intstatus(void)
+{
+ return getreg32(BLFB_USB_BASE + USB_DEV_RXZ_OFFSET);
+}
+
+static inline void bflb_usb_clear_tx_zlp_intstatus(uint8_t ep_idx)
+{
+ putreg32((1 << (ep_idx - 1)), BLFB_USB_BASE + USB_DEV_TXZ_OFFSET);
+}
+
+static inline void bflb_usb_clear_rx_zlp_intstatus(uint8_t ep_idx)
+{
+ putreg32((1 << (ep_idx - 1)), BLFB_USB_BASE + USB_DEV_RXZ_OFFSET);
+}
+
+static uint32_t bflb_usb_get_source_group_intstatus(uint8_t group)
+{
+ switch (group) {
+ case 0:
+ return (getreg32(BLFB_USB_BASE + USB_DEV_ISG0_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG0_OFFSET));
+ case 1:
+ return (getreg32(BLFB_USB_BASE + USB_DEV_ISG1_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG1_OFFSET));
+ case 2:
+ return (getreg32(BLFB_USB_BASE + USB_DEV_ISG2_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG2_OFFSET));
+ case 3:
+ return (getreg32(BLFB_USB_BASE + USB_DEV_ISG3_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG3_OFFSET));
+ case 4:
+ return (getreg32(BLFB_USB_BASE + USB_DEV_ISG4_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG4_OFFSET));
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void bflb_usb_source_group_int_clear(uint8_t group, uint32_t int_clear)
+{
+ switch (group) {
+ case 0:
+ putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG0_OFFSET);
+ break;
+ case 1:
+ putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG1_OFFSET);
+ break;
+ case 2:
+ putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG2_OFFSET);
+ break;
+ case 3:
+ putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG3_OFFSET);
+ break;
+ case 4:
+ putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG4_OFFSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static uint8_t usb_get_transfer_fifo(uint8_t ep_idx)
+{
+ uint8_t target_fifo_id;
+
+ if ((g_bl_udc.out_ep[ep_idx].ep_mps > 512) || (g_bl_udc.in_ep[ep_idx].ep_mps > 512)) {
+#ifdef CONFIG_USB_PINGPONG_ENABLE
+ target_fifo_id = 0;
+#else
+ target_fifo_id = ((2 * ep_idx - 1) - 1);
+#endif
+ } else {
+#ifdef CONFIG_USB_PINGPONG_ENABLE
+ target_fifo_id = ((2 * ep_idx - 1) - 1);
+#else
+ target_fifo_id = (ep_idx - 1);
+#endif
+ }
+
+ return target_fifo_id;
+}
+
+int usb_dc_init(void)
+{
+ uint32_t regval;
+
+ bflb_usb_phy_init();
+
+ bflb_irq_attach(37, USBD_IRQHandler, NULL);
+ bflb_irq_enable(37);
+
+ /* disable global irq */
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+ regval &= ~USB_GLINT_EN_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+ regval |= USB_UNPLUG;
+ putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+ regval &= ~USB_CAP_RMWAKUP;
+ regval |= USB_CHIP_EN_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+ regval |= USB_SFRST_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+ while (getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET) & USB_SFRST_HOV) {
+ }
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+ regval &= ~USB_AFT_CONF;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+ regval &= ~USB_SOFMT_MASK;
+#ifdef CONFIG_USB_HS
+ regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS;
+#else
+ regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS;
+#endif
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+
+ /* enable setup irq in source group0 */
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_MISG0_OFFSET);
+ regval &= ~USB_MCX_SETUP_INT;
+ regval |= USB_MCX_IN_INT;
+ regval |= (1 << 3);
+ regval |= USB_MCX_OUT_INT;
+ regval |= USB_MCX_IN_INT;
+ regval |= USB_MCX_COMFAIL_INT;
+ regval |= USB_MCX_COMABORT_INT;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_MISG0_OFFSET);
+
+ /* disable all fifo irq in source group1 */
+ putreg32(0xffffffff, BLFB_USB_BASE + USB_DEV_MISG1_OFFSET);
+
+ /* enable rst/tx0/rx0 irq in source group2 */
+ regval = 0xffffffff;
+ regval &= ~USB_MUSBRST_INT;
+ regval &= ~USB_MSUSP_INT;
+ regval &= ~USB_MRESM_INT;
+ regval &= ~USB_MTX0BYTE_INT;
+ regval &= ~USB_MRX0BYTE_INT;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_MISG2_OFFSET);
+
+ /* enable vdma cmplt and error irq in source group3 */
+ regval = 0xffffffff;
+ regval &= ~(USB_MVDMA_CMPLT_CXF |
+ USB_MVDMA_CMPLT_F0 |
+ USB_MVDMA_CMPLT_F1 |
+ USB_MVDMA_CMPLT_F2 |
+ USB_MVDMA_CMPLT_F3);
+ // regval &= ~(USB_MVDMA_ERROR_CXF |
+ // USB_MVDMA_ERROR_F0 |
+ // USB_MVDMA_ERROR_F1 |
+ // USB_MVDMA_ERROR_F2 |
+ // USB_MVDMA_ERROR_F3);
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_MISG3_OFFSET);
+
+ /* enable group irq */
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_MIGR_OFFSET);
+ regval &= ~USB_MINT_G0;
+ regval &= ~USB_MINT_G1;
+ regval &= ~USB_MINT_G2;
+ regval &= ~USB_MINT_G3;
+ regval &= ~USB_MINT_G4;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_MIGR_OFFSET);
+
+ /* enable device irq */
+ regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+ regval |= USB_MHC_INT;
+ regval |= USB_MOTG_INT;
+ regval &= ~USB_MDEV_INT;
+ putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+
+ bflb_usb_source_group_int_clear(2, 0x3ff);
+ bflb_usb_source_group_int_clear(3, 0xffffffff);
+
+ for (uint8_t i = 1; i < 9; i++) {
+ bflb_usb_set_ep_fifomap(i, 15);
+ bflb_usb_set_fifo_epmap(i, 15, 0);
+ }
+
+ /* enable vdma */
+ regval = getreg32(BLFB_USB_BASE + USB_VDMA_CTRL_OFFSET);
+ regval |= USB_VDMA_EN;
+ putreg32(regval, BLFB_USB_BASE + USB_VDMA_CTRL_OFFSET);
+
+ regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+ regval &= ~USB_UNPLUG;
+ putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+ /* enable global irq */
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+ regval |= USB_GLINT_EN_HOV;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+ return 0;
+}
+
+int usb_dc_deinit(void)
+{
+ return 0;
+}
+
+int usbd_set_address(const uint8_t addr)
+{
+ uint32_t regval;
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+ regval &= ~USB_DEVADR_MASK;
+ regval |= addr;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+
+ return 0;
+}
+
+uint8_t usbd_get_port_speed(const uint8_t port)
+{
+ uint8_t speed = 3;
+
+ speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
+
+ if (speed == 0) {
+ return USB_SPEED_FULL;
+ } else if (speed == 1) {
+ return USB_SPEED_LOW;
+ } else if (speed == 2) {
+ return USB_SPEED_HIGH;
+ }
+ return USB_SPEED_HIGH;
+}
+
+int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
+{
+ uint8_t ep;
+ uint32_t regval;
+
+ ep = ep_cfg->ep_addr;
+
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if ((ep_idx > 4) && (ep_idx < 9)) {
+ return 0;
+ }
+
+ if (USB_EP_DIR_IS_OUT(ep)) {
+ g_bl_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+ g_bl_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
+ g_bl_udc.out_ep[ep_idx].ep_enable = 1U;
+ bflb_usb_set_outep_mps(ep_idx, ep_cfg->ep_mps);
+ } else {
+ g_bl_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+ g_bl_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
+ g_bl_udc.in_ep[ep_idx].ep_enable = 1U;
+ bflb_usb_set_inep_mps(ep_idx, ep_cfg->ep_mps);
+ bflb_usb_set_mult(ep_idx, 0);
+ }
+
+ if (ep_idx != 0) {
+#ifndef CONFIG_USB_PINGPONG_ENABLE
+ if (ep_cfg->ep_mps > 512) {
+ bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+ bflb_usb_set_ep_fifomap(2, USB_FIFO_F2);
+
+ bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID);
+
+ if (ep_idx == 1) {
+ bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 1024, 1, true);
+ bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 1024, 1, false);
+ } else if (ep_idx == 2) {
+ bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 1024, 1, true);
+ bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 1024, 1, false);
+ } else {
+ return -1;
+ }
+ } else {
+ bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+ bflb_usb_set_ep_fifomap(2, USB_FIFO_F1);
+ bflb_usb_set_ep_fifomap(3, USB_FIFO_F2);
+ bflb_usb_set_ep_fifomap(4, USB_FIFO_F3);
+
+ bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F1, 2, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F2, 3, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F3, 4, USB_FIFO_DIR_BID);
+
+ if (ep_idx == 1) {
+ bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 512, 1, true);
+ } else if (ep_idx == 2) {
+ bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 512, 1, true);
+ } else if (ep_idx == 3) {
+ bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 512, 1, true);
+ } else if (ep_idx == 4) {
+ bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 512, 1, true);
+ } else {
+ return -1;
+ }
+ }
+#else
+ if (ep_cfg->ep_mps > 512) {
+ bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+
+ bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F3, 1, USB_FIFO_DIR_BID);
+
+ if (ep_idx == 1) {
+ bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 1024, 2, true);
+ bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 1024, 2, false);
+ bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 1024, 2, false);
+ bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 1024, 2, false);
+ } else {
+ return -1;
+ }
+ } else {
+ bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+ bflb_usb_set_ep_fifomap(2, USB_FIFO_F2);
+
+ bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID);
+ bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID);
+
+ if (ep_idx == 1) {
+ bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 512, 2, true);
+ bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 512, 2, false);
+ } else if (ep_idx == 2) {
+ bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 512, 2, true);
+ bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 512, 2, false);
+ } else {
+ return -1;
+ }
+ }
+#endif
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+ regval |= USB_AFT_CONF;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+ }
+ return 0;
+}
+
+int usbd_ep_close(const uint8_t ep)
+{
+ return 0;
+}
+
+int usbd_ep_set_stall(const uint8_t ep)
+{
+ uint32_t regval;
+
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (ep_idx == 0) {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+ regval |= USB_CX_STL;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+ } else {
+ if (USB_EP_DIR_IS_OUT(ep)) {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+ regval |= USB_STL_OEP1;
+ //regval |= USB_RSTG_OEP1;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+ } else {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+ regval |= USB_STL_IEP1;
+ //regval |= USB_RSTG_IEP1;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+ }
+ }
+
+ return 0;
+}
+
+int usbd_ep_clear_stall(const uint8_t ep)
+{
+ uint32_t regval;
+
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (ep_idx == 0) {
+ } else {
+ if (USB_EP_DIR_IS_OUT(ep)) {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+ //regval &= ~USB_RSTG_OEP1;
+ regval &= ~USB_STL_OEP1;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+ } else {
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+ //regval &= ~USB_RSTG_IEP1;
+ regval &= ~USB_STL_IEP1;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+ }
+ }
+
+ return 0;
+}
+
+int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
+{
+ return 0;
+}
+
+int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
+{
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (!data && data_len) {
+ return -1;
+ }
+
+ if (!g_bl_udc.in_ep[ep_idx].ep_enable) {
+ return -2;
+ }
+
+ g_bl_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
+ g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+ g_bl_udc.in_ep[ep_idx].actual_xfer_len = 0;
+ g_bl_udc.in_ep[ep_idx].ep_active = true;
+
+ if (ep_idx == 0) {
+ if (data_len == 0) {
+ g_bl_udc.in_ep[ep_idx].ep_active = false;
+ bflb_usb_control_transfer_done();
+ } else {
+ data_len = MIN(data_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+ g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+ bflb_usb_vdma_start_write(USB_FIFO_CXF, data, data_len);
+ }
+ } else {
+ if (data_len == 0) {
+ bflb_usb_send_zlp(ep_idx);
+ } else {
+ bflb_usb_vdma_start_write(usb_get_transfer_fifo(ep_idx), data, data_len);
+ }
+ }
+
+ return 0;
+}
+
+int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
+{
+ uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+ if (!data && data_len) {
+ return -1;
+ }
+
+ if (!g_bl_udc.out_ep[ep_idx].ep_enable) {
+ return -2;
+ }
+
+ g_bl_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data;
+ g_bl_udc.out_ep[ep_idx].xfer_len = data_len;
+ g_bl_udc.out_ep[ep_idx].actual_xfer_len = 0;
+ g_bl_udc.out_ep[ep_idx].ep_active = true;
+
+ if (ep_idx == 0) {
+ if (data_len == 0) {
+ g_bl_udc.out_ep[ep_idx].ep_active = false;
+ } else {
+ data_len = MIN(data_len, g_bl_udc.out_ep[ep_idx].ep_mps);
+ g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+ bflb_usb_vdma_start_read(USB_FIFO_CXF, data, data_len);
+ }
+ } else {
+ if (data_len == 0) {
+ } else {
+ bflb_usb_vdma_start_read(usb_get_transfer_fifo(ep_idx), data, data_len);
+ }
+ }
+ return 0;
+}
+
+void USBD_IRQHandler(int irq, void *arg)
+{
+ uint32_t glb_intstatus;
+ uint32_t dev_intstatus;
+ uint32_t subgroup_intstatus;
+ uint32_t regval;
+ uint8_t ep_idx;
+
+ glb_intstatus = getreg32(BLFB_USB_BASE + USB_GLB_ISR_OFFSET);
+
+ if (glb_intstatus & USB_DEV_INT) {
+ dev_intstatus = getreg32(BLFB_USB_BASE + USB_DEV_IGR_OFFSET);
+ if (dev_intstatus & USB_INT_G0) {
+ subgroup_intstatus = bflb_usb_get_source_group_intstatus(0);
+
+ if (subgroup_intstatus & USB_CX_SETUP_INT) {
+ uint32_t setup[2];
+ bflb_usb_get_setup_packet(setup);
+ usbd_event_ep0_setup_complete_handler((uint8_t *)setup);
+ }
+ }
+ if (dev_intstatus & USB_INT_G1) {
+ }
+ if (dev_intstatus & USB_INT_G2) {
+ subgroup_intstatus = bflb_usb_get_source_group_intstatus(2);
+
+ if (subgroup_intstatus & USB_SUSP_INT) {
+ bflb_usb_source_group_int_clear(2, USB_SUSP_INT);
+ usbd_event_suspend_handler();
+ }
+ if (subgroup_intstatus & USB_RESM_INT) {
+ bflb_usb_source_group_int_clear(2, USB_RESM_INT);
+ usbd_event_resume_handler();
+ }
+ if (subgroup_intstatus & USB_TX0BYTE_INT) {
+ for (uint8_t i = 1; i < 5; i++) {
+ if (bflb_usb_get_tx_zlp_intstatus() & (1 << (i - 1))) {
+ bflb_usb_clear_tx_zlp_intstatus(i);
+ usbd_event_ep_in_complete_handler(i | 0x80, 0);
+ }
+ }
+ bflb_usb_source_group_int_clear(2, USB_TX0BYTE_INT);
+ }
+ if (subgroup_intstatus & USB_RX0BYTE_INT) {
+ for (uint8_t i = 1; i < 5; i++) {
+ if (bflb_usb_get_rx_zlp_intstatus() & (1 << (i - 1))) {
+ bflb_usb_clear_rx_zlp_intstatus(i);
+ usbd_event_ep_out_complete_handler(i, 0);
+ }
+ }
+
+ bflb_usb_source_group_int_clear(2, USB_RX0BYTE_INT);
+ }
+ if (subgroup_intstatus & USBRST_INT) {
+ bflb_usb_source_group_int_clear(2, USBRST_INT);
+
+ bflb_usb_reset_fifo(USB_FIFO_F0);
+ bflb_usb_reset_fifo(USB_FIFO_F1);
+ bflb_usb_reset_fifo(USB_FIFO_F2);
+ bflb_usb_reset_fifo(USB_FIFO_F3);
+ bflb_usb_reset_fifo(USB_FIFO_CXF);
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+ regval &= ~USB_SOFMT_MASK;
+#ifdef CONFIG_USB_HS
+ regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS;
+#else
+ regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS;
+#endif
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+
+ memset(&g_bl_udc, 0, sizeof(g_bl_udc));
+
+ usbd_event_reset_handler();
+ }
+ }
+ if (dev_intstatus & USB_INT_G3) {
+ subgroup_intstatus = bflb_usb_get_source_group_intstatus(3);
+ bflb_usb_source_group_int_clear(3, subgroup_intstatus);
+ if (subgroup_intstatus & USB_VDMA_CMPLT_CXF) {
+ if (g_bl_udc.in_ep[0].ep_active) {
+ g_bl_udc.in_ep[0].ep_active = false;
+ g_bl_udc.in_ep[0].actual_xfer_len = g_bl_udc.in_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF);
+ if (g_bl_udc.in_ep[0].actual_xfer_len < g_bl_udc.in_ep[0].ep_mps) {
+ bflb_usb_control_transfer_done();
+ }
+ usbd_event_ep_in_complete_handler(0x80, g_bl_udc.in_ep[0].actual_xfer_len);
+ } else {
+ g_bl_udc.out_ep[0].ep_active = false;
+ g_bl_udc.out_ep[0].actual_xfer_len = g_bl_udc.out_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF);
+ usbd_event_ep_out_complete_handler(0x00, g_bl_udc.out_ep[0].actual_xfer_len);
+ }
+ }
+
+ for (uint8_t i = 0; i < 4; i++) {
+ if (subgroup_intstatus & (1 << (i + 1))) {
+ ep_idx = bflb_usb_get_fifo_ep(i);
+ if (g_bl_udc.in_ep[ep_idx].ep_active) {
+ g_bl_udc.in_ep[ep_idx].ep_active = 0;
+ g_bl_udc.in_ep[ep_idx].actual_xfer_len = g_bl_udc.in_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i);
+ usbd_event_ep_in_complete_handler(ep_idx | 0x80, g_bl_udc.in_ep[ep_idx].actual_xfer_len);
+ } else {
+ g_bl_udc.out_ep[ep_idx].ep_active = 0;
+ g_bl_udc.out_ep[ep_idx].actual_xfer_len = g_bl_udc.out_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i);
+ usbd_event_ep_out_complete_handler(ep_idx & 0x7f, g_bl_udc.out_ep[ep_idx].actual_xfer_len);
+ }
+ }
+ }
+ }
+ if (dev_intstatus & USB_INT_G4) {
+ }
+ }
+}
+
+#ifdef CONFIG_USBDEV_TEST_MODE
+void usbd_execute_test_mode(struct usb_setup_packet *setup)
+{
+ uint32_t regval;
+ uint8_t index = setup->wIndex >> 8;
+
+ switch (index) {
+ case 1: // Test_J
+ {
+ regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+ regval |= USB_TST_JSTA;
+ putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+ bflb_usb_control_transfer_done();
+ } break;
+ case 2: // Test_K
+ {
+ regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+ regval |= USB_TST_KSTA;
+ putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+ bflb_usb_control_transfer_done();
+ } break;
+ case 3: // TEST_SE0_NAK
+ {
+ regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+ regval |= USB_TST_SE0NAK;
+ putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+ bflb_usb_control_transfer_done();
+ } break;
+ case 4: // Test_Packet
+ {
+ bflb_usb_control_transfer_done();
+ regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+ regval |= USB_TST_PKT;
+ putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+ __attribute__((aligned(32))) uint8_t temp[53];
+ uint8_t *pp;
+ uint8_t i;
+ pp = temp;
+
+ for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/
+ *pp++ = 0x00;
+
+ for (i = 0; i < 8; i++) /* 8*AA */
+ *pp++ = 0xAA;
+
+ for (i = 0; i < 8; i++) /* 8*EE */
+ *pp++ = 0xEE;
+
+ *pp++ = 0xFE;
+
+ for (i = 0; i < 11; i++) /* 11*FF */
+ *pp++ = 0xFF;
+
+ *pp++ = 0x7F;
+ *pp++ = 0xBF;
+ *pp++ = 0xDF;
+ *pp++ = 0xEF;
+ *pp++ = 0xF7;
+ *pp++ = 0xFB;
+ *pp++ = 0xFD;
+ *pp++ = 0xFC;
+ *pp++ = 0x7E;
+ *pp++ = 0xBF;
+ *pp++ = 0xDF;
+ *pp++ = 0xEF;
+ *pp++ = 0xF7;
+ *pp++ = 0xFB;
+ *pp++ = 0xFD;
+ *pp++ = 0x7E;
+
+ bflb_usb_vdma_start_write(USB_FIFO_CXF, temp, 53);
+
+ regval = getreg32(BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+ regval |= USB_TST_PKDONE;
+ putreg32(regval, BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+
+ } break;
+ case 5: // Test_Force_Enable
+ break;
+
+ default:
+ break;
+ }
+}
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/bflb_wdg.c b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_wdg.c
new file mode 100644
index 00000000..e6905728
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/bflb_wdg.c
@@ -0,0 +1,119 @@
+#include "bflb_wdg.h"
+#include "bflb_clock.h"
+#include "hardware/timer_reg.h"
+
+void bflb_wdg_init(struct bflb_device_s *dev, const struct bflb_wdg_config_s *config)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+ putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+ regval = getreg32(reg_base + TIMER_WMER_OFFSET);
+ regval &= ~TIMER_WE;
+ if (config->mode == WDG_MODE_INTERRUPT) {
+ regval &= ~TIMER_WRIE;
+ } else {
+ regval |= TIMER_WRIE;
+ }
+ putreg32(regval, reg_base + TIMER_WMER_OFFSET);
+
+ /* Configure clock source */
+ regval = getreg32(reg_base + TIMER_TCCR_OFFSET);
+ regval &= ~TIMER_CS_WDT_MASK;
+ regval |= (config->clock_source << TIMER_CS_WDT_SHIFT);
+ putreg32(regval, reg_base + TIMER_TCCR_OFFSET);
+
+ /* Configure clock div */
+ regval = getreg32(reg_base + TIMER_TCDR_OFFSET);
+ regval &= ~TIMER_WCDR_MASK;
+ regval |= (config->clock_div << TIMER_WCDR_SHIFT);
+ putreg32(regval, reg_base + TIMER_TCDR_OFFSET);
+
+ putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+ putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+ putreg16(config->comp_val, reg_base + TIMER_WMR_OFFSET);
+}
+
+void bflb_wdg_start(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+ putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+ regval = getreg32(reg_base + TIMER_WMER_OFFSET);
+ regval |= TIMER_WE;
+ putreg32(regval, reg_base + TIMER_WMER_OFFSET);
+}
+
+void bflb_wdg_stop(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+ putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+ regval = getreg32(reg_base + TIMER_WMER_OFFSET);
+ regval &= ~TIMER_WE;
+ putreg32(regval, reg_base + TIMER_WMER_OFFSET);
+}
+
+uint16_t bflb_wdg_get_countervalue(struct bflb_device_s *dev)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ return getreg16(reg_base + TIMER_WVR_OFFSET);
+}
+
+void bflb_wdg_set_countervalue(struct bflb_device_s *dev, uint16_t value)
+{
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+ putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+ putreg16(value, reg_base + TIMER_WMR_OFFSET);
+}
+
+void bflb_wdg_reset_countervalue(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+ putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+ regval = getreg32(reg_base + TIMER_WCR_OFFSET);
+ regval |= TIMER_WCR;
+ putreg32(regval, reg_base + TIMER_WCR_OFFSET);
+}
+
+void bflb_wdg_compint_clear(struct bflb_device_s *dev)
+{
+ uint32_t regval;
+ uint32_t reg_base;
+
+ reg_base = dev->reg_base;
+
+ putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+ putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+ regval = getreg32(reg_base + TIMER_WICR_OFFSET);
+ regval |= TIMER_WICLR;
+ putreg32(regval, reg_base + TIMER_WICR_OFFSET);
+}
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_cfg.c b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_cfg.c
new file mode 100644
index 00000000..994528d1
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_cfg.c
@@ -0,0 +1,3703 @@
+/**
+ ******************************************************************************
+ * @file bflb_sf_cfg.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
+#include "bflb_xip_sflash.h"
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SF_CFG
+ * @{
+ */
+
+/** @defgroup SF_CFG_Private_Macros
+ * @{
+ */
+#define BFLB_FLASH_CFG_MAGIC "FCFG"
+
+/*@} end of group SF_CFG_Private_Macros */
+
+/** @defgroup SF_CFG_Private_Types
+ * @{
+ */
+typedef struct
+{
+ uint32_t jedec_id;
+ char *name;
+ const spi_flash_cfg_type *cfg;
+}flash_info_t;
+
+/*@} end of group SF_CFG_Private_Types */
+
+/** @defgroup SF_CFG_Private_Variables
+ * @{
+ */
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_80dv = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xef,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 0,
+ .c_read_mode = 0xFF,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3d,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 3,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_16jv = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xef,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3d,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 3,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_80ew_16fw_32jw_32fw_32fv = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xef,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xa0,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 400,
+ .time_e_32k = 1600,
+ .time_e_64k = 2000,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 3,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_128jw_128jv = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xef,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 0,
+ .c_read_mode = 0xFF,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 400,
+ .time_e_32k = 1600,
+ .time_e_64k = 2000,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 3,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_issi = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x9d,
+
+ .de_burst_wrap_cmd = 0xC0,
+ .de_burst_wrap_cmd_dmy_clk = 0x00,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .de_burst_wrap_data = 0x00,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0,
+ .qe_bit = 0x06,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xA0,
+
+ .burst_wrap_cmd = 0xC0,
+ .burst_wrap_cmd_dmy_clk = 0x00,
+ .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .burst_wrap_data = 0x06,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 5,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_md_40d = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x51,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 0,
+ .c_read_mode = 0xA0,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_DO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_lq08c_le16c_lq32d_wq32e = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc8,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_q80e_q16e = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc8,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xA0,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_wq80e_wq16e = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc8,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 32 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xA0,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 8 / 8,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0x12,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_q32e_q128e = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc8,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xC2,
+
+ .de_burst_wrap_cmd = 0xC0,
+ .de_burst_wrap_cmd_dmy_clk = 0x00,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .de_burst_wrap_data = 0x10,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0,
+ .qe_bit = 0x06,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xA5,
+
+ .burst_wrap_cmd = 0xC0,
+ .burst_wrap_cmd_dmy_clk = 0x00,
+ .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .burst_wrap_data = 0x02,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x38,
+ .qpp_addr_mode = SF_CTRL_ADDR_4_LINES,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 45,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic_1635f = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xC2,
+
+ .de_burst_wrap_cmd = 0xC0,
+ .de_burst_wrap_cmd_dmy_clk = 0x00,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .de_burst_wrap_data = 0x10,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0,
+ .qe_bit = 0x06,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xA5,
+
+ .burst_wrap_cmd = 0xC0,
+ .burst_wrap_cmd_dmy_clk = 0x00,
+ .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .burst_wrap_data = 0x02,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x38,
+ .qpp_addr_mode = SF_CTRL_ADDR_4_LINES,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 45,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic_25l256 = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc2,
+
+ .de_burst_wrap_cmd = 0xC0,
+ .de_burst_wrap_cmd_dmy_clk = 0x00,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .de_burst_wrap_data = 0x10,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0,
+ .qe_bit = 0x06,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x15,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xA5,
+
+ .burst_wrap_cmd = 0xC0,
+ .burst_wrap_cmd_dmy_clk = 0x00,
+ .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+ .burst_wrap_data = 0x02,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x38,
+ .qpp_addr_mode = SF_CTRL_ADDR_4_LINES,
+
+ .io_mode = (SF_CTRL_QIO_MODE | 0x20),
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 400,
+ .time_e_32k = 1000,
+ .time_e_64k = 2000,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_xtx = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x0B,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0x01,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 6000,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_puya_q80l_q80h_q16h = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x85,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0x01,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3d,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 8,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_puya_q32h = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x85,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0x01,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 8,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_boya40 = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x68,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 0,
+ .c_read_mode = 0xA0,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_DO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_boya = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x68,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0x01,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = SF_CTRL_QIO_MODE,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mx_kh25 = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xc2,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x00,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x00,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 0,
+ .c_read_mode = 0x20,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = (SF_CTRL_DO_MODE | 0x10),
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 20 * 1000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_256fv= {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0xef,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 1,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x01,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x31,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xa0,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = 0x24,
+ .clk_delay = 1,
+ .clk_invert = 0x3f,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 400,
+ .time_e_32k = 1600,
+ .time_e_64k = 2000,
+ .time_page_pgm = 5,
+ .time_ce = 33 * 1000,
+ .pd_delay = 3,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_xtx_q80b_f16b = {
+ .reset_c_read_cmd = 0xff,
+ .reset_c_read_cmd_size = 3,
+ .mid = 0x85,
+
+ .de_burst_wrap_cmd = 0x77,
+ .de_burst_wrap_cmd_dmy_clk = 0x3,
+ .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .de_burst_wrap_data = 0xF0,
+
+ /*reg*/
+ .write_enable_cmd = 0x06,
+ .wr_enable_index = 0x00,
+ .wr_enable_bit = 0x01,
+ .wr_enable_read_reg_len = 0x01,
+
+ .qe_index = 0x01,
+ .qe_bit = 0x01,
+ .qe_write_reg_len = 0x02,
+ .qe_read_reg_len = 0x1,
+
+ .busy_index = 0,
+ .busy_bit = 0x00,
+ .busy_read_reg_len = 0x1,
+ .release_powerdown = 0xab,
+
+ .read_reg_cmd[0] = 0x05,
+ .read_reg_cmd[1] = 0x35,
+ .write_reg_cmd[0] = 0x01,
+ .write_reg_cmd[1] = 0x01,
+
+ .fast_read_qio_cmd = 0xeb,
+ .fr_qio_dmy_clk = 16 / 8,
+ .c_read_support = 1,
+ .c_read_mode = 0xa0,
+
+ .burst_wrap_cmd = 0x77,
+ .burst_wrap_cmd_dmy_clk = 0x3,
+ .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+ .burst_wrap_data = 0x40,
+ /*erase*/
+ .chip_erase_cmd = 0xc7,
+ .sector_erase_cmd = 0x20,
+ .blk32_erase_cmd = 0x52,
+ .blk64_erase_cmd = 0xd8,
+ /*write*/
+ .page_program_cmd = 0x02,
+ .qpage_program_cmd = 0x32,
+ .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+ .io_mode = 0x14,
+ .clk_delay = 1,
+ .clk_invert = 0x01,
+
+ .reset_en_cmd = 0x66,
+ .reset_cmd = 0x99,
+ .c_rexit = 0xff,
+ .wr_enable_write_reg_len = 0x00,
+ /*id*/
+ .jedec_id_cmd = 0x9f,
+ .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ .qpi_jedec_id_cmd = 0x9f,
+ .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+ .enter_32bits_addr_cmd = 0xb7,
+ .exit_32bits_addr_cmd = 0xe9,
+#endif
+ .sector_size = 4,
+ .page_size = 256,
+
+ /*read*/
+ .fast_read_cmd = 0x0b,
+ .fr_dmy_clk = 8 / 8,
+ .qpi_fast_read_cmd = 0x0b,
+ .qpi_fr_dmy_clk = 8 / 8,
+ .fast_read_do_cmd = 0x3b,
+ .fr_do_dmy_clk = 8 / 8,
+ .fast_read_dio_cmd = 0xbb,
+ .fr_dio_dmy_clk = 0,
+ .fast_read_qo_cmd = 0x6b,
+ .fr_qo_dmy_clk = 8 / 8,
+
+ .qpi_fast_read_qio_cmd = 0xeb,
+ .qpi_fr_qio_dmy_clk = 16 / 8,
+ .qpi_page_program_cmd = 0x02,
+ .write_vreg_enable_cmd = 0x50,
+
+ /* qpi mode */
+ .enter_qpi = 0x38,
+ .exit_qpi = 0xff,
+
+ /*AC*/
+ .time_e_sector = 300,
+ .time_e_32k = 1200,
+ .time_e_64k = 1200,
+ .time_page_pgm = 5,
+ .time_ce = 33000,
+ .pd_delay = 20,
+ .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[] = {
+ {
+ .jedec_id = 0x1440ef,
+ //.name="winb_80dv_08_33",
+ .cfg = &flash_cfg_winb_80dv,
+ },
+ {
+ .jedec_id = 0x1540ef,
+ //.name="winb_16dv_16_33",
+ .cfg = &flash_cfg_winb_16jv,
+ },
+ {
+ .jedec_id = 0x1570ef,
+ //.name="wb_16jv_16_33",
+ .cfg = &flash_cfg_winb_16jv,
+ },
+ {
+ .jedec_id = 0x1640ef,
+ //.name="winb_32fv_32_33",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x1740ef,
+ //.name="wb_64jv_64_33",
+ .cfg = &flash_cfg_winb_128jw_128jv,
+ },
+ {
+ .jedec_id = 0x1840ef,
+ //.name="winb_128jv_128_33",
+ .cfg = &flash_cfg_winb_128jw_128jv,
+ },
+ {
+ .jedec_id = 0x1870ef,
+ //.name="winb_128jv_128_33",
+ .cfg = &flash_cfg_winb_128jw_128jv,
+ },
+ {
+ .jedec_id = 0x1940ef,
+ //.name="wb_256fv_256_33",
+ .cfg = &flash_cfg_winb_256fv,
+ },
+ {
+ .jedec_id = 0x1460ef,
+ //.name="winb_80ew_08_18",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x1560ef,
+ //.name="winb_16fw_16_18",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x1660ef,
+ //.name="winb_32fw_32_18",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x1760ef,
+ //.name="wb_64jw_64_18",
+ .cfg = &flash_cfg_winb_128jw_128jv,
+ },
+ {
+ .jedec_id = 0x1860ef,
+ //.name="winb_128jw_128_18",
+ .cfg = &flash_cfg_winb_128jw_128jv,
+ },
+ {
+ .jedec_id = 0x1680ef,
+ //.name="winb_32jw_32_18",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x1880ef,
+ //.name="winb_128jw_128_18",
+ .cfg = &flash_cfg_winb_128jw_128jv,
+ },
+ {
+ .jedec_id = 0x134051,
+ //.name="gd_md04d_04_33",
+ .cfg = &flash_cfg_gd_md_40d,
+ },
+ {
+ .jedec_id = 0x1440c8,
+ //.name="gd_q08e_08_33",
+ .cfg = &flash_cfg_gd_q80e_q16e,
+ },
+ {
+ .jedec_id = 0x1540c8,
+ //.name="gd_q16e_16_33",
+ .cfg = &flash_cfg_gd_q80e_q16e,
+ },
+ {
+ .jedec_id = 0x1640c8,
+ //.name="gd_q32c_32_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x1740c8,
+ //.name="gd_64e_64_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x1840c8,
+ //.name="gd_q128e_128_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x1460c8,
+ //.name="gd_lq08c_08_18",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x1560c8,
+ //.name="gd_le16c_16_18",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x1660c8,
+ //.name="gd_lq32d_32_18",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x1760c8,
+ //.name="gd_lq64e_64_18",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x1860c8,
+ //.name="gd_lq128e_128_18",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x1465c8,
+ //.name="gd_wq80e_80_33",
+ .cfg = &flash_cfg_gd_wq80e_wq16e,
+ },
+ {
+ .jedec_id = 0x1565c8,
+ //.name="gd_wq16e_16_33",
+ .cfg = &flash_cfg_gd_wq80e_wq16e,
+ },
+ {
+ .jedec_id = 0x1665c8,
+ //.name="gd_wq32e_32_33",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x1320c2,
+ //.name="mx_kh40_04_33",
+ .cfg = &flash_cfg_mx_kh25,
+ },
+ {
+ .jedec_id = 0x1420c2,
+ //.name="mx_kh80_08_33",
+ .cfg = &flash_cfg_mx_kh25,
+ },
+ {
+ .jedec_id = 0x1520c2,
+ //.name="mx_kh16_16_33",
+ .cfg = &flash_cfg_mx_kh25,
+ },
+ {
+ .jedec_id = 0x3425c2,
+ //.name="mx_25v80_08_18",
+ .cfg = &flash_cfg_mxic,
+ },
+ {
+ .jedec_id = 0x3525c2,
+ //.name="mx_25u16_35_18",
+ .cfg = &flash_cfg_mxic_1635f,
+ },
+ {
+ .jedec_id = 0x3625c2,
+ //.name="mx_25v32_32_18",
+ .cfg = &flash_cfg_mxic,
+ },
+ {
+ .jedec_id = 0x3925c2,
+ //.name="mx_u25643g_256_18",
+ .cfg = &flash_cfg_mxic_25l256,
+ },
+ {
+ .jedec_id = 0x1820c2,
+ //.name="mx_25l128_128_33",
+ .cfg = &flash_cfg_mxic_1635f,
+ },
+ {
+ .jedec_id = 0x1920c2,
+ //.name="mx_25l256_256_33",
+ .cfg = &flash_cfg_mxic_25l256,
+ },
+ {
+ .jedec_id = 0x13400b,
+ //.name="xt_25f04d_04_33",
+ .cfg = &flash_cfg_xtx,
+ },
+ {
+ .jedec_id = 0x15400b,
+ //.name="xt_25f16b_16_33",
+ .cfg = &flashcfg_xtx_q80b_f16b,
+ },
+ {
+ .jedec_id = 0x16400b,
+ //.name="xt_25f32b_32_33",
+ .cfg = &flash_cfg_xtx,
+ },
+ {
+ .jedec_id = 0x17400b,
+ //.name="xt_f64b_64_33",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x18400b,
+ //.name="xt_25f128b_128_33",
+ .cfg = &flash_cfg_xtx,
+ },
+ {
+ .jedec_id = 0x14600b,
+ //.name="xt_25q80b_08_18",
+ .cfg = &flashcfg_xtx_q80b_f16b,
+ },
+ {
+ .jedec_id = 0x16600b,
+ //.name="xt_25q32b_32_18",
+ .cfg = &flash_cfg_xtx,
+ },
+ {
+ .jedec_id = 0x134068,
+ //.name="boya_q04b_04_33",
+ .cfg = &flash_cfg_boya40,
+ },
+ {
+ .jedec_id = 0x144068,
+ //.name="boya_q08b_08_33",
+ .cfg = &flash_cfg_boya,
+ },
+ {
+ .jedec_id = 0x154068,
+ //.name="boya_q16b_16_33",
+ .cfg = &flash_cfg_boya,
+ },
+ {
+ .jedec_id = 0x164068,
+ //.name="boya_q32b_32_33",
+ .cfg = &flash_cfg_boya,
+ },
+ {
+ .jedec_id = 0x174068,
+ //.name="boya_q64a_64_33",
+ .cfg = &flash_cfg_boya,
+ },
+ {
+ .jedec_id = 0x184068,
+ //.name="boya_q128a_128_33",
+ .cfg = &flash_cfg_boya,
+ },
+ {
+ .jedec_id = 0x13325e,
+ //.name="zbit_04_33",
+ .cfg = &flash_cfg_mx_kh25,
+ },
+ {
+ .jedec_id = 0x14325e,
+ //.name="zbit_08_33",
+ .cfg = &flash_cfg_mx_kh25,
+ },
+ {
+ .jedec_id = 0x15345e,
+ //.name="zb_wq16a_16_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x13605e,
+ //.name="zbit_04_33",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x14605e,
+ //.name="zbit_08_33",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x15605e,
+ //.name="zb_vq16_16_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x15405e,
+ //.name="zb_16b_16_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x16405e,
+ //.name="zb_32b_32_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x17405e,
+ //.name="zb_vq64_64_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x18405e,
+ //.name="zb_vq128_128_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x144020,
+ //.name="xm_qh80_08_33",
+ .cfg = &flash_cfg_winb_16jv,
+ },
+ {
+ .jedec_id = 0x154020,
+ //.name="xm_qh16_16_33",
+ .cfg = &flash_cfg_winb_16jv,
+ },
+ {
+ .jedec_id = 0x164020,
+ //.name="xm_qh32_32_33",
+ .cfg = &flash_cfg_winb_16jv,
+ },
+ {
+ .jedec_id = 0x174020,
+ //.name="xm_qh64_64_33",
+ .cfg = &flash_cfg_winb_16jv,
+ },
+ {
+ .jedec_id = 0x184020,
+ //.name="xm_qh128_128_33",
+ .cfg = &flash_cfg_gd_q32e_q128e,
+ },
+ {
+ .jedec_id = 0x174220,
+ //.name="xm_qw64_64_1833",
+ .cfg = &flash_cfg_winb_16jv,
+ },
+ {
+ .jedec_id = 0x1440a1,
+ //.name="fm25q80_80_33",
+ .cfg = &flash_cfg_gd_q80e_q16e,
+ },
+ {
+ .jedec_id = 0x1740a1,
+ //.name="fm25q64_64_33",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x1840a1,
+ //.name="fm25q128_128_33",
+ .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+ },
+ {
+ .jedec_id = 0x146085,
+ //.name="puya_q80l/h_08_18/33",
+ .cfg = &flash_cfg_puya_q80l_q80h_q16h,
+ },
+ {
+ .jedec_id = 0x156085,
+ //.name="puya_q16h_16_33",
+ .cfg = &flash_cfg_puya_q80l_q80h_q16h,
+ },
+ {
+ .jedec_id = 0x166085,
+ //.name="puya_q32h_32_33",
+ .cfg = &flash_cfg_puya_q32h,
+ },
+ {
+ .jedec_id = 0x176085,
+ //.name="puya_q64h_64_33",
+ .cfg = &flash_cfg_puya_q32h,
+ },
+ {
+ .jedec_id = 0x186085,
+ //.name="puya_q128h_128_33",
+ .cfg = &flash_cfg_puya_q32h,
+ },
+ {
+ .jedec_id = 0x14609d,
+ //.name="issi_08_33",
+ .cfg = &flash_cfg_issi,
+ },
+ {
+ .jedec_id = 0x15609d,
+ //.name="issi_16_33",
+ .cfg = &flash_cfg_issi,
+ },
+ {
+ .jedec_id = 0x16609d,
+ //.name="issi_32_33",
+ .cfg = &flash_cfg_issi,
+ },
+ {
+ .jedec_id = 0x14709d,
+ //.name="issi_08_18",
+ .cfg = &flash_cfg_issi,
+ },
+ {
+ .jedec_id = 0x15709d,
+ //.name="issi_16_18",
+ .cfg = &flash_cfg_issi,
+ },
+ {
+ .jedec_id = 0x16709d,
+ //.name="issi_32_18",
+ .cfg = &flash_cfg_issi,
+ },
+ {
+ .jedec_id = 0x1460cd,
+ //.name="th25q80_80_33",
+ .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+ },
+ {
+ .jedec_id = 0x1560eb,
+ //.name="th25q16_16_33",
+ .cfg = &flash_cfg_gd_q80e_q16e,
+ },
+ {
+ .jedec_id = 0x1560ba,
+ //.name="zd25a16_16_33",
+ .cfg = &flashcfg_xtx_q80b_f16b,
+ },
+};
+
+/*@} end of group SF_CFG_Private_Variables */
+
+/** @defgroup SF_CFG_Global_Variables
+ * @{
+ */
+
+/*@} end of group SF_CFG_Global_Variables */
+
+/** @defgroup SF_CFG_Private_Fun_Declaration
+ * @{
+ */
+
+#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)\
+ || defined(BL602) || defined(BL702) || defined(BL702L)
+/**
+ * @brief Error type definition
+ */
+typedef enum {
+ SUCCESS = 0,
+ ERROR = 1,
+ TIMEOUT = 2,
+ INVALID = 3, /* invalid arguments */
+ NORESC = 4 /* no resource or resource temperary unavailable */
+} BL_Err_Type;
+#endif
+#if defined(BL808) || defined(BL606P)
+extern BL_Err_Type GLB_Set_Flash_IO_PARM(uint8_t sel_embedded, uint8_t swap);
+#elif defined(BL616)
+extern BL_Err_Type GLB_Set_SFlash_IO_PARM(uint8_t sel_embedded, uint8_t swapIo3Io0, uint8_t swapIo2Cs);
+extern BL_Err_Type GLB_Set_SFlash2_IO_PARM(uint8_t swapIo3Io0);
+#elif defined(BL702L)
+extern BL_Err_Type GLB_Set_Embedded_FLash_IO_PARM(uint8_t reverse, uint8_t swapIo3Io0, uint8_t swapIo2Cs);
+#elif defined(BL628)
+extern void bflb_glb_set_sflash_io_parm(uint8_t sel_embedded, uint8_t swap_io3_io0, uint8_t swap_io2_cs);
+extern void bflb_glb_set_sflash2_io_parm(uint8_t swap_io3_io0);
+#elif defined(BL602)
+extern BL_Err_Type GLB_Select_Internal_Flash(void);
+extern BL_Err_Type GLB_Select_External_Flash(void);
+extern BL_Err_Type GLB_Deswap_Flash_Pin(void);
+extern BL_Err_Type GLB_Swap_Flash_Pin(void);
+#endif
+
+/*@} end of group SF_CFG_Private_Fun_Declaration */
+
+/** @defgroup SF_CFG_Private_Functions
+ * @{
+ */
+
+#if defined(BL702L)
+/****************************************************************************/ /**
+ * @brief Embedded flash set input function enable
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void)
+{
+#define GLB_BASE_ADDR 0x40000000
+#define GLB_GPIO_OFFSET_ADDR 0x100
+ uint32_t regval;
+ uint32_t gpio_pin;
+ uint32_t pin_offset;
+
+ for (gpio_pin = 32; gpio_pin < 38; gpio_pin++) {
+ pin_offset = (gpio_pin >> 1) << 2;
+ regval = *(uint32_t *)(GLB_BASE_ADDR + GLB_GPIO_OFFSET_ADDR + pin_offset);
+ if (gpio_pin % 2 == 0) {
+ /* [0] is ie */
+ regval |= (1 << 0);
+ } else {
+ /* [16] is ie */
+ regval |= (1 << 16);
+ }
+ *(uint32_t *)(GLB_BASE_ADDR + GLB_GPIO_OFFSET_ADDR + pin_offset) = regval;
+ }
+}
+#elif defined(BL702) || defined(BL602)
+/****************************************************************************/ /**
+ * @brief Init internal flash GPIO
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void)
+{
+ struct bflb_device_s *gpio;
+ uint8_t gpio_pins[6];
+ uint8_t i = 0;
+
+ gpio = bflb_device_get_by_name("gpio");
+ for (i = 0; i < sizeof(gpio_pins); i++) {
+ gpio_pins[i] = 23+i;
+ bflb_gpio_init(gpio, gpio_pins[i],
+ BFLB_GPIO_FUNC_SF | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+ }
+}
+#endif
+
+#if defined(BL602)
+/****************************************************************************/ /**
+ * @brief Restore GPIO17 function
+ *
+ * @param fun: GPIO17 function
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_cfg_restore_gpio17_fun(uint8_t fun)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, GPIO_PIN_17,
+ fun | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Init external flash GPIO according to flash GPIO config
+ *
+ * @param ext_flash_pin: Flash GPIO config
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+ struct bflb_device_s *gpio;
+ uint8_t gpio_pins[6];
+ uint8_t i = 0;
+
+ gpio = bflb_device_get_by_name("gpio");
+ if (ext_flash_pin == 0) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK0_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS0_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA00_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA10_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA20_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA30_GPIO;
+#if defined(BL628) || defined(BL616)
+ } else if (ext_flash_pin == 1) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#elif defined(BL702)
+ } else if (ext_flash_pin == 1) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+ } else if (ext_flash_pin == 2) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK2_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS2_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA02_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA12_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA22_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA32_GPIO;
+#elif defined(BL602)
+ } else if (ext_flash_pin == 1) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#endif
+ } else {
+ return -1;
+ }
+
+ for (i = 0; i < sizeof(gpio_pins); i++) {
+ bflb_gpio_init(gpio, gpio_pins[i],
+ BFLB_GPIO_FUNC_SF | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Deinit external flash GPIO according to flash GPIO config
+ *
+ * @param ext_flash_pin: Flash GPIO config
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+ struct bflb_device_s *gpio;
+ uint8_t gpio_pins[6];
+ uint8_t i = 0;
+
+ gpio = bflb_device_get_by_name("gpio");
+ if (ext_flash_pin == 0) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK0_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS0_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA00_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA10_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA20_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA30_GPIO;
+#if defined(BL628) || defined(BL616)
+ } else if (ext_flash_pin == 1) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#elif defined(BL702)
+ } else if (ext_flash_pin == 1) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+ } else if (ext_flash_pin == 2) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK2_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS2_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA02_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA12_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA22_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA32_GPIO;
+#elif defined(BL602)
+ } else if (ext_flash_pin == 1) {
+ gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+ gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+ gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+ gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+ gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+ gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#endif
+ } else {
+ return -1;
+ }
+
+ for (i = 0; i < sizeof(gpio_pins); i++) {
+ bflb_gpio_init(gpio, gpio_pins[i], GPIO_INPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ }
+
+ return 0;
+}
+
+/*@} end of group SF_CFG_Private_Functions */
+
+/** @defgroup SF_CFG_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Get flash config according to flash ID
+ *
+ * @param flash_id: Flash ID
+ * @param p_flash_cfg: Flash config pointer
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+ uint8_t group, uint8_t bank)
+{
+ uint32_t i = 0;
+ uint8_t buf[sizeof(spi_flash_cfg_type) + 8];
+ uint32_t crc = 0, *p_crc;
+ uint32_t xip_offset = 0;
+
+ if (flash_id == 0) {
+ xip_offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+ bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+ bflb_xip_sflash_read_via_cache_need_lock(8 + BFLB_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank);
+ bflb_sf_ctrl_set_flash_image_offset(xip_offset, group, bank);
+
+ if (arch_memcmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) {
+ crc = bflb_soft_crc32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+ p_crc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type));
+
+ if (*p_crc == crc) {
+ arch_memcpy_fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+ return 0;
+ }
+ }
+ } else {
+ for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+ if (flash_infos[i].jedec_id == flash_id) {
+ arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+ return 0;
+ }
+ }
+ }
+
+ return -1;
+}
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL702L)
+/****************************************************************************/ /**
+ * @brief Get flash config according to flash ID patch
+ *
+ * @param flash_id: Flash ID
+ * @param p_flash_cfg: Flash config pointer
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+ uint8_t group, uint8_t bank)
+{
+ return bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Init flash GPIO according to flash Pin config
+ *
+ * @param flash_pin_cfg: Specify flash Pin config
+ * @param restore_default: Wether to restore default setting
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+#if defined(BL628) || defined(BL616)
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+ uint8_t sel_embedded = 0;
+ uint8_t swap_io2_cs = 0;
+ uint8_t swap_io3_io0 = 0;
+
+ if (restore_default) {
+ /* Set Default first */
+#if defined(BL628)
+ bflb_glb_set_sflash_io_parm(1, 1, 0);
+#else
+ GLB_Set_SFlash_IO_PARM(1, 1, 0);
+#endif
+ bflb_sf_ctrl_select_pad(SF_IO_EMB_SWAP_IO3IO0);
+
+ /* Default is set, so return */
+ if (flash_pin_cfg == SF_IO_EMB_SWAP_IO3IO0) {
+ return 0;
+ }
+ }
+
+ if (flash_pin_cfg & (1 << 2)) {
+ /* Init sf2 gpio */
+ bflb_sf_cfg_init_flash2_gpio(!((flash_pin_cfg >> 5) & 1));
+ sel_embedded = 0;
+ } else if (flash_pin_cfg & (1 << 3)) {
+ /* Init sf3 gpio */
+ bflb_sf_cfg_init_ext_flash_gpio(1);
+ sel_embedded = 0;
+ } else {
+ sel_embedded = 1;
+ }
+ /* if pin select dual flash, embedded is default */
+ if ((flash_pin_cfg & (1 << 4))) {
+ sel_embedded = 1;
+ }
+
+ swap_io3_io0 = ((flash_pin_cfg >> 1) & 1);
+ swap_io3_io0 = (!swap_io3_io0);
+ swap_io2_cs = ((flash_pin_cfg >> 0) & 1);
+#if defined(BL628)
+ bflb_glb_set_sflash_io_parm(sel_embedded, swap_io3_io0, swap_io2_cs);
+#else
+ GLB_Set_SFlash_IO_PARM(sel_embedded, swap_io3_io0, swap_io2_cs);
+#endif
+ bflb_sf_ctrl_select_pad(flash_pin_cfg);
+
+ return 0;
+}
+#elif defined(BL808) || defined(BL606P)
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+ uint8_t sel_embedded = 0;
+ uint8_t swap = 0;
+
+ if ((flash_pin_cfg&(1<<3)) > 0) {
+ return ERROR;
+ }
+
+ if (restore_default) {
+ /* Set Default first */
+ GLB_Set_Flash_IO_PARM(1, 1);
+ bflb_sf_ctrl_select_pad(SF_IO_EMB_SWAP_IO0_IO3);
+
+ /* Default is set, so return */
+ if (flash_pin_cfg == SF_IO_EMB_SWAP_IO0_IO3) {
+ return SUCCESS;
+ }
+ }
+
+ if (flash_pin_cfg & (1 << 2)) {
+ /* Init sf2 gpio */
+ bflb_sf_cfg_init_ext_flash_gpio(0);
+ sel_embedded = 0;
+ } else {
+ sel_embedded = 1;
+ }
+ /* if pin select dual flash, embedded is default */
+ if ((flash_pin_cfg & (1 << 4))) {
+ sel_embedded = 1;
+ }
+
+ swap = ((flash_pin_cfg >> 1) & 1);
+ swap = (!swap);
+ GLB_Set_Flash_IO_PARM(sel_embedded, swap);
+ bflb_sf_ctrl_select_pad(flash_pin_cfg);
+
+ return SUCCESS;
+}
+#elif defined(BL702L)
+/****************************************************************************/ /**
+ * @brief Init flash GPIO according to flash Pin config
+ *
+ * @param flash_pin_cfg: Specify flash Pin config
+ * @param restore_default: Wether to restore default setting
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+ if (restore_default) {
+ GLB_Set_Embedded_FLash_IO_PARM(0, 0, 0);
+
+ bflb_sf_cfg_init_internal_flash_gpio();
+ bflb_sf_ctrl_select_pad(SF_CTRL_PAD1);
+
+ /* Default is set, so return */
+ if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) {
+ return 0;
+ }
+ }
+
+ if (flash_pin_cfg == SF_CTRL_SEL_EXTERNAL_FLASH) {
+ bflb_sf_cfg_init_ext_flash_gpio(0);
+ bflb_sf_ctrl_select_pad(SF_CTRL_PAD2);
+ } else {
+ if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) {
+ GLB_Set_Embedded_FLash_IO_PARM(0, 0, 0);
+ } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) {
+ GLB_Set_Embedded_FLash_IO_PARM(0, 0, 1);
+ } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) {
+ GLB_Set_Embedded_FLash_IO_PARM(0, 1, 0);
+ } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) {
+ GLB_Set_Embedded_FLash_IO_PARM(0, 1, 1);
+ } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) {
+ GLB_Set_Embedded_FLash_IO_PARM(1, 0, 0);
+ } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) {
+ GLB_Set_Embedded_FLash_IO_PARM(1, 0, 1);
+ } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) {
+ GLB_Set_Embedded_FLash_IO_PARM(1, 1, 0);
+ } else {
+ GLB_Set_Embedded_FLash_IO_PARM(1, 1, 1);
+ }
+
+ bflb_sf_cfg_init_internal_flash_gpio();
+ bflb_sf_ctrl_select_pad(SF_CTRL_PAD1);
+ }
+
+ return 0;
+}
+#elif defined(BL702)
+/****************************************************************************/ /**
+ * @brief Init flash GPIO according to flash Pin config
+ *
+ * @param flash_pin_cfg: Specify flash Pin config
+ * @param restore_default: Wether to restore default setting
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+#define GLB_BASE_ADDR 0x40000000
+#define GLB_PARM_OFFSET_ADDR 0x80
+#define GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR 0x88
+ uint8_t flash_cfg;
+ uint8_t swap_cfg;
+ uint32_t regval;
+
+ flash_cfg = (flash_pin_cfg >> 2) & 0x03;
+ swap_cfg = flash_pin_cfg & 0x03;
+
+ if (restore_default) {
+ /* Set Default first */
+ regval = getreg32(GLB_BASE_ADDR + GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR);
+
+ /* Bit0~5 is sf io select */
+ if ((regval&0x3F) == 0x00) {
+ bflb_sf_cfg_init_ext_flash_gpio(1);
+ }
+
+ regval = getreg32(GLB_BASE_ADDR + GLB_PARM_OFFSET_ADDR);
+ /* Bit9 is flash2 swap cs with io2 */
+ regval &= ~(1 << 9);
+ /* Bit8 is flash2 swap io0 with io3 */
+ regval &= ~(1 << 8);
+ putreg32(regval, GLB_BASE_ADDR+GLB_PARM_OFFSET_ADDR);
+
+ bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF2);
+
+ /* Default is set, so return */
+ if (flash_cfg == BFLB_FLASH_CFG_SF2_EXT_23_28 && swap_cfg == BFLB_SF2_SWAP_NONE) {
+ return 0;
+ }
+ }
+
+ if (flash_cfg == BFLB_FLASH_CFG_SF1_EXT_17_22) {
+ bflb_sf_cfg_init_ext_flash_gpio(0);
+ bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF1);
+ } else {
+ regval = getreg32(GLB_BASE_ADDR + GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR);
+
+ /* Bit0~5 is sf io select */
+ if ((regval&0x3F) == 0x00) {
+ bflb_sf_cfg_init_ext_flash_gpio(1);
+ }
+
+ regval = getreg32(GLB_BASE_ADDR + GLB_PARM_OFFSET_ADDR);
+ if (swap_cfg == BFLB_SF2_SWAP_NONE) {
+ /* Bit9 is flash2 swap cs with io2 */
+ regval &= ~(1 << 9);
+ /* Bit8 is flash2 swap io0 with io3 */
+ regval &= ~(1 << 8);
+ } else if (swap_cfg == BFLB_SF2_SWAP_CS_IO2) {
+ /* Bit9 is flash2 swap cs with io2 */
+ regval |= (1 << 9);
+ /* Bit8 is flash2 swap io0 with io3 */
+ regval &= ~(1 << 8);
+ } else if (swap_cfg == BFLB_SF2_SWAP_IO0_IO3) {
+ /* Bit9 is flash2 swap cs with io2 */
+ regval &= ~(1 << 9);
+ /* Bit8 is flash2 swap io0 with io3 */
+ regval |= (1 << 8);
+ } else {
+ /* Bit9 is flash2 swap cs with io2 */
+ regval |= (1 << 9);
+ /* Bit8 is flash2 swap io0 with io3 */
+ regval |= (1 << 8);
+ }
+ putreg32(regval, GLB_BASE_ADDR+GLB_PARM_OFFSET_ADDR);
+
+ bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF2);
+ }
+
+ return 0;
+}
+#elif defined(BL602)
+/****************************************************************************/ /**
+ * @brief Init flash GPIO according to flash Pin config
+ *
+ * @param flash_pin_cfg: Specify flash Pin config
+ * @param restore_default: Wether to restore default setting
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+ if (restore_default) {
+ /* Set Default first */
+ bflb_sf_ctrl_select_pad(SF_CTRL_EMBEDDED_SEL);
+ GLB_Select_Internal_Flash();
+ GLB_Swap_Flash_Pin();
+ //SF_Cfg_Deinit_Ext_Flash_Gpio(0);
+ bflb_sf_cfg_deinit_ext_flash_gpio(1);
+ bflb_sf_cfg_init_internal_flash_gpio();
+ }
+
+ if (flash_pin_cfg > 0) {
+ /*01: deswap flash PIN
+ 10: use ext flash 1(GPIO17-22)
+ 11: use ext flash 0(GPIO0-2, 20-22)
+ */
+ if (flash_pin_cfg == BFLB_FLASH_CFG_DESWAP) {
+ bflb_sf_ctrl_select_pad(SF_CTRL_EMBEDDED_SEL);
+ /*DONOT Swap flash PIN*/
+ GLB_Deswap_Flash_Pin();
+ } else {
+ bflb_sf_ctrl_select_pad(flash_pin_cfg - 1);
+ GLB_Select_External_Flash();
+ bflb_sf_cfg_init_ext_flash_gpio(flash_pin_cfg - BFLB_FLASH_CFG_EXT0_17_22);
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+/****************************************************************************/ /**
+ * @brief Init flash2 GPIO
+ *
+ * @param swap: Select embedded flash2 swap io3 with io0
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash2_gpio(uint8_t swap)
+{
+ bflb_sf_cfg_init_ext_flash_gpio(0);
+#if defined(BL628)
+ bflb_glb_set_sflash2_io_parm(swap);
+#elif defined(BL616)
+ GLB_Set_SFlash2_IO_PARM(swap);
+#endif
+
+ return 0;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Identify one flash
+ *
+ * @param call_from_flash: code run at flash or ram
+ * @param flash_pin_cfg: Bit 7: auto_scan, Bit6-0: flash GPIO config
+ * @param restore_default: Wether restore default flash GPIO config
+ * @param p_flash_cfg: Flash config pointer
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+__WEAK
+uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
+ spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+ uint8_t auto_scan = 0;
+ uint8_t flash_pin = 0;
+ uint32_t jedec_id = 0;
+ uint32_t i = 0;
+ uint32_t offset = 0;
+ uint8_t stat = 0;
+#if defined(BL602)
+ uint8_t gpio17_fun = 0;
+#endif
+
+ auto_scan = ((flash_pin_cfg >> 7) & 1);
+ flash_pin = (flash_pin_cfg & 0x7F);
+
+ arch_memcpy_fast(p_flash_cfg, &flash_cfg_winb_16jv, sizeof(spi_flash_cfg_type));
+
+ if (call_from_flash == 1) {
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB);
+ return 0;
+ }
+ }
+
+ if (auto_scan) {
+ flash_pin = 0;
+ do {
+#if defined(BL628) || defined(BL616)
+ if (!IS_SF_CTRL_PIN_SELECT(flash_pin)) {
+ flash_pin++;
+ continue;
+ }
+ if (bank == SF_CTRL_FLASH_BANK1) {
+ if (flash_pin > SF_IO_EMB_SWAP_IO2CS_AND_SF2) {
+ jedec_id = 0;
+ break;
+ }
+ if (flash_pin < SF_IO_EXT_SF3) {
+ flash_pin = SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0;
+ }
+ if (flash_pin == SF_IO_EXT_SF2) {
+ flash_pin++;
+ }
+ bflb_sf_cfg_init_flash2_gpio(!((flash_pin >> 5) & 1));
+ } else {
+ if (flash_pin > SF_IO_EXT_SF2) {
+ jedec_id = 0;
+ break;
+ }
+ if (flash_pin > SF_IO_EXT_SF3) {
+ flash_pin = SF_IO_EXT_SF2;
+ }
+ bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+ }
+#elif defined(BL808) || defined(BL606P)
+ if (flash_pin > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+ jedec_id = 0;
+ break;
+ }
+ if (!IS_SF_CTRL_PIN_SELECT(flash_pin) || (flash_pin&(1<<3)) > 0) {
+ flash_pin++;
+ continue;
+ }
+ bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#elif defined(BL702L)
+ if (flash_pin > SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH) {
+ jedec_id = 0;
+ break;
+ }
+ bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#elif defined(BL702)
+ if (flash_pin > 0x0f) {
+ jedec_id = 0;
+ break;
+ }
+ bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#elif defined(BL602)
+#define GLB_BASE_ADDR 0x40000000
+#define GLB_GPIO17_OFFSET_ADDR 0x120
+ if (flash_pin > BFLB_FLASH_CFG_EXT1_0_2_20_22) {
+ jedec_id = 0;
+ break;
+ }
+
+ if (flash_pin > BFLB_FLASH_CFG_EXT0_17_22) {
+ /*flash_pin=2 has make gpio17 into jtag,but not success*/
+ bflb_sf_cfg_restore_gpio17_fun(gpio17_fun);
+ }
+
+ /* select media gpio */
+ if (flash_pin == BFLB_FLASH_CFG_EXT0_17_22) {
+ gpio17_fun = ((getreg32(GLB_BASE_ADDR + GLB_GPIO17_OFFSET_ADDR)>>24) & 0xf);
+ }
+
+ bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#endif
+ bflb_sflash_release_powerdown(p_flash_cfg);
+ bflb_sflash_reset_continue_read(p_flash_cfg);
+ bflb_sflash_disable_burst_wrap(p_flash_cfg);
+ jedec_id = 0;
+ bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id);
+ bflb_sflash_disable_burst_wrap(p_flash_cfg);
+ jedec_id = jedec_id & 0xffffff;
+ flash_pin++;
+ } while ((jedec_id & 0x00ffff) == 0 || (jedec_id & 0xffff00) == 0 || (jedec_id & 0x00ffff) == 0xffff || (jedec_id & 0xffff00) == 0xffff00);
+ } else {
+ /* select media gpio */
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+ if (bank == SF_CTRL_FLASH_BANK1) {
+ bflb_sf_cfg_init_flash2_gpio(!((flash_pin >> 5) & 1));
+ } else {
+ bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+ }
+#else
+ bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#endif
+ bflb_sflash_release_powerdown(p_flash_cfg);
+ bflb_sflash_reset_continue_read(p_flash_cfg);
+ bflb_sflash_disable_burst_wrap(p_flash_cfg);
+ bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id);
+ bflb_sflash_disable_burst_wrap(p_flash_cfg);
+ jedec_id = jedec_id & 0xffffff;
+ }
+
+ for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+ if (flash_infos[i].jedec_id == jedec_id) {
+ arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+ break;
+ }
+ }
+
+ if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) {
+ if (call_from_flash == 1) {
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ return jedec_id;
+ } else {
+ if (call_from_flash == 1) {
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ return (jedec_id | BFLB_FLASH_ID_VALID_FLAG);
+ }
+}
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+/****************************************************************************/ /**
+ * @brief Identify one flash patch
+ *
+ * @param call_from_flash: code run at flash or ram
+ * @param flash_pin_cfg: Bit 7: auto_scan, Bit6-0: flash GPIO config
+ * @param restore_default: Wether restore default flash GPIO config
+ * @param p_flash_cfg: Flash config pointer
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+__WEAK
+uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg,
+ uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+ return bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank);
+}
+#endif
+
+#if defined(BL628) || defined(BL616)
+/****************************************************************************/ /**
+ * @brief SF Cfg flash init
+ *
+ * @param sel: SF pin select
+ * @param p_sf_ctrl_cfg: Serial flash controller configuration pointer
+ * @param p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg,
+ const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+ uint8_t sel_embedded = 0;
+ uint8_t swap_io2_cs = 0;
+ uint8_t swap_io3_io0 = 0;
+
+ if (sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) {
+ return -1;
+ }
+
+ if (sel & (1 << 2)) {
+ bflb_sf_cfg_init_flash2_gpio(!((sel >> 5) & 1));
+ sel_embedded = 0;
+ } else if (sel & (1 << 3)) {
+ bflb_sf_cfg_init_ext_flash_gpio(1);
+ sel_embedded = 0;
+ } else {
+ sel_embedded = 1;
+ }
+ /* If pin select dual flash, embedded is default */
+ if ((sel & (1 << 4))) {
+ sel_embedded = 1;
+ }
+
+ swap_io3_io0 = ((sel >> 1) & 1);
+ swap_io3_io0 = (!swap_io3_io0);
+ swap_io2_cs = ((sel >> 0) & 1);
+#if defined(BL628)
+ bflb_glb_set_sflash_io_parm(sel_embedded, swap_io3_io0, swap_io2_cs);
+#else
+ GLB_Set_SFlash_IO_PARM(sel_embedded, swap_io3_io0, swap_io2_cs);
+#endif
+ bflb_sf_ctrl_select_pad(sel);
+
+ if (sel <= SF_IO_EMB_SWAP_IO2CS) {
+ /* Embedded pad1 io delay set */
+ if (p_sf_ctrl_cfg != NULL) {
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+ }
+ } else if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) {
+ /* Pad2 or pad3 io delay set */
+ if (p_sf_ctrl_cfg != NULL) {
+ bflb_sf_ctrl_set_io_delay(((sel&0xf) >> 2), p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+ }
+ } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+ ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+ /* Dual flash mode, embedded pad1 and pad2 io delay set */
+ if (p_sf_ctrl_cfg != NULL) {
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+ }
+ if (p_bank2_cfg != NULL) {
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+ }
+ }
+
+ if (p_bank2_cfg != NULL) {
+ if (p_bank2_cfg->sbus2_select) {
+ if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+ ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+ /* Default sbus2 replace opt flash2 */
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ }
+ }
+ }
+
+ bflb_sflash_init(p_sf_ctrl_cfg, p_bank2_cfg);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief SF Cfg system bus 2 flash init
+ *
+ * @param sel: SF pin select
+ * @param p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+ if (sel < SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 || sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) {
+ return -1;
+ }
+
+ /* Init flash2 gpio */
+ if (sel & (1 << 2)) {
+ bflb_sf_cfg_init_flash2_gpio(!((sel >> 5) & 1));
+ }
+
+ /* Set remap for flash2 xip mode */
+ bflb_sf_ctrl_remap_set(p_bank2_cfg->remap, p_bank2_cfg->remap_lock);
+
+ if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+ ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+ /* Dual flash mode, pad2 io delay set */
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+ }
+ if (p_bank2_cfg->sbus2_select) {
+ if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+ ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+ /* Default sbus2 replace opt flash2 */
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ }
+ }
+
+ bflb_sflash_init(NULL, p_bank2_cfg);
+
+ return 0;
+}
+#elif defined(BL808) || defined(BL606P)
+/****************************************************************************/ /**
+ * @brief SF Cfg flash init
+ *
+ * @param sel: SF pin select
+ * @param p_sf_ctrl_cfg: Serial flash controller configuration pointer
+ * @param p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg,
+ const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+ uint8_t sel_embedded = 0;
+ uint8_t swap = 0;
+
+ if ((sel&(1<<3)) > 0) {
+ return ERROR;
+ }
+
+ if (sel & (1 << 2)) {
+ bflb_sf_cfg_init_ext_flash_gpio(0);
+ sel_embedded = 0;
+ } else {
+ sel_embedded = 1;
+ }
+ /* If pin select dual flash, embedded is default */
+ if ((sel & (1 << 4))) {
+ sel_embedded = 1;
+ }
+
+ swap = ((sel >> 1) & 1);
+ swap = (!swap);
+ GLB_Set_Flash_IO_PARM(sel_embedded, swap);
+ bflb_sf_ctrl_select_pad(sel);
+
+ if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) {
+ /* Embedded pad1 io delay set */
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+ } else if (sel <= SF_IO_EXT_SF2) {
+ /* Pad2 or pad3 io delay set */
+ bflb_sf_ctrl_set_io_delay((sel >> 2), p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+ } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+ /* Dual flash mode, embedded pad1 and pad2 io delay set */
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+ }
+
+ if (p_bank2_cfg != NULL) {
+ if (p_bank2_cfg->sbus2_select) {
+ if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+ /* Default sbus2 replace opt flash2 */
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ }
+ }
+ }
+
+ bflb_sflash_init(p_sf_ctrl_cfg, p_bank2_cfg);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief SF Cfg system bus 2 flash init
+ *
+ * @param sel: SF pin select
+ * @param p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+ if (sel < SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 || sel > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+ return ERROR;
+ }
+
+ /* Init flash2 gpio */
+ if (sel & (1 << 2)) {
+ bflb_sf_cfg_init_ext_flash_gpio(0);
+ }
+
+ /* Set remap for flash2 xip mode */
+ bflb_sf_ctrl_remap_set(p_bank2_cfg->remap, p_bank2_cfg->remap_lock);
+
+ /* Dual flash mode, pad2 io delay set */
+ bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+
+ if (p_bank2_cfg->sbus2_select) {
+ /* Default sbus2 replace opt flash2 */
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ }
+
+ bflb_sflash_init(NULL, p_bank2_cfg);
+
+ return SUCCESS;
+}
+#endif
+
+/*@} end of group SF_CFG_Public_Functions */
+
+/*@} end of group SF_CFG */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_cfg.h b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_cfg.h
new file mode 100644
index 00000000..7b984cf0
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_cfg.h
@@ -0,0 +1,215 @@
+/**
+ ******************************************************************************
+ * @file bflb_sf_cfg.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL628_SF_CFG_H__
+#define __BL628_SF_CFG_H__
+
+#include "bflb_gpio.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SF_CFG
+ * @{
+ */
+
+/** @defgroup SF_CFG_Public_Types
+ * @{
+ */
+
+/*@} end of group SF_CFG_Public_Types */
+
+/** @defgroup SF_CFG_Public_Constants
+ * @{
+ */
+
+/*@} end of group SF_CFG_Public_Constants */
+
+/** @defgroup SF_CFG_Public_Macros
+ * @{
+ */
+#define BFLB_GPIO_FUNC_SF 2
+#if defined(BL628) || defined(BL616)
+/* Flash option sf2 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_8
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_4
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_7
+#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_5
+#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_6
+#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_9
+/* Flash option sf3 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_15
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_20
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_16
+#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_19
+#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_18
+#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_14
+#elif defined(BL808) || defined(BL606P)
+/* Flash option sf2 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_34
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_35
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_36
+#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_37
+#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_38
+#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_39
+#elif defined(BL702L)
+/* Flash option */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_27
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_26
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_23
+#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_25
+#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_24
+#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_28
+#elif defined(BL702)
+/* Flash option 0 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_21
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_19
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_17
+#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_18
+#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_22
+#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_20
+/* Flash option 1 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_27
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_25
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_28
+#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_24
+#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_23
+#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_26
+/* Flash option 2 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK2_GPIO GPIO_PIN_36
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS2_GPIO GPIO_PIN_35
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA02_GPIO GPIO_PIN_32
+#define BFLB_EXTFLASH_DATA12_GPIO GPIO_PIN_34
+#define BFLB_EXTFLASH_DATA22_GPIO GPIO_PIN_33
+#define BFLB_EXTFLASH_DATA32_GPIO GPIO_PIN_37
+#define BFLB_FLASH_CFG_SF2_EXT_23_28 0
+#define BFLB_FLASH_CFG_SF2_INT_512K 1
+#define BFLB_FLASH_CFG_SF2_INT_1M 2
+#define BFLB_FLASH_CFG_SF1_EXT_17_22 3
+#define BFLB_SF2_SWAP_NONE 0
+#define BFLB_SF2_SWAP_CS_IO2 1
+#define BFLB_SF2_SWAP_IO0_IO3 2
+#define BFLB_SF2_SWAP_BOTH 3
+#elif defined(BL602)
+/*Flash option 0*/
+/*Flash CLK*/
+#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_22
+/*FLASH CS*/
+#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_21
+/*FLASH DATA*/
+#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_20
+#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_19
+#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_18
+#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_17
+/*Flash option 1*/
+/*Flash CLK*/
+#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_22
+/*FLASH CS*/
+#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_21
+/*FLASH DATA*/
+#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_20
+#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_0
+#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_1
+#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_2
+#define BFLB_FLASH_CFG_DESWAP 1
+#define BFLB_FLASH_CFG_EXT0_17_22 2
+#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3
+#endif
+#define BFLB_FLASH_ID_VALID_FLAG 0x80000000
+#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF
+
+/*@} end of group SF_CFG_Public_Macros */
+
+/** @defgroup SF_CFG_Public_Functions
+ * @{
+ */
+int bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+ uint8_t group, uint8_t bank);
+int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+ uint8_t group, uint8_t bank);
+#if defined(BL702L) || defined(BL702)
+void bflb_sf_cfg_init_internal_flash_gpio(void);
+#endif
+#if defined(BL602)
+void bflb_sf_cfg_restore_gpio17_fun(uint8_t fun);
+#endif
+int bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+int bflb_sf_cfg_init_flash2_gpio(uint8_t swap);
+#endif
+int bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin);
+int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin);
+uint32_t bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
+ spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
+uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t callfromflash, uint8_t flash_pin_cfg, uint8_t restore_default,
+ spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg,
+ const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
+int bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
+#else
+int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg);
+#endif
+
+/*@} end of group SF_CFG_Public_Functions */
+
+/*@} end of group SF_CFG */
+
+/*@} end of group BL628_Peripheral_Driver */
+
+#endif /* __BL628_SF_CFG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_ctrl.c b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_ctrl.c
new file mode 100644
index 00000000..2996a656
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_ctrl.c
@@ -0,0 +1,2244 @@
+/**
+ ******************************************************************************
+ * @file bl628_sf_ctrl.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bflb_sf_ctrl.h"
+#include "hardware/sf_ctrl_reg.h"
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#include
+#else
+#include
+#endif
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SF_CTRL
+ * @{
+ */
+
+/** @defgroup SF_CTRL_Private_Macros
+ * @{
+ */
+
+/*@} end of group SF_CTRL_Private_Macros */
+
+/** @defgroup SF_CTRL_Private_Types
+ * @{
+ */
+
+/*@} end of group SF_CTRL_Private_Types */
+
+/** @defgroup SF_CTRL_Private_Variables
+ * @{
+ */
+
+#if defined(BL702) || defined(BL702L)
+#define bflb_sf_ctrl_get_aes_region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100)
+#else
+#define bflb_sf_ctrl_get_aes_region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80)
+#endif
+#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+
+/*@} end of group SF_CTRL_Private_Variables */
+
+/** @defgroup SF_CTRL_Global_Variables
+ * @{
+ */
+
+/*@} end of group SF_CTRL_Global_Variables */
+
+/** @defgroup SF_CTRL_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group SF_CTRL_Private_Fun_Declaration */
+
+/** @defgroup SF_CTRL_Private_Functions
+ * @{
+ */
+
+/*@} end of group SF_CTRL_Private_Functions */
+
+/** @defgroup SF_CTRL_Public_Functions
+ * @{
+ */
+
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ //return __builtin_bswap32(value);
+ uint32_t res = 0;
+
+ res = (value << 24) | (value >> 24);
+ res &= 0xFF0000FF; /* only for sure */
+ res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
+
+ return res;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Enable serail flash controller
+ *
+ * @param cfg: serial flash controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+ uint32_t time_out = 0;
+
+ if (cfg == NULL) {
+ return;
+ }
+
+ reg_base = BFLB_SF_CTRL_BASE;
+ time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ time_out--;
+
+ if (time_out == 0) {
+ return;
+ }
+ }
+
+ regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+ if (cfg->en32b_addr) {
+ regval |= SF_CTRL_SF_IF_32B_ADR_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_32B_ADR_EN;
+ }
+#endif
+
+ if (cfg->clk_delay > 0) {
+ regval |= SF_CTRL_SF_IF_READ_DLY_EN;
+ regval &= ~SF_CTRL_SF_IF_READ_DLY_N_MASK;
+ regval |= ((cfg->clk_delay-1) << SF_CTRL_SF_IF_READ_DLY_N_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_READ_DLY_EN;
+ }
+
+ /* Serail out inverted, so sf ctrl send on negative edge */
+ if (cfg->clk_invert) {
+ regval |= SF_CTRL_SF_CLK_OUT_INV_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF_CLK_OUT_INV_SEL;
+ }
+ if (cfg->rx_clk_invert) {
+ regval |= SF_CTRL_SF_CLK_SF_RX_INV_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF_CLK_SF_RX_INV_SEL;
+ }
+ putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+
+#if defined(BL602) ||defined(BL702) || defined(BL702L)
+ bflb_sf_ctrl_set_io_delay(0, cfg->do_delay, cfg->di_delay, cfg->oe_delay);
+ bflb_sf_ctrl_set_io_delay(1, cfg->do_delay, cfg->di_delay, cfg->oe_delay);
+ bflb_sf_ctrl_set_io_delay(2, cfg->do_delay, cfg->di_delay, cfg->oe_delay);
+#endif
+
+ /* Enable AHB access sram buffer and enable sf interface */
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ regval |= SF_CTRL_SF_AHB2SRAM_EN;
+ regval |= SF_CTRL_SF_IF_EN;
+ putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+
+ bflb_sf_ctrl_set_owner(cfg->owner);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl set io delay
+ *
+ * @param pad: Pad select
+ * @param do_delay: DO delay select
+ * @param di_delay: DI delay select
+ * @param oe_delay: OE delay select
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t do_delay, uint8_t di_delay, uint8_t oe_delay)
+{
+ uint32_t offset = 0;
+ uint32_t regval = 0;
+
+ if (pad == SF_CTRL_PAD1) {
+ offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET;
+ } else if (pad == SF_CTRL_PAD2) {
+ offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET;
+ } else {
+ offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET;
+ }
+
+ /* Set do di and oe delay */
+ regval = getreg32(offset + SF_CTRL_IO_DLY_1_OFFSET);
+ regval &= ~SF_CTRL_IO_0_DO_DLY_SEL_MASK;
+ regval |= (do_delay << SF_CTRL_IO_0_DO_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_0_DI_DLY_SEL_MASK;
+ regval |= (di_delay << SF_CTRL_IO_0_DI_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_0_OE_DLY_SEL_MASK;
+ regval |= (oe_delay << SF_CTRL_IO_0_OE_DLY_SEL_SHIFT);
+ putreg32(regval, offset + SF_CTRL_IO_DLY_1_OFFSET);
+
+ regval = getreg32(offset + SF_CTRL_IO_DLY_2_OFFSET);
+ regval &= ~SF_CTRL_IO_1_DO_DLY_SEL_MASK;
+ regval |= (do_delay << SF_CTRL_IO_1_DO_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_1_DI_DLY_SEL_MASK;
+ regval |= (di_delay << SF_CTRL_IO_1_DI_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_1_OE_DLY_SEL_MASK;
+ regval |= (oe_delay << SF_CTRL_IO_1_OE_DLY_SEL_SHIFT);
+ putreg32(regval, offset + SF_CTRL_IO_DLY_2_OFFSET);
+
+ regval = getreg32(offset + SF_CTRL_IO_DLY_3_OFFSET);
+ regval &= ~SF_CTRL_IO_2_DO_DLY_SEL_MASK;
+ regval |= (do_delay << SF_CTRL_IO_2_DO_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_2_DI_DLY_SEL_MASK;
+ regval |= (di_delay << SF_CTRL_IO_2_DI_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_2_OE_DLY_SEL_MASK;
+ regval |= (oe_delay << SF_CTRL_IO_2_OE_DLY_SEL_SHIFT);
+ putreg32(regval, offset + SF_CTRL_IO_DLY_3_OFFSET);
+
+ regval = getreg32(offset + SF_CTRL_IO_DLY_4_OFFSET);
+ regval &= ~SF_CTRL_IO_3_DO_DLY_SEL_MASK;
+ regval |= (do_delay << SF_CTRL_IO_3_DO_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_3_DI_DLY_SEL_MASK;
+ regval |= (di_delay << SF_CTRL_IO_3_DI_DLY_SEL_SHIFT);
+ regval &= ~SF_CTRL_IO_3_OE_DLY_SEL_MASK;
+ regval |= (oe_delay << SF_CTRL_IO_3_OE_DLY_SEL_SHIFT);
+ putreg32(regval, offset + SF_CTRL_IO_DLY_4_OFFSET);
+}
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+/****************************************************************************/ /**
+ * @brief Enable serail bank2 controller
+ *
+ * @param bank2_cfg: serial bank2 controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2_cfg)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ if (bank2_cfg == NULL) {
+ return;
+ }
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ /* Select if1 bank2 clock delay */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_12_OFFSET);
+ if (bank2_cfg->bank2_rx_clk_invert_src) {
+ regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+
+ if (bank2_cfg->bank2_rx_clk_invert_sel) {
+ regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+ }
+ } else {
+ regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+ }
+
+ if (bank2_cfg->bank2_delay_src) {
+ regval |= SF_CTRL_SF2_IF_READ_DLY_SRC;
+
+ if (bank2_cfg->bank2_clk_delay > 0) {
+ regval |= SF_CTRL_SF2_IF_READ_DLY_EN;
+ regval &= ~SF_CTRL_SF2_IF_READ_DLY_N_MASK;
+ regval |= ((bank2_cfg->bank2_clk_delay - 1) << SF_CTRL_SF2_IF_READ_DLY_N_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF2_IF_READ_DLY_EN;
+ }
+ } else {
+ regval &= ~SF_CTRL_SF2_IF_READ_DLY_SRC;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_12_OFFSET);
+
+ /* Select sbus2 clock delay */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+ if (bank2_cfg->bank2_rx_clk_invert_sel) {
+ regval |= SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+ }
+
+ if (bank2_cfg->bank2_clk_delay > 0) {
+ regval |= SF_CTRL_SF_IF2_READ_DLY_EN;
+ regval &= ~SF_CTRL_SF_IF2_READ_DLY_N_MASK;
+ regval |= ((bank2_cfg->bank2_clk_delay - 1) << SF_CTRL_SF_IF2_READ_DLY_N_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF2_READ_DLY_EN;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+
+ /* Dual flash mode, enable bank2, select pad1 and pad2 */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+ regval |= SF_CTRL_SF_IF_BK2_EN;
+ regval |= SF_CTRL_SF_IF_BK2_MODE;
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Flash controller sbus2 hold sram
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_hold_sram(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ /* Sbus2 hold sram */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+ regval |= SF_CTRL_SF_IF2_FN_SEL;
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Flash controller sbus2 release sram
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_release_sram(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ /* Sbus2 release sram */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+ regval &= ~SF_CTRL_SF_IF2_FN_SEL;
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Get flash controller sbus2 status
+ *
+ * @param None
+ *
+ * @return Wether if2 is enable
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_is_sbus2_enable(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+ if (regval & SF_CTRL_SF_IF2_EN) {
+ if (regval & SF_CTRL_SF_IF2_FN_SEL) {
+ return 1;
+ } else {
+ return 0;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl set sbus2 repalce
+ *
+ * @param pad: SF pad to replace
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_replace(uint8_t pad)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ /* Sbus2 enable */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+ regval |= SF_CTRL_SF_IF2_EN;
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+
+ bflb_sf_ctrl_sbus2_hold_sram();
+
+ /* Sbus2 repalce pad */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+ regval &= ~SF_CTRL_SF_IF2_REPLACE_SF1;
+ regval &= ~SF_CTRL_SF_IF2_REPLACE_SF2;
+ regval &= ~SF_CTRL_SF_IF2_REPLACE_SF3;
+
+ if (pad == SF_CTRL_PAD1) {
+ regval |= SF_CTRL_SF_IF2_REPLACE_SF1;
+ } else if (pad == SF_CTRL_PAD2) {
+ regval |= SF_CTRL_SF_IF2_REPLACE_SF2;
+ } else {
+ regval |= SF_CTRL_SF_IF2_REPLACE_SF3;
+ }
+
+ regval &= ~SF_CTRL_SF_IF2_PAD_SEL_MASK;
+ regval |= (pad << SF_CTRL_SF_IF2_PAD_SEL_SHIFT);
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl sbus2 revoke replace
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_revoke_replace(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ bflb_sf_ctrl_sbus2_release_sram();
+
+ /* Sbus2 clear repalce pad */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+ regval &= ~SF_CTRL_SF_IF2_REPLACE_SF1;
+ regval &= ~SF_CTRL_SF_IF2_REPLACE_SF2;
+ regval &= ~SF_CTRL_SF_IF2_REPLACE_SF3;
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+
+ /* Sbus2 disable */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+ regval &= ~SF_CTRL_SF_IF2_EN;
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl set sbus2 clock delay
+ *
+ * @param clk_delay: Sbus2 clock delay
+ * @param rx_clk_invert: Sbus2 rx clock invert
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+
+ if (clk_delay > 0) {
+ regval |= SF_CTRL_SF_IF2_READ_DLY_EN;
+ regval &= ~SF_CTRL_SF_IF2_READ_DLY_N_MASK;
+ regval |= ((clk_delay-1) << SF_CTRL_SF_IF2_READ_DLY_N_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF2_READ_DLY_EN;
+ }
+
+ if (rx_clk_invert) {
+ regval |= SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl dual flash memory remap set
+ *
+ * @param remap: Memory remap set type
+ * @param lock: Memory remap lock
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+ regval &= ~SF_CTRL_SF_AHB2SIF_REMAP_MASK;
+ regval |= (remap << SF_CTRL_SF_AHB2SIF_REMAP_SHIFT);
+ putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+
+ regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+ if (lock) {
+ regval |= SF_CTRL_SF_AHB2SIF_REMAP_LOCK;
+ } else {
+ regval &= ~SF_CTRL_SF_AHB2SIF_REMAP_LOCK;
+ }
+ putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+#endif
+
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+/****************************************************************************/ /**
+ * @brief Get flash controller clock delay value
+ *
+ * @param en32_bits_addr: Serial flash enable or disable 32-bits addr
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_32bits_addr_en(uint8_t en32_bits_addr)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+ if (en32_bits_addr) {
+ regval |= SF_CTRL_SF_IF_32B_ADR_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_32B_ADR_EN;
+ }
+ putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+#endif
+
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+/****************************************************************************/ /**
+ * @brief Enable serail psram controller
+ *
+ * @param psram_cfg: serial psram controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+#if defined(BL702L)
+ /* Enable psram dual bank mode */
+ regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+ regval |= SF_CTRL_SF_IF_BK2_EN;
+ regval |= SF_CTRL_SF_IF_BK2_MODE;
+ putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+#endif
+
+ /* Select psram clock delay */
+ regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_12_OFFSET);
+ if (psram_cfg->psram_rx_clk_invert_src) {
+ regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+
+ if (psram_cfg->psram_rx_clk_invert_sel) {
+ regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+ }
+ } else {
+ regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+ }
+
+ if (psram_cfg->psram_delay_src) {
+ regval |= SF_CTRL_SF2_IF_READ_DLY_SRC;
+
+ if (psram_cfg->psram_clk_delay > 0) {
+ regval |= SF_CTRL_SF2_IF_READ_DLY_EN;
+ regval &= ~SF_CTRL_SF2_IF_READ_DLY_N_MASK;
+ regval |= ((psram_cfg->psram_clk_delay - 1) << SF_CTRL_SF2_IF_READ_DLY_N_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF2_IF_READ_DLY_EN;
+ }
+ } else {
+ regval &= ~SF_CTRL_SF2_IF_READ_DLY_SRC;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_12_OFFSET);
+
+ /* Enable AHB access sram buffer and enable sf interface */
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ regval |= SF_CTRL_SF_AHB2SRAM_EN;
+ regval |= SF_CTRL_SF_IF_EN;
+ putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+
+ bflb_sf_ctrl_set_owner(psram_cfg->owner);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Get flash controller clock delay value
+ *
+ * @param None
+ *
+ * @return Clock delay value
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_clock_delay(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+ if ((regval&SF_CTRL_SF_IF_READ_DLY_EN) == 0) {
+ return 0;
+ }
+
+ return ((regval&SF_CTRL_SF_IF_READ_DLY_N_MASK)>>SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1;
+}
+
+/****************************************************************************/ /**
+ * @brief Set flash controller clock delay value
+ *
+ * @param delay: Clock delay value
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_clock_delay(uint8_t delay)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+ if (delay > 0) {
+ regval |= SF_CTRL_SF_IF_READ_DLY_EN;
+ regval &= ~SF_CTRL_SF_IF_READ_DLY_N_MASK;
+ regval |= ((delay-1) << SF_CTRL_SF_IF_READ_DLY_N_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_READ_DLY_EN;
+ }
+ putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl get wrap queue value
+ *
+ * @param None
+ *
+ * @return Wrap queue value
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_wrap_queue_value(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+ return (regval&SF_CTRL_SF_CMDS_2_WRAP_Q) ? 1:0;
+}
+
+#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)
+/****************************************************************************/ /**
+ * @brief SF Ctrl set cmds config
+ *
+ * @param cmds_cfg: SF Ctrl cmds config
+ * @param bank: bank select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t bank)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+ regval &= ~SF_CTRL_SF_IF_1_ACK_LAT_MASK;
+ regval |= ((cmds_cfg->ack_latency) << SF_CTRL_SF_IF_1_ACK_LAT_SHIFT);
+
+ if (cmds_cfg->cmds_core_en) {
+ regval |= SF_CTRL_SF_CMDS_CORE_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_CORE_EN;
+ }
+
+ if (bank == SF_CTRL_FLASH_BANK1) {
+ if (cmds_cfg->cmds_en) {
+ regval |= SF_CTRL_SF_CMDS_2_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_2_EN;
+ }
+
+ regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT);
+ regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT);
+ } else {
+ if (cmds_cfg->cmds_en) {
+ regval |= SF_CTRL_SF_CMDS_1_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_1_EN;
+ }
+
+ regval &= ~SF_CTRL_SF_CMDS_1_WRAP_MODE_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT);
+ regval &= ~SF_CTRL_SF_CMDS_1_WRAP_LEN_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT);
+ }
+ putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+}
+#elif defined(BL702L)
+/****************************************************************************/ /**
+ * @brief SF Ctrl set cmds config
+ *
+ * @param cmds_cfg: SF Ctrl cmds config
+ * @param sel: select set flash or psram cmds
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+ if (sel == SF_CTRL_SEL_FLASH) {
+ if (cmds_cfg->cmds_en) {
+ regval |= SF_CTRL_SF_CMDS_1_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_1_EN;
+ }
+ regval &= ~SF_CTRL_SF_CMDS_1_WRAP_MODE_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT);
+ regval &= ~SF_CTRL_SF_CMDS_1_WRAP_LEN_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT);
+ } else {
+ if (cmds_cfg->cmds_en) {
+ regval |= SF_CTRL_SF_CMDS_2_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_2_EN;
+ }
+ regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT);
+ regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK;
+ regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT);
+ }
+ putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl burst toggle select
+ *
+ * @param burst_toggle_en: burst toggle enable or not
+ * @param mode: SPI or QPI mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+ if (burst_toggle_en) {
+ regval |= SF_CTRL_SF_CMDS_2_BT_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_2_BT_EN;
+ }
+ putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+
+ regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_6_OFFSET);
+ if (mode) {
+ regval |= SF_CTRL_SF_IF_3_QPI_MODE_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_3_QPI_MODE_EN;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_6_OFFSET);
+}
+#elif defined(BL702) || defined(BL602)
+/****************************************************************************/ /**
+ * @brief SF Ctrl set cmds config
+ *
+ * @param cmds_cfg: SF Ctrl cmds config
+ * @param sel: select bank0 or bank1
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+
+ if (cmds_cfg->cmds_en) {
+ regval |= SF_CTRL_SF_CMDS_2_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_2_EN;
+ }
+
+#if defined(BL702)
+ if (cmds_cfg->burst_toggle_en) {
+ regval |= SF_CTRL_SF_CMDS_2_BT_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_CMDS_2_BT_EN;
+ }
+#endif
+
+ regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK;
+ regval |= (cmds_cfg->cmds_wrap_mode << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT);
+
+ regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK;
+ regval |= (cmds_cfg->cmds_wrap_len << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT);
+ putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl pad select
+ *
+ * @param sel: Pin select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_select_pad(uint8_t sel)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+#if defined(BL628) || defined(BL616)
+ if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) {
+ /* Single flash mode, disable bank2 */
+ regval &= ~SF_CTRL_SF_IF_BK2_EN;
+
+ if (sel <= SF_IO_EMB_SWAP_IO2CS) {
+ /* Select embedded pad1 */
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ } else {
+ /* Select pad2 or pad3 */
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ regval |= (((sel&0xf) >> 2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+ }
+ } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+ ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+ /* Dual flash mode, enable bank2, select pad1 and pad2 */
+ regval |= SF_CTRL_SF_IF_BK2_EN;
+ regval |= SF_CTRL_SF_IF_BK2_MODE;
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ }
+#elif defined(BL808) || defined(BL606P)
+ if (sel <= SF_IO_EXT_SF2) {
+ /* Single flash mode, disable bank2 */
+ regval &= ~SF_CTRL_SF_IF_BK2_EN;
+
+ if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) {
+ /* Select embedded pad1 */
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ } else {
+ /* Select pad2 or pad3 */
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ regval |= (((sel&0xf) >> 2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+ }
+ } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+ /* Dual flash mode, enable bank2, select pad1 and pad2 */
+ regval |= SF_CTRL_SF_IF_BK2_EN;
+ regval |= SF_CTRL_SF_IF_BK2_MODE;
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ }
+#elif defined(BL702)
+ if (sel <= SF_CTRL_SEL_SF3) {
+ regval &= ~SF_CTRL_SF_IF_BK2_EN;
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ regval |= (sel << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+ } else if (sel >= SF_CTRL_SEL_DUAL_BANK_SF1_SF2 && sel <= SF_CTRL_SEL_DUAL_BANK_SF3_SF1) {
+ regval |= SF_CTRL_SF_IF_BK2_EN;
+ regval |= SF_CTRL_SF_IF_BK2_MODE;
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ regval |= ((sel - SF_CTRL_SEL_DUAL_BANK_SF1_SF2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+ } else if (sel == SF_CTRL_SEL_DUAL_CS_SF2) {
+ regval |= SF_CTRL_SF_IF_BK2_EN;
+ regval &= ~SF_CTRL_SF_IF_BK2_MODE;
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ regval |= (1 << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+ } else if (sel == SF_CTRL_SEL_DUAL_CS_SF3) {
+ regval |= SF_CTRL_SF_IF_BK2_EN;
+ regval &= ~SF_CTRL_SF_IF_BK2_MODE;
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ regval |= (2 << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+ }
+#else
+ regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+ regval |= (sel << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+#endif
+ putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl select bank on system bus
+ *
+ * @param bank: bank select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus_select_bank(uint8_t bank)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+ if (bank) {
+ regval |= SF_CTRL_SF_IF_0_BK_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_0_BK_SEL;
+ }
+ putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Set flash controller owner:I/D AHB or system AHB
+ *
+ * @param owner: owner type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_owner(uint8_t owner)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+ uint32_t time_out = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+ time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ time_out--;
+
+ if (time_out == 0) {
+ return;
+ }
+ }
+
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ /* Set owner */
+ if (owner) {
+ regval |= SF_CTRL_SF_IF_FN_SEL;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_FN_SEL;
+ }
+
+ /* Set iahb to flash interface */
+ if (owner == SF_CTRL_OWNER_IAHB) {
+ regval |= SF_CTRL_SF_AHB2SIF_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_AHB2SIF_EN;
+ }
+ putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Disable flash controller
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_disable(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ regval &= ~SF_CTRL_SF_IF_EN;
+ putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Enable flash controller AES with big indian
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_be(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+ regval |= SF_CTRL_SF_AES_KEY_ENDIAN;
+ regval |= SF_CTRL_SF_AES_IV_ENDIAN;
+ regval |= SF_CTRL_SF_AES_DIN_ENDIAN;
+ regval |= SF_CTRL_SF_AES_DOUT_ENDIAN;
+ putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Enable flash controller AES with little indian
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_le(void)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+ regval &= ~SF_CTRL_SF_AES_KEY_ENDIAN;
+ regval &= ~SF_CTRL_SF_AES_IV_ENDIAN;
+ regval &= ~SF_CTRL_SF_AES_DIN_ENDIAN;
+ regval &= ~SF_CTRL_SF_AES_DOUT_ENDIAN;
+ putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Serial flash controller set AES region
+ *
+ * @param region: region number
+ * @param enable: enable or not
+ * @param hw_key: hardware key or software key
+ * @param start_addr: region start address
+ * @param end_addr: region end address
+ * @param locked: lock this region or not
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+#if defined (BL702) || defined(BL602)
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hw_key,
+ uint32_t start_addr, uint32_t end_addr, uint8_t locked)
+{
+ /* 0x30 : sf_aes_cfg */
+ #define SF_CTRL_SF_AES_REGION_CFG_END_SHIFT (0U)
+ #define SF_CTRL_SF_AES_REGION_CFG_END_MASK (0x3fff<cmd_buf[0], cmd_offset+SF_CTRL_IF_SAHB_1_OFFSET);
+ putreg32(cfg->cmd_buf[1], cmd_offset+SF_CTRL_IF_SAHB_2_OFFSET);
+
+ regval = getreg32(cmd_offset + SF_CTRL_IF_SAHB_0_OFFSET);
+ /* Configure SPI and IO mode*/
+ if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+ regval &= ~SF_CTRL_IF_0_QPI_MODE_EN;
+ } else {
+ regval |= SF_CTRL_IF_0_QPI_MODE_EN;
+ }
+
+ regval &= ~SF_CTRL_IF_0_SPI_MODE_MASK;
+ if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+ if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+ regval |= (SF_CTRL_NIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_DO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_QO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+ }
+ } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_DIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_QIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+ }
+
+ /* Configure cmd */
+ regval |= SF_CTRL_IF_0_CMD_EN;
+ regval &= ~SF_CTRL_IF_0_CMD_BYTE_MASK;
+
+ /* Configure address */
+ regval &= ~SF_CTRL_IF_0_ADR_BYTE_MASK;
+ if (cfg->addr_size != 0) {
+ regval |= SF_CTRL_IF_0_ADR_EN;
+ regval |= ((cfg->addr_size-1) << SF_CTRL_IF_0_ADR_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_IF_0_ADR_EN;
+ }
+
+ /* Configure dummy */
+ regval &= ~SF_CTRL_IF_0_DMY_BYTE_MASK;
+ if (cfg->dummy_clks != 0) {
+ regval |= SF_CTRL_IF_0_DMY_EN;
+ regval |= ((cfg->dummy_clks-1) << SF_CTRL_IF_0_DMY_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_IF_0_DMY_EN;
+ }
+
+ /* Configure data */
+ regval &= ~SF_CTRL_IF_0_DAT_BYTE_MASK;
+ if (cfg->nb_data != 0) {
+ regval |= SF_CTRL_IF_0_DAT_EN;
+ regval |= ((cfg->nb_data-1) << SF_CTRL_IF_0_DAT_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_IF_0_DAT_EN;
+ }
+
+ /* Set read write flag */
+ if (cfg->rw_flag) {
+ regval |= SF_CTRL_IF_0_DAT_RW;
+ } else {
+ regval &= ~SF_CTRL_IF_0_DAT_RW;
+ }
+ putreg32(regval, cmd_offset+SF_CTRL_IF_SAHB_0_OFFSET);
+
+ //switch sf_clk_sahb_sram_sel = 0
+ bflb_sf_ctrl_select_clock(1);
+
+ /* Trigger */
+ regval |= SF_CTRL_IF_0_TRIG;
+ putreg32(regval, cmd_offset+SF_CTRL_IF_SAHB_0_OFFSET);
+
+ time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+ while (bflb_sf_ctrl_get_busy_state()) {
+ time_out--;
+
+ if (time_out == 0) {
+ bflb_sf_ctrl_select_clock(0);
+ return;
+ }
+ }
+
+ //switch sf_clk_sahb_sram_sel = 0
+ bflb_sf_ctrl_select_clock(0);
+}
+
+/****************************************************************************/ /**
+ * @brief SF Ctrl disable iahb to flash wrap access for XTS mode
+ *
+ * @param disable: Disable for 1 and enable for 0
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_disable_wrap_access(uint8_t disable)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ if (disable) {
+ regval &= ~SF_CTRL_SF_AHB2SIF_DISWRAP;
+ } else {
+ regval |= SF_CTRL_SF_AHB2SIF_DISWRAP;
+ }
+ putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Config SF controller for xip read
+ *
+ * @param cfg: Serial flash controller command configuration pointer
+ * @param cmd_valid: command valid or not, for continous read, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+ uint32_t time_out = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+ time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ time_out--;
+
+ if (time_out == 0) {
+ return;
+ }
+ }
+
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) {
+ return;
+ }
+
+ /* Copy command buffer */
+ putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_1_OFFSET);
+ putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_2_OFFSET);
+
+ regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_0_OFFSET);
+ /* Configure SPI and IO mode*/
+ if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+ regval &= ~SF_CTRL_SF_IF_1_QPI_MODE_EN;
+ } else {
+ regval |= SF_CTRL_SF_IF_1_QPI_MODE_EN;
+ }
+
+ regval &= ~SF_CTRL_SF_IF_1_SPI_MODE_MASK;
+ if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+ if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+ regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+ }
+ } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+ }
+
+ regval &= ~SF_CTRL_SF_IF_1_CMD_BYTE_MASK;
+ if (cmd_valid) {
+ regval |= SF_CTRL_SF_IF_1_CMD_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_1_CMD_EN;
+ }
+
+ /* Configure address */
+ regval &= ~SF_CTRL_SF_IF_1_ADR_BYTE_MASK;
+ if (cfg->addr_size != 0) {
+ regval |= SF_CTRL_SF_IF_1_ADR_EN;
+ regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_1_ADR_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_1_ADR_EN;
+ }
+
+ /* configure dummy */
+ regval &= ~SF_CTRL_SF_IF_1_DMY_BYTE_MASK;
+ if (cfg->dummy_clks != 0) {
+ regval |= SF_CTRL_SF_IF_1_DMY_EN;
+ regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_1_DMY_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_1_DMY_EN;
+ }
+
+ /* Configure data */
+ if (cfg->nb_data != 0) {
+ regval |= SF_CTRL_SF_IF_1_DAT_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_1_DAT_EN;
+ }
+
+ /* Set read write flag */
+ if (cfg->rw_flag) {
+ regval |= SF_CTRL_SF_IF_1_DAT_RW;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_1_DAT_RW;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_0_OFFSET);
+}
+
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+/****************************************************************************/ /**
+ * @brief Config psram controller for psram I/D cache write
+ *
+ * @param cfg: Serial flash controller command configuration pointer
+ * @param cmd_valid: command valid or not, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+ uint32_t time_out = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+ time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ time_out--;
+
+ if (time_out == 0) {
+ return;
+ }
+ }
+
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) {
+ return;
+ }
+
+ /* Copy command buffer */
+ putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_4_OFFSET);
+ putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_5_OFFSET);
+
+ getreg32(reg_base + SF_CTRL_SF_IF_IAHB_3_OFFSET);
+ /* Configure SPI and IO mode*/
+ if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+ regval &= ~SF_CTRL_SF_IF_2_QPI_MODE_EN;
+ } else {
+ regval |= SF_CTRL_SF_IF_2_QPI_MODE_EN;
+ }
+
+ regval &= ~SF_CTRL_SF_IF_2_SPI_MODE_MASK;
+ if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+ if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+ regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+ }
+ } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+ }
+
+ regval &= ~SF_CTRL_SF_IF_2_CMD_BYTE_MASK;
+ if (cmd_valid) {
+ regval |= SF_CTRL_SF_IF_2_CMD_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_2_CMD_EN;
+ }
+
+ /* Configure address */
+ regval &= ~SF_CTRL_SF_IF_2_ADR_BYTE_MASK;
+ if (cfg->addr_size != 0) {
+ regval |= SF_CTRL_SF_IF_2_ADR_EN;
+ regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_2_ADR_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_2_ADR_EN;
+ }
+
+ /* configure dummy */
+ regval &= ~SF_CTRL_SF_IF_2_DMY_BYTE_MASK;
+ if (cfg->dummy_clks != 0) {
+ regval |= SF_CTRL_SF_IF_2_DMY_EN;
+ regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_2_DMY_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_2_DMY_EN;
+ }
+
+ /* Configure data */
+ if (cfg->nb_data != 0) {
+ regval |= SF_CTRL_SF_IF_2_DAT_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_2_DAT_EN;
+ }
+
+ /* Set read write flag */
+ if (cfg->rw_flag) {
+ regval |= SF_CTRL_SF_IF_2_DAT_RW;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_2_DAT_RW;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_3_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Config bank2 controller for flash2 I/D cache read
+ *
+ * @param cfg: Serial flash controller command configuration pointer
+ * @param cmd_valid: command valid or not, for continous read, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+void ATTR_TCM_SECTION bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+#else
+void ATTR_TCM_SECTION bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+#endif
+{
+ uint32_t reg_base = 0;
+ uint32_t regval = 0;
+ uint32_t time_out = 0;
+
+ reg_base = BFLB_SF_CTRL_BASE;
+ time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ time_out--;
+
+ if (time_out == 0) {
+ return;
+ }
+ }
+
+ regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+ if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) {
+ return;
+ }
+
+ /* Copy command buffer */
+ putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_10_OFFSET);
+ putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_11_OFFSET);
+
+ regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_9_OFFSET);
+ /* Configure SPI and IO mode*/
+ if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+ regval &= ~SF_CTRL_SF_IF_4_QPI_MODE_EN;
+ } else {
+ regval |= SF_CTRL_SF_IF_4_QPI_MODE_EN;
+ }
+
+ regval &= ~SF_CTRL_SF_IF_4_SPI_MODE_MASK;
+ if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+ if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+ regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+ regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+ }
+ } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+ } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+ regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+ }
+
+ regval &= ~SF_CTRL_SF_IF_4_CMD_BYTE_MASK;
+ if (cmd_valid) {
+ regval |= SF_CTRL_SF_IF_4_CMD_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_4_CMD_EN;
+ }
+
+ /* Configure address */
+ regval &= ~SF_CTRL_SF_IF_4_ADR_BYTE_MASK;
+ if (cfg->addr_size != 0) {
+ regval |= SF_CTRL_SF_IF_4_ADR_EN;
+ regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_4_ADR_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_4_ADR_EN;
+ }
+
+ /* configure dummy */
+ regval &= ~SF_CTRL_SF_IF_4_DMY_BYTE_MASK;
+ if (cfg->dummy_clks != 0) {
+ regval |= SF_CTRL_SF_IF_4_DMY_EN;
+ regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_4_DMY_BYTE_SHIFT);
+ } else {
+ regval &= ~SF_CTRL_SF_IF_4_DMY_EN;
+ }
+
+ /* Configure data */
+ if (cfg->nb_data != 0) {
+ regval |= SF_CTRL_SF_IF_4_DAT_EN;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_4_DAT_EN;
+ }
+
+ /* Set read write flag */
+ if (cfg->rw_flag) {
+ regval |= SF_CTRL_SF_IF_4_DAT_RW;
+ } else {
+ regval &= ~SF_CTRL_SF_IF_4_DAT_RW;
+ }
+ putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_9_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief Get SF Ctrl busy state
+ *
+ * @param None
+ *
+ * @return 1 means SF ctrl busy or 0 means SF ctrl not busy
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_busy_state(void)
+{
+ uint32_t regval = 0;
+ uint32_t cmd_offset = 0;
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+ if (bflb_sf_ctrl_is_sbus2_enable() == 0) {
+ cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET;
+ } else {
+ cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET;
+ }
+#else
+ cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET;
+#endif
+
+ regval = getreg32(cmd_offset + SF_CTRL_IF_SAHB_0_OFFSET);
+ if (regval & SF_CTRL_IF_BUSY) {
+ return 1;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief SF Controller interrupt handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_sf_ctrl_irqhandler(void)
+{
+ /* TODO: Not implemented */
+}
+
+/*@} end of group SF_CTRL_Public_Functions */
+
+/*@} end of group SF_CTRL */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_ctrl.h b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_ctrl.h
new file mode 100644
index 00000000..de58709e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sf_ctrl.h
@@ -0,0 +1,482 @@
+/**
+ ******************************************************************************
+ * @file bflb_sf_ctrl.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL628_SF_CTRL_H__
+#define __BL628_SF_CTRL_H__
+
+#include "bflb_core.h"
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SF_CTRL
+ * @{
+ */
+
+/** @defgroup SF_CTRL_Public_Types
+ * @{
+ */
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_SF_CTRL_BASE ((uint32_t)0x4000B000)
+#elif defined(BL606P) || defined(BL808) || defined(BL616)
+#define BFLB_SF_CTRL_BASE ((uint32_t)0x2000b000)
+#elif defined(BL628)
+#define BFLB_SF_CTRL_BASE ((uint32_t)0x20082000)
+#endif
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_FLASH_XIP_BASE (0x23000000)
+#define BFLB_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
+#elif defined(BL606P) || defined(BL808)
+#define BFLB_FLASH_XIP_BASE (0x58000000)
+#define BFLB_FLASH_XIP_END (0x58000000 + 64 * 1024 * 1024)
+#elif defined(BL616)
+#define BFLB_FLASH_XIP_BASE (0xA0000000)
+#define BFLB_FLASH_XIP_END (0xA0000000 + 64 * 1024 * 1024)
+#elif defined(BL628)
+#define BFLB_FLASH_XIP_BASE (0x80000000)
+#define BFLB_FLASH_XIP_END (0x80000000 + 64 * 1024 * 1024)
+#endif
+
+#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)
+#define BFLB_SF_CTRL_SBUS2_ENABLE
+#define BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+#define BFLB_SF_CTRL_AES_XTS_ENABLE
+#endif
+#if defined(BL702) || defined(BL702L)
+#define BFLB_SF_CTRL_PSRAM_ENABLE
+#endif
+
+/**
+ * @brief Serial flash pad type definition
+ */
+#define SF_CTRL_PAD1 0 /*!< SF Ctrl pad 1 */
+#define SF_CTRL_PAD2 1 /*!< SF Ctrl pad 2 */
+#define SF_CTRL_PAD3 2 /*!< SF Ctrl pad 3 */
+
+/**
+ * @brief Serial flash config pin select type definition
+ */
+#if defined(BL628) || defined(BL616)
+#define SF_IO_EMB_SWAP_IO3IO0 0x0 /*!< SF select embedded flash swap io3 with io0 */
+#define SF_IO_EMB_SWAP_IO3IO0_IO2CS 0x1 /*!< SF select embedded flash swap io3 with io0 and io2 with cs */
+#define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */
+#define SF_IO_EMB_SWAP_IO2CS 0x3 /*!< SF select embedded flash swap io2 with cs */
+#define SF_IO_EXT_SF2_SWAP_IO3IO0 0x4 /*!< SF select external flash SF2 use gpio4-9 and SF2 swap io3 with io0 */
+#define SF_IO_EXT_SF3 0x8 /*!< SF select external flash SF3 use gpio10-15 */
+#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 0x14 /*!< SF select embedded flash swap io3 with io0 and SF2 swap io3 with io0*/
+#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0 0x15 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 swap io3 with io0 */
+#define SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0 0x16 /*!< SF select embedded flash no swap and SF2 swap io3 with io0 */
+#define SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0 0x17 /*!< SF select embedded flash swap io2 with cs, and SF2 swap io3 with io0 */
+#define SF_IO_EXT_SF2 0x24 /*!< SF select external flash SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2 0x34 /*!< SF select embedded flash swap io3 with io0 and SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2 0x35 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_NONE_AND_SF2 0x36 /*!< SF select embedded flash no swap and SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_IO2CS_AND_SF2 0x37 /*!< SF select embedded flash swap io2 with cs and SF2 use gpio4-9 */
+#elif defined(BL808) || defined(BL606P)
+#define SF_IO_EMB_SWAP_IO0_IO3 0x0 /*!< SF select embedded flash swap io0 with io3 */
+#define SF_IO_EMB_SWAP_DUAL_IO0_IO3 0x1 /*!< SF select embedded flash swap dual io0 with io3 */
+#define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */
+#define SF_IO_EMB_SWAP_NONE_DUAL_IO0 0x3 /*!< SF select embedded flash no swap and use dual io0 */
+#define SF_IO_EXT_SF2 0x4 /*!< SF select external flash SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 0x14 /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 0x15 /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 0x16 /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 0x17 /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */
+#elif defined(BL702L)
+#define SF_CTRL_SEL_EXTERNAL_FLASH 0x0 /*!< SF select sf2, flash use GPIO 23-28, external flash */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE 0x1 /*!< SF select sf1, embedded flash do not swap */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2 0x2 /*!< SF select sf1, embedded flash swap cs/io2 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3 0x3 /*!< SF select sf1, embedded flash swap io0/io3 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH 0x4 /*!< SF select sf1, embedded flash swap cs/io2 and io0/io3 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE 0x5 /*!< SF select sf1, embedded flash interface reverse and do not swap */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2 0x6 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3 0x7 /*!< SF select sf1, embedded flash interface reverse and swap io0/io3 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH 0x8 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 and io0/io3 */
+#elif defined(BL702)
+#define SF_CTRL_SEL_SF1 0x0 /*!< SF Ctrl select sf1, flash use GPIO 17-22, no psram */
+#define SF_CTRL_SEL_SF2 0x1 /*!< SF Ctrl select sf2, flash use GPIO 23-28, no psram, embedded flash */
+#define SF_CTRL_SEL_SF3 0x2 /*!< SF Ctrl select sf3, flash use GPIO 32-37, no psram */
+#define SF_CTRL_SEL_DUAL_BANK_SF1_SF2 0x3 /*!< SF Ctrl select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */
+#define SF_CTRL_SEL_DUAL_BANK_SF2_SF3 0x4 /*!< SF Ctrl select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */
+#define SF_CTRL_SEL_DUAL_BANK_SF3_SF1 0x5 /*!< SF Ctrl select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */
+#define SF_CTRL_SEL_DUAL_CS_SF2 0x6 /*!< SF Ctrl select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */
+#define SF_CTRL_SEL_DUAL_CS_SF3 0x7 /*!< SF Ctrl select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */
+#elif defined(BL602)
+#define SF_CTRL_EMBEDDED_SEL 0x0 /*!< Embedded flash select */
+#define SF_CTRL_EXTERNAL_17TO22_SEL 0x1 /*!< External flash select gpio 17-22 */
+#define SF_CTRL_EXTERNAL_0TO2_20TO22_SEL 0x2 /*!< External flash select gpio 0-2 and 20-22 */
+#endif
+
+
+/**
+ * @brief Serial flash select bank control type definition
+ */
+#if defined(BL702) || defined(BL702L)
+#define SF_CTRL_SEL_FLASH 0 /*!< SF Ctrl system bus control flash */
+#define SF_CTRL_SEL_PSRAM 1 /*!< SF Ctrl system bus control psram */
+#else
+#define SF_CTRL_FLASH_BANK0 0 /*!< SF Ctrl select flash bank0 */
+#define SF_CTRL_FLASH_BANK1 1 /*!< SF Ctrl select flash bank1 */
+#endif
+
+/**
+ * @brief Serial flash controller wrap mode type definition
+ */
+#define SF_CTRL_WRAP_MODE_0 0 /*!< Cmds bypass wrap commands to macro, original mode */
+#define SF_CTRL_WRAP_MODE_1 1 /*!< Cmds handle wrap commands, original mode */
+#define SF_CTRL_WRAP_MODE_2 2 /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */
+#define SF_CTRL_WRAP_MODE_3 3 /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */
+
+/**
+ * @brief Serail flash controller wrap mode len type definition
+ */
+#define SF_CTRL_WRAP_LEN_8 0 /*!< SF Ctrl wrap length: 8 */
+#define SF_CTRL_WRAP_LEN_16 1 /*!< SF Ctrl wrap length: 16 */
+#define SF_CTRL_WRAP_LEN_32 2 /*!< SF Ctrl wrap length: 32 */
+#define SF_CTRL_WRAP_LEN_64 3 /*!< SF Ctrl wrap length: 64 */
+#define SF_CTRL_WRAP_LEN_128 4 /*!< SF Ctrl wrap length: 128 */
+#define SF_CTRL_WRAP_LEN_256 5 /*!< SF Ctrl wrap length: 256 */
+#define SF_CTRL_WRAP_LEN_512 6 /*!< SF Ctrl wrap length: 512 */
+#define SF_CTRL_WRAP_LEN_1024 7 /*!< SF Ctrl wrap length: 1024 */
+#define SF_CTRL_WRAP_LEN_2048 8 /*!< SF Ctrl wrap length: 2048 */
+#define SF_CTRL_WRAP_LEN_4096 9 /*!< SF Ctrl wrap length: 4096 */
+
+/**
+ * @brief Serail flash controller memory remap type define
+ */
+#define SF_CTRL_ORIGINAL_MEMORY_MAP 0 /*!< Remap none, use two addr map when use dual flash */
+#define SF_CTRL_REMAP_16MB 1 /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */
+#define SF_CTRL_REMAP_8MB 2 /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */
+#define SF_CTRL_REMAP_4MB 3 /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */
+
+/**
+ * @brief Serial flash controller select clock type definition
+ */
+#define SF_CTRL_OWNER_SAHB 0 /*!< System AHB bus control serial flash controller */
+#define SF_CTRL_OWNER_IAHB 1 /*!< I-Code AHB bus control serial flash controller */
+
+/**
+ * @brief Serial flash controller select clock type definition
+ */
+#define SF_CTRL_SAHB_CLOCK 0 /*!< Serial flash controller select default sahb clock */
+#define SF_CTRL_FLASH_CLOCK 1 /*!< Serial flash controller select flash clock */
+
+/**
+ * @brief Read and write type definition
+ */
+#define SF_CTRL_READ 0 /*!< Serail flash read command flag */
+#define SF_CTRL_WRITE 1 /*!< Serail flash write command flag */
+
+/**
+ * @brief Serail flash interface IO type definition
+ */
+#define SF_CTRL_NIO_MODE 0 /*!< Normal IO mode define */
+#define SF_CTRL_DO_MODE 1 /*!< Dual Output mode define */
+#define SF_CTRL_QO_MODE 2 /*!< Quad Output mode define */
+#define SF_CTRL_DIO_MODE 3 /*!< Dual IO mode define */
+#define SF_CTRL_QIO_MODE 4 /*!< Quad IO mode define */
+
+/**
+ * @brief Serail flash controller interface mode type definition
+ */
+#define SF_CTRL_SPI_MODE 0 /*!< SPI mode define */
+#define SF_CTRL_QPI_MODE 1 /*!< QPI mode define */
+
+/**
+ * @brief Serail flash controller command mode type definition
+ */
+#define SF_CTRL_CMD_1_LINE 0 /*!< Command in one line mode */
+#define SF_CTRL_CMD_4_LINES 1 /*!< Command in four lines mode */
+
+/**
+ * @brief Serail flash controller address mode type definition
+ */
+#define SF_CTRL_ADDR_1_LINE 0 /*!< Address in one line mode */
+#define SF_CTRL_ADDR_2_LINES 1 /*!< Address in two lines mode */
+#define SF_CTRL_ADDR_4_LINES 2 /*!< Address in four lines mode */
+
+/**
+ * @brief Serail flash controller dummy mode type definition
+ */
+#define SF_CTRL_DUMMY_1_LINE 0 /*!< Dummy in one line mode */
+#define SF_CTRL_DUMMY_2_LINES 1 /*!< Dummy in two lines mode */
+#define SF_CTRL_DUMMY_4_LINES 2 /*!< Dummy in four lines mode */
+
+/**
+ * @brief Serail flash controller data mode type definition
+ */
+#define SF_CTRL_DATA_1_LINE 0 /*!< Data in one line mode */
+#define SF_CTRL_DATA_2_LINES 1 /*!< Data in two lines mode */
+#define SF_CTRL_DATA_4_LINES 2 /*!< Data in four lines mode */
+
+/**
+ * @brief Serail flash controller AES mode type definition
+ */
+#define SF_CTRL_AES_CTR_MODE 0 /*!< Serail flash AES CTR mode */
+#define SF_CTRL_AES_XTS_MODE 1 /*!< Serail flash AES XTS mode */
+
+/**
+ * @brief Serail flash controller AES key len type definition
+ */
+#define SF_CTRL_AES_128BITS 0 /*!< Serail flash AES key 128 bits length */
+#define SF_CTRL_AES_256BITS 1 /*!< Serail flash AES key 256 bits length */
+#define SF_CTRL_AES_192BITS 2 /*!< Serail flash AES key 192 bits length */
+#define SF_CTRL_AES_128BITS_DOUBLE_KEY 3 /*!< Serail flash AES key 128 bits length double key */
+
+/**
+ * @brief Serail flash controller configuration structure type definition
+ */
+struct sf_ctrl_cfg_type {
+ uint8_t owner; /*!< Sflash interface bus owner */
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+ uint8_t en32b_addr; /*!< Sflash enable 32-bits address */
+#endif
+ uint8_t clk_delay; /*!< Clock count for read due to pad delay */
+ uint8_t clk_invert; /*!< Clock invert */
+ uint8_t rx_clk_invert; /*!< RX clock invert */
+ uint8_t do_delay; /*!< Data out delay */
+ uint8_t di_delay; /*!< Data in delay */
+ uint8_t oe_delay; /*!< Output enable delay */
+};
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+/**
+ * @brief SF Ctrl bank2 controller configuration structure type definition
+ */
+struct sf_ctrl_bank2_cfg {
+ uint8_t sbus2_select; /*!< Select sbus2 as 2nd flash controller */
+ uint8_t bank2_rx_clk_invert_src; /*!< Select bank2 rx clock invert source */
+ uint8_t bank2_rx_clk_invert_sel; /*!< Select inveted bank2 rx clock */
+ uint8_t bank2_delay_src; /*!< Select bank2 read delay source */
+ uint8_t bank2_clk_delay; /*!< Bank2 read delay cycle = n + 1 */
+ uint8_t do_delay; /*!< Data out delay */
+ uint8_t di_delay; /*!< Data in delay */
+ uint8_t oe_delay; /*!< Output enable delay */
+ uint8_t remap; /*!< Select dual flash memory remap set */
+ uint8_t remap_lock; /*!< Select memory remap lock */
+};
+#endif
+
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+/**
+ * @brief SF Ctrl psram controller configuration structure type definition
+ */
+struct sf_ctrl_psram_cfg {
+ uint8_t owner; /*!< Psram interface bus owner */
+ uint8_t pad_sel; /*!< SF Ctrl pad select */
+ uint8_t bank_sel; /*!< SF Ctrl bank select */
+ uint8_t psram_rx_clk_invert_src; /*!< Select psram rx clock invert source */
+ uint8_t psram_rx_clk_invert_sel; /*!< Select inveted psram rx clock */
+ uint8_t psram_delay_src; /*!< Select psram read delay source */
+ uint8_t psram_clk_delay; /*!< Psram read delay cycle = n + 1 */
+} ;
+#endif
+
+/**
+ * @brief SF Ctrl cmds configuration structure type definition
+ */
+struct sf_ctrl_cmds_cfg {
+ uint8_t ack_latency; /*!< SF Ctrl ack latency cycles */
+ uint8_t cmds_core_en; /*!< SF Ctrl cmds core enable */
+#if defined(BL702)
+ uint8_t burst_toggle_en; /*!< SF Ctrl burst toggle mode enable */
+#endif
+ uint8_t cmds_en; /*!< SF Ctrl cmds enable */
+ uint8_t cmds_wrap_mode; /*!< SF Ctrl cmds wrap mode */
+ uint8_t cmds_wrap_len; /*!< SF Ctrl cmds wrap length */
+};
+
+/**
+ * @brief Serail flash command configuration structure type definition
+ */
+struct sf_ctrl_cmd_cfg_type {
+ uint8_t rw_flag; /*!< Read write flag */
+ uint8_t cmd_mode; /*!< Command mode */
+ uint8_t addr_mode; /*!< Address mode */
+ uint8_t addr_size; /*!< Address size */
+ uint8_t dummy_clks; /*!< Dummy clocks */
+ uint8_t dummy_mode; /*!< Dummy mode */
+ uint8_t data_mode; /*!< Data mode */
+ uint8_t rsv[1]; /*!< Reserved */
+ uint32_t nb_data; /*!< Transfer number of bytes */
+ uint32_t cmd_buf[2]; /*!< Command buffer */
+};
+
+/*@} end of group SF_CTRL_Public_Types */
+
+/** @defgroup SF_CTRL_Public_Macros
+ * @{
+ */
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000)
+#else
+#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000)
+#endif
+#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF
+#define NOR_FLASH_CTRL_BUF_SIZE 256
+#define NAND_FLASH_CTRL_BUF_SIZE 512
+
+#if defined(BL628) || defined(BL616)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO3IO0) || \
+ ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS) || \
+ ((type) == SF_IO_EMB_SWAP_NONE) || \
+ ((type) == SF_IO_EMB_SWAP_IO2CS) || \
+ ((type) == SF_IO_EXT_SF2_SWAP_IO3IO0) || \
+ ((type) == SF_IO_EXT_SF3) || \
+ ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0) || \
+ ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0) || \
+ ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0) || \
+ ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) || \
+ ((type) == SF_IO_EXT_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2))
+#elif defined(BL808) || defined(BL606P)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \
+ ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \
+ ((type) == SF_IO_EMB_SWAP_NONE) || \
+ ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \
+ ((type) == SF_IO_EXT_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \
+ ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2))
+#elif defined(BL702L)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_EXTERNAL_FLASH) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) || \
+ ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH))
+#elif defined(BL702)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_SF1) || \
+ ((type) == SF_CTRL_SEL_SF2) || \
+ ((type) == SF_CTRL_SEL_SF3) || \
+ ((type) == SF_CTRL_SEL_DUAL_BANK_SF1_SF2) || \
+ ((type) == SF_CTRL_SEL_DUAL_BANK_SF2_SF3) || \
+ ((type) == SF_CTRL_SEL_DUAL_BANK_SF3_SF1) || \
+ ((type) == SF_CTRL_SEL_DUAL_CS_SF2) || \
+ ((type) == SF_CTRL_SEL_DUAL_CS_SF3))
+#elif defined(BL602)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \
+ ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \
+ ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL))
+#endif
+
+/*@} end of group SF_CTRL_Public_Macros */
+
+/** @defgroup SF_CTRL_Public_Functions
+ * @{
+ */
+void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg);
+void bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t dodelay, uint8_t didelay, uint8_t oedelay);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2cfg);
+void bflb_sf_ctrl_sbus2_hold_sram(void);
+void bflb_sf_ctrl_sbus2_release_sram(void);
+uint8_t sf_ctrl_is_sbus2_enable(void);
+void bflb_sf_ctrl_sbus2_replace(uint8_t pad);
+void bflb_sf_ctrl_sbus2_revoke_replace(void);
+void bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert);
+void bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock);
+#endif
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+void bflb_sf_ctrl_32bits_addr_en(uint8_t en_32bit_saddr);
+#endif
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg);
+#endif
+uint8_t bflb_sf_ctrl_get_clock_delay(void);
+void bflb_sf_ctrl_set_clock_delay(uint8_t delay);
+uint8_t bflb_sf_ctrl_get_wrap_queue_value(void);
+void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel);
+#if defined(BL702L)
+void bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode);
+#endif
+void bflb_sf_ctrl_select_pad(uint8_t sel);
+void bflb_sf_ctrl_sbus_select_bank(uint8_t bank);
+void bflb_sf_ctrl_set_owner(uint8_t owner);
+void bflb_sf_ctrl_disable(void);
+void bflb_sf_ctrl_aes_enable_be(void);
+void bflb_sf_ctrl_aes_enable_le(void);
+void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwkey,
+ uint32_t start_addr, uint32_t end_addr, uint8_t locked);
+void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+#ifdef BFLB_SF_CTRL_AES_XTS_ENABLE
+void bflb_sf_ctrl_aes_xts_set_key(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_xts_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_xts_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+void bflb_sf_ctrl_aes_xts_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+#endif
+void bflb_sf_ctrl_aes_set_mode(uint8_t mode);
+void bflb_sf_ctrl_aes_enable(void);
+void bflb_sf_ctrl_aes_disable(void);
+uint8_t bflb_sf_ctrl_is_aes_enable(void);
+void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank);
+uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank);
+void bflb_sf_ctrl_lock_flash_image_offset(uint8_t lock);
+void bflb_sf_ctrl_select_clock(uint8_t sahb_sram_sel);
+void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg);
+void bflb_sf_ctrl_disable_wrap_access(uint8_t disable);
+void bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+#endif
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+void bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+void bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+#endif
+uint8_t bflb_sf_ctrl_get_busy_state(void);
+#ifndef BFLB_USE_HAL_DRIVER
+void bflb_sf_ctrl_irqhandler(void);
+#endif
+
+/*@} end of group SF_CTRL_Public_Functions */
+
+/*@} end of group SF_CTRL */
+
+/*@} end of group BL628_Peripheral_Driver */
+
+#endif /* __BL628_SF_CTRL_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sflash.c b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sflash.c
new file mode 100644
index 00000000..a97f9de4
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sflash.c
@@ -0,0 +1,2182 @@
+/**
+ ******************************************************************************
+ * @file bflb_sflash.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "bflb_sf_ctrl.h"
+#include "bflb_sflash.h"
+//#include "bl628_l1c.h"
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SFLASH
+ * @{
+ */
+
+/** @defgroup SFLASH_Private_Macros
+ * @{
+ */
+
+#if defined(BL602) || defined(BL702)
+#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#elif defined(BL702L)
+#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x4000B600)
+#elif defined(BL606P) || defined(BL808) || defined(BL616)
+#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x2000b600)
+#elif defined(BL628)
+#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x20082600)
+#endif
+
+/*@} end of group SFLASH_Private_Macros */
+
+/** @defgroup SFLASH_Private_Types
+ * @{
+ */
+
+/*@} end of group SFLASH_Private_Types */
+
+/** @defgroup SFLASH_Private_Variables
+ * @{
+ */
+
+/*@} end of group SFLASH_Private_Variables */
+
+/** @defgroup SFLASH_Global_Variables
+ * @{
+ */
+
+/*@} end of group SFLASH_Global_Variables */
+
+/** @defgroup SFLASH_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group SFLASH_Private_Fun_Declaration */
+
+/** @defgroup SFLASH_Private_Functions
+ * @{
+ */
+
+/*@} end of group SFLASH_Private_Functions */
+
+/** @defgroup SFLASH_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Init serial flash control interface
+ *
+ * @param p_sf_ctrl_cfg: Serial flash controller configuration pointer
+ * @param p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg,
+ const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+ uint8_t clk_delay = 0;
+ uint8_t rx_clk_invert = 0;
+
+ if (p_bank2_cfg != NULL) {
+ if (p_bank2_cfg->sbus2_select) {
+ if (p_bank2_cfg->bank2_delay_src) {
+ clk_delay = p_bank2_cfg->bank2_clk_delay;
+ } else {
+ if (p_sf_ctrl_cfg != NULL) {
+ clk_delay = p_sf_ctrl_cfg->clk_delay;
+ } else {
+ clk_delay = 1;
+ }
+ }
+
+ if (p_bank2_cfg->bank2_rx_clk_invert_src) {
+ rx_clk_invert = p_bank2_cfg->bank2_rx_clk_invert_sel;
+ } else {
+ if (p_sf_ctrl_cfg != NULL) {
+ rx_clk_invert = p_sf_ctrl_cfg->rx_clk_invert;
+ } else {
+ rx_clk_invert = 0;
+ }
+ }
+
+ bflb_sf_ctrl_sbus2_set_delay(clk_delay, rx_clk_invert);
+ } else {
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ }
+
+ bflb_sf_ctrl_bank2_enable(p_bank2_cfg);
+ } else {
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ }
+#else
+void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg)
+{
+#endif
+
+ if (p_sf_ctrl_cfg != NULL) {
+ bflb_sf_ctrl_enable(p_sf_ctrl_cfg);
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Set serial flash control interface SPI or QPI mode
+ *
+ * @param mode: Serial flash interface mode
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_set_spi_mode(uint8_t mode)
+{
+ int stat = 0;
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief Read flash register
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param reg_index: register index
+ * @param reg_value: register value pointer to store data
+ * @param reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index,
+ uint8_t *reg_value, uint8_t reg_len)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint32_t cnt = 0;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (flash_cfg->read_reg_cmd[reg_index]) << 24;
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.nb_data = reg_len;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ arch_delay_us(1);
+ cnt++;
+
+ if (cnt > 1000) {
+ return -1;
+ }
+ }
+
+ arch_memcpy(reg_value, flash_ctrl_buf, reg_len);
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Write flash register
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param reg_index: register index
+ * @param reg_value: register value pointer storing data
+ * @param reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index,
+ uint8_t *reg_value, uint8_t reg_len)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint32_t cnt = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ arch_memcpy(flash_ctrl_buf, reg_value, reg_len);
+
+ flash_cmd.cmd_buf[0] = (flash_cfg->write_reg_cmd[reg_index]) << 24;
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ flash_cmd.nb_data = reg_len;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ /* take 40ms for tw(write status register) as default */
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(100);
+ cnt++;
+
+ if (cnt > 400) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Read flash register with read command
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param read_reg_cmd: read command
+ * @param reg_value: register value pointer to store data
+ * @param reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg,
+ uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint32_t cnt = 0;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = read_reg_cmd << 24;
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.nb_data = reg_len;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ arch_delay_us(1);
+ cnt++;
+
+ if (cnt > 1000) {
+ return -1;
+ }
+ }
+
+ arch_memcpy(reg_value, flash_ctrl_buf, reg_len);
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Write flash register with write command
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param write_reg_cmd: write command
+ * @param reg_value: register value pointer storing data
+ * @param reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg,
+ uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint32_t cnt = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ arch_memcpy(flash_ctrl_buf, reg_value, reg_len);
+
+ flash_cmd.cmd_buf[0] = write_reg_cmd << 24;
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ flash_cmd.nb_data = reg_len;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ /* take 40ms for tw(write status register) as default */
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(100);
+ cnt++;
+
+ if (cnt > 400) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Check flash busy status
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return 1 means busy or 0 means not busy
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_busy(spi_flash_cfg_type *flash_cfg)
+{
+ uint32_t stat = 0;
+ bflb_sflash_read_reg(flash_cfg, flash_cfg->busy_index, (uint8_t *)&stat, flash_cfg->busy_read_reg_len);
+
+ if ((stat & (1 << flash_cfg->busy_bit)) == 0) {
+ return 0;
+ }
+
+ return 1;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable flash write function
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+ uint32_t stat = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ /* Write enable*/
+ flash_cmd.cmd_buf[0] = (flash_cfg->write_enable_cmd) << 24;
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ bflb_sflash_read_reg(flash_cfg, flash_cfg->wr_enable_index, (uint8_t *)&stat, flash_cfg->wr_enable_read_reg_len);
+
+ if ((stat & (1 << flash_cfg->wr_enable_bit)) != 0) {
+ return 0;
+ }
+
+ return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable flash flash controller QSPI interface
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg)
+{
+ uint32_t stat = 0, ret = 0;
+
+ if (flash_cfg->qe_read_reg_len == 0) {
+ ret = bflb_sflash_write_enable(flash_cfg);
+
+ if (0 != ret) {
+ return -1;
+ }
+
+ bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+ return 0;
+ }
+
+ bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+ if (flash_cfg->qe_data == 0) {
+ if ((stat & (1 << flash_cfg->qe_bit)) != 0) {
+ return 0;
+ }
+ } else {
+ if (((stat >> (flash_cfg->qe_bit & 0x08)) & 0xff) == flash_cfg->qe_data) {
+ return 0;
+ }
+ }
+
+ if (flash_cfg->qe_write_reg_len != 1) {
+ /* This is read r0,read r1 write r0,r1 case*/
+ bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1);
+ bflb_sflash_read_reg(flash_cfg, 1, ((uint8_t *)&stat) + 1, 1);
+
+ if (flash_cfg->qe_data == 0) {
+ stat |= (1 << (flash_cfg->qe_bit + 8 * flash_cfg->qe_index));
+ } else {
+ stat = stat & (~(0xff << (8 * flash_cfg->qe_index)));
+ stat |= (flash_cfg->qe_data << (8 * flash_cfg->qe_index));
+ }
+ } else {
+ if (flash_cfg->qe_data == 0) {
+ stat |= (1 << (flash_cfg->qe_bit % 8));
+ } else {
+ stat = flash_cfg->qe_data;
+ }
+ }
+
+ ret = bflb_sflash_write_enable(flash_cfg);
+
+ if (0 != ret) {
+ return -1;
+ }
+
+ bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+ bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+ if (flash_cfg->qe_data == 0) {
+ if ((stat & (1 << flash_cfg->qe_bit)) != 0) {
+ return 0;
+ }
+ } else {
+ if (((stat >> (flash_cfg->qe_bit & 0x08)) & 0xff) == flash_cfg->qe_data) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief Disable flash flash controller QSPI interface
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg)
+{
+ uint32_t stat = 0, ret = 0;
+
+ if (flash_cfg->qe_read_reg_len == 0) {
+ ret = bflb_sflash_write_enable(flash_cfg);
+
+ if (0 != ret) {
+ return -1;
+ }
+
+ bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+ return 0;
+ }
+
+ bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+ if ((stat & (1 << flash_cfg->qe_bit)) == 0) {
+ return 0;
+ }
+
+ if (flash_cfg->qe_write_reg_len != 1) {
+ /* This is read r0,read r1 write r0,r1 case*/
+ bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1);
+ bflb_sflash_read_reg(flash_cfg, 1, ((uint8_t *)&stat) + 1, 1);
+ stat &= (~(1 << (flash_cfg->qe_bit + 8 * flash_cfg->qe_index)));
+ } else {
+ stat &= (~(1 << (flash_cfg->qe_bit % 8)));
+ }
+
+ ret = bflb_sflash_write_enable(flash_cfg);
+
+ if (0 != ret) {
+ return -1;
+ }
+
+ bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+ bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+ if ((stat & (1 << flash_cfg->qe_bit)) == 0) {
+ return 0;
+ }
+
+ return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable flash volatile register write enable
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (flash_cfg->write_vreg_enable_cmd) << 24;
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief Erase flash whole chip
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg)
+{
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint32_t cnt = 0;
+ uint32_t timeout = 0;
+ int stat = bflb_sflash_write_enable(flash_cfg);
+
+ if (stat != 0) {
+ return stat;
+ }
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (flash_cfg->chip_erase_cmd) << 24;
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = flash_cfg->time_ce;
+
+ if ((timeout >> 15) > 0) {
+ timeout = (timeout & 0x7FFF) * 1000;
+ }
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(500);
+ cnt++;
+
+ if (cnt > timeout * 3) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Erase flash one sector
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param sector_num: flash sector number
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num)
+{
+ uint32_t cnt = 0;
+ uint8_t is_32bits_addr = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ int stat = bflb_sflash_write_enable(flash_cfg);
+
+ if (stat != 0) {
+ return stat;
+ }
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ is_32bits_addr = (flash_cfg->io_mode & 0x20);
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = 3;
+
+ if (is_32bits_addr > 0) {
+ flash_cmd.addr_size++;
+ flash_cmd.cmd_buf[0] = (flash_cfg->sector_erase_cmd << 24) | ((flash_cfg->sector_size * 1024 * sector_num) >> 8);
+ flash_cmd.cmd_buf[1] = ((flash_cfg->sector_size * 1024 * sector_num) << 24);
+ } else {
+ flash_cmd.cmd_buf[0] = (flash_cfg->sector_erase_cmd << 24) | (flash_cfg->sector_size * 1024 * sector_num);
+ }
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(500);
+ cnt++;
+
+ if (cnt > flash_cfg->time_e_sector * 3) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Erase flash one 32K block
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param blk_num: flash 32K block number
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
+{
+ uint32_t cnt = 0;
+ uint8_t is_32bits_addr = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ int stat = bflb_sflash_write_enable(flash_cfg);
+
+ if (stat != 0) {
+ return stat;
+ }
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ is_32bits_addr = (flash_cfg->io_mode & 0x20);
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = 3;
+
+ if (is_32bits_addr > 0) {
+ flash_cmd.addr_size++;
+ flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) >> 8);
+ flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) << 24);
+ } else {
+ flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blk_num);
+ }
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(500);
+ cnt++;
+
+ if (cnt > flash_cfg->time_e_32k * 3) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Erase flash one 64K block
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param blk_num: flash 64K block number
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
+{
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint32_t cnt = 0;
+ uint8_t is_32bits_addr = 0;
+ int stat = bflb_sflash_write_enable(flash_cfg);
+
+ if (stat != 0) {
+ return stat;
+ }
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ is_32bits_addr = (flash_cfg->io_mode & 0x20);
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = 3;
+
+ if (is_32bits_addr > 0) {
+ flash_cmd.addr_size++;
+ flash_cmd.cmd_buf[0] = (flash_cfg->blk64_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blk_num) >> 8);
+ flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blk_num) << 24);
+ } else {
+ flash_cmd.cmd_buf[0] = (flash_cfg->blk64_erase_cmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blk_num);
+ }
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(500);
+ cnt++;
+
+ if (cnt > flash_cfg->time_e_64k * 3) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Erase flash one region
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param start_addr: start address to erase
+ * @param end_addr: end address(include this address) to erase
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr)
+{
+ uint32_t len = 0;
+ uint32_t erase_len = 0;
+ uint8_t ret = 0;
+
+ if (start_addr > end_addr) {
+ return -1;
+ }
+
+ while (start_addr <= end_addr) {
+ len = end_addr - start_addr + 1;
+
+ if (flash_cfg->blk64_erase_cmd != BFLB_SPIFLASH_CMD_INVALID &&
+ (start_addr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 &&
+ len > (BFLB_SPIFLASH_BLK64K_SIZE - flash_cfg->sector_size * 1024)) {
+ /* 64K margin address,and length > 64K-sector size, erase one first */
+ ret = bflb_sflash_blk64_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK64K_SIZE);
+ erase_len = BFLB_SPIFLASH_BLK64K_SIZE;
+ } else if (flash_cfg->blk32_erase_cmd != BFLB_SPIFLASH_CMD_INVALID &&
+ (start_addr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 &&
+ len > (BFLB_SPIFLASH_BLK32K_SIZE - flash_cfg->sector_size * 1024)) {
+ /* 32K margin address,and length > 32K-sector size, erase one first */
+ ret = bflb_sflash_blk32_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK32K_SIZE);
+ erase_len = BFLB_SPIFLASH_BLK32K_SIZE;
+ } else {
+ /* Sector erase */
+ start_addr = ((start_addr) & (~(flash_cfg->sector_size * 1024 - 1)));
+ ret = bflb_sflash_sector_erase(flash_cfg, start_addr / flash_cfg->sector_size / 1024);
+ erase_len = flash_cfg->sector_size * 1024;
+ }
+
+ start_addr += erase_len;
+
+ if (ret != 0) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Get flash unique ID
+ *
+ * @param data: data pointer to store read data
+ * @param id_len: unique ID len
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint8_t cmd = 0, dummy_clks = 0;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ dummy_clks = 4;
+ cmd = 0x4B;
+ flash_cmd.cmd_buf[0] = (cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.dummy_clks = dummy_clks;
+ flash_cmd.nb_data = id_len;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return;
+ }
+ }
+
+ arch_memcpy(data, flash_ctrl_buf, id_len);
+}
+
+/****************************************************************************/ /**
+ * @brief Get flash jedec ID
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param data: data pointer to store read data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint8_t cmd = 0, dummy_clks = 0;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ dummy_clks = flash_cfg->jedec_id_cmd_dmy_clk;
+ cmd = flash_cfg->jedec_id_cmd;
+ flash_cmd.cmd_buf[0] = (cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.dummy_clks = dummy_clks;
+ flash_cmd.nb_data = 3;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return;
+ }
+ }
+
+ arch_memcpy(data, flash_ctrl_buf, 3);
+}
+
+/****************************************************************************/ /**
+ * @brief Get flash device ID
+ *
+ * @param data: data pointer to store read data
+ * @param is_32bits_addr: Is flash addr mode in 32-bits
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint8_t cmd = 0, dummy_clks = 0;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint32_t addr = 0x00000001;
+ uint8_t read_mode = 0xFF;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ dummy_clks = 2;
+ cmd = 0x94;
+ flash_cmd.addr_size = 4;
+
+ if (is_32bits_addr) {
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+ flash_cmd.cmd_buf[1] = (addr << 24) | (read_mode << 16);
+ flash_cmd.addr_size++;
+ } else {
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+ flash_cmd.cmd_buf[1] = (read_mode << 24);
+ }
+
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.dummy_clks = dummy_clks;
+ flash_cmd.nb_data = 2;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return;
+ }
+ }
+
+ arch_memcpy(data, flash_ctrl_buf, 2);
+}
+
+/****************************************************************************/ /**
+ * @brief Set flash power down
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_powerdown(void)
+{
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint8_t cmd = 0;
+ uint32_t timeout = 0;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ cmd = 0xB9;
+ flash_cmd.cmd_buf[0] = (cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return;
+ }
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Release flash power down for wake up
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg)
+{
+ uint8_t cmd = 0;
+ uint32_t timeout = 0;
+
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ cmd = flash_cfg->release_powerdown;
+ flash_cmd.cmd_buf[0] = (cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return;
+ }
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Sflash restore from power down
+ *
+ * @param flash_cfg: Flash configuration pointer
+ * @param flash_cont_read: Whether enable continuous read
+ * @param bank: bank select type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg,
+ uint8_t flash_cont_read, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t jedecid = 0;
+ uint8_t tmp[8];
+ uint8_t io_mode = flash_cfg->io_mode & 0xf;
+
+ /* Wake flash up from power down */
+ bflb_sflash_release_powerdown(flash_cfg);
+ arch_delay_us(120);
+
+ bflb_sflash_get_jedecid(flash_cfg, (uint8_t *)&jedecid);
+
+ if (SF_CTRL_QO_MODE == io_mode || SF_CTRL_QIO_MODE == io_mode) {
+ bflb_sflash_qspi_enable(flash_cfg);
+ }
+
+ if (((flash_cfg->io_mode >> 4) & 0x01) == 1) {
+ /* unwrap */
+ //L1C_Set_Wrap(0);
+ } else {
+ /* burst wrap */
+ //L1C_Set_Wrap(1);
+ /* For command that is setting register instead of send command, we need write enable */
+ bflb_sflash_write_enable(flash_cfg);
+ bflb_sflash_set_burst_wrap(flash_cfg);
+ }
+
+ if (flash_cont_read) {
+ stat = bflb_sflash_read(flash_cfg, io_mode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+ stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, 0, 0, 32, bank);
+ }
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief Set flash burst wrap config
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint8_t cmd = 0, dummy_clks = 0;
+ uint32_t wrap_data = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((flash_cfg->io_mode >> 4) & 0x01) == 1) {
+ /* Disable burst wrap ,just return */
+ return;
+ }
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.addr_mode = flash_cfg->burst_wrap_data_mode;
+ flash_cmd.data_mode = flash_cfg->burst_wrap_data_mode;
+ dummy_clks = flash_cfg->burst_wrap_cmd_dmy_clk;
+ cmd = flash_cfg->burst_wrap_cmd;
+ wrap_data = flash_cfg->burst_wrap_data;
+ arch_memcpy4((uint32_t *)flash_ctrl_buf, &wrap_data, 4);
+ flash_cmd.cmd_buf[0] = (cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ flash_cmd.dummy_clks = dummy_clks;
+ flash_cmd.nb_data = 1;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief Disable flash burst wrap config
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint8_t cmd = 0, dummy_clks = 0;
+ uint32_t wrap_data = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.addr_mode = flash_cfg->de_burst_wrap_data_mode;
+ flash_cmd.data_mode = flash_cfg->de_burst_wrap_data_mode;
+ dummy_clks = flash_cfg->de_burst_wrap_cmd_dmy_clk;
+ cmd = flash_cfg->de_burst_wrap_cmd;
+ wrap_data = flash_cfg->de_burst_wrap_data;
+ arch_memcpy4((uint32_t *)flash_ctrl_buf, &wrap_data, 4);
+ flash_cmd.cmd_buf[0] = (cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ flash_cmd.dummy_clks = dummy_clks;
+ flash_cmd.nb_data = 1;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+/****************************************************************************/ /**
+ * @brief Set flash 24-bits or 32-bits addr mode
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param en_32bits_addr: Serial flash enable or disable 32-bits addr
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg,
+ uint8_t en_32bits_addr)
+{
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint8_t cmd = 0;
+
+ if ((flash_cfg->io_mode & 0x20) == 0) {
+ return -1;
+ }
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ bflb_sf_ctrl_32bits_addr_en(en_32bits_addr);
+
+ if (en_32bits_addr) {
+ cmd = flash_cfg->enter_32bits_addr_cmd;
+ } else {
+ cmd = flash_cfg->exit_32bits_addr_cmd;
+ }
+
+ flash_cmd.cmd_buf[0] = (cmd << 24);
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ return 0;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Software reset flash
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg)
+{
+ uint16_t cnt = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ /* Reset enable */
+ flash_cmd.cmd_buf[0] = (flash_cfg->reset_en_cmd) << 24;
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+
+ /* Wait for write done */
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(100);
+ cnt++;
+
+ if (cnt > 20) {
+ return -1;
+ }
+ }
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ /* Reset */
+ flash_cmd.cmd_buf[0] = (flash_cfg->reset_cmd) << 24;
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ arch_delay_us(50);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Reset flash continous read mode
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg)
+{
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ /* Reset continous read */
+ arch_memset(&flash_cmd.cmd_buf[0], flash_cfg->reset_c_read_cmd, 4);
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = flash_cfg->reset_c_read_cmd_size;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief Set xip read flash configuration in flash controller
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param io_mode: flash controller interface mode
+ * @param cont_read: Wether enable cont read mode
+ * @param addr: address to read/write
+ * @param len: data length to read/write
+ * @param bank: bank select type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode,
+ uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank)
+{
+ uint8_t cmd = 0, dummy_clks = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint8_t cmd_valid = 1;
+ uint8_t no_read_mode_cfg = 0;
+ uint8_t c_read_support = 0;
+ uint8_t is_32bits_addr = 0;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB);
+
+ if (SF_CTRL_NIO_MODE == io_mode) {
+ cmd = flash_cfg->fast_read_cmd;
+ dummy_clks = flash_cfg->fr_dmy_clk;
+ } else if (SF_CTRL_DO_MODE == io_mode) {
+ flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+ cmd = flash_cfg->fast_read_do_cmd;
+ dummy_clks = flash_cfg->fr_do_dmy_clk;
+ } else if (SF_CTRL_DIO_MODE == io_mode) {
+ flash_cmd.addr_mode = SF_CTRL_ADDR_2_LINES;
+ flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+ cmd = flash_cfg->fast_read_dio_cmd;
+ dummy_clks = flash_cfg->fr_dio_dmy_clk;
+ } else if (SF_CTRL_QO_MODE == io_mode) {
+ flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = flash_cfg->fast_read_qo_cmd;
+ dummy_clks = flash_cfg->fr_qo_dmy_clk;
+ } else if (SF_CTRL_QIO_MODE == io_mode) {
+ flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = flash_cfg->fast_read_qio_cmd;
+ dummy_clks = flash_cfg->fr_qio_dmy_clk;
+ } else {
+ return -1;
+ }
+
+ is_32bits_addr = (flash_cfg->io_mode & 0x20);
+ /*prepare command**/
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = 3;
+
+ if (is_32bits_addr > 0) {
+ flash_cmd.addr_size++;
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+ flash_cmd.cmd_buf[1] = (addr << 24);
+ } else {
+ flash_cmd.cmd_buf[0] = (cmd << 24) | addr;
+ }
+
+ if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) {
+ no_read_mode_cfg = flash_cfg->c_read_support & 0x02;
+ c_read_support = flash_cfg->c_read_support & 0x01;
+
+ if (no_read_mode_cfg == 0) {
+ /* Read mode must be set*/
+ if (c_read_support == 0) {
+ /* Not support cont read,but we still need set read mode(winbond 80dv)*/
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16);
+ } else {
+ flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+ }
+ } else {
+ /* Flash support cont read, setting depend on user parameter */
+ if (cont_read) {
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[0] = addr;
+ flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+ } else {
+ flash_cmd.cmd_buf[0] = (addr << 8) | flash_cfg->c_read_mode;
+ }
+
+ cmd_valid = 0;
+ } else {
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[1] |= ((!flash_cfg->c_read_mode) << 16);
+ } else {
+ flash_cmd.cmd_buf[1] = ((!flash_cfg->c_read_mode) << 24);
+ }
+ }
+ }
+
+ flash_cmd.addr_size++;
+ }
+ }
+
+ flash_cmd.dummy_clks = dummy_clks;
+ flash_cmd.nb_data = len;
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+ if (bank == SF_CTRL_FLASH_BANK0) {
+ bflb_sf_ctrl_xip_set(&flash_cmd, cmd_valid);
+ } else {
+ bflb_sf_ctrl_xip2_set(&flash_cmd, cmd_valid);
+ }
+#else
+ bflb_sf_ctrl_xip_set(&flash_cmd, cmd_valid);
+#endif
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable xip read from flash
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param io_mode: flash controller interface mode
+ * @param cont_read: Wether enable cont read mode
+ * @param bank: bank select type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg,
+ uint8_t io_mode, uint8_t cont_read, uint8_t bank)
+{
+ int stat = 0;
+
+ stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, cont_read, 0, 32, bank);
+ if (0 != stat) {
+ return stat;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Disable read from flash with xip
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_xip_read_disable(void)
+{
+
+}
+
+/****************************************************************************/ /**
+ * @brief Sflash enable RCV mode to recovery for erase while power drop
+ *
+ * @param flash_cfg: Flash configuration pointer
+ * @param r_cmd: Read RCV register cmd
+ * @param w_cmd: Write RCV register cmd
+ * @param bit_pos: RCV register bit pos
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd,
+ uint8_t w_cmd, uint8_t bit_pos)
+{
+ int stat = 0;
+ uint32_t cnt = 0;
+ uint32_t temp_val = 0;
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(500);
+ cnt++;
+
+ if (cnt > 20000 * 3) {
+ return -1;
+ }
+ }
+
+ stat = bflb_sflash_read_reg_with_cmd(flash_cfg, r_cmd, (uint8_t *)&temp_val, 1);
+ if (0 != stat) {
+ stat = -1;
+ }
+
+ if (((temp_val >> bit_pos) & 0x01) > 0) {
+ return 0;
+ }
+
+ temp_val |= (uint32_t)(1 << bit_pos);
+ stat = bflb_sflash_write_enable(flash_cfg);
+ if (0 != stat) {
+ stat = -1;
+ }
+
+ stat = bflb_sflash_write_reg_with_cmd(flash_cfg, w_cmd, (uint8_t *)&temp_val, 1);
+ if (0 != stat) {
+ return stat;
+ }
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(500);
+ cnt++;
+
+ if (cnt > 20000 * 3) {
+ return -1;
+ }
+ }
+
+ stat = bflb_sflash_read_reg_with_cmd(flash_cfg, r_cmd, (uint8_t *)&temp_val, 1);
+ if (0 != stat) {
+ stat = -1;
+ }
+
+ if (((temp_val >> bit_pos) & 0x01) <= 0) {
+ return -1;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Erase flash security register one block
+ *
+ * @param flash_cfg: Flash configuration pointer
+ * @param p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg,
+ struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+ int stat = 0;
+ uint32_t cnt = 0;
+ uint8_t cmd = 0;
+ uint8_t sec_opt_mode = 0;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+ sec_opt_mode = 1;
+
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+ }
+
+ stat = bflb_sflash_write_enable(flash_cfg);
+ if (stat != 0) {
+ return stat;
+ }
+
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ cmd = p_sec_reg_cfg->erase_cmd;
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (p_sec_reg_cfg->block_num << 12);
+ /* rw_flag don't care */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = 3;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(500);
+ cnt++;
+
+ if (cnt > flash_cfg->time_e_sector * 3) {
+ return -1;
+ }
+ }
+
+ if (sec_opt_mode > 0) {
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Program flash security register one block
+ *
+ * @param flash_cfg: Flash configuration pointer
+ * @param p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg,
+ struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint32_t i = 0, cur_len = 0;
+ uint32_t cnt = 0;
+ int stat = 0;
+ uint8_t cmd = 0;
+ uint8_t sec_opt_mode = 0;
+ uint8_t *data = p_sec_reg_cfg->data;
+ uint32_t addr = p_sec_reg_cfg->addr;
+ uint32_t len = p_sec_reg_cfg->len;
+ uint32_t current_addr = 0;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+ sec_opt_mode = 1;
+
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+ }
+
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ /* Prepare command */
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ flash_cmd.addr_size = 3;
+ cmd = p_sec_reg_cfg->program_cmd;
+
+ for (i = 0; i < len;) {
+ /* Write enable is needed for every program */
+ stat = bflb_sflash_write_enable(flash_cfg);
+
+ if (stat != 0) {
+ return stat;
+ }
+
+ /* Get current programmed length within page size */
+ cur_len = 256 - addr % 256;
+
+ if (cur_len > len - i) {
+ cur_len = len - i;
+ }
+
+ current_addr = (p_sec_reg_cfg->block_num << 12) | addr;
+
+ /* Prepare command */
+ arch_memcpy_fast(flash_ctrl_buf, data, cur_len);
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr);
+ flash_cmd.nb_data = cur_len;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ /* Adjust address and programmed length */
+ addr += cur_len;
+ i += cur_len;
+ data += cur_len;
+
+ /* Wait for write done */
+ cnt = 0;
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(100);
+ cnt++;
+
+ if (cnt > flash_cfg->time_page_pgm * 20) {
+ return -1;
+ }
+ }
+ }
+
+ if (sec_opt_mode > 0) {
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Read data from flash security register one block
+ *
+ * @param p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint32_t cur_len = 0, i = 0;
+ uint8_t cmd = 0;
+ uint8_t sec_opt_mode = 0;
+ uint8_t *data = p_sec_reg_cfg->data;
+ uint32_t addr = p_sec_reg_cfg->addr;
+ uint32_t len = p_sec_reg_cfg->len;
+ uint32_t current_addr = 0;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+ sec_opt_mode = 1;
+
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+ }
+
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ /* Prepare command */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = 3;
+ flash_cmd.dummy_clks = 1;
+ cmd = p_sec_reg_cfg->read_cmd;
+
+ /* Read data */
+ for (i = 0; i < len;) {
+ current_addr = (p_sec_reg_cfg->block_num << 12) | addr;
+ /* Prepare command */
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr);
+ cur_len = len - i;
+
+ if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
+ cur_len = NOR_FLASH_CTRL_BUF_SIZE;
+ flash_cmd.nb_data = cur_len;
+ } else {
+ /* Make sf_ctrl word read */
+ flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
+ }
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ arch_memcpy_fast(data, flash_ctrl_buf, cur_len);
+
+ addr += cur_len;
+ i += cur_len;
+ data += cur_len;
+ }
+
+ if (sec_opt_mode > 0) {
+ if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************//**
+ * @brief Clear flash status register
+ *
+ * @param flash_cfg: Flash configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg)
+{
+ uint32_t ret = 0;
+ uint32_t qe_value = 0;
+ uint32_t reg_value = 0;
+ uint32_t read_value = 0;
+ uint8_t read_reg_value0 = 0;
+ uint8_t read_reg_value1 = 0;
+
+ if ((flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE) {
+ qe_value = 1;
+ }
+
+ bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&read_reg_value0, 1);
+ bflb_sflash_read_reg(flash_cfg, 1, (uint8_t *)&read_reg_value1, 1);
+ read_value = (read_reg_value0|(read_reg_value1<<8));
+ if ((read_value & (~((1<<(flash_cfg->qe_index*8+flash_cfg->qe_bit)) |
+ (1<<(flash_cfg->busy_index*8+flash_cfg->busy_bit)) |
+ (1<<(flash_cfg->wr_enable_index*8+flash_cfg->wr_enable_bit))))) == 0) {
+ return 0;
+ }
+
+ ret = bflb_sflash_write_enable(flash_cfg);
+ if (0 != ret) {
+ return ret;
+ }
+ if (flash_cfg->qe_write_reg_len == 2) {
+ reg_value = (qe_value<<(flash_cfg->qe_index*8+flash_cfg->qe_bit));
+ bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 2);
+ } else {
+ if (flash_cfg->qe_index == 0) {
+ reg_value = (qe_value<qe_bit);
+ } else {
+ reg_value = 0;
+ }
+ bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 1);
+ ret = bflb_sflash_write_enable(flash_cfg);
+ if (0 != ret) {
+ return ret;
+ }
+ if (flash_cfg->qe_index == 1) {
+ reg_value = (qe_value<qe_bit);
+ } else {
+ reg_value = 0;
+ }
+ bflb_sflash_write_reg(flash_cfg, 1, (uint8_t *)®_value, 1);
+ }
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Read data from flash
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param io_mode: flash controller interface mode
+ * @param cont_read: Wether enable cont read mode
+ * @param addr: flash read start address
+ * @param data: data pointer to store data read from flash
+ * @param len: data length to read
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode,
+ uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint32_t cur_len = 0, i = 0;
+ uint8_t cmd = 0, dummy_clks = 0;
+ uint32_t timeout = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+ uint8_t no_read_mode_cfg = 0;
+ uint8_t c_read_support = 0;
+ uint8_t is_32bits_addr = 0;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ if (SF_CTRL_NIO_MODE == io_mode) {
+ cmd = flash_cfg->fast_read_cmd;
+ dummy_clks = flash_cfg->fr_dmy_clk;
+ } else if (SF_CTRL_DO_MODE == io_mode) {
+ flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+ cmd = flash_cfg->fast_read_do_cmd;
+ dummy_clks = flash_cfg->fr_do_dmy_clk;
+ } else if (SF_CTRL_DIO_MODE == io_mode) {
+ flash_cmd.addr_mode = SF_CTRL_ADDR_2_LINES;
+ flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+ cmd = flash_cfg->fast_read_dio_cmd;
+ dummy_clks = flash_cfg->fr_dio_dmy_clk;
+ } else if (SF_CTRL_QO_MODE == io_mode) {
+ flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = flash_cfg->fast_read_qo_cmd;
+ dummy_clks = flash_cfg->fr_qo_dmy_clk;
+ } else if (SF_CTRL_QIO_MODE == io_mode) {
+ flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+ flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = flash_cfg->fast_read_qio_cmd;
+ dummy_clks = flash_cfg->fr_qio_dmy_clk;
+ } else {
+ return -1;
+ }
+
+ is_32bits_addr = (flash_cfg->io_mode & 0x20);
+ /* Prepare command */
+ flash_cmd.rw_flag = SF_CTRL_READ;
+ flash_cmd.addr_size = 3;
+
+ if (is_32bits_addr > 0) {
+ flash_cmd.addr_size++;
+ }
+
+ if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) {
+ no_read_mode_cfg = flash_cfg->c_read_support & 0x02;
+ c_read_support = flash_cfg->c_read_support & 0x01;
+
+ if (no_read_mode_cfg == 0) {
+ /* Read mode must be set*/
+ if (c_read_support == 0) {
+ /* Not support cont read,but we still need set read mode(winbond 80dv)*/
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16);
+ } else {
+ flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+ }
+ } else {
+ /* Flash support cont read, setting depend on user parameter */
+ if (cont_read) {
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16);
+ } else {
+ flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+ }
+ } else {
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[1] |= ((!flash_cfg->c_read_mode) << 16);
+ } else {
+ flash_cmd.cmd_buf[1] = ((!flash_cfg->c_read_mode) << 24);
+ }
+ }
+ }
+
+ flash_cmd.addr_size++;
+ }
+ }
+
+ flash_cmd.dummy_clks = dummy_clks;
+
+ /* Read data */
+ for (i = 0; i < len;) {
+ /* Prepare command */
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+ flash_cmd.cmd_buf[1] |= (addr << 24);
+ } else {
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+ }
+
+ cur_len = len - i;
+
+ if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
+ cur_len = NOR_FLASH_CTRL_BUF_SIZE;
+ flash_cmd.nb_data = cur_len;
+ } else {
+ /* Make sf_ctrl word read */
+ flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
+ }
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+ while (bflb_sf_ctrl_get_busy_state()) {
+ timeout--;
+
+ if (timeout == 0) {
+ return -2;
+ }
+ }
+
+ arch_memcpy_fast(data, flash_ctrl_buf, cur_len);
+
+ addr += cur_len;
+ i += cur_len;
+ data += cur_len;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Program flash one region
+ *
+ * @param flash_cfg: Serial flash parameter configuration pointer
+ * @param io_mode: progran mode:SPI mode or QPI mode
+ * @param addr: start address to be programed
+ * @param data: data pointer to be programed
+ * @param len: data length to be programed
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode,
+ uint32_t addr, uint8_t *data, uint32_t len)
+{
+ uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+ uint32_t i = 0, cur_len = 0;
+ uint32_t cnt = 0;
+ int stat = 0;
+ uint8_t is_32bits_addr = 0;
+ uint8_t cmd = 0;
+ struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+ if (((uintptr_t)&flash_cmd) % 4 == 0) {
+ arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+ } else {
+ arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+ }
+
+ if (SF_CTRL_NIO_MODE == io_mode || SF_CTRL_DO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) {
+ cmd = flash_cfg->page_program_cmd;
+ } else if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_QO_MODE == io_mode) {
+ flash_cmd.addr_mode = flash_cfg->qpp_addr_mode;
+ flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+ cmd = flash_cfg->qpage_program_cmd;
+ } else {
+ return -1;
+ }
+
+ is_32bits_addr = (flash_cfg->io_mode & 0x20);
+ /* Prepare command */
+ flash_cmd.rw_flag = SF_CTRL_WRITE;
+ flash_cmd.addr_size = 3;
+
+ if (is_32bits_addr > 0) {
+ flash_cmd.addr_size++;
+ }
+
+ for (i = 0; i < len;) {
+ /* Write enable is needed for every program */
+ stat = bflb_sflash_write_enable(flash_cfg);
+
+ if (stat != 0) {
+ return stat;
+ }
+
+ /* Get current programmed length within page size */
+ cur_len = flash_cfg->page_size - addr % flash_cfg->page_size;
+
+ if (cur_len > len - i) {
+ cur_len = len - i;
+ }
+
+ /* Prepare command */
+ arch_memcpy_fast(flash_ctrl_buf, data, cur_len);
+
+ if (is_32bits_addr > 0) {
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+ flash_cmd.cmd_buf[1] = (addr << 24);
+ } else {
+ flash_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+ }
+
+ flash_cmd.nb_data = cur_len;
+
+ bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+ /* Adjust address and programmed length */
+ addr += cur_len;
+ i += cur_len;
+ data += cur_len;
+
+ /* Wait for write done */
+ cnt = 0;
+
+ while (bflb_sflash_busy(flash_cfg)) {
+ arch_delay_us(100);
+ cnt++;
+
+ if (cnt > flash_cfg->time_page_pgm * 20) {
+ return -1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/*@} end of group SFLASH_Public_Functions */
+
+/*@} end of group SFLASH */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sflash.h b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sflash.h
new file mode 100644
index 00000000..339f3790
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_sflash.h
@@ -0,0 +1,226 @@
+/**
+ ******************************************************************************
+ * @file bl628_sflah.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL628_SFLAH_H__
+#define __BL628_SFLAH_H__
+
+#include "bflb_sf_ctrl.h"
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SFLAH
+ * @{
+ */
+
+/** @defgroup SFLAH_Public_Types
+ * @{
+ */
+
+/**
+ * @brief Serial flash configuration structure type definition
+ */
+typedef struct
+{
+ uint8_t io_mode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */
+ uint8_t c_read_support; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+ uint8_t clk_delay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+ uint8_t clk_invert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+ uint8_t reset_en_cmd; /*!< Flash enable reset command */
+ uint8_t reset_cmd; /*!< Flash reset command */
+ uint8_t reset_c_read_cmd; /*!< Flash reset continuous read command */
+ uint8_t reset_c_read_cmd_size; /*!< Flash reset continuous read command size */
+ uint8_t jedec_id_cmd; /*!< JEDEC ID command */
+ uint8_t jedec_id_cmd_dmy_clk; /*!< JEDEC ID command dummy clock */
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+ uint8_t qpi_jedec_id_cmd; /*!< QPI JEDEC ID comamnd */
+ uint8_t qpi_jedec_id_cmd_dmy_clk; /*!< QPI JEDEC ID command dummy clock */
+#else
+ uint8_t enter_32bits_addr_cmd; /*!< Enter 32-bits addr command */
+ uint8_t exit_32bits_addr_cmd; /*!< Exit 32-bits addr command */
+#endif
+ uint8_t sector_size; /*!< *1024bytes */
+ uint8_t mid; /*!< Manufacturer ID */
+ uint16_t page_size; /*!< Page size */
+ uint8_t chip_erase_cmd; /*!< Chip erase cmd */
+ uint8_t sector_erase_cmd; /*!< Sector erase command */
+ uint8_t blk32_erase_cmd; /*!< Block 32K erase command,some Micron not support */
+ uint8_t blk64_erase_cmd; /*!< Block 64K erase command */
+ uint8_t write_enable_cmd; /*!< Need before every erase or program */
+ uint8_t page_program_cmd; /*!< Page program cmd */
+ uint8_t qpage_program_cmd; /*!< QIO page program cmd */
+ uint8_t qpp_addr_mode; /*!< QIO page program address mode */
+ uint8_t fast_read_cmd; /*!< Fast read command */
+ uint8_t fr_dmy_clk; /*!< Fast read command dummy clock */
+ uint8_t qpi_fast_read_cmd; /*!< QPI fast read command */
+ uint8_t qpi_fr_dmy_clk; /*!< QPI fast read command dummy clock */
+ uint8_t fast_read_do_cmd; /*!< Fast read dual output command */
+ uint8_t fr_do_dmy_clk; /*!< Fast read dual output command dummy clock */
+ uint8_t fast_read_dio_cmd; /*!< Fast read dual io comamnd */
+ uint8_t fr_dio_dmy_clk; /*!< Fast read dual io command dummy clock */
+ uint8_t fast_read_qo_cmd; /*!< Fast read quad output comamnd */
+ uint8_t fr_qo_dmy_clk; /*!< Fast read quad output comamnd dummy clock */
+ uint8_t fast_read_qio_cmd; /*!< Fast read quad io comamnd */
+ uint8_t fr_qio_dmy_clk; /*!< Fast read quad io comamnd dummy clock */
+ uint8_t qpi_fast_read_qio_cmd; /*!< QPI fast read quad io comamnd */
+ uint8_t qpi_fr_qio_dmy_clk; /*!< QPI fast read QIO dummy clock */
+ uint8_t qpi_page_program_cmd; /*!< QPI program command */
+ uint8_t write_vreg_enable_cmd; /*!< Enable write reg */
+ uint8_t wr_enable_index; /*!< Write enable register index */
+ uint8_t qe_index; /*!< Quad mode enable register index */
+ uint8_t busy_index; /*!< Busy status register index */
+ uint8_t wr_enable_bit; /*!< Write enable bit pos */
+ uint8_t qe_bit; /*!< Quad enable bit pos */
+ uint8_t busy_bit; /*!< Busy status bit pos */
+ uint8_t wr_enable_write_reg_len; /*!< Register length of write enable */
+ uint8_t wr_enable_read_reg_len; /*!< Register length of write enable status */
+ uint8_t qe_write_reg_len; /*!< Register length of contain quad enable */
+ uint8_t qe_read_reg_len; /*!< Register length of contain quad enable status */
+ uint8_t release_powerdown; /*!< Release power down command */
+ uint8_t busy_read_reg_len; /*!< Register length of contain busy status */
+ uint8_t read_reg_cmd[4]; /*!< Read register command buffer */
+ uint8_t write_reg_cmd[4]; /*!< Write register command buffer */
+ uint8_t enter_qpi; /*!< Enter qpi command */
+ uint8_t exit_qpi; /*!< Exit qpi command */
+ uint8_t c_read_mode; /*!< Config data for continuous read mode */
+ uint8_t c_rexit; /*!< Config data for exit continuous read mode */
+ uint8_t burst_wrap_cmd; /*!< Enable burst wrap command */
+ uint8_t burst_wrap_cmd_dmy_clk; /*!< Enable burst wrap command dummy clock */
+ uint8_t burst_wrap_data_mode; /*!< Data and address mode for this command */
+ uint8_t burst_wrap_data; /*!< Data to enable burst wrap */
+ uint8_t de_burst_wrap_cmd; /*!< Disable burst wrap command */
+ uint8_t de_burst_wrap_cmd_dmy_clk; /*!< Disable burst wrap command dummy clock */
+ uint8_t de_burst_wrap_data_mode; /*!< Data and address mode for this command */
+ uint8_t de_burst_wrap_data; /*!< Data to disable burst wrap */
+ uint16_t time_e_sector; /*!< 4K erase time */
+ uint16_t time_e_32k; /*!< 32K erase time */
+ uint16_t time_e_64k; /*!< 64K erase time */
+ uint16_t time_page_pgm; /*!< Page program time */
+ uint16_t time_ce; /*!< Chip erase time in ms */
+ uint8_t pd_delay; /*!< Release power down command delay time for wake up */
+ uint8_t qe_data; /*!< QE set data */
+} __attribute__((packed)) spi_flash_cfg_type;
+
+/**
+ * @brief Serial flash security register configuration
+ */
+struct sflash_sec_reg_cfg
+{
+ uint8_t erase_cmd; /*!< Erase security register command */
+ uint8_t program_cmd; /*!< Program security register command */
+ uint8_t read_cmd; /*!< Read security register command */
+ uint8_t enter_sec_opt_cmd; /*!< Enter security register option mode command */
+ uint8_t exit_sec_opt_cmd; /*!< Exit security register option mode command */
+ uint8_t block_num; /*!< Security register block number */
+ uint8_t *data; /*!< Data pointer to be program/read */
+ uint32_t addr; /*!< Start address to be program/read */
+ uint32_t len; /*!< Data length to be program/read */
+};
+/*@} end of group SFLAH_Public_Types */
+
+/** @defgroup SFLAH_Public_Constants
+ * @{
+ */
+
+/*@} end of group SFLAH_Public_Constants */
+
+/** @defgroup SFLAH_Public_Macros
+ * @{
+ */
+#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
+#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
+#define BFLB_SPIFLASH_CMD_INVALID 0xff
+
+/*@} end of group SFLAH_Public_Macros */
+
+/** @defgroup SFLAH_Public_Functions
+ * @{
+ */
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
+#else
+void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg);
+#endif
+int bflb_sflash_set_spi_mode(uint8_t mode);
+int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len);
+int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len);
+int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value,
+ uint8_t reg_len);
+int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value,
+ uint8_t reg_len);
+int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg);
+void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num);
+int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num);
+int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num);
+int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr);
+void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len);
+void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data);
+void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr);
+void bflb_sflash_powerdown(void);
+void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, uint8_t flash_cont_read, uint8_t bank);
+void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg);
+void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg);
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+int bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, uint8_t en_32bits_addr);
+#endif
+int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg);
+void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr,
+ uint32_t len, uint8_t bank);
+int bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank);
+void bflb_sflash_xip_read_disable(void);
+int bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos);
+int bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data,
+ uint32_t len);
+int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
+
+/*@} end of group SFLAH_Public_Functions */
+
+/*@} end of group SFLAH */
+
+/*@} end of group BL628_Peripheral_Driver */
+
+#endif /* __BL628_SFLAH_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_xip_sflash.c b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_xip_sflash.c
new file mode 100644
index 00000000..4d4a5943
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_xip_sflash.c
@@ -0,0 +1,495 @@
+/**
+ ******************************************************************************
+ * @file bflb_xip_sflash.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bflb_common.h"
+#include "bflb_xip_sflash.h"
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup XIP_SFLASH
+ * @{
+ */
+
+/** @defgroup XIP_SFLASH_Private_Macros
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Macros */
+
+/** @defgroup XIP_SFLASH_Private_Types
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Types */
+
+/** @defgroup XIP_SFLASH_Private_Variables
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Variables */
+
+/** @defgroup XIP_SFLASH_Global_Variables
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Global_Variables */
+
+/** @defgroup XIP_SFLASH_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Fun_Declaration */
+
+/** @defgroup XIP_SFLASH_Private_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Save flash controller state
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param offset: CPU XIP flash offset pointer
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset,
+ uint8_t group, uint8_t bank)
+{
+ /* XIP_SFlash_Delay */
+ volatile uint32_t i = 32 * 2;
+
+ while (i--)
+ ;
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+ if (bank == SF_CTRL_FLASH_BANK1) {
+ bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+ }
+#endif
+ bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+ /* Exit form continous read for accepting command */
+ bflb_sflash_reset_continue_read(p_flash_cfg);
+ /* For disable command that is setting register instaed of send command, we need write enable */
+ bflb_sflash_disable_burst_wrap(p_flash_cfg);
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+ /* Enable 32Bits addr mode again in case reset command make it reset */
+ bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1);
+#endif
+ if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
+ /* Enable QE again in case reset command make it reset */
+ bflb_sflash_qspi_enable(p_flash_cfg);
+ }
+ /* Deburst again to make sure */
+ bflb_sflash_disable_burst_wrap(p_flash_cfg);
+
+ /* Clear offset setting*/
+ *offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+ bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Restore flash controller state
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param offset: CPU XIP flash offset
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset,
+ uint8_t group, uint8_t bank)
+{
+ uint32_t tmp[1];
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
+
+ if(((p_flash_cfg->io_mode>>4)&0x01) == 0) {
+ if((p_flash_cfg->io_mode&0x0f)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0x0f)==SF_CTRL_QIO_MODE) {
+ bflb_sflash_set_burst_wrap(p_flash_cfg);
+ }
+ }
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+ bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1);
+#endif
+ bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+ if (bank == SF_CTRL_FLASH_BANK1) {
+ bflb_sf_ctrl_sbus2_revoke_replace();
+ }
+#endif
+
+ return 0;
+}
+
+/*@} end of group XIP_SFLASH_Private_Functions */
+
+/** @defgroup XIP_SFLASH_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Erase flash one region
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param start_addr: start address to erase
+ * @param len: data length to erase
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr,
+ int len, uint8_t group, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t offset = 0;
+ uint8_t aes_enable = 0;
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_xip_sflash_opt_enter(&aes_enable);
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ stat = bflb_sflash_erase(p_flash_cfg, start_addr, start_addr + len - 1);
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ bflb_xip_sflash_opt_exit(aes_enable);
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief Program flash one region
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param addr: start address to be programed
+ * @param data: data pointer to be programed
+ * @param len: data length to be programed
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+ uint32_t len, uint8_t group, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t offset = 0;
+ uint8_t aes_enable = 0;
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_xip_sflash_opt_enter(&aes_enable);
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ stat = bflb_sflash_program(p_flash_cfg, io_mode, addr, data, len);
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ bflb_xip_sflash_opt_exit(aes_enable);
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief Read data from flash
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param addr: flash read start address
+ * @param data: data pointer to store data read from flash
+ * @param len: data length to read
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+ uint32_t len, uint8_t group, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t offset = 0;
+ uint8_t aes_enable = 0;
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_xip_sflash_opt_enter(&aes_enable);
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ stat = bflb_sflash_read(p_flash_cfg, io_mode, 0, addr, data, len);
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ bflb_xip_sflash_opt_exit(aes_enable);
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief Get Flash Jedec ID
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param data: data pointer to store Jedec ID Read from flash
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+ uint8_t group, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t offset = 0;
+ uint8_t aes_enable = 0;
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_xip_sflash_opt_enter(&aes_enable);
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ bflb_sflash_get_jedecid(p_flash_cfg, data);
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ bflb_xip_sflash_opt_exit(aes_enable);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Get Flash Device ID
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param is_32bits_addr: Is flash addr mode in 32-bits
+ * @param data: data pointer to store Device ID Read from flash
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
+ uint8_t *data, uint8_t group, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t offset = 0;
+ uint8_t aes_enable = 0;
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_xip_sflash_opt_enter(&aes_enable);
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ bflb_sflash_get_deviceid(data, is_32bits_addr);
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ bflb_xip_sflash_opt_exit(aes_enable);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Get Flash Unique ID
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param data: data pointer to store Device ID Read from flash
+ * @param id_len: Unique id len
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+ uint8_t id_len, uint8_t group, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t offset = 0;
+ uint8_t aes_enable = 0;
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_xip_sflash_opt_enter(&aes_enable);
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ bflb_sflash_get_uniqueid(data, id_len);
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ bflb_xip_sflash_opt_exit(aes_enable);
+
+ return 0;
+}
+
+/****************************************************************************//**
+ * @brief Clear flash status register need lock
+ *
+ * @param p_flash_cfg: Flash config pointer
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg,
+ uint8_t group, uint8_t bank)
+{
+ int stat = 0;
+ uint32_t offset = 0;
+ uint8_t aes_enable = 0;
+ uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+ bflb_xip_sflash_opt_enter(&aes_enable);
+ stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+ if (stat != 0) {
+ bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+ } else {
+ stat = bflb_sflash_clear_status_register(p_flash_cfg);
+ bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+ }
+
+ bflb_xip_sflash_opt_exit(aes_enable);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Read data from flash via XIP
+ *
+ * @param addr: flash read start address
+ * @param data: data pointer to store data read from flash
+ * @param len: data length to read
+ * @param group: CPU group id 0 or 1
+ * @param bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len,
+ uint8_t group, uint8_t bank)
+{
+ uint32_t offset = 0;
+
+ addr = addr & (BFLB_FLASH_XIP_END-BFLB_FLASH_XIP_BASE-1);
+ addr |= BFLB_FLASH_XIP_BASE;
+
+ offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+ bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+ /* Flash read */
+ arch_memcpy_fast(data, (void *)(uintptr_t)(addr - bflb_sf_ctrl_get_flash_image_offset(group, bank)), len);
+ bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief XIP SFlash option save
+ *
+ * @param aes_enable: AES enable status pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable)
+{
+ *aes_enable = bflb_sf_ctrl_is_aes_enable();
+
+ if (*aes_enable) {
+ bflb_sf_ctrl_aes_disable();
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief XIP SFlash option restore
+ *
+ * @param aes_enable: AES enable status
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable)
+{
+ if (aes_enable) {
+ bflb_sf_ctrl_aes_enable();
+ }
+}
+
+/*@} end of group XIP_SFLASH_Public_Functions */
+
+/*@} end of group XIP_SFLASH */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_xip_sflash.h b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_xip_sflash.h
new file mode 100644
index 00000000..ab4cf7d7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/lhal/src/flash/bflb_xip_sflash.h
@@ -0,0 +1,99 @@
+/**
+ ******************************************************************************
+ * @file bflb_xip_sflash.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL628_XIP_SFLASH_H__
+#define __BL628_XIP_SFLASH_H__
+
+#include "bflb_sflash.h"
+
+/** @addtogroup BL628_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup XIP_SFLASH
+ * @{
+ */
+
+/** @defgroup XIP_SFLASH_Public_Types
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Public_Types */
+
+/** @defgroup XIP_SFLASH_Public_Constants
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Public_Constants */
+
+/** @defgroup XIP_SFLASH_Public_Macros
+ * @{
+ */
+
+/*@} end of group XIP_SFLASH_Public_Macros */
+
+/** @defgroup XIP_SFLASH_Public_Functions
+ * @{
+ */
+int bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset,
+ uint8_t group, uint8_t bank);
+int bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset,
+ uint8_t group, uint8_t bank);
+int bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr,
+ int len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
+ uint8_t *data, uint32_t len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
+ uint8_t *data, uint32_t len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+ uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
+ uint8_t *data, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+ uint8_t idlen, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_Flash_Cfg,
+ uint8_t group, uint8_t bank);
+int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len,
+ uint8_t group, uint8_t bank);
+void bflb_xip_sflash_opt_enter(uint8_t *aes_enable);
+void bflb_xip_sflash_opt_exit(uint8_t aes_enable);
+
+/*@} end of group XIP_SFLASH_Public_Functions */
+
+/*@} end of group XIP_SFLASH */
+
+/*@} end of group BL628_Peripheral_Driver */
+
+#endif /* __BL628_XIP_SFLASH_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/CMakeLists.txt b/arch/riscv32/bl808/src/drivers/soc/bl808/std/CMakeLists.txt
new file mode 100644
index 00000000..73ccc4de
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/CMakeLists.txt
@@ -0,0 +1,50 @@
+sdk_generate_library()
+
+sdk_library_add_sources(startup/${CPU_ID}/start.S)
+sdk_library_add_sources(startup/${CPU_ID}/vector.S)
+sdk_library_add_sources(startup/${CPU_ID}/riscv_fpu.S)
+sdk_library_add_sources(startup/${CPU_ID}/start_load.c)
+sdk_library_add_sources(startup/${CPU_ID}/system_bl808.c)
+sdk_library_add_sources(startup/${CPU_ID}/interrupt.c)
+
+sdk_library_add_sources(src/bl808_aon.c)
+sdk_library_add_sources(src/bl808_clock.c)
+sdk_library_add_sources(src/bl808_common.c)
+sdk_library_add_sources(src/bl808_ef_cfg.c)
+sdk_library_add_sources(src/bl808_glb.c)
+sdk_library_add_sources(src/bl808_glb_gpio.c)
+sdk_library_add_sources(src/bl808_hbn.c)
+sdk_library_add_sources(src/bl808_l1c.c)
+sdk_library_add_sources(src/bl808_pds.c)
+sdk_library_add_sources(src/bl808_sdh.c)
+
+sdk_library_add_sources(src/bl808_tzc_sec.c)
+sdk_library_add_sources(src/bl808_psram_uhs.c)
+sdk_library_add_sources(src/bl808_uhs_phy.c)
+
+sdk_library_add_sources(port/bl808_clock.c)
+
+sdk_add_include_directories(
+include
+include/hardware
+)
+
+if("${CPU_ID}" STREQUAL "m0")
+SET(MCPU "e907")
+SET(MARCH "rv32imafcpzpsfoperand_xtheade")
+SET(MABI "ilp32f")
+elseif("${CPU_ID}" STREQUAL "d0")
+SET(MCPU "c906")
+SET(MARCH "rv64imafdcv0p7_zfh_xtheadc")
+SET(MABI "lp64d")
+elseif("${CPU_ID}" STREQUAL "lp")
+SET(MCPU "e902")
+SET(MARCH "rv32emcxtheadse")
+SET(MABI "ilp32e")
+endif()
+
+sdk_add_compile_definitions(-DARCH_RISCV -DBFLB_USE_HAL_DRIVER)
+sdk_add_compile_options(-march=${MARCH} -mabi=${MABI} -mtune=${MCPU})
+sdk_add_link_options(-march=${MARCH} -mabi=${MABI} -mtune=${MCPU})
+
+sdk_add_compile_definitions(-DCONFIG_IRQ_NUM=80)
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_aon.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_aon.h
new file mode 100644
index 00000000..e35e8a59
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_aon.h
@@ -0,0 +1,127 @@
+/**
+ ******************************************************************************
+ * @file bl808_aon.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_AON_H__
+#define __BL808_AON_H__
+
+#include "aon_reg.h"
+#include "glb_reg.h"
+#include "hbn_reg.h"
+#include "pds_reg.h"
+#include "bl808_ef_ctrl.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup AON
+ * @{
+ */
+
+/** @defgroup AON_Public_Types
+ * @{
+ */
+
+/**
+ * @brief AON DCDC level type definition
+ */
+typedef enum {
+ AON_DCDC_LEVEL_0P900V = 0, /*!< AON DCDC voltage 0.900V */
+ AON_DCDC_LEVEL_1P075V = 7, /*!< AON DCDC voltage 1.075V */
+ AON_DCDC_LEVEL_1P100V = 8, /*!< AON DCDC voltage 1.100V */
+ AON_DCDC_LEVEL_1P125V = 9, /*!< AON DCDC voltage 1.125V */
+ AON_DCDC_LEVEL_1P900V = 31, /*!< AON DCDC voltage 1.900V */
+} AON_DCDC_LEVEL_Type;
+
+/*@} end of group AON_Public_Types */
+
+/** @defgroup AON_Public_Constants
+ * @{
+ */
+
+/*@} end of group AON_Public_Constants */
+
+/** @defgroup AON_Public_Macros
+ * @{
+ */
+/** @defgroup HBN_LDO_LEVEL_TYPE
+ * @{
+ */
+#define IS_AON_DCDC_LEVEL_TYPE(type) (((type) == AON_DCDC_LEVEL_0P900V) || \
+ ((type) == AON_DCDC_LEVEL_1P075V) || \
+ ((type) == AON_DCDC_LEVEL_1P100V) || \
+ ((type) == AON_DCDC_LEVEL_1P125V) || \
+ ((type) == AON_DCDC_LEVEL_1P900V))
+
+/*@} end of group AON_Public_Macros */
+
+/** @defgroup AON_Public_Functions
+ * @{
+ */
+/*----------*/
+BL_Err_Type AON_Power_On_MBG(void);
+BL_Err_Type AON_Power_Off_MBG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_XTAL(void);
+BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut);
+uint8_t AON_Get_Xtal_CapCode(void);
+BL_Err_Type AON_Power_Off_XTAL(void);
+/*----------*/
+BL_Err_Type AON_Power_On_BG(void);
+BL_Err_Type AON_Power_Off_BG(void);
+/*----------*/
+BL_Err_Type AON_Trim_DCDC11_Vout(void);
+BL_Err_Type AON_Trim_DCDC18_Vout(void);
+BL_Err_Type AON_Trim_USB20_RCAL(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO15_RF(void);
+BL_Err_Type AON_Power_Off_LDO15_RF(void);
+/*----------*/
+BL_Err_Type AON_Power_On_SFReg(void);
+BL_Err_Type AON_Power_Off_SFReg(void);
+/*----------*/
+BL_Err_Type AON_LowPower_Enter_PDS0(void);
+BL_Err_Type AON_LowPower_Exit_PDS0(void);
+/*----------*/
+BL_Err_Type AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel);
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_AON_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_clock.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_clock.h
new file mode 100644
index 00000000..774743d6
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_clock.h
@@ -0,0 +1,201 @@
+/**
+ ******************************************************************************
+ * @file bl808_clock.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_CLOCK_H__
+#define __BL808_CLOCK_H__
+
+#include "glb_reg.h"
+#include "mcu_misc_reg.h"
+#include "mm_misc_reg.h"
+#include "pds_reg.h"
+#include "bl808_glb.h"
+#include "bl808_hbn.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup CLOCK
+ * @{
+ */
+
+/** @defgroup CLOCK_Public_Types
+ * @{
+ */
+
+/**
+ * @brief System clock type definition
+ */
+typedef enum {
+ BL_SYSTEM_CLOCK_MCU_XCLK, /*!< MCU xclk clock */
+ BL_SYSTEM_CLOCK_MCU_ROOT_CLK, /*!< MCU root clock */
+ BL_SYSTEM_CLOCK_MCU_CLK, /*!< MCU Fast clock/CPU clock */
+ BL_SYSTEM_CLOCK_MCU_BCLK, /*!< MCU BUS clock */
+ BL_SYSTEM_CLOCK_MCU_PBCLK, /*!< MCU peri BUS clock */
+ BL_SYSTEM_CLOCK_DSP_XCLK, /*!< DSP xclk clock */
+ BL_SYSTEM_CLOCK_DSP_ROOT_CLK, /*!< DSP root clock */
+ BL_SYSTEM_CLOCK_DSP_CLK, /*!< DSP Fast clock/CPU clock */
+ BL_SYSTEM_CLOCK_DSP_BCLK, /*!< DSP BUS clock */
+ BL_SYSTEM_CLOCK_DSP_PBCLK, /*!< DSP peri BUS clock */
+ BL_SYSTEM_CLOCK_LP_CLK, /*!< LP clock */
+ BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */
+ BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */
+ BL_SYSTEM_CLOCK_MAX, /*!< MAX type of system clock */
+} BL_System_Clock_Type;
+
+/**
+ * @brief SOC clock config type
+ */
+typedef struct
+{
+ uint32_t magic; /*!< Clock config magic */
+ uint32_t systemClock[BL_SYSTEM_CLOCK_MAX]; /*!< System lock value */
+ uint32_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */
+ uint32_t i2sClock; /*!< I2S clock */
+} Clock_Cfg_Type;
+
+typedef enum {
+ CLOCK_AUPLL_DIV1,
+ CLOCK_AUPLL_DIV2,
+ CLOCK_AUPLL_DIV2P5,
+ CLOCK_AUPLL_DIV3,
+ CLOCK_AUPLL_DIV4,
+ CLOCK_AUPLL_DIV5,
+ CLOCK_AUPLL_DIV6,
+ CLOCK_AUPLL_DIV10,
+ CLOCK_AUPLL_DIV15,
+} CLOCK_AUPLL_Type;
+
+/**
+ * @brief Peripheral clock type definition
+ */
+typedef enum {
+ BL_PERIPHERAL_CLOCK_UART0, /*!< UART0 clock */
+ BL_PERIPHERAL_CLOCK_UART1, /*!< UART1 clock */
+ BL_PERIPHERAL_CLOCK_UART2, /*!< UART2 clock */
+ BL_PERIPHERAL_CLOCK_UART3, /*!< UART3 clock */
+ BL_PERIPHERAL_CLOCK_SPI0, /*!< SPI0 clock */
+ BL_PERIPHERAL_CLOCK_SPI1, /*!< SPI1 clock */
+ BL_PERIPHERAL_CLOCK_I2C0, /*!< I2C0 clock */
+ BL_PERIPHERAL_CLOCK_I2C1, /*!< I2C1 clock */
+ BL_PERIPHERAL_CLOCK_I2C2, /*!< I2C2 clock */
+ BL_PERIPHERAL_CLOCK_I2C3, /*!< I2C3 clock */
+ BL_PERIPHERAL_CLOCK_TIMER0, /*!< TIMER0 clock */
+ BL_PERIPHERAL_CLOCK_TIMER1, /*!< TIMER1 clock */
+ BL_PERIPHERAL_CLOCK_PSRAMA, /*!< PSRAMA clock */
+ BL_PERIPHERAL_CLOCK_PSRAMB, /*!< PSRAMB clock */
+ BL_PERIPHERAL_CLOCK_FLASH, /*!< FLASH clock */
+ BL_PERIPHERAL_CLOCK_I2S, /*!< I2S clock */
+ BL_PERIPHERAL_CLOCK_BLAI, /*!< BLAI clock */
+ BL_PERIPHERAL_CLOCK_DISPLAY, /*!< DISPLAY clock */
+ BL_PERIPHERAL_CLOCK_IR, /*!< IR clock */
+ BL_PERIPHERAL_CLOCK_PDM, /*!< PDM clock */
+ BL_PERIPHERAL_CLOCK_ADC, /*!< ADC clock */
+ BL_PERIPHERAL_CLOCK_DAC, /*!< DAC clock */
+ BL_PERIPHERAL_CLOCK_GPADC, /*!< GPADC clock */
+ BL_PERIPHERAL_CLOCK_GPDAC, /*!< GPDAC clock */
+ BL_PERIPHERAL_CLOCK_CAM, /*!< CAM clock */
+ BL_PERIPHERAL_CLOCK_SDH, /*!< SDH clock */
+ BL_PERIPHERAL_CLOCK_PKA, /*!< PKA clock */
+ BL_PERIPHERAL_CLOCK_EMI, /*!< EMI clock */
+ BL_PERIPHERAL_CLOCK_H264, /*!< H264 clock */
+ BL_PERIPHERAL_CLOCK_SUB, /*!< SUB clock */
+ BL_PERIPHERAL_CLOCK_MAX,
+} BL_Peripheral_Type;
+
+/*@} end of group CLOCK_Public_Types */
+
+/** @defgroup CLOCK_Public_Constants
+ * @{
+ */
+
+/** @defgroup BL_SYSTEM_CLOCK_TYPE
+ * @{
+ */
+#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_MCU_XCLK) || \
+ ((type) == BL_SYSTEM_CLOCK_MCU_ROOT_CLK) || \
+ ((type) == BL_SYSTEM_CLOCK_MCU_CLK) || \
+ ((type) == BL_SYSTEM_CLOCK_MCU_BCLK) || \
+ ((type) == BL_SYSTEM_CLOCK_MCU_PBCLK) || \
+ ((type) == BL_SYSTEM_CLOCK_DSP_XCLK) || \
+ ((type) == BL_SYSTEM_CLOCK_DSP_ROOT_CLK) || \
+ ((type) == BL_SYSTEM_CLOCK_DSP_CLK) || \
+ ((type) == BL_SYSTEM_CLOCK_DSP_BCLK) || \
+ ((type) == BL_SYSTEM_CLOCK_DSP_PBCLK) || \
+ ((type) == BL_SYSTEM_CLOCK_LP_CLK) || \
+ ((type) == BL_SYSTEM_CLOCK_F32K) || \
+ ((type) == BL_SYSTEM_CLOCK_XTAL) || \
+ ((type) == BL_SYSTEM_CLOCK_MAX))
+
+/*@} end of group CLOCK_Public_Constants */
+
+/** @defgroup CLOCK_Public_Macros
+ * @{
+ */
+#define SYS_CLOCK_CFG_MAGIC (0x12345678)
+#define SYS_CLOCK_CFG_ADDR (0x20010000 + 4 * 1024 - 512)
+
+/*@} end of group CLOCK_Public_Macros */
+
+/** @defgroup CLOCK_Public_Functions
+ * @{
+ */
+/*----------*/
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type);
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type);
+/*----------*/
+uint32_t SystemCoreClockGet(void);
+/*----------*/
+BL_Err_Type CPU_Set_MTimer_RST(uint8_t rstEn);
+BL_Err_Type CPU_Reset_MTimer(void);
+BL_Err_Type CPU_Set_MTimer_CLK(uint8_t enable, uint16_t div);
+uint32_t CPU_Get_MTimer_Source_Clock(void);
+uint32_t CPU_Get_MTimer_Clock(void);
+uint64_t CPU_Get_MTimer_Counter(void);
+uint64_t CPU_Get_CPU_Cycle(void);
+uint64_t CPU_Get_MTimer_US(void);
+uint64_t CPU_Get_MTimer_MS(void);
+BL_Err_Type CPU_MTimer_Delay_US(uint32_t cnt);
+BL_Err_Type CPU_MTimer_Delay_MS(uint32_t cnt);
+/*----------*/
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_CLOCK_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_common.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_common.h
new file mode 100644
index 00000000..a89c01cb
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_common.h
@@ -0,0 +1,192 @@
+#ifndef __BL808_COMMON_H__
+#define __BL808_COMMON_H__
+
+#include "bl808.h"
+#include "bflb_core.h"
+
+#ifndef __set_MSP
+#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
+#endif
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup COMMON
+ * @{
+ */
+
+/**
+ * @brief Memory access macro
+ */
+#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr)))
+#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr)))
+#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr)))
+#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val))
+#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+
+#define BL_WRWD_TO_BYTEP(p, val) \
+ { \
+ p[0] = val & 0xff; \
+ p[1] = (val >> 8) & 0xff; \
+ p[2] = (val >> 16) & 0xff; \
+ p[3] = (val >> 24) & 0xff; \
+ }
+/**
+ * @brief Register access macro
+ */
+#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)
+#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val)
+#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET)
+#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)
+#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS))
+#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK)
+#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS)
+#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
+#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0)
+#define BL_DRV_DUMMY \
+ { \
+ __ASM volatile("nop"); \
+ __ASM volatile("nop"); \
+ __ASM volatile("nop"); \
+ __ASM volatile("nop"); \
+ }
+
+/** @defgroup COMMON_Public_Types
+ * @{
+ */
+#ifdef BIT
+#undef BIT
+#define BIT(n) (1UL << (n))
+#else
+#define BIT(n) (1UL << (n))
+#endif
+
+/**
+ * @brief Null Type definition
+ */
+#ifndef NULL
+#define NULL 0
+#endif
+
+/**
+ * @brief Error type definition
+ */
+typedef enum {
+ SUCCESS = 0,
+ ERROR = 1,
+ TIMEOUT = 2,
+ INVALID = 3, /* invalid arguments */
+ NORESC = 4 /* no resource or resource temperary unavailable */
+} BL_Err_Type;
+
+/**
+ * @brief Functional type definition
+ */
+typedef enum {
+ DISABLE = 0,
+ ENABLE = 1,
+} BL_Fun_Type;
+
+/**
+ * @brief Status type definition
+ */
+typedef enum {
+ RESET = 0,
+ SET = 1,
+} BL_Sts_Type;
+
+/**
+ * @brief Mask type definition
+ */
+typedef enum {
+ UNMASK = 0,
+ MASK = 1
+} BL_Mask_Type;
+
+/**
+ * @brief Logical status Type definition
+ */
+typedef enum {
+ LOGIC_LO = 0,
+ LOGIC_HI = !LOGIC_LO
+} LogicalStatus;
+
+/**
+ * @brief Active status Type definition
+ */
+typedef enum {
+ DEACTIVE = 0,
+ ACTIVE = !DEACTIVE
+} ActiveStatus;
+
+/**
+ * @brief Interrupt callback function type
+ */
+typedef void(intCallback_Type)(void);
+typedef void (*pFunc)(void);
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr) ((void)0)
+#endif /* DEBUG */
+
+/** @defgroup COMMON_Public_Types
+ * @{
+ */
+
+/*@} end of group COMMON_Public_Types */
+
+/** @defgroup COMMON_Public_Constants
+ * @{
+ */
+
+/** @defgroup DRIVER_INT_PERIPH
+ * @{
+ */
+#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
+
+/*@} end of group DRIVER_INT_PERIPH */
+
+/** @defgroup DRIVER_INT_MASK
+ * @{
+ */
+#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
+
+#define ARCH_MemCpy arch_memcpy
+#define ARCH_MemSet arch_memset
+#define ARCH_MemCmp arch_memcmp
+#define ARCH_MemCpy4 arch_memcpy4
+#define arch_memcpy_fast arch_memcpy_fast
+#define ARCH_MemSet4 arch_memset4
+#define BFLB_Soft_CRC32 bflb_soft_crc32
+#define CPU_Interrupt_Enable(irq)
+#define CPU_Interrupt_Disable(irq)
+#define Interrupt_Handler_Register(irq, callback)
+/*@} end of group COMMON_Public_Constants */
+
+/** @defgroup DRIVER_Public_FunctionDeclaration
+ * @brief DRIVER functions declaration
+ * @{
+ */
+
+void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT);
+void arch_delay_us(uint32_t cnt);
+void arch_delay_ms(uint32_t cnt);
+
+void *ARCH_MemCpy(void *dst, const void *src, uint32_t n);
+uint32_t *ARCH_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
+void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
+void *ARCH_MemSet(void *s, uint8_t c, uint32_t n);
+uint32_t *ARCH_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n);
+int ARCH_MemCmp(const void *s1, const void *s2, uint32_t n);
+
+void C906_All_Int_Enable(void);
+void C906_All_Int_Disable(void);
+/*@} end of group DRIVER_COMMON */
+
+#endif /* __BL808_COMMON_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ef_cfg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ef_cfg.h
new file mode 100644
index 00000000..5ba6c94e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ef_cfg.h
@@ -0,0 +1,90 @@
+/**
+ ******************************************************************************
+ * @file bl808_ef_cfg.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_EF_CFG_H__
+#define __BL808_EF_CFG_H__
+
+#include "bflb_ef_ctrl.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup EF_CTRL
+ * @{
+ */
+
+/** @defgroup EF_CTRL_Public_Types
+ * @{
+ */
+
+/**
+ * @brief Efuse analog device info type definition
+ */
+typedef struct
+{
+ uint8_t chipInfo; /*!< Efuse chip revision */
+ uint8_t memoryInfo; /*!< Efuse memory info 0:no memory, 8:1MB flash */
+ uint8_t psramInfo; /*!< Efuse psram info 0:no psram, 1:WB 4MB, 2:UHS 32MB, 3:UHS 64MB, 4:WB 32MB, 5:WB 16MB */
+ uint8_t deviceInfo; /*!< Efuse device information */
+} bflb_efuse_device_info_type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup EF_CTRL_Public_Constants
+ * @{
+ */
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup EF_CTRL_Public_Macros
+ * @{
+ */
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup EF_CTRL_Public_Functions
+ * @{
+ */
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_EF_CFG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ef_ctrl.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ef_ctrl.h
new file mode 100644
index 00000000..d9524a0e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ef_ctrl.h
@@ -0,0 +1,379 @@
+/**
+ ******************************************************************************
+ * @file bl808_ef_ctrl.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_EF_CTRL_H__
+#define __BL808_EF_CTRL_H__
+
+#include "ef_ctrl_reg.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup EF_CTRL
+ * @{
+ */
+
+/** @defgroup EF_CTRL_Public_Types
+ * @{
+ */
+
+/**
+ * @brief Efuse Ctrl key slot type definition
+ */
+typedef enum {
+ EF_CTRL_KEY_SLOT0, /*!< key slot 0 */
+ EF_CTRL_KEY_SLOT1, /*!< key slot 1 */
+ EF_CTRL_KEY_SLOT2, /*!< key slot 2 */
+ EF_CTRL_KEY_SLOT3, /*!< key slot 3 */
+ EF_CTRL_KEY_SLOT4, /*!< key slot 4 */
+ EF_CTRL_KEY_SLOT5, /*!< key slot 5 */
+ EF_CTRL_KEY_MAX, /*!< */
+} EF_Ctrl_Key_Type;
+
+/**
+ * @brief Efuse Ctrl sign type definition
+ */
+typedef enum {
+ EF_CTRL_SIGN_NONE, /*!< no sign */
+ EF_CTRL_SIGN_RSA, /*!< use RSA to sign */
+ EF_CTRL_SIGN_ECC, /*!< use ECC to sign */
+} EF_Ctrl_Sign_Type;
+
+/**
+ * @brief Efuse Ctrl flash AES type definition
+ */
+typedef enum {
+ EF_CTRL_SF_AES_NONE, /*!< No AES */
+ EF_CTRL_SF_AES_128, /*!< AES 128 */
+ EF_CTRL_SF_AES_192, /*!< AES 192 */
+ EF_CTRL_SF_AES_256, /*!< AES 256 */
+} EF_Ctrl_SF_AES_Type;
+
+/**
+ * @brief Efuse Ctrl Dbg type definition
+ */
+typedef enum {
+ EF_CTRL_DBG_OPEN = 0, /*!< Open debug */
+ EF_CTRL_DBG_PASSWORD, /*!< Open debug with password */
+ EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */
+} EF_Ctrl_Dbg_Mode_Type;
+
+/**
+ * @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+ EF_CTRL_EF_CLK, /*!< Select efuse clock */
+ EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */
+} EF_Ctrl_CLK_Type;
+
+/**
+ * @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+ EF_CTRL_PARA_DFT, /*!< Select default cyc parameter */
+ EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */
+} EF_Ctrl_CYC_PARA_Type;
+
+/**
+ * @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+ EF_CTRL_OP_MODE_AUTO, /*!< Select efuse program auto mode */
+ EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */
+} EF_Ctrl_OP_MODE_Type;
+
+/**
+ * @brief Efuse Ctrl secure configuration structure type definition
+ */
+typedef struct
+{
+ EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */
+ uint8_t ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */
+ uint8_t ef_dbg_jtag_1_dis; /*!< Jtag debug disable config value */
+ uint8_t ef_sboot_en; /*!< Secure boot enable config value */
+} EF_Ctrl_Sec_Param_Type;
+
+/**
+ * @brief Efuse analog dcdc11 trim type definition
+ */
+typedef struct
+{
+ uint32_t trimDcdc11VoutAon : 4; /*!< Efuse analog trim:dcdc11_vout_trim_aon */
+ uint32_t trimDcdc11VoutAonParity : 1; /*!< Efuse analog trim:dcdc11_vout_trim_aon_parity */
+ uint32_t trimDcdc11VoutAonEn : 1; /*!< Efuse analog trim:dcdc11_vout_trim_aon_en */
+ uint32_t reserved : 26; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_DCDC11_Trim_Type;
+
+/**
+ * @brief Efuse analog dcdc18 trim type definition
+ */
+typedef struct
+{
+ uint32_t trimDcdc18VoutAon : 4; /*!< Efuse analog trim:dcdc18_vout_trim_aon */
+ uint32_t trimDcdc18VoutAonParity : 1; /*!< Efuse analog trim:dcdc18_vout_trim_aon_parity */
+ uint32_t trimDcdc18VoutAonEn : 1; /*!< Efuse analog trim:dcdc18_vout_trim_aon_en */
+ uint32_t reserved : 26; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_DCDC18_Trim_Type;
+
+/**
+ * @brief Efuse analog ldo18flash trim type definition
+ */
+typedef struct
+{
+ uint32_t trimLdo18flashVoutAon : 4; /*!< Efuse analog trim:ldo18flash_vout_trim */
+ uint32_t trimLdo18flashVoutAonParity : 1; /*!< Efuse analog trim:ldo18flash_vout_trim_parity */
+ uint32_t trimLdo18flashVoutAonEn : 1; /*!< Efuse analog trim:ldo18flash_vout_trim_en */
+ uint32_t reserved : 26; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_LDO18FLASH_Trim_Type;
+
+/**
+ * @brief Efuse analog usb20rcal trim type definition
+ */
+typedef struct
+{
+ uint32_t trimUsb20rcalAon : 6; /*!< Efuse analog trim:usb20_rcal_code_aon */
+ uint32_t trimUsb20rcalAonParity : 1; /*!< Efuse analog trim:usb20_rcal_code_aon_parity */
+ uint32_t trimUsb20rcalAonEn : 1; /*!< Efuse analog trim:usb20_rcal_code_aon_en */
+ uint32_t reserved : 24; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_USB20RCAL_Trim_Type;
+
+/**
+ * @brief Efuse analog RC32M trim type definition
+ */
+typedef struct
+{
+ uint32_t trimRc32mCodeFrExt : 8; /*!< Efuse analog trim:trim_rc32m_code_fr_ext */
+ uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */
+ uint32_t trimRc32mExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en */
+ uint32_t reserved : 22; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32M_Trim_Type;
+
+/**
+ * @brief Efuse analog RC32K trim type definition
+ */
+typedef struct
+{
+ uint32_t trimRc32kCodeFrExt : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */
+ uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */
+ uint32_t trimRc32kExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32k_ext_code_en */
+ uint32_t reserved : 20; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32K_Trim_Type;
+
+typedef struct
+{
+ uint32_t trimLdo18ioVoutVal : 4; /*!< Efuse analog trim:trim_ldo18io_vout_val */
+ uint32_t trimLdo18ioVoutParity : 1; /*!< Efuse analog trim:trim_ldo18io_vout_parity */
+ uint32_t trimLdo18ioVoutEn : 1; /*!< Efuse analog trim:trim_ldo18io_vout_en */
+ uint32_t reserved : 26; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_LDO18IO_VOUT_Trim_Type;
+
+/**
+ * @brief Efuse analog TSEN trim type definition
+ */
+typedef struct
+{
+ uint32_t tsenRefcodeCorner : 12; /*!< TSEN refcode */
+ uint32_t tsenRefcodeCornerParity : 1; /*!< TSEN refcode parity */
+ uint32_t tsenRefcodeCornerEn : 1; /*!< TSEN refcode enable */
+ uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN refcode version */
+ uint32_t reserved : 17; /*!< TSEN analog trim:reserved */
+} Efuse_TSEN_Refcode_Corner_Type;
+
+/**
+ * @brief Efuse analog ADC Gain trim type definition
+ */
+typedef struct
+{
+ uint32_t adcGainCoeff : 12; /*!< ADC gain coeff */
+ uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */
+ uint32_t adcGainCoeffEn : 1; /*!< ADC gain coeff enable */
+ uint32_t reserved : 18; /*!< ADC gain coeff:reserved */
+} Efuse_ADC_Gain_Coeff_Type;
+
+/**
+ * @brief Efuse analog device info type definition
+ */
+typedef struct
+{
+ uint32_t rsvd : 22; /*!< Reserved */
+ uint32_t deviceInfo : 3; /*!< Efuse device information */
+ uint32_t psramInfo : 2; /*!< Efuse psram info 0:no psram, 1:BW 4MB, 2:UHS 64MB */
+ uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 8:1MB flash */
+ uint32_t chipInfo : 3; /*!< Efuse chip revision */
+} Efuse_Device_Info_Type;
+
+/**
+ * @brief Efuse Capcode type definition
+ */
+typedef struct
+{
+ uint32_t capCode : 6; /*!< Cap code value */
+ uint32_t parity : 1; /*!< Parity of capcode */
+ uint32_t en : 1; /*!< Enable status */
+ uint32_t rsvd : 24; /*!< Reserved */
+} Efuse_Capcode_Info_Type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup EF_CTRL_Public_Constants
+ * @{
+ */
+
+/** @defgroup EF_CTRL_KEY_TYPE
+ * @{
+ */
+#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \
+ ((type) == EF_CTRL_KEY_SLOT1) || \
+ ((type) == EF_CTRL_KEY_SLOT2) || \
+ ((type) == EF_CTRL_KEY_SLOT3) || \
+ ((type) == EF_CTRL_KEY_SLOT4) || \
+ ((type) == EF_CTRL_KEY_SLOT5) || \
+ ((type) == EF_CTRL_KEY_MAX))
+
+/** @defgroup EF_CTRL_SIGN_TYPE
+ * @{
+ */
+#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \
+ ((type) == EF_CTRL_SIGN_RSA) || \
+ ((type) == EF_CTRL_SIGN_ECC))
+
+/** @defgroup EF_CTRL_SF_AES_TYPE
+ * @{
+ */
+#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \
+ ((type) == EF_CTRL_SF_AES_128) || \
+ ((type) == EF_CTRL_SF_AES_192) || \
+ ((type) == EF_CTRL_SF_AES_256))
+
+/** @defgroup EF_CTRL_DBG_MODE_TYPE
+ * @{
+ */
+#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) || \
+ ((type) == EF_CTRL_DBG_PASSWORD) || \
+ ((type) == EF_CTRL_DBG_CLOSE))
+
+/** @defgroup EF_CTRL_CLK_TYPE
+ * @{
+ */
+#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \
+ ((type) == EF_CTRL_SAHB_CLK))
+
+/** @defgroup EF_CTRL_CYC_PARA_TYPE
+ * @{
+ */
+#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \
+ ((type) == EF_CTRL_PARA_MANUAL))
+
+/** @defgroup EF_CTRL_OP_MODE_TYPE
+ * @{
+ */
+#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \
+ ((type) == EF_CTRL_OP_MODE_MANUAL))
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup EF_CTRL_Public_Macros
+ * @{
+ */
+#define EF_CTRL_EFUSE_R0_SIZE 128
+#define EF_CTRL_EFUSE_R1_SIZE 128
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup EF_CTRL_Public_Functions
+ * @{
+ */
+/*----------*/
+BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]);
+/*----------*/
+void EF_Ctrl_Load_Efuse_R0(void);
+void EF_Ctrl_Load_Efuse_R1(void);
+void EF_Ctrl_Program_Efuse_0(void);
+void EF_Ctrl_Program_Efuse_1(void);
+BL_Sts_Type EF_Ctrl_Busy(void);
+BL_Sts_Type EF_Ctrl_AutoLoad_Done(void);
+void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program);
+void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh);
+void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program);
+void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg);
+void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program);
+void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2]);
+void EF_Ctrl_Read_Xtal_Trim_RC32M(uint8_t *forceNoTrim, uint8_t *noXtal);
+void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel);
+uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len);
+void EF_Ctrl_Read_DCDC11_Trim(Efuse_Ana_DCDC11_Trim_Type *trim);
+void EF_Ctrl_Read_DCDC18_Trim(Efuse_Ana_DCDC18_Trim_Type *trim);
+void EF_Ctrl_Read_LDO18FLASH_Trim(Efuse_Ana_LDO18FLASH_Trim_Type *trim);
+void EF_Ctrl_Read_USB20RCAL_Trim(Efuse_Ana_USB20RCAL_Trim_Type *trim);
+void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim);
+void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim);
+void EF_Ctrl_Read_LDO18IO_Vout_Trim(Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim);
+void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim);
+void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim);
+void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program);
+void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage);
+void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program);
+void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
+BL_Err_Type EF_Ctrl_Read_ZiggBee_MAC_Address(uint8_t mac[8]);
+void EF_Ctrl_Writelock_MAC_Address(uint8_t program);
+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
+void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program);
+void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
+void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Program_Direct(uint32_t offset, uint32_t *pword, uint32_t count);
+void EF_Ctrl_Read_Direct(uint32_t offset, uint32_t *pword, uint32_t count);
+void EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len);
+void EF_Ctrl_Crc_Enable(void);
+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
+void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue);
+BL_Err_Type EF_Ctrl_Crc_Result(void);
+void EF_Ctrl_Sw_AHB_Clk_0(void);
+void EF_Ctrl_Sw_AHB_Clk_1(void);
+uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_EF_CTRL_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_glb.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_glb.h
new file mode 100644
index 00000000..156335ad
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_glb.h
@@ -0,0 +1,2527 @@
+/**
+ ******************************************************************************
+ * @file bl808_glb.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_GLB_H__
+#define __BL808_GLB_H__
+
+#include "glb_reg.h"
+#include "cci_reg.h"
+#include "mm_glb_reg.h"
+#include "pds_reg.h"
+#include "bl808_gpio.h"
+#include "bl808_hbn.h"
+#include "bl808_aon.h"
+#include "bl808_pds.h"
+#include "bl808_common.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup GLB
+ * @{
+ */
+
+/** @defgroup GLB_Public_Types
+ * @{
+ */
+
+/**
+ * @brief GLB AHB clock IP type definition
+ */
+typedef enum {
+ GLB_AHB_CLOCK_IP_CPU,
+ GLB_AHB_CLOCK_IP_SDU,
+ GLB_AHB_CLOCK_IP_SEC,
+ GLB_AHB_CLOCK_IP_DMA_0,
+ GLB_AHB_CLOCK_IP_DMA_1,
+ GLB_AHB_CLOCK_IP_DMA_2,
+ GLB_AHB_CLOCK_IP_CCI,
+ GLB_AHB_CLOCK_IP_RF_TOP,
+ GLB_AHB_CLOCK_IP_GPIP,
+ GLB_AHB_CLOCK_IP_TZC,
+ GLB_AHB_CLOCK_IP_EF_CTRL,
+ GLB_AHB_CLOCK_IP_SF_CTRL,
+ GLB_AHB_CLOCK_IP_EMAC,
+ GLB_AHB_CLOCK_IP_UART0,
+ GLB_AHB_CLOCK_IP_UART1,
+ GLB_AHB_CLOCK_IP_UART2,
+ GLB_AHB_CLOCK_IP_UART3,
+ GLB_AHB_CLOCK_IP_SPI,
+ GLB_AHB_CLOCK_IP_I2C,
+ GLB_AHB_CLOCK_IP_PWM,
+ GLB_AHB_CLOCK_IP_TIMER,
+ GLB_AHB_CLOCK_IP_IR,
+ GLB_AHB_CLOCK_IP_CHECKSUM,
+ GLB_AHB_CLOCK_IP_QDEC,
+ GLB_AHB_CLOCK_IP_KYS,
+ GLB_AHB_CLOCK_IP_I2S,
+ GLB_AHB_CLOCK_IP_USB11,
+ GLB_AHB_CLOCK_IP_CAM,
+ GLB_AHB_CLOCK_IP_MJPEG,
+ GLB_AHB_CLOCK_IP_BT_BLE_NORMAL,
+ GLB_AHB_CLOCK_IP_BT_BLE_LP,
+ GLB_AHB_CLOCK_IP_ZB_NORMAL,
+ GLB_AHB_CLOCK_IP_ZB_LP,
+ GLB_AHB_CLOCK_IP_WIFI_NORMAL,
+ GLB_AHB_CLOCK_IP_WIFI_LP,
+ GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL,
+ GLB_AHB_CLOCK_IP_BT_BLE_2_LP,
+ GLB_AHB_CLOCK_IP_EMI_MISC,
+ GLB_AHB_CLOCK_IP_PSRAM0_CTRL,
+ GLB_AHB_CLOCK_IP_PSRAM1_CTRL,
+ GLB_AHB_CLOCK_IP_USB20,
+ GLB_AHB_CLOCK_IP_MIX2,
+ GLB_AHB_CLOCK_IP_AUDIO,
+ GLB_AHB_CLOCK_IP_SDH,
+ GLB_AHB_CLOCK_IP_ZB2_NORMAL,
+ GLB_AHB_CLOCK_IP_ZB2_LP,
+ GLB_AHB_CLOCK_IP_I2C1,
+ GLB_AHB_CLOCK_IP_WIFI_PHY,
+ GLB_AHB_CLOCK_IP_WIFI_MAC_PHY,
+ GLB_AHB_CLOCK_IP_WIFI_PLATFORM,
+ GLB_AHB_CLOCK_IP_LZ4,
+ GLB_AHB_CLOCK_IP_AUPDM,
+ GLB_AHB_CLOCK_IP_GAUGE,
+} GLB_AHB_CLOCK_IP_Type;
+
+/**
+ * @brief GLB core ID type definition
+ */
+typedef enum {
+ GLB_CORE_ID_M0, /*!< M0 */
+ GLB_CORE_ID_D0, /*!< D0 */
+ GLB_CORE_ID_LP, /*!< LP */
+ GLB_CORE_ID_MAX, /*!< ID max */
+ GLB_CORE_ID_INVALID, /*!< ID invalid */
+} GLB_CORE_ID_Type;
+
+/**
+ * @brief cci ID type definition
+ */
+typedef enum {
+ CCI0_ID, /*!< CCI0 port define */
+ CCI_ID_MAX, /*!< CCI MAX ID define */
+} CCI_ID_Type;
+
+/**
+ * @brief GLB DSP all interrupt type definition
+ */
+typedef enum {
+ GLB_DSP_ALL_INT_BUS_DEC_ERR_INT = 0, /*!< bus_dec_err_int */
+ GLB_DSP_ALL_INT_RSV1_INT = 1, /*!< rsv1 */
+ GLB_DSP_ALL_INT_IPC2_NP2AP_IRQ = 2, /*!< |ipc2_np2ap_irq */
+ GLB_DSP_ALL_INT_RSV3 = 3, /*!< rsv3 */
+ GLB_DSP_ALL_INT_UART0_INT = 4, /*!< uart0_int */
+ GLB_DSP_ALL_INT_I2C0_INT = 5, /*!< i2c0_int */
+ GLB_DSP_ALL_INT_I2C1_INT = 6, /*!< i2c1_int */
+ GLB_DSP_ALL_INT_SPI_INT = 7, /*!< spi_int */
+ GLB_DSP_ALL_INT_RSV4_INT = 8, /*!< rsv4 */
+ GLB_DSP_ALL_INT_RSV5_INT = 9, /*!< rsv5 */
+ GLB_DSP_ALL_INT_SEOF1_INT = 10, /*!< seof1_int */
+ GLB_DSP_ALL_INT_SEOF2_INT = 11, /*!< seof2_int */
+ GLB_DSP_ALL_INT_SEOF3_INT = 12, /*!< seof3_int */
+ GLB_DSP_ALL_INT_DVP2BUS_INT_0 = 13, /*!< dvp2bus_int[0] */
+ GLB_DSP_ALL_INT_DVP2BUS_INT_1 = 14, /*!< dvp2bus_int[1] */
+ GLB_DSP_ALL_INT_DVP2BUS_INT_2 = 15, /*!< dvp2bus_int[2] */
+ GLB_DSP_ALL_INT_DVP2BUS_INT_3 = 16, /*!< dvp2bus_int[3] */
+ GLB_DSP_ALL_INT_H264_BS_IRQ = 17, /*!< h264_bs_irq */
+ GLB_DSP_ALL_INT_H264_FRAME_IRQ = 18, /*!< h264_frame_irq */
+ GLB_DSP_ALL_INT_H264_SEQ_DONE_INT = 19, /*!< h264_seq_done_int */
+ GLB_DSP_ALL_INT_MJPEG_INT = 20, /*!< mjpeg_int */
+ GLB_DSP_ALL_INT_H264_S_BS_IRQ = 21, /*!< h264_s_bs_irq */
+ GLB_DSP_ALL_INT_H264_S_FRAME_IRQ = 22, /*!< h264_s_frame_irq */
+ GLB_DSP_ALL_INT_H264_S_SEQ_DONE_INT = 23, /*!< h264_s_seq_done_int */
+ GLB_DSP_ALL_INT_DMA_INTR_0 = 24, /*!< DMA_INTR[0] */
+ GLB_DSP_ALL_INT_DMA_INTR_1 = 25, /*!< DMA_INTR[1] */
+ GLB_DSP_ALL_INT_DMA_INTR_2 = 26, /*!< DMA_INTR[2] */
+ GLB_DSP_ALL_INT_DMA_INTR_3 = 27, /*!< DMA_INTR[3] */
+ GLB_DSP_ALL_INT_DMA_INTR_4 = 28, /*!< DMA_INTR[4] */
+ GLB_DSP_ALL_INT_DMA_INTR_5 = 29, /*!< DMA_INTR[5] */
+ GLB_DSP_ALL_INT_DMA_INTR_6 = 30, /*!< DMA_INTR[6] */
+ GLB_DSP_ALL_INT_DMA_INTR_7 = 31, /*!< DMA_INTR[7] */
+ GLB_DSP_ALL_INT_RSV32 = 32, /*!< rsv32 */
+ GLB_DSP_ALL_INT_RSV33 = 33, /*!< rsv33 */
+ GLB_DSP_ALL_INT_RSV34 = 34, /*!< rsv34 */
+ GLB_DSP_ALL_INT_RSV35 = 35, /*!< rsv35 */
+ GLB_DSP_ALL_INT_RSV36 = 36, /*!< rsv36 */
+ GLB_DSP_ALL_INT_MIPI_CSI_INT = 37, /*!< mipi_csi_int */
+ GLB_DSP_ALL_INT_IPC2_AP2NP_IRQ = 38, /*!< |ipc2_ap2np_irq */
+ GLB_DSP_ALL_INT_RSV39 = 39, /*!< rsv39 */
+ GLB_DSP_ALL_INT_MJDEC_INT = 40, /*!< mjdec_int */
+ GLB_DSP_ALL_INT_DVP2BUS_IN_4 = 41, /*!< dvp2bus_int[4] */
+ GLB_DSP_ALL_INT_DVP2BUS_IN_5 = 42, /*!< dvp2bus_int[5] */
+ GLB_DSP_ALL_INT_DVP2BUS_IN_6 = 43, /*!< dvp2bus_int[6] */
+ GLB_DSP_ALL_INT_DVP2BUS_IN_7 = 44, /*!< dvp2bus_int[7] */
+ GLB_DSP_ALL_INT_DMA2D_INT_0 = 45, /*!< dma2d_int[0] */
+ GLB_DSP_ALL_INT_DMA2D_INT_1 = 46, /*!< dma2d_int[1] */
+ GLB_DSP_ALL_INT_DP_SOEF0_INT = 47, /*!< dp_soef0_int */
+ GLB_DSP_ALL_INT_RSV48 = 48, /*!< rsv48 */
+ GLB_DSP_ALL_INT_RSV49 = 49, /*!< rsv49 */
+ GLB_DSP_ALL_INT_RSV50 = 50, /*!< rsv50 */
+ GLB_DSP_ALL_INT_RSV51 = 51, /*!< rsv51 */
+ GLB_DSP_ALL_INT_OSDDP_INT = 52, /*!< osdDP_int */
+ GLB_DSP_ALL_INT_DBI_INT = 53, /*!< dbi_int */
+ GLB_DSP_ALL_INT_RSV6_INT = 54, /*!< rsv6 */
+ GLB_DSP_ALL_INT_OSDA_INT = 55, /*!< osdA_int */
+ GLB_DSP_ALL_INT_OSDB_INT = 56, /*!< osdB_int */
+ GLB_DSP_ALL_INT_OSD_PB_INT = 57, /*!< osd_pb_int */
+ GLB_DSP_ALL_INT_RSV7_INT = 58, /*!< rsv7 */
+ GLB_DSP_ALL_INT_MIPI_DSI_INT = 59, /*!< mipi_dsi_int */
+ GLB_DSP_ALL_INT_RSV8_INT = 60, /*!< rsv8 */
+ GLB_DSP_ALL_INT_MM_TIMER_IRQ2 = 61, /*!< mm_timer_irq2 */
+ GLB_DSP_ALL_INT_MM_TIMER_IRQ3 = 62, /*!< mm_timer_irq3 */
+ GLB_DSP_ALL_INT_MM_WDT_IRQ = 63, /*!< mm_wdt_irq */
+} GLB_DSP_ALL_INT_Type;
+
+/**
+ * @brief GLB MCU all interrupt type definition
+ */
+typedef enum {
+ GLB_MCU_ALL_INT_BMX_ERR_INT = 0, /*!< bmx_err_intmcu_dec_err_int */
+ GLB_MCU_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT = 1, /*!< bmx_timeout_intmcu_timeout_int */
+ GLB_MCU_ALL_INT_IPC0_NP2AP_IRQ = 2, /*!< ipc0_np2ap_irq */
+ GLB_MCU_ALL_INT_IPC0_AP2NP_IRQ = 3, /*!< ipc0_ap2np_irq */
+ GLB_MCU_ALL_INT_AUDIO_INT = 4, /*!< audio_int */
+ GLB_MCU_ALL_INT_RF_TOP_INT_0 = 5, /*!< rf_top_int[0] */
+ GLB_MCU_ALL_INT_RF_TOP_INT_1 = 6, /*!< rf_top_int[1] */
+ GLB_MCU_ALL_INT_LZ4_INT = 7, /*!< lz4_int */
+ GLB_MCU_ALL_INT_RSV8 = 8, /*!< rsv8 */
+ GLB_MCU_ALL_INT_SEC_ENG_ID0_GMAC_INT = 9, /*!< sec_eng_id0_gmac_int */
+ GLB_MCU_ALL_INT_SEC_ENG_ID0_CDET_INT = 10, /*!< sec_eng_id0_cdet_int */
+ GLB_MCU_ALL_INT_SEC_ENG_ID0_PKA_INT = 11, /*!< sec_eng_id0_pka_int */
+ GLB_MCU_ALL_INT_SEC_ENG_ID0_TRNG_INT = 12, /*!< sec_eng_id0_trng_int */
+ GLB_MCU_ALL_INT_SEC_ENG_ID0_AES_INT = 13, /*!< sec_eng_id0_aes_int */
+ GLB_MCU_ALL_INT_SEC_ENG_ID0_SHA_INT = 14, /*!< sec_eng_id0_sha_int */
+ GLB_MCU_ALL_INT_DMA_INTR_ALL = 15, /*!< DMA_INTR_ALL */
+ GLB_MCU_ALL_INT_DMA2_INTR_ALL = 16, /*!< DMA2_INTR_ALL */
+ GLB_MCU_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1 = 17, /*!< sdh_mmc1_intsdh2pmu_wakeup_int1 */
+ GLB_MCU_ALL_INT_MM_IRQ_ALL = 18, /*!< mm_irq_all */
+ GLB_MCU_ALL_INT_IRTX_INT = 19, /*!< irtx_int */
+ GLB_MCU_ALL_INT_IRRX_INT = 20, /*!< irrx_int */
+ GLB_MCU_ALL_INT_USB_INT = 21, /*!< usb_int */
+ GLB_MCU_ALL_INT_AUPDM_INT = 22, /*!< aupdm_int */
+ GLB_MCU_ALL_INT_SF_CTRL_ID0_INT = 23, /*!< sf_ctrl_id0_int */
+ GLB_MCU_ALL_INT_EMAC_INT = 24, /*!< emac_int */
+ GLB_MCU_ALL_INT_GPADC_DMA_INT = 25, /*!< gpadc_dma_int */
+ GLB_MCU_ALL_INT_EFUSE_INT = 26, /*!< efuse_int */
+ GLB_MCU_ALL_INT_SPI_0_INT = 27, /*!< spi_0_int */
+ GLB_MCU_ALL_INT_UART_IRQ = 28, /*!< uart_irq */
+ GLB_MCU_ALL_INT_UART1_IRQ = 29, /*!< uart1_irq */
+ GLB_MCU_ALL_INT_UART2_IRQ = 30, /*!< uart2_irq */
+ GLB_MCU_ALL_INT_GPIO_DMA_INT = 31, /*!< gpio_dma_int */
+ GLB_MCU_ALL_INT_I2C_0_INT = 32, /*!< i2c_0_int */
+ GLB_MCU_ALL_INT_PWM_INT = 33, /*!< pwm_int */
+ GLB_MCU_ALL_INT_IPC1_NP2AP_IRQ = 34, /*!< ipc1_np2ap_irq */
+ GLB_MCU_ALL_INT_IPC1_AP2NP_IRQ = 35, /*!< ipc1_ap2np_irq */
+ GLB_MCU_ALL_INT_TIMER0_2_IRQ = 36, /*!< timer0_2_irq */
+ GLB_MCU_ALL_INT_TIMER0_3_IRQ = 37, /*!< timer0_3_irq */
+ GLB_MCU_ALL_INT_WDT0_IRQ = 38, /*!< wdt0_irq */
+ GLB_MCU_ALL_INT_I2C_1_INT = 39, /*!< i2c_1_int */
+ GLB_MCU_ALL_INT_I2S0_INT = 40, /*!< i2s0_int */
+ GLB_MCU_ALL_INT_RSV41 = 41, /*!< rsv41 */
+ GLB_MCU_ALL_INT_RSV42 = 42, /*!< rsv42 */
+ GLB_MCU_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ = 43, /*!< ana_ocp_out_to_cpu_irq[2:0] */
+ GLB_MCU_ALL_INT_GPIO_IRQ = 44, /*!< gpio_irq */
+ GLB_MCU_ALL_INT_DM_IRQ = 45, /*!< dm_irq */
+ GLB_MCU_ALL_INT_BT_IRQ = 46, /*!< bt_irq */
+ GLB_MCU_ALL_INT_M154_REQ_ENH_ACK_INT = 47, /*!< m154_req_enh_ack_int */
+ GLB_MCU_ALL_INT_M154_INT = 48, /*!< m154_int */
+ GLB_MCU_ALL_INT_M154_AES_INT = 49, /*!< m154_aes_int */
+ GLB_MCU_ALL_INT_PDS_INT = 50, /*!< pds_int */
+ GLB_MCU_ALL_INT_HBN_IRQ_OUT_0 = 51, /*!< hbn_irq_out[0] */
+ GLB_MCU_ALL_INT_HBN_IRQ_OUT_1 = 52, /*!< hbn_irq_out[1] */
+ GLB_MCU_ALL_INT_BOR_OUT = 53, /*!< bor_out */
+ GLB_MCU_ALL_INT_WIFI_TO_CPU_IRQ_N = 54, /*!< wifi_to_cpu_irq_n */
+ GLB_MCU_ALL_INT_BZ_PHY_INT = 55, /*!< bz_phy_int */
+ GLB_MCU_ALL_INT_BLE_INT = 56, /*!< ble_int */
+ GLB_MCU_ALL_INT_MAC_INT_TX_RX_TIMER = 57, /*!< mac_int_tx_rx_timer */
+ GLB_MCU_ALL_INT_MAC_INT_TX_RX_MISC = 58, /*!< mac_int_tx_rx_misc */
+ GLB_MCU_ALL_INT_MAC_INT_RX_TRIGGER = 59, /*!< mac_int_rx_trigger */
+ GLB_MCU_ALL_INT_MAC_INT_TX_TRIGGER = 60, /*!< mac_int_tx_trigger */
+ GLB_MCU_ALL_INT_MAC_INT_GEN = 61, /*!< mac_int_gen */
+ GLB_MCU_ALL_INT_MAC_INT_PROT_TRIGGER = 62, /*!< mac_int_prot_trigger */
+ GLB_MCU_ALL_INT_WIFI_IPC = 63, /*!< wifi_ipc */
+} GLB_MCU_ALL_INT_Type;
+
+/**
+ * @brief GLB LP all interrupt type definition
+ */
+typedef enum {
+ GLB_LP_ALL_INT_BMX_ERR_INT = 0, /*!< bmx_err_int */
+ GLB_LP_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT = 1, /*!< bmx_timeout_intmcu_timeout_int */
+ GLB_LP_ALL_INT_IPC0_NP2AP_IRQ = 2, /*!< ipc0_np2ap_irq */
+ GLB_LP_ALL_INT_IPC0_AP2NP_IRQ = 3, /*!< ipc0_ap2np_irq */
+ GLB_LP_ALL_INT_AUDIO_INT = 4, /*!< audio_int */
+ GLB_LP_ALL_INT_RF_TOP_INT_0 = 5, /*!< rf_top_int[0] */
+ GLB_LP_ALL_INT_RF_TOP_INT_1 = 6, /*!< rf_top_int[1] */
+ GLB_LP_ALL_INT_LZ4_INT = 7, /*!< lz4_int */
+ GLB_LP_ALL_INT_RSV8 = 8, /*!< rsv8 */
+ GLB_LP_ALL_INT_SEC_ENG_ID0_GMAC_INT = 9, /*!< sec_eng_id0_gmac_int */
+ GLB_LP_ALL_INT_SEC_ENG_ID0_CDET_INT = 10, /*!< sec_eng_id0_cdet_int */
+ GLB_LP_ALL_INT_SEC_ENG_ID0_PKA_INT = 11, /*!< sec_eng_id0_pka_int */
+ GLB_LP_ALL_INT_SEC_ENG_ID0_TRNG_INT = 12, /*!< sec_eng_id0_trng_int */
+ GLB_LP_ALL_INT_SEC_ENG_ID0_AES_INT = 13, /*!< sec_eng_id0_aes_int */
+ GLB_LP_ALL_INT_SEC_ENG_ID0_SHA_INT = 14, /*!< sec_eng_id0_sha_int */
+ GLB_LP_ALL_INT_DMA_INTR_ALL = 15, /*!< DMA_INTR_ALL */
+ GLB_LP_ALL_INT_DMA2_INTR_ALL = 16, /*!< DMA2_INTR_ALL */
+ GLB_LP_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1 = 17, /*!< sdh_mmc1_intsdh2pmu_wakeup_int1 */
+ GLB_LP_ALL_INT_MM_IRQ_ALL = 18, /*!< mm_irq_all */
+ GLB_LP_ALL_INT_IRTX_INT = 19, /*!< irtx_int */
+ GLB_LP_ALL_INT_IRRX_INT = 20, /*!< irrx_int */
+ GLB_LP_ALL_INT_USB_INT = 21, /*!< usb_int */
+ GLB_LP_ALL_INT_AUPDM_INT = 22, /*!< aupdm_int */
+ GLB_LP_ALL_INT_SF_CTRL_ID0_INT = 23, /*!< sf_ctrl_id0_int */
+ GLB_LP_ALL_INT_EMAC_INT = 24, /*!< emac_int */
+ GLB_LP_ALL_INT_GPADC_DMA_INT = 25, /*!< gpadc_dma_int */
+ GLB_LP_ALL_INT_EFUSE_INT = 26, /*!< efuse_int */
+ GLB_LP_ALL_INT_SPI_0_INT = 27, /*!< spi_0_int */
+ GLB_LP_ALL_INT_UART_IRQ = 28, /*!< uart_irq */
+ GLB_LP_ALL_INT_UART1_IRQ = 29, /*!< uart1_irq */
+ GLB_LP_ALL_INT_UART2_IRQ = 30, /*!< uart2_irq */
+ GLB_LP_ALL_INT_GPIO_DMA_INT = 31, /*!< gpio_dma_int */
+ GLB_LP_ALL_INT_I2C_0_INT = 32, /*!< i2c_0_int */
+ GLB_LP_ALL_INT_PWM_INT = 33, /*!< pwm_int */
+ GLB_LP_ALL_INT_IPC1_NP2AP_IRQ = 34, /*!< ipc1_np2ap_irq */
+ GLB_LP_ALL_INT_IPC1_AP2NP_IRQ = 35, /*!< ipc1_ap2np_irq */
+ GLB_LP_ALL_INT_TIMER0_2_IRQ = 36, /*!< timer0_2_irq */
+ GLB_LP_ALL_INT_TIMER0_3_IRQ = 37, /*!< timer0_3_irq */
+ GLB_LP_ALL_INT_WDT0_IRQ = 38, /*!< wdt0_irq */
+ GLB_LP_ALL_INT_I2C_1_INT = 39, /*!< i2c_1_int */
+ GLB_LP_ALL_INT_I2S0_INT = 40, /*!< i2s0_int */
+ GLB_LP_ALL_INT_RSV41 = 41, /*!< rsv41 */
+ GLB_LP_ALL_INT_RSV42 = 42, /*!< rsv42 */
+ GLB_LP_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ = 43, /*!< ana_ocp_out_to_cpu_irq[2:0] */
+ GLB_LP_ALL_INT_GPIO_IRQ = 44, /*!< gpio_irq */
+ GLB_LP_ALL_INT_DM_IRQ = 45, /*!< dm_irq */
+ GLB_LP_ALL_INT_BT_IRQ = 46, /*!< bt_irq */
+ GLB_LP_ALL_INT_M154_REQ_ENH_ACK_INT = 47, /*!< m154_req_enh_ack_int */
+ GLB_LP_ALL_INT_M154_INT = 48, /*!< m154_int */
+ GLB_LP_ALL_INT_M154_AES_INT = 49, /*!< m154_aes_int */
+ GLB_LP_ALL_INT_PDS_INT = 50, /*!< pds_int */
+ GLB_LP_ALL_INT_HBN_IRQ_OUT_0 = 51, /*!< hbn_irq_out[0] */
+ GLB_LP_ALL_INT_HBN_IRQ_OUT_1 = 52, /*!< hbn_irq_out[1] */
+ GLB_LP_ALL_INT_BOR_OUT = 53, /*!< bor_out */
+ GLB_LP_ALL_INT_WIFI_TO_CPU_IRQ_N = 54, /*!< wifi_to_cpu_irq_n */
+ GLB_LP_ALL_INT_BZ_PHY_INT = 55, /*!< bz_phy_int */
+ GLB_LP_ALL_INT_BLE_INT = 56, /*!< ble_int */
+ GLB_LP_ALL_INT_MAC_INT_TX_RX_TIMER = 57, /*!< mac_int_tx_rx_timer */
+ GLB_LP_ALL_INT_MAC_INT_TX_RX_MISC = 58, /*!< mac_int_tx_rx_misc */
+ GLB_LP_ALL_INT_MAC_INT_RX_TRIGGER = 59, /*!< mac_int_rx_trigger */
+ GLB_LP_ALL_INT_MAC_INT_TX_TRIGGER = 60, /*!< mac_int_tx_trigger */
+ GLB_LP_ALL_INT_MAC_INT_GEN = 61, /*!< mac_int_gen */
+ GLB_LP_ALL_INT_MAC_INT_PROT_TRIGGER = 62, /*!< mac_int_prot_trigger */
+ GLB_LP_ALL_INT_WIFI_IPC = 63, /*!< wifi_ipc */
+} GLB_LP_ALL_INT_Type;
+
+/**
+ * @brief GLB dsp muxpll 320M clock type definition
+ */
+typedef enum {
+ GLB_DSP_MUXPLL_SEL_WIFIPLL_320M, /*!< dsp muxpll select wifipll 320M */
+ GLB_DSP_MUXPLL_SEL_AUPLL_DIV1, /*!< dsp muxpll select aupll div1 */
+} GLB_DSP_MUXPLL_320M_CLK_SEL_Type;
+
+/**
+ * @brief GLB dsp muxpll 240M clock type definition
+ */
+typedef enum {
+ GLB_DSP_MUXPLL_SEL_WIFIPLL_240M, /*!< dsp muxpll select wifipll 240M */
+ GLB_DSP_MUXPLL_SEL_AUPLL_DIV2, /*!< dsp muxpll select aupll div2 */
+} GLB_DSP_MUXPLL_240M_CLK_SEL_Type;
+
+/**
+ * @brief GLB dsp muxpll 160M clock type definition
+ */
+typedef enum {
+ GLB_DSP_MUXPLL_SEL_WIFIPLL_160M, /*!< dsp muxpll select wifipll 160M */
+ GLB_DSP_MUXPLL_SEL_CPUPLL_160M, /*!< dsp muxpll select cpupll 160M */
+} GLB_DSP_MUXPLL_160M_CLK_SEL_Type;
+
+/**
+ * @brief GLB mcu muxpll 160M clock type definition
+ */
+typedef enum {
+ GLB_MCU_MUXPLL_SEL_WIFIPLL_160M, /*!< mcu muxpll select wifipll 160M */
+ GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_160M, /*!< mcu muxpll select top cpupll 160M */
+ GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV2, /*!< mcu muxpll select top aupll div2 */
+ GLB_MCU_MUXPLL_SEL_AUPLL_DIV2P5, /*!< mcu muxpll select aupll div2p5 */
+} GLB_MCU_MUXPLL_160M_CLK_SEL_Type;
+
+/**
+ * @brief GLB mcu muxpll 80M clock type definition
+ */
+typedef enum {
+ GLB_MCU_MUXPLL_SEL_WIFIPLL_80M, /*!< mcu muxpll select wifipll 80M */
+ GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_80M, /*!< mcu muxpll select top cpupll 80M */
+ GLB_MCU_MUXPLL_SEL_AUPLL_DIV5, /*!< mcu muxpll select aupll div5 */
+ GLB_MCU_MUXPLL_SEL_AUPLL_DIV6, /*!< mcu muxpll select aupll div6 */
+} GLB_MCU_MUXPLL_80M_CLK_SEL_Type;
+
+/**
+ * @brief GLB pll clock gate type definition
+ */
+typedef enum {
+ GLB_PLL_CGEN_MM_WIFIPLL_160M, /*!< pll cgen mm wifipll 160m */
+ GLB_PLL_CGEN_MM_WIFIPLL_240M, /*!< pll cgen mm wifipll 240m */
+ GLB_PLL_CGEN_MM_WIFIPLL_320M, /*!< pll cgen mm wifipll 320m */
+ GLB_PLL_CGEN_MM_AUPLL_DIV1, /*!< pll cgen mm aupll div1 */
+ GLB_PLL_CGEN_MM_AUPLL_DIV2, /*!< pll cgen mm aupll div2 */
+ GLB_PLL_CGEN_EMI_CPUPLL_400M, /*!< pll cgen emi cpupll 400m */
+ GLB_PLL_CGEN_EMI_CPUPLL_200M, /*!< pll cgen emi cpupll 200m */
+ GLB_PLL_CGEN_EMI_WIFIPLL_320M, /*!< pll cgen emi wifipll 320m */
+ GLB_PLL_CGEN_EMI_AUPLL_DIV1, /*!< pll cgen emi aupll div1 */
+ GLB_PLL_CGEN_TOP_CPUPLL_80M, /*!< pll cgen top cpupll 80m */
+ GLB_PLL_CGEN_TOP_CPUPLL_100M, /*!< pll cgen top cpupll 100m */
+ GLB_PLL_CGEN_TOP_CPUPLL_160M, /*!< pll cgen top cpupll 160m */
+ GLB_PLL_CGEN_TOP_CPUPLL_400M, /*!< pll cgen top cpupll 400m */
+ GLB_PLL_CGEN_TOP_WIFIPLL_240M, /*!< pll cgen top wifipll 240m */
+ GLB_PLL_CGEN_TOP_WIFIPLL_320M, /*!< pll cgen top wifipll 320m */
+ GLB_PLL_CGEN_TOP_AUPLL_DIV2, /*!< pll cgen top aupll div2 */
+ GLB_PLL_CGEN_TOP_AUPLL_DIV1, /*!< pll cgen top aupll div1 */
+} GLB_PLL_CGEN_Type;
+
+/**
+ * @brief GLB mcu system clock type definition
+ */
+typedef enum {
+ GLB_MCU_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */
+ GLB_MCU_SYS_CLK_XTAL, /*!< use XTAL as system clock */
+ GLB_MCU_SYS_CLK_CPUPLL_400M, /*!< use CPUPLL output 400M as system clock */
+ GLB_MCU_SYS_CLK_WIFIPLL_240M, /*!< use WIFIPLL output 240M as system clock */
+ GLB_MCU_SYS_CLK_WIFIPLL_320M, /*!< use WIFIPLL output 320M as system clock */
+} GLB_MCU_SYS_CLK_Type;
+
+/**
+ * @brief GLB dsp system clock type definition
+ */
+typedef enum {
+ GLB_DSP_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */
+ GLB_DSP_SYS_CLK_XTAL, /*!< use XTAL as system clock */
+ GLB_DSP_SYS_CLK_MM_WIFIPLL_240M, /*!< use WIFIPLL 240M as system clock */
+ GLB_DSP_SYS_CLK_MM_WIFIPLL_320M, /*!< use WIFIPLL 320M as system clock */
+ GLB_DSP_SYS_CLK_CPUPLL_400M, /*!< use CPUPLL output 400M as system clock */
+} GLB_DSP_SYS_CLK_Type;
+
+/**
+ * @brief GLB dsp pbus clock type definition
+ */
+typedef enum {
+ GLB_DSP_SYS_PBCLK_RC32M, /*!< use rc32m as pbus clock */
+ GLB_DSP_SYS_PBCLK_XTAL, /*!< use xtal as pbus clock */
+ GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M, /*!< use mm_wifipll_160m_clk as pbus clock */
+ GLB_DSP_SYS_PBCLK_CPUPLL_160M, /*!< use cpupll_160m_clk as pbus clock */
+ GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M, /*!< use mm_wifipll_240m_clk as pbus clock */
+} GLB_DSP_SYS_PBCLK_Type;
+
+/**
+ * @brief GLB dsp system clock type definition
+ */
+typedef enum {
+ GLB_PLL_REFCLK_XTAL = 0, /*!< use XTAL as pll ref clock */
+ GLB_PLL_REFCLK_RC32M = 3, /*!< use RC32M as pll ref clock */
+} GLB_PLL_REF_CLK_Type;
+
+typedef struct {
+ uint8_t clkpllRefdivRatio; /*!< xxx pll_refdiv_ratio */
+ uint8_t clkpllIntFracSw; /*!< xxx pll_int_frac_sw */
+ uint8_t clkpllIcp1u; /*!< xxx pll_icp_1u */
+ uint8_t clkpllIcp5u; /*!< xxx pll_icp_5u */
+ uint8_t clkpllRz; /*!< xxx pll_rz */
+ uint8_t clkpllCz; /*!< xxx pll_cz */
+ uint8_t clkpllC3; /*!< xxx pll_c3 */
+ uint8_t clkpllR4Short; /*!< xxx pll_r4_short */
+ uint8_t clkpllC4En; /*!< xxx pll_r4_en */
+ uint8_t clkpllSelSampleClk; /*!< xxx pll_sel_sample_clk */
+ uint8_t clkpllVcoSpeed; /*!< xxx pll_vco_speed */
+ uint8_t clkpllSdmCtrlHw; /*!< xxx pll_sdm_ctrl_hw */
+ uint8_t clkpllSdmBypass; /*!< xxx pll_sdm_bypass */
+} GLB_WAC_PLL_CFG_BASIC_Type;
+
+typedef struct {
+ const GLB_WAC_PLL_CFG_BASIC_Type *const basicCfg; /*!< pll basic configuration */
+ uint32_t clkpllSdmin; /*!< pll sdmin value */
+} GLB_WAC_PLL_Cfg_Type;
+
+typedef struct {
+ uint8_t clkpllRefdivRatio; /*!< xxx pll_refdiv_ratio */
+ uint8_t clkpllSelSampleClk; /*!< xxx pll_sel_sample_clk */
+ uint8_t clkpllVcoSpeed; /*!< xxx pll_vco_speed */
+ uint8_t clkpllEvenDivEn; /*!< xxx pll_even_div_en */
+ uint8_t clkpllEvenDivRatio; /*!< xxx pll_even_div_ratio */
+} GLB_MU_PLL_CFG_BASIC_Type;
+
+typedef struct {
+ const GLB_MU_PLL_CFG_BASIC_Type *const basicCfg; /*!< pll basic configuration */
+ uint32_t clkpllSdmin; /*!< pll sdmin value */
+} GLB_MU_PLL_Cfg_Type;
+
+/**
+ * @brief GLB CAM clock type definition
+ */
+typedef enum {
+ GLB_CAM_CLK_XCLK, /*!< Select XCLK as CAM clock */
+ GLB_CAM_CLK_WIFIPLL_96M, /*!< Select WIFIPLL_96M as CAM clock */
+ GLB_CAM_CLK_CPUPLL_100M, /*!< Select CPUPLL_96M as CAM clock */
+} GLB_CAM_CLK_Type;
+
+/**
+ * @brief GLB SDH clock type definition
+ */
+typedef enum {
+ GLB_SDH_CLK_WIFIPLL_96M, /*!< Select WIFIPLL_96M as SDH clock */
+ GLB_SDH_CLK_CPUPLL_100M, /*!< Select CPUPLL_100M as SDH clock */
+} GLB_SDH_CLK_Type;
+
+/**
+ * @brief GLB UART sig swap group type definition
+ */
+typedef enum {
+ GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, /*!< SWAP UART SIG GROUP GPIO0 - GPIO11 */
+ GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, /*!< SWAP UART SIG GROUP GPIO12 - GPIO23 */
+ GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35, /*!< SWAP UART SIG GROUP GPIO24 - GPIO35 */
+ GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, /*!< SWAP UART SIG GROUP GPIO36 - GPIO45 */
+} GLB_UART_SIG_SWAP_GRP_Type;
+
+/**
+ * @brief GLB I2S output ref clock type definition
+ */
+typedef enum {
+ GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */
+ GLB_I2S_OUT_REF_CLK_SRC, /*!< output reference clock on I2S_0 ref_clock port */
+} GLB_I2S_OUT_REF_CLK_Type;
+
+/**
+ * @brief GLB DMA clock ID type definition
+ */
+typedef enum {
+ GLB_DMA0_CLK_CH0, /*!< DMA0 clock ID:channel 0 */
+ GLB_DMA0_CLK_CH1, /*!< DMA0 clock ID:channel 1 */
+ GLB_DMA0_CLK_CH2, /*!< DMA0 clock ID:channel 2 */
+ GLB_DMA0_CLK_CH3, /*!< DMA0 clock ID:channel 3 */
+ GLB_DMA0_CLK_CH4, /*!< DMA0 clock ID:channel 4 */
+ GLB_DMA0_CLK_CH5, /*!< DMA0 clock ID:channel 5 */
+ GLB_DMA0_CLK_CH6, /*!< DMA0 clock ID:channel 6 */
+ GLB_DMA0_CLK_CH7, /*!< DMA0 clock ID:channel 7 */
+ GLB_DMA1_CLK_CH0, /*!< DMA1 clock ID:channel 0 */
+ GLB_DMA1_CLK_CH1, /*!< DMA1 clock ID:channel 1 */
+ GLB_DMA1_CLK_CH2, /*!< DMA1 clock ID:channel 2 */
+ GLB_DMA1_CLK_CH3, /*!< DMA1 clock ID:channel 3 */
+} GLB_DMA_CLK_ID_Type;
+
+/**
+ * @brief GLB peripheral DMA type definition
+ */
+typedef enum {
+ GLB_PERI_DMA_UART0_RX = 0, /*!< uart_rx */
+ GLB_PERI_DMA_UART0_TX = 1, /*!< uart_tx */
+ GLB_PERI_DMA_UART1_RX = 2, /*!< uart1_rx */
+ GLB_PERI_DMA_UART1_TX = 3, /*!< uart1_tx */
+ GLB_PERI_DMA_UART2_RX = 4, /*!< uart2_rx */
+ GLB_PERI_DMA_UART2_TX = 5, /*!< uart2_tx */
+ GLB_PERI_DMA_I2C_0_RX = 6, /*!< i2c_0_rx */
+ GLB_PERI_DMA_I2C_0_TX = 7, /*!< i2c_0_tx */
+ GLB_PERI_DMA_IRTX_TX = 8, /*!< irtx_tx */
+ GLB_PERI_DMA_GPIO_TX = 9, /*!< gpio_tx */
+ GLB_PERI_DMA_SPI_RX = 10, /*!< spi_rx */
+ GLB_PERI_DMA_SPI_TX = 11, /*!< spi_tx */
+ GLB_PERI_DMA_AUDIO_RX = 12, /*!< audio_rx */
+ GLB_PERI_DMA_AUDIO_TX = 13, /*!< audio_tx */
+ GLB_PERI_DMA_I2C_1_RX = 14, /*!< i2c_1_rx */
+ GLB_PERI_DMA_I2C_1_TX = 15, /*!< i2c_1_tx */
+ GLB_PERI_DMA_I2S_0_RX = 16, /*!< i2s_0_rx */
+ GLB_PERI_DMA_I2S_0_TX = 17, /*!< i2s_0_tx */
+ GLB_PERI_DMA_PDM_RX = 18, /*!< pdm_rx */
+ GLB_PERI_DMA_PADC = 19, /*!< padc */
+ GLB_PERI_DMA_GAUGE = 20, /*!< gauge */
+ GLB_PERI_DMA_GPADC = 22, /*!< gpadc */
+ GLB_PERI_DMA_GPDAC_TX = 23, /*!< gpdac_tx */
+} GLB_PERI_DMA_Type;
+
+/**
+ * @brief GLB DMA CN selection type definition
+ */
+typedef enum {
+ GLB_PERI_DMA_CN_SEL_DMA0 = 0, /*!< peripheral DMA channel select DMA0 */
+ GLB_PERI_DMA_CN_SEL_DMA1 = 1, /*!< peripheral DMA channel select DMA1 */
+} GLB_PERI_DMA_CN_SEL_Type;
+
+/**
+ * @brief GLB clock source type definition
+ */
+typedef enum {
+ GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */
+} GLB_IR_CLK_SRC_Type;
+
+/**
+ * @brief GLB flash clock type definition
+ */
+typedef enum {
+ GLB_SFLASH_CLK_120M_WIFIPLL, /*!< Select WIFIPLL 120M as flash clock */
+ GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */
+ GLB_SFLASH_CLK_100M_CPUPLL, /*!< Select CPUPLL 100M as flash clock */
+ GLB_SFLASH_CLK_80M_MUXPLL, /*!< Select MUXPLL 80M as flash clock */
+ GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */
+ GLB_SFLASH_CLK_96M_WIFIPLL, /*!< Select WIFIPLL 96M as flash clock */
+} GLB_SFLASH_CLK_Type;
+
+/**
+ * @brief GLB I2C clock type definition
+ */
+typedef enum {
+ GLB_I2C_CLK_BCLK, /*!< Select bus clk as I2C clock */
+ GLB_I2C_CLK_XCLK, /*!< Select xclk as I2C clock */
+} GLB_I2C_CLK_Type;
+
+/**
+ * @brief GLB SPI clock type definition
+ */
+typedef enum {
+ GLB_SPI_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as SPI clock */
+ GLB_SPI_CLK_XCLK, /*!< Select xclk as SPI clock */
+} GLB_SPI_CLK_Type;
+
+/**
+ * @brief GLB PWM1 io type definition
+ */
+typedef enum {
+ GLB_PWM1_IO_SINGLE_END, /*!< Select pwm1 io single end */
+ GLB_PWM1_IO_DIFF_END, /*!< Select pwm1 io differential end for BLDC */
+} GLB_PWM1_IO_SEL_Type;
+
+/**
+ * @brief GLB PWM2 io type definition
+ */
+typedef enum {
+ GLB_PWM2_IO_SINGLE_END, /*!< Select pwm2 io single end */
+ GLB_PWM2_IO_SINGLE_END_BLDC, /*!< Select pwm2 io single end BLDC */
+} GLB_PWM2_IO_SEL_Type;
+
+/**
+ * @brief GLB PDM io type definition
+ */
+typedef enum {
+ GLB_PDM_IO_SEL_AUDIO_TOP, /*!< Select audio_top PDM */
+ GLB_PDM_IO_SEL_AUPDM_TOP, /*!< Select aupdm_top PDM */
+} GLB_PDM_IO_SEL_Type;
+
+/**
+ * @brief GLB SPI pad action type definition
+ */
+typedef enum {
+ GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */
+ GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */
+} GLB_SPI_PAD_ACT_AS_Type;
+
+/**
+ * @brief GLB AHB software type definition
+ */
+typedef enum {
+ GLB_AHB_MCU_SW_RSV0 = 0,
+ GLB_AHB_MCU_SW_RSV1 = 1,
+ GLB_AHB_MCU_SW_WIFI = 4,
+ GLB_AHB_MCU_SW_BTDM = 8,
+ GLB_AHB_MCU_SW_ZIGBEE = 9,
+ GLB_AHB_MCU_SW_BLE2 = 10,
+ GLB_AHB_MCU_SW_ZIGBEE2 = 11,
+ GLB_AHB_MCU_SW_EMI_MISC = 16,
+ GLB_AHB_MCU_SW_PSRAM0_CTRL = 17,
+ GLB_AHB_MCU_SW_PSRAM1_CTRL = 18,
+ GLB_AHB_MCU_SW_USB_EMAC = 19,
+ GLB_AHB_MCU_SW_RSV20 = 20,
+ GLB_AHB_MCU_SW_AUDIO = 21,
+ GLB_AHB_MCU_SW_SDH = 22,
+ GLB_AHB_MCU_SW_RSV23 = 23,
+ GLB_AHB_MCU_SW_DMA2 = 24,
+ GLB_AHB_MCU_SW_GLB = 32,
+ GLB_AHB_MCU_SW_MIX = 33,
+ GLB_AHB_MCU_SW_GPIP = 34,
+ GLB_AHB_MCU_SW_SEC_DBG = 35,
+ GLB_AHB_MCU_SW_SEC_ENG = 36,
+ GLB_AHB_MCU_SW_TZ1 = 37,
+ GLB_AHB_MCU_SW_TZ2 = 38,
+ GLB_AHB_MCU_SW_EFUSE = 39,
+ GLB_AHB_MCU_SW_CCI = 40,
+ GLB_AHB_MCU_SW_MCU_PERI_BUS = 41,
+ GLB_AHB_MCU_SW_RSV42 = 42,
+ GLB_AHB_MCU_SW_SF = 43,
+ GLB_AHB_MCU_SW_DMA = 44,
+ GLB_AHB_MCU_SW_SDU = 45,
+ GLB_AHB_MCU_SW_PDS = 46,
+ GLB_AHB_MCU_SW_RSV47 = 47,
+ GLB_AHB_MCU_SW_UART0 = 48,
+ GLB_AHB_MCU_SW_UART1 = 49,
+ GLB_AHB_MCU_SW_SPI = 50,
+ GLB_AHB_MCU_SW_I2C = 51,
+ GLB_AHB_MCU_SW_PWM = 52,
+ GLB_AHB_MCU_SW_TIMER = 53,
+ GLB_AHB_MCU_SW_IR_REMOTE = 54,
+ GLB_AHB_MCU_SW_CHECKSUM = 55,
+ GLB_AHB_MCU_SW_IPC = 56,
+ GLB_AHB_MCU_SW_I2C1 = 57,
+ GLB_AHB_MCU_SW_UART2 = 58,
+ GLB_AHB_MCU_SW_I2S = 59,
+ GLB_AHB_MCU_SW_AUPDM = 60,
+ GLB_AHB_MCU_SW_LZ4 = 61,
+ GLB_AHB_MCU_SW_RSV62 = 62,
+ GLB_AHB_MCU_SW_RSV63 = 63,
+ GLB_AHB_MCU_SW_PWRON_RST = 64,
+ GLB_AHB_MCU_SW_CPU_RESET = 65,
+ GLB_AHB_MCU_SW_SYS_RESET = 66,
+ GLB_AHB_MCU_SW_PICO_RESET = 67,
+ GLB_AHB_MCU_SW_CPU2_RESET = 68,
+ GLB_AHB_MCU_SW_CHIP_RESET = 69,
+ GLB_AHB_MCU_SW_WL_WDT_RESET_MM_EN = 70,
+ GLB_AHB_MCU_SW_MMWDT2WL_RST_MSK = 71,
+} GLB_AHB_MCU_SW_Type;
+
+/**
+ * @brief GLB AHB software type definition
+ */
+typedef enum {
+ GLB_AHB_DSP_SW_REG_CTRL_SYS_RESET = 0,
+ GLB_AHB_DSP_SW_REG_CTRL_PWRON_RST = 2,
+ GLB_AHB_DSP_SW_REG_CTRL_MMCPU0_RESET = 8,
+ GLB_AHB_DSP_SW_SWRST_MM_MISC = 32,
+ GLB_AHB_DSP_SW_SWRST_DMA = 33,
+ GLB_AHB_DSP_SW_SWRST_UART0 = 34,
+ GLB_AHB_DSP_SW_SWRST_I2C0 = 35,
+ GLB_AHB_DSP_SW_SWRST_I2C1 = 36,
+ GLB_AHB_DSP_SW_SWRST_IPC = 37,
+ GLB_AHB_DSP_SW_SWRST_DMA2D = 38,
+ GLB_AHB_DSP_SW_SWRST_SPI = 40,
+ GLB_AHB_DSP_SW_SWRST_TIMER = 41,
+ GLB_AHB_DSP_SW_SWRST_I2S0 = 42,
+ GLB_AHB_DSP_SW_SWRST_I2S1 = 43,
+ GLB_AHB_DSP_SW_SWRST_PDM0 = 44,
+ GLB_AHB_DSP_SW_SWRST_PDM1 = 45,
+ GLB_AHB_DSP_SW_SWRST_PUHS = 47,
+ GLB_AHB_DSP_SW_SWRST_SUB_MISC = 64,
+ GLB_AHB_DSP_SW_SWRST_SUB_MAIN = 65,
+ GLB_AHB_DSP_SW_SWRST_SUB_TSRC = 66,
+ GLB_AHB_DSP_SW_SWRST_DP_TSRC = 67,
+ GLB_AHB_DSP_SW_SWRST_NR3D_CTRL = 68,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSA = 69,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSB = 70,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSC = 71,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSD = 72,
+ GLB_AHB_DSP_SW_SWRST_MIPI = 73,
+ GLB_AHB_DSP_SW_SWRST_SUB_REG = 80,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSE = 81,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSF = 82,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSG = 83,
+ GLB_AHB_DSP_SW_SWRST_DVP2BUSH = 84,
+ GLB_AHB_DSP_SW_SWRST_CODEC_MISC = 96,
+ GLB_AHB_DSP_SW_SWRST_MJPEG = 97,
+ GLB_AHB_DSP_SW_SWRST_H264 = 98,
+ GLB_AHB_DSP_SW_SWRST_MJPEG_DEC = 99,
+ GLB_AHB_DSP_SW_SWRST_CNN = 100,
+ GLB_AHB_DSP_SW_SWRST_VRAM = 112,
+ GLB_AHB_DSP_SW_RG_IS_RST_N = 128,
+} GLB_AHB_DSP_SW_Type;
+
+/**
+ * @brief GLB dis reset type definition
+ */
+typedef enum {
+ GLB_DISRST_GPIP = 2,
+ GLB_DISRST_SEC_ENG = 4,
+ GLB_DISRST_CCI = 8,
+ GLB_DISRST_SF = 11,
+ GLB_DISRST_UART0 = 16,
+ GLB_DISRST_UART1 = 17,
+ GLB_DISRST_SPI = 18,
+ GLB_DISRST_I2C0 = 19,
+ GLB_DISRST_PWM = 20,
+ GLB_DISRST_TIMER = 21,
+ GLB_DISRST_IR_REMOTE = 22,
+ GLB_DISRST_CHECKSUM = 23,
+ GLB_DISRST_IPC = 24,
+ GLB_DISRST_I2C1 = 25,
+ GLB_DISRST_UART2 = 26,
+} GLB_DISRST_Type;
+
+/**
+ * @brief GLB PKA clock type definition
+ */
+typedef enum {
+ GLB_PKA_CLK_MCU_BCLK, /*!< Select MCU_BCLK as PKA clock */
+ GLB_PKA_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as PKA clock */
+} GLB_PKA_CLK_Type;
+
+/**
+ * @brief GLB MCU software system reset type definition
+ */
+typedef enum {
+ GLB_MCU_SW_SYSTEM_CTRL_MCU = 1, /*!< mcu reset */
+ GLB_MCU_SW_SYSTEM_CTRL_LP = 3, /*!< lp reset */
+} GLB_MCU_SW_SYSTEM_Type;
+
+/**
+ * @brief BMX arb mode type definition
+ */
+typedef enum {
+ BMX_ARB_ROUND_ROBIN = 0, /*!< 0->round-robin */
+ BMX_ARB_FIX = 1, /*!< 1->fix */
+} BMX_ARB_Type;
+
+/**
+ * @brief BMX latch type definition
+ */
+typedef enum {
+ BMX_LATCH_FIRST_ERROR = 0, /*!< 0->Latch first error */
+ BMX_LATCH_LAST_ERROR = 1, /*!< 1->Latch last error */
+} BMX_LATCH_Type;
+
+/**
+ * @brief BMX configuration structure type definition
+ */
+typedef struct {
+ BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+ uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+} BMX_TO_Cfg_Type;
+
+/**
+ * @brief BMX bus err type definition
+ */
+typedef enum {
+ BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+ BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */
+} BMX_BUS_ERR_Type;
+
+/**
+ * @brief BMX bus err interrupt type definition
+ */
+typedef enum {
+ BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */
+ BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */
+} BMX_ERR_INT_Type;
+
+/**
+ * @brief BMX time out interrupt type definition
+ */
+typedef enum {
+ BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */
+ BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */
+} BMX_TO_INT_Type;
+
+/**
+ * @brief GLB eth ref clock out type definition
+ */
+typedef enum {
+ GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */
+ GLB_ETH_REF_CLK_OUT_INSIDE_50M, /*!< select inside 50MHz RMII ref clock */
+} GLB_ETH_REF_CLK_OUT_Type;
+
+/**
+ * @brief GLB EM type definition
+ */
+typedef enum {
+ GLB_WRAM160KB_EM0KB, /*!< WRAM_160KB EM_0KB */
+ GLB_WRAM144KB_EM16KB, /*!< WRAM_144KB EM_16KB */
+ GLB_WRAM128KB_EM32KB, /*!< WRAM_128KB EM_32KB */
+ GLB_WRAM112KB_EM48KB, /*!< WRAM_112KB EM_48KB */
+ GLB_WRAM96KB_EM64KB, /*!< WRAM_96KB EM_64KB */
+} GLB_EM_Type;
+
+/**
+ * @brief GLB ADC clock type definition
+ */
+typedef enum {
+ GLB_ADC_CLK_AUPLL, /*!< use AUPLL as ADC clock */
+ GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */
+} GLB_ADC_CLK_Type;
+
+/**
+ * @brief GLB DAC clock type definition
+ */
+typedef enum {
+ GLB_DAC_CLK_32M, /*!< use 32M as DAC clock */
+ GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */
+} GLB_DAC_CLK_Type;
+
+/**
+ * @brief GLB chip clock input output type definition
+ */
+/**
+ * @brief GLB chip clock out 0 type definition
+ */
+typedef enum {
+ GLB_CHIP_CLK_OUT_0_CAM_REF_CLK = 0, /*!< cam_ref_clk */
+ GLB_CHIP_CLK_OUT_0_I2S_REF_CLK = 1, /*!< i2s_ref_clk out */
+ GLB_CHIP_CLK_OUT_0_CLK_AUDIO_ADC = 2, /*!< clk_adc */
+ GLB_CHIP_CLK_OUT_0_CLK_AUDIO_DAC = 3, /*!< clk_dac */
+} GLB_CHIP_CLK_OUT_0_Type;
+
+/**
+ * @brief GLB chip clock out 1 type definition
+ */
+typedef enum {
+ GLB_CHIP_CLK_OUT_1_CAM_REF_CLK = 0, /*!< no chip clock out */
+ GLB_CHIP_CLK_OUT_1_I2S_REF_CLK = 1, /*!< i2s_ref_clk out */
+ GLB_CHIP_CLK_OUT_1_CLK_AUDIO_ADC = 2, /*!< clk_adc_in_128fs */
+ GLB_CHIP_CLK_OUT_1_CLK_AUDIO_DAC = 3, /*!< clk_dac_in_128fs */
+} GLB_CHIP_CLK_OUT_1_Type;
+
+/**
+ * @brief GLB chip clock out 2 type definition
+ */
+typedef enum {
+ GLB_CHIP_CLK_OUT_2_CAM_REF_CLK = 0, /*!< cam_ref_clk */
+ GLB_CHIP_CLK_OUT_2_I2S_REF_CLK = 1, /*!< i2s_ref_clk */
+ GLB_CHIP_CLK_OUT_2_ANA_XTAL_CLK = 2, /*!< ana_xtal_clk */
+ GLB_CHIP_CLK_OUT_2_PLL_32M_CLK = 3, /*!< pll_32m_clk */
+} GLB_CHIP_CLK_OUT_2_Type;
+
+/**
+ * @brief GLB chip clock out 3 type definition
+ */
+typedef enum {
+ GLB_CHIP_CLK_OUT_3_CAM_REF_CLK = 0, /*!< no chip clock out */
+ GLB_CHIP_CLK_OUT_3_I2S_REF_CLK = 1, /*!< i2s_ref_clk out */
+ GLB_CHIP_CLK_OUT_3_NONE = 2, /*!< no clock out */
+ GLB_CHIP_CLK_OUT_3_PLL_48M_CLK = 3, /*!< pll_48m_clk */
+} GLB_CHIP_CLK_OUT_3_Type;
+
+/**
+ * @brief GLB CSI DSI clock source select type definition
+ */
+typedef enum {
+ GLB_CSI_DSI_CLK_SEL_XTAL_CLK, /*!< xtal_clk */
+ GLB_CSI_DSI_CLK_SEL_CPUPLL_DIV10, /*!< cpupll_div10 */
+} GLB_CSI_DSI_CLK_SEL_Type;
+
+/**
+ * @brief GLB DIG clock source select type definition
+ */
+typedef enum {
+ GLB_DIG_CLK_WIFIPLL_32M, /*!< select WIFIPLL 32M as DIG clock source */
+ GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */
+ GLB_DIG_CLK_AUPLL, /*!< select AUPLL as DIG clock source */
+} GLB_DIG_CLK_Type;
+
+/**
+ * @brief GLB 512K clock out select type definition
+ */
+typedef enum {
+ GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */
+ GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */
+ GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */
+} GLB_512K_CLK_OUT_Type;
+
+/**
+ * @brief GLB BT bandwidth type definition
+ */
+typedef enum {
+ GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */
+ GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */
+} GLB_BT_BANDWIDTH_Type;
+
+/**
+ * @brief GLB UART2 IO selection type definition
+ */
+typedef enum {
+ GLB_UART2_IO_SEL_UART2, /*!< Select UART2 function */
+ GLB_UART2_IO_SEL_ISO11898, /*!< Select ISO11898 function */
+} GLB_UART2_IO_SEL_Type;
+
+/**
+ * @brief GLB UART signal type definition
+ */
+typedef enum {
+ GLB_UART_SIG_0, /*!< UART signal 0 */
+ GLB_UART_SIG_1, /*!< UART signal 1 */
+ GLB_UART_SIG_2, /*!< UART signal 2 */
+ GLB_UART_SIG_3, /*!< UART signal 3 */
+ GLB_UART_SIG_4, /*!< UART signal 4 */
+ GLB_UART_SIG_5, /*!< UART signal 5 */
+ GLB_UART_SIG_6, /*!< UART signal 6 */
+ GLB_UART_SIG_7, /*!< UART signal 7 */
+ GLB_UART_SIG_8, /*!< UART signal 8 */
+ GLB_UART_SIG_9, /*!< UART signal 9 */
+ GLB_UART_SIG_10, /*!< UART signal 10 */
+ GLB_UART_SIG_11, /*!< UART signal 11 */
+} GLB_UART_SIG_Type;
+
+/**
+ * @brief GLB UART signal function type definition
+ */
+typedef enum {
+ GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */
+ GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */
+ GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */
+ GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */
+ GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */
+ GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */
+ GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */
+ GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */
+ GLB_UART_SIG_FUN_UART2_RTS, /*!< UART funtion: UART 2 RTS */
+ GLB_UART_SIG_FUN_UART2_CTS, /*!< UART funtion: UART 2 CTS */
+ GLB_UART_SIG_FUN_UART2_TXD, /*!< UART funtion: UART 2 TXD */
+ GLB_UART_SIG_FUN_UART2_RXD, /*!< UART funtion: UART 2 RXD */
+} GLB_UART_SIG_FUN_Type;
+
+/**
+ * @brief XTAL type definition
+ */
+typedef enum {
+ GLB_XTAL_NONE, /*!< XTAL is none */
+ GLB_XTAL_24M, /*!< XTAL is 24M */
+ GLB_XTAL_32M, /*!< XTAL is 32M */
+ GLB_XTAL_38P4M, /*!< XTAL is 38.4M */
+ GLB_XTAL_40M, /*!< XTAL is 40M */
+ GLB_XTAL_26M, /*!< XTAL is 26M */
+ GLB_XTAL_RC32M, /*!< XTAL is RC32M */
+ GLB_XTAL_MAX, /*!< type max num */
+} GLB_XTAL_Type;
+
+/**
+ * @brief PLL power on type definition
+ */
+typedef enum {
+ GLB_PLL_NONE = 0, /*!< power on xtal and pll */
+ GLB_PLL_WIFIPLL = 1, /*!< power on WIFIPLL */
+ GLB_PLL_AUPLL = 2, /*!< power on AUPLL */
+ GLB_PLL_CPUPLL = 4, /*!< power on CPUPLL */
+ GLB_PLL_MIPIPLL = 8, /*!< power on ETHPLL */
+ GLB_PLL_UHSPLL = 16, /*!< power on ETHPLL */
+} GLB_PLL_Type;
+
+/**
+ * @brief WAC PLL XTAL type definition
+ */
+typedef enum {
+ GLB_WAC_PLL_WIFIPLL, /*!< wifi pll */
+ GLB_WAC_PLL_AUPLL, /*!< audio pll */
+ GLB_WAC_PLL_CPUPLL, /*!< cpu pll */
+} GLB_WAC_PLL_Type;
+
+/**
+ * @brief MU PLL XTAL type definition
+ */
+typedef enum {
+ GLB_MU_PLL_MIPIPLL, /*!< mipi pll */
+ GLB_MU_PLL_UHSPLL, /*!< uhs pll */
+} GLB_MU_PLL_Type;
+
+/**
+ * @brief DISP clock type definition
+ */
+typedef enum {
+ GLB_DISP_CLK_MIPIPLL_1500M, /*!< mipi pll 1500M */
+} GLB_DISP_CLK_Type;
+
+/**
+ * @brief PLL XTAL type definition
+ */
+typedef enum {
+ GLB_PSRAM_EMI_CPUPLL_400M, /*!< emi_cpupll_400m_clk */
+ GLB_PSRAM_EMI_WIFIPLL_320M, /*!< emi_wifipll_320m_clk */
+ GLB_PSRAM_EMI_AUPLL_DIV1, /*!< emi_aupll_div1_clk */
+} GLB_PSRAM_PLL_Type;
+
+/**
+ * @brief GLB DSP xclk clock type definition
+ */
+typedef enum {
+ GLB_DSP_XCLK_RC32M, /*!< use RC32M as xclk clock */
+ GLB_DSP_XCLK_XTAL, /*!< use XTAL as xclk clock */
+} GLB_DSP_XCLK_Type;
+
+/**
+ * @brief GLB DSP root clock type definition
+ */
+typedef enum {
+ GLB_DSP_ROOT_CLK_XCLK, /*!< use XCLK as root clock */
+ GLB_DSP_ROOT_CLK_PLL, /*!< use PLL as root clock */
+} GLB_DSP_ROOT_CLK_Type;
+
+/**
+ * @brief GLB DSP pbroot clock type definition
+ */
+typedef enum {
+ GLB_DSP_PBROOT_CLK_MM_XCLK, /*!< use mm_xclk as pbroot clock */
+ GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M, /*!< use mm_muxpll_160m_clk as pbroot clock */
+ GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M, /*!< use mm_muxpll_240m_clk as pbroot clock */
+} GLB_DSP_PBROOT_CLK_Type;
+
+/**
+ * @brief GLB DSP PLL clock type definition
+ */
+typedef enum {
+ GLB_DSP_PLL_CLK_MUXPLL_240M, /*!< select DSP PLL output muxpll 240m as cpu clock */
+ GLB_DSP_PLL_CLK_MUXPLL_320M, /*!< select DSP PLL output muxpll 320m as cpu clock */
+ GLB_DSP_PLL_CLK_CPUPLL_400M, /*!< select DSP PLL output cpupll 400m as cpu clock */
+} GLB_DSP_PLL_CLK_Type;
+
+/**
+ * @brief GLB DSP UART clock type definition
+ */
+typedef enum {
+ GLB_DSP_UART_CLK_DSP_PBCLK, /*!< Select dsp pbclk as UART clock */
+ GLB_DSP_UART_CLK_MUXPLL_160M, /*!< Select muxpll 160m as UART clock */
+ GLB_DSP_UART_CLK_DSP_XCLK, /*!< Select xclk as UART clock */
+} GLB_DSP_UART_CLK_Type;
+
+/**
+ * @brief GLB UART clock type definition
+ */
+typedef enum {
+ GLB_UART_CLK_BCLK, /*!< Select bclk clock as UART clock */
+ GLB_UART_CLK_PLL_160M, /*!< Select PLL 160M as UART clock */
+} GLB_UART_CLK_Type;
+
+/**
+ * @brief GLB DSP CNN clock type definition
+ */
+typedef enum {
+ GLB_DSP_CNN_CLK_160M, /*!< Select 160M as CNN clock */
+ GLB_DSP_CNN_CLK_240M, /*!< Select 240M as CNN clock */
+ GLB_DSP_CNN_CLK_320M, /*!< Select 320M as CNN clock */
+} GLB_DSP_CNN_CLK_Type;
+
+/**
+ * @brief GLB DSP DP clock type definition
+ */
+typedef enum {
+ GLB_DSP_DP_CLK_DISPLAY_PLL, /*!< Select display pll as DP clock */
+ GLB_DSP_DP_CLK_DSP_XCLK, /*!< Select mm xclk as DP clock */
+} GLB_DSP_DP_CLK_Type;
+
+/**
+ * @brief GLB DSP clock type definition
+ */
+typedef enum {
+ GLB_DSP_CLK_MUXPLL_160M, /*!< Select muxpll 160M as DSP sub clock */
+ GLB_DSP_CLK_MUXPLL_240M, /*!< Select muxpll 240M as DSP sub clock */
+ GLB_DSP_CLK_CPUPLL_400M, /*!< Select cpupll 400M as DSP sub clock */
+ GLB_DSP_CLK_DSP_XCLK, /*!< Select dsp xclk as DSP sub clock */
+} GLB_DSP_CLK_Type;
+
+/**
+ * @brief GLB DSP H264 clock type definition
+ */
+typedef enum {
+ GLB_DSP_H264_DSP_MUXPLL_160M, /*!< Select dsp muxpll 160M as SUB clock */
+ GLB_DSP_H264_DSP_MUXPLL_240M, /*!< Select dsp muxpll 240M as SUB clock */
+ GLB_DSP_H264_DSP_MUXPLL_320M, /*!< Select dsp muxpll 320M as SUB clock */
+} GLB_DSP_H264_CLK_Type;
+
+/**
+ * @brief GLB DSP SPI clock type definition
+ */
+typedef enum {
+ GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, /*!< Select muxpll 160M as SPI clock */
+ GLB_DSP_SPI_CLK_DSP_XCLK, /*!< Select xclk as SPI clock */
+} GLB_DSP_SPI_CLK_Type;
+
+/**
+ * @brief GLB DSP I2C clock type definition
+ */
+typedef enum {
+ GLB_DSP_I2C_CLK_DSP_PBCLK, /*!< Select dsp pbclk as I2C clock */
+ GLB_DSP_I2C_CLK_XCLK, /*!< Select xclk as I2C clock */
+} GLB_DSP_I2C_CLK_Type;
+
+/**
+ * @brief GLB I2S di ref clock type definition
+ */
+typedef enum {
+ GLB_I2S_DI_SEL_I2S_DI_INPUT, /*!< Select i2s_di input */
+ GLB_I2S_DI_SEL_I2S_REF_OUTPUT, /*!< Select i2s_ref_clk output */
+} GLB_I2S_DI_REF_CLK_Type;
+
+/**
+ * @brief GLB I2S do ref clock type definition
+ */
+typedef enum {
+ GLB_I2S_DO_SEL_I2S_DO_OUTPT, /*!< Select i2s_do output */
+ GLB_I2S_DO_SEL_I2S_REF_OUTPUT, /*!< Select i2s_ref_clk output */
+} GLB_I2S_DO_REF_CLK_Type;
+
+/**
+ * @brief GLB EMI clock type definition
+ */
+typedef enum {
+ GLB_EMI_CLK_MCU_PBCLK, /*!< mcu_pbclk */
+ GLB_EMI_CLK_CPUPLL_200M_CLK, /*!< cpupll_200m_clk */
+ GLB_EMI_CLK_WIFIPLL_320M_CLK, /*!< wifipll_320m_clk */
+ GLB_EMI_CLK_CPUPLL_400M_CLK, /*!< cpupll_400m_clk */
+} GLB_EMI_CLK_Type;
+
+/**
+ * @brief GLB DSP sw system type definition
+ */
+typedef enum {
+ GLB_DSP_SW_SYSTEM_CTRL_SYS = 0, /*!< SW system reset(pulse trigger) */
+ GLB_DSP_SW_SYSTEM_CTRL_PWRON = 2, /*!< SW power-on reset (pulse trigger) */
+ GLB_DSP_SW_SYSTEM_CTRL_DSP0 = 8, /*!< MMCPU0 reset(pulse trigger) */
+ GLB_DSP_SW_SYSTEM_CTRL_DSP1 = 9, /*!< MMCPU1 reset(pulse trigger) */
+ GLB_DSP_SW_SYSTEM_CTRL_WL2MM = 15, /*!< wl2mm */
+} GLB_DSP_SW_SYSTEM_Type;
+
+/**
+ * @brief GLB DSP peripheral type definition
+ */
+typedef enum {
+ GLB_DSP_PERIPHERAL_MM_MISC = 0, /*!< mm_misc */
+ GLB_DSP_PERIPHERAL_DMA = 1, /*!< dma */
+ GLB_DSP_PERIPHERAL_UART0 = 2, /*!< uart0 */
+ GLB_DSP_PERIPHERAL_I2C0 = 3, /*!< i2c0 */
+ GLB_DSP_PERIPHERAL_IPC = 5, /*!< ipc */
+ GLB_DSP_PERIPHERAL_SPI = 8, /*!< spi */
+ GLB_DSP_PERIPHERAL_TIMER = 9, /*!< timer */
+ GLB_DSP_PERIPHERAL_I2S0 = 10, /*!< i2s0 */
+} GLB_DSP_PERIPHERAL_Type;
+
+/**
+ * @brief GLB DSP sub type definition
+ */
+typedef enum {
+ GLB_DSP_SUB_MISC = 0, /*!< sub_misc */
+ GLB_DSP_SUB_DVP2BUSA = 1, /*!< dvp2busA */
+ GLB_DSP_SUB_DVP2BUSB = 2, /*!< dvp2busB */
+ GLB_DSP_SUB_DVP2BUSC = 3, /*!< dvp2busC */
+ GLB_DSP_SUB_OSD_DRAW = 4, /*!< osd_draw */
+ GLB_DSP_SUB_DP = 5, /*!< display */
+ GLB_DSP_SUB_IMG_PR = 16, /*!< img_pr scaler/yuv2rgb */
+ GLB_DSP_SUB_SCLRA = 17, /*!< ScalerA */
+ GLB_DSP_SUB_SCLRB = 18, /*!< ScalerB */
+} GLB_DSP_SUB_Type;
+
+/**
+ * @brief GLB DSP codec sub type definition
+ */
+typedef enum {
+ GLB_DSP_CODEC_SUB_MJPEG = 1, /*!< mjpeg */
+ GLB_DSP_CODEC_SUB_CNN = 2, /*!< BLAI */
+ GLB_DSP_CODEC_SUB_VRAM = 16, /*!< vram control logic(SRAM content would not be reset) */
+} GLB_DSP_CODEC_SUB_Type;
+
+/**
+ * @brief GLB DSP image sensor type definition
+ */
+typedef enum {
+ GLB_DSP_IMAGE_SENSOR_RG_IS = 1, /*!< Image sensor */
+} GLB_DSP_IMAGE_SENSOR_Type;
+
+/**
+ * @brief GLB LDO15CIS level type definition
+ */
+typedef enum {
+ GLB_LDO15CIS_LEVEL_1P00V = 0, /*!< GLB LDO15CIS voltage 1.00V */
+ GLB_LDO15CIS_LEVEL_1P05V = 1, /*!< GLB LDO15CIS voltage 1.05V */
+ GLB_LDO15CIS_LEVEL_1P10V = 2, /*!< GLB LDO15CIS voltage 1.10V */
+ GLB_LDO15CIS_LEVEL_1P15V = 3, /*!< GLB LDO15CIS voltage 1.15V */
+ GLB_LDO15CIS_LEVEL_1P20V = 4, /*!< GLB LDO15CIS voltage 1.20V */
+ GLB_LDO15CIS_LEVEL_1P30V = 5, /*!< GLB LDO15CIS voltage 1.30V */
+ GLB_LDO15CIS_LEVEL_1P40V = 6, /*!< GLB LDO15CIS voltage 1.40V */
+ GLB_LDO15CIS_LEVEL_1P45V = 7, /*!< GLB LDO15CIS voltage 1.45V */
+ GLB_LDO15CIS_LEVEL_1P50V = 8, /*!< GLB LDO15CIS voltage 1.50V */
+ GLB_LDO15CIS_LEVEL_1P55V = 9, /*!< GLB LDO15CIS voltage 1.55V */
+ GLB_LDO15CIS_LEVEL_1P60V = 10, /*!< GLB LDO15CIS voltage 1.60V */
+ GLB_LDO15CIS_LEVEL_1P65V = 11, /*!< GLB LDO15CIS voltage 1.65V */
+ GLB_LDO15CIS_LEVEL_1P70V = 12, /*!< GLB LDO15CIS voltage 1.70V */
+ GLB_LDO15CIS_LEVEL_1P75V = 13, /*!< GLB LDO15CIS voltage 1.75V */
+ GLB_LDO15CIS_LEVEL_1P80V = 14, /*!< GLB LDO15CIS voltage 1.80V */
+ GLB_LDO15CIS_LEVEL_1P85V = 15, /*!< GLB LDO15CIS voltage 1.85V */
+} GLB_LDO15CIS_LEVEL_Type;
+
+/*@} end of group GLB_Public_Types */
+
+/** @defgroup GLB_Public_Constants
+ * @{
+ */
+
+/** @defgroup GLB_CORE_ID_TYPE
+ * @{
+ */
+#define IS_GLB_CORE_ID_TYPE(type) (((type) == GLB_CORE_ID_M0) || \
+ ((type) == GLB_CORE_ID_D0) || \
+ ((type) == GLB_CORE_ID_LP) || \
+ ((type) == GLB_CORE_ID_MAX) || \
+ ((type) == GLB_CORE_ID_INVALID))
+
+/** @defgroup CCI_ID_TYPE
+ * @{
+ */
+#define IS_CCI_ID_TYPE(type) (((type) == CCI0_ID) || \
+ ((type) == CCI_ID_MAX))
+
+/** @defgroup GLB_DSP_ALL_INT_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_ALL_INT_TYPE(type) (((type) == GLB_DSP_ALL_INT_BUS_DEC_ERR_INT) || \
+ ((type) == GLB_DSP_ALL_INT_RSV1_INT) || \
+ ((type) == GLB_DSP_ALL_INT_IPC2_NP2AP_IRQ) || \
+ ((type) == GLB_DSP_ALL_INT_RSV3) || \
+ ((type) == GLB_DSP_ALL_INT_UART0_INT) || \
+ ((type) == GLB_DSP_ALL_INT_I2C0_INT) || \
+ ((type) == GLB_DSP_ALL_INT_I2C1_INT) || \
+ ((type) == GLB_DSP_ALL_INT_SPI_INT) || \
+ ((type) == GLB_DSP_ALL_INT_RSV4_INT) || \
+ ((type) == GLB_DSP_ALL_INT_RSV5_INT) || \
+ ((type) == GLB_DSP_ALL_INT_SEOF1_INT) || \
+ ((type) == GLB_DSP_ALL_INT_SEOF2_INT) || \
+ ((type) == GLB_DSP_ALL_INT_SEOF3_INT) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_0) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_1) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_2) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_3) || \
+ ((type) == GLB_DSP_ALL_INT_H264_BS_IRQ) || \
+ ((type) == GLB_DSP_ALL_INT_H264_FRAME_IRQ) || \
+ ((type) == GLB_DSP_ALL_INT_H264_SEQ_DONE_INT) || \
+ ((type) == GLB_DSP_ALL_INT_MJPEG_INT) || \
+ ((type) == GLB_DSP_ALL_INT_H264_S_BS_IRQ) || \
+ ((type) == GLB_DSP_ALL_INT_H264_S_FRAME_IRQ) || \
+ ((type) == GLB_DSP_ALL_INT_H264_S_SEQ_DONE_INT) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_0) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_1) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_2) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_3) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_4) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_5) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_6) || \
+ ((type) == GLB_DSP_ALL_INT_DMA_INTR_7) || \
+ ((type) == GLB_DSP_ALL_INT_RSV32) || \
+ ((type) == GLB_DSP_ALL_INT_RSV33) || \
+ ((type) == GLB_DSP_ALL_INT_RSV34) || \
+ ((type) == GLB_DSP_ALL_INT_RSV35) || \
+ ((type) == GLB_DSP_ALL_INT_RSV36) || \
+ ((type) == GLB_DSP_ALL_INT_MIPI_CSI_INT) || \
+ ((type) == GLB_DSP_ALL_INT_IPC2_AP2NP_IRQ) || \
+ ((type) == GLB_DSP_ALL_INT_RSV39) || \
+ ((type) == GLB_DSP_ALL_INT_MJDEC_INT) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_4) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_5) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_6) || \
+ ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_7) || \
+ ((type) == GLB_DSP_ALL_INT_DMA2D_INT_0) || \
+ ((type) == GLB_DSP_ALL_INT_DMA2D_INT_1) || \
+ ((type) == GLB_DSP_ALL_INT_DP_SOEF0_INT) || \
+ ((type) == GLB_DSP_ALL_INT_RSV48) || \
+ ((type) == GLB_DSP_ALL_INT_RSV49) || \
+ ((type) == GLB_DSP_ALL_INT_RSV50) || \
+ ((type) == GLB_DSP_ALL_INT_RSV51) || \
+ ((type) == GLB_DSP_ALL_INT_OSDDP_INT) || \
+ ((type) == GLB_DSP_ALL_INT_DBI_INT) || \
+ ((type) == GLB_DSP_ALL_INT_RSV6_INT) || \
+ ((type) == GLB_DSP_ALL_INT_OSDA_INT) || \
+ ((type) == GLB_DSP_ALL_INT_OSDB_INT) || \
+ ((type) == GLB_DSP_ALL_INT_OSD_PB_INT) || \
+ ((type) == GLB_DSP_ALL_INT_RSV7_INT) || \
+ ((type) == GLB_DSP_ALL_INT_MIPI_DSI_INT) || \
+ ((type) == GLB_DSP_ALL_INT_RSV8_INT) || \
+ ((type) == GLB_DSP_ALL_INT_MM_TIMER_IRQ2) || \
+ ((type) == GLB_DSP_ALL_INT_MM_TIMER_IRQ3) || \
+ ((type) == GLB_DSP_ALL_INT_MM_WDT_IRQ))
+
+/** @defgroup GLB_MCU_ALL_INT_TYPE
+ * @{
+ */
+#define IS_GLB_MCU_ALL_INT_TYPE(type) (((type) == GLB_MCU_ALL_INT_BMX_ERR_INT) || \
+ ((type) == GLB_MCU_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT) || \
+ ((type) == GLB_MCU_ALL_INT_IPC0_NP2AP_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_IPC0_AP2NP_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_AUDIO_INT) || \
+ ((type) == GLB_MCU_ALL_INT_RF_TOP_INT_0) || \
+ ((type) == GLB_MCU_ALL_INT_RF_TOP_INT_1) || \
+ ((type) == GLB_MCU_ALL_INT_LZ4_INT) || \
+ ((type) == GLB_MCU_ALL_INT_RSV8) || \
+ ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_GMAC_INT) || \
+ ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_CDET_INT) || \
+ ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_PKA_INT) || \
+ ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_TRNG_INT) || \
+ ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_AES_INT) || \
+ ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_SHA_INT) || \
+ ((type) == GLB_MCU_ALL_INT_DMA_INTR_ALL) || \
+ ((type) == GLB_MCU_ALL_INT_DMA2_INTR_ALL) || \
+ ((type) == GLB_MCU_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1) || \
+ ((type) == GLB_MCU_ALL_INT_MM_IRQ_ALL) || \
+ ((type) == GLB_MCU_ALL_INT_IRTX_INT) || \
+ ((type) == GLB_MCU_ALL_INT_IRRX_INT) || \
+ ((type) == GLB_MCU_ALL_INT_USB_INT) || \
+ ((type) == GLB_MCU_ALL_INT_AUPDM_INT) || \
+ ((type) == GLB_MCU_ALL_INT_SF_CTRL_ID0_INT) || \
+ ((type) == GLB_MCU_ALL_INT_EMAC_INT) || \
+ ((type) == GLB_MCU_ALL_INT_GPADC_DMA_INT) || \
+ ((type) == GLB_MCU_ALL_INT_EFUSE_INT) || \
+ ((type) == GLB_MCU_ALL_INT_SPI_0_INT) || \
+ ((type) == GLB_MCU_ALL_INT_UART_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_UART1_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_UART2_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_GPIO_DMA_INT) || \
+ ((type) == GLB_MCU_ALL_INT_I2C_0_INT) || \
+ ((type) == GLB_MCU_ALL_INT_PWM_INT) || \
+ ((type) == GLB_MCU_ALL_INT_IPC1_NP2AP_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_IPC1_AP2NP_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_TIMER0_2_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_TIMER0_3_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_WDT0_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_I2C_1_INT) || \
+ ((type) == GLB_MCU_ALL_INT_I2S0_INT) || \
+ ((type) == GLB_MCU_ALL_INT_RSV41) || \
+ ((type) == GLB_MCU_ALL_INT_RSV42) || \
+ ((type) == GLB_MCU_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_GPIO_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_DM_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_BT_IRQ) || \
+ ((type) == GLB_MCU_ALL_INT_M154_REQ_ENH_ACK_INT) || \
+ ((type) == GLB_MCU_ALL_INT_M154_INT) || \
+ ((type) == GLB_MCU_ALL_INT_M154_AES_INT) || \
+ ((type) == GLB_MCU_ALL_INT_PDS_INT) || \
+ ((type) == GLB_MCU_ALL_INT_HBN_IRQ_OUT_0) || \
+ ((type) == GLB_MCU_ALL_INT_HBN_IRQ_OUT_1) || \
+ ((type) == GLB_MCU_ALL_INT_BOR_OUT) || \
+ ((type) == GLB_MCU_ALL_INT_WIFI_TO_CPU_IRQ_N) || \
+ ((type) == GLB_MCU_ALL_INT_BZ_PHY_INT) || \
+ ((type) == GLB_MCU_ALL_INT_BLE_INT) || \
+ ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_RX_TIMER) || \
+ ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_RX_MISC) || \
+ ((type) == GLB_MCU_ALL_INT_MAC_INT_RX_TRIGGER) || \
+ ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_TRIGGER) || \
+ ((type) == GLB_MCU_ALL_INT_MAC_INT_GEN) || \
+ ((type) == GLB_MCU_ALL_INT_MAC_INT_PROT_TRIGGER) || \
+ ((type) == GLB_MCU_ALL_INT_WIFI_IPC))
+
+/** @defgroup GLB_LP_ALL_INT_TYPE
+ * @{
+ */
+#define IS_GLB_LP_ALL_INT_TYPE(type) (((type) == GLB_LP_ALL_INT_BMX_ERR_INT) || \
+ ((type) == GLB_LP_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT) || \
+ ((type) == GLB_LP_ALL_INT_IPC0_NP2AP_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_IPC0_AP2NP_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_AUDIO_INT) || \
+ ((type) == GLB_LP_ALL_INT_RF_TOP_INT_0) || \
+ ((type) == GLB_LP_ALL_INT_RF_TOP_INT_1) || \
+ ((type) == GLB_LP_ALL_INT_LZ4_INT) || \
+ ((type) == GLB_LP_ALL_INT_RSV8) || \
+ ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_GMAC_INT) || \
+ ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_CDET_INT) || \
+ ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_PKA_INT) || \
+ ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_TRNG_INT) || \
+ ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_AES_INT) || \
+ ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_SHA_INT) || \
+ ((type) == GLB_LP_ALL_INT_DMA_INTR_ALL) || \
+ ((type) == GLB_LP_ALL_INT_DMA2_INTR_ALL) || \
+ ((type) == GLB_LP_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1) || \
+ ((type) == GLB_LP_ALL_INT_MM_IRQ_ALL) || \
+ ((type) == GLB_LP_ALL_INT_IRTX_INT) || \
+ ((type) == GLB_LP_ALL_INT_IRRX_INT) || \
+ ((type) == GLB_LP_ALL_INT_USB_INT) || \
+ ((type) == GLB_LP_ALL_INT_AUPDM_INT) || \
+ ((type) == GLB_LP_ALL_INT_SF_CTRL_ID0_INT) || \
+ ((type) == GLB_LP_ALL_INT_EMAC_INT) || \
+ ((type) == GLB_LP_ALL_INT_GPADC_DMA_INT) || \
+ ((type) == GLB_LP_ALL_INT_EFUSE_INT) || \
+ ((type) == GLB_LP_ALL_INT_SPI_0_INT) || \
+ ((type) == GLB_LP_ALL_INT_UART_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_UART1_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_UART2_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_GPIO_DMA_INT) || \
+ ((type) == GLB_LP_ALL_INT_I2C_0_INT) || \
+ ((type) == GLB_LP_ALL_INT_PWM_INT) || \
+ ((type) == GLB_LP_ALL_INT_IPC1_NP2AP_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_IPC1_AP2NP_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_TIMER0_2_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_TIMER0_3_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_WDT0_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_I2C_1_INT) || \
+ ((type) == GLB_LP_ALL_INT_I2S0_INT) || \
+ ((type) == GLB_LP_ALL_INT_RSV41) || \
+ ((type) == GLB_LP_ALL_INT_RSV42) || \
+ ((type) == GLB_LP_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_GPIO_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_DM_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_BT_IRQ) || \
+ ((type) == GLB_LP_ALL_INT_M154_REQ_ENH_ACK_INT) || \
+ ((type) == GLB_LP_ALL_INT_M154_INT) || \
+ ((type) == GLB_LP_ALL_INT_M154_AES_INT) || \
+ ((type) == GLB_LP_ALL_INT_PDS_INT) || \
+ ((type) == GLB_LP_ALL_INT_HBN_IRQ_OUT_0) || \
+ ((type) == GLB_LP_ALL_INT_HBN_IRQ_OUT_1) || \
+ ((type) == GLB_LP_ALL_INT_BOR_OUT) || \
+ ((type) == GLB_LP_ALL_INT_WIFI_TO_CPU_IRQ_N) || \
+ ((type) == GLB_LP_ALL_INT_BZ_PHY_INT) || \
+ ((type) == GLB_LP_ALL_INT_BLE_INT) || \
+ ((type) == GLB_LP_ALL_INT_MAC_INT_TX_RX_TIMER) || \
+ ((type) == GLB_LP_ALL_INT_MAC_INT_TX_RX_MISC) || \
+ ((type) == GLB_LP_ALL_INT_MAC_INT_RX_TRIGGER) || \
+ ((type) == GLB_LP_ALL_INT_MAC_INT_TX_TRIGGER) || \
+ ((type) == GLB_LP_ALL_INT_MAC_INT_GEN) || \
+ ((type) == GLB_LP_ALL_INT_MAC_INT_PROT_TRIGGER) || \
+ ((type) == GLB_LP_ALL_INT_WIFI_IPC))
+
+/** @defgroup GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE(type) (((type) == GLB_DSP_MUXPLL_SEL_WIFIPLL_320M) || \
+ ((type) == GLB_DSP_MUXPLL_SEL_AUPLL_DIV1))
+
+/** @defgroup GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE(type) (((type) == GLB_DSP_MUXPLL_SEL_WIFIPLL_240M) || \
+ ((type) == GLB_DSP_MUXPLL_SEL_AUPLL_DIV2))
+
+/** @defgroup GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE(type) (((type) == GLB_DSP_MUXPLL_SEL_WIFIPLL_160M) || \
+ ((type) == GLB_DSP_MUXPLL_SEL_CPUPLL_160M))
+
+/** @defgroup GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(type) (((type) == GLB_MCU_MUXPLL_SEL_WIFIPLL_160M) || \
+ ((type) == GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_160M) || \
+ ((type) == GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV2) || \
+ ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV2P5))
+
+/** @defgroup GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(type) (((type) == GLB_MCU_MUXPLL_SEL_WIFIPLL_80M) || \
+ ((type) == GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_80M) || \
+ ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV5) || \
+ ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV6))
+
+/** @defgroup GLB_PLL_CGEN_TYPE
+ * @{
+ */
+#define IS_GLB_PLL_CGEN_TYPE(type) (((type) == GLB_PLL_CGEN_MM_WIFIPLL_160M) || \
+ ((type) == GLB_PLL_CGEN_MM_WIFIPLL_240M) || \
+ ((type) == GLB_PLL_CGEN_MM_WIFIPLL_320M) || \
+ ((type) == GLB_PLL_CGEN_MM_AUPLL_DIV1) || \
+ ((type) == GLB_PLL_CGEN_MM_AUPLL_DIV2) || \
+ ((type) == GLB_PLL_CGEN_EMI_CPUPLL_400M) || \
+ ((type) == GLB_PLL_CGEN_EMI_CPUPLL_200M) || \
+ ((type) == GLB_PLL_CGEN_EMI_WIFIPLL_320M) || \
+ ((type) == GLB_PLL_CGEN_EMI_AUPLL_DIV1) || \
+ ((type) == GLB_PLL_CGEN_TOP_CPUPLL_80M) || \
+ ((type) == GLB_PLL_CGEN_TOP_CPUPLL_100M) || \
+ ((type) == GLB_PLL_CGEN_TOP_CPUPLL_160M) || \
+ ((type) == GLB_PLL_CGEN_TOP_CPUPLL_400M) || \
+ ((type) == GLB_PLL_CGEN_TOP_WIFIPLL_240M) || \
+ ((type) == GLB_PLL_CGEN_TOP_WIFIPLL_320M) || \
+ ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV2) || \
+ ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV1))
+
+/** @defgroup GLB_MCU_SYS_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_MCU_SYS_CLK_TYPE(type) (((type) == GLB_MCU_SYS_CLK_RC32M) || \
+ ((type) == GLB_MCU_SYS_CLK_XTAL) || \
+ ((type) == GLB_MCU_SYS_CLK_CPUPLL_400M) || \
+ ((type) == GLB_MCU_SYS_CLK_WIFIPLL_240M) || \
+ ((type) == GLB_MCU_SYS_CLK_WIFIPLL_320M))
+
+/** @defgroup GLB_DSP_SYS_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_SYS_CLK_TYPE(type) (((type) == GLB_DSP_SYS_CLK_RC32M) || \
+ ((type) == GLB_DSP_SYS_CLK_XTAL) || \
+ ((type) == GLB_DSP_SYS_CLK_MM_WIFIPLL_240M) || \
+ ((type) == GLB_DSP_SYS_CLK_MM_WIFIPLL_320M) || \
+ ((type) == GLB_DSP_SYS_CLK_CPUPLL_400M))
+
+/** @defgroup GLB_DSP_SYS_PBCLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_SYS_PBCLK_TYPE(type) (((type) == GLB_DSP_SYS_PBCLK_RC32M) || \
+ ((type) == GLB_DSP_SYS_PBCLK_XTAL) || \
+ ((type) == GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M) || \
+ ((type) == GLB_DSP_SYS_PBCLK_CPUPLL_160M) || \
+ ((type) == GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M))
+
+/** @defgroup GLB_PLL_REF_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_PLL_REF_CLK_TYPE(type) (((type) == GLB_PLL_REFCLK_XTAL) || \
+ ((type) == GLB_PLL_REFCLK_RC32M))
+
+/** @defgroup GLB_WIFIPLL_REF_CLK_Type
+ * @{
+ */
+#define IS_GLB_WIFIPLL_REF_CLK_TYPE(type) (((type) == GLB_WIFIPLL_REF_XTAL_SOC_CLK) || \
+ ((type) == GLB_WIFIPLL_REF_XTAL_CLK) || \
+ ((type) == GLB_WIFIPLL_REF_XTAL_LO_CLK) || \
+ ((type) == GLB_WIFIPLL_REF_RC32M_CLK))
+
+/** @defgroup GLB_AUPLL_REF_CLK_Type
+ * @{
+ */
+#define IS_GLB_AUPLL_REF_CLK_TYPE(type) (((type) == GLB_AUPLL_REF_XTAL_SOC_CLK) || \
+ ((type) == GLB_AUPLL_REF_RC32M_CLK))
+
+/** @defgroup GLB_CPUPLL_REF_CLK_Type
+ * @{
+ */
+#define IS_GLB_CPUPLL_REF_CLK_TYPE(type) (((type) == GLB_CPUPLL_REF_XTAL_SOC_CLK) || \
+ ((type) == GLB_CPUPLL_REF_RC32M_CLK))
+
+/** @defgroup GLB_MIPIPLL_REF_CLK_Type
+ * @{
+ */
+#define IS_GLB_MIPIPLL_REF_CLK_TYPE(type) (((type) == GLB_MIPIPLL_REF_XTAL_SOC_CLK) || \
+ ((type) == GLB_MIPIPLL_REF_RC32M_CLK))
+
+/** @defgroup GLB_UHSPLL_REF_CLK_Type
+ * @{
+ */
+#define IS_GLB_UHSPLL_REF_CLK_TYPE(type) (((type) == GLB_UHSPLL_REF_XTAL_SOC_CLK) || \
+ ((type) == GLB_UHSPLL_REF_RC32M_CLK))
+
+/** @defgroup GLB_CAM_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) || \
+ ((type) == GLB_CAM_CLK_WIFIPLL_96M) || \
+ ((type) == GLB_CAM_CLK_CPUPLL_100M))
+
+/** @defgroup GLB_SDH_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_SDH_CLK_TYPE(type) (((type) == GLB_SDH_CLK_WIFIPLL_96M) || \
+ ((type) == GLB_SDH_CLK_CPUPLL_100M))
+
+/** @defgroup GLB_GLB_UART_SIG_SWAP_SET_TYPE
+ * @{
+ */
+#define IS_GLB_UART_SIG_SWAP_GRP_TYPE(type) (((type) == GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11) || \
+ ((type) == GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23) || \
+ ((type) == GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35) || \
+ ((type) == GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45))
+
+/** @defgroup GLB_I2S_OUT_REF_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \
+ ((type) == GLB_I2S_OUT_REF_CLK_SRC))
+
+/** @defgroup GLB_DMA_CLK_ID_TYPE
+ * @{
+ */
+#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA0_CLK_CH0) || \
+ ((type) == GLB_DMA0_CLK_CH1) || \
+ ((type) == GLB_DMA0_CLK_CH2) || \
+ ((type) == GLB_DMA0_CLK_CH3) || \
+ ((type) == GLB_DMA0_CLK_CH4) || \
+ ((type) == GLB_DMA0_CLK_CH5) || \
+ ((type) == GLB_DMA0_CLK_CH6) || \
+ ((type) == GLB_DMA0_CLK_CH7) || \
+ ((type) == GLB_DMA1_CLK_CH0) || \
+ ((type) == GLB_DMA1_CLK_CH1) || \
+ ((type) == GLB_DMA1_CLK_CH2) || \
+ ((type) == GLB_DMA1_CLK_CH3))
+
+/** @defgroup GLB_PERI_DMA_TYPE
+ * @{
+ */
+#define IS_GLB_PERI_DMA_TYPE(type) (((type) == GLB_PERI_DMA_UART0_RX) || \
+ ((type) == GLB_PERI_DMA_UART0_TX) || \
+ ((type) == GLB_PERI_DMA_UART1_RX) || \
+ ((type) == GLB_PERI_DMA_UART1_TX) || \
+ ((type) == GLB_PERI_DMA_UART2_RX) || \
+ ((type) == GLB_PERI_DMA_UART2_TX) || \
+ ((type) == GLB_PERI_DMA_I2C_0_RX) || \
+ ((type) == GLB_PERI_DMA_I2C_0_TX) || \
+ ((type) == GLB_PERI_DMA_IRTX_TX) || \
+ ((type) == GLB_PERI_DMA_GPIO_TX) || \
+ ((type) == GLB_PERI_DMA_SPI_RX) || \
+ ((type) == GLB_PERI_DMA_SPI_TX) || \
+ ((type) == GLB_PERI_DMA_AUDIO_RX) || \
+ ((type) == GLB_PERI_DMA_AUDIO_TX) || \
+ ((type) == GLB_PERI_DMA_I2C_1_RX) || \
+ ((type) == GLB_PERI_DMA_I2C_1_TX) || \
+ ((type) == GLB_PERI_DMA_I2S_0_RX) || \
+ ((type) == GLB_PERI_DMA_I2S_0_TX) || \
+ ((type) == GLB_PERI_DMA_PDM_RX) || \
+ ((type) == GLB_PERI_DMA_PADC) || \
+ ((type) == GLB_PERI_DMA_GAUGE) || \
+ ((type) == GLB_PERI_DMA_GPADC) || \
+ ((type) == GLB_PERI_DMA_GPDAC_TX))
+
+/** @defgroup GLB_PERI_DMA_CN_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_PERI_DMA_CN_SEL_TYPE(type) (((type) == GLB_PERI_DMA_CN_SEL_DMA0) || \
+ ((type) == GLB_PERI_DMA_CN_SEL_DMA1))
+
+/** @defgroup GLB_IR_CLK_SRC_TYPE
+ * @{
+ */
+#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK))
+
+/** @defgroup GLB_SFLASH_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M_WIFIPLL) || \
+ ((type) == GLB_SFLASH_CLK_XTAL) || \
+ ((type) == GLB_SFLASH_CLK_100M_CPUPLL) || \
+ ((type) == GLB_SFLASH_CLK_80M_MUXPLL) || \
+ ((type) == GLB_SFLASH_CLK_BCLK) || \
+ ((type) == GLB_SFLASH_CLK_96M_WIFIPLL))
+
+/** @defgroup GLB_I2C_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_I2C_CLK_TYPE(type) (((type) == GLB_I2C_CLK_BCLK) || \
+ ((type) == GLB_I2C_CLK_XCLK))
+
+/** @defgroup GLB_SPI_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_SPI_CLK_TYPE(type) (((type) == GLB_SPI_CLK_PLL160M) || \
+ ((type) == GLB_SPI_CLK_XCLK))
+
+/** @defgroup GLB_PWM1_IO_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_PWM1_IO_SEL_TYPE(type) (((type) == GLB_PWM1_IO_SINGLE_END) || \
+ ((type) == GLB_PWM1_IO_DIFF_END))
+
+/** @defgroup GLB_PWM2_IO_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_PWM2_IO_SEL_TYPE(type) (((type) == GLB_PWM2_IO_SINGLE_END) || \
+ ((type) == GLB_PWM2_IO_SINGLE_END_BLDC))
+
+/** @defgroup GLB_PDM_IO_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_PDM_IO_SEL_TYPE(type) (((type) == GLB_PDM_IO_SEL_AUDIO_TOP) || \
+ ((type) == GLB_PDM_IO_SEL_AUPDM_TOP))
+
+/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE
+ * @{
+ */
+#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \
+ ((type) == GLB_SPI_PAD_ACT_AS_MASTER))
+
+/** @defgroup GLB_AHB_SW_TYPE
+ * @{
+ */
+#define IS_GLB_AHB_MCU_SW_TYPE(type) (((type) == GLB_AHB_MCU_SW_RSV0) || \
+ ((type) == GLB_AHB_MCU_SW_RSV1) || \
+ ((type) == GLB_AHB_MCU_SW_WIFI) || \
+ ((type) == GLB_AHB_MCU_SW_BTDM) || \
+ ((type) == GLB_AHB_MCU_SW_ZIGBEE) || \
+ ((type) == GLB_AHB_MCU_SW_BLE2) || \
+ ((type) == GLB_AHB_MCU_SW_ZIGBEE2) || \
+ ((type) == GLB_AHB_MCU_SW_EMI_MISC) || \
+ ((type) == GLB_AHB_MCU_SW_PSRAM0_CTRL) || \
+ ((type) == GLB_AHB_MCU_SW_PSRAM1_CTRL) || \
+ ((type) == GLB_AHB_MCU_SW_USB) || \
+ ((type) == GLB_AHB_MCU_SW_MIX2) || \
+ ((type) == GLB_AHB_MCU_SW_AUDIO) || \
+ ((type) == GLB_AHB_MCU_SW_SDH) || \
+ ((type) == GLB_AHB_MCU_SW_EMAC) || \
+ ((type) == GLB_AHB_MCU_SW_DMA2) || \
+ ((type) == GLB_AHB_MCU_SW_GLB) || \
+ ((type) == GLB_AHB_MCU_SW_MIX) || \
+ ((type) == GLB_AHB_MCU_SW_GPIP) || \
+ ((type) == GLB_AHB_MCU_SW_SEC_DBG) || \
+ ((type) == GLB_AHB_MCU_SW_SEC_ENG) || \
+ ((type) == GLB_AHB_MCU_SW_TZ1) || \
+ ((type) == GLB_AHB_MCU_SW_TZ2) || \
+ ((type) == GLB_AHB_MCU_SW_EFUSE) || \
+ ((type) == GLB_AHB_MCU_SW_CCI) || \
+ ((type) == GLB_AHB_MCU_SW_L1C) || \
+ ((type) == GLB_AHB_MCU_SW_RSV42) || \
+ ((type) == GLB_AHB_MCU_SW_SF) || \
+ ((type) == GLB_AHB_MCU_SW_DMA) || \
+ ((type) == GLB_AHB_MCU_SW_SDU) || \
+ ((type) == GLB_AHB_MCU_SW_PDS) || \
+ ((type) == GLB_AHB_MCU_SW_RSV47) || \
+ ((type) == GLB_AHB_MCU_SW_UART0) || \
+ ((type) == GLB_AHB_MCU_SW_UART1) || \
+ ((type) == GLB_AHB_MCU_SW_SPI) || \
+ ((type) == GLB_AHB_MCU_SW_I2C) || \
+ ((type) == GLB_AHB_MCU_SW_PWM) || \
+ ((type) == GLB_AHB_MCU_SW_TIMER) || \
+ ((type) == GLB_AHB_MCU_SW_IR_REMOTE) || \
+ ((type) == GLB_AHB_MCU_SW_CHECKSUM) || \
+ ((type) == GLB_AHB_MCU_SW_QDEC) || \
+ ((type) == GLB_AHB_MCU_SW_KYS) || \
+ ((type) == GLB_AHB_MCU_SW_UART2) || \
+ ((type) == GLB_AHB_MCU_SW_RSV59) || \
+ ((type) == GLB_AHB_MCU_SW_RSV60) || \
+ ((type) == GLB_AHB_MCU_SW_RSV61) || \
+ ((type) == GLB_AHB_MCU_SW_RSV62) || \
+ ((type) == GLB_AHB_MCU_SW_RSV63) || \
+ ((type) == GLB_AHB_MCU_SW_PWRON_RST) || \
+ ((type) == GLB_AHB_MCU_SW_CPU_RESET) || \
+ ((type) == GLB_AHB_MCU_SW_SYS_RESET) || \
+ ((type) == GLB_AHB_MCU_SW_PICO_RESET) || \
+ ((type) == GLB_AHB_MCU_SW_CPU2_RESET) || \
+ ((type) == GLB_AHB_MCU_SW_CHIP_RESET) || \
+ ((type) == GLB_AHB_MCU_SW_WL_WDT_RESET_MM_EN) || \
+ ((type) == GLB_AHB_MCU_SW_MMWDT2WL_RST_MSK))
+
+/** @defgroup GLB_AHB_DSP_SW_TYPE
+ * @{
+ */
+#define IS_GLB_AHB_DSP_SW_TYPE(type) (((type) == GLB_AHB_DSP_SW_REG_CTRL_SYS_RESET) || \
+ ((type) == GLB_AHB_DSP_SW_REG_CTRL_PWRON_RST) || \
+ ((type) == GLB_AHB_DSP_SW_REG_CTRL_MMCPU0_RESET) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_MM_MISC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DMA) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_UART0) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_I2C0) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_I2C1) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_IPC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DMA2D) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_SPI) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_TIMER) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_I2S0) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_I2S1) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_PDM0) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_PDM1) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_PUHS) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_SUB_MISC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_SUB_MAIN) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_SUB_TSRC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DP_TSRC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_NR3D_CTRL) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSA) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSB) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSD) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_MIPI) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_SUB_REG) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSE) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSF) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSG) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSH) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_CODEC_MISC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_MJPEG) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_H264) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_MJPEG_DEC) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_CNN) || \
+ ((type) == GLB_AHB_DSP_SW_SWRST_VRAM) || \
+ ((type) == GLB_AHB_DSP_SW_RG_IS_RST_N))
+
+/** @defgroup GLB DISRST_TYPE
+ * @{
+ */
+#define IS_GLB_DISRST_TYPE(type) (((type) == GLB_DISRST_GPIP) || \
+ ((type) == GLB_DISRST_SEC_ENG) || \
+ ((type) == GLB_DISRST_CCI) || \
+ ((type) == GLB_DISRST_SF) || \
+ ((type) == GLB_DISRST_UART0) || \
+ ((type) == GLB_DISRST_UART1) || \
+ ((type) == GLB_DISRST_SPI) || \
+ ((type) == GLB_DISRST_I2C0) || \
+ ((type) == GLB_DISRST_PWM) || \
+ ((type) == GLB_DISRST_TIMER) || \
+ ((type) == GLB_DISRST_IR_REMOTE) || \
+ ((type) == GLB_DISRST_CHECKSUM) || \
+ ((type) == GLB_DISRST_IPC) || \
+ ((type) == GLB_DISRST_I2C1) || \
+ ((type) == GLB_DISRST_UART2))
+
+/** @defgroup GLB_PKA_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_MCU_BCLK) || \
+ ((type) == GLB_PKA_CLK_MCU_MUXPLL_160M))
+
+/** @defgroup GLB_MCU_SW_SYSTEM_TYPE
+ * @{
+ */
+#define IS_GLB_MCU_SW_SYSTEM_TYPE(type) (((type) == GLB_MCU_SW_SYSTEM_CTRL_MCU) || \
+ ((type) == GLB_MCU_SW_SYSTEM_CTRL_LP))
+
+/** @defgroup BMX_ARB_TYPE
+ * @{
+ */
+#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_ROUND_ROBIN) || \
+ ((type) == BMX_ARB_FIX))
+
+/** @defgroup BMX_LATCH_TYPE
+ * @{
+ */
+#define IS_BMX_LATCH_TYPE(type) (((type) == BMX_LATCH_FIRST_ERROR) || \
+ ((type) == BMX_LATCH_LAST_ERROR))
+
+/** @defgroup BMX_BUS_ERR_TYPE
+ * @{
+ */
+#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+ ((type) == BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup BMX_ERR_INT_TYPE
+ * @{
+ */
+#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \
+ ((type) == BMX_ERR_INT_ALL))
+
+/** @defgroup BMX_TO_INT_TYPE
+ * @{
+ */
+#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \
+ ((type) == BMX_TO_INT_ALL))
+
+/** @defgroup GLB_ETH_REF_CLK_OUT_TYPE
+ * @{
+ */
+#define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \
+ ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M))
+
+/** @defgroup GLB_EM_TYPE
+ * @{
+ */
+#define IS_GLB_EM_TYPE(type) (((type) == GLB_WRAM160KB_EM0KB) || \
+ ((type) == GLB_WRAM144KB_EM16KB) || \
+ ((type) == GLB_WRAM128KB_EM32KB) || \
+ ((type) == GLB_WRAM112KB_EM48KB) || \
+ ((type) == GLB_WRAM96KB_EM64KB))
+
+/** @defgroup GLB_ADC_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUPLL) || \
+ ((type) == GLB_ADC_CLK_XCLK))
+
+/** @defgroup GLB_DAC_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \
+ ((type) == GLB_DAC_CLK_XCLK))
+
+/** @defgroup GLB_CHIP_CLK_INOUT_TYPE
+ * @{
+ */
+#define IS_GLB_CHIP_CLK_INOUT_TYPE(type) (((type) == GLB_CHIP_CLK_INOUT_INPUT) || \
+ ((type) == GLB_CHIP_CLK_INOUT_OUTPUT))
+
+/** @defgroup GLB_CHIP_CLK_OUT_0_TYPE
+ * @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_0_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_0_CAM_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_0_I2S_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_0_CLK_AUDIO_ADC) || \
+ ((type) == GLB_CHIP_CLK_OUT_0_CLK_AUDIO_DAC))
+
+/** @defgroup GLB_CHIP_CLK_OUT_1_TYPE
+ * @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_1_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_1_CAM_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_1_I2S_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_1_CLK_AUDIO_ADC) || \
+ ((type) == GLB_CHIP_CLK_OUT_1_CLK_AUDIO_DAC))
+
+/** @defgroup GLB_CHIP_CLK_OUT_2_TYPE
+ * @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_2_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_2_CAM_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_2_I2S_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_2_ANA_XTAL_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_2_PLL_32M_CLK))
+
+/** @defgroup GLB_CHIP_CLK_OUT_3_TYPE
+ * @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_3_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_3_CAM_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_3_I2S_REF_CLK) || \
+ ((type) == GLB_CHIP_CLK_OUT_3_NONE) || \
+ ((type) == GLB_CHIP_CLK_OUT_3_PLL_48M_CLK))
+
+/** @defgroup GLB_CSI_DSI_CLK_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_CSI_DSI_CLK_SEL_TYPE(type) (((type) == GLB_CSI_DSI_CLK_SEL_XTAL_CLK) || \
+ ((type) == GLB_CSI_DSI_CLK_SEL_CPUPLL_DIV10))
+
+/** @defgroup GLB_DIG_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_WIFIPLL_32M) || \
+ ((type) == GLB_DIG_CLK_XCLK) || \
+ ((type) == GLB_DIG_CLK_AUPLL))
+
+/** @defgroup GLB_512K_CLK_OUT_TYPE
+ * @{
+ */
+#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \
+ ((type) == GLB_512K_CLK_OUT_256K) || \
+ ((type) == GLB_512K_CLK_OUT_128K))
+
+/** @defgroup GLB_BT_BANDWIDTH_TYPE
+ * @{
+ */
+#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \
+ ((type) == GLB_BT_BANDWIDTH_2M))
+
+/** @defgroup GLB_UART2_IO_SEL_TYPE
+ * @{
+ */
+#define IS_GLB_UART2_IO_SEL_TYPE(type) (((type) == GLB_UART2_IO_SEL_UART2) || \
+ ((type) == GLB_UART2_IO_SEL_ISO11898))
+
+/** @defgroup GLB_UART_SIG_TYPE
+ * @{
+ */
+#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \
+ ((type) == GLB_UART_SIG_1) || \
+ ((type) == GLB_UART_SIG_2) || \
+ ((type) == GLB_UART_SIG_3) || \
+ ((type) == GLB_UART_SIG_4) || \
+ ((type) == GLB_UART_SIG_5) || \
+ ((type) == GLB_UART_SIG_6) || \
+ ((type) == GLB_UART_SIG_7) || \
+ ((type) == GLB_UART_SIG_8) || \
+ ((type) == GLB_UART_SIG_9) || \
+ ((type) == GLB_UART_SIG_10) || \
+ ((type) == GLB_UART_SIG_11))
+
+/** @defgroup GLB_UART_SIG_FUN_TYPE
+ * @{
+ */
+#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \
+ ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \
+ ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \
+ ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \
+ ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \
+ ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \
+ ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \
+ ((type) == GLB_UART_SIG_FUN_UART1_RXD) || \
+ ((type) == GLB_UART_SIG_FUN_UART2_RTS) || \
+ ((type) == GLB_UART_SIG_FUN_UART2_CTS) || \
+ ((type) == GLB_UART_SIG_FUN_UART2_TXD) || \
+ ((type) == GLB_UART_SIG_FUN_UART2_RXD))
+
+/** @defgroup GLB_XTAL_TYPE
+ * @{
+ */
+#define IS_GLB_XTAL_TYPE(type) (((type) == GLB_XTAL_NONE) || \
+ ((type) == GLB_XTAL_24M) || \
+ ((type) == GLB_XTAL_32M) || \
+ ((type) == GLB_XTAL_38P4M) || \
+ ((type) == GLB_XTAL_40M) || \
+ ((type) == GLB_XTAL_26M) || \
+ ((type) == GLB_XTAL_RC32M) || \
+ ((type) == GLB_XTAL_MAX))
+
+/** @defgroup GLB_PLL_TYPE
+ * @{
+ */
+#define IS_GLB_PLL_TYPE(type) (((type) == GLB_PLL_NONE) || \
+ ((type) == GLB_PLL_WIFIPLL) || \
+ ((type) == GLB_PLL_AUPLL) || \
+ ((type) == GLB_PLL_CPUPLL) || \
+ ((type) == GLB_PLL_MIPIPLL) || \
+ ((type) == GLB_PLL_UHSPLL))
+
+/** @defgroup GLB_WAC_PLL_TYPE
+ * @{
+ */
+#define IS_GLB_WAC_PLL_TYPE(type) (((type) == GLB_WAC_PLL_WIFIPLL) || \
+ ((type) == GLB_WAC_PLL_AUPLL) || \
+ ((type) == GLB_WAC_PLL_CPUPLL))
+
+/** @defgroup GLB_MU_PLL_TYPE
+ * @{
+ */
+#define IS_GLB_MU_PLL_TYPE(type) (((type) == GLB_MU_PLL_MIPIPLL) || \
+ ((type) == GLB_MU_PLL_UHSPLL))
+
+/** @defgroup GLB_DISP_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DISP_CLK_TYPE(type) (((type) == GLB_DISP_CLK_MIPIPLL_1500M))
+
+/** @defgroup GLB_PSRAM_PLL_TYPE
+ * @{
+ */
+#define IS_GLB_PSRAM_PLL_TYPE(type) (((type) == GLB_PSRAM_EMI_CPUPLL_400M) || \
+ ((type) == GLB_PSRAM_EMI_WIFIPLL_320M) || \
+ ((type) == GLB_PSRAM_EMI_AUPLL_DIV1))
+
+/** @defgroup GLB_DSP_XCLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_XCLK_TYPE(type) (((type) == GLB_DSP_XCLK_RC32M) || \
+ ((type) == GLB_DSP_XCLK_XTAL))
+
+/** @defgroup GLB_DSP_ROOT_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_ROOT_CLK_TYPE(type) (((type) == GLB_DSP_ROOT_CLK_XCLK) || \
+ ((type) == GLB_DSP_ROOT_CLK_PLL))
+
+/** @defgroup GLB_DSP_PBROOT_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_PBROOT_CLK_TYPE(type) (((type) == GLB_DSP_PBROOT_CLK_MM_XCLK) || \
+ ((type) == GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M) || \
+ ((type) == GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M))
+
+/** @defgroup GLB_DSP_PLL_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_PLL_CLK_TYPE(type) (((type) == GLB_DSP_PLL_CLK_MUXPLL_240M) || \
+ ((type) == GLB_DSP_PLL_CLK_MUXPLL_320M) || \
+ ((type) == GLB_DSP_PLL_CLK_CPUPLL_400M))
+
+/** @defgroup GLB_DSP_UART_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_UART_CLK_TYPE(type) (((type) == GLB_DSP_UART_CLK_DSP_PBCLK) || \
+ ((type) == GLB_DSP_UART_CLK_MUXPLL_160M) || \
+ ((type) == GLB_DSP_UART_CLK_DSP_XCLK))
+
+/** @defgroup GLB_UART_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_UART_CLK_TYPE(type) (((type) == GLB_UART_CLK_BCLK) || \
+ ((type) == GLB_UART_CLK_PLL_160M))
+
+/** @defgroup GLB_DSP_CNN_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_CNN_CLK_TYPE(type) (((type) == GLB_DSP_CNN_CLK_160M) || \
+ ((type) == GLB_DSP_CNN_CLK_240M) || \
+ ((type) == GLB_DSP_CNN_CLK_320M))
+
+/** @defgroup GLB_DSP_DP_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_DP_CLK_TYPE(type) (((type) == GLB_DSP_DP_CLK_DISPLAY_PLL) || \
+ ((type) == GLB_DSP_DP_CLK_DSP_XCLK))
+
+/** @defgroup GLB_DSP_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_CLK_TYPE(type) (((type) == GLB_DSP_CLK_MUXPLL_160M) || \
+ ((type) == GLB_DSP_CLK_MUXPLL_240M) || \
+ ((type) == GLB_DSP_CLK_CPUPLL_400M) || \
+ ((type) == GLB_DSP_CLK_DSP_XCLK))
+
+/** @defgroup GLB_DSP_H264_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_H264_CLK_TYPE(type) (((type) == GLB_DSP_H264_DSP_MUXPLL_160M) || \
+ ((type) == GLB_DSP_H264_DSP_MUXPLL_240M) || \
+ ((type) == GLB_DSP_H264_DSP_MUXPLL_320M))
+
+/** @defgroup GLB_DSP_SPI_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_SPI_CLK_TYPE(type) (((type) == GLB_DSP_SPI_CLK_DSP_MUXPLL_160M) || \
+ ((type) == GLB_DSP_SPI_CLK_DSP_XCLK))
+
+/** @defgroup GLB_DSP_I2C_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_I2C_CLK_TYPE(type) (((type) == GLB_DSP_I2C_CLK_DSP_PBCLK) || \
+ ((type) == GLB_DSP_I2C_CLK_XCLK))
+
+/** @defgroup GLB_I2S_DI_REF_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_I2S_DI_REF_CLK_TYPE(type) (((type) == GLB_I2S_DI_SEL_I2S_DI_INPUT) || \
+ ((type) == GLB_I2S_DI_SEL_I2S_REF_OUTPUT))
+
+/** @defgroup GLB_I2S_DO_REF_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_I2S_DO_REF_CLK_TYPE(type) (((type) == GLB_I2S_DO_SEL_I2S_DO_OUTPT) || \
+ ((type) == GLB_I2S_DO_SEL_I2S_REF_OUTPUT))
+
+/** @defgroup GLB_EMI_CLK_TYPE
+ * @{
+ */
+#define IS_GLB_EMI_CLK_TYPE(type) (((type) == GLB_EMI_CLK_MCU_PBCLK) || \
+ ((type) == GLB_EMI_CLK_CPUPLL_200M_CLK) || \
+ ((type) == GLB_EMI_CLK_WIFIPLL_320M_CLK) || \
+ ((type) == GLB_EMI_CLK_CPUPLL_400M_CLK))
+
+/** @defgroup GLB_DSP_SW_SYSTEM_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_SW_SYSTEM_TYPE(type) (((type) == GLB_DSP_SW_SYSTEM_CTRL_SYS) || \
+ ((type) == GLB_DSP_SW_SYSTEM_CTRL_PWRON) || \
+ ((type) == GLB_DSP_SW_SYSTEM_CTRL_DSP0) || \
+ ((type) == GLB_DSP_SW_SYSTEM_CTRL_DSP1) || \
+ ((type) == GLB_DSP_SW_SYSTEM_CTRL_WL2MM))
+
+/** @defgroup GLB_DSP_PERIPHERAL_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_PERIPHERAL_TYPE(type) (((type) == GLB_DSP_PERIPHERAL_MM_MISC) || \
+ ((type) == GLB_DSP_PERIPHERAL_DMA) || \
+ ((type) == GLB_DSP_PERIPHERAL_UART0) || \
+ ((type) == GLB_DSP_PERIPHERAL_I2C0) || \
+ ((type) == GLB_DSP_PERIPHERAL_IPC) || \
+ ((type) == GLB_DSP_PERIPHERAL_SPI) || \
+ ((type) == GLB_DSP_PERIPHERAL_TIMER) || \
+ ((type) == GLB_DSP_PERIPHERAL_I2S0))
+
+/** @defgroup GLB_DSP_SUB_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_SUB_TYPE(type) (((type) == GLB_DSP_SUB_MISC) || \
+ ((type) == GLB_DSP_SUB_DVP2BUSA) || \
+ ((type) == GLB_DSP_SUB_DVP2BUSB) || \
+ ((type) == GLB_DSP_SUB_DVP2BUSC) || \
+ ((type) == GLB_DSP_SUB_OSD_DRAW) || \
+ ((type) == GLB_DSP_SUB_DP) || \
+ ((type) == GLB_DSP_SUB_IMG_PR) || \
+ ((type) == GLB_DSP_SUB_SCLRA) || \
+ ((type) == GLB_DSP_SUB_SCLRB))
+
+/** @defgroup GLB_DSP_CODEC_SUB_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_CODEC_SUB_TYPE(type) (((type) == GLB_DSP_CODEC_SUB_MJPEG) || \
+ ((type) == GLB_DSP_CODEC_SUB_CNN) || \
+ ((type) == GLB_DSP_CODEC_SUB_VRAM))
+
+/** @defgroup GLB_DSP_IMAGE_SENSOR_TYPE
+ * @{
+ */
+#define IS_GLB_DSP_IMAGE_SENSOR_TYPE(type) (((type) == GLB_DSP_IMAGE_SENSOR_RG_IS))
+
+/** @defgroup GLB_LDO15CIS_LEVEL_TYPE
+ * @{
+ */
+#define IS_GLB_LDO15CIS_LEVEL_TYPE(type) (((type) == GLB_LDO15CIS_LEVEL_1P00V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P05V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P10V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P15V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P20V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P30V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P40V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P45V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P50V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P55V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P60V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P65V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P70V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P75V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P80V) || \
+ ((type) == GLB_LDO15CIS_LEVEL_1P85V))
+
+/*@} end of group GLB_Public_Constants */
+
+/** @defgroup GLB_Public_Macros
+ * @{
+ */
+#define UART_SIG_SWAP_NONE (0x00) /* uart_sig[0:11] -> uart_sig[0:11] */
+#define UART_SIG_SWAP_GPIO0_GPIO11 (0x01) /* GPIO0-11 uart_sig[ 0:11] -> uart_sig[ 6:11], uart_sig[ 0: 5] */
+#define UART_SIG_SWAP_GPIO12_GPIO23 (0x02) /* GPIO12-23 uart_sig[12:23] -> uart_sig[18:23], uart_sig[12:17] */
+#define UART_SIG_SWAP_GPIO24_GPIO35 (0x04) /* GPIO24-35 uart_sig[24:35] -> uart_sig[30:35], uart_sig[24:29] */
+#define UART_SIG_SWAP_GPIO36_GPIO47 (0x08) /* GPIO36-47 uart_sig[36:47] -> uart_sig[42:47], uart_sig[36:41] */
+
+#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+
+#define GLB_AHB_CLOCK_CPU (0x1ULL<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_GLB_GPIO_H__
+#define __BL808_GLB_GPIO_H__
+
+#include "glb_reg.h"
+#include "mm_glb_reg.h"
+#include "pds_reg.h"
+#include "bl808_gpio.h"
+#include "bl808_hbn.h"
+#include "bl808_aon.h"
+#include "bl808_pds.h"
+#include "bl808_common.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup GLB_GPIO
+ * @{
+ */
+
+/** @defgroup GLB_GPIO_Public_Types
+ * @{
+ */
+
+/**
+ * @brief GLB GPIO interrupt control mode type definition
+ */
+typedef enum {
+ GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE = 0, /*!< GPIO interrupt sync mode, GPIO falling edge trigger interrupt */
+ GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE = 1, /*!< GPIO interrupt sync mode, GPIO rising edge trigger interrupt */
+ GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL = 2, /*!< GPIO interrupt sync mode, GPIO low level trigger interrupt (32k 3T) */
+ GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL = 3, /*!< GPIO interrupt sync mode, GPIO high level trigger interrupt (32k 3T) */
+ GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE = 4, /*!< GPIO interrupt sync mode, GPIO falling and rising edge trigger interrupt */
+ GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE = 8, /*!< GPIO interrupt async mode, GPIO falling edge trigger interrupt */
+ GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE = 9, /*!< GPIO interrupt async mode, GPIO rising edge trigger interrupt */
+ GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL = 10, /*!< GPIO interrupt async mode, GPIO low level trigger interrupt (32k 3T) */
+ GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL = 11, /*!< GPIO interrupt async mode, GPIO high level trigger interrupt (32k 3T) */
+} GLB_GPIO_INT_TRIG_Type;
+
+/**
+ * @brief GLB GPIO FIFO interrupt type definition
+ */
+typedef enum {
+ GLB_GPIO_FIFO_INT_FER, /*!< GLB GPIO FIFO Underflow or Overflow interrupt */
+ GLB_GPIO_FIFO_INT_FIFO, /*!< GLB GPIO FIFO ready (tx_fifo_cnt > tx_fifo_th) interrupt */
+ GLB_GPIO_FIFO_INT_END, /*!< GLB GPIO FIFO Empty interrupt */
+ GLB_GPIO_FIFO_INT_ALL, /*!< All the interrupt */
+} GLB_GPIO_FIFO_INT_Type;
+
+/**
+ * @brief GLB GPIO FIFO Timing Phase type definition
+ */
+typedef enum {
+ GPIO_FIFO_PHASE_FIRST_HIGH, /*!< GPIO first send high level */
+ GPIO_FIFO_PHASE_FIRST_LOW, /*!< GPIO first send low level */
+} GLB_GPIO_FIFO_PHASE_Type;
+
+/**
+ * @brief GLB GPIO FIFO Idle State type definition
+ */
+typedef enum {
+ GPIO_FIFO_IDLE_LOW,
+ GPIO_FIFO_IDLE_HIGH,
+} GLB_GPIO_FIFO_IDLE_Type;
+
+/**
+ * @brief GLB GPIO FIFO Latch Mode type definition
+ */
+typedef enum {
+ GPIO_FIFO_LATCH_WRITE, /*!< GPIO FIFO direct write I/O */
+ GPIO_FIFO_LATCH_SETCLEAR, /*!< GPIO FIFO set/clr I/O */
+} GLB_GPIO_FIFO_LATCH_Type;
+
+/**
+ * @brief GPIO interrupt configuration structure type definition
+ */
+typedef struct
+{
+ GLB_GPIO_Type gpioPin; /*!< GPIO pin num */
+ GLB_GPIO_INT_TRIG_Type trig; /*!< GPIO interrupt trig mode */
+ BL_Mask_Type intMask; /*!< GPIO interrupt mask config */
+} GLB_GPIO_INT_Cfg_Type;
+
+/**
+ * @brief UART configuration structure type definition
+ */
+typedef struct
+{
+ uint8_t code0FirstTime; /*!< The clock num of code0 first send */
+ uint8_t code1FirstTime; /*!< The clock num of code1 first send */
+ uint16_t codeTotalTime; /*!< The total clock num of code0/1(high + low */
+ GLB_GPIO_FIFO_PHASE_Type code0Phase; /*!< low or high level of code0 first send */
+ GLB_GPIO_FIFO_PHASE_Type code1Phase; /*!< low or high level of code1 first send */
+ GLB_GPIO_FIFO_IDLE_Type idle; /*!< the I/O idle level */
+ uint8_t fifoDmaThreshold; /*!< FIFO threshold */
+ BL_Fun_Type fifoDmaEnable; /*!< Enable or disable DMA of GPIO */
+ GLB_GPIO_FIFO_LATCH_Type latch; /*!< Write or set/clr GPIO level */
+} GLB_GPIO_FIFO_CFG_Type;
+
+/*@} end of group GLB_GPIO_Public_Types */
+
+/** @defgroup GLB_GPIO_Public_Constants
+ * @{
+ */
+
+/** @defgroup GLB_GPIO_INT_TRIG_TYPE
+ * @{
+ */
+#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE) || \
+ ((type) == GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE) || \
+ ((type) == GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL) || \
+ ((type) == GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL) || \
+ ((type) == GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE) || \
+ ((type) == GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE) || \
+ ((type) == GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE) || \
+ ((type) == GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL) || \
+ ((type) == GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL))
+
+/** @defgroup GLB_GPIO_INT_TRIG_TYPE
+ * @{
+ */
+#define IS_GLB_GPIO_FIFO_INT_TYPE(type) (((type) == GLB_GPIO_INT_FER) || \
+ ((type) == GLB_GPIO_INT_FIFO) || \
+ ((type) == GLB_GPIO_INT_END) || \
+ ((type) == GLB_GPIO_FIFO_INT_ALL))
+
+/** @defgroup GLB_GPIO_FIFO_PHASE_TYPE
+ * @{
+ */
+#define IS_GLB_GPIO_FIFO_PHASE_TYPE(type) (((type) == GPIO_FIFO_HIGH_FIRST_LOW_FOLLOWED) || \
+ ((type) == GPIO_FIFO_LOW_FIRST_HIGH_FOLLOWED))
+
+/** @defgroup GLB_GPIO_FIFO_PHASE_TYPE
+ * @{
+ */
+#define IS_GLB_GPIO_FIFO_LATCH_TYPE(type) (((type) == GPIO_FIFO_LATCH_WRITE) || \
+ ((type) == GPIO_FIFO_LATCH_SETCLEAR))
+
+/*@} end of group GLB_GPIO_Public_Constants */
+
+/** @defgroup GLB_GPIO_Public_Macros
+ * @{
+ */
+
+/*@} end of group GLB_GPIO_Public_Macros */
+
+/** @defgroup GLB_GPIO_Public_Functions
+ * @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_INT0_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg);
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt);
+BL_Err_Type GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Embedded_Flash_Pad_Enable(void);
+BL_Err_Type GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
+uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val);
+BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg);
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void);
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
+
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_FIFO_IRQHandler(void);
+#endif
+BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type GLB_GPIO_Fifo_IRQHandler_Install(void);
+BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg);
+BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len);
+uint32_t GLB_GPIO_Fifo_GetCount(void);
+BL_Err_Type GLB_GPIO_Fifo_Clear(void);
+BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask);
+BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType);
+BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType);
+BL_Sts_Type GLB_GPIO_Fifo_Enable(void);
+BL_Sts_Type GLB_GPIO_Fifo_Disable(void);
+
+/*@} end of group GLB_GPIO_Public_Functions */
+
+/*@} end of group GLB_GPIO */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_GLB_GPIO_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_gpio.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_gpio.h
new file mode 100644
index 00000000..f4c0fb6f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_gpio.h
@@ -0,0 +1,166 @@
+/**
+ ******************************************************************************
+ * @file bl808_gpio.h
+ * @version V1.0
+ * @date 2020-11-06
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_GPIO_H__
+#define __BL808_GPIO_H__
+
+typedef enum {
+ GLB_GPIO_PIN_0 = 0,
+ GLB_GPIO_PIN_1,
+ GLB_GPIO_PIN_2,
+ GLB_GPIO_PIN_3,
+ GLB_GPIO_PIN_4,
+ GLB_GPIO_PIN_5,
+ GLB_GPIO_PIN_6,
+ GLB_GPIO_PIN_7,
+ GLB_GPIO_PIN_8,
+ GLB_GPIO_PIN_9,
+ GLB_GPIO_PIN_10,
+ GLB_GPIO_PIN_11,
+ GLB_GPIO_PIN_12,
+ GLB_GPIO_PIN_13,
+ GLB_GPIO_PIN_14,
+ GLB_GPIO_PIN_15,
+ GLB_GPIO_PIN_16,
+ GLB_GPIO_PIN_17,
+ GLB_GPIO_PIN_18,
+ GLB_GPIO_PIN_19,
+ GLB_GPIO_PIN_20,
+ GLB_GPIO_PIN_21,
+ GLB_GPIO_PIN_22,
+ GLB_GPIO_PIN_23,
+ GLB_GPIO_PIN_24,
+ GLB_GPIO_PIN_25,
+ GLB_GPIO_PIN_26,
+ GLB_GPIO_PIN_27,
+ GLB_GPIO_PIN_28,
+ GLB_GPIO_PIN_29,
+ GLB_GPIO_PIN_30,
+ GLB_GPIO_PIN_31,
+ GLB_GPIO_PIN_32,
+ GLB_GPIO_PIN_33,
+ GLB_GPIO_PIN_34,
+ GLB_GPIO_PIN_35,
+ GLB_GPIO_PIN_36,
+ GLB_GPIO_PIN_37,
+ GLB_GPIO_PIN_38,
+ GLB_GPIO_PIN_39,
+ GLB_GPIO_PIN_40,
+ GLB_GPIO_PIN_41,
+ GLB_GPIO_PIN_42,
+ GLB_GPIO_PIN_43,
+ GLB_GPIO_PIN_44,
+ GLB_GPIO_PIN_45,
+ GLB_GPIO_PIN_MAX,
+} GLB_GPIO_Type;
+
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
+#define GPIO_MODE_AF ((uint32_t)0x00000002U) /*!< Alternate function */
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function */
+#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */
+#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */
+#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */
+#define GPIO_OUTPUT_VALUE_MODE ((uint8_t)0x00U) /*!< GPIO Output by reg_gpio_x_o Value */
+#define GPIO_SET_CLR_MODE ((uint8_t)0x01U) /*!< GPIO Output set by reg_gpio_x_set and clear by reg_gpio_x_clr */
+#define GPIO_DMA_OUTPUT_VALUE_MODE ((uint8_t)0x02U) /*!< GPIO Output value by gpio_dma_o */
+#define GPIO_DMA_SET_CLR_MODE ((uint8_t)0x03U) /*!< GPIO Outout value by gpio_dma_set/gpio_dma_clr */
+
+typedef enum {
+ GPIO_FUN_SDH = 0,
+ GPIO_FUN_SPI0 = 1,
+ GPIO_FUN_FLASH = 2,
+ GPIO_FUN_I2S = 3,
+ GPIO_FUN_PDM = 4,
+ GPIO_FUN_I2C0 = 5,
+ GPIO_FUN_I2C1 = 6,
+ GPIO_FUN_UART = 7,
+ GPIO_FUN_ETHER_MAC = 8,
+ GPIO_FUN_CAM = 9,
+ GPIO_FUN_ANALOG = 10,
+ GPIO_FUN_GPIO = 11,
+ GPIO_FUN_PWM0 = 16,
+ GPIO_FUN_PWM1 = 17,
+ GPIO_FUN_SPI1 = 18,
+ GPIO_FUN_I2C2 = 19,
+ GPIO_FUN_I2C3 = 20,
+ GPIO_FUN_MM_UART = 21,
+ GPIO_FUN_DBI_B = 22,
+ GPIO_FUN_DBI_C = 23,
+ GPIO_FUN_DPI = 24,
+ GPIO_FUN_JTAG_LP = 25,
+ GPIO_FUN_JTAG_M0 = 26,
+ GPIO_FUN_JTAG_D0 = 27,
+ GPIO_FUN_CLOCK_OUT = 31,
+
+ GPIO_FUN_CLOCK_OUT_X_CAM_REF_CLK = 0xE0,
+ GPIO_FUN_CLOCK_OUT_X_I2S_REF_CLK = 0xE1,
+ GPIO_FUN_CLOCK_OUT_0_1_AUDIO_ADC_CLK = 0xE2,
+ GPIO_FUN_CLOCK_OUT_0_1_AUDIO_DAC_CLK = 0xE3,
+ GPIO_FUN_CLOCK_OUT_2_ANA_XTAL_CLK = 0xE2,
+ GPIO_FUN_CLOCK_OUT_2_PLL_32M_CLK = 0xE3,
+ GPIO_FUN_CLOCK_OUT_3_NONE = 0xE2,
+ GPIO_FUN_CLOCK_OUT_3_PLL_48M_CLK = 0xE3,
+
+ GPIO_FUN_UART0_RTS = 0xF0,
+ GPIO_FUN_UART0_CTS = 0xF1,
+ GPIO_FUN_UART0_TX = 0xF2,
+ GPIO_FUN_UART0_RX = 0xF3,
+ GPIO_FUN_UART1_RTS = 0xF4,
+ GPIO_FUN_UART1_CTS = 0xF5,
+ GPIO_FUN_UART1_TX = 0xF6,
+ GPIO_FUN_UART1_RX = 0xF7,
+ GPIO_FUN_UART2_RTS = 0xF8,
+ GPIO_FUN_UART2_CTS = 0xF9,
+ GPIO_FUN_UART2_TX = 0xFA,
+ GPIO_FUN_UART2_RX = 0xFB,
+
+ GPIO_FUN_UART3 = 21,
+
+ GPIO_FUN_UNUSED = 0xFF,
+} GLB_GPIO_FUNC_Type;
+
+typedef struct
+{
+ uint8_t gpioPin;
+ uint8_t gpioFun;
+ uint8_t gpioMode;
+ uint8_t pullType;
+ uint8_t drive;
+ uint8_t smtCtrl;
+ uint8_t outputMode;
+} GLB_GPIO_Cfg_Type;
+
+#endif /*__BL808_GPIO_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_hbn.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_hbn.h
new file mode 100644
index 00000000..6f151ee2
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_hbn.h
@@ -0,0 +1,677 @@
+/**
+ ******************************************************************************
+ * @file bl808_hbn.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_HBN_H__
+#define __BL808_HBN_H__
+
+#include "hbn_reg.h"
+#include "bl808_aon.h"
+#include "bl808_l1c.h"
+#include "bl808_common.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup HBN
+ * @{
+ */
+
+/** @defgroup HBN_Public_Types
+ * @{
+ */
+
+/**
+ * @brief HBN PIR interrupt configuration type definition
+ */
+typedef struct
+{
+ BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */
+ BL_Fun_Type highIntEn; /*!< High will trigger interrupt */
+} HBN_PIR_INT_CFG_Type;
+
+/**
+ * @brief HBN PIR low pass filter type definition
+ */
+typedef enum {
+ HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */
+ HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */
+} HBN_PIR_LPF_Type;
+
+/**
+ * @brief HBN PIR high pass filter type definition
+ */
+typedef enum {
+ HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */
+ HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */
+ HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */
+} HBN_PIR_HPF_Type;
+
+/**
+ * @brief HBN flash pad pu pd type
+ */
+typedef enum {
+ HBN_FLASH_PAD_PULL_NONE, /*!< flash pad pull none when Flash at Deep Power Down Mode */
+ HBN_FLASH_PAD_PULL_UP, /*!< flash pad pull up when Flash at Deep Power Down Mode */
+ HBN_FLASH_PAD_PULL_DOWN, /*!< flash pad pull down when Flash at Deep Power Down Mode */
+} HBN_FLASH_PAD_PULL_Type;
+
+/**
+ * @brief HBN BOD threshold type definition
+ */
+typedef enum {
+ HBN_BOD_THRES_2P05V, /*!< BOD threshold 2.05V */
+ HBN_BOD_THRES_2P10V, /*!< BOD threshold 2.10V */
+ HBN_BOD_THRES_2P15V, /*!< BOD threshold 2.15V */
+ HBN_BOD_THRES_2P20V, /*!< BOD threshold 2.20V */
+ HBN_BOD_THRES_2P25V, /*!< BOD threshold 2.25V */
+ HBN_BOD_THRES_2P30V, /*!< BOD threshold 2.30V */
+ HBN_BOD_THRES_2P35V, /*!< BOD threshold 2.35V */
+ HBN_BOD_THRES_2P40V, /*!< BOD threshold 2.40V */
+} HBN_BOD_THRES_Type;
+
+/**
+ * @brief HBN BOD mode type definition
+ */
+typedef enum {
+ HBN_BOD_MODE_POR_INDEPENDENT, /*!< POR is independent of BOD */
+ HBN_BOD_MODE_POR_RELEVANT, /*!< POR is relevant to BOD */
+} HBN_BOD_MODE_Type;
+
+/**
+ * @brief HBN 32K clock type definition
+ */
+typedef enum {
+ HBN_32K_RC = 0, /*!< HBN use rc 32k */
+ HBN_32K_XTAL, /*!< HBN use xtal 32k */
+ HBN_32K_DIG = 3, /*!< HBN use dig 32k */
+} HBN_32K_CLK_Type;
+
+/**
+ * @brief HBN xclk clock type definition
+ */
+typedef enum {
+ HBN_MCU_XCLK_RC32M, /*!< use RC32M as xclk clock */
+ HBN_MCU_XCLK_XTAL, /*!< use XTAL as xclk clock */
+} HBN_MCU_XCLK_Type;
+
+/**
+ * @brief HBN root clock type definition
+ */
+typedef enum {
+ HBN_MCU_ROOT_CLK_XCLK, /*!< use XCLK as root clock */
+ HBN_MCU_ROOT_CLK_PLL, /*!< use PLL as root clock */
+} HBN_MCU_ROOT_CLK_Type;
+
+/**
+ * @brief HBN UART clock type definition
+ */
+typedef enum {
+ HBN_UART_CLK_MCU_PBCLK = 0, /*!< Select mcu_pbclk as UART clock */
+ HBN_UART_CLK_160M, /*!< Select 160M as UART clock */
+ HBN_UART_CLK_XCLK, /*!< Select XCLK as UART clock */
+} HBN_UART_CLK_Type;
+
+/**
+ * @brief HBN RTC interrupt delay type definition
+ */
+typedef enum {
+ HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */
+ HBN_RTC_INT_DELAY_0T = 1, /*!< HBN RTC interrupt delay 0T */
+} HBN_RTC_INT_Delay_Type;
+
+/**
+ * @brief HBN interrupt type definition
+ */
+typedef enum {
+ HBN_INT_GPIO9 = 0, /*!< HBN interrupt type: GPIO9 */
+ HBN_INT_GPIO10 = 1, /*!< HBN interrupt type: GPIO10 */
+ HBN_INT_GPIO11 = 2, /*!< HBN interrupt type: GPIO11 */
+ HBN_INT_GPIO12 = 3, /*!< HBN interrupt type: GPIO12 */
+ HBN_INT_GPIO13 = 4, /*!< HBN interrupt type: GPIO13 */
+ HBN_INT_GPIO14 = 5, /*!< HBN interrupt type: GPIO14 */
+ HBN_INT_GPIO15 = 6, /*!< HBN interrupt type: GPIO15 */
+ HBN_INT_GPIO40 = 7, /*!< HBN interrupt type: GPIO40 */
+ HBN_INT_GPIO41 = 8, /*!< HBN interrupt type: GPIO41 */
+ HBN_INT_RTC = 16, /*!< HBN interrupt type: RTC */
+ HBN_INT_PIR = 17, /*!< HBN interrupt type: PIR */
+ HBN_INT_BOD = 18, /*!< HBN interrupt type: BOD */
+ HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */
+ HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */
+} HBN_INT_Type;
+
+/**
+ * @brief HBN aon pad type definition
+ */
+typedef enum {
+ HBN_AON_PAD_GPIO9 = 0, /*!< HBN aon pad type: GPIO9 */
+ HBN_AON_PAD_GPIO10 = 1, /*!< HBN aon pad type: GPIO10 */
+ HBN_AON_PAD_GPIO11 = 2, /*!< HBN aon pad type: GPIO11 */
+ HBN_AON_PAD_GPIO12 = 3, /*!< HBN aon pad type: GPIO12 */
+ HBN_AON_PAD_GPIO13 = 4, /*!< HBN aon pad type: GPIO13 */
+ HBN_AON_PAD_GPIO14 = 5, /*!< HBN aon pad type: GPIO14 */
+ HBN_AON_PAD_GPIO15 = 6, /*!< HBN aon pad type: GPIO15 */
+ HBN_AON_PAD_GPIO40 = 7, /*!< HBN aon pad type: GPIO40 */
+ HBN_AON_PAD_GPIO41 = 8, /*!< HBN aon pad type: GPIO41 */
+} HBN_AON_PAD_Type;
+
+/**
+ * @brief HBN acomp interrupt type definition
+ */
+typedef enum {
+ HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */
+ HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */
+} HBN_ACOMP_INT_EDGE_Type;
+
+/**
+ * @brief HBN GPIO pad pu pd type
+ */
+typedef enum {
+ HBN_GPIO_PAD_PULL_NONE = 0, /*!< gpio pad pull none at hbn */
+ HBN_GPIO_PAD_PULL_DOWN = 1, /*!< gpio pad pull down at hbn */
+ HBN_GPIO_PAD_PULL_UP = 2, /*!< gpio pad pull up at hbn */
+ HBN_GPIO_PAD_ACTIVE_IE = 3, /*!< gpio pad active ie at hbn */
+} HBN_GPIO_PAD_PULL_Type;
+
+/**
+ * @brief HBN AON PAD configuration type definition
+ */
+typedef struct
+{
+ uint8_t ctrlEn; /*!< AON GPIO41/40/15~9 Control by AON HW */
+ uint8_t inputEn; /*!< Always on PAD IE/SMT (if corresponding AON GPIO controlled by AON HW) */
+ uint8_t outputEn; /*!< Always on PAD OE (if corresponding AON GPIO controlled by AON HW) */
+ HBN_GPIO_PAD_PULL_Type pullCfg; /*!< Always on PAD PU/PD (if corresponding AON GPIO controlled by AON HW) */
+} HBN_AON_PAD_CFG_Type;
+
+/**
+ * @brief HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+ HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE = 0x0, /*!< HBN GPIO INT trigger type: sync falling edge trigger */
+ HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE = 0x1, /*!< HBN GPIO INT trigger type: sync rising edge trigger */
+ HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL = 0x2, /*!< HBN GPIO INT trigger type: sync low level trigger */
+ HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL = 0x3, /*!< HBN GPIO INT trigger type: sync high level trigger */
+ HBN_GPIO_INT_TRIGGER_SYNC_RISING_FALLING_EDGE = 0x4, /*!< HBN GPIO INT trigger type: sync rising falling edge trigger */
+ HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE = 0x8, /*!< HBN GPIO INT trigger type: async falling edge trigger */
+ HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE = 0x9, /*!< HBN GPIO INT trigger type: async rising edge trigger */
+ HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL = 0xA, /*!< HBN GPIO INT trigger type: async low level trigger */
+ HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL = 0xB, /*!< HBN GPIO INT trigger type: async high level trigger */
+} HBN_GPIO_INT_Trigger_Type;
+
+/**
+ * @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+ HBN_OUT0_INT_GPIO9 = 0, /*!< HBN out 0 interrupt type: GPIO9 */
+ HBN_OUT0_INT_GPIO10 = 1, /*!< HBN out 0 interrupt type: GPIO10 */
+ HBN_OUT0_INT_GPIO11 = 2, /*!< HBN out 0 interrupt type: GPIO11 */
+ HBN_OUT0_INT_GPIO12 = 3, /*!< HBN out 0 interrupt type: GPIO12 */
+ HBN_OUT0_INT_GPIO13 = 4, /*!< HBN out 0 interrupt type: GPIO13 */
+ HBN_OUT0_INT_GPIO14 = 5, /*!< HBN out 0 interrupt type: GPIO14 */
+ HBN_OUT0_INT_GPIO15 = 6, /*!< HBN out 0 interrupt type: GPIO15 */
+ HBN_OUT0_INT_GPIO40 = 7, /*!< HBN out 0 interrupt type: GPIO40 */
+ HBN_OUT0_INT_GPIO41 = 8, /*!< HBN out 0 interrupt type: GPIO41 */
+ HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */
+ HBN_OUT0_INT_MAX, /*!< MAX */
+} HBN_OUT0_INT_Type;
+
+/**
+ * @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+ HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */
+ HBN_OUT1_INT_BOD, /*!< HBN out 1 interrupt type: BOD */
+ HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */
+ HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */
+ HBN_OUT1_INT_MAX, /*!< MAX */
+} HBN_OUT1_INT_Type;
+
+/**
+ * @brief HBN LDO level type definition
+ */
+typedef enum {
+ HBN_LDO_LEVEL_0P70V = 2, /*!< HBN LDO voltage 0.70V */
+ HBN_LDO_LEVEL_0P75V = 3, /*!< HBN LDO voltage 0.75V */
+ HBN_LDO_LEVEL_0P80V = 4, /*!< HBN LDO voltage 0.80V */
+ HBN_LDO_LEVEL_0P85V = 5, /*!< HBN LDO voltage 0.85V */
+ HBN_LDO_LEVEL_0P90V = 6, /*!< HBN LDO voltage 0.90V */
+ HBN_LDO_LEVEL_0P95V = 7, /*!< HBN LDO voltage 0.95V */
+ HBN_LDO_LEVEL_1P00V = 8, /*!< HBN LDO voltage 1.00V */
+ HBN_LDO_LEVEL_1P05V = 9, /*!< HBN LDO voltage 1.05V */
+ HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */
+ HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */
+ HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */
+ HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */
+ HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */
+ HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */
+} HBN_LDO_LEVEL_Type;
+
+/**
+ * @brief HBN level type definition
+ */
+typedef enum {
+ HBN_LEVEL_0, /*!< HBN pd_core */
+ HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */
+} HBN_LEVEL_Type;
+
+/**
+ * @brief HBN RTC misc configuration type definition
+ */
+typedef struct
+{
+ uint32_t rtcRstHoldCnt_rtc : 3; /*!< rtc_rst_hold_cnt_rtc */
+ uint32_t rsvda : 1; /*!< reserved */
+ uint32_t rtcRstEnRtc : 1; /*!< rtc_rst_en_rtc */
+ uint32_t rtcRstInvRtc : 1; /*!< rtc_rst_inv_rtc */
+ uint32_t rtcRstClkSel_rtc : 1; /*!< rtc_rst_clk_sel_rtc */
+ uint32_t rsvdb : 1; /*!< reserved */
+ uint32_t ldo11RtcVoutSelRtc : 4; /*!< ldo11_rtc_vout_sel_rtc */
+ uint32_t rsvdc : 22; /*!< reserved */
+} HBN_RTC_MISC_Type;
+
+/**
+ * @brief HBN BOD configuration type definition
+ */
+typedef struct
+{
+ uint8_t enableBod; /*!< Enable BOD or not */
+ uint8_t enableBodInt; /*!< Enable BOD interrupt or not */
+ uint8_t bodThreshold; /*!< BOD threshold */
+ uint8_t enablePorInBod; /*!< Enable POR when BOD occure or not */
+} HBN_BOD_CFG_Type;
+
+/**
+ * @brief HBN APP configuration type definition
+ */
+typedef struct
+{
+ uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */
+ uint32_t sleepTime; /*!< HBN sleep time */
+ uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */
+ HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
+ spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */
+ HBN_LEVEL_Type hbnLevel; /*!< HBN level */
+ HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
+ uint8_t dcdcPuSeq; /*!< power on dcdc sequence */
+} HBN_APP_CFG_Type;
+
+/*@} end of group HBN_Public_Types */
+
+/** @defgroup HBN_Public_Constants
+ * @{
+ */
+
+/** @defgroup HBN_PIR_LPF_TYPE
+ * @{
+ */
+#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \
+ ((type) == HBN_PIR_LPF_DIV2))
+
+/** @defgroup HBN_PIR_HPF_TYPE
+ * @{
+ */
+#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \
+ ((type) == HBN_PIR_HPF_METHOD1) || \
+ ((type) == HBN_PIR_HPF_METHOD2))
+
+/** @defgroup HBN_FLASH_PAD_PULL_TYPE
+ * @{
+ */
+#define IS_HBN_FLASH_PAD_PULL_TYPE(type) (((type) == HBN_FLASH_PAD_PULL_NONE) || \
+ ((type) == HBN_FLASH_PAD_PULL_UP) || \
+ ((type) == HBN_FLASH_PAD_PULL_DOWN))
+
+/** @defgroup HBN_BOD_THRES_TYPE
+ * @{
+ */
+#define IS_HBN_BOD_THRES_TYPE(type) (((type) == HBN_BOD_THRES_2P05V) || \
+ ((type) == HBN_BOD_THRES_2P10V) || \
+ ((type) == HBN_BOD_THRES_2P15V) || \
+ ((type) == HBN_BOD_THRES_2P20V) || \
+ ((type) == HBN_BOD_THRES_2P25V) || \
+ ((type) == HBN_BOD_THRES_2P30V) || \
+ ((type) == HBN_BOD_THRES_2P35V) || \
+ ((type) == HBN_BOD_THRES_2P40V))
+
+/** @defgroup HBN_BOD_MODE_TYPE
+ * @{
+ */
+#define IS_HBN_BOD_MODE_TYPE(type) (((type) == HBN_BOD_MODE_POR_INDEPENDENT) || \
+ ((type) == HBN_BOD_MODE_POR_RELEVANT))
+
+/** @defgroup HBN_32K_CLK_TYPE
+ * @{
+ */
+#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \
+ ((type) == HBN_32K_XTAL) || \
+ ((type) == HBN_32K_DIG))
+
+/** @defgroup HBN_MCU_XCLK_TYPE
+ * @{
+ */
+#define IS_HBN_MCU_XCLK_TYPE(type) (((type) == HBN_MCU_XCLK_RC32M) || \
+ ((type) == HBN_MCU_XCLK_XTAL))
+
+/** @defgroup HBN_MCU_ROOT_CLK_TYPE
+ * @{
+ */
+#define IS_HBN_MCU_ROOT_CLK_TYPE(type) (((type) == HBN_MCU_ROOT_CLK_XCLK) || \
+ ((type) == HBN_MCU_ROOT_CLK_PLL))
+
+/** @defgroup HBN_UART_CLK_TYPE
+ * @{
+ */
+#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_MCU_PBCLK) || \
+ ((type) == HBN_UART_CLK_160M) || \
+ ((type) == HBN_UART_CLK_XCLK))
+
+/** @defgroup HBN_RTC_INT_DELAY_TYPE
+ * @{
+ */
+#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \
+ ((type) == HBN_RTC_INT_DELAY_0T))
+
+/** @defgroup HBN_INT_TYPE
+ * @{
+ */
+#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) || \
+ ((type) == HBN_INT_GPIO10) || \
+ ((type) == HBN_INT_GPIO11) || \
+ ((type) == HBN_INT_GPIO12) || \
+ ((type) == HBN_INT_GPIO13) || \
+ ((type) == HBN_INT_GPIO14) || \
+ ((type) == HBN_INT_GPIO15) || \
+ ((type) == HBN_INT_GPIO40) || \
+ ((type) == HBN_INT_GPIO41) || \
+ ((type) == HBN_INT_RTC) || \
+ ((type) == HBN_INT_PIR) || \
+ ((type) == HBN_INT_BOD) || \
+ ((type) == HBN_INT_ACOMP0) || \
+ ((type) == HBN_INT_ACOMP1))
+
+/** @defgroup HBN_ACOMP_INT_EDGE_TYPE
+ * @{
+ */
+#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \
+ ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE))
+
+/** @defgroup HBN_AON_PAD_TYPE
+ * @{
+ */
+#define IS_HBN_AON_PAD_TYPE(type) (((type) == HBN_AON_PAD_GPIO9) || \
+ ((type) == HBN_AON_PAD_GPIO10) || \
+ ((type) == HBN_AON_PAD_GPIO11) || \
+ ((type) == HBN_AON_PAD_GPIO12) || \
+ ((type) == HBN_AON_PAD_GPIO13) || \
+ ((type) == HBN_AON_PAD_GPIO14) || \
+ ((type) == HBN_AON_PAD_GPIO15) || \
+ ((type) == HBN_AON_PAD_GPIO40) || \
+ ((type) == HBN_AON_PAD_GPIO41))
+
+/** @defgroup HBN_GPIO_PAD_PULL_TYPE
+ * @{
+ */
+#define IS_HBN_GPIO_PAD_PULL_TYPE(type) (((type) == HBN_GPIO_PAD_PULL_NONE) || \
+ ((type) == HBN_GPIO_PAD_PULL_DOWN) || \
+ ((type) == HBN_GPIO_PAD_PULL_UP) || \
+ ((type) == HBN_GPIO_PAD_ACTIVE_IE))
+
+/** @defgroup HBN_GPIO_INT_TRIGGER_TYPE
+ * @{
+ */
+#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_FALLING_EDGE) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \
+ ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/** @defgroup HBN_OUT0_INT_TYPE
+ * @{
+ */
+#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) || \
+ ((type) == HBN_OUT0_INT_GPIO10) || \
+ ((type) == HBN_OUT0_INT_GPIO11) || \
+ ((type) == HBN_OUT0_INT_GPIO12) || \
+ ((type) == HBN_OUT0_INT_GPIO13) || \
+ ((type) == HBN_OUT0_INT_GPIO14) || \
+ ((type) == HBN_OUT0_INT_GPIO15) || \
+ ((type) == HBN_OUT0_INT_GPIO40) || \
+ ((type) == HBN_OUT0_INT_GPIO41) || \
+ ((type) == HBN_OUT0_INT_RTC) || \
+ ((type) == HBN_OUT0_INT_MAX))
+
+/** @defgroup HBN_OUT1_INT_TYPE
+ * @{
+ */
+#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \
+ ((type) == HBN_OUT1_INT_BOD) || \
+ ((type) == HBN_OUT1_INT_ACOMP0) || \
+ ((type) == HBN_OUT1_INT_ACOMP1) || \
+ ((type) == HBN_OUT1_INT_MAX))
+
+/** @defgroup HBN_LDO_LEVEL_TYPE
+ * @{
+ */
+#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P70V) || \
+ ((type) == HBN_LDO_LEVEL_0P75V) || \
+ ((type) == HBN_LDO_LEVEL_0P80V) || \
+ ((type) == HBN_LDO_LEVEL_0P85V) || \
+ ((type) == HBN_LDO_LEVEL_0P90V) || \
+ ((type) == HBN_LDO_LEVEL_0P95V) || \
+ ((type) == HBN_LDO_LEVEL_1P00V) || \
+ ((type) == HBN_LDO_LEVEL_1P05V) || \
+ ((type) == HBN_LDO_LEVEL_1P10V) || \
+ ((type) == HBN_LDO_LEVEL_1P15V) || \
+ ((type) == HBN_LDO_LEVEL_1P20V) || \
+ ((type) == HBN_LDO_LEVEL_1P25V) || \
+ ((type) == HBN_LDO_LEVEL_1P30V) || \
+ ((type) == HBN_LDO_LEVEL_1P35V))
+
+/** @defgroup HBN_LEVEL_TYPE
+ * @{
+ */
+#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \
+ ((type) == HBN_LEVEL_1))
+
+/*@} end of group HBN_Public_Constants */
+
+/** @defgroup HBN_Public_Macros
+ * @{
+ */
+#define HBN_RAM_SIZE (4 * 1024)
+#define HBN_RTC_COMP_BIT0_39 0x01
+#define HBN_RTC_COMP_BIT0_23 0x02
+#define HBN_RTC_COMP_BIT13_39 0x04
+#define HBN_STATUS_ENTER_FLAG 0x4e424845
+#define HBN_STATUS_WAKEUP_FLAG 0x4e424857
+#define HBN_RELEASE_CORE_FLAG (0x48)
+#define HBN_REPOWER_LDO18FLASH_FLAG (0x52)
+#define HBN_XTAL_FLAG_MASK 0x0000ff00
+#define HBN_XTAL_FLAG_VALUE 0x5800
+
+/* 0x108 : HBN_RSV2 */
+#define HBN_REPOWER_LDO18FLASH_DLY HBN_REPOWER_LDO18FLASH_DLY
+#define HBN_REPOWER_LDO18FLASH_DLY_POS (0U)
+#define HBN_REPOWER_LDO18FLASH_DLY_LEN (8U)
+#define HBN_REPOWER_LDO18FLASH_DLY_MSK (((1U << HBN_REPOWER_LDO18FLASH_DLY_LEN) - 1) << HBN_REPOWER_LDO18FLASH_DLY_POS)
+#define HBN_REPOWER_LDO18FLASH_DLY_UMSK (~(((1U << HBN_REPOWER_LDO18FLASH_DLY_LEN) - 1) << HBN_REPOWER_LDO18FLASH_DLY_POS))
+#define HBN_REPOWER_LDO18FLASH HBN_REPOWER_LDO18FLASH
+#define HBN_REPOWER_LDO18FLASH_POS (8U)
+#define HBN_REPOWER_LDO18FLASH_LEN (8U)
+#define HBN_REPOWER_LDO18FLASH_MSK (((1U << HBN_REPOWER_LDO18FLASH_LEN) - 1) << HBN_REPOWER_LDO18FLASH_POS)
+#define HBN_REPOWER_LDO18FLASH_UMSK (~(((1U << HBN_REPOWER_LDO18FLASH_LEN) - 1) << HBN_REPOWER_LDO18FLASH_POS))
+#define HBN_CORE_UNHALT HBN_CORE_UNHALT
+#define HBN_CORE_UNHALT_POS (16U)
+#define HBN_CORE_UNHALT_LEN (5U)
+#define HBN_CORE_UNHALT_MSK (((1U << HBN_CORE_UNHALT_LEN) - 1) << HBN_CORE_UNHALT_POS)
+#define HBN_CORE_UNHALT_UMSK (~(((1U << HBN_CORE_UNHALT_LEN) - 1) << HBN_CORE_UNHALT_POS))
+#define HBN_POWER_ON_MM HBN_POWER_ON_MM
+#define HBN_POWER_ON_MM_POS (21U)
+#define HBN_POWER_ON_MM_LEN (1U)
+#define HBN_POWER_ON_MM_MSK (((1U << HBN_POWER_ON_MM_LEN) - 1) << HBN_POWER_ON_MM_POS)
+#define HBN_POWER_ON_MM_UMSK (~(((1U << HBN_POWER_ON_MM_LEN) - 1) << HBN_POWER_ON_MM_POS))
+#define HBN_HAND_OFF_SEL HBN_HAND_OFF_SEL
+#define HBN_HAND_OFF_SEL_POS (22U)
+#define HBN_HAND_OFF_SEL_LEN (2U)
+#define HBN_HAND_OFF_SEL_MSK (((1U << HBN_HAND_OFF_SEL_LEN) - 1) << HBN_HAND_OFF_SEL_POS)
+#define HBN_HAND_OFF_SEL_UMSK (~(((1U << HBN_HAND_OFF_SEL_LEN) - 1) << HBN_HAND_OFF_SEL_POS))
+#define HBN_RELEASE_CORE HBN_RELEASE_CORE
+#define HBN_RELEASE_CORE_POS (24U)
+#define HBN_RELEASE_CORE_LEN (8U)
+#define HBN_RELEASE_CORE_MSK (((1U << HBN_RELEASE_CORE_LEN) - 1) << HBN_RELEASE_CORE_POS)
+#define HBN_RELEASE_CORE_UMSK (~(((1U << HBN_RELEASE_CORE_LEN) - 1) << HBN_RELEASE_CORE_POS))
+
+/*@} end of group HBN_Public_Macros */
+
+/** @defgroup HBN_Public_Functions
+ * @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void);
+void HBN_OUT1_IRQHandler(void);
+#endif
+/*----------*/
+void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
+void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg);
+void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq);
+BL_Err_Type HBN_Reset(void);
+/*----------*/
+BL_Err_Type HBN_PIR_Enable(void);
+BL_Err_Type HBN_PIR_Disable(void);
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg);
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf);
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf);
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold);
+uint16_t HBN_Get_PIR_Threshold(void);
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval);
+uint16_t HBN_Get_PIR_Interval(void);
+/*----------*/
+BL_Sts_Type HBN_Get_BOD_OUT_State(void);
+BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode);
+/*----------*/
+BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+/*----------*/
+BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
+HBN_MCU_XCLK_Type HBN_Get_MCU_XCLK_Sel(void);
+BL_Err_Type HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_Type xclk);
+HBN_MCU_ROOT_CLK_Type HBN_Get_MCU_Root_CLK_Sel(void);
+BL_Err_Type HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_Type rootClk);
+/*----------*/
+BL_Err_Type HBN_Set_HRAM_slp(void);
+BL_Err_Type HBN_Set_HRAM_Ret(void);
+
+/*----------*/
+uint32_t HBN_Get_Status_Flag(void);
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag);
+uint32_t HBN_Get_Wakeup_Addr(void);
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr);
+/*----------*/
+uint8_t HBN_Get_Core_Unhalt_Config(void);
+BL_Err_Type HBN_Set_Core_Reboot_Config(uint8_t core, uint8_t hcfg);
+uint8_t HBN_Get_MM_Power_Config(void);
+BL_Err_Type HBN_Set_MM_Power_Config(uint8_t pcfg);
+uint8_t HBN_Get_Hand_Off_Config(void);
+BL_Err_Type HBN_Set_Hand_Off_Config(uint8_t dcfg);
+uint16_t HBN_Get_Ldo18flash_Repower_Config(void);
+BL_Err_Type HBN_Set_Ldo18flash_Repower_Delay(uint8_t delay);
+/*----------*/
+BL_Err_Type HBN_Set_Xtal_Type(uint8_t xtalType);
+BL_Err_Type HBN_Get_Xtal_Type(uint8_t *xtalType);
+BL_Err_Type HBN_Get_Xtal_Value(uint32_t *xtalVal);
+/*----------*/
+BL_Err_Type HBN_Clear_RTC_Counter(void);
+BL_Err_Type HBN_Enable_RTC_Counter(void);
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode);
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh);
+BL_Err_Type HBN_Clear_RTC_IRQ(void);
+/*----------*/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType);
+BL_Err_Type HBN_GPIO_INT_Disable(void);
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType);
+uint8_t HBN_Get_Pin_Wakeup_Mode(void);
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType);
+BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable);
+BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal);
+BL_Err_Type HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2);
+BL_Err_Type HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg);
+BL_Err_Type HBN_Set_IO4041_As_Xtal_32K_IO(uint8_t xtal32kIoEn);
+/*----------*/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+/*----------*/
+BL_Err_Type HBN_Enable_BOD_IRQ(void);
+BL_Err_Type HBN_Disable_BOD_IRQ(void);
+/*----------*/
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec);
+/*----------*/
+BL_Err_Type HBN_Power_On_Xtal_32K(void);
+BL_Err_Type HBN_Power_Off_Xtal_32K(void);
+BL_Err_Type HBN_Power_On_RC32K(void);
+BL_Err_Type HBN_Power_Off_RC32K(void);
+BL_Err_Type HBN_Trim_RC32K(void);
+/*----------*/
+BL_Err_Type HBN_PD_RC32K_All_State(void);
+BL_Err_Type HBN_PD_RC32K_In_Poff(void);
+/*----------*/
+BL_Err_Type HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg);
+BL_Err_Type HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg);
+/*----------*/
+BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg);
+BL_Err_Type HBN_Clear_RTC_INT(void);
+/*----------*/
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_HBN_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ipc.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ipc.h
new file mode 100644
index 00000000..dde28e30
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_ipc.h
@@ -0,0 +1,241 @@
+/**
+ ******************************************************************************
+ * @file bl606p_ipc.h
+ * @version V1.2
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2018 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_IPC_H__
+#define __BL808_IPC_H__
+
+#include "ipc_reg.h"
+#include "bl808_common.h"
+#include "bl808_glb.h"
+
+/** @addtogroup BL606P_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup IPC
+ * @{
+ */
+
+/** @defgroup IPC_Public_Types
+ * @{
+ */
+typedef void(ipcIntCallback)(uint32_t src);
+/**
+ * @brief IPC interrupt source type definition
+ */
+typedef enum {
+ IPC_INT_SRC_BIT0 = 0, /*!< IPC interrupt source bit 0 */
+ IPC_INT_SRC_BIT1, /*!< IPC interrupt source bit 1 */
+ IPC_INT_SRC_BIT2, /*!< IPC interrupt source bit 2 */
+ IPC_INT_SRC_BIT3, /*!< IPC interrupt source bit 3 */
+ IPC_INT_SRC_BIT4, /*!< IPC interrupt source bit 4 */
+ IPC_INT_SRC_BIT5, /*!< IPC interrupt source bit 5 */
+ IPC_INT_SRC_BIT6, /*!< IPC interrupt source bit 6 */
+ IPC_INT_SRC_BIT7, /*!< IPC interrupt source bit 7 */
+ IPC_INT_SRC_BIT8, /*!< IPC interrupt source bit 8 */
+ IPC_INT_SRC_BIT9, /*!< IPC interrupt source bit 9 */
+ IPC_INT_SRC_BIT10, /*!< IPC interrupt source bit 10 */
+ IPC_INT_SRC_BIT11, /*!< IPC interrupt source bit 11 */
+ IPC_INT_SRC_BIT12, /*!< IPC interrupt source bit 12 */
+ IPC_INT_SRC_BIT13, /*!< IPC interrupt source bit 13 */
+ IPC_INT_SRC_BIT14, /*!< IPC interrupt source bit 14 */
+ IPC_INT_SRC_BIT15, /*!< IPC interrupt source bit 15 */
+ IPC_INT_SRC_BIT16, /*!< IPC interrupt source bit 16 */
+ IPC_INT_SRC_BIT17, /*!< IPC interrupt source bit 17 */
+ IPC_INT_SRC_BIT18, /*!< IPC interrupt source bit 18 */
+ IPC_INT_SRC_BIT19, /*!< IPC interrupt source bit 19 */
+ IPC_INT_SRC_BIT20, /*!< IPC interrupt source bit 20 */
+ IPC_INT_SRC_BIT21, /*!< IPC interrupt source bit 21 */
+ IPC_INT_SRC_BIT22, /*!< IPC interrupt source bit 22 */
+ IPC_INT_SRC_BIT23, /*!< IPC interrupt source bit 23 */
+ IPC_INT_SRC_BIT24, /*!< IPC interrupt source bit 24 */
+ IPC_INT_SRC_BIT25, /*!< IPC interrupt source bit 25 */
+ IPC_INT_SRC_BIT26, /*!< IPC interrupt source bit 26 */
+ IPC_INT_SRC_BIT27, /*!< IPC interrupt source bit 27 */
+ IPC_INT_SRC_BIT28, /*!< IPC interrupt source bit 28 */
+ IPC_INT_SRC_BIT29, /*!< IPC interrupt source bit 29 */
+ IPC_INT_SRC_BIT30, /*!< IPC interrupt source bit 30 */
+ IPC_INT_SRC_BIT31, /*!< IPC interrupt source bit 31 */
+ IPC_INT_SRC_MAX, /*!< */
+} IPC_Int_Src_Type;
+
+/**
+ * @brief IPC interrupt source type definition
+ */
+typedef enum {
+ IPC_GRP_INT_SRC_BIT0 = 0, /*!< IPC interrupt source bit 0 */
+ IPC_GRP_INT_SRC_BIT1, /*!< IPC interrupt source bit 1 */
+ IPC_GRP_INT_SRC_BIT2, /*!< IPC interrupt source bit 2 */
+ IPC_GRP_INT_SRC_BIT3, /*!< IPC interrupt source bit 3 */
+ IPC_GRP_INT_SRC_BIT4, /*!< IPC interrupt source bit 4 */
+ IPC_GRP_INT_SRC_BIT5, /*!< IPC interrupt source bit 5 */
+ IPC_GRP_INT_SRC_BIT6, /*!< IPC interrupt source bit 6 */
+ IPC_GRP_INT_SRC_BIT7, /*!< IPC interrupt source bit 7 */
+ IPC_GRP_INT_SRC_BIT8, /*!< IPC interrupt source bit 8 */
+ IPC_GRP_INT_SRC_BIT9, /*!< IPC interrupt source bit 9 */
+ IPC_GRP_INT_SRC_BIT10, /*!< IPC interrupt source bit 10 */
+ IPC_GRP_INT_SRC_BIT11, /*!< IPC interrupt source bit 11 */
+ IPC_GRP_INT_SRC_BIT12, /*!< IPC interrupt source bit 12 */
+ IPC_GRP_INT_SRC_BIT13, /*!< IPC interrupt source bit 13 */
+ IPC_GRP_INT_SRC_BIT14, /*!< IPC interrupt source bit 14 */
+ IPC_GRP_INT_SRC_BIT15, /*!< IPC interrupt source bit 15 */
+ IPC_GRP_INT_SRC_MAX, /*!< */
+} IPC_Grp_Int_Src_Type;
+
+/*@} end of group IPC_Public_Types */
+
+/** @defgroup IPC_Public_Constants
+ * @{
+ */
+
+/** @defgroup IPC_INT_GRP_TYPE
+ * @{
+ */
+#define IS_IPC_GRP_INT_TYPE(type) (((type) == IPC_GRP_INT_SRC_BIT0) || \
+ ((type) == IPC_GRP_INT_SRC_BIT1) || \
+ ((type) == IPC_GRP_INT_SRC_BIT2) || \
+ ((type) == IPC_GRP_INT_SRC_BIT3) || \
+ ((type) == IPC_GRP_INT_SRC_BIT4) || \
+ ((type) == IPC_GRP_INT_SRC_BIT5) || \
+ ((type) == IPC_GRP_INT_SRC_BIT6) || \
+ ((type) == IPC_GRP_INT_SRC_BIT7) || \
+ ((type) == IPC_GRP_INT_SRC_BIT8) || \
+ ((type) == IPC_GRP_INT_SRC_BIT9) || \
+ ((type) == IPC_GRP_INT_SRC_BIT10) || \
+ ((type) == IPC_GRP_INT_SRC_BIT11) || \
+ ((type) == IPC_GRP_INT_SRC_BIT12) || \
+ ((type) == IPC_GRP_INT_SRC_BIT13) || \
+ ((type) == IPC_GRP_INT_SRC_BIT14) || \
+ ((type) == IPC_GRP_INT_SRC_BIT15))
+
+/** @defgroup IPC_INT_SRC_TYPE
+ * @{
+ */
+#define IS_IPC_INT_SRC_TYPE(type) (((type) == IPC_INT_SRC_BIT0) || \
+ ((type) == IPC_INT_SRC_BIT1) || \
+ ((type) == IPC_INT_SRC_BIT2) || \
+ ((type) == IPC_INT_SRC_BIT3) || \
+ ((type) == IPC_INT_SRC_BIT4) || \
+ ((type) == IPC_INT_SRC_BIT5) || \
+ ((type) == IPC_INT_SRC_BIT6) || \
+ ((type) == IPC_INT_SRC_BIT7) || \
+ ((type) == IPC_INT_SRC_BIT8) || \
+ ((type) == IPC_INT_SRC_BIT9) || \
+ ((type) == IPC_INT_SRC_BIT10) || \
+ ((type) == IPC_INT_SRC_BIT11) || \
+ ((type) == IPC_INT_SRC_BIT12) || \
+ ((type) == IPC_INT_SRC_BIT13) || \
+ ((type) == IPC_INT_SRC_BIT14) || \
+ ((type) == IPC_INT_SRC_BIT15) || \
+ ((type) == IPC_INT_SRC_BIT16) || \
+ ((type) == IPC_INT_SRC_BIT17) || \
+ ((type) == IPC_INT_SRC_BIT18) || \
+ ((type) == IPC_INT_SRC_BIT19) || \
+ ((type) == IPC_INT_SRC_BIT20) || \
+ ((type) == IPC_INT_SRC_BIT21) || \
+ ((type) == IPC_INT_SRC_BIT22) || \
+ ((type) == IPC_INT_SRC_BIT23) || \
+ ((type) == IPC_INT_SRC_BIT24) || \
+ ((type) == IPC_INT_SRC_BIT25) || \
+ ((type) == IPC_INT_SRC_BIT26) || \
+ ((type) == IPC_INT_SRC_BIT27) || \
+ ((type) == IPC_INT_SRC_BIT28) || \
+ ((type) == IPC_INT_SRC_BIT29) || \
+ ((type) == IPC_INT_SRC_BIT30) || \
+ ((type) == IPC_INT_SRC_BIT31))
+
+/*@} end of group IPC_Public_Constants */
+
+/** @defgroup IPC_Public_Macros
+ * @{
+ */
+
+/*@} end of group IPC_Public_Macros */
+
+/** @defgroup IPC_Public_Functions
+ * @{
+ */
+void IPC_M0_Init(ipcIntCallback *onLPTriggerCallBack,
+ ipcIntCallback *onD0TriggerCallBack);
+void IPC_M0_Int_Unmask(IPC_Int_Src_Type src);
+void IPC_M0_Int_Unmask_By_Word(uint32_t src);
+uint32_t IPC_M0_Get_Int_Raw_Status(void);
+void IPC_M0_Clear_Int(IPC_Int_Src_Type src);
+void IPC_M0_Clear_Int_By_Word(uint32_t src);
+void IPC_LP_Trigger_M0(IPC_Grp_Int_Src_Type src);
+void IPC_D0_Trigger_M0(IPC_Grp_Int_Src_Type src);
+void IPC_M0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src);
+
+void IPC_LP_Init(ipcIntCallback *onM0TriggerCallBack,
+ ipcIntCallback *onD0TriggerCallBack);
+void IPC_LP_Int_Unmask(IPC_Int_Src_Type src);
+void IPC_LP_Int_Unmask_By_Word(uint32_t src);
+uint32_t IPC_LP_Get_Int_Raw_Status(void);
+void IPC_LP_Clear_Int(IPC_Int_Src_Type src);
+void IPC_LP_Clear_Int_By_Word(uint32_t src);
+void IPC_M0_Trigger_LP(IPC_Grp_Int_Src_Type src);
+void IPC_D0_Trigger_LP(IPC_Grp_Int_Src_Type src);
+void IPC_LP_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src);
+
+void IPC_D0_Init(ipcIntCallback *onM0TriggerCallBack,
+ ipcIntCallback *onLPTriggerCallBack);
+void IPC_D0_Int_Unmask(IPC_Int_Src_Type src);
+void IPC_D0_Int_Unmask_By_Word(uint32_t src);
+uint32_t IPC_D0_Get_Int_Raw_Status(void);
+void IPC_D0_Clear_Int(IPC_Int_Src_Type src);
+void IPC_D0_Clear_Int_By_Word(uint32_t src);
+void IPC_M0_Trigger_D0(IPC_Grp_Int_Src_Type src);
+void IPC_LP_Trigger_D0(IPC_Grp_Int_Src_Type src);
+void IPC_D0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src);
+
+void IPC_Trigger_Target_CPU(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src);
+
+#ifndef BFLB_USE_HAL_DRIVER
+void IPC_M0_IRQHandler(void);
+#endif
+#ifndef BFLB_USE_HAL_DRIVER
+void IPC_LP_IRQHandler(void);
+#endif
+#ifndef BFLB_USE_HAL_DRIVER
+void IPC_D0_IRQHandler(void);
+#endif
+
+/*@} end of group IPC_Public_Functions */
+
+/*@} end of group IPC */
+
+/*@} end of group BL606P_Peripheral_Driver */
+
+#endif /* __BL606P_IPC_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_l1c.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_l1c.h
new file mode 100644
index 00000000..3d796c1d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_l1c.h
@@ -0,0 +1,118 @@
+/**
+ ******************************************************************************
+ * @file bl808_l1c.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_L1C_H__
+#define __BL808_L1C_H__
+
+#include "pds_reg.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup L1C
+ * @{
+ */
+
+/** @defgroup L1C_Public_Types
+ * @{
+ */
+
+/**
+ * @brief L1C configuration structure type definition
+ */
+typedef struct
+{
+ uint8_t cacheEn;
+ uint8_t wayDis;
+ uint8_t wa;
+ uint8_t wb;
+ uint8_t wt;
+ uint8_t rsvd[3];
+ uint32_t cacheRangeL;
+ uint32_t cacheRangeH;
+} L1C_CACHE_Cfg_Type;
+
+/*@} end of group L1C_Public_Types */
+
+/** @defgroup L1C_Public_Constants
+ * @{
+ */
+
+/*@} end of group L1C_Public_Constants */
+
+/** @defgroup L1C_Public_Macros
+ * @{
+ */
+#define L1C_WAY_DISABLE_NONE 0x00
+#define L1C_WAY_DISABLE_ONE 0x01
+#define L1C_WAY_DISABLE_TWO 0x03
+#define L1C_WAY_DISABLE_ALL 0x03
+#define L1C_WAY_DISABLE_NOT_CAHNGE 0xFF
+
+/*@} end of group L1C_Public_Macros */
+
+/** @defgroup L1C_Public_Functions
+ * @{
+ */
+
+/*----------*/
+BL_Err_Type L1C_ICache_Enable(uint8_t wayDsiable);
+BL_Err_Type L1C_DCache_Enable(uint8_t wayDsiable);
+BL_Err_Type L1C_ICache_Disable(void);
+BL_Err_Type L1C_DCache_Disable(void);
+void L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn);
+BL_Err_Type L1C_DCache_Clean_All(void);
+BL_Err_Type L1C_DCache_Clean_Invalid_All(void);
+BL_Err_Type L1C_ICache_Invalid_All(void);
+BL_Err_Type L1C_DCache_Invalid_All(void);
+BL_Err_Type L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len);
+BL_Err_Type L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len);
+BL_Err_Type L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len);
+BL_Err_Type L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len);
+/*----------*/
+BL_Err_Type L1C_Set_Wrap(uint8_t en);
+BL_Err_Type L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting);
+/*----------*/
+int L1C_Is_DCache_Range(uintptr_t addr);
+int L1C_Get_None_Cache_Addr(uintptr_t addr);
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_L1C_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_pds.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_pds.h
new file mode 100644
index 00000000..6dd9acc9
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_pds.h
@@ -0,0 +1,518 @@
+/**
+ ******************************************************************************
+ * @file bl808_pds.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_PDS_H__
+#define __BL808_PDS_H__
+
+#include "pds_reg.h"
+#include "glb_reg.h"
+#include "bl808_clock.h"
+#include "bl808_aon.h"
+#include "bl808_hbn.h"
+#include "bl808_common.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_ctrl.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup PDS
+ * @{
+ */
+
+/** @defgroup PDS_Public_Types
+ * @{
+ */
+
+/**
+ * @brief PDS GPIO int set type
+ */
+typedef enum {
+ PDS_GPIO_INT_SET_1_GPIO0_GPIO7, /*!< gpio int set 1, gpio0 - gpio7 */
+ PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22, /*!< gpio int set 2, gpio8, gpio16 - gpio22 */
+ PDS_GPIO_INT_SET_3_GPIO23_GPIO30, /*!< gpio int set 3, gpio23 - gpio30 */
+ PDS_GPIO_INT_SET_4_GPIO31_GPIO38, /*!< gpio int set 4, gpio31 - gpio38 */
+} PDS_GPIO_INT_SET_Type;
+
+/**
+ * @brief PDS GPIO interrupt control mode type definition
+ */
+typedef enum {
+ PDS_GPIO_INT_SYNC_FALLING_EDGE = 0, /*!< GPIO interrupt sync mode, GPIO negedge pulse trigger interrupt */
+ PDS_GPIO_INT_SYNC_RISING_EDGE = 1, /*!< GPIO interrupt sync mode, GPIO posedge pulse trigger interrupt */
+ PDS_GPIO_INT_SYNC_LOW_LEVEL = 2, /*!< GPIO interrupt sync mode, GPIO negedge level trigger interrupt */
+ PDS_GPIO_INT_SYNC_HIGH_LEVEL = 3, /*!< GPIO interrupt sync mode, GPIO posedge level trigger interrupt */
+ PDS_GPIO_INT_SYNC_RISING_FALLING_EDGE = 4, /*!< GPIO interrupt sync mode, GPIO posedge negedge pulse trigger interrupt */
+ PDS_GPIO_INT_ASYNC_FALLING_EDGE = 8, /*!< GPIO interrupt async mode, GPIO negedge pulse trigger interrupt */
+ PDS_GPIO_INT_ASYNC_RISING_EDGE = 9, /*!< GPIO interrupt async mode, GPIO posedge pulse trigger interrupt */
+ PDS_GPIO_INT_ASYNC_LOW_LEVEL = 10, /*!< GPIO interrupt async mode, GPIO negedge level trigger interrupt */
+ PDS_GPIO_INT_ASYNC_HIGH_LEVEL = 11, /*!< GPIO interrupt async mode, GPIO posedge level trigger interrupt */
+} PDS_GPIO_INT_TRIG_Type;
+
+/**
+ * @brief PDS lp system clock type definition
+ */
+typedef enum {
+ PDS_LP_SYS_CLK_BCLK_DIV, /*!< use bclk div as system clock frequency */
+} PDS_LP_SYS_CLK_Type;
+
+/**
+ * @brief PDS LDO level type definition
+ */
+typedef enum {
+ PDS_LDO_LEVEL_0P70V = 2, /*!< PDS LDO voltage 0.70V */
+ PDS_LDO_LEVEL_0P75V = 3, /*!< PDS LDO voltage 0.75V */
+ PDS_LDO_LEVEL_0P80V = 4, /*!< PDS LDO voltage 0.80V */
+ PDS_LDO_LEVEL_0P85V = 5, /*!< PDS LDO voltage 0.85V */
+ PDS_LDO_LEVEL_0P90V = 6, /*!< PDS LDO voltage 0.90V */
+ PDS_LDO_LEVEL_0P95V = 7, /*!< PDS LDO voltage 0.95V */
+ PDS_LDO_LEVEL_1P00V = 8, /*!< PDS LDO voltage 1.00V */
+ PDS_LDO_LEVEL_1P05V = 9, /*!< PDS LDO voltage 1.05V */
+ PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */
+ PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */
+ PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */
+ PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */
+ PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */
+ PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */
+} PDS_LDO_LEVEL_Type;
+
+/**
+ * @brief PDS configuration type definition
+ */
+typedef struct
+{
+ uint32_t pdsStart : 1; /*!< [0]PDS Start */
+ uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */
+ uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */
+ uint32_t saveWiFiState : 1; /*!< [3]Save WIFI State Before Enter PDS */
+ uint32_t dcdc11Off : 1; /*!< [4]power down dcdc11 during PDS */
+ uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */
+ uint32_t ctrlGpioIePuPd : 1; /*!< [6]PDS control */
+ uint32_t dcdc18Off : 1; /*!< [7]power down dcdc18 during PDS */
+ uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
+ uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
+ uint32_t glbRstProtect : 1; /*!< [10]avoid glb_reg reset by any reset */
+ uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
+ uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
+ uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
+ uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */
+ uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */
+ uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */
+ uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
+ uint32_t pdsDcdc11VselEn : 1; /*!< [18]PDS "SLEEP" control DCDC11 voltage enable */
+ uint32_t usbpllOff : 1; /*!< [19]PDS Control USB PLL off When pds_pwr_off */
+ uint32_t aupllOff : 1; /*!< [20]PDS control aupll power off */
+ uint32_t cpupllOff : 1; /*!< [21]PDS control cpupll power off */
+ uint32_t wifipllOff : 1; /*!< [22]PDS control wifipll power off */
+ uint32_t pdsDcdc11Vsel : 5; /*!< [27:23]DCDC11 voltage selection in PDS mode */
+ uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */
+ uint32_t pdsUseTbttSlp : 1; /*!< [30]PDS Auto Sleep When wifi_tbtt_sleep_irq detect to 1 */
+ uint32_t pdsGpioIsoMod : 1; /*!< [31]HW Keep GPIO at PDS Mode */
+} PDS_CTL_Type;
+
+/**
+ * @brief PDS force configuration type definition
+ */
+typedef struct
+{
+ uint32_t rsv0 : 1; /*!< [0] */
+ uint32_t mcuRst : 1; /*!< [1] */
+ uint32_t mcuMemStby : 1; /*!< [2] */
+ uint32_t mcuGateClk : 1; /*!< [3] */
+ uint32_t rsv4_7 : 4; /*!< [7:4]reserve */
+ uint32_t dspPwrOff : 1; /*!< [8] */
+ uint32_t dspRst : 1; /*!< [9] */
+ uint32_t dspMemStby : 1; /*!< [10] */
+ uint32_t dspGateClk : 1; /*!< [11] */
+ uint32_t rsv12 : 1; /*!< [12] */
+ uint32_t WbRst : 1; /*!< [13] */
+ uint32_t WbMemStby : 1; /*!< [14] */
+ uint32_t WbGateClk : 1; /*!< [15] */
+ uint32_t rsv16_19 : 4; /*!< [19:16]reserve */
+ uint32_t usbPwrOff : 1; /*!< [20] */
+ uint32_t usbRst : 1; /*!< [21] */
+ uint32_t usbMemStby : 1; /*!< [22] */
+ uint32_t usbGateClk : 1; /*!< [23] */
+ uint32_t MiscPwrOff : 1; /*!< [24] */
+ uint32_t MiscRst : 1; /*!< [25] */
+ uint32_t MiscMemStby : 1; /*!< [26] */
+ uint32_t MiscGateClk : 1; /*!< [27] */
+ uint32_t rsv28_31 : 4; /*!< [31:28]reserve */
+} PDS_CTL4_Type;
+
+/**
+ * @brief PDS interrupt type definition
+ */
+typedef enum {
+ PDS_INT_WAKEUP = 0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */
+ PDS_INT_RF_DONE = 1, /*!< PDS RF done interrupt */
+ PDS_INT_WIFI_TBTT_SLEEP = 2, /*!< PDS wifi tbtt sleep interrupt */
+ PDS_INT_WIFI_TBTT_WAKEUP = 3, /*!< PDS wifi tbtt wakeup interrupt */
+ PDS_INT_MAX = 4, /*!< PDS int max number */
+} PDS_INT_Type;
+
+/**
+ * @brief PDS force configuration type definition
+ */
+typedef struct
+{
+ uint32_t rsv0 : 1; /*!< [0]manual force NP power off */
+ uint32_t forceDspPwrOff : 1; /*!< [1]manual force MM power off */
+ uint32_t rsv2 : 1; /*!< [2]manual force WB power off */
+ uint32_t forceUsbPwrOff : 1; /*!< [3]manual force USB power off */
+ uint32_t rsv4 : 1; /*!< [4]manual force NP isolation */
+ uint32_t forceDspIso : 1; /*!< [5]manual force MM isolation */
+ uint32_t rsv6 : 1; /*!< [6]manual force WB isolation */
+ uint32_t forceUsbIso : 1; /*!< [7]manual force USB isolation */
+ uint32_t forceMcuPdsRst : 1; /*!< [8]manual force NP pds reset */
+ uint32_t forceDspPdsRst : 1; /*!< [9]manual force MM pds reset */
+ uint32_t forceWbPdsRst : 1; /*!< [10]manual force WB pds reset */
+ uint32_t forceUsbPdsRst : 1; /*!< [11]manual force USB pds reset */
+ uint32_t forceMcuMemStby : 1; /*!< [12]manual force NP memory sleep */
+ uint32_t forceDspMemStby : 1; /*!< [13]manual force MM memory sleep */
+ uint32_t forceWbMemStby : 1; /*!< [14]manual force WB memory sleep */
+ uint32_t forceUsbMemStby : 1; /*!< [15]manual force USB memory sleep */
+ uint32_t forceMcuGateClk : 1; /*!< [16]manual force NP clock gated */
+ uint32_t forceDspGateClk : 1; /*!< [17]manual force MM clock gated */
+ uint32_t forceWbGateClk : 1; /*!< [18]manual force WB clock gated */
+ uint32_t forceUsbGateClk : 1; /*!< [19]manual force USB clock gated */
+ uint32_t rsv20_31 : 12; /*!< [31:20]reserve */
+} PDS_CTL2_Type;
+
+/**
+ * @brief PDS force configuration type definition
+ */
+typedef struct
+{
+ uint32_t rsv0 : 1; /*!< [0]reserve */
+ uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */
+ uint32_t rsv2_3 : 2; /*!< [3:2]reserve */
+ uint32_t forceMiscIsoEn : 1; /*!< [4]manual force MISC iso_en */
+ uint32_t rsv5_6 : 2; /*!< [6:5]reserve */
+ uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */
+ uint32_t rsv8_9 : 2; /*!< [9:8]reserve */
+ uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */
+ uint32_t rsv11_12 : 2; /*!< [12:11]reserve */
+ uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */
+ uint32_t rsv14_25 : 12; /*!< [25:14]reserve */
+ uint32_t DspIsoEn : 1; /*!< [26]make MM isolated at PDS Sleep state */
+ uint32_t rsv27_28 : 2; /*!< [28:27]reserve */
+ uint32_t UsbIsoEn : 1; /*!< [29]make USB isolated at PDS Sleep state */
+ uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */
+ uint32_t rsv31 : 1; /*!< [31]reserve */
+} PDS_CTL3_Type;
+
+/**
+ * @brief PDS force configuration type definition
+ */
+typedef struct
+{
+ uint32_t McuWfiMask : 1; /*!< [0]pds start condition mask np_wfi */
+ uint32_t rsv1 : 1; /*!< [1]reserve */
+ uint32_t DspWfiMask : 1; /*!< [2]pds start condition mask mm_wfi */
+ uint32_t rsv3 : 1; /*!< [3]reserve */
+ uint32_t LpWfiMask : 1; /*!< [4]pds start condition mask pico_wfi */
+ uint32_t rsv5_7 : 3; /*!< [7:5]reserve */
+ uint32_t ctrlUsb33 : 1; /*!< [8]enable HW control turn on&&off USB 3.3V */
+ uint32_t pdLdo18io : 1; /*!< [9]power down ldo18io during PDS */
+ uint32_t rsv10_15 : 6; /*!< [15:10]reserve */
+ uint32_t gpioKeepEn : 3; /*!< [18:16]can use bit to enable or disable keep function */
+ uint32_t rsv19_31 : 13; /*!< [31:19]reserve */
+} PDS_CTL5_Type;
+
+/**
+ * @brief PDS default level configuration type definition
+ */
+typedef struct
+{
+ PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */
+ PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */
+ PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */
+ PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */
+ PDS_CTL5_Type pdsCtl5; /*!< PDS_CTL5 configuration */
+} PDS_DEFAULT_LV_CFG_Type;
+
+/**
+ * @brief PDS control RAM1 type definition
+ */
+typedef struct
+{
+ uint32_t ocramSlp : 4; /*!< [3:0] cr_ocram_slp */
+ uint32_t ocramRet : 4; /*!< [7:4] cr_ocram_ret */
+ uint32_t ramClkCnt : 6; /*!< [13:8] HW Option : Assert Extra Clock Counter in MEM_STBY */
+ uint32_t rsv14_15 : 2; /*!< [15:14] reserved */
+ uint32_t ramClkCnt2 : 6; /*!< [21:16] HW Option : Assert Extra Clock Counter in MEM_IDLE/LV_MEM_IDLE */
+ uint32_t rsv22_23 : 2; /*!< [23:22] reserved */
+ uint32_t mcuRamClk : 1; /*!< [24] PDS Control PD_CORE_CPU SRAM Clock */
+ uint32_t dspRamClk : 1; /*!< [25] PDS Control PD_MM SRAM Clock */
+ uint32_t wbRamClk : 1; /*!< [26] PDS Control PD_WB SRAM Clock */
+ uint32_t usbRamClk : 1; /*!< [27] PDS Control PD_usb SRAM Clock */
+ uint32_t miscRamClk : 1; /*!< [28] PDS Control PD_CORE_MISC SRAM Clock */
+ uint32_t rsv29 : 1; /*!< [29] reserved */
+ uint32_t ctlRamClk2 : 1; /*!< [30] To assert extra clock during PDS on sequence */
+ uint32_t ctlRamClk : 1; /*!< [31] Enable PDS Control PD_CORE SRAM Clock */
+} PDS_CTRL_RAM1_Type;
+
+/**
+ * @brief PDS control RAM2 type definition
+ */
+typedef struct
+{
+ uint32_t wramSlp : 10; /*!< [9:0] cr_wram_slp */
+ uint32_t wramRet : 10; /*!< [19:10] cr_wram_ret */
+ uint32_t rsv20_31 : 12; /*!< [31:20] reserved */
+} PDS_CTRL_RAM2_Type;
+
+/**
+ * @brief PDS OCRAM configuration type definition
+ */
+typedef struct
+{
+ uint32_t PDS_OCRAM_CFG_0KB_16KB_CPU_RAM_SLP : 1; /*!< [0] 0~16KB cpu_ram sleep */
+ uint32_t PDS_OCRAM_CFG_16KB_32KB_CPU_RAM_SLP : 1; /*!< [1] 16~32KB cpu_ram sleep */
+ uint32_t PDS_OCRAM_CFG_32KB_48KB_CPU_RAM_SLP : 1; /*!< [2] 32~48KB cpu_ram sleep */
+ uint32_t PDS_OCRAM_CFG_48KB_64KB_CPU_RAM_SLP : 1; /*!< [3] 48~64KB cpu_ram sleep */
+ uint32_t PDS_OCRAM_CFG_0KB_16KB_CPU_RAM_RET : 1; /*!< [4] 0~16KB cpu_ram retension */
+ uint32_t PDS_OCRAM_CFG_16KB_32KB_CPU_RAM_RET : 1; /*!< [5] 16~32KB cpu_ram retension */
+ uint32_t PDS_OCRAM_CFG_32KB_48KB_CPU_RAM_RET : 1; /*!< [6] 32~48KB cpu_ram retension */
+ uint32_t PDS_OCRAM_CFG_48KB_64KB_CPU_RAM_RET : 1; /*!< [7] 48~64KB cpu_ram retension */
+ uint32_t PDS_OCRAM_CFG_RSV : 24; /*!< [31:8]reserve */
+} PDS_OCRAM_CFG_Type;
+
+/**
+ * @brief PDS WRAM configuration type definition
+ */
+typedef struct
+{
+ uint32_t PDS_WRAM_CFG_0KB_16KB_CPU_RAM_SLP : 1; /*!< [0] 0~16KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_16KB_32KB_CPU_RAM_SLP : 1; /*!< [1] 16~32KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_32KB_48KB_CPU_RAM_SLP : 1; /*!< [2] 32~48KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_48KB_64KB_CPU_RAM_SLP : 1; /*!< [3] 48~64KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_64KB_80KB_CPU_RAM_SLP : 1; /*!< [4] 64~80KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_80KB_96KB_CPU_RAM_SLP : 1; /*!< [5] 80~96KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_96KB_112KB_CPU_RAM_SLP : 1; /*!< [6] 96~112KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_112KB_128KB_CPU_RAM_SLP : 1; /*!< [7] 112~128KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_128KB_144KB_CPU_RAM_SLP : 1; /*!< [8] 128~144KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_144KB_160KB_CPU_RAM_SLP : 1; /*!< [9] 144~160KB cpu_ram sleep */
+ uint32_t PDS_WRAM_CFG_0KB_16KB_CPU_RAM_RET : 1; /*!< [10] 0~16KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_16KB_32KB_CPU_RAM_RET : 1; /*!< [11] 16~32KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_32KB_48KB_CPU_RAM_RET : 1; /*!< [12] 32~48KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_48KB_64KB_CPU_RAM_RET : 1; /*!< [13] 48~64KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_64KB_80KB_CPU_RAM_RET : 1; /*!< [14] 64~80KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_80KB_96KB_CPU_RAM_RET : 1; /*!< [15] 80~96KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_96KB_112KB_CPU_RAM_RET : 1; /*!< [16] 96~112KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_112KB_128KB_CPU_RAM_RET : 1; /*!< [17] 112~128KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_128KB_144KB_CPU_RAM_RET : 1; /*!< [18] 128~144KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_144KB_160KB_CPU_RAM_RET : 1; /*!< [19] 144~160KB cpu_ram retension */
+ uint32_t PDS_WRAM_CFG_RSV : 22; /*!< [31:20]reserve */
+} PDS_WRAM_CFG_Type;
+
+/**
+ * @brief PDS level 0/1/2/3 mode HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+ PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE = 0, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync falling edge trigger */
+ PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE = 1, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising edge trigger */
+ PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL = 2, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync low level trigger */
+ PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL = 3, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync high level trigger */
+ PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_FALLING = 7, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising+falling edge trigger */
+ PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE = 8, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async falling edge trigger */
+ PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE = 9, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async rising edge trigger */
+ PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL = 10, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async low level trigger */
+ PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL = 11, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async high level trigger */
+} PDS_AON_GPIO_INT_Trigger_Type;
+
+/**
+ * @brief PDS APP configuration type definition
+ */
+typedef struct
+{
+ uint8_t pdsLevel; /*!< PDS level */
+ uint8_t turnOffRF; /*!< Wheather turn off RF */
+ uint8_t useXtal32k; /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */
+ uint8_t pdsAonGpioWakeupSrc; /*!< PDS level 0/1/2/3 mode always on GPIO Wakeup source(HBN wakeup pin) */
+ PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0/1/2/3 mode always on GPIO Triger type(HBN wakeup pin) */
+ uint8_t powerDownFlash; /*!< Whether power down flash */
+ uint8_t turnOffFlashPad; /*!< Whether turn off embedded flash pad */
+ uint8_t ocramRetetion; /*!< Whether OCRAM Retention */
+ uint8_t turnoffPLL; /*!< Whether trun off PLL */
+ uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
+ uint8_t flashContRead; /*!< Whether enable flash continue read */
+ uint32_t sleepTime; /*!< PDS sleep time */
+ spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */
+ PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
+ void (*preCbFun)(void); /*!< Pre callback function */
+ void (*postCbFun)(void); /*!< Post callback function */
+} PDS_APP_CFG_Type;
+
+/*@} end of group PDS_Public_Types */
+
+/** @defgroup PDS_Public_Constants
+ * @{
+ */
+
+/** @defgroup PDS_GPIO_INT_SET_TYPE
+ * @{
+ */
+#define IS_PDS_GPIO_INT_SET_TYPE(type) (((type) == PDS_GPIO_INT_SET_1_GPIO0_GPIO7) || \
+ ((type) == PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22) || \
+ ((type) == PDS_GPIO_INT_SET_3_GPIO23_GPIO30) || \
+ ((type) == PDS_GPIO_INT_SET_4_GPIO31_GPIO38))
+
+/** @defgroup GLB_GPIO_INT_TRIG_TYPE
+ * @{
+ */
+#define IS_PDS_GPIO_INT_TRIG_TYPE(type) (((type) == PDS_GPIO_INT_SYNC_FALLING_EDGE) || \
+ ((type) == PDS_GPIO_INT_SYNC_RISING_EDGE) || \
+ ((type) == PDS_GPIO_INT_SYNC_LOW_LEVEL) || \
+ ((type) == PDS_GPIO_INT_SYNC_HIGH_LEVEL) || \
+ ((type) == PDS_GPIO_INT_SYNC_RISING_FALLING_EDGE) || \
+ ((type) == PDS_GPIO_INT_ASYNC_FALLING_EDGE) || \
+ ((type) == PDS_GPIO_INT_ASYNC_RISING_EDGE) || \
+ ((type) == PDS_GPIO_INT_ASYNC_LOW_LEVEL) || \
+ ((type) == PDS_GPIO_INT_ASYNC_HIGH_LEVEL))
+
+/** @defgroup PDS_LP_SYS_CLK_TYPE
+ * @{
+ */
+#define IS_PDS_LP_SYS_CLK_TYPE(type) (((type) == PDS_LP_SYS_CLK_BCLK_DIV))
+
+/** @defgroup PDS_LDO_LEVEL_TYPE
+ * @{
+ */
+#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P70V) || \
+ ((type) == PDS_LDO_LEVEL_0P75V) || \
+ ((type) == PDS_LDO_LEVEL_0P80V) || \
+ ((type) == PDS_LDO_LEVEL_0P85V) || \
+ ((type) == PDS_LDO_LEVEL_0P90V) || \
+ ((type) == PDS_LDO_LEVEL_0P95V) || \
+ ((type) == PDS_LDO_LEVEL_1P00V) || \
+ ((type) == PDS_LDO_LEVEL_1P05V) || \
+ ((type) == PDS_LDO_LEVEL_1P10V) || \
+ ((type) == PDS_LDO_LEVEL_1P15V) || \
+ ((type) == PDS_LDO_LEVEL_1P20V) || \
+ ((type) == PDS_LDO_LEVEL_1P25V) || \
+ ((type) == PDS_LDO_LEVEL_1P30V) || \
+ ((type) == PDS_LDO_LEVEL_1P35V))
+
+/** @defgroup PDS_INT_TYPE
+ * @{
+ */
+#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \
+ ((type) == PDS_INT_RF_DONE) || \
+ ((type) == PDS_INT_WIFI_TBTT_SLEEP) || \
+ ((type) == PDS_INT_WIFI_TBTT_WAKEUP) || \
+ ((type) == PDS_INT_MAX))
+
+/** @defgroup PDS_AON_GPIO_INT_TRIGGER_TYPE
+ * @{
+ */
+#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_FALLING) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \
+ ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/*@} end of group PDS_Public_Constants */
+
+/** @defgroup PDS_Public_Macros
+ * @{
+ */
+#define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */
+#define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */
+#define PDS_INT_MASK_BIT_OFFSET (4)
+
+/*@} end of group PDS_Public_Macros */
+
+/** @defgroup PDS_Public_Functions
+ * @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void);
+#endif
+BL_Err_Type PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_Type pad, uint8_t pu, uint8_t pd, uint8_t ie);
+BL_Err_Type PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask);
+BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig);
+BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set);
+BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad);
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg);
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg);
+BL_Err_Type PDS_Set_MCU0_Clock_Enable(void);
+BL_Err_Type PDS_Set_MCU0_Clock_Disable(void);
+BL_Err_Type PDS_Set_MCU0_Reset_Address(uint32_t addr);
+BL_Err_Type PDS_Set_LP_Clock_Enable(void);
+BL_Err_Type PDS_Set_LP_Clock_Disable(void);
+BL_Err_Type PDS_Set_LP_System_CLK_Div(uint8_t div);
+BL_Err_Type PDS_Set_LP_System_CLK(PDS_LP_SYS_CLK_Type clkFreq);
+BL_Err_Type PDS_Reset_LP_RTC(void);
+BL_Err_Type PDS_Set_LP_RTC_CLK(uint8_t enable, uint16_t div);
+BL_Err_Type PDS_Set_LP_Reset_Address(uint32_t addr);
+/*----------*/
+BL_Sts_Type PDS_Get_MM_System_Power_On_State(void);
+BL_Err_Type PDS_Power_On_MM_System(void);
+/*----------*/
+BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt);
+BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5);
+BL_Err_Type PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg);
+/*----------*/
+BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_CTRL_RAM1_Type *ram1Cfg,
+ PDS_CTRL_RAM2_Type *ram2Cfg, uint32_t pdsSleepCnt);
+/*----------*/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask);
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType);
+BL_Err_Type PDS_IntClear(void);
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type PDS_Trim_RC32M(void);
+/*----------*/
+BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady);
+BL_Err_Type PDS_Turn_Off_USB(void);
+BL_Err_Type PDS_Set_USB_Suspend(void);
+BL_Err_Type PDS_Set_USB_Resume(void);
+/*----------*/
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_PDS_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_psram.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_psram.h
new file mode 100644
index 00000000..f199d599
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_psram.h
@@ -0,0 +1,488 @@
+/**
+ ******************************************************************************
+ * @file bl808_psram.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_PSRAM_CTRL_H__
+#define __BL808_PSRAM_CTRL_H__
+
+#include "psram_reg.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup PSRAM_CTRL
+ * @{
+ */
+
+/** @defgroup PSRAM_CTRL_Public_Types
+ * @{
+ */
+
+/**
+ * @brief PSRAM ID
+ */
+typedef enum {
+ PSRAM0_ID, /*!< PSRAM0 identifier */
+} PSRAM_ID_Type;
+
+/**
+ * @brief PSRAM Ctrl IO mode type definition
+ */
+typedef enum {
+ PSRAM_CTRL_X8_MODE, /*!< PSRAM X8 mode */
+ PSRAM_CTRL_X16_MODE, /*!< PSRAM X16 mode */
+} PSRAM_Ctrl_Io_Mode_Type;
+
+/**
+ * @brief PSRAM Ctrl PSRAM vendor type definition
+ */
+typedef enum {
+ PSRAM_CTRL_VENDOR_WINBOND = 0x1, /*!< Winbond psram */
+ PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB = 0x2, /*!< AP memory psram exclude 4MB size */
+ PSRAM_CTRL_VENDOR_APMEM_4MB = 0x4, /*!< AP memory psram 4MB size */
+} PSRAM_Ctrl_Vendor_Type;
+
+/**
+ * @brief PSRAM SIZE
+ */
+typedef enum {
+ PSRAM_SIZE_4MB = 0x3, /*!< PSRAM size is 4MB */
+ PSRAM_SIZE_8MB = 0x7, /*!< PSRAM size is 8MB */
+ PSRAM_SIZE_16MB = 0xf, /*!< PSRAM size is 16MB */
+ PSRAM_SIZE_32MB = 0x1f, /*!< PSRAM size is 32MB */
+} PSRAM_Ctrl_Size_Type;
+
+/**
+ * @brief Winbond PSRAM configuration register type definition
+ */
+typedef enum {
+ PSRAM_WINBOND_REG_ID0, /*!< Winbond register ID0 */
+ PSRAM_WINBOND_REG_ID1, /*!< Winbond register ID1 */
+ PSRAM_WINBOND_REG_CR0, /*!< Winbond register CR0 */
+ PSRAM_WINBOND_REG_CR1, /*!< Winbond register CR1 */
+ PSRAM_WINBOND_REG_CR2, /*!< Winbond register CR2 */
+ PSRAM_WINBOND_REG_CR3, /*!< Winbond register CR3 */
+ PSRAM_WINBOND_REG_CR4, /*!< Winbond register CR4 */
+} PSRAM_Ctrl_Winbond_Cfg_Reg_Type;
+
+/**
+ * @brief APMemory PSRAM configuration register type definition
+ */
+typedef enum {
+ PSRAM_APMEM_REG_0 = 0, /*!< APMemory register 0 */
+ PSRAM_APMEM_REG_1, /*!< APMemory register 1 */
+ PSRAM_APMEM_REG_2, /*!< APMemory register 2 */
+ PSRAM_APMEM_REG_3, /*!< APMemory register 3 */
+ PSRAM_APMEM_REG_4, /*!< APMemory register 4 */
+ PSRAM_APMEM_REG_5, /*!< APMemory register 5 */
+ PSRAM_APMEM_REG_6, /*!< APMemory register 6 */
+ PSRAM_APMEM_REG_8, /*!< APMemory register 8 */
+} PSRAM_Ctrl_ApMem_Cfg_Reg_Type;
+
+/**
+ * @brief PSRAM Latency Counter type definition
+ */
+typedef enum {
+ PSRAM_WINBOND_5_CLOCKS_LATENCY, /*!< PSRAM 5 clocks latency 133MHZ */
+ PSRAM_WINBOND_6_CLOCKS_LATENCY, /*!< PSRAM 6 clocks latency 166MHZ */
+ PSRAM_WINBOND_7_CLOCKS_LATENCY, /*!< PSRAM 7 clocks latency 200MHZ */
+ PSRAM_WINBOND_3_CLOCKS_LATENCY = 0xE, /*!< PSRAM 3 clocks latency 83MHZ */
+ PSRAM_WINBOND_4_CLOCKS_LATENCY = 0xF, /*!< PSRAM 4 clocks latency 100MHZ */
+ PSRAM_WINBOND_14_CLOCKS_LATENCY = 0x7, /*!< PSRAM 14 clocks latency only for Hyperbus3 400MHZ */
+ PSRAM_WINBOND_19_CLOCKS_LATENCY = 0x9, /*!< PSRAM 19 clocks latency only for Hyperbus3 533MHZ */
+} PSRAM_Latency_Winbond_Type;
+
+/**
+ * @brief PSRAM Burst Type
+ */
+typedef enum {
+ PSRAM_HYBRID_BURST, /*!< PSRAM use hybrid brust */
+ PSRAM_WRAPPED_BURST, /*!< PSRAM use warpped brust */
+} PSRAM_Burst_Type;
+
+/**
+ * @brief PSRAM Latency Counter type definition
+ */
+typedef enum {
+ PSRAM_APMEM_3_CLOCKS_LATENCY, /*!< PSRAM 3 clocks latency */
+ PSRAM_APMEM_4_CLOCKS_LATENCY = 0x4, /*!< PSRAM 4 clocks latency */
+ PSRAM_APMEM_5_CLOCKS_LATENCY = 0x2, /*!< PSRAM 5 clocks latency */
+ PSRAM_APMEM_6_CLOCKS_LATENCY = 0x6, /*!< PSRAM 6 clocks latency */
+ PSRAM_APMEM_7_CLOCKS_LATENCY = 0x1, /*!< PSRAM 7 clocks latency */
+} PSRAM_Latency_ApMem_Type;
+
+/**
+ * @brief PSRAM Drive Strength type definition for Winbon 4M
+ */
+typedef enum {
+ PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M, /*!< drive strength 50 ohms for 4M size ,34 ohms for 8M size */
+ PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M, /*!< drive strength 35 ohms for 4M size ,115 ohms for 8M size */
+ PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M, /*!< drive strength 100 ohms for 4M size ,67 ohms for 8M size */
+ PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M, /*!< drive strength 200 ohms for 4M size ,46 ohms for 8M size */
+ PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M, /*!< drive strength 34 ohms only for 8M size */
+ PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M, /*!< drive strength 27 ohms only for 8M size */
+ PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M, /*!< drive strength 22 ohms only for 8M size */
+ PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M, /*!< drive strength 19 ohms only for 8M size */
+} PSRAM_Winbond_Drive_Strength;
+
+/**
+ * @brief PSRAM Drive Strength type definition for Winbon 8MB
+ */
+typedef enum {
+ PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS, /*!< drive strength 25 ohms */
+ PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS, /*!< drive strength 50 ohms */
+ PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS, /*!< drive strength 100 ohms */
+ PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS, /*!< drive strength 200 ohms */
+} PSRAM_ApMem_Drive_Strength;
+
+/**
+ * @brief PSRAM Burst Length type definition
+ */
+typedef enum {
+ PSRAM_WINBOND_BURST_LENGTH_128_BYTES = 0x4, /*!< Burst Length 128 bytes */
+ PSRAM_WINBOND_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */
+ PSRAM_WINBOND_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */
+ PSRAM_WINBOND_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */
+ PSRAM_WINBOND_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 only for HyperBus3 */
+} PSRAM_Winbond_Burst_Length;
+
+/**
+ * @brief PSRAM Burst Length type definition
+ */
+typedef enum {
+ PSRAM_APMEM_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */
+ PSRAM_APMEM_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */
+ PSRAM_APMEM_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */
+ PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256, /*!< Burst Length 1K bytes for APS6408L and 2Kbytes for APS256XXN */
+} PSRAM_ApMem_Burst_Length;
+
+/**
+ * @brief PSRAM Fixed Latency Enable type definition
+ */
+typedef enum {
+ PSRAM_VARIALBE_INITIAL_LATENCY, /*!< 1 or 2 times Initial Latency depending on RWDS during CA cycles */
+ PSRAM_FIXED_2_TIMES_INITIAL_LATENCY, /*!< Fixed 2 times Initial Latency (default) */
+} PSRAM_Fixed_Latency_Enable;
+
+/**
+ * @brief PSRAM Deep Power Down Enable type definition
+ */
+typedef enum {
+ PSRAM_DPD_ENTER, /*!< Writing 0 to CR0[15] causes the device to enter Deep Power Down */
+ PSRAM_DPD_NORMAL, /*!< Normal operation (default) */
+} PSRAM_Deep_Power_Down;
+
+/**
+ * @brief Partial Array Self Refresh definition
+ */
+typedef enum {
+ PSRAM_PARTIAL_REFRESH_FULL, /*!< PSRAM partial refresh full array (000000h - 1FFFFFh) */
+ PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2, /*!< PSRAM partial refresh Bottom 1/2 array (000000h - 0FFFFFh) */
+ PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4, /*!< PSRAM partial refresh Bottom 1/4 array (000000h - 07FFFFh) */
+ PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8, /*!< PSRAM partial refresh Bottom 1/8 array (000000h - 03FFFFh) */
+ PSRAM_PARTIAL_REFRESH_NONE, /*!< PSRAM partial refresh None */
+ PSRAM_PARTIAL_REFRESH_TOP_1TO2, /*!< PSRAM partial refresh Top 1/2 array (100000h - 1FFFFFh) */
+ PSRAM_PARTIAL_REFRESH_TOP_1TO4, /*!< PSRAM partial refresh Top 1/4 array (180000h - 1FFFFFh) */
+ PSRAM_PARTIAL_REFRESH_TOP_1TO8, /*!< PSRAM partial refresh Top 1/8 array (1C0000h - 1FFFFFh) */
+} PSRAM_Partial_Array_Refresh;
+
+/**
+ * @brief PSRAM ApMem self-fresh freq
+ */
+typedef enum {
+ PSRAM_APMEM_FAST_REFRESH, /*!< Fast Refresh (default) */
+ PSRAM_APMEM_SLOW_REFRESH, /*!< Enables Slow Refresh when temperature allows */
+} PSRAM_ApMem_Refresh_Speed;
+
+/**
+ * @brief PSRAM Hybrid Sleep Mode type definition
+ */
+typedef enum {
+ PSRAM_HYBRID_SLEEP_DISABLE, /*!< not in Hybrid Sleep Mode */
+ PSRAM_HYBRID_SLEEP_ENABLE, /*!< entering Hybrid Sleep Mode */
+} PSRAM_Hybrid_Sleep_Mode;
+
+/**
+ * @brief PSRAM Master Clock type definition
+ */
+typedef enum {
+ PSRAM_CLOCK_DIFF, /*!< PSRAM Master Clock is differential */
+ PSRAM_CLOCK_SINGLE, /*!< PSRAM Master Clock is single end */
+} PSRAM_Clock_Type;
+
+/**
+ * @brief PSRAM delay chain configuration definition
+ */
+typedef struct
+{
+ PSRAM_Ctrl_Vendor_Type vendor; /*!< PSRAM Vendor */
+ PSRAM_Ctrl_Io_Mode_Type ioMode; /*!< PSRAM interface mode */
+ PSRAM_Ctrl_Size_Type size; /*!< PSRAM size */
+ uint32_t dqs_delay; /*!< PSRAM dqs delay value */
+} PSRAM_Ctrl_Cfg_Type;
+
+/**
+ * @brief PSRAM Winbon configuration definition
+ */
+typedef struct
+{
+ BL_Fun_Type rst; /*!< Winbond pSRAM CR1 - Software Reset */
+ PSRAM_Clock_Type clockType; /*!< Winbond pSRAM CR1 - Master Clock Type */
+ BL_Fun_Type inputPowerDownMode; /*!< Winbond pSRAM CR1 - Input Power Down */
+ BL_Fun_Type linear_dis; /*!< Winbond pSRAM linear burst disable */
+ BL_Fun_Type hybridSleepMode; /*!< Winbond pSRAM CR1 - Hybrid Sleep Mode configuration */
+ PSRAM_Partial_Array_Refresh PASR; /*!< Winbond pSRAM CR1 - Partial Array Refresh + Distributed Refresh Interval */
+ BL_Fun_Type disDeepPowerDownMode; /*!< Winbond pSRAM CR0 - Deep Power-Down Disable configuration */
+ BL_Fun_Type fixedLatency; /*!< Winbond pSRAM CR1 - Fix Latency configuration */
+ PSRAM_Winbond_Burst_Length brustLen; /*!< Winbond pSRAM CR0 - Burst Length configuration */
+ PSRAM_Burst_Type brustType; /*!< Winbond pSRAM CR0 - Hybrid Burst Enable */
+ PSRAM_Winbond_Drive_Strength driveStrength; /*!< Winbond pSRAM CR0 - Drive Strength configuration */
+ PSRAM_Latency_Winbond_Type latency; /*!< Winbond pSRAM CR0 - Latency Counter configuration */
+} PSRAM_Winbond_Cfg_Type;
+
+/**
+ * @brief PSRAM Winbon configuration definition
+ */
+typedef struct
+{
+ BL_Fun_Type rst; /*!< AP Memory pSRAM configure global reset enable */
+ BL_Fun_Type fixedLatency; /*!< AP Memory pSRAM configure MR0 - read latency type */
+ PSRAM_Latency_ApMem_Type readLatency; /*!< AP Memory pSRAM configure MR0 - read latency code */
+ PSRAM_ApMem_Refresh_Speed refreshFreq; /*!< AP Memory pSRAM configure MR4 - refresh frequency */
+ PSRAM_ApMem_Drive_Strength driveStrength; /*!< AP Memory pSRAM configure MR0 - drive strength */
+ PSRAM_Latency_ApMem_Type writeLatency; /*!< AP Memory pSRAM configure MR4 - write latency code */
+ PSRAM_Partial_Array_Refresh PASR; /*!< AP Memory pSRAM configure MR4 - partial array refresh */
+ BL_Fun_Type halfSleepModeEnable; /*!< AP Memory pSRAM configure MR6 - Half Sleep enable */
+ BL_Fun_Type deepPowerDownModeEnable; /*!< AP Memory pSRAM configure MR6 - Deep Power Down enable */
+ BL_Fun_Type crossBoundaryEnable; /*!< AP Memory pSRAM configure MR8 - cross boundary enable 1'b0 - Read within 1K boundary 1'b1 -
+ Read cross 1K boundary */
+ PSRAM_Burst_Type brustType; /*!< AP Memory pSRAM configure MR8 - burst type */
+ PSRAM_ApMem_Burst_Length brustLen; /*!< AP Memory pSRAM configure MR8 - burst length */
+} PSRAM_APMemory_Cfg_Type;
+
+/*@} end of group PSRAM_CTRL_Public_Types */
+
+/** @defgroup PSRAM_CTRL_Public_Constants
+ * @{
+ */
+
+/** @defgroup PSRAM_ID_TYPE
+ * @{
+ */
+#define IS_PSRAM_ID_TYPE(type) (((type) == PSRAM0_ID) || \
+ ((type) == PSRAM1_ID))
+
+/** @defgroup PSRAM_CTRL_IO_MODE_TYPE
+ * @{
+ */
+#define IS_PSRAM_CTRL_IO_MODE_TYPE(type) (((type) == PSRAM_CTRL_X8_MODE) || \
+ ((type) == PSRAM_CTRL_X16_MODE))
+
+/** @defgroup PSRAM_CTRL_VENDOR_TYPE
+ * @{
+ */
+#define IS_PSRAM_CTRL_VENDOR_TYPE(type) (((type) == PSRAM_CTRL_VENDOR_WINBOND) || \
+ ((type) == PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB) || \
+ ((type) == PSRAM_CTRL_VENDOR_APMEM_4MB))
+
+/** @defgroup PSRAM_CTRL_SIZE_TYPE
+ * @{
+ */
+#define IS_PSRAM_CTRL_SIZE_TYPE(type) (((type) == PSRAM_SIZE_4MB) || \
+ ((type) == PSRAM_SIZE_8MB) || \
+ ((type) == PSRAM_SIZE_16MB) || \
+ ((type) == PSRAM_SIZE_32MB))
+
+/** @defgroup PSRAM_CTRL_WINBOND_CFG_REG_TYPE
+ * @{
+ */
+#define IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(type) (((type) == PSRAM_WINBOND_REG_ID0) || \
+ ((type) == PSRAM_WINBOND_REG_ID1) || \
+ ((type) == PSRAM_WINBOND_REG_CR0) || \
+ ((type) == PSRAM_WINBOND_REG_CR1) || \
+ ((type) == PSRAM_WINBOND_REG_CR2) || \
+ ((type) == PSRAM_WINBOND_REG_CR3) || \
+ ((type) == PSRAM_WINBOND_REG_CR4))
+
+/** @defgroup PSRAM_CTRL_APMEM_CFG_REG_TYPE
+ * @{
+ */
+#define IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(type) (((type) == PSRAM_APMEM_REG_0) || \
+ ((type) == PSRAM_APMEM_REG_1) || \
+ ((type) == PSRAM_APMEM_REG_2) || \
+ ((type) == PSRAM_APMEM_REG_3) || \
+ ((type) == PSRAM_APMEM_REG_4) || \
+ ((type) == PSRAM_APMEM_REG_5) || \
+ ((type) == PSRAM_APMEM_REG_6) || \
+ ((type) == PSRAM_APMEM_REG_8))
+
+/** @defgroup PSRAM_LATENCY_WINBOND_TYPE
+ * @{
+ */
+#define IS_PSRAM_LATENCY_WINBOND_TYPE(type) (((type) == PSRAM_WINBOND_5_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_WINBOND_6_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_WINBOND_7_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_WINBOND_3_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_WINBOND_4_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_WINBOND_14_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_WINBOND_19_CLOCKS_LATENCY))
+
+/** @defgroup PSRAM_BURST_TYPE
+ * @{
+ */
+#define IS_PSRAM_BURST_TYPE(type) (((type) == PSRAM_HYBRID_BURST) || \
+ ((type) == PSRAM_WRAPPED_BURST))
+
+/** @defgroup PSRAM_LATENCY_APMEM_TYPE
+ * @{
+ */
+#define IS_PSRAM_LATENCY_APMEM_TYPE(type) (((type) == PSRAM_APMEM_3_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_APMEM_4_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_APMEM_5_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_APMEM_6_CLOCKS_LATENCY) || \
+ ((type) == PSRAM_APMEM_7_CLOCKS_LATENCY))
+
+/** @defgroup PSRAM_WINBOND_DRIVE_STRENGTH
+ * @{
+ */
+#define IS_PSRAM_WINBOND_DRIVE_STRENGTH(type) (((type) == PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M) || \
+ ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M) || \
+ ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M) || \
+ ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M) || \
+ ((type) == PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M) || \
+ ((type) == PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M) || \
+ ((type) == PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M) || \
+ ((type) == PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M))
+
+/** @defgroup PSRAM_APMEM_DRIVE_STRENGTH
+ * @{
+ */
+#define IS_PSRAM_APMEM_DRIVE_STRENGTH(type) (((type) == PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS) || \
+ ((type) == PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS) || \
+ ((type) == PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS) || \
+ ((type) == PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS))
+
+/** @defgroup PSRAM_WINBOND_BURST_LENGTH
+ * @{
+ */
+#define IS_PSRAM_WINBOND_BURST_LENGTH(type) (((type) == PSRAM_WINBOND_BURST_LENGTH_128_BYTES) || \
+ ((type) == PSRAM_WINBOND_BURST_LENGTH_64_BYTES) || \
+ ((type) == PSRAM_WINBOND_BURST_LENGTH_16_BYTES) || \
+ ((type) == PSRAM_WINBOND_BURST_LENGTH_32_BYTES) || \
+ ((type) == PSRAM_WINBOND_BURST_LENGTH_512_BYTES))
+
+/** @defgroup PSRAM_APMEM_BURST_LENGTH
+ * @{
+ */
+#define IS_PSRAM_APMEM_BURST_LENGTH(type) (((type) == PSRAM_APMEM_BURST_LENGTH_16_BYTES) || \
+ ((type) == PSRAM_APMEM_BURST_LENGTH_32_BYTES) || \
+ ((type) == PSRAM_APMEM_BURST_LENGTH_64_BYTES) || \
+ ((type) == PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256))
+
+/** @defgroup PSRAM_FIXED_LATENCY_ENABLE
+ * @{
+ */
+#define IS_PSRAM_FIXED_LATENCY_ENABLE(type) (((type) == PSRAM_VARIALBE_INITIAL_LATENCY) || \
+ ((type) == PSRAM_FIXED_2_TIMES_INITIAL_LATENCY))
+
+/** @defgroup PSRAM_DEEP_POWER_DOWN
+ * @{
+ */
+#define IS_PSRAM_DEEP_POWER_DOWN(type) (((type) == PSRAM_DPD_ENTER) || \
+ ((type) == PSRAM_DPD_NORMAL))
+
+/** @defgroup PSRAM_PARTIAL_ARRAY_REFRESH
+ * @{
+ */
+#define IS_PSRAM_PARTIAL_ARRAY_REFRESH(type) (((type) == PSRAM_PARTIAL_REFRESH_FULL) || \
+ ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2) || \
+ ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4) || \
+ ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8) || \
+ ((type) == PSRAM_PARTIAL_REFRESH_NONE) || \
+ ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO2) || \
+ ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO4) || \
+ ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO8))
+
+/** @defgroup PSRAM_APMEM_REFRESH_SPEED
+ * @{
+ */
+#define IS_PSRAM_APMEM_REFRESH_SPEED(type) (((type) == PSRAM_APMEM_FAST_REFRESH) || \
+ ((type) == PSRAM_APMEM_SLOW_REFRESH))
+
+/** @defgroup PSRAM_HYBRID_SLEEP_MODE
+ * @{
+ */
+#define IS_PSRAM_HYBRID_SLEEP_MODE(type) (((type) == PSRAM_HYBRID_SLEEP_DISABLE) || \
+ ((type) == PSRAM_HYBRID_SLEEP_ENABLE))
+
+/** @defgroup PSRAM_CLOCK_TYPE
+ * @{
+ */
+#define IS_PSRAM_CLOCK_TYPE(type) (((type) == PSRAM_CLOCK_DIFF) || \
+ ((type) == PSRAM_CLOCK_SINGLE))
+
+/*@} end of group PSRAM_CTRL_Public_Constants */
+
+/** @defgroup PSRAM_CTRL_Public_Macros
+ * @{
+ */
+
+/*@} end of group PSRAM_CTRL_Public_Macros */
+
+/** @defgroup PSRAM_CTRL_Public_Functions
+ * @{
+ */
+void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg);
+BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);
+BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,
+ PSRAM_Winbond_Cfg_Type *reg_cfg);
+BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);
+BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,
+ PSRAM_APMemory_Cfg_Type *reg_cfg);
+void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID);
+void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel);
+void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID);
+uint8_t PSram_Ctrl_Get_Timeout_Flag(PSRAM_ID_Type PSRAM_ID);
+void PSram_Ctrl_Clear_Timout_Flag(PSRAM_ID_Type PSRAM_ID);
+void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t timeoutThr);
+
+/*@} end of group PSRAM_CTRL_Public_Functions */
+
+/*@} end of group PSRAM_CTRL */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_PSRAM_CTRL_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_psram_uhs.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_psram_uhs.h
new file mode 100644
index 00000000..df369258
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_psram_uhs.h
@@ -0,0 +1,273 @@
+/**
+ ******************************************************************************
+ * @file bl808_psram_uhs.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_PSRAM_UHS_H__
+#define __BL808_PSRAM_UHS_H__
+
+#include "psram_uhs_reg.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup PSRAM_UHS
+ * @{
+ */
+
+/** @defgroup PSRAM_UHS_Public_Types
+ * @{
+ */
+
+/**
+ * @brief Psram UHS Size
+ */
+typedef enum {
+ PSRAM_MEM_SIZE_4MB = 0x03, /*!< PSRAM Memory Size 4M */
+ PSRAM_MEM_SIZE_8MB = 0x07, /*!< PSRAM Memory Size 8M */
+ PSRAM_MEM_SIZE_16MB = 0x0f, /*!< PSRAM Memory Size 16M */
+ PSRAM_MEM_SIZE_32MB = 0x1f, /*!< PSRAM Memory Size 32M */
+ PSRAM_MEM_SIZE_64MB = 0x3f, /*!< PSRAM Memory Size 64M */
+} PSRAM_UHS_Mem_Size_Type;
+
+/**
+ * @brief Psram UHS Page Type
+ */
+typedef enum {
+ PSRAM_PAGE_SIZE_2KB = 0x0B, /*!< PSRAM Page Size 2KB */
+ PSRAM_PAGE_SIZE_4KB = 0x16, /*!< PSRAM Page Size 4KB */
+} PSRAM_UHS_Page_Size_Type;
+
+/**
+ * @brief Psram UHS Burst Size
+ */
+typedef enum {
+ PSRAM_UHS_WARP_BURST_64, /*!< PSRAM Warp Burst Size 64 */
+ PSRAM_UHS_WARP_BURST_32, /*!< PSRAM Warp Burst Size 32 */
+ PSRAM_UHS_WARP_BURST_16, /*!< PSRAM Warp Burst Size 16 */
+ PSRAM_UHS_WARP_BURST_NONE, /*!< PSRAM Warp Burst NONE */
+ PSRAM_UHS_WARP_BURST_NO_CHANGE, /*!< Not change this value */
+} PSRAM_UHS_WARP_BURST_Type;
+
+/**
+ * @brief Psram UHS Driver Strength
+ */
+typedef enum {
+ PSRAM_UHS_DRIVER_ST_34P3_PDPU = 0x1, /*!< 34.3 PD/PU */
+ PSRAM_UHS_DRIVER_ST_40_PDPU = 0x2, /*!< 40 PD/PU */
+ PSRAM_UHS_DRIVER_ST_48_PDPU = 0x3, /*!< 48 PD/PU */
+ PSRAM_UHS_DRIVER_ST_60_PDPU = 0x4, /*!< 60 PD/PU */
+ PSRAM_UHS_DRIVER_ST_80_PDPU = 0x6, /*!< 80 PD/PU */
+ PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU = 0x9, /*!< 34.3 PD & 40 PU */
+ PSRAM_UHS_DRIVER_ST_40_PD_48_PU = 0xa, /*!< 40 PD & 48 PU */
+ PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU = 0xb, /*!< 34.3 PD & 48 PU */
+ PSRAM_UHS_DRIVER_ST_NO_CHANGE = 0xf, /*!< Not change this value */
+} PSRAM_UHS_DRIVER_ST_Type;
+
+/**
+ * @brief Psram UHS LATENCY
+ */
+typedef enum {
+ PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ, /*!< MAX freq. = 533 MHz / Write LATENCY=10 / Read LATENCY=20 */
+ PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ, /*!< MAX freq. = 800 MHz / Write LATENCY=14 / Read LATENCY=29 */
+ PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ, /*!< MAX freq. = 933 MHz / Write LATENCY=16 / Read LATENCY=33 */
+ PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ, /*!< MAX freq. = 1066 MHz / Write LATENCY=18 / Read LATENCY=37 */
+ PSRAM_UHS_LATENCY_RESERVED, /*!< Reserved */
+ PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ, /*!< MAX freq. = 400 MHz / Write LATENCY=6 / Read LATENCY=16 */
+ PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ, /*!< MAX freq. = 333 MHz / Write LATENCY=5 / Read LATENCY=13 */
+ PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ, /*!< MAX freq. = 200 MHz / Write LATENCY=5 / Read LATENCY=9 */
+ PSRAM_UHS_LATENCY_NO_CHANGE, /*!< Not change this value */
+} PSRAM_UHS_LATENCY_Type;
+
+/**
+ * @brief Psram UHS CMD Type
+ */
+typedef enum {
+ PSRAM_UHS_CMD_SELF_REFRESH_IN, /*!< pSRAM self-refresh in command */
+ PSRAM_UHS_CMD_SELF_REFRESH_EXIT, /*!< pSRAM self-refresh exit command */
+ PSRAM_UHS_CMD_GLOBAL_RESET, /*!< pSRAM global reset command */
+ PSRAM_UHS_CMD_ZQ_CAL_LONG, /*! */
+ PSRAM_UHS_CMD_ZQ_CAL_SHORT, /*!*/
+ PSRAM_UHS_CMD_ZQ_CAL_RESET, /*!*/
+} PSRAM_UHS_CMD_Type;
+
+/**
+ * @brief PSRAM UHS Temperature
+ *
+ */
+typedef enum {
+ PSRAM_UHS_NORMAL_TEMP,
+ PSRAM_UHS_HIGH_TEMP,
+} PSRAM_UHS_TEMP_Type;
+
+/**
+ * @brief PSRAM_UHS_Cfg_Type
+ */
+typedef struct {
+ uint32_t pck_freq; /*!< pck frequency unit is MHZ */
+ PSRAM_UHS_Mem_Size_Type psramMemSize; /*!< psram uhm memory size */
+ PSRAM_UHS_Page_Size_Type psramPageSize; /*!< psram uhm page size */
+ PSRAM_UHS_TEMP_Type isHighTem; /*!< auto refresh work temperature */
+} PSRAM_UHS_Cfg_Type;
+
+/**
+ * @brief PSRAM_UHS_Phy_Latency_Pra_Type
+ */
+typedef struct {
+ uint8_t phy_rl_ana; /*!< phy_rl_ana */
+ uint8_t phy_rl_dig; /*!< phy_rl_dig*/
+ uint8_t phy_wl_ana; /*!< phy_wl_ana */
+ uint8_t phy_wl_dig; /*!< phy_wl_dig*/
+ uint8_t phy_wl_dq_ana; /*!< phy_wl_dq_ana */
+ uint8_t phy_wl_dq_dig; /*!< phy_wl_dq_dig */
+
+ uint8_t reg_timer_array_read; /*!< reg_timer_array_read */
+ uint8_t reg_timer_array_write; /*!< reg_timer_array_write */
+ uint8_t reg_timer_dqs_array_stop; /*!< reg_timer_dqs_array_stop */
+ uint8_t reg_timer_dqs_start; /*!< reg_timer_dqs_start */
+
+ uint8_t reg_timer_dqs_stop; /*!< reg_timer_dqs_stop */
+ uint8_t reg_timer_reg_read; /*!< reg_timer_reg_read */
+ uint8_t reg_timer_reg_write; /*!< reg_timer_reg_write */
+ uint8_t reg_timer_auto_refresh; /*!< reg_timer_auto_refresh */
+
+ uint16_t reg_timer_global_rst; /*!< reg_timer_global_rst */
+ uint8_t reg_timer_self_refresh1_in; /*!< reg_timer_self_refresh1_in */
+ uint8_t reg_timer_self_refresh1_exit; /*!< reg_timer_self_refresh1_exit */
+
+ uint8_t reg_timer_reg_write_busy; /*!< reg_timer_reg_write_busy */
+ uint8_t reg_timer_reg_read_busy; /*!< reg_timer_reg_read_busy */
+ uint8_t reg_timer_arrary_write_busy; /*!< reg_timer_arrary_write_busy */
+ uint8_t reg_timer_arrary_read_busy; /*!< reg_timer_arrary_read_busy */
+
+ uint8_t en_rx_fe_dly; /*!< en_rx_fe_dly */
+ uint8_t odt_sel_dly; /*!< odt_sel_dly */
+
+ uint8_t reg_trc_cycle; /*!< reg_trc_cycle */
+ uint8_t reg_trfc_cycle; /*!< reg_trfc_cycle */
+ uint8_t reg_tcphr_cycle; /*!< reg_tcphr_cycle */
+ uint8_t reg_tcphw_cycle; /*!< reg_tcphw_cycle */
+
+} PSRAM_UHS_Phy_Latency_Pra_Type;
+
+/**
+ * @brief PSRAM_UHS_Write_Reg_Cfg_Type
+ */
+typedef struct {
+ PSRAM_UHS_DRIVER_ST_Type driver_st; /*!< driver strength */
+ PSRAM_UHS_WARP_BURST_Type burst_size; /*!< burst size */
+ PSRAM_UHS_LATENCY_Type lentency; /*!< lentency */
+} PSRAM_UHS_Write_Reg_Cfg_Type;
+
+/*@} end of group PSRAM_UHS_Public_Types */
+
+/** @defgroup PSRAM_UHS_Public_Constants
+ * @{
+ */
+
+/** @defgroup PSRAM_UHS_MEM_SIZE_TYPE
+ * @{
+ */
+#define IS_PSRAM_UHS_MEM_SIZE_TYPE(type) (((type) == PSRAM_MEM_SIZE_4MB) || \
+ ((type) == PSRAM_MEM_SIZE_8MB) || \
+ ((type) == PSRAM_MEM_SIZE_16MB) || \
+ ((type) == PSRAM_MEM_SIZE_32MB))
+
+/** @defgroup PSRAM_UHS_PAGE_SIZE_TYPE
+ * @{
+ */
+#define IS_PSRAM_UHS_PAGE_SIZE_TYPE(type) (((type) == PSRAM_PAGE_SIZE_2KB) || \
+ ((type) == PSRAM_PAGE_SIZE_4KB))
+
+/** @defgroup PSRAM_UHS_WARP_BURST_TYPE
+ * @{
+ */
+#define IS_PSRAM_UHS_WARP_BURST_TYPE(type) (((type) == PSRAM_UHS_WARP_BURST_64) || \
+ ((type) == PSRAM_UHS_WARP_BURST_32) || \
+ ((type) == PSRAM_UHS_WARP_BURST_16))
+
+/** @defgroup PSRAM_UHS_DRIVER_ST_TYPE
+ * @{
+ */
+#define IS_PSRAM_UHS_DRIVER_ST_TYPE(type) (((type) == PSRAM_UHS_DRIVER_ST_34P3_PUPU) || \
+ ((type) == PSRAM_UHS_DRIVER_ST_40_PUPU) || \
+ ((type) == PSRAM_UHS_DRIVER_ST_48_PUPU) || \
+ ((type) == PSRAM_UHS_DRIVER_ST_60_PUPU) || \
+ ((type) == PSRAM_UHS_DRIVER_ST_80_PUPU) || \
+ ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU) || \
+ ((type) == PSRAM_UHS_DRIVER_ST_40_PD_48_PU) || \
+ ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU))
+
+/** @defgroup PSRAM_UHS_LATENCY_TYPE
+ * @{
+ */
+#define IS_PSRAM_UHS_LATENCY_TYPE(type) (((type) == PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ) || \
+ ((type) == PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ) || \
+ ((type) == PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ) || \
+ ((type) == PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ) || \
+ ((type) == PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ) || \
+ ((type) == PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ) || \
+ ((type) == PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ))
+/** @defgroup PSRAM_UHS_CMD_Type
+ * @{
+ */
+#define IS_PSRAM_UHS_CMD_TYPE(type) (((type) == PSRAM_UHS_CMD_SELF_REFRESH_IN) || \
+ ((type) == PSRAM_UHS_CMD_SELF_REFRESH_EXIT) || \
+ ((type) == PSRAM_UHS_CMD_GLOBAL_RESET)
+
+/*@} end of group PSRAM_UHS_Public_Constants */
+
+/** @defgroup PSRAM_UHS_Public_Macros
+ * @{
+ */
+
+/*@} end of group PSRAM_UHS_Public_Macros */
+
+/** @defgroup PSRAM_UHS_Public_Functions
+ * @{
+ */
+void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg);
+int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal);
+int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg);
+int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd);
+void Psram_UHS_x16_Init(uint32_t uhs_pll_clk);
+void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg);
+/*@} end of group PSRAM_UHS_Public_Functions */
+
+/*@} end of group PSRAM_UHS */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_PSRAM_UHS_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_sdh.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_sdh.h
new file mode 100644
index 00000000..5eb0fc7e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_sdh.h
@@ -0,0 +1,978 @@
+/**
+ ******************************************************************************
+ * @file bl808_sdh.h
+ * @version V1.2
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2018 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_SDH_H__
+#define __BL808_SDH_H__
+
+#include "sdh_reg.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SDH
+ * @{
+ */
+
+/** @defgroup SDH_Public_Types
+ * @{
+ */
+
+/**
+ * @brief SDH status type definition
+ */
+typedef enum {
+ SDH_STAT_SUCCESS = 0, /*!< SDH status success */
+ SDH_STAT_BUSY, /*!< SDH status busy */
+ SDH_STAT_INVLAID_PARA, /*!< SDH status invalid parameter */
+ SDH_STAT_NOT_SUPPORT, /*!< SDH not support this feature */
+ SDH_STAT_OUTOF_RANGE, /*!< SDH out of range */
+ SDH_STAT_PREPARE_DESC, /*!< SDH status prepare ADMA descriptor */
+ SDH_STAT_SEND_CMD_FAIL, /*!< SDH status send command fail */
+ SDH_STAT_SEND_DATA_FAIL, /*!< SDH status send data fail */
+ SDH_STAT_RECV_DATA_FAIL, /*!< SDH status receive data fail */
+ SDH_STAT_DMA_ADDR_NOT_ALIGN, /*!< SDH status DMA address not align */
+ SDH_STAT_RETUNE_REQ, /*!< SDH status re-tune request */
+ SDH_STAT_TUNE_ERROR, /*!< SDH status tune error */
+} SDH_Stat_Type;
+
+/**
+ * @brief SDH capability type definition
+ */
+typedef enum {
+ SDH_CAP_SUPPORT_8BITS = 0x00000004, /*!< SDH support 8 bits */
+ SDH_CAP_SUPPORT_ADMA2 = 0x00000008, /*!< SDH support ADMA 2 */
+ SDH_CAP_SUPPORT_ADMA1 = 0x00000010, /*!< SDH support ADMA 1 */
+ SDH_CAP_SUPPORT_HIGHSPEED = 0x00000020, /*!< SDH support SDMA */
+ SDH_CAP_SUPPORT_SDMA = 0x00000040, /*!< SDH support high speed */
+ SDH_CAP_SUPPORT_SUS_RES = 0x00000080, /*!< SDH support suspend and resume */
+ SDH_CAP_SUPPORT_VLT33 = 0x00000100, /*!< SDH support voltgae 3.3V */
+ SDH_CAP_SUPPORT_VLT30 = 0x00000200, /*!< SDH support voltage 3.0V */
+ SDH_CAP_SUPPORT_VLT18 = 0x00000400, /*!< SDH support voltage 1.8V */
+ SDH_CAP_SUPPORT_SBUS_64BITS = 0x00001000, /*!< SDH support system bus 64 bits */
+ SDH_CAP_SUPPORT_ASYNC_INT = 0x00002000, /*!< SDH support async interrupt */
+ SDH_CAP_SUPPORT_DDR50 = 0x00010000, /*!< SDH support DDR 50MHz */
+ SDH_CAP_SUPPORT_SDR104 = 0x00020000, /*!< SDH support SDR 104MHz */
+ SDH_CAP_SUPPORT_SDR50 = 0x00040000, /*!< SDH support SDR 50MHz */
+ SDH_CAP_SUPPORT_DRV_TYPE_A = 0x00100000, /*!< SDH support driver type C */
+ SDH_CAP_SUPPORT_DRV_TYPE_C = 0x00200000, /*!< SDH support driver type A */
+ SDH_CAP_SUPPORT_DRV_TYPE_D = 0x00400000, /*!< SDH support driver type A */
+ SDH_CAP_SUPPORT_SDR50_TUNE = 0x20000000, /*!< SDH support SDR 50MHz tuning */
+} SDH_Cap_Support_Type;
+
+/**
+ * @brief SDH wakeup event type definition
+ */
+typedef enum {
+ SDH_WAKEUP_EVENT_INT, /*!< Wakeup on card interrupt */
+ SDH_WAKEUP_EVENT_INSERT, /*!< Wakeup on card insertion */
+ SDH_WAKEUP_EVENT_REMOVE, /*!< Wakeup on card remove */
+} SDH_Wakeup_Event_Type;
+
+/**
+ * @brief SDH trnasfer flag type definition
+ */
+typedef enum {
+ SDH_TRANS_FLAG_NONE = 0x00000000,
+ SDH_TRANS_FLAG_EN_DMA = 0x00000001, /*!< Enable DMA */
+ SDH_TRANS_FLAG_EN_BLK_COUNT = 0x00000002, /*!< Enable block count */
+ SDH_TRANS_FLAG_EN_AUTO_CMD12 = 0x00000004, /*!< Enable auto CMD12 */
+ SDH_TRANS_FLAG_EN_AUTO_CMD23 = 0x00000008, /*!< Enable auto CMD23 */
+ SDH_TRANS_FLAG_READ_DATA = 0x00000010, /*!< Enable read data */
+ SDH_TRANS_FLAG_MULTI_BLK = 0x00000020, /*!< Enable multi-block data operation */
+ SDH_TRANS_FLAG_RESP_136BITS = 0x00010000, /*!< Response is 136 bits length */
+ SDH_TRANS_FLAG_RESP_48BITS = 0x00020000, /*!< Response is 48 bits length */
+ SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY = 0x00030000, /*!< Response is 48 bits length with busy status */
+ SDH_TRANS_FLAG_EN_CRC_CHECK = 0x00080000, /*!< Enable CRC check */
+ SDH_TRANS_FLAG_EN_INDEX_CHECK = 0x00100000, /*!< Enable index check */
+ SDH_TRANS_FLAG_DATA_PRESENT = 0x00200000, /*!< Data present */
+ SDH_TRANS_FLAG_SUSPEND = 0x00400000, /*!< Suspend command */
+ SDH_TRANS_FLAG_RESUME = 0x00800000, /*!< Resume command */
+ SDH_TRANS_FLAG_ABORT = 0x00C00000, /*!< Abort command */
+} SDH_Trans_Flag_Type;
+
+/**
+ * @brief SDH present flag type definition
+ */
+typedef enum {
+ SDH_PRESENT_FLAG_CMD_INHBIT = 0x00000001, /*!< Command inhbit */
+ SDH_PRESENT_FLAG_DATA_INHBIT = 0x00000002, /*!< Data inhbit */
+ SDH_PRESENT_FLAG_DATA_LINE_ACTIVE = 0x00000004, /*!< Data line active */
+ SDH_PRESENT_FLAG_RETUNE_REQ = 0x00000008, /*!< Retuning request */
+ SDH_PRESENT_FLAG_TX_ACTIVE = 0x00000100, /*!< Write trnasfer atcive */
+ SDH_PRESENT_FLAG_RX_ACTIVE = 0x00000200, /*!< Read transfer active */
+ SDH_PRESENT_FLAG_BUF_WRITE_ENABLE = 0x00000400, /*!< Buffer write enabled */
+ SDH_PRESENT_FLAG_BUF_READ_ENABLE = 0x00000800, /*!< Buffer read enabled */
+ SDH_PRESENT_FLAG_CARD_INSERT = 0x00010000, /*!< Card intert */
+ SDH_PRESENT_FLAG_CARD_STABLE = 0x00020000, /*!< Card stable */
+ SDH_PRESENT_FLAG_CARD_DET = 0x00040000, /*!< Card detect */
+ SDH_PRESENT_FLAG_CARD_WP = 0x00080000, /*!< Card write protect */
+ SDH_PRESENT_FLAG_DATA0_LINE_LEVEL = 0x00100000, /*!< Data 0 line signal level */
+ SDH_PRESENT_FLAG_DATA1_LINE_LEVEL = 0x00200000, /*!< Data 1 line signal level */
+ SDH_PRESENT_FLAG_DATA2_LINE_LEVEL = 0x00400000, /*!< Data 2 line signal level */
+ SDH_PRESENT_FLAG_DATA3_LINE_LEVEL = 0x00800000, /*!< Data 3 line signal level */
+ SDH_PRESENT_FLAG_CMD_LINE_LEVEL = 0x01000000, /*!< Command line signal level */
+} SDH_Present_Flag_Type;
+
+/**
+ * @brief SDH interrupt type definition
+ */
+#define SDH_INT_CMD_COMPLETED ((uint32_t)(0x00000001)) /*!< SDH command complete interrupt */
+#define SDH_INT_DATA_COMPLETED ((uint32_t)(0x00000002)) /*!< SDH data complete interrupt */
+#define SDH_INT_BLK_GAP_EVENT ((uint32_t)(0x00000004)) /*!< SDH block gap event interrupt */
+#define SDH_INT_DMA_COMPLETED ((uint32_t)(0x00000008)) /*!< SDH DMA complete interrupt */
+#define SDH_INT_BUFFER_WRITE_READY ((uint32_t)(0x00000010)) /*!< SDH buffer write ready interrupt */
+#define SDH_INT_BUFFER_READ_READY ((uint32_t)(0x00000020)) /*!< SDH buffer read ready interrupt */
+#define SDH_INT_CARD_INSERT ((uint32_t)(0x00000040)) /*!< SDH card insert interrupt */
+#define SDH_INT_CARD_REMOVE ((uint32_t)(0x00000080)) /*!< SDH card remove interrupt */
+#define SDH_INT_CARD ((uint32_t)(0x00000100)) /*!< SDH card produce interrupt */
+#define SDH_INT_DRIVER_TA ((uint32_t)(0x00000200)) /*!< SDH driver type A interrupt */
+#define SDH_INT_DRIVER_TB ((uint32_t)(0x00000400)) /*!< SDH driver type B interrupt */
+#define SDH_INT_DRIVER_TC ((uint32_t)(0x00000800)) /*!< SDH driver type C interrupt */
+#define SDH_INT_RETUNE_EVENT ((uint32_t)(0x00001000)) /*!< SDH re-tuning event interrupt */
+#define SDH_INT_CMD_TIMEOUT ((uint32_t)(0x00010000)) /*!< SDH command timeout interrupt */
+#define SDH_INT_CMD_CRC_ERROR ((uint32_t)(0x00020000)) /*!< SDH command CRC error interrupt */
+#define SDH_INT_CMD_ENDBIT_ERROR ((uint32_t)(0x00040000)) /*!< SDH command endbit error interrupt */
+#define SDH_INT_CMD_INDEX_ERROR ((uint32_t)(0x00080000)) /*!< SDH command index error interrupt */
+#define SDH_INT_DATA_TIMEOUT ((uint32_t)(0x00100000)) /*!< SDH data timeout interrupt */
+#define SDH_INT_DATA_CRC_ERROR ((uint32_t)(0x00200000)) /*!< SDH data CRC error interrupt */
+#define SDH_INT_DATA_ENDBIT_ERROR ((uint32_t)(0x00400000)) /*!< SDH data endbit error interrupt */
+#define SDH_INT_CURRENT_ERROR ((uint32_t)(0x00800000)) /*!< SDH current error interrupt */
+#define SDH_INT_AUTO_CMD12_ERROR ((uint32_t)(0x01000000)) /*!< SDH auto command12 error */
+#define SDH_INT_DMA_ERROR ((uint32_t)(0x02000000)) /*!< SDH DMA error interrupt */
+#define SDH_INT_TUNE_ERROR ((uint32_t)(0x04000000)) /*!< SDH tuning maybe fail,this bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure */
+#define SDH_INT_SPI_ERROR ((uint32_t)(0x10000000)) /*!< SDH SPI mode error,read field in the SPI mode register */
+#define SDH_INT_AXI_RESP_ERROR ((uint32_t)(0x20000000)) /*!< SDH AXI bus response error */
+#define SDH_INT_CPL_TIMEOUT_ERROR ((uint32_t)(0x40000000)) /*!< SDH command completion signal timeout error,this field is applicable for CE-ATA mode only */
+#define SDH_INT_CRC_STAT_ERROR ((uint32_t)(0x80000000)) /*!< SDH CRC status start bit or CRC status end bit or boot ack status, returned from the card in write transaction has errors */
+#define SDH_INT_CMD_ERRORS ((uint32_t)(0x000f0000)) /*!< SDH all command errors */
+#define SDH_INT_DATA_ERRORS ((uint32_t)(0x01700000)) /*!< SDH all data errors */
+#define SDH_INT_ALL ((uint32_t)(0xffffffff)) /*!< SDH all interrupt */
+
+/**
+ * @brief SDH boot mode type definition
+ */
+typedef enum {
+ SDH_BOOT_MODE_NORMAL, /*!< SDH normal boot mode */
+ SDH_BOOT_MODE_ALT, /*!< SDH alternative boot mode */
+} SDH_Boot_Mode_Type;
+
+/**
+ * @brief SDH auto command 12 error status type definition
+ */
+typedef enum {
+ SDH_AUTO_CMD12_ERR_NOT_EXE, /*!< SDH auto command not execute error */
+ SDH_AUTO_CMD12_ERR_TIMEOUT, /*!< SDH auto command timeout error */
+ SDH_AUTO_CMD12_ERR_ENDBIT, /*!< SDH auto command endbit error */
+ SDH_AUTO_CMD12_ERR_INDEX, /*!< SDH auto command index error */
+ SDH_AUTO_CMD12_ERR_CRC, /*!< SDH auto command CRC error */
+ SDH_AUTO_CMD12_ERR_NOT_ISSUE, /*!< SDH auto command not issue error */
+} SDH_AUTO_CMD12_ERR_Type;
+
+/**
+ * @brief SDH ADMA error type definition
+ */
+typedef enum {
+ SDH_ADMA_ERR_LEN_MISMATCH, /*!< SDH ADMA length mismatch */
+ SDH_ADMA_ERR_DESC_ERROR, /*!< SDH ADMA descriptor error */
+} SDH_ADMA_ERR_Type;
+
+/**
+ * @brief SDH ADMA error status type definition
+ */
+typedef enum {
+ SDH_ADMA_ERR_STAT_STOP_DMA, /*!< SDH ADMA stop */
+ SDH_ADMA_ERR_STAT_FETCH_DESC, /*!< SDH ADMA fetch descriptor */
+ SDH_ADMA_ERR_STAT_CHANGE_ADDR, /*!< SDH ADMA change address */
+ SDH_ADMA_ERR_STAT_TRANS_DATA, /*!< SDH ADMA transfer data */
+ SDH_ADMA_ERR_STAT_INVALID_LEN, /*!< SDH ADMA invalid length */
+ SDH_ADMA_ERR_STAT_INVALID_DESC, /*!< SDH ADMA invalid descriptor */
+} SDH_ADMA_ERR_Stat_Type;
+
+/**
+ * @brief SDH force event type definition
+ */
+typedef enum {
+ SDH_FORCE_EVENT_AUTO_CMD12_NOT_EXE, /*!< SDH force event auto command 12 not executed */
+ SDH_FORCE_EVENT_AUTO_CMD12_TIMEOUT, /*!< SDH force event auto command 12 timeout */
+ SDH_FORCE_EVENT_AUTO_CMD12_CRC_ERROR, /*!< SDH force event auto command 12 crc error */
+ SDH_FORCE_EVENT_AUTO_CMD12_INDEX_ERROR, /*!< SDH force event auto command 12 index error */
+ SDH_FORCE_EVENT_AUTO_CMD12_NOT_ISSUE, /*!< SDH force event auto command 12 not issue */
+ SDH_FORCE_EVENT_ENDBIT_ERROR, /*!< SDH force event end bit error */
+ SDH_FORCE_EVENT_CMD_TIMEOUT, /*!< SDH force event command timeout */
+ SDH_FORCE_EVENT_CMD_CRC_ERROR, /*!< SDH force event command crc error */
+ SDH_FORCE_EVENT_CMD_ENDBIT_ERROR, /*!< SDH force event command end bit error */
+ SDH_FORCE_EVENT_CMD_INDEX_ERROR, /*!< SDH force event command index error */
+ SDH_FORCE_EVENT_DATA_TIMEOUT, /*!< SDH force event data timeout */
+ SDH_FORCE_EVENT_DATA_CRC_ERROR, /*!< SDH force event data crc error */
+ SDH_FORCE_EVENT_DATA_ENDBIT_ERROR, /*!< SDH force event data end bit error */
+ SDH_FORCE_EVENT_DATA_INDEX_ERROR, /*!< SDH force event data index error */
+ SDH_FORCE_EVENT_AUTO_CMD12_ERROR, /*!< SDH force event auto command 12 error */
+ SDH_FORCE_EVENT_CARD_INT, /*!< SDH force event card interrupt */
+ SDH_FORCE_EVENT_DMA_ERROR, /*!< SDH force event DMA error */
+} SDH_Force_Event_Type;
+
+/**
+ * @brief SDH speed mode type definition
+ */
+typedef enum {
+ SDH_SPEED_MODE_SDR12, /*!< SDH speed :12.5MHZ */
+ SDH_SPEED_MODE_SDR25, /*!< SDH speed :25MHZ */
+ SDH_SPEED_MODE_SDR50, /*!< SDH speed :50MHZ */
+ SDH_SPEED_MODE_SDR104, /*!< SDH speed :104MHZ */
+ SDH_SPEED_MODE_DDR50, /*!< SDH speed :50MHZ (DDR mode) */
+} SDH_Speed_Mode_Type;
+
+/**
+ * @brief SDH data bus width type definition
+ */
+typedef enum {
+ SDH_DATA_BUS_WIDTH_1BIT, /*!< SDH data bus width 1 bit */
+ SDH_DATA_BUS_WIDTH_4BITS, /*!< SDH data bus width 4 bits */
+ SDH_DATA_BUS_WIDTH_8BITS, /*!< SDH data bus width 8 bits */
+} SDH_Data_Bus_Width_Type;
+
+/**
+ * @brief SDH voltage type definition
+ */
+typedef enum {
+ SDH_VOLTAGE_3P3V = 0x07, /*!< SDH voltage 3.3V */
+ SDH_VOLTAGE_3P0V = 0x06, /*!< SDH voltage 3.0V */
+ SDH_VOLTAGE_1P8V = 0x05, /*!< SDH voltage 1.8V */
+} SDH_Voltage_Type;
+
+/**
+ * @brief SDH DMA mode type definition
+ */
+typedef enum {
+ SDH_DMA_MODE_SIMPLE, /*!< SDH DMA mode:simple */
+ SDH_DMA_MODE_ADMA1, /*!< SDH DMA mode:ADMA1 */
+ SDH_DMA_MODE_ADMA2, /*!< SDH DMA mode:ADMA2 */
+} SDH_DMA_Mode_Type;
+
+/**
+ * @brief SDH control flag type definition
+ */
+typedef enum {
+ SDH_CTRL_FLAG_STOP_AT_BLK_GAP, /*!< SDH control flag: stop at block gap */
+ SDH_CTRL_FLAG_READ_WAIT, /*!< SDH control flag: read wait */
+ SDH_CTRL_FLAG_INT_AT_BLK_GAP, /*!< SDH control flag: interrupt at block gap */
+ SDH_CTRL_FLAG_RAED_DONE_WITHOUT_8CLKS, /*!< SDH control flag: read done without 8 clks for block gap */
+ SDH_CTRL_FLAG_EXACT_BLK_NUM_READ, /*!< SDH control flag: Exact block number read */
+} SDH_Ctrl_Flag_Type;
+
+/**
+ * @brief SDH Command type definition
+ */
+typedef enum {
+ SDH_CMD_NORMAL, /*!< SDH command type:normal */
+ SDH_CMD_SUSPEND, /*!< SDH command type:suspend */
+ SDH_CMD_RESUME, /*!< SDH command type:resume */
+ SDH_CMD_ABORT, /*!< SDH command type:abort */
+ SDH_CMD_EMPTY, /*!< SDH command type:empty */
+} SDH_Cmd_Type;
+
+/**
+ * @brief SDH response type definition
+ */
+typedef enum {
+ SDH_RESP_NONE, /*!< SDH response type:none */
+ SDH_RESP_136LEN,
+ SDH_RESP_48LEN,
+ SDH_RESP_48LEN_BUSY,
+ SDH_RESP_R1, /*!< SDH response type:r1 */
+ SDH_RESP_R1B, /*!< SDH response type:r1b */
+ SDH_RESP_R2, /*!< SDH response type:r2 */
+ SDH_RESP_R3, /*!< SDH response type:r3 */
+ SDH_RESP_R4, /*!< SDH response type:r4 */
+ SDH_RESP_R5, /*!< SDH response type:r5 */
+ SDH_RESP_R5B, /*!< SDH response type:r5b */
+ SDH_RESP_R6, /*!< SDH response type:r6 */
+ SDH_RESP_R7, /*!< SDH response type:r7 */
+} SDH_Resp_Type;
+
+/**
+ * @brief SDH ADMA descriptor chain type definition
+ */
+typedef enum {
+ SDH_ADMA_FLAG_SINGLE_DESC, /*!< SDH transfer a single ADMA descriptor */
+ SDH_ADMA_FLAG_MULTI_DESC, /*!< SDH create multiple ADMA descriptor within the ADMA table(mmc boot mode) */
+} SDH_ADMA_Flag_Type;
+
+/**
+ * @brief SDH ADMA1 descriptor flag type definition
+ */
+typedef enum {
+ SDH_ADMA1_DESC_FLAG_VALID = 0X01, /*!< SDH ADMA1 descriptor valid flag */
+ SDH_ADMA1_DESC_FLAG_END = 0X02, /*!< SDH ADMA1 descriptor end flag */
+ SDH_ADMA1_DESC_FLAG_INT = 0X04, /*!< SDH ADMA1 descriptor interrupt flag */
+ SDH_ADMA1_DESC_FLAG_ACTIVE1 = 0X10, /*!< SDH ADMA1 descriptor atcive1 flag */
+ SDH_ADMA1_DESC_FLAG_ACTIVE2 = 0X20, /*!< SDH ADMA1 descriptor active2 flag */
+ SDH_ADMA1_DESC_FLAG_TRANSFER = 0x21, /*!< SDH ADMA1 trnasfer descriptor flag\ */
+ SDH_ADMA1_DESC_FLAG_LINK = 0x31, /*!< SDH ADMA1 link descriptor flag */
+ SDH_ADMA1_DESC_FLAG_SETLEN = 0x11, /*!< SDH ADMA1 set length descriptor flag */
+} SDH_ADMA1_Desc_Flag_Type;
+
+/**
+ * @brief SDH ADMA2 descriptor flag type definition
+ */
+typedef enum {
+ SDH_ADMA2_DESC_FLAG_VALID = 0X01, /*!< SDH ADMA2 descriptor valid flag */
+ SDH_ADMA2_DESC_FLAG_END = 0X02, /*!< SDH ADMA2 descriptor end flag */
+ SDH_ADMA2_DESC_FLAG_INT = 0X04, /*!< SDH ADMA2 descriptor interrupt flag */
+ SDH_ADMA2_DESC_FLAG_ACTIVE1 = 0X10, /*!< SDH ADMA2 descriptor atcive1 flag */
+ SDH_ADMA2_DESC_FLAG_ACTIVE2 = 0X20, /*!< SDH ADMA2 descriptor active2 flag */
+ SDH_ADMA2_DESC_FLAG_TRANSFER = 0x21, /*!< SDH ADMA2 trnasfer descriptor flag\ */
+ SDH_ADMA2_DESC_FLAG_LINK = 0x31, /*!< SDH ADMA2 link descriptor flag */
+} SDH_ADMA2_Desc_Flag_Type;
+
+/**
+ * @brief SDH burst length type definition
+ */
+typedef enum {
+ SDH_BUSRT_INCR, /*!< SDH burst length incremental */
+ SDH_BUSRT_INCR4, /*!< SDH ADMA2 length INCR4 */
+ SDH_BUSRT_WRAP4, /*!< SDH ADMA2 length Wrap 4 */
+} SDH_Burst_Type;
+
+/**
+ * @brief SDH FIFO threshold type definition
+ */
+typedef enum {
+ SDH_FIFO_THRESHOLD_64_BYTES, /*!< SDH FIFO threshold is 64 bytes to generate DMA request */
+ SDH_FIFO_THRESHOLD_128_BYTES, /*!< SDH FIFO threshold is 128 bytes to generate DMA request */
+ SDH_FIFO_THRESHOLD_192_BYTES, /*!< SDH FIFO threshold is 192 bytes to generate DMA request */
+ SDH_FIFO_THRESHOLD_256_BYTES, /*!< SDH FIFO threshold is 256 bytes to generate DMA request */
+} SDH_FIFO_Threshold_Type;
+
+/**
+ * @brief SDH burst length type definition
+ */
+typedef enum {
+ SDH_BURST_SIZE_32_BYTES, /*!< SDH busrt size is 32 bytes */
+ SDH_BURST_SIZE_64_BYTES, /*!< SDH busrt size is 64 bytes */
+ SDH_BURST_SIZE_128_BYTES, /*!< SDH busrt size is 128 bytes */
+ SDH_BURST_SIZE_256_BYTES, /*!< SDH busrt size is 256 bytes */
+} SDH_Burst_Size_Type;
+
+/**
+ * @brief SDH transferd data type definition
+ */
+typedef enum {
+ SDH_TRANS_DATA_NORMAL, /*!< SDH transfer normal data */
+ SDH_TRANS_DATA_TUNING, /*!< SDH transfer tuning data */
+ SDH_TRANS_DATA_BOOT, /*!< SDH transfer boot data */
+ SDH_TRANS_DATA_BOOT_CONT, /*!< SDH transfer boot data continous */
+} SDH_Trans_Data_Type;
+
+/**
+ * @brief SDH ADMA2 descriptor structure type definition
+ */
+typedef struct
+{
+ uint32_t attribute; /*!< SDH ADMA2 descriptor attribute */
+ uint32_t address; /*!< SDH ADMA2 descriptor address pointer */
+} SDH_ADMA2_Desc_Type;
+/**
+ * @brief SDH capability structure type definition
+ */
+typedef struct
+{
+ uint32_t sdVersion; /*!< SDH support SD card/sdio version */
+ uint32_t mmcVersion; /*!< SDH support emmc card version */
+ uint32_t maxBlockLength; /*!< SDH maximum block length united as byte */
+ uint32_t maxBlockCount; /*!< SDH maximum block count can be set one time */
+ uint32_t flags; /*!< SDH capability flags to indicate the support information */
+} SDH_Cap_Cfg_Type;
+
+/**
+ * @brief SDH boot config structure type definition
+ */
+typedef struct
+{
+ uint32_t ackTimeoutCount; /*!< SDH timeout value for the boot ACK. The available range is 0 ~ 15 */
+ SDH_Boot_Mode_Type bootMode; /*!< SDH boot mode selection */
+ uint32_t blockCount; /*!< SDH stop at block gap value of automatic mode. Available range is 0 ~ 65535 */
+ uint32_t blockSize; /*!< SDH block size */
+ uint8_t enableBootAck; /*!< SDH enable or disable boot ACK */
+ uint8_t enableAutoStopAtBlockGap; /*!< SDH enable or disable auto stop at block gap function in boot period */
+} SDH_Boot_Cfg_Type;
+
+/**
+ * @brief SDH config structure type definition
+ */
+typedef struct
+{
+ SDH_Speed_Mode_Type speed; /*!< SDH host controller speed */
+ BL_Fun_Type vlot18Enable; /*!< SDH enable 1.8V */
+ BL_Fun_Type highSpeed; /*!< SDH enable high speed */
+ SDH_Data_Bus_Width_Type dataWidth; /*!< SDH data bus width */
+ SDH_Voltage_Type volt; /*!< SDH voltage */
+ uint32_t srcClock; /*!< SDH source clock frequency in HZ */
+ uint32_t busClock; /*!< SDH bus clock frequency in HZ */
+ uint32_t dataTimeout; /*!< SDH data timeout value */
+ uint8_t readWatermarkLevel; /*!< SDH watermark level for DMA read operation. Available range is 1 ~ 128. */
+ uint8_t writeWatermarkLevel; /*!< SDH watermark level for DMA write operation. Available range is 1 ~ 128. */
+ uint8_t readBurstLen; /*!< SDH read burst len */
+ uint8_t writeBurstLen; /*!< SDH write burst len */
+} SDH_Cfg_Type;
+
+/**
+ * @brief SDH config structure type definition
+ */
+typedef struct
+{
+ BL_Fun_Type enableAutoCommand12; /*!< SDH enable auto CMD12 */
+ BL_Fun_Type enableAutoCommand23; /*!< SDH enable auto CMD23 */
+ BL_Fun_Type enableIgnoreError; /*!< SDH enable to ignore error event to read/write all the data */
+ SDH_Trans_Data_Type dataType; /*!< SDH this is used to distinguish the normal/tuning/boot data */
+ uint32_t blockSize; /*!< SDH block size */
+ uint32_t blockCount; /*!< SDH block count */
+ uint32_t rxDataLen; /*!< SDH RX data length */
+ uint32_t *rxData; /*!< SDH buffer to save data read */
+ const uint32_t *txData; /*!< SDH data buffer to write */
+ uint32_t txDataLen; /*!< SDH TX data length */
+} SDH_Data_Cfg_Type;
+
+/**
+ * @brief SDH command config structure type definition
+ */
+typedef struct
+{
+ uint32_t index; /*!< SDH command index */
+ uint32_t argument; /*!< SDH command argument */
+ SDH_Cmd_Type type; /*!< SDH command type */
+ SDH_Resp_Type respType; /*!< SDH command response type */
+ uint32_t response[4U]; /*!< SDH response for this command */
+ uint32_t flag; /*!< SDH cmd flag */
+} SDH_CMD_Cfg_Type;
+
+/**
+ * @brief SDH DMA config structure type definition
+ */
+typedef struct
+{
+ SDH_DMA_Mode_Type dmaMode; /*!< SDH DMA mode */
+ //SDH_Burst_Type burstType; /*!< SDH burst type config */
+ SDH_Burst_Size_Type burstSize; /*!< SDH DMA burst size type */
+ SDH_FIFO_Threshold_Type fifoThreshold; /*!< SDH FIFO threshold */
+ uint32_t *admaEntries; /*!< SDH ADMA table entries address */
+ uint32_t maxEntries; /*!< SDH ADMA table entries size */
+} SDH_DMA_Cfg_Type;
+
+/**
+ * @brief SDH transfer config structure type definition
+ */
+typedef struct
+{
+ SDH_Data_Cfg_Type *dataCfg; /*!< SDH data config */
+ SDH_CMD_Cfg_Type *cmdCfg; /*!< SDH command config */
+} SDH_Trans_Cfg_Type;
+
+typedef struct SDH_Handle_Cfg_Tag SDH_Handle_Cfg_Type;
+
+/**
+ * @brief SDH transfer callback function config structure type definition
+ */
+typedef struct
+{
+ void (*SDH_CallBack_CardInserted)(void *userData); /*!< SDH card inserted occurs when DAT3/CD pin is for card detect */
+ void (*SDH_CallBack_CardRemoved)(void *userData); /*!< SDH card removed occurs */
+ void (*SDH_CallBack_SdioInterrupt)(void *userData); /*!< SDH SDIO card interrupt occurs */
+ void (*SDH_CallBack_BlockGap)(void *userData); /*!< SDH stopped at block gap event */
+ void (*SDH_CallBack_TransferFinished)(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData); /*!< SDH transfer complete callback */
+ void (*SDH_CMDCallBack_TransferFinished)(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData); /*!< SDH transfer complete callback */
+ void (*SDH_CallBack_ReTuning)(void *userData); /*!< SDH handle the re-tuning */
+ void (*SDH_CallBack_Vendor)(void *userData); /*!< SDH handle vendor specified interrupt callback */
+} SDH_Trans_Callback_Cfg_Type;
+
+struct SDH_Handle_Cfg_Tag {
+ SDH_Data_Cfg_Type *dataCfg; /*!< SDH data config to transfer */
+ SDH_CMD_Cfg_Type *cmdCfg; /*!< SDH command config to transfer */
+ uint32_t intFlag; /*!< SDH interrupt flags of last transaction */
+ SDH_Trans_Callback_Cfg_Type callBack; /*!< SDH callback function */
+ void *userData; /*!< SDH parameter for transfer complete callback */
+};
+
+/*@} end of group SDH_Public_Types */
+
+/** @defgroup SDH_Public_Constants
+ * @{
+ */
+
+/** @defgroup SDH_STAT_TYPE
+ * @{
+ */
+#define IS_SDH_STAT_TYPE(type) (((type) == SDH_STAT_SUCCESS) || \
+ ((type) == SDH_STAT_BUSY) || \
+ ((type) == SDH_STAT_INVLAID_PARA) || \
+ ((type) == SDH_STAT_NOT_SUPPORT) || \
+ ((type) == SDH_STAT_OUTOF_RANGE) || \
+ ((type) == SDH_STAT_PREPARE_DESC) || \
+ ((type) == SDH_STAT_SEND_CMD_FAIL) || \
+ ((type) == SDH_STAT_SEND_DATA_FAIL) || \
+ ((type) == SDH_STAT_RECV_DATA_FAIL) || \
+ ((type) == SDH_STAT_DMA_ADDR_NOT_ALIGN) || \
+ ((type) == SDH_STAT_RETUNE_REQ) || \
+ ((type) == SDH_STAT_TUNE_ERROR))
+
+/** @defgroup SDH_CAP_SUPPORT_TYPE
+ * @{
+ */
+#define IS_SDH_CAP_SUPPORT_TYPE(type) (((type) == SDH_CAP_SUPPORT_8BITS) || \
+ ((type) == SDH_CAP_SUPPORT_ADMA2) || \
+ ((type) == SDH_CAP_SUPPORT_ADMA1) || \
+ ((type) == SDH_CAP_SUPPORT_HIGHSPEED) || \
+ ((type) == SDH_CAP_SUPPORT_SDMA) || \
+ ((type) == SDH_CAP_SUPPORT_SUS_RES) || \
+ ((type) == SDH_CAP_SUPPORT_VLT33) || \
+ ((type) == SDH_CAP_SUPPORT_VLT30) || \
+ ((type) == SDH_CAP_SUPPORT_VLT18) || \
+ ((type) == SDH_CAP_SUPPORT_SBUS_64BITS) || \
+ ((type) == SDH_CAP_SUPPORT_ASYNC_INT) || \
+ ((type) == SDH_CAP_SUPPORT_DDR50) || \
+ ((type) == SDH_CAP_SUPPORT_SDR104) || \
+ ((type) == SDH_CAP_SUPPORT_SDR50) || \
+ ((type) == SDH_CAP_SUPPORT_DRV_TYPE_A) || \
+ ((type) == SDH_CAP_SUPPORT_DRV_TYPE_C) || \
+ ((type) == SDH_CAP_SUPPORT_DRV_TYPE_D) || \
+ ((type) == SDH_CAP_SUPPORT_SDR50_TUNE))
+
+/** @defgroup SDH_WAKEUP_EVENT_TYPE
+ * @{
+ */
+#define IS_SDH_WAKEUP_EVENT_TYPE(type) (((type) == SDH_WAKEUP_EVENT_INT) || \
+ ((type) == SDH_WAKEUP_EVENT_INSERT) || \
+ ((type) == SDH_WAKEUP_EVENT_REMOVE))
+
+/** @defgroup SDH_TRANS_FLAG_TYPE
+ * @{
+ */
+#define IS_SDH_TRANS_FLAG_TYPE(type) (((type) == SDH_TRANS_FLAG_EN_DMA) || \
+ ((type) == SDH_TRANS_FLAG_EN_BLK_COUNT) || \
+ ((type) == SDH_TRANS_FLAG_EN_AUTO_CMD12) || \
+ ((type) == SDH_TRANS_FLAG_EN_AUTO_CMD23) || \
+ ((type) == SDH_TRANS_FLAG_READ_DATA) || \
+ ((type) == SDH_TRANS_FLAG_MULTI_BLK) || \
+ ((type) == SDH_TRANS_FLAG_RESP_136BITS) || \
+ ((type) == SDH_TRANS_FLAG_RESP_48BITS) || \
+ ((type) == SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY) || \
+ ((type) == SDH_TRANS_FLAG_EN_CRC_CHECK) || \
+ ((type) == SDH_TRANS_FLAG_EN_INDEX_CHECK) || \
+ ((type) == SDH_TRANS_FLAG_DATA_PRESENT) || \
+ ((type) == SDH_TRANS_FLAG_SUSPEND) || \
+ ((type) == SDH_TRANS_FLAG_RESUME) || \
+ ((type) == SDH_TRANS_FLAG_ABORT))
+
+/** @defgroup SDH_PRESENT_FLAG_TYPE
+ * @{
+ */
+#define IS_SDH_PRESENT_FLAG_TYPE(type) (((type) == SDH_PRESENT_FLAG_CMD_INHBIT) || \
+ ((type) == SDH_PRESENT_FLAG_DATA_INHBIT) || \
+ ((type) == SDH_PRESENT_FLAG_DATA_LINE_ACTIVE) || \
+ ((type) == SDH_PRESENT_FLAG_RETUNE_REQ) || \
+ ((type) == SDH_PRESENT_FLAG_TX_ACTIVE) || \
+ ((type) == SDH_PRESENT_FLAG_RX_ACTIVE) || \
+ ((type) == SDH_PRESENT_FLAG_BUF_WRITE_ENABLE) || \
+ ((type) == SDH_PRESENT_FLAG_BUF_READ_ENABLE) || \
+ ((type) == SDH_PRESENT_FLAG_CARD_INSERT) || \
+ ((type) == SDH_PRESENT_FLAG_CARD_STABLE) || \
+ ((type) == SDH_PRESENT_FLAG_CARD_DET) || \
+ ((type) == SDH_PRESENT_FLAG_CARD_WP) || \
+ ((type) == SDH_PRESENT_FLAG_DATA0_LINE_LEVEL) || \
+ ((type) == SDH_PRESENT_FLAG_DATA1_LINE_LEVEL) || \
+ ((type) == SDH_PRESENT_FLAG_DATA2_LINE_LEVEL) || \
+ ((type) == SDH_PRESENT_FLAG_DATA3_LINE_LEVEL) || \
+ ((type) == SDH_PRESENT_FLAG_CMD_LINE_LEVEL))
+
+/** @defgroup SDH_INT_TYPE
+ * @{
+ */
+#define IS_SDH_INT_TYPE(type) (((type) == SDH_INT_CMD_COMPLETED) || \
+ ((type) == SDH_INT_DATA_COMPLETED) || \
+ ((type) == SDH_INT_BLK_GAP_EVENT) || \
+ ((type) == SDH_INT_DMA_COMPLETED) || \
+ ((type) == SDH_INT_BUFFER_WRITE_READY) || \
+ ((type) == SDH_INT_BUFFER_READ_READY) || \
+ ((type) == SDH_INT_CARD_INSERT) || \
+ ((type) == SDH_INT_CARD_REMOVE) || \
+ ((type) == SDH_INT_CARD) || \
+ ((type) == SDH_INT_DRIVER_TA) || \
+ ((type) == SDH_INT_DRIVER_TB) || \
+ ((type) == SDH_INT_DRIVER_TC) || \
+ ((type) == SDH_INT_RETUNE_EVENT) || \
+ ((type) == SDH_INT_CMD_TIMEOUT) || \
+ ((type) == SDH_INT_CMD_CRC_ERROR) || \
+ ((type) == SDH_INT_CMD_ENDBIT_ERROR) || \
+ ((type) == SDH_INT_CMD_INDEX_ERROR) || \
+ ((type) == SDH_INT_DATA_TIMEOUT) || \
+ ((type) == SDH_INT_DATA_CRC_ERROR) || \
+ ((type) == SDH_INT_DATA_ENDBIT_ERROR) || \
+ ((type) == SDH_INT_CURRENT_ERROR) || \
+ ((type) == SDH_INT_AUTO_CMD12_ERROR) || \
+ ((type) == SDH_INT_DMA_ERROR) || \
+ ((type) == SDH_INT_TUNE_ERROR) || \
+ ((type) == SDH_INT_SPI_ERROR) || \
+ ((type) == SDH_INT_AXI_RESP_ERROR) || \
+ ((type) == SDH_INT_CPL_TIMEOUT_ERROR) || \
+ ((type) == SDH_INT_CRC_STAT_ERROR) || \
+ ((type) == SDH_INT_CMD_ERRORS) || \
+ ((type) == SDH_INT_DATA_ERRORS) || \
+ ((type) == SDH_INT_ALL))
+
+/** @defgroup SDH_BOOT_MODE_TYPE
+ * @{
+ */
+#define IS_SDH_BOOT_MODE_TYPE(type) (((type) == SDH_BOOT_MODE_NORMAL) || \
+ ((type) == SDH_BOOT_MODE_ALT))
+
+/** @defgroup SDH_AUTO_CMD12_ERR_TYPE
+ * @{
+ */
+#define IS_SDH_AUTO_CMD12_ERR_TYPE(type) (((type) == SDH_AUTO_CMD12_ERR_NOT_EXE) || \
+ ((type) == SDH_AUTO_CMD12_ERR_TIMEOUT) || \
+ ((type) == SDH_AUTO_CMD12_ERR_ENDBIT) || \
+ ((type) == SDH_AUTO_CMD12_ERR_INDEX) || \
+ ((type) == SDH_AUTO_CMD12_ERR_CRC) || \
+ ((type) == SDH_AUTO_CMD12_ERR_NOT_ISSUE))
+
+/** @defgroup SDH_ADMA_ERR_TYPE
+ * @{
+ */
+#define IS_SDH_ADMA_ERR_TYPE(type) (((type) == SDH_ADMA_ERR_LEN_MISMATCH) || \
+ ((type) == SDH_ADMA_ERR_DESC_ERROR))
+
+/** @defgroup SDH_ADMA_ERR_STAT_TYPE
+ * @{
+ */
+#define IS_SDH_ADMA_ERR_STAT_TYPE(type) (((type) == SDH_ADMA_ERR_STAT_STOP_DMA) || \
+ ((type) == SDH_ADMA_ERR_STAT_FETCH_DESC) || \
+ ((type) == SDH_ADMA_ERR_STAT_CHANGE_ADDR) || \
+ ((type) == SDH_ADMA_ERR_STAT_TRANS_DATA) || \
+ ((type) == SDH_ADMA_ERR_STAT_INVALID_LEN) || \
+ ((type) == SDH_ADMA_ERR_STAT_INVALID_DESC))
+
+/** @defgroup SDH_FORCE_EVENT_TYPE
+ * @{
+ */
+#define IS_SDH_FORCE_EVENT_TYPE(type) (((type) == SDH_FORCE_EVENT_AUTO_CMD12_NOT_EXE) || \
+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_TIMEOUT) || \
+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_CRC_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_INDEX_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_NOT_ISSUE) || \
+ ((type) == SDH_FORCE_EVENT_ENDBIT_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_CMD_TIMEOUT) || \
+ ((type) == SDH_FORCE_EVENT_CMD_CRC_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_CMD_ENDBIT_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_CMD_INDEX_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_DATA_TIMEOUT) || \
+ ((type) == SDH_FORCE_EVENT_DATA_CRC_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_DATA_ENDBIT_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_DATA_INDEX_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_ERROR) || \
+ ((type) == SDH_FORCE_EVENT_CARD_INT) || \
+ ((type) == SDH_FORCE_EVENT_DMA_ERROR))
+
+/** @defgroup SDH_SPEED_MODE_TYPE
+ * @{
+ */
+#define IS_SDH_SPEED_MODE_TYPE(type) (((type) == SDH_SPEED_MODE_SDR12) || \
+ ((type) == SDH_SPEED_MODE_SDR25) || \
+ ((type) == SDH_SPEED_MODE_SDR50) || \
+ ((type) == SDH_SPEED_MODE_SDR104) || \
+ ((type) == SDH_SPEED_MODE_DDR50))
+
+/** @defgroup SDH_DATA_BUS_WIDTH_TYPE
+ * @{
+ */
+#define IS_SDH_DATA_BUS_WIDTH_TYPE(type) (((type) == SDH_DATA_BUS_WIDTH_1BIT) || \
+ ((type) == SDH_DATA_BUS_WIDTH_4BITS) || \
+ ((type) == SDH_DATA_BUS_WIDTH_8BITS))
+
+/** @defgroup SDH_VOLTAGE_TYPE
+ * @{
+ */
+#define IS_SDH_VOLTAGE_TYPE(type) (((type) == SDH_VOLTAGE_3P3V) || \
+ ((type) == SDH_VOLTAGE_3P0V) || \
+ ((type) == SDH_VOLTAGE_1P8V))
+
+/** @defgroup SDH_DMA_MODE_TYPE
+ * @{
+ */
+#define IS_SDH_DMA_MODE_TYPE(type) (((type) == SDH_DMA_MODE_SIMPLE) || \
+ ((type) == SDH_DMA_MODE_ADMA1) || \
+ ((type) == SDH_DMA_MODE_ADMA2))
+
+/** @defgroup SDH_CTRL_FLAG_TYPE
+ * @{
+ */
+#define IS_SDH_CTRL_FLAG_TYPE(type) (((type) == SDH_CTRL_FLAG_STOP_AT_BLK_GAP) || \
+ ((type) == SDH_CTRL_FLAG_READ_WAIT) || \
+ ((type) == SDH_CTRL_FLAG_INT_AT_BLK_GAP) || \
+ ((type) == SDH_CTRL_FLAG_RAED_DONE_WITHOUT_8CLKS) || \
+ ((type) == SDH_CTRL_FLAG_EXACT_BLK_NUM_READ))
+
+/** @defgroup SDH_CMD_TYPE
+ * @{
+ */
+#define IS_SDH_CMD_TYPE(type) (((type) == SDH_CMD_NORMAL) || \
+ ((type) == SDH_CMD_SUSPEND) || \
+ ((type) == SDH_CMD_RESUME) || \
+ ((type) == SDH_CMD_ABORT) || \
+ ((type) == SDH_CMD_EMPTY))
+
+/** @defgroup SDH_RESP_TYPE
+ * @{
+ */
+#define IS_SDH_RESP_TYPE(type) (((type) == SDH_RESP_NONE) || \
+ ((type) == SDH_RESP_R1) || \
+ ((type) == SDH_RESP_R1B) || \
+ ((type) == SDH_RESP_R2) || \
+ ((type) == SDH_RESP_R3) || \
+ ((type) == SDH_RESP_R4) || \
+ ((type) == SDH_RESP_R5) || \
+ ((type) == SDH_RESP_R5B) || \
+ ((type) == SDH_RESP_R6) || \
+ ((type) == SDH_RESP_R7))
+
+/** @defgroup SDH_ADMA_FLAG_TYPE
+ * @{
+ */
+#define IS_SDH_ADMA_FLAG_TYPE(type) (((type) == SDH_ADMA_FLAG_SINGLE_DESC) || \
+ ((type) == SDH_ADMA_FLAG_MULTI_DESC))
+
+/** @defgroup SDH_ADMA1_DESC_FLAG_TYPE
+ * @{
+ */
+#define IS_SDH_ADMA1_DESC_FLAG_TYPE(type) (((type) == SDH_ADMA1_DESC_FLAG_VALID) || \
+ ((type) == SDH_ADMA1_DESC_FLAG_END) || \
+ ((type) == SDH_ADMA1_DESC_FLAG_INT) || \
+ ((type) == SDH_ADMA1_DESC_FLAG_ACTIVE1) || \
+ ((type) == SDH_ADMA1_DESC_FLAG_ACTIVE2) || \
+ ((type) == SDH_ADMA1_DESC_FLAG_TRANSFER) || \
+ ((type) == SDH_ADMA1_DESC_FLAG_LINK) || \
+ ((type) == SDH_ADMA1_DESC_FLAG_SETLEN))
+
+/** @defgroup SDH_ADMA2_DESC_FLAG_TYPE
+ * @{
+ */
+#define IS_SDH_ADMA2_DESC_FLAG_TYPE(type) (((type) == SDH_ADMA2_DESC_FLAG_VALID) || \
+ ((type) == SDH_ADMA2_DESC_FLAG_END) || \
+ ((type) == SDH_ADMA2_DESC_FLAG_INT) || \
+ ((type) == SDH_ADMA2_DESC_FLAG_ACTIVE1) || \
+ ((type) == SDH_ADMA2_DESC_FLAG_ACTIVE2) || \
+ ((type) == SDH_ADMA2_DESC_FLAG_TRANSFER) || \
+ ((type) == SDH_ADMA2_DESC_FLAG_LINK))
+
+/** @defgroup SDH_BURST_TYPE
+ * @{
+ */
+#define IS_SDH_BURST_TYPE(type) (((type) == SDH_BUSRT_INCR) || \
+ ((type) == SDH_BUSRT_INCR4) || \
+ ((type) == SDH_BUSRT_WRAP4))
+
+/** @defgroup SDH_FIFO_THRESHOLD_TYPE
+ * @{
+ */
+#define IS_SDH_FIFO_THRESHOLD_TYPE(type) (((type) == SDH_FIFO_THRESHOLD_64_BYTES) || \
+ ((type) == SDH_FIFO_THRESHOLD_128_BYTES) || \
+ ((type) == SDH_FIFO_THRESHOLD_192_BYTES) || \
+ ((type) == SDH_FIFO_THRESHOLD_256_BYTES))
+
+/** @defgroup SDH_BURST_SIZE_TYPE
+ * @{
+ */
+#define IS_SDH_BURST_SIZE_TYPE(type) (((type) == SDH_BURST_SIZE_32_BYTES) || \
+ ((type) == SDH_BURST_SIZE_64_BYTES) || \
+ ((type) == SDH_BURST_SIZE_128_BYTES) || \
+ ((type) == SDH_BURST_SIZE_256_BYTES))
+
+/** @defgroup SDH_TRANS_DATA_TYPE
+ * @{
+ */
+#define IS_SDH_TRANS_DATA_TYPE(type) (((type) == SDH_TRANS_DATA_NORMAL) || \
+ ((type) == SDH_TRANS_DATA_TUNING) || \
+ ((type) == SDH_TRANS_DATA_BOOT) || \
+ ((type) == SDH_TRANS_DATA_BOOT_CONT))
+
+/*@} end of group SDH_Public_Constants */
+
+/** @defgroup SDH_Public_Macros
+ * @{
+ */
+/* The alignment size for ADDRESS filed in SDMA */
+#define SDH_SDMA_ADDRESS_ALIGN (1U)
+/* The alignment size for LENGTH field in SDMA */
+#define SDH_SDMA_LENGTH_ALIGN (1U)
+/* The alignment size for ADDRESS filed in ADMA1's descriptor */
+#define SDH_ADMA1_ADDRESS_ALIGN (4096U)
+/* The alignment size for ADDRESS field in ADMA2's descriptor */
+#define SDH_ADMA2_ADDRESS_ALIGN (1U)
+/* The alignment size for LENGTH filed in ADMA2's descriptor */
+#define SDH_ADMA2_LENGTH_ALIGN (1U)
+/* ADMA1 descriptor table
+* |------------------------|---------|--------------------------|
+* | Address/page field |Reserved | Attribute |
+* |------------------------|---------|--------------------------|
+* |31 12|11 6|05 |04 |03|02 |01 |00 |
+* |------------------------|---------|----|----|--|---|---|-----|
+* | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|
+* |------------------------|---------|----|----|--|---|---|-----|
+*
+*
+* |------|------|-----------------|-------|-------------|
+* | Act2 | Act1 | Comment | 31-28 | 27 - 12 |
+* |------|------|-----------------|---------------------|
+* | 0 | 0 | No op | Don't care |
+* |------|------|-----------------|-------|-------------|
+* | 0 | 1 | Set data length | 0000 | Data Length |
+* |------|------|-----------------|-------|-------------|
+* | 1 | 0 | Transfer data | Data address |
+* |------|------|-----------------|---------------------|
+* | 1 | 1 | Link descriptor | Descriptor address |
+* |------|------|-----------------|---------------------|
+*/
+/* The bit shift for ADDRESS filed in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_ADDRESS_POS (12U)
+/* The bit mask for ADDRESS field in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)
+/* The bit shift for LENGTH filed in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_LENGTH_POS (12U)
+/* The mask for LENGTH field in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
+/* The maximum value of LENGTH filed in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDH_ADMA1_DESCRIPTOR_LENGTH_MASK - 511U)
+/* ADMA2 descriptor table
+* |----------------|---------------|-------------|--------------------------|
+* | Address field | Length | Reserved | Attribute |
+* |----------------|---------------|-------------|--------------------------|
+* |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |
+* |----------------|---------------|-------------|----|----|--|---|---|-----|
+* | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|
+* |----------------|---------------|-------------|----|----|--|---|---|-----|
+*
+*
+* | Act2 | Act1 | Comment | Operation |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* | 0 | 0 | No op | Don't care |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* | 0 | 1 | Reserved | Read this line and go to next one |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* | 1 | 1 | Link descriptor | Link to another descriptor |
+* |------|------|-----------------|-------------------------------------------------------------------|
+*/
+/* The bit shift for LENGTH field in ADMA2's descriptor */
+#define SDH_ADMA2_DESCRIPTOR_LENGTH_POS (16U)
+/* The bit mask for LENGTH field in ADMA2's descriptor */
+#define SDH_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
+/* The maximum value of LENGTH field in ADMA2's descriptor */
+#define SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDH_ADMA2_DESCRIPTOR_LENGTH_MASK - 511U)
+#define SDH_EnableIntStatus(mask) \
+ do { \
+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN, \
+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN) | (mask)); \
+ } while (0)
+#define SDH_DisableIntStatus(mask) \
+ do { \
+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN, \
+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN) & (~(mask))); \
+ } while (0)
+#define SDH_EnableIntSource(mask) \
+ do { \
+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN, \
+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN) | (mask)); \
+ } while (0)
+#define SDH_DisableIntSource(mask) \
+ do { \
+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN, \
+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN) & (~(mask))); \
+ } while (0)
+#define SDH_GetIntStatus() BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS);
+#define SDH_GetIntEnableStatus() BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN);
+#define SDH_ClearIntStatus(mask) BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS, (mask));
+#define SDH_AutoCmd12ErrStatus() BL_RD_SHORT(SDH_BASE + SDH_SD_AUTO_CMD12_ERROR_STATUS_OFFSET);
+#define SDH_GetDMAErrStatus() BL_RD_SHORT(SDH_BASE + SDH_SD_ADMA_ERROR_STATUS_OFFSET);
+#define SDH_GetPresentStatus() BL_RD_REG(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+#define SDH_MAX_BLOCK_COUNT 0xffff
+//#define SDH_CMD_INDEX(x) (x)
+
+/*@} end of group SDH_Public_Macros */
+
+/** @defgroup SDH_Public_Functions
+ * @{
+ */
+void SDH_MMC1_IRQHandler(void);
+
+void SDH_Reset(void);
+void SDH_Set_Timeout(uint8_t tmo);
+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);
+void SDH_ITConfig(uint32_t SDH_IT_FLAG, BL_Fun_Type NewState);
+void SDH_Ctrl_Init(const SDH_Cfg_Type *cfg);
+void SDH_Powon(void);
+void SDH_SendCommand(SDH_CMD_Cfg_Type *cmd);
+void SDH_DisableDMA(void);
+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);
+SDH_Stat_Type SDH_GetCmdResp(SDH_CMD_Cfg_Type *cmd);
+uint32_t SDH_ReadDataPort(SDH_Data_Cfg_Type *dataCfg);
+SDH_Stat_Type SDH_WaitCommandDone(SDH_CMD_Cfg_Type *cmd);
+SDH_Stat_Type SDH_ConfigDataTranfer(SDH_Data_Cfg_Type *dataCfg);
+SDH_Stat_Type SDH_TransferDataBlocking(SDH_Data_Cfg_Type *dataCfg, uint8_t enDMA);
+SDH_Stat_Type SDH_TransferBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer);
+SDH_Stat_Type SDH_TransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer);
+void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle, const SDH_Trans_Callback_Cfg_Type *callBack, void *userData);
+void SDH_EnableDMA(SDH_DMA_Mode_Type dmaMode);
+void SDH_EnableStatus(void);
+SDH_Stat_Type SDH_ReadDataPortBlock(SDH_Data_Cfg_Type *dataCfg);
+uint32_t SDH_WriteDataPort(SDH_Data_Cfg_Type *dataCfg);
+SDH_Stat_Type SDH_WriteDataPortBlock(SDH_Data_Cfg_Type *dataCfg);
+void SDH_DisableSdClock(void);
+void SDH_Deinit(void);
+void SDH_GetCapability(SDH_Cap_Cfg_Type *capability);
+SDH_Stat_Type SDH_CreateADMA1Descriptor(uint32_t *adma1Entries, uint32_t maxEntries,
+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag);
+SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint32_t maxEntries,
+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag);
+SDH_Stat_Type SDH_SetInternalDmaConfig(SDH_DMA_Cfg_Type *dmaCfg, const uint32_t *data, uint8_t enAutoCmd23);
+SDH_Stat_Type SDH_CreateAdmaEntryConfig(SDH_DMA_Cfg_Type *dmaCfg, SDH_Data_Cfg_Type *dataCfg, SDH_ADMA_Flag_Type flag);
+/*@} end of group SDH_Public_Functions */
+
+/*@} end of group SDH */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_SDH_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_tzc_sec.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_tzc_sec.h
new file mode 100644
index 00000000..34500811
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_tzc_sec.h
@@ -0,0 +1,295 @@
+/**
+ ******************************************************************************
+ * @file bl808_tzc_sec.h
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL808_TZC_SEC_H__
+#define __BL808_TZC_SEC_H__
+
+#include "tzc_sec_reg.h"
+#include "bl808_common.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup TZC_SEC
+ * @{
+ */
+
+/** @defgroup TZC_SEC_Public_Types
+ * @{
+ */
+
+/**
+ * @brief TZC_SEC master type definition
+ */
+typedef enum {
+ TZC_SEC_MASTER_LP, /*!< TZC Master:LP CPU */
+ TZC_SEC_MASTER_MM_BUS, /*!< TZC Master:MM Bus */
+ TZC_SEC_MASTER_USB, /*!< TZC Master:USB */
+ TZC_SEC_MASTER_WIFI, /*!< TZC Master:WIFI */
+ TZC_SEC_MASTER_CCI, /*!< TZC Master:CCI */
+ TZC_SEC_MASTER_SDH, /*!< TZC Master:SDH */
+ TZC_SEC_MASTER_EMAC, /*!< TZC Master:EMAC */
+ TZC_SEC_MASTER_M0, /*!< TZC Master:M0 CPU */
+ TZC_SEC_MASTER_DMA0, /*!< TZC Master:DMA0 */
+ TZC_SEC_MASTER_DMA1, /*!< TZC Master:DMA1 */
+ TZC_SEC_MASTER_LZ4, /*!< TZC Master:LZ4 */
+ TZC_SEC_MASTER_D0, /*!< TZC Master:D0 */
+ TZC_SEC_MASTER_BLAI, /*!< TZC Master:BLAI */
+ TZC_SEC_MASTER_CODEC, /*!< TZC Master:CODEC */
+ TZC_SEC_MASTER_ISP, /*!< TZC Master:ISP */
+ TZC_SEC_MASTER_2DDMA, /*!< TZC Master:2D DMA */
+ TZC_SEC_MASTER_DMA2, /*!< TZC Master:DMA2 */
+ TZC_SEC_MASTER_MAX, /*!< TZC Master max */
+} TZC_SEC_Master_Type;
+
+/**
+ * @brief TZC_SEC slave type definition
+ */
+typedef enum {
+ TZC_SEC_SLAVE_GLB = 0, /*!< TZC Slave:GLB */
+ TZC_SEC_SLAVE_MIX, /*!< TZC Slave:MIX */
+ TZC_SEC_SLAVE_GPIP, /*!< TZC Slave:GPIP */
+ TZC_SEC_SLAVE_DBG, /*!< TZC Slave:DBG */
+ TZC_SEC_SLAVE_RSVD, /*!< TZC Slave:Reserved */
+ TZC_SEC_SLAVE_TZC1, /*!< TZC Slave:TZC1 */
+ TZC_SEC_SLAVE_TZC2, /*!< TZC Slave:TZC2 */
+ TZC_SEC_SLAVE_RSVD2, /*!< TZC Slave:Reserved */
+ TZC_SEC_SLAVE_CCI, /*!< TZC Slave:CCI */
+ TZC_SEC_SLAVE_MCU_MISC, /*!< TZC Slave:MCU_MISC */
+ TZC_SEC_SLAVE_PERIPHERAL, /*!< TZC Slave:Peripheral */
+ TZC_SEC_SLAVE_EMI_MISC = 16, /*!< TZC Slave:emi misc */
+ TZC_SEC_SLAVE_PSRAMA, /*!< TZC Slave:PSRAMA */
+ TZC_SEC_SLAVE_PSRAMB, /*!< TZC Slave:PSRAMB */
+ TZC_SEC_SLAVE_USB, /*!< TZC Slave:USB */
+ TZC_SEC_SLAVE_RF2, /*!< TZC Slave:RF2 */
+ TZC_SEC_SLAVE_AUDIO, /*!< TZC Slave:Audio */
+ TZC_SEC_SLAVE_EF_CTRL, /*!< TZC Slave:efuse control*/
+
+ TZC_SEC_SLAVE_MM = 32, /*!< TZC Slave:MM */
+ TZC_SEC_SLAVE_DMA0, /*!< TZC Slave:DMA0 */
+ TZC_SEC_SLAVE_DMA1, /*!< TZC Slave:DMA1 */
+ TZC_SEC_SLAVE_PWR, /*!< TZC Slave:Power */
+
+ TZC_SEC_SLAVE_MAX, /*!< TZC slave max*/
+} TZC_SEC_Slave_Type;
+
+/**
+ * @brief TZC_SEC MM slave type definition
+ */
+typedef enum {
+ TZC_SEC_MM_SLAVE_MISC, /*!< TZC MM Slave:MISC */
+ TZC_SEC_MM_SLAVE_DMA, /*!< TZC MM Slave:DMA */
+ TZC_SEC_MM_SLAVE_UART, /*!< TZC MM Slave:UART */
+ TZC_SEC_MM_SLAVE_I2C0, /*!< TZC MM Slave:I2C0 */
+ TZC_SEC_MM_SLAVE_I2C1, /*!< TZC MM Slave:I2C1 */
+ TZC_SEC_MM_SLAVE_IPC, /*!< TZC MM Slave:IPC */
+ TZC_SEC_MM_SLAVE_2DDMA, /*!< TZC MM Slave:2DDMA */
+ TZC_SEC_MM_SLAVE_CLKRST, /*!< TZC MM Slave:Clock and reset */
+ TZC_SEC_MM_SLAVE_SPI, /*!< TZC MM Slave:SPI */
+ TZC_SEC_MM_SLAVE_TIMER, /*!< TZC MM Slave:Timer */
+ TZC_SEC_MM_SLAVE_RSVD1, /*!< TZC MM Slave:reserved1 */
+ TZC_SEC_MM_SLAVE_RSVD2, /*!< TZC MM Slave:reserved2 */
+ TZC_SEC_MM_SLAVE_RSVD3, /*!< TZC MM Slave:reserved3 */
+ TZC_SEC_MM_SLAVE_RSVD4, /*!< TZC MM Slave:reserved4 */
+ TZC_SEC_MM_SLAVE_RSVD5, /*!< TZC MM Slave:reserved5 */
+ TZC_SEC_MM_SLAVE_UHS_PSRAM, /*!< TZC MM Slave:uhs psram */
+
+ TZC_SEC_MM_SLAVE_ISP_MISC = 16, /*!< TZC MM Slave:ISP MISC */
+ TZC_SEC_MM_SLAVE_ISP_TOP, /*!< TZC MM Slave:ISP TOP */
+ TZC_SEC_MM_SLAVE_DVP_MISC, /*!< TZC MM Slave:DVP MISC */
+ TZC_SEC_MM_SLAVE_OSD_A, /*!< TZC MM Slave:OSD_A */
+ TZC_SEC_MM_SLAVE_OSD_B, /*!< TZC MM Slave:OSD_B */
+ TZC_SEC_MM_SLAVE_OSD_DP, /*!< TZC MM Slave:OSD_DP */
+ TZC_SEC_MM_SLAVE_AWB3_CORE, /*!< TZC MM Slave:AWB3 core */
+ TZC_SEC_MM_SLAVE_AWB3_SRAM, /*!< TZC MM Slave:AWB3 SRAM */
+ TZC_SEC_MM_SLAVE_RSVD6, /*!< TZC MM Slave:Reserved */
+ TZC_SEC_MM_SLAVE_ISP_AE_SRAM, /*!< TZC MM Slave:ISP AE SRAM */
+ TZC_SEC_MM_SLAVE_MIPI, /*!< TZC MM Slave:MIPI(DSI & CSI )*/
+ TZC_SEC_MM_SLAVE_DBI, /*!< TZC MM Slave:DBI */
+ TZC_SEC_MM_SLAVE_ISP_AWB_SRAM, /*!< TZC MM Slave:ISP AWB SRAM */
+
+ TZC_SEC_MM_SLAVE_CODEC_MISC = 32, /*!< TZC MM Slave:Codec misc */
+ TZC_SEC_MM_SLAVE_MJPEG, /*!< TZC MM Slave:MJPEG */
+ TZC_SEC_MM_SLAVE_VIDEO, /*!< TZC MM Slave:Video */
+ TZC_SEC_MM_SLAVE_MJPEG_DEC, /*!< TZC MM Slave:MJPEG Decoder */
+ TZC_SEC_MM_SLAVE_BLAI, /*!< TZC MM Slave:BLAI */
+
+ TZC_SEC_MM_SLAVE_MAX, /*!< TZC MM slave max*/
+} TZC_SEC_MM_Slave_Type;
+
+/**
+ * @brief TZC_SEC GLB Ctrl type definition
+ */
+typedef enum {
+ TZC_SEC_GLB_CTRL_POR_RESET, /*!< TZC GLB Ctrl: Power on reset */
+ TZC_SEC_GLB_CTRL_CPU_RESET, /*!< TZC GLB Ctrl: CPU reset */
+ TZC_SEC_GLB_CTRL_SYS_RESET, /*!< TZC GLB Ctrl: System reset */
+ TZC_SEC_GLB_CTRL_CCPU_RESET, /*!< TZC GLB Ctrl: Coupled CPU reset */
+ TZC_SEC_GLB_CTRL_MISC, /*!< TZC GLB Ctrl: MISC */
+ TZC_SEC_GLB_CTRL_SRAM, /*!< TZC GLB Ctrl: SRAM */
+ TZC_SEC_GLB_CTRL_SWRESET, /*!< TZC GLB Ctrl: Software reset */
+ TZC_SEC_GLB_CTRL_BMX, /*!< TZC GLB Ctrl: BMX */
+ TZC_SEC_GLB_CTRL_DBG, /*!< TZC GLB Ctrl: DBG */
+ TZC_SEC_GLB_CTRL_MBIST, /*!< TZC GLB Ctrl: MBIST */
+ TZC_SEC_GLB_CTRL_CLK, /*!< TZC GLB Ctrl: CLK */
+ TZC_SEC_GLB_CTRL_INT, /*!< TZC GLB Ctrl: Interrupt */
+ TZC_SEC_GLB_CTRL_PWR, /*!< TZC GLB Ctrl: Power */
+ TZC_SEC_GLB_CTRL_MAX,
+} TZC_SEC_GLB_Ctrl_Type;
+
+/**
+ * @brief TZC_SEC MM GLB Ctrl type definition
+ */
+typedef enum {
+ TZC_SEC_MM_GLB_CTRL_POR_RESET, /*!< TZC MM GLB Ctrl: Power on reset */
+ TZC_SEC_MM_GLB_CTRL_CPU_RESET, /*!< TZC MM GLB Ctrl: CPU reset */
+ TZC_SEC_MM_GLB_CTRL_SYS_RESET, /*!< TZC MM GLB Ctrl: System reset */
+ TZC_SEC_MM_GLB_CTRL_CCPU_RESET, /*!< TZC MM GLB Ctrl: Coupled CPU reset */
+ TZC_SEC_MM_GLB_CTRL_RSVD1, /*!< TZC MM GLB Ctrl: Reserved */
+ TZC_SEC_MM_GLB_CTRL_SRAM, /*!< TZC MM GLB Ctrl: SRAM */
+ TZC_SEC_MM_GLB_CTRL_SWRESET, /*!< TZC MM GLB Ctrl: Software reset */
+ TZC_SEC_MM_GLB_CTRL_RSVD2, /*!< TZC MM GLB Ctrl: Reserved */
+ TZC_SEC_MM_GLB_CTRL_RSVD3, /*!< TZC MM GLB Ctrl: Reserved */
+ TZC_SEC_MM_GLB_CTRL_RSVD4, /*!< TZC MM GLB Ctrl: Reserved */
+ TZC_SEC_MM_GLB_CTRL_CLK, /*!< TZC MM GLB Ctrl: CLK */
+ TZC_SEC_MM_GLB_CTRL_MAX,
+} TZC_SEC_MM_GLB_Ctrl_Type;
+
+/**
+ * @brief TZC_SEC SE Ctrl type definition
+ */
+typedef enum {
+ TZC_SEC_SE_CTRL_SHA, /*!< TZC SE Ctrl: SHA */
+ TZC_SEC_SE_CTRL_AES, /*!< TZC SE Ctrl: AES */
+ TZC_SEC_SE_CTRL_TRNG, /*!< TZC SE Ctrl: TRNG */
+ TZC_SEC_SE_CTRL_PKA, /*!< TZC SE Ctrl: PKA */
+ TZC_SEC_SE_CTRL_CDET, /*!< TZC SE Ctrl: CEDT */
+ TZC_SEC_SE_CTRL_GMAC, /*!< TZC SE Ctrl: GMAC */
+ TZC_SEC_SE_CTRL_MAX,
+} TZC_SEC_SE_Ctrl_Type;
+
+/**
+ * @brief TZC_SEC SF Ctrl type definition
+ */
+typedef enum {
+ TZC_SEC_SF_CTRL_CR, /*!< TZC SF Ctrl: control register */
+ TZC_SEC_SF_CTRL_SEC, /*!< TZC SF Ctrl: security register */
+ TZC_SEC_SF_CTRL_MAX,
+} TZC_SEC_SF_Ctrl_Type;
+
+/**
+ * @brief TZC_SEC SE Ctrl mode definition
+ */
+typedef enum {
+ TZC_SEC_SE_MODE_ARB, /*!< TZC SE Ctrl mode: cpus arbitrate */
+ TZC_SEC_SE_MODE_TZC, /*!< TZC SE Ctrl: TZC control as group */
+} TZC_SEC_SE_Ctrl_Mode;
+
+/**
+ * @brief TZC_SEC SF Ctrl mode definition
+ */
+typedef enum {
+ TZC_SEC_SF_MODE_ARB, /*!< TZC SF Ctrl mode: cpus arbitrate */
+ TZC_SEC_SF_MODE_TZC, /*!< TZC SF Ctrl: TZC control as group */
+} TZC_SEC_SF_Ctrl_Mode;
+
+/**
+ * @brief TZC_SEC Auth group
+ */
+typedef enum {
+ TZC_SEC_AUTH_GRP_0, /*!< TZC auth group 0 */
+ TZC_SEC_AUTH_GRP_1, /*!< TZC auth group 1 */
+} TZC_SEC_Auth_Group;
+
+/**
+ * @brief TZC_SEC Advance Auth group
+ */
+typedef enum {
+ TZC_SEC_ADV_AUTH_GRP_0_IBUS = 0x01, /*!< TZC advance auth group 0 IBUS */
+ TZC_SEC_ADV_AUTH_GRP_0_DBUS = 0x02, /*!< TZC advance auth group 0 DBUS */
+ TZC_SEC_ADV_AUTH_GRP_1_IBUS = 0x04, /*!< TZC advance auth group 1 IBUS */
+ TZC_SEC_ADV_AUTH_GRP_1_DBUS = 0x08, /*!< TZC advance auth group 1 DBUS */
+} TZC_SEC_Advance_Auth_Group;
+
+/*@} end of group TZC_SEC_Public_Types */
+
+/** @defgroup TZC_SEC_Public_Constants
+ * @{
+ */
+
+/*@} end of group TZC_SEC_Public_Constants */
+
+/** @defgroup TZC_SEC_Public_Macros
+ * @{
+ */
+
+#define TZC_SEC_MAX_AUTH_GRP 3
+/*@} end of group TZC_SEC_Public_Macros */
+
+/** @defgroup TZC_SEC_Public_Functions
+ * @{
+ */
+void Tzc_Sec_Set_Sboot_Done(void);
+void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group);
+void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group);
+void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group);
+void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group);
+void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group);
+void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group);
+void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group);
+void Tzc_Sec_L2SRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_VRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_PSRAMA_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_PSRAMA_Access_Release(void);
+void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_PSRAMB_Access_Release(void);
+void Tzc_Sec_XRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);
+void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);
+void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group);
+void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group);
+void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue);
+/*@} end of group TZC_SEC_Public_Functions */
+
+/*@} end of group TZC_SEC */
+
+/*@} end of group BL808_Peripheral_Driver */
+
+#endif /* __BL808_TZC_SEC_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_uhs_phy.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_uhs_phy.h
new file mode 100644
index 00000000..a2560b06
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/bl808_uhs_phy.h
@@ -0,0 +1,117 @@
+#ifndef __UHS_PHY_H__
+#define __UHS_PHY_H__
+
+#include "bl808_common.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_glb.h"
+
+#ifndef CAL_MODE
+#define CAL_MODE (0) // 0 is for sw call, 1 is for phy test, 2 is for ate cal
+#endif
+
+enum {
+ UHS_LATENCY_CODE_533 = 3, // "0"
+ UHS_LATENCY_CODE_800 = 3, // "1"
+ UHS_LATENCY_CODE_933 = 3, // "2"
+ UHS_LATENCY_CODE_1066 = 3,
+ UHS_LATENCY_CODE_RESERVED = 3, //"4"
+ UHS_LATENCY_CODE_400 = 3, //"5"
+ UHS_LATENCY_CODE_333 = 3, //"6"
+ UHS_LATENCY_CODE_200 = 3, //"7"
+};
+
+enum{
+ UHS_REGR_GNT_ERR = 1,
+ UHS_REGR_DONE_ERR,
+ UHS_REGW_GNT_ERR,
+ UHS_REGW_DONE_ERR,
+ UHS_LATENCY_CODE_WRITE_ERR,
+ UHS_INIT_ARRAY_WRITE_ERR,
+ UHS_REG_READ_CAL_ERR,
+ UHS_REG_WRITE_CAL_ERR,
+ UHS_ARRAY_READ_LAT_ERR,
+ UHS_ARRAY_WRITE_CK_ERR,
+ UHS_ARRAY_READ_CAL_ERR,
+ UHS_ARRAY_WRITE_CAL_ERR,
+ UHS_CACHE_ENABLE_ERR,
+ UHS_CACHE_DISABLE_ERR,
+ UHS_CACHE_RECOVER_ERR,
+ UHS_REG_WRITE_2kM_ERR,
+ UHS_BAD_DIE_ERR,
+ UHS_DIAGONAL_TEST_ERR,
+ UHS_ALL_ADDR_TEST_ERR,
+};
+
+#if CAL_MODE != 2
+typedef struct
+{
+ uint8_t rl :6;
+ uint8_t rdqs :4;
+ uint8_t rdq :4;
+ uint8_t wl :5;
+ uint8_t wdqs :4;
+ uint8_t wdq :4;
+ uint8_t ck :4;
+ uint8_t err_type;
+ uint8_t err_sub_type;
+ uint8_t cal_mode;
+ uint16_t datarate;
+ uint8_t rwindow;
+ uint8_t rwindow_begin;
+ uint8_t rwindow_end;
+ uint8_t wwindow;
+ uint8_t wwindow_begin;
+ uint8_t wwindow_end;
+ uint8_t cal_done;
+ uint32_t crc_res;
+} uhs_phy_cal_res_struct;
+#else
+typedef struct
+{
+ uint32_t rl;
+ uint32_t rdqs;
+ uint32_t rdq;
+ uint32_t wl;
+ uint32_t wdqs;
+ uint32_t wdq;
+ uint32_t ck;
+ uint32_t err_type;
+ uint32_t err_sub_type;
+ uint32_t cal_mode;
+ uint32_t datarate;
+ uint32_t rwindow;
+ uint32_t rwindow_begin;
+ uint32_t rwindow_end;
+ uint32_t wwindow;
+ uint32_t wwindow_begin;
+ uint32_t wwindow_end;
+ uint32_t cal_done;
+ uint32_t crc_res;
+} uhs_phy_cal_res_struct;
+#endif
+extern uhs_phy_cal_res_struct* uhs_phy_cal_res;
+
+// function call
+void uhs_phy_init(PSRAM_UHS_Cfg_Type *cfg);
+void uhs_phy_pwr_down(void);
+uint8_t mr_read_back(void);
+void set_odt_en(void);
+// for htol test api
+uint8_t uhs_all_addr_test(void);
+
+// for test or debug in example main.c
+void soft_reset(void);
+void uhs_reset(uint8_t ma_rb);
+void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1);
+uint8_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1);
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq);
+//
+void set_uhs_latency_r(uint32_t uhs_latency);
+void set_uhs_latency_w(uint32_t uhs_latency);
+void cfg_dq_drv(uint32_t dq);
+void cfg_dqs_drv(uint32_t dqs);
+void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv);
+void cfg_dq_rx(uint8_t dq);
+void cfg_dqs_rx(uint8_t dqs);
+
+#endif // __UHS_PHY_H__
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/aon_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/aon_reg.h
new file mode 100644
index 00000000..65d46a0c
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/aon_reg.h
@@ -0,0 +1,2041 @@
+/**
+ ******************************************************************************
+ * @file aon_reg.h
+ * @version V1.0
+ * @date 2021-09-10
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __AON_REG_H__
+#define __AON_REG_H__
+
+#include "bl808.h"
+
+/* 0x800 : aon */
+#define AON_OFFSET (0x800)
+#define AON_RESV AON_RESV
+#define AON_RESV_POS (0U)
+#define AON_RESV_LEN (8U)
+#define AON_RESV_MSK (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)
+#define AON_RESV_UMSK (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS))
+#define AON_PU_AON_DC_TBUF AON_PU_AON_DC_TBUF
+#define AON_PU_AON_DC_TBUF_POS (12U)
+#define AON_PU_AON_DC_TBUF_LEN (1U)
+#define AON_PU_AON_DC_TBUF_MSK (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)
+#define AON_PU_AON_DC_TBUF_UMSK (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS))
+#define AON_LDO11_RT_PULLDOWN AON_LDO11_RT_PULLDOWN
+#define AON_LDO11_RT_PULLDOWN_POS (20U)
+#define AON_LDO11_RT_PULLDOWN_LEN (1U)
+#define AON_LDO11_RT_PULLDOWN_MSK (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)
+#define AON_LDO11_RT_PULLDOWN_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS))
+#define AON_LDO11_RT_PULLDOWN_SEL AON_LDO11_RT_PULLDOWN_SEL
+#define AON_LDO11_RT_PULLDOWN_SEL_POS (21U)
+#define AON_LDO11_RT_PULLDOWN_SEL_LEN (1U)
+#define AON_LDO11_RT_PULLDOWN_SEL_MSK (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)
+#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS))
+#define AON_SW_PU_LDO11_RT AON_SW_PU_LDO11_RT
+#define AON_SW_PU_LDO11_RT_POS (22U)
+#define AON_SW_PU_LDO11_RT_LEN (1U)
+#define AON_SW_PU_LDO11_RT_MSK (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)
+#define AON_SW_PU_LDO11_RT_UMSK (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS))
+
+/* 0x804 : aon_common */
+#define AON_COMMON_OFFSET (0x804)
+#define AON_TMUX_AON AON_TMUX_AON
+#define AON_TMUX_AON_POS (0U)
+#define AON_TMUX_AON_LEN (3U)
+#define AON_TMUX_AON_MSK (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)
+#define AON_TMUX_AON_UMSK (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS))
+#define AON_PMIP_DC_TP_OUT_EN_AON AON_PMIP_DC_TP_OUT_EN_AON
+#define AON_PMIP_DC_TP_OUT_EN_AON_POS (3U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_LEN (1U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_MSK (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)
+#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS))
+#define AON_TEN_BG_SYS_AON AON_TEN_BG_SYS_AON
+#define AON_TEN_BG_SYS_AON_POS (4U)
+#define AON_TEN_BG_SYS_AON_LEN (1U)
+#define AON_TEN_BG_SYS_AON_MSK (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)
+#define AON_TEN_BG_SYS_AON_UMSK (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS))
+#define AON_TEN_DCDC11_0_AON AON_TEN_DCDC11_0_AON
+#define AON_TEN_DCDC11_0_AON_POS (5U)
+#define AON_TEN_DCDC11_0_AON_LEN (1U)
+#define AON_TEN_DCDC11_0_AON_MSK (((1U << AON_TEN_DCDC11_0_AON_LEN) - 1) << AON_TEN_DCDC11_0_AON_POS)
+#define AON_TEN_DCDC11_0_AON_UMSK (~(((1U << AON_TEN_DCDC11_0_AON_LEN) - 1) << AON_TEN_DCDC11_0_AON_POS))
+#define AON_TEN_DCDC11_1_AON AON_TEN_DCDC11_1_AON
+#define AON_TEN_DCDC11_1_AON_POS (6U)
+#define AON_TEN_DCDC11_1_AON_LEN (1U)
+#define AON_TEN_DCDC11_1_AON_MSK (((1U << AON_TEN_DCDC11_1_AON_LEN) - 1) << AON_TEN_DCDC11_1_AON_POS)
+#define AON_TEN_DCDC11_1_AON_UMSK (~(((1U << AON_TEN_DCDC11_1_AON_LEN) - 1) << AON_TEN_DCDC11_1_AON_POS))
+#define AON_TEN_DCDC18_0_AON AON_TEN_DCDC18_0_AON
+#define AON_TEN_DCDC18_0_AON_POS (7U)
+#define AON_TEN_DCDC18_0_AON_LEN (1U)
+#define AON_TEN_DCDC18_0_AON_MSK (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)
+#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS))
+#define AON_TEN_DCDC18_1_AON AON_TEN_DCDC18_1_AON
+#define AON_TEN_DCDC18_1_AON_POS (8U)
+#define AON_TEN_DCDC18_1_AON_LEN (1U)
+#define AON_TEN_DCDC18_1_AON_MSK (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)
+#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS))
+#define AON_TEN_LDO12UHS AON_TEN_LDO12UHS
+#define AON_TEN_LDO12UHS_POS (9U)
+#define AON_TEN_LDO12UHS_LEN (1U)
+#define AON_TEN_LDO12UHS_MSK (((1U << AON_TEN_LDO12UHS_LEN) - 1) << AON_TEN_LDO12UHS_POS)
+#define AON_TEN_LDO12UHS_UMSK (~(((1U << AON_TEN_LDO12UHS_LEN) - 1) << AON_TEN_LDO12UHS_POS))
+#define AON_TEN_LDO18FLASH AON_TEN_LDO18FLASH
+#define AON_TEN_LDO18FLASH_POS (10U)
+#define AON_TEN_LDO18FLASH_LEN (1U)
+#define AON_TEN_LDO18FLASH_MSK (((1U << AON_TEN_LDO18FLASH_LEN) - 1) << AON_TEN_LDO18FLASH_POS)
+#define AON_TEN_LDO18FLASH_UMSK (~(((1U << AON_TEN_LDO18FLASH_LEN) - 1) << AON_TEN_LDO18FLASH_POS))
+#define AON_TEN_LDO15CIS AON_TEN_LDO15CIS
+#define AON_TEN_LDO15CIS_POS (11U)
+#define AON_TEN_LDO15CIS_LEN (1U)
+#define AON_TEN_LDO15CIS_MSK (((1U << AON_TEN_LDO15CIS_LEN) - 1) << AON_TEN_LDO15CIS_POS)
+#define AON_TEN_LDO15CIS_UMSK (~(((1U << AON_TEN_LDO15CIS_LEN) - 1) << AON_TEN_LDO15CIS_POS))
+#define AON_TEN_LDO18IO_AON AON_TEN_LDO18IO_AON
+#define AON_TEN_LDO18IO_AON_POS (12U)
+#define AON_TEN_LDO18IO_AON_LEN (1U)
+#define AON_TEN_LDO18IO_AON_MSK (((1U << AON_TEN_LDO18IO_AON_LEN) - 1) << AON_TEN_LDO18IO_AON_POS)
+#define AON_TEN_LDO18IO_AON_UMSK (~(((1U << AON_TEN_LDO18IO_AON_LEN) - 1) << AON_TEN_LDO18IO_AON_POS))
+#define AON_TEN_LDO28CIS AON_TEN_LDO28CIS
+#define AON_TEN_LDO28CIS_POS (13U)
+#define AON_TEN_LDO28CIS_LEN (1U)
+#define AON_TEN_LDO28CIS_MSK (((1U << AON_TEN_LDO28CIS_LEN) - 1) << AON_TEN_LDO28CIS_POS)
+#define AON_TEN_LDO28CIS_UMSK (~(((1U << AON_TEN_LDO28CIS_LEN) - 1) << AON_TEN_LDO28CIS_POS))
+#define AON_TEN_RC32M AON_TEN_RC32M
+#define AON_TEN_RC32M_POS (14U)
+#define AON_TEN_RC32M_LEN (1U)
+#define AON_TEN_RC32M_MSK (((1U << AON_TEN_RC32M_LEN) - 1) << AON_TEN_RC32M_POS)
+#define AON_TEN_RC32M_UMSK (~(((1U << AON_TEN_RC32M_LEN) - 1) << AON_TEN_RC32M_POS))
+#define AON_TEN_LDO15RF_AON AON_TEN_LDO15RF_AON
+#define AON_TEN_LDO15RF_AON_POS (16U)
+#define AON_TEN_LDO15RF_AON_LEN (1U)
+#define AON_TEN_LDO15RF_AON_MSK (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)
+#define AON_TEN_LDO15RF_AON_UMSK (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS))
+#define AON_TEN_XTAL_AON AON_TEN_XTAL_AON
+#define AON_TEN_XTAL_AON_POS (17U)
+#define AON_TEN_XTAL_AON_LEN (1U)
+#define AON_TEN_XTAL_AON_MSK (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)
+#define AON_TEN_XTAL_AON_UMSK (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS))
+#define AON_DTEN_XTAL_AON AON_DTEN_XTAL_AON
+#define AON_DTEN_XTAL_AON_POS (18U)
+#define AON_DTEN_XTAL_AON_LEN (1U)
+#define AON_DTEN_XTAL_AON_MSK (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)
+#define AON_DTEN_XTAL_AON_UMSK (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS))
+#define AON_TEN_MBG_AON AON_TEN_MBG_AON
+#define AON_TEN_MBG_AON_POS (19U)
+#define AON_TEN_MBG_AON_LEN (1U)
+#define AON_TEN_MBG_AON_MSK (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)
+#define AON_TEN_MBG_AON_UMSK (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS))
+#define AON_TEN_CIP_MISC_AON AON_TEN_CIP_MISC_AON
+#define AON_TEN_CIP_MISC_AON_POS (20U)
+#define AON_TEN_CIP_MISC_AON_LEN (1U)
+#define AON_TEN_CIP_MISC_AON_MSK (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)
+#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS))
+#define AON_TEN_AON AON_TEN_AON
+#define AON_TEN_AON_POS (21U)
+#define AON_TEN_AON_LEN (1U)
+#define AON_TEN_AON_MSK (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)
+#define AON_TEN_AON_UMSK (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS))
+
+/* 0x808 : aon_misc */
+#define AON_MISC_OFFSET (0x808)
+#define AON_SW_SOC_EN_AON AON_SW_SOC_EN_AON
+#define AON_SW_SOC_EN_AON_POS (0U)
+#define AON_SW_SOC_EN_AON_LEN (1U)
+#define AON_SW_SOC_EN_AON_MSK (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)
+#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS))
+#define AON_SW_WB_EN_AON AON_SW_WB_EN_AON
+#define AON_SW_WB_EN_AON_POS (1U)
+#define AON_SW_WB_EN_AON_LEN (1U)
+#define AON_SW_WB_EN_AON_MSK (((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS)
+#define AON_SW_WB_EN_AON_UMSK (~(((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS))
+
+/* 0x810 : bg_sys_top */
+#define AON_BG_SYS_TOP_OFFSET (0x810)
+#define AON_PU_BG_SYS_AON AON_PU_BG_SYS_AON
+#define AON_PU_BG_SYS_AON_POS (0U)
+#define AON_PU_BG_SYS_AON_LEN (1U)
+#define AON_PU_BG_SYS_AON_MSK (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)
+#define AON_PU_BG_SYS_AON_UMSK (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS))
+#define AON_ISTART_CTRL_AON AON_ISTART_CTRL_AON
+#define AON_ISTART_CTRL_AON_POS (1U)
+#define AON_ISTART_CTRL_AON_LEN (1U)
+#define AON_ISTART_CTRL_AON_MSK (((1U << AON_ISTART_CTRL_AON_LEN) - 1) << AON_ISTART_CTRL_AON_POS)
+#define AON_ISTART_CTRL_AON_UMSK (~(((1U << AON_ISTART_CTRL_AON_LEN) - 1) << AON_ISTART_CTRL_AON_POS))
+
+/* 0x814 : dcdc_top_0 */
+#define AON_DCDC_TOP_0_OFFSET (0x814)
+#define AON_DCDC11_SSTART_TIME_AON AON_DCDC11_SSTART_TIME_AON
+#define AON_DCDC11_SSTART_TIME_AON_POS (0U)
+#define AON_DCDC11_SSTART_TIME_AON_LEN (2U)
+#define AON_DCDC11_SSTART_TIME_AON_MSK (((1U << AON_DCDC11_SSTART_TIME_AON_LEN) - 1) << AON_DCDC11_SSTART_TIME_AON_POS)
+#define AON_DCDC11_SSTART_TIME_AON_UMSK (~(((1U << AON_DCDC11_SSTART_TIME_AON_LEN) - 1) << AON_DCDC11_SSTART_TIME_AON_POS))
+#define AON_DCDC11_STBY_LP_CUR_AON AON_DCDC11_STBY_LP_CUR_AON
+#define AON_DCDC11_STBY_LP_CUR_AON_POS (4U)
+#define AON_DCDC11_STBY_LP_CUR_AON_LEN (3U)
+#define AON_DCDC11_STBY_LP_CUR_AON_MSK (((1U << AON_DCDC11_STBY_LP_CUR_AON_LEN) - 1) << AON_DCDC11_STBY_LP_CUR_AON_POS)
+#define AON_DCDC11_STBY_LP_CUR_AON_UMSK (~(((1U << AON_DCDC11_STBY_LP_CUR_AON_LEN) - 1) << AON_DCDC11_STBY_LP_CUR_AON_POS))
+#define AON_DCDC11_VC_CLAMP_VTH_AON AON_DCDC11_VC_CLAMP_VTH_AON
+#define AON_DCDC11_VC_CLAMP_VTH_AON_POS (8U)
+#define AON_DCDC11_VC_CLAMP_VTH_AON_LEN (3U)
+#define AON_DCDC11_VC_CLAMP_VTH_AON_MSK (((1U << AON_DCDC11_VC_CLAMP_VTH_AON_LEN) - 1) << AON_DCDC11_VC_CLAMP_VTH_AON_POS)
+#define AON_DCDC11_VC_CLAMP_VTH_AON_UMSK (~(((1U << AON_DCDC11_VC_CLAMP_VTH_AON_LEN) - 1) << AON_DCDC11_VC_CLAMP_VTH_AON_POS))
+#define AON_DCDC11_VOUT_SEL_AON AON_DCDC11_VOUT_SEL_AON
+#define AON_DCDC11_VOUT_SEL_AON_POS (11U)
+#define AON_DCDC11_VOUT_SEL_AON_LEN (5U)
+#define AON_DCDC11_VOUT_SEL_AON_MSK (((1U << AON_DCDC11_VOUT_SEL_AON_LEN) - 1) << AON_DCDC11_VOUT_SEL_AON_POS)
+#define AON_DCDC11_VOUT_SEL_AON_UMSK (~(((1U << AON_DCDC11_VOUT_SEL_AON_LEN) - 1) << AON_DCDC11_VOUT_SEL_AON_POS))
+#define AON_DCDC11_VOUT_TRIM_AON AON_DCDC11_VOUT_TRIM_AON
+#define AON_DCDC11_VOUT_TRIM_AON_POS (16U)
+#define AON_DCDC11_VOUT_TRIM_AON_LEN (4U)
+#define AON_DCDC11_VOUT_TRIM_AON_MSK (((1U << AON_DCDC11_VOUT_TRIM_AON_LEN) - 1) << AON_DCDC11_VOUT_TRIM_AON_POS)
+#define AON_DCDC11_VOUT_TRIM_AON_UMSK (~(((1U << AON_DCDC11_VOUT_TRIM_AON_LEN) - 1) << AON_DCDC11_VOUT_TRIM_AON_POS))
+#define AON_DCDC11_VPFM_AON AON_DCDC11_VPFM_AON
+#define AON_DCDC11_VPFM_AON_POS (20U)
+#define AON_DCDC11_VPFM_AON_LEN (4U)
+#define AON_DCDC11_VPFM_AON_MSK (((1U << AON_DCDC11_VPFM_AON_LEN) - 1) << AON_DCDC11_VPFM_AON_POS)
+#define AON_DCDC11_VPFM_AON_UMSK (~(((1U << AON_DCDC11_VPFM_AON_LEN) - 1) << AON_DCDC11_VPFM_AON_POS))
+#define AON_DCDC11_ZVS_TD_OPT_AON AON_DCDC11_ZVS_TD_OPT_AON
+#define AON_DCDC11_ZVS_TD_OPT_AON_POS (24U)
+#define AON_DCDC11_ZVS_TD_OPT_AON_LEN (3U)
+#define AON_DCDC11_ZVS_TD_OPT_AON_MSK (((1U << AON_DCDC11_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC11_ZVS_TD_OPT_AON_POS)
+#define AON_DCDC11_ZVS_TD_OPT_AON_UMSK (~(((1U << AON_DCDC11_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC11_ZVS_TD_OPT_AON_POS))
+#define AON_DCDC11_VSTBY_AON AON_DCDC11_VSTBY_AON
+#define AON_DCDC11_VSTBY_AON_POS (28U)
+#define AON_DCDC11_VSTBY_AON_LEN (2U)
+#define AON_DCDC11_VSTBY_AON_MSK (((1U << AON_DCDC11_VSTBY_AON_LEN) - 1) << AON_DCDC11_VSTBY_AON_POS)
+#define AON_DCDC11_VSTBY_AON_UMSK (~(((1U << AON_DCDC11_VSTBY_AON_LEN) - 1) << AON_DCDC11_VSTBY_AON_POS))
+
+/* 0x818 : dcdc_top_1 */
+#define AON_DCDC_TOP_1_OFFSET (0x818)
+#define AON_DCDC11_NONOVERLAP_TD_AON AON_DCDC11_NONOVERLAP_TD_AON
+#define AON_DCDC11_NONOVERLAP_TD_AON_POS (0U)
+#define AON_DCDC11_NONOVERLAP_TD_AON_LEN (5U)
+#define AON_DCDC11_NONOVERLAP_TD_AON_MSK (((1U << AON_DCDC11_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC11_NONOVERLAP_TD_AON_POS)
+#define AON_DCDC11_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC11_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC11_NONOVERLAP_TD_AON_POS))
+#define AON_DCDC11_OCP_OUT_AON AON_DCDC11_OCP_OUT_AON
+#define AON_DCDC11_OCP_OUT_AON_POS (5U)
+#define AON_DCDC11_OCP_OUT_AON_LEN (1U)
+#define AON_DCDC11_OCP_OUT_AON_MSK (((1U << AON_DCDC11_OCP_OUT_AON_LEN) - 1) << AON_DCDC11_OCP_OUT_AON_POS)
+#define AON_DCDC11_OCP_OUT_AON_UMSK (~(((1U << AON_DCDC11_OCP_OUT_AON_LEN) - 1) << AON_DCDC11_OCP_OUT_AON_POS))
+#define AON_DCDC11_OCP_RST_AON AON_DCDC11_OCP_RST_AON
+#define AON_DCDC11_OCP_RST_AON_POS (6U)
+#define AON_DCDC11_OCP_RST_AON_LEN (1U)
+#define AON_DCDC11_OCP_RST_AON_MSK (((1U << AON_DCDC11_OCP_RST_AON_LEN) - 1) << AON_DCDC11_OCP_RST_AON_POS)
+#define AON_DCDC11_OCP_RST_AON_UMSK (~(((1U << AON_DCDC11_OCP_RST_AON_LEN) - 1) << AON_DCDC11_OCP_RST_AON_POS))
+#define AON_DCDC11_OCP_VTH_AON AON_DCDC11_OCP_VTH_AON
+#define AON_DCDC11_OCP_VTH_AON_POS (8U)
+#define AON_DCDC11_OCP_VTH_AON_LEN (3U)
+#define AON_DCDC11_OCP_VTH_AON_MSK (((1U << AON_DCDC11_OCP_VTH_AON_LEN) - 1) << AON_DCDC11_OCP_VTH_AON_POS)
+#define AON_DCDC11_OCP_VTH_AON_UMSK (~(((1U << AON_DCDC11_OCP_VTH_AON_LEN) - 1) << AON_DCDC11_OCP_VTH_AON_POS))
+#define AON_DCDC11_OSC_2M_MODE_AON AON_DCDC11_OSC_2M_MODE_AON
+#define AON_DCDC11_OSC_2M_MODE_AON_POS (11U)
+#define AON_DCDC11_OSC_2M_MODE_AON_LEN (1U)
+#define AON_DCDC11_OSC_2M_MODE_AON_MSK (((1U << AON_DCDC11_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC11_OSC_2M_MODE_AON_POS)
+#define AON_DCDC11_OSC_2M_MODE_AON_UMSK (~(((1U << AON_DCDC11_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC11_OSC_2M_MODE_AON_POS))
+#define AON_DCDC11_OSC_FREQ_TRIM_AON AON_DCDC11_OSC_FREQ_TRIM_AON
+#define AON_DCDC11_OSC_FREQ_TRIM_AON_POS (12U)
+#define AON_DCDC11_OSC_FREQ_TRIM_AON_LEN (4U)
+#define AON_DCDC11_OSC_FREQ_TRIM_AON_MSK (((1U << AON_DCDC11_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC11_OSC_FREQ_TRIM_AON_POS)
+#define AON_DCDC11_OSC_FREQ_TRIM_AON_UMSK (~(((1U << AON_DCDC11_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC11_OSC_FREQ_TRIM_AON_POS))
+#define AON_DCDC11_PULLDOWN_AON AON_DCDC11_PULLDOWN_AON
+#define AON_DCDC11_PULLDOWN_AON_POS (16U)
+#define AON_DCDC11_PULLDOWN_AON_LEN (1U)
+#define AON_DCDC11_PULLDOWN_AON_MSK (((1U << AON_DCDC11_PULLDOWN_AON_LEN) - 1) << AON_DCDC11_PULLDOWN_AON_POS)
+#define AON_DCDC11_PULLDOWN_AON_UMSK (~(((1U << AON_DCDC11_PULLDOWN_AON_LEN) - 1) << AON_DCDC11_PULLDOWN_AON_POS))
+#define AON_DCDC11_RC_SEL_AON AON_DCDC11_RC_SEL_AON
+#define AON_DCDC11_RC_SEL_AON_POS (20U)
+#define AON_DCDC11_RC_SEL_AON_LEN (4U)
+#define AON_DCDC11_RC_SEL_AON_MSK (((1U << AON_DCDC11_RC_SEL_AON_LEN) - 1) << AON_DCDC11_RC_SEL_AON_POS)
+#define AON_DCDC11_RC_SEL_AON_UMSK (~(((1U << AON_DCDC11_RC_SEL_AON_LEN) - 1) << AON_DCDC11_RC_SEL_AON_POS))
+#define AON_DCDC11_RDY_AON AON_DCDC11_RDY_AON
+#define AON_DCDC11_RDY_AON_POS (24U)
+#define AON_DCDC11_RDY_AON_LEN (1U)
+#define AON_DCDC11_RDY_AON_MSK (((1U << AON_DCDC11_RDY_AON_LEN) - 1) << AON_DCDC11_RDY_AON_POS)
+#define AON_DCDC11_RDY_AON_UMSK (~(((1U << AON_DCDC11_RDY_AON_LEN) - 1) << AON_DCDC11_RDY_AON_POS))
+#define AON_DCDC11_SLOPE_CURR_SEL_AON AON_DCDC11_SLOPE_CURR_SEL_AON
+#define AON_DCDC11_SLOPE_CURR_SEL_AON_POS (26U)
+#define AON_DCDC11_SLOPE_CURR_SEL_AON_LEN (5U)
+#define AON_DCDC11_SLOPE_CURR_SEL_AON_MSK (((1U << AON_DCDC11_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC11_SLOPE_CURR_SEL_AON_POS)
+#define AON_DCDC11_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC11_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC11_SLOPE_CURR_SEL_AON_POS))
+
+/* 0x81C : ldo11soc_and_dctest */
+#define AON_LDO11SOC_AND_DCTEST_OFFSET (0x81C)
+#define AON_DCDC11_CFB_SEL_AON AON_DCDC11_CFB_SEL_AON
+#define AON_DCDC11_CFB_SEL_AON_POS (4U)
+#define AON_DCDC11_CFB_SEL_AON_LEN (4U)
+#define AON_DCDC11_CFB_SEL_AON_MSK (((1U << AON_DCDC11_CFB_SEL_AON_LEN) - 1) << AON_DCDC11_CFB_SEL_AON_POS)
+#define AON_DCDC11_CFB_SEL_AON_UMSK (~(((1U << AON_DCDC11_CFB_SEL_AON_LEN) - 1) << AON_DCDC11_CFB_SEL_AON_POS))
+#define AON_DCDC11_CHF_SEL_AON AON_DCDC11_CHF_SEL_AON
+#define AON_DCDC11_CHF_SEL_AON_POS (8U)
+#define AON_DCDC11_CHF_SEL_AON_LEN (4U)
+#define AON_DCDC11_CHF_SEL_AON_MSK (((1U << AON_DCDC11_CHF_SEL_AON_LEN) - 1) << AON_DCDC11_CHF_SEL_AON_POS)
+#define AON_DCDC11_CHF_SEL_AON_UMSK (~(((1U << AON_DCDC11_CHF_SEL_AON_LEN) - 1) << AON_DCDC11_CHF_SEL_AON_POS))
+#define AON_DCDC11_COMP_GM_SEL_AON AON_DCDC11_COMP_GM_SEL_AON
+#define AON_DCDC11_COMP_GM_SEL_AON_POS (12U)
+#define AON_DCDC11_COMP_GM_SEL_AON_LEN (3U)
+#define AON_DCDC11_COMP_GM_SEL_AON_MSK (((1U << AON_DCDC11_COMP_GM_SEL_AON_LEN) - 1) << AON_DCDC11_COMP_GM_SEL_AON_POS)
+#define AON_DCDC11_COMP_GM_SEL_AON_UMSK (~(((1U << AON_DCDC11_COMP_GM_SEL_AON_LEN) - 1) << AON_DCDC11_COMP_GM_SEL_AON_POS))
+#define AON_DCDC11_CS_DELAY_AON AON_DCDC11_CS_DELAY_AON
+#define AON_DCDC11_CS_DELAY_AON_POS (16U)
+#define AON_DCDC11_CS_DELAY_AON_LEN (3U)
+#define AON_DCDC11_CS_DELAY_AON_MSK (((1U << AON_DCDC11_CS_DELAY_AON_LEN) - 1) << AON_DCDC11_CS_DELAY_AON_POS)
+#define AON_DCDC11_CS_DELAY_AON_UMSK (~(((1U << AON_DCDC11_CS_DELAY_AON_LEN) - 1) << AON_DCDC11_CS_DELAY_AON_POS))
+#define AON_DCDC11_DRV_SR_AON AON_DCDC11_DRV_SR_AON
+#define AON_DCDC11_DRV_SR_AON_POS (20U)
+#define AON_DCDC11_DRV_SR_AON_LEN (2U)
+#define AON_DCDC11_DRV_SR_AON_MSK (((1U << AON_DCDC11_DRV_SR_AON_LEN) - 1) << AON_DCDC11_DRV_SR_AON_POS)
+#define AON_DCDC11_DRV_SR_AON_UMSK (~(((1U << AON_DCDC11_DRV_SR_AON_LEN) - 1) << AON_DCDC11_DRV_SR_AON_POS))
+#define AON_DCDC11_EN_ANTIRING_AON AON_DCDC11_EN_ANTIRING_AON
+#define AON_DCDC11_EN_ANTIRING_AON_POS (22U)
+#define AON_DCDC11_EN_ANTIRING_AON_LEN (1U)
+#define AON_DCDC11_EN_ANTIRING_AON_MSK (((1U << AON_DCDC11_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC11_EN_ANTIRING_AON_POS)
+#define AON_DCDC11_EN_ANTIRING_AON_UMSK (~(((1U << AON_DCDC11_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC11_EN_ANTIRING_AON_POS))
+#define AON_DCDC11_EN_OSC_INHIBIT_T2_AON AON_DCDC11_EN_OSC_INHIBIT_T2_AON
+#define AON_DCDC11_EN_OSC_INHIBIT_T2_AON_POS (23U)
+#define AON_DCDC11_EN_OSC_INHIBIT_T2_AON_LEN (1U)
+#define AON_DCDC11_EN_OSC_INHIBIT_T2_AON_MSK (((1U << AON_DCDC11_EN_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC11_EN_OSC_INHIBIT_T2_AON_POS)
+#define AON_DCDC11_EN_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC11_EN_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC11_EN_OSC_INHIBIT_T2_AON_POS))
+#define AON_DCDC11_EN_SLOW_OSC_AON AON_DCDC11_EN_SLOW_OSC_AON
+#define AON_DCDC11_EN_SLOW_OSC_AON_POS (24U)
+#define AON_DCDC11_EN_SLOW_OSC_AON_LEN (1U)
+#define AON_DCDC11_EN_SLOW_OSC_AON_MSK (((1U << AON_DCDC11_EN_SLOW_OSC_AON_LEN) - 1) << AON_DCDC11_EN_SLOW_OSC_AON_POS)
+#define AON_DCDC11_EN_SLOW_OSC_AON_UMSK (~(((1U << AON_DCDC11_EN_SLOW_OSC_AON_LEN) - 1) << AON_DCDC11_EN_SLOW_OSC_AON_POS))
+#define AON_DCDC11_EN_STBY_LP_AON AON_DCDC11_EN_STBY_LP_AON
+#define AON_DCDC11_EN_STBY_LP_AON_POS (25U)
+#define AON_DCDC11_EN_STBY_LP_AON_LEN (1U)
+#define AON_DCDC11_EN_STBY_LP_AON_MSK (((1U << AON_DCDC11_EN_STBY_LP_AON_LEN) - 1) << AON_DCDC11_EN_STBY_LP_AON_POS)
+#define AON_DCDC11_EN_STBY_LP_AON_UMSK (~(((1U << AON_DCDC11_EN_STBY_LP_AON_LEN) - 1) << AON_DCDC11_EN_STBY_LP_AON_POS))
+#define AON_DCDC11_EN_STOP_OSC_AON AON_DCDC11_EN_STOP_OSC_AON
+#define AON_DCDC11_EN_STOP_OSC_AON_POS (26U)
+#define AON_DCDC11_EN_STOP_OSC_AON_LEN (1U)
+#define AON_DCDC11_EN_STOP_OSC_AON_MSK (((1U << AON_DCDC11_EN_STOP_OSC_AON_LEN) - 1) << AON_DCDC11_EN_STOP_OSC_AON_POS)
+#define AON_DCDC11_EN_STOP_OSC_AON_UMSK (~(((1U << AON_DCDC11_EN_STOP_OSC_AON_LEN) - 1) << AON_DCDC11_EN_STOP_OSC_AON_POS))
+#define AON_DCDC11_FORCE_EN_CS_ZVS_AON AON_DCDC11_FORCE_EN_CS_ZVS_AON
+#define AON_DCDC11_FORCE_EN_CS_ZVS_AON_POS (27U)
+#define AON_DCDC11_FORCE_EN_CS_ZVS_AON_LEN (1U)
+#define AON_DCDC11_FORCE_EN_CS_ZVS_AON_MSK (((1U << AON_DCDC11_FORCE_EN_CS_ZVS_AON_LEN) - 1) << AON_DCDC11_FORCE_EN_CS_ZVS_AON_POS)
+#define AON_DCDC11_FORCE_EN_CS_ZVS_AON_UMSK (~(((1U << AON_DCDC11_FORCE_EN_CS_ZVS_AON_LEN) - 1) << AON_DCDC11_FORCE_EN_CS_ZVS_AON_POS))
+#define AON_DCDC11_ISENSE_TRIM_AON AON_DCDC11_ISENSE_TRIM_AON
+#define AON_DCDC11_ISENSE_TRIM_AON_POS (28U)
+#define AON_DCDC11_ISENSE_TRIM_AON_LEN (3U)
+#define AON_DCDC11_ISENSE_TRIM_AON_MSK (((1U << AON_DCDC11_ISENSE_TRIM_AON_LEN) - 1) << AON_DCDC11_ISENSE_TRIM_AON_POS)
+#define AON_DCDC11_ISENSE_TRIM_AON_UMSK (~(((1U << AON_DCDC11_ISENSE_TRIM_AON_LEN) - 1) << AON_DCDC11_ISENSE_TRIM_AON_POS))
+
+/* 0x820 : move to 0x2000F000[23] */
+#define AON_DCDC18_TOP_0_OFFSET (0x820)
+#define AON_DCDC18_SSTART_TIME_AON AON_DCDC18_SSTART_TIME_AON
+#define AON_DCDC18_SSTART_TIME_AON_POS (0U)
+#define AON_DCDC18_SSTART_TIME_AON_LEN (2U)
+#define AON_DCDC18_SSTART_TIME_AON_MSK (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)
+#define AON_DCDC18_SSTART_TIME_AON_UMSK (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS))
+#define AON_DCDC18_STBY_LP_CUR_AON AON_DCDC18_STBY_LP_CUR_AON
+#define AON_DCDC18_STBY_LP_CUR_AON_POS (4U)
+#define AON_DCDC18_STBY_LP_CUR_AON_LEN (3U)
+#define AON_DCDC18_STBY_LP_CUR_AON_MSK (((1U << AON_DCDC18_STBY_LP_CUR_AON_LEN) - 1) << AON_DCDC18_STBY_LP_CUR_AON_POS)
+#define AON_DCDC18_STBY_LP_CUR_AON_UMSK (~(((1U << AON_DCDC18_STBY_LP_CUR_AON_LEN) - 1) << AON_DCDC18_STBY_LP_CUR_AON_POS))
+#define AON_DCDC18_VC_CLAMP_VTH_AON AON_DCDC18_VC_CLAMP_VTH_AON
+#define AON_DCDC18_VC_CLAMP_VTH_AON_POS (8U)
+#define AON_DCDC18_VC_CLAMP_VTH_AON_LEN (3U)
+#define AON_DCDC18_VC_CLAMP_VTH_AON_MSK (((1U << AON_DCDC18_VC_CLAMP_VTH_AON_LEN) - 1) << AON_DCDC18_VC_CLAMP_VTH_AON_POS)
+#define AON_DCDC18_VC_CLAMP_VTH_AON_UMSK (~(((1U << AON_DCDC18_VC_CLAMP_VTH_AON_LEN) - 1) << AON_DCDC18_VC_CLAMP_VTH_AON_POS))
+#define AON_DCDC18_VOUT_SEL_AON AON_DCDC18_VOUT_SEL_AON
+#define AON_DCDC18_VOUT_SEL_AON_POS (11U)
+#define AON_DCDC18_VOUT_SEL_AON_LEN (5U)
+#define AON_DCDC18_VOUT_SEL_AON_MSK (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)
+#define AON_DCDC18_VOUT_SEL_AON_UMSK (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS))
+#define AON_DCDC18_VOUT_TRIM_AON AON_DCDC18_VOUT_TRIM_AON
+#define AON_DCDC18_VOUT_TRIM_AON_POS (16U)
+#define AON_DCDC18_VOUT_TRIM_AON_LEN (4U)
+#define AON_DCDC18_VOUT_TRIM_AON_MSK (((1U << AON_DCDC18_VOUT_TRIM_AON_LEN) - 1) << AON_DCDC18_VOUT_TRIM_AON_POS)
+#define AON_DCDC18_VOUT_TRIM_AON_UMSK (~(((1U << AON_DCDC18_VOUT_TRIM_AON_LEN) - 1) << AON_DCDC18_VOUT_TRIM_AON_POS))
+#define AON_DCDC18_VPFM_AON AON_DCDC18_VPFM_AON
+#define AON_DCDC18_VPFM_AON_POS (20U)
+#define AON_DCDC18_VPFM_AON_LEN (4U)
+#define AON_DCDC18_VPFM_AON_MSK (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)
+#define AON_DCDC18_VPFM_AON_UMSK (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS))
+#define AON_DCDC18_ZVS_TD_OPT_AON AON_DCDC18_ZVS_TD_OPT_AON
+#define AON_DCDC18_ZVS_TD_OPT_AON_POS (24U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_LEN (3U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_MSK (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)
+#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS))
+#define AON_DCDC18_VSTBY_AON AON_DCDC18_VSTBY_AON
+#define AON_DCDC18_VSTBY_AON_POS (28U)
+#define AON_DCDC18_VSTBY_AON_LEN (2U)
+#define AON_DCDC18_VSTBY_AON_MSK (((1U << AON_DCDC18_VSTBY_AON_LEN) - 1) << AON_DCDC18_VSTBY_AON_POS)
+#define AON_DCDC18_VSTBY_AON_UMSK (~(((1U << AON_DCDC18_VSTBY_AON_LEN) - 1) << AON_DCDC18_VSTBY_AON_POS))
+
+/* 0x824 : dcdc18_top_1 */
+#define AON_DCDC18_TOP_1_OFFSET (0x824)
+#define AON_DCDC18_NONOVERLAP_TD_AON AON_DCDC18_NONOVERLAP_TD_AON
+#define AON_DCDC18_NONOVERLAP_TD_AON_POS (0U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_LEN (5U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_MSK (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)
+#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS))
+#define AON_DCDC18_OCP_OUT_AON AON_DCDC18_OCP_OUT_AON
+#define AON_DCDC18_OCP_OUT_AON_POS (5U)
+#define AON_DCDC18_OCP_OUT_AON_LEN (1U)
+#define AON_DCDC18_OCP_OUT_AON_MSK (((1U << AON_DCDC18_OCP_OUT_AON_LEN) - 1) << AON_DCDC18_OCP_OUT_AON_POS)
+#define AON_DCDC18_OCP_OUT_AON_UMSK (~(((1U << AON_DCDC18_OCP_OUT_AON_LEN) - 1) << AON_DCDC18_OCP_OUT_AON_POS))
+#define AON_DCDC18_OCP_RST_AON AON_DCDC18_OCP_RST_AON
+#define AON_DCDC18_OCP_RST_AON_POS (6U)
+#define AON_DCDC18_OCP_RST_AON_LEN (1U)
+#define AON_DCDC18_OCP_RST_AON_MSK (((1U << AON_DCDC18_OCP_RST_AON_LEN) - 1) << AON_DCDC18_OCP_RST_AON_POS)
+#define AON_DCDC18_OCP_RST_AON_UMSK (~(((1U << AON_DCDC18_OCP_RST_AON_LEN) - 1) << AON_DCDC18_OCP_RST_AON_POS))
+#define AON_DCDC18_OCP_VTH_AON AON_DCDC18_OCP_VTH_AON
+#define AON_DCDC18_OCP_VTH_AON_POS (8U)
+#define AON_DCDC18_OCP_VTH_AON_LEN (3U)
+#define AON_DCDC18_OCP_VTH_AON_MSK (((1U << AON_DCDC18_OCP_VTH_AON_LEN) - 1) << AON_DCDC18_OCP_VTH_AON_POS)
+#define AON_DCDC18_OCP_VTH_AON_UMSK (~(((1U << AON_DCDC18_OCP_VTH_AON_LEN) - 1) << AON_DCDC18_OCP_VTH_AON_POS))
+#define AON_DCDC18_OSC_2M_MODE_AON AON_DCDC18_OSC_2M_MODE_AON
+#define AON_DCDC18_OSC_2M_MODE_AON_POS (11U)
+#define AON_DCDC18_OSC_2M_MODE_AON_LEN (1U)
+#define AON_DCDC18_OSC_2M_MODE_AON_MSK (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)
+#define AON_DCDC18_OSC_2M_MODE_AON_UMSK (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS))
+#define AON_DCDC18_OSC_FREQ_TRIM_AON AON_DCDC18_OSC_FREQ_TRIM_AON
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS (12U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN (4U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS))
+#define AON_DCDC18_PULLDOWN_AON AON_DCDC18_PULLDOWN_AON
+#define AON_DCDC18_PULLDOWN_AON_POS (16U)
+#define AON_DCDC18_PULLDOWN_AON_LEN (1U)
+#define AON_DCDC18_PULLDOWN_AON_MSK (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)
+#define AON_DCDC18_PULLDOWN_AON_UMSK (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS))
+#define AON_DCDC18_RC_SEL_AON AON_DCDC18_RC_SEL_AON
+#define AON_DCDC18_RC_SEL_AON_POS (20U)
+#define AON_DCDC18_RC_SEL_AON_LEN (4U)
+#define AON_DCDC18_RC_SEL_AON_MSK (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)
+#define AON_DCDC18_RC_SEL_AON_UMSK (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS))
+#define AON_DCDC18_RDY_AON AON_DCDC18_RDY_AON
+#define AON_DCDC18_RDY_AON_POS (24U)
+#define AON_DCDC18_RDY_AON_LEN (1U)
+#define AON_DCDC18_RDY_AON_MSK (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)
+#define AON_DCDC18_RDY_AON_UMSK (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS))
+#define AON_DCDC18_SLOPE_CURR_SEL_AON AON_DCDC18_SLOPE_CURR_SEL_AON
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS (26U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN (5U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS))
+
+/* 0x828 : dcdc18_top_2 */
+#define AON_DCDC18_TOP_2_OFFSET (0x828)
+#define AON_DCDC18_CFB_SEL_AON AON_DCDC18_CFB_SEL_AON
+#define AON_DCDC18_CFB_SEL_AON_POS (4U)
+#define AON_DCDC18_CFB_SEL_AON_LEN (4U)
+#define AON_DCDC18_CFB_SEL_AON_MSK (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)
+#define AON_DCDC18_CFB_SEL_AON_UMSK (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS))
+#define AON_DCDC18_CHF_SEL_AON AON_DCDC18_CHF_SEL_AON
+#define AON_DCDC18_CHF_SEL_AON_POS (8U)
+#define AON_DCDC18_CHF_SEL_AON_LEN (4U)
+#define AON_DCDC18_CHF_SEL_AON_MSK (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)
+#define AON_DCDC18_CHF_SEL_AON_UMSK (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS))
+#define AON_DCDC18_COMP_GM_SEL_AON AON_DCDC18_COMP_GM_SEL_AON
+#define AON_DCDC18_COMP_GM_SEL_AON_POS (12U)
+#define AON_DCDC18_COMP_GM_SEL_AON_LEN (3U)
+#define AON_DCDC18_COMP_GM_SEL_AON_MSK (((1U << AON_DCDC18_COMP_GM_SEL_AON_LEN) - 1) << AON_DCDC18_COMP_GM_SEL_AON_POS)
+#define AON_DCDC18_COMP_GM_SEL_AON_UMSK (~(((1U << AON_DCDC18_COMP_GM_SEL_AON_LEN) - 1) << AON_DCDC18_COMP_GM_SEL_AON_POS))
+#define AON_DCDC18_CS_DELAY_AON AON_DCDC18_CS_DELAY_AON
+#define AON_DCDC18_CS_DELAY_AON_POS (16U)
+#define AON_DCDC18_CS_DELAY_AON_LEN (3U)
+#define AON_DCDC18_CS_DELAY_AON_MSK (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)
+#define AON_DCDC18_CS_DELAY_AON_UMSK (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS))
+#define AON_DCDC18_DRV_SR_AON AON_DCDC18_DRV_SR_AON
+#define AON_DCDC18_DRV_SR_AON_POS (20U)
+#define AON_DCDC18_DRV_SR_AON_LEN (2U)
+#define AON_DCDC18_DRV_SR_AON_MSK (((1U << AON_DCDC18_DRV_SR_AON_LEN) - 1) << AON_DCDC18_DRV_SR_AON_POS)
+#define AON_DCDC18_DRV_SR_AON_UMSK (~(((1U << AON_DCDC18_DRV_SR_AON_LEN) - 1) << AON_DCDC18_DRV_SR_AON_POS))
+#define AON_DCDC18_EN_ANTIRING_AON AON_DCDC18_EN_ANTIRING_AON
+#define AON_DCDC18_EN_ANTIRING_AON_POS (22U)
+#define AON_DCDC18_EN_ANTIRING_AON_LEN (1U)
+#define AON_DCDC18_EN_ANTIRING_AON_MSK (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)
+#define AON_DCDC18_EN_ANTIRING_AON_UMSK (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS))
+#define AON_DCDC18_EN_OSC_INHIBIT_T2_AON AON_DCDC18_EN_OSC_INHIBIT_T2_AON
+#define AON_DCDC18_EN_OSC_INHIBIT_T2_AON_POS (23U)
+#define AON_DCDC18_EN_OSC_INHIBIT_T2_AON_LEN (1U)
+#define AON_DCDC18_EN_OSC_INHIBIT_T2_AON_MSK (((1U << AON_DCDC18_EN_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_EN_OSC_INHIBIT_T2_AON_POS)
+#define AON_DCDC18_EN_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_EN_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_EN_OSC_INHIBIT_T2_AON_POS))
+#define AON_DCDC18_EN_SLOW_OSC_AON AON_DCDC18_EN_SLOW_OSC_AON
+#define AON_DCDC18_EN_SLOW_OSC_AON_POS (24U)
+#define AON_DCDC18_EN_SLOW_OSC_AON_LEN (1U)
+#define AON_DCDC18_EN_SLOW_OSC_AON_MSK (((1U << AON_DCDC18_EN_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_EN_SLOW_OSC_AON_POS)
+#define AON_DCDC18_EN_SLOW_OSC_AON_UMSK (~(((1U << AON_DCDC18_EN_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_EN_SLOW_OSC_AON_POS))
+#define AON_DCDC18_EN_STBY_LP_AON AON_DCDC18_EN_STBY_LP_AON
+#define AON_DCDC18_EN_STBY_LP_AON_POS (25U)
+#define AON_DCDC18_EN_STBY_LP_AON_LEN (1U)
+#define AON_DCDC18_EN_STBY_LP_AON_MSK (((1U << AON_DCDC18_EN_STBY_LP_AON_LEN) - 1) << AON_DCDC18_EN_STBY_LP_AON_POS)
+#define AON_DCDC18_EN_STBY_LP_AON_UMSK (~(((1U << AON_DCDC18_EN_STBY_LP_AON_LEN) - 1) << AON_DCDC18_EN_STBY_LP_AON_POS))
+#define AON_DCDC18_EN_STOP_OSC_AON AON_DCDC18_EN_STOP_OSC_AON
+#define AON_DCDC18_EN_STOP_OSC_AON_POS (26U)
+#define AON_DCDC18_EN_STOP_OSC_AON_LEN (1U)
+#define AON_DCDC18_EN_STOP_OSC_AON_MSK (((1U << AON_DCDC18_EN_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_EN_STOP_OSC_AON_POS)
+#define AON_DCDC18_EN_STOP_OSC_AON_UMSK (~(((1U << AON_DCDC18_EN_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_EN_STOP_OSC_AON_POS))
+#define AON_DCDC18_FORCE_EN_CS_ZVS_AON AON_DCDC18_FORCE_EN_CS_ZVS_AON
+#define AON_DCDC18_FORCE_EN_CS_ZVS_AON_POS (27U)
+#define AON_DCDC18_FORCE_EN_CS_ZVS_AON_LEN (1U)
+#define AON_DCDC18_FORCE_EN_CS_ZVS_AON_MSK (((1U << AON_DCDC18_FORCE_EN_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_EN_CS_ZVS_AON_POS)
+#define AON_DCDC18_FORCE_EN_CS_ZVS_AON_UMSK (~(((1U << AON_DCDC18_FORCE_EN_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_EN_CS_ZVS_AON_POS))
+#define AON_DCDC18_ISENSE_TRIM_AON AON_DCDC18_ISENSE_TRIM_AON
+#define AON_DCDC18_ISENSE_TRIM_AON_POS (28U)
+#define AON_DCDC18_ISENSE_TRIM_AON_LEN (3U)
+#define AON_DCDC18_ISENSE_TRIM_AON_MSK (((1U << AON_DCDC18_ISENSE_TRIM_AON_LEN) - 1) << AON_DCDC18_ISENSE_TRIM_AON_POS)
+#define AON_DCDC18_ISENSE_TRIM_AON_UMSK (~(((1U << AON_DCDC18_ISENSE_TRIM_AON_LEN) - 1) << AON_DCDC18_ISENSE_TRIM_AON_POS))
+
+/* 0x82C : psw_irrcv */
+#define AON_PSW_IRRCV_OFFSET (0x82C)
+#define AON_PU_PSW_IRRCV_AON AON_PU_PSW_IRRCV_AON
+#define AON_PU_PSW_IRRCV_AON_POS (0U)
+#define AON_PU_PSW_IRRCV_AON_LEN (1U)
+#define AON_PU_PSW_IRRCV_AON_MSK (((1U << AON_PU_PSW_IRRCV_AON_LEN) - 1) << AON_PU_PSW_IRRCV_AON_POS)
+#define AON_PU_PSW_IRRCV_AON_UMSK (~(((1U << AON_PU_PSW_IRRCV_AON_LEN) - 1) << AON_PU_PSW_IRRCV_AON_POS))
+#define AON_USB20_RREF_EXT_EN_AON AON_USB20_RREF_EXT_EN_AON
+#define AON_USB20_RREF_EXT_EN_AON_POS (19U)
+#define AON_USB20_RREF_EXT_EN_AON_LEN (1U)
+#define AON_USB20_RREF_EXT_EN_AON_MSK (((1U << AON_USB20_RREF_EXT_EN_AON_LEN) - 1) << AON_USB20_RREF_EXT_EN_AON_POS)
+#define AON_USB20_RREF_EXT_EN_AON_UMSK (~(((1U << AON_USB20_RREF_EXT_EN_AON_LEN) - 1) << AON_USB20_RREF_EXT_EN_AON_POS))
+#define AON_EN_POR33_AON AON_EN_POR33_AON
+#define AON_EN_POR33_AON_POS (20U)
+#define AON_EN_POR33_AON_LEN (1U)
+#define AON_EN_POR33_AON_MSK (((1U << AON_EN_POR33_AON_LEN) - 1) << AON_EN_POR33_AON_POS)
+#define AON_EN_POR33_AON_UMSK (~(((1U << AON_EN_POR33_AON_LEN) - 1) << AON_EN_POR33_AON_POS))
+#define AON_USB20_RREF_HIZ_AON AON_USB20_RREF_HIZ_AON
+#define AON_USB20_RREF_HIZ_AON_POS (21U)
+#define AON_USB20_RREF_HIZ_AON_LEN (1U)
+#define AON_USB20_RREF_HIZ_AON_MSK (((1U << AON_USB20_RREF_HIZ_AON_LEN) - 1) << AON_USB20_RREF_HIZ_AON_POS)
+#define AON_USB20_RREF_HIZ_AON_UMSK (~(((1U << AON_USB20_RREF_HIZ_AON_LEN) - 1) << AON_USB20_RREF_HIZ_AON_POS))
+#define AON_USB20_RCAL_CODE_AON AON_USB20_RCAL_CODE_AON
+#define AON_USB20_RCAL_CODE_AON_POS (24U)
+#define AON_USB20_RCAL_CODE_AON_LEN (6U)
+#define AON_USB20_RCAL_CODE_AON_MSK (((1U << AON_USB20_RCAL_CODE_AON_LEN) - 1) << AON_USB20_RCAL_CODE_AON_POS)
+#define AON_USB20_RCAL_CODE_AON_UMSK (~(((1U << AON_USB20_RCAL_CODE_AON_LEN) - 1) << AON_USB20_RCAL_CODE_AON_POS))
+
+/* 0x880 : rf_top_aon */
+#define AON_RF_TOP_AON_OFFSET (0x880)
+#define AON_PU_MBG_AON AON_PU_MBG_AON
+#define AON_PU_MBG_AON_POS (0U)
+#define AON_PU_MBG_AON_LEN (1U)
+#define AON_PU_MBG_AON_MSK (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)
+#define AON_PU_MBG_AON_UMSK (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS))
+#define AON_PU_LDO15RF_AON AON_PU_LDO15RF_AON
+#define AON_PU_LDO15RF_AON_POS (1U)
+#define AON_PU_LDO15RF_AON_LEN (1U)
+#define AON_PU_LDO15RF_AON_MSK (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)
+#define AON_PU_LDO15RF_AON_UMSK (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS))
+#define AON_PU_SFREG_AON AON_PU_SFREG_AON
+#define AON_PU_SFREG_AON_POS (2U)
+#define AON_PU_SFREG_AON_LEN (1U)
+#define AON_PU_SFREG_AON_MSK (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)
+#define AON_PU_SFREG_AON_UMSK (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS))
+#define AON_PU_XTAL_BUF_AON AON_PU_XTAL_BUF_AON
+#define AON_PU_XTAL_BUF_AON_POS (4U)
+#define AON_PU_XTAL_BUF_AON_LEN (1U)
+#define AON_PU_XTAL_BUF_AON_MSK (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)
+#define AON_PU_XTAL_BUF_AON_UMSK (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS))
+#define AON_PU_XTAL_AON AON_PU_XTAL_AON
+#define AON_PU_XTAL_AON_POS (5U)
+#define AON_PU_XTAL_AON_LEN (1U)
+#define AON_PU_XTAL_AON_MSK (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)
+#define AON_PU_XTAL_AON_UMSK (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS))
+#define AON_LDO15RF_SSTART_SEL_AON AON_LDO15RF_SSTART_SEL_AON
+#define AON_LDO15RF_SSTART_SEL_AON_POS (8U)
+#define AON_LDO15RF_SSTART_SEL_AON_LEN (1U)
+#define AON_LDO15RF_SSTART_SEL_AON_MSK (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)
+#define AON_LDO15RF_SSTART_SEL_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS))
+#define AON_LDO15RF_SSTART_DELAY_AON AON_LDO15RF_SSTART_DELAY_AON
+#define AON_LDO15RF_SSTART_DELAY_AON_POS (9U)
+#define AON_LDO15RF_SSTART_DELAY_AON_LEN (2U)
+#define AON_LDO15RF_SSTART_DELAY_AON_MSK (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)
+#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS))
+#define AON_LDO15RF_PULLDOWN_AON AON_LDO15RF_PULLDOWN_AON
+#define AON_LDO15RF_PULLDOWN_AON_POS (12U)
+#define AON_LDO15RF_PULLDOWN_AON_LEN (1U)
+#define AON_LDO15RF_PULLDOWN_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)
+#define AON_LDO15RF_PULLDOWN_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS))
+#define AON_LDO15RF_PULLDOWN_SEL_AON AON_LDO15RF_PULLDOWN_SEL_AON
+#define AON_LDO15RF_PULLDOWN_SEL_AON_POS (13U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN (1U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS))
+#define AON_LDO15RF_VOUT_SEL_AON AON_LDO15RF_VOUT_SEL_AON
+#define AON_LDO15RF_VOUT_SEL_AON_POS (16U)
+#define AON_LDO15RF_VOUT_SEL_AON_LEN (3U)
+#define AON_LDO15RF_VOUT_SEL_AON_MSK (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)
+#define AON_LDO15RF_VOUT_SEL_AON_UMSK (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS))
+#define AON_LDO15RF_CC_AON AON_LDO15RF_CC_AON
+#define AON_LDO15RF_CC_AON_POS (24U)
+#define AON_LDO15RF_CC_AON_LEN (2U)
+#define AON_LDO15RF_CC_AON_MSK (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)
+#define AON_LDO15RF_CC_AON_UMSK (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS))
+#define AON_LDO15RF_BYPASS_AON AON_LDO15RF_BYPASS_AON
+#define AON_LDO15RF_BYPASS_AON_POS (28U)
+#define AON_LDO15RF_BYPASS_AON_LEN (1U)
+#define AON_LDO15RF_BYPASS_AON_MSK (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)
+#define AON_LDO15RF_BYPASS_AON_UMSK (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS))
+
+/* 0x884 : xtal_cfg */
+#define AON_XTAL_CFG_OFFSET (0x884)
+#define AON_XTAL_BK_AON AON_XTAL_BK_AON
+#define AON_XTAL_BK_AON_POS (0U)
+#define AON_XTAL_BK_AON_LEN (2U)
+#define AON_XTAL_BK_AON_MSK (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)
+#define AON_XTAL_BK_AON_UMSK (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS))
+#define AON_XTAL_CAPCODE_EXTRA_AON AON_XTAL_CAPCODE_EXTRA_AON
+#define AON_XTAL_CAPCODE_EXTRA_AON_POS (2U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_LEN (1U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_MSK (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)
+#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS))
+#define AON_XTAL_EXT_SEL_AON AON_XTAL_EXT_SEL_AON
+#define AON_XTAL_EXT_SEL_AON_POS (3U)
+#define AON_XTAL_EXT_SEL_AON_LEN (1U)
+#define AON_XTAL_EXT_SEL_AON_MSK (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)
+#define AON_XTAL_EXT_SEL_AON_UMSK (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS))
+#define AON_XTAL_BUF_EN_AON AON_XTAL_BUF_EN_AON
+#define AON_XTAL_BUF_EN_AON_POS (4U)
+#define AON_XTAL_BUF_EN_AON_LEN (4U)
+#define AON_XTAL_BUF_EN_AON_MSK (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)
+#define AON_XTAL_BUF_EN_AON_UMSK (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS))
+#define AON_XTAL_BUF_HP_AON AON_XTAL_BUF_HP_AON
+#define AON_XTAL_BUF_HP_AON_POS (8U)
+#define AON_XTAL_BUF_HP_AON_LEN (4U)
+#define AON_XTAL_BUF_HP_AON_MSK (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)
+#define AON_XTAL_BUF_HP_AON_UMSK (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS))
+#define AON_XTAL_FAST_STARTUP_AON AON_XTAL_FAST_STARTUP_AON
+#define AON_XTAL_FAST_STARTUP_AON_POS (12U)
+#define AON_XTAL_FAST_STARTUP_AON_LEN (1U)
+#define AON_XTAL_FAST_STARTUP_AON_MSK (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)
+#define AON_XTAL_FAST_STARTUP_AON_UMSK (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS))
+#define AON_XTAL_SLEEP_AON AON_XTAL_SLEEP_AON
+#define AON_XTAL_SLEEP_AON_POS (13U)
+#define AON_XTAL_SLEEP_AON_LEN (1U)
+#define AON_XTAL_SLEEP_AON_MSK (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)
+#define AON_XTAL_SLEEP_AON_UMSK (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS))
+#define AON_XTAL_AMP_CTRL_AON AON_XTAL_AMP_CTRL_AON
+#define AON_XTAL_AMP_CTRL_AON_POS (14U)
+#define AON_XTAL_AMP_CTRL_AON_LEN (2U)
+#define AON_XTAL_AMP_CTRL_AON_MSK (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)
+#define AON_XTAL_AMP_CTRL_AON_UMSK (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS))
+#define AON_XTAL_CAPCODE_OUT_AON AON_XTAL_CAPCODE_OUT_AON
+#define AON_XTAL_CAPCODE_OUT_AON_POS (16U)
+#define AON_XTAL_CAPCODE_OUT_AON_LEN (6U)
+#define AON_XTAL_CAPCODE_OUT_AON_MSK (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)
+#define AON_XTAL_CAPCODE_OUT_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS))
+#define AON_XTAL_CAPCODE_IN_AON AON_XTAL_CAPCODE_IN_AON
+#define AON_XTAL_CAPCODE_IN_AON_POS (22U)
+#define AON_XTAL_CAPCODE_IN_AON_LEN (6U)
+#define AON_XTAL_CAPCODE_IN_AON_MSK (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)
+#define AON_XTAL_CAPCODE_IN_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS))
+#define AON_XTAL_GM_BOOST_AON AON_XTAL_GM_BOOST_AON
+#define AON_XTAL_GM_BOOST_AON_POS (28U)
+#define AON_XTAL_GM_BOOST_AON_LEN (2U)
+#define AON_XTAL_GM_BOOST_AON_MSK (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)
+#define AON_XTAL_GM_BOOST_AON_UMSK (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS))
+#define AON_XTAL_RDY_SEL_AON AON_XTAL_RDY_SEL_AON
+#define AON_XTAL_RDY_SEL_AON_POS (30U)
+#define AON_XTAL_RDY_SEL_AON_LEN (2U)
+#define AON_XTAL_RDY_SEL_AON_MSK (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)
+#define AON_XTAL_RDY_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS))
+
+/* 0x888 : xtal_cfg2 */
+#define AON_XTAL_CFG2_OFFSET (0x888)
+#define AON_WIFI_XTAL_LDO33_BYPASS_AON AON_WIFI_XTAL_LDO33_BYPASS_AON
+#define AON_WIFI_XTAL_LDO33_BYPASS_AON_POS (0U)
+#define AON_WIFI_XTAL_LDO33_BYPASS_AON_LEN (1U)
+#define AON_WIFI_XTAL_LDO33_BYPASS_AON_MSK (((1U << AON_WIFI_XTAL_LDO33_BYPASS_AON_LEN) - 1) << AON_WIFI_XTAL_LDO33_BYPASS_AON_POS)
+#define AON_WIFI_XTAL_LDO33_BYPASS_AON_UMSK (~(((1U << AON_WIFI_XTAL_LDO33_BYPASS_AON_LEN) - 1) << AON_WIFI_XTAL_LDO33_BYPASS_AON_POS))
+#define AON_WIFI_XTAL_LDO33_SEL_AON AON_WIFI_XTAL_LDO33_SEL_AON
+#define AON_WIFI_XTAL_LDO33_SEL_AON_POS (1U)
+#define AON_WIFI_XTAL_LDO33_SEL_AON_LEN (3U)
+#define AON_WIFI_XTAL_LDO33_SEL_AON_MSK (((1U << AON_WIFI_XTAL_LDO33_SEL_AON_LEN) - 1) << AON_WIFI_XTAL_LDO33_SEL_AON_POS)
+#define AON_WIFI_XTAL_LDO33_SEL_AON_UMSK (~(((1U << AON_WIFI_XTAL_LDO33_SEL_AON_LEN) - 1) << AON_WIFI_XTAL_LDO33_SEL_AON_POS))
+#define AON_WIFI_XTAL_LDO18_SEL_AON AON_WIFI_XTAL_LDO18_SEL_AON
+#define AON_WIFI_XTAL_LDO18_SEL_AON_POS (4U)
+#define AON_WIFI_XTAL_LDO18_SEL_AON_LEN (2U)
+#define AON_WIFI_XTAL_LDO18_SEL_AON_MSK (((1U << AON_WIFI_XTAL_LDO18_SEL_AON_LEN) - 1) << AON_WIFI_XTAL_LDO18_SEL_AON_POS)
+#define AON_WIFI_XTAL_LDO18_SEL_AON_UMSK (~(((1U << AON_WIFI_XTAL_LDO18_SEL_AON_LEN) - 1) << AON_WIFI_XTAL_LDO18_SEL_AON_POS))
+#define AON_WIFI_XTAL_LDO33_PU_AON AON_WIFI_XTAL_LDO33_PU_AON
+#define AON_WIFI_XTAL_LDO33_PU_AON_POS (6U)
+#define AON_WIFI_XTAL_LDO33_PU_AON_LEN (1U)
+#define AON_WIFI_XTAL_LDO33_PU_AON_MSK (((1U << AON_WIFI_XTAL_LDO33_PU_AON_LEN) - 1) << AON_WIFI_XTAL_LDO33_PU_AON_POS)
+#define AON_WIFI_XTAL_LDO33_PU_AON_UMSK (~(((1U << AON_WIFI_XTAL_LDO33_PU_AON_LEN) - 1) << AON_WIFI_XTAL_LDO33_PU_AON_POS))
+#define AON_WIFI_XTAL_LDO18_PU_AON AON_WIFI_XTAL_LDO18_PU_AON
+#define AON_WIFI_XTAL_LDO18_PU_AON_POS (7U)
+#define AON_WIFI_XTAL_LDO18_PU_AON_LEN (1U)
+#define AON_WIFI_XTAL_LDO18_PU_AON_MSK (((1U << AON_WIFI_XTAL_LDO18_PU_AON_LEN) - 1) << AON_WIFI_XTAL_LDO18_PU_AON_POS)
+#define AON_WIFI_XTAL_LDO18_PU_AON_UMSK (~(((1U << AON_WIFI_XTAL_LDO18_PU_AON_LEN) - 1) << AON_WIFI_XTAL_LDO18_PU_AON_POS))
+#define AON_WIFI_XTAL_RESERVE AON_WIFI_XTAL_RESERVE
+#define AON_WIFI_XTAL_RESERVE_POS (10U)
+#define AON_WIFI_XTAL_RESERVE_LEN (4U)
+#define AON_WIFI_XTAL_RESERVE_MSK (((1U << AON_WIFI_XTAL_RESERVE_LEN) - 1) << AON_WIFI_XTAL_RESERVE_POS)
+#define AON_WIFI_XTAL_RESERVE_UMSK (~(((1U << AON_WIFI_XTAL_RESERVE_LEN) - 1) << AON_WIFI_XTAL_RESERVE_POS))
+#define AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON
+#define AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_POS (16U)
+#define AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_LEN (1U)
+#define AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_MSK (((1U << AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_LEN) - 1) << AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_POS)
+#define AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_UMSK (~(((1U << AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_LEN) - 1) << AON_WIFI_XTAL_LDO18_SHORT_FILTER_AON_POS))
+#define AON_XTAL_BUF_DRV_AON AON_XTAL_BUF_DRV_AON
+#define AON_XTAL_BUF_DRV_AON_POS (30U)
+#define AON_XTAL_BUF_DRV_AON_LEN (2U)
+#define AON_XTAL_BUF_DRV_AON_MSK (((1U << AON_XTAL_BUF_DRV_AON_LEN) - 1) << AON_XTAL_BUF_DRV_AON_POS)
+#define AON_XTAL_BUF_DRV_AON_UMSK (~(((1U << AON_XTAL_BUF_DRV_AON_LEN) - 1) << AON_XTAL_BUF_DRV_AON_POS))
+
+/* 0x88C : xtal_cfg3 */
+#define AON_XTAL_CFG3_OFFSET (0x88C)
+#define AON_WIFI_XTAL_CLK_INV_EN_AON AON_WIFI_XTAL_CLK_INV_EN_AON
+#define AON_WIFI_XTAL_CLK_INV_EN_AON_POS (12U)
+#define AON_WIFI_XTAL_CLK_INV_EN_AON_LEN (1U)
+#define AON_WIFI_XTAL_CLK_INV_EN_AON_MSK (((1U << AON_WIFI_XTAL_CLK_INV_EN_AON_LEN) - 1) << AON_WIFI_XTAL_CLK_INV_EN_AON_POS)
+#define AON_WIFI_XTAL_CLK_INV_EN_AON_UMSK (~(((1U << AON_WIFI_XTAL_CLK_INV_EN_AON_LEN) - 1) << AON_WIFI_XTAL_CLK_INV_EN_AON_POS))
+#define AON_WIFI_XTAL_CML_EN_AON AON_WIFI_XTAL_CML_EN_AON
+#define AON_WIFI_XTAL_CML_EN_AON_POS (16U)
+#define AON_WIFI_XTAL_CML_EN_AON_LEN (1U)
+#define AON_WIFI_XTAL_CML_EN_AON_MSK (((1U << AON_WIFI_XTAL_CML_EN_AON_LEN) - 1) << AON_WIFI_XTAL_CML_EN_AON_POS)
+#define AON_WIFI_XTAL_CML_EN_AON_UMSK (~(((1U << AON_WIFI_XTAL_CML_EN_AON_LEN) - 1) << AON_WIFI_XTAL_CML_EN_AON_POS))
+#define AON_WIFI_XTAL_CML_R_SEL_AON AON_WIFI_XTAL_CML_R_SEL_AON
+#define AON_WIFI_XTAL_CML_R_SEL_AON_POS (17U)
+#define AON_WIFI_XTAL_CML_R_SEL_AON_LEN (2U)
+#define AON_WIFI_XTAL_CML_R_SEL_AON_MSK (((1U << AON_WIFI_XTAL_CML_R_SEL_AON_LEN) - 1) << AON_WIFI_XTAL_CML_R_SEL_AON_POS)
+#define AON_WIFI_XTAL_CML_R_SEL_AON_UMSK (~(((1U << AON_WIFI_XTAL_CML_R_SEL_AON_LEN) - 1) << AON_WIFI_XTAL_CML_R_SEL_AON_POS))
+#define AON_WIFI_XTAL_CLK_EN_AON AON_WIFI_XTAL_CLK_EN_AON
+#define AON_WIFI_XTAL_CLK_EN_AON_POS (20U)
+#define AON_WIFI_XTAL_CLK_EN_AON_LEN (1U)
+#define AON_WIFI_XTAL_CLK_EN_AON_MSK (((1U << AON_WIFI_XTAL_CLK_EN_AON_LEN) - 1) << AON_WIFI_XTAL_CLK_EN_AON_POS)
+#define AON_WIFI_XTAL_CLK_EN_AON_UMSK (~(((1U << AON_WIFI_XTAL_CLK_EN_AON_LEN) - 1) << AON_WIFI_XTAL_CLK_EN_AON_POS))
+#define AON_WIFI_XTAL_BUF_DRV_AON AON_WIFI_XTAL_BUF_DRV_AON
+#define AON_WIFI_XTAL_BUF_DRV_AON_POS (30U)
+#define AON_WIFI_XTAL_BUF_DRV_AON_LEN (2U)
+#define AON_WIFI_XTAL_BUF_DRV_AON_MSK (((1U << AON_WIFI_XTAL_BUF_DRV_AON_LEN) - 1) << AON_WIFI_XTAL_BUF_DRV_AON_POS)
+#define AON_WIFI_XTAL_BUF_DRV_AON_UMSK (~(((1U << AON_WIFI_XTAL_BUF_DRV_AON_LEN) - 1) << AON_WIFI_XTAL_BUF_DRV_AON_POS))
+
+/* 0x890 : tsen */
+#define AON_TSEN_OFFSET (0x890)
+#define AON_TSEN_REFCODE_CORNER AON_TSEN_REFCODE_CORNER
+#define AON_TSEN_REFCODE_CORNER_POS (0U)
+#define AON_TSEN_REFCODE_CORNER_LEN (12U)
+#define AON_TSEN_REFCODE_CORNER_MSK (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)
+#define AON_TSEN_REFCODE_CORNER_UMSK (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS))
+#define AON_TSEN_REFCODE_RFCAL AON_TSEN_REFCODE_RFCAL
+#define AON_TSEN_REFCODE_RFCAL_POS (16U)
+#define AON_TSEN_REFCODE_RFCAL_LEN (12U)
+#define AON_TSEN_REFCODE_RFCAL_MSK (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)
+#define AON_TSEN_REFCODE_RFCAL_UMSK (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS))
+#define AON_XTAL_RDY AON_XTAL_RDY
+#define AON_XTAL_RDY_POS (28U)
+#define AON_XTAL_RDY_LEN (1U)
+#define AON_XTAL_RDY_MSK (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)
+#define AON_XTAL_RDY_UMSK (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS))
+#define AON_XTAL_INN_CFG_EN_AON AON_XTAL_INN_CFG_EN_AON
+#define AON_XTAL_INN_CFG_EN_AON_POS (29U)
+#define AON_XTAL_INN_CFG_EN_AON_LEN (1U)
+#define AON_XTAL_INN_CFG_EN_AON_MSK (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)
+#define AON_XTAL_INN_CFG_EN_AON_UMSK (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS))
+#define AON_XTAL_RDY_INT_SEL_AON AON_XTAL_RDY_INT_SEL_AON
+#define AON_XTAL_RDY_INT_SEL_AON_POS (30U)
+#define AON_XTAL_RDY_INT_SEL_AON_LEN (2U)
+#define AON_XTAL_RDY_INT_SEL_AON_MSK (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)
+#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS))
+
+/* 0x8C4 : ldo18io */
+#define AON_LDO18IO_OFFSET (0x8C4)
+#define AON_LDO18IO_BYPASS_ISO_AON AON_LDO18IO_BYPASS_ISO_AON
+#define AON_LDO18IO_BYPASS_ISO_AON_POS (1U)
+#define AON_LDO18IO_BYPASS_ISO_AON_LEN (1U)
+#define AON_LDO18IO_BYPASS_ISO_AON_MSK (((1U << AON_LDO18IO_BYPASS_ISO_AON_LEN) - 1) << AON_LDO18IO_BYPASS_ISO_AON_POS)
+#define AON_LDO18IO_BYPASS_ISO_AON_UMSK (~(((1U << AON_LDO18IO_BYPASS_ISO_AON_LEN) - 1) << AON_LDO18IO_BYPASS_ISO_AON_POS))
+#define AON_LDO18IO_PULLDOWN_AON AON_LDO18IO_PULLDOWN_AON
+#define AON_LDO18IO_PULLDOWN_AON_POS (2U)
+#define AON_LDO18IO_PULLDOWN_AON_LEN (1U)
+#define AON_LDO18IO_PULLDOWN_AON_MSK (((1U << AON_LDO18IO_PULLDOWN_AON_LEN) - 1) << AON_LDO18IO_PULLDOWN_AON_POS)
+#define AON_LDO18IO_PULLDOWN_AON_UMSK (~(((1U << AON_LDO18IO_PULLDOWN_AON_LEN) - 1) << AON_LDO18IO_PULLDOWN_AON_POS))
+#define AON_LDO18IO_PULLDOWN_SEL_AON AON_LDO18IO_PULLDOWN_SEL_AON
+#define AON_LDO18IO_PULLDOWN_SEL_AON_POS (3U)
+#define AON_LDO18IO_PULLDOWN_SEL_AON_LEN (1U)
+#define AON_LDO18IO_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO18IO_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO18IO_PULLDOWN_SEL_AON_POS)
+#define AON_LDO18IO_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO18IO_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO18IO_PULLDOWN_SEL_AON_POS))
+#define AON_LDO18IO_BM_AON AON_LDO18IO_BM_AON
+#define AON_LDO18IO_BM_AON_POS (4U)
+#define AON_LDO18IO_BM_AON_LEN (3U)
+#define AON_LDO18IO_BM_AON_MSK (((1U << AON_LDO18IO_BM_AON_LEN) - 1) << AON_LDO18IO_BM_AON_POS)
+#define AON_LDO18IO_BM_AON_UMSK (~(((1U << AON_LDO18IO_BM_AON_LEN) - 1) << AON_LDO18IO_BM_AON_POS))
+#define AON_LDO18IO_CC_AON AON_LDO18IO_CC_AON
+#define AON_LDO18IO_CC_AON_POS (8U)
+#define AON_LDO18IO_CC_AON_LEN (3U)
+#define AON_LDO18IO_CC_AON_MSK (((1U << AON_LDO18IO_CC_AON_LEN) - 1) << AON_LDO18IO_CC_AON_POS)
+#define AON_LDO18IO_CC_AON_UMSK (~(((1U << AON_LDO18IO_CC_AON_LEN) - 1) << AON_LDO18IO_CC_AON_POS))
+#define AON_LDO18IO_OCP_OUT_AON AON_LDO18IO_OCP_OUT_AON
+#define AON_LDO18IO_OCP_OUT_AON_POS (11U)
+#define AON_LDO18IO_OCP_OUT_AON_LEN (1U)
+#define AON_LDO18IO_OCP_OUT_AON_MSK (((1U << AON_LDO18IO_OCP_OUT_AON_LEN) - 1) << AON_LDO18IO_OCP_OUT_AON_POS)
+#define AON_LDO18IO_OCP_OUT_AON_UMSK (~(((1U << AON_LDO18IO_OCP_OUT_AON_LEN) - 1) << AON_LDO18IO_OCP_OUT_AON_POS))
+#define AON_LDO18IO_OCP_TH_AON AON_LDO18IO_OCP_TH_AON
+#define AON_LDO18IO_OCP_TH_AON_POS (12U)
+#define AON_LDO18IO_OCP_TH_AON_LEN (3U)
+#define AON_LDO18IO_OCP_TH_AON_MSK (((1U << AON_LDO18IO_OCP_TH_AON_LEN) - 1) << AON_LDO18IO_OCP_TH_AON_POS)
+#define AON_LDO18IO_OCP_TH_AON_UMSK (~(((1U << AON_LDO18IO_OCP_TH_AON_LEN) - 1) << AON_LDO18IO_OCP_TH_AON_POS))
+#define AON_LDO18IO_OCP_EN_AON AON_LDO18IO_OCP_EN_AON
+#define AON_LDO18IO_OCP_EN_AON_POS (15U)
+#define AON_LDO18IO_OCP_EN_AON_LEN (1U)
+#define AON_LDO18IO_OCP_EN_AON_MSK (((1U << AON_LDO18IO_OCP_EN_AON_LEN) - 1) << AON_LDO18IO_OCP_EN_AON_POS)
+#define AON_LDO18IO_OCP_EN_AON_UMSK (~(((1U << AON_LDO18IO_OCP_EN_AON_LEN) - 1) << AON_LDO18IO_OCP_EN_AON_POS))
+#define AON_LDO18IO_SSTART_DELAY_AON AON_LDO18IO_SSTART_DELAY_AON
+#define AON_LDO18IO_SSTART_DELAY_AON_POS (16U)
+#define AON_LDO18IO_SSTART_DELAY_AON_LEN (3U)
+#define AON_LDO18IO_SSTART_DELAY_AON_MSK (((1U << AON_LDO18IO_SSTART_DELAY_AON_LEN) - 1) << AON_LDO18IO_SSTART_DELAY_AON_POS)
+#define AON_LDO18IO_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO18IO_SSTART_DELAY_AON_LEN) - 1) << AON_LDO18IO_SSTART_DELAY_AON_POS))
+#define AON_LDO18IO_SSTART_EN_AON AON_LDO18IO_SSTART_EN_AON
+#define AON_LDO18IO_SSTART_EN_AON_POS (19U)
+#define AON_LDO18IO_SSTART_EN_AON_LEN (1U)
+#define AON_LDO18IO_SSTART_EN_AON_MSK (((1U << AON_LDO18IO_SSTART_EN_AON_LEN) - 1) << AON_LDO18IO_SSTART_EN_AON_POS)
+#define AON_LDO18IO_SSTART_EN_AON_UMSK (~(((1U << AON_LDO18IO_SSTART_EN_AON_LEN) - 1) << AON_LDO18IO_SSTART_EN_AON_POS))
+#define AON_LDO18IO_VOUT_SEL_AON AON_LDO18IO_VOUT_SEL_AON
+#define AON_LDO18IO_VOUT_SEL_AON_POS (20U)
+#define AON_LDO18IO_VOUT_SEL_AON_LEN (4U)
+#define AON_LDO18IO_VOUT_SEL_AON_MSK (((1U << AON_LDO18IO_VOUT_SEL_AON_LEN) - 1) << AON_LDO18IO_VOUT_SEL_AON_POS)
+#define AON_LDO18IO_VOUT_SEL_AON_UMSK (~(((1U << AON_LDO18IO_VOUT_SEL_AON_LEN) - 1) << AON_LDO18IO_VOUT_SEL_AON_POS))
+#define AON_LDO18IO_VOUT_TRIM_AON AON_LDO18IO_VOUT_TRIM_AON
+#define AON_LDO18IO_VOUT_TRIM_AON_POS (24U)
+#define AON_LDO18IO_VOUT_TRIM_AON_LEN (4U)
+#define AON_LDO18IO_VOUT_TRIM_AON_MSK (((1U << AON_LDO18IO_VOUT_TRIM_AON_LEN) - 1) << AON_LDO18IO_VOUT_TRIM_AON_POS)
+#define AON_LDO18IO_VOUT_TRIM_AON_UMSK (~(((1U << AON_LDO18IO_VOUT_TRIM_AON_LEN) - 1) << AON_LDO18IO_VOUT_TRIM_AON_POS))
+
+/* 0x900 : acomp0_ctrl */
+#define AON_ACOMP0_CTRL_OFFSET (0x900)
+#define AON_ACOMP0_EN AON_ACOMP0_EN
+#define AON_ACOMP0_EN_POS (0U)
+#define AON_ACOMP0_EN_LEN (1U)
+#define AON_ACOMP0_EN_MSK (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)
+#define AON_ACOMP0_EN_UMSK (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS))
+#define AON_ACOMP0_HYST_SELN AON_ACOMP0_HYST_SELN
+#define AON_ACOMP0_HYST_SELN_POS (4U)
+#define AON_ACOMP0_HYST_SELN_LEN (3U)
+#define AON_ACOMP0_HYST_SELN_MSK (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)
+#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS))
+#define AON_ACOMP0_HYST_SELP AON_ACOMP0_HYST_SELP
+#define AON_ACOMP0_HYST_SELP_POS (7U)
+#define AON_ACOMP0_HYST_SELP_LEN (3U)
+#define AON_ACOMP0_HYST_SELP_MSK (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)
+#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS))
+#define AON_ACOMP0_BIAS_PROG AON_ACOMP0_BIAS_PROG
+#define AON_ACOMP0_BIAS_PROG_POS (10U)
+#define AON_ACOMP0_BIAS_PROG_LEN (2U)
+#define AON_ACOMP0_BIAS_PROG_MSK (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)
+#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS))
+#define AON_ACOMP0_LEVEL_SEL AON_ACOMP0_LEVEL_SEL
+#define AON_ACOMP0_LEVEL_SEL_POS (12U)
+#define AON_ACOMP0_LEVEL_SEL_LEN (6U)
+#define AON_ACOMP0_LEVEL_SEL_MSK (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)
+#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS))
+#define AON_ACOMP0_NEG_SEL AON_ACOMP0_NEG_SEL
+#define AON_ACOMP0_NEG_SEL_POS (18U)
+#define AON_ACOMP0_NEG_SEL_LEN (4U)
+#define AON_ACOMP0_NEG_SEL_MSK (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)
+#define AON_ACOMP0_NEG_SEL_UMSK (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS))
+#define AON_ACOMP0_POS_SEL AON_ACOMP0_POS_SEL
+#define AON_ACOMP0_POS_SEL_POS (22U)
+#define AON_ACOMP0_POS_SEL_LEN (4U)
+#define AON_ACOMP0_POS_SEL_MSK (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)
+#define AON_ACOMP0_POS_SEL_UMSK (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS))
+#define AON_ACOMP0_MUXEN AON_ACOMP0_MUXEN
+#define AON_ACOMP0_MUXEN_POS (26U)
+#define AON_ACOMP0_MUXEN_LEN (1U)
+#define AON_ACOMP0_MUXEN_MSK (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)
+#define AON_ACOMP0_MUXEN_UMSK (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS))
+
+/* 0x904 : acomp1_ctrl */
+#define AON_ACOMP1_CTRL_OFFSET (0x904)
+#define AON_ACOMP1_EN AON_ACOMP1_EN
+#define AON_ACOMP1_EN_POS (0U)
+#define AON_ACOMP1_EN_LEN (1U)
+#define AON_ACOMP1_EN_MSK (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)
+#define AON_ACOMP1_EN_UMSK (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS))
+#define AON_ACOMP1_HYST_SELN AON_ACOMP1_HYST_SELN
+#define AON_ACOMP1_HYST_SELN_POS (4U)
+#define AON_ACOMP1_HYST_SELN_LEN (3U)
+#define AON_ACOMP1_HYST_SELN_MSK (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)
+#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS))
+#define AON_ACOMP1_HYST_SELP AON_ACOMP1_HYST_SELP
+#define AON_ACOMP1_HYST_SELP_POS (7U)
+#define AON_ACOMP1_HYST_SELP_LEN (3U)
+#define AON_ACOMP1_HYST_SELP_MSK (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)
+#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS))
+#define AON_ACOMP1_BIAS_PROG AON_ACOMP1_BIAS_PROG
+#define AON_ACOMP1_BIAS_PROG_POS (10U)
+#define AON_ACOMP1_BIAS_PROG_LEN (2U)
+#define AON_ACOMP1_BIAS_PROG_MSK (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)
+#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS))
+#define AON_ACOMP1_LEVEL_SEL AON_ACOMP1_LEVEL_SEL
+#define AON_ACOMP1_LEVEL_SEL_POS (12U)
+#define AON_ACOMP1_LEVEL_SEL_LEN (6U)
+#define AON_ACOMP1_LEVEL_SEL_MSK (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)
+#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS))
+#define AON_ACOMP1_NEG_SEL AON_ACOMP1_NEG_SEL
+#define AON_ACOMP1_NEG_SEL_POS (18U)
+#define AON_ACOMP1_NEG_SEL_LEN (4U)
+#define AON_ACOMP1_NEG_SEL_MSK (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)
+#define AON_ACOMP1_NEG_SEL_UMSK (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS))
+#define AON_ACOMP1_POS_SEL AON_ACOMP1_POS_SEL
+#define AON_ACOMP1_POS_SEL_POS (22U)
+#define AON_ACOMP1_POS_SEL_LEN (4U)
+#define AON_ACOMP1_POS_SEL_MSK (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)
+#define AON_ACOMP1_POS_SEL_UMSK (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS))
+#define AON_ACOMP1_MUXEN AON_ACOMP1_MUXEN
+#define AON_ACOMP1_MUXEN_POS (26U)
+#define AON_ACOMP1_MUXEN_LEN (1U)
+#define AON_ACOMP1_MUXEN_MSK (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)
+#define AON_ACOMP1_MUXEN_UMSK (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS))
+
+/* 0x908 : acomp_ctrl */
+#define AON_ACOMP_CTRL_OFFSET (0x908)
+#define AON_ACOMP1_RSTN_ANA AON_ACOMP1_RSTN_ANA
+#define AON_ACOMP1_RSTN_ANA_POS (0U)
+#define AON_ACOMP1_RSTN_ANA_LEN (1U)
+#define AON_ACOMP1_RSTN_ANA_MSK (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)
+#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS))
+#define AON_ACOMP0_RSTN_ANA AON_ACOMP0_RSTN_ANA
+#define AON_ACOMP0_RSTN_ANA_POS (1U)
+#define AON_ACOMP0_RSTN_ANA_LEN (1U)
+#define AON_ACOMP0_RSTN_ANA_MSK (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)
+#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS))
+#define AON_ACOMP1_TEST_EN AON_ACOMP1_TEST_EN
+#define AON_ACOMP1_TEST_EN_POS (8U)
+#define AON_ACOMP1_TEST_EN_LEN (1U)
+#define AON_ACOMP1_TEST_EN_MSK (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)
+#define AON_ACOMP1_TEST_EN_UMSK (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS))
+#define AON_ACOMP0_TEST_EN AON_ACOMP0_TEST_EN
+#define AON_ACOMP0_TEST_EN_POS (9U)
+#define AON_ACOMP0_TEST_EN_LEN (1U)
+#define AON_ACOMP0_TEST_EN_MSK (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)
+#define AON_ACOMP0_TEST_EN_UMSK (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS))
+#define AON_ACOMP1_TEST_SEL AON_ACOMP1_TEST_SEL
+#define AON_ACOMP1_TEST_SEL_POS (10U)
+#define AON_ACOMP1_TEST_SEL_LEN (2U)
+#define AON_ACOMP1_TEST_SEL_MSK (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)
+#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS))
+#define AON_ACOMP0_TEST_SEL AON_ACOMP0_TEST_SEL
+#define AON_ACOMP0_TEST_SEL_POS (12U)
+#define AON_ACOMP0_TEST_SEL_LEN (2U)
+#define AON_ACOMP0_TEST_SEL_MSK (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)
+#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS))
+#define AON_ACOMP1_OUT_RAW AON_ACOMP1_OUT_RAW
+#define AON_ACOMP1_OUT_RAW_POS (17U)
+#define AON_ACOMP1_OUT_RAW_LEN (1U)
+#define AON_ACOMP1_OUT_RAW_MSK (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)
+#define AON_ACOMP1_OUT_RAW_UMSK (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS))
+#define AON_ACOMP0_OUT_RAW AON_ACOMP0_OUT_RAW
+#define AON_ACOMP0_OUT_RAW_POS (19U)
+#define AON_ACOMP0_OUT_RAW_LEN (1U)
+#define AON_ACOMP0_OUT_RAW_MSK (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)
+#define AON_ACOMP0_OUT_RAW_UMSK (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS))
+#define AON_ACOMP_VREF_SEL AON_ACOMP_VREF_SEL
+#define AON_ACOMP_VREF_SEL_POS (24U)
+#define AON_ACOMP_VREF_SEL_LEN (6U)
+#define AON_ACOMP_VREF_SEL_MSK (((1U << AON_ACOMP_VREF_SEL_LEN) - 1) << AON_ACOMP_VREF_SEL_POS)
+#define AON_ACOMP_VREF_SEL_UMSK (~(((1U << AON_ACOMP_VREF_SEL_LEN) - 1) << AON_ACOMP_VREF_SEL_POS))
+#define AON_ACOMP_RESERVED AON_ACOMP_RESERVED
+#define AON_ACOMP_RESERVED_POS (30U)
+#define AON_ACOMP_RESERVED_LEN (2U)
+#define AON_ACOMP_RESERVED_MSK (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)
+#define AON_ACOMP_RESERVED_UMSK (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS))
+
+/* 0x90C : gpadc_reg_cmd */
+#define AON_GPADC_REG_CMD_OFFSET (0x90C)
+#define AON_GPADC_GLOBAL_EN AON_GPADC_GLOBAL_EN
+#define AON_GPADC_GLOBAL_EN_POS (0U)
+#define AON_GPADC_GLOBAL_EN_LEN (1U)
+#define AON_GPADC_GLOBAL_EN_MSK (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)
+#define AON_GPADC_GLOBAL_EN_UMSK (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS))
+#define AON_GPADC_CONV_START AON_GPADC_CONV_START
+#define AON_GPADC_CONV_START_POS (1U)
+#define AON_GPADC_CONV_START_LEN (1U)
+#define AON_GPADC_CONV_START_MSK (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)
+#define AON_GPADC_CONV_START_UMSK (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS))
+#define AON_GPADC_SOFT_RST AON_GPADC_SOFT_RST
+#define AON_GPADC_SOFT_RST_POS (2U)
+#define AON_GPADC_SOFT_RST_LEN (1U)
+#define AON_GPADC_SOFT_RST_MSK (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)
+#define AON_GPADC_SOFT_RST_UMSK (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS))
+#define AON_GPADC_NEG_SEL AON_GPADC_NEG_SEL
+#define AON_GPADC_NEG_SEL_POS (3U)
+#define AON_GPADC_NEG_SEL_LEN (5U)
+#define AON_GPADC_NEG_SEL_MSK (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)
+#define AON_GPADC_NEG_SEL_UMSK (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS))
+#define AON_GPADC_POS_SEL AON_GPADC_POS_SEL
+#define AON_GPADC_POS_SEL_POS (8U)
+#define AON_GPADC_POS_SEL_LEN (5U)
+#define AON_GPADC_POS_SEL_MSK (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)
+#define AON_GPADC_POS_SEL_UMSK (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS))
+#define AON_GPADC_NEG_GND AON_GPADC_NEG_GND
+#define AON_GPADC_NEG_GND_POS (13U)
+#define AON_GPADC_NEG_GND_LEN (1U)
+#define AON_GPADC_NEG_GND_MSK (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)
+#define AON_GPADC_NEG_GND_UMSK (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS))
+#define AON_GPADC_MICBIAS_EN AON_GPADC_MICBIAS_EN
+#define AON_GPADC_MICBIAS_EN_POS (14U)
+#define AON_GPADC_MICBIAS_EN_LEN (1U)
+#define AON_GPADC_MICBIAS_EN_MSK (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)
+#define AON_GPADC_MICBIAS_EN_UMSK (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS))
+#define AON_GPADC_MICPGA_EN AON_GPADC_MICPGA_EN
+#define AON_GPADC_MICPGA_EN_POS (15U)
+#define AON_GPADC_MICPGA_EN_LEN (1U)
+#define AON_GPADC_MICPGA_EN_MSK (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)
+#define AON_GPADC_MICPGA_EN_UMSK (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS))
+#define AON_GPADC_BYP_MICBOOST AON_GPADC_BYP_MICBOOST
+#define AON_GPADC_BYP_MICBOOST_POS (16U)
+#define AON_GPADC_BYP_MICBOOST_LEN (1U)
+#define AON_GPADC_BYP_MICBOOST_MSK (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)
+#define AON_GPADC_BYP_MICBOOST_UMSK (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS))
+#define AON_GPADC_RCAL_EN AON_GPADC_RCAL_EN
+#define AON_GPADC_RCAL_EN_POS (17U)
+#define AON_GPADC_RCAL_EN_LEN (1U)
+#define AON_GPADC_RCAL_EN_MSK (((1U << AON_GPADC_RCAL_EN_LEN) - 1) << AON_GPADC_RCAL_EN_POS)
+#define AON_GPADC_RCAL_EN_UMSK (~(((1U << AON_GPADC_RCAL_EN_LEN) - 1) << AON_GPADC_RCAL_EN_POS))
+#define AON_GPADC_DWA_EN AON_GPADC_DWA_EN
+#define AON_GPADC_DWA_EN_POS (18U)
+#define AON_GPADC_DWA_EN_LEN (1U)
+#define AON_GPADC_DWA_EN_MSK (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)
+#define AON_GPADC_DWA_EN_UMSK (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS))
+#define AON_GPADC_MIC2_DIFF AON_GPADC_MIC2_DIFF
+#define AON_GPADC_MIC2_DIFF_POS (19U)
+#define AON_GPADC_MIC2_DIFF_LEN (1U)
+#define AON_GPADC_MIC2_DIFF_MSK (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)
+#define AON_GPADC_MIC2_DIFF_UMSK (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS))
+#define AON_GPADC_MIC1_DIFF AON_GPADC_MIC1_DIFF
+#define AON_GPADC_MIC1_DIFF_POS (20U)
+#define AON_GPADC_MIC1_DIFF_LEN (1U)
+#define AON_GPADC_MIC1_DIFF_MSK (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)
+#define AON_GPADC_MIC1_DIFF_UMSK (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS))
+#define AON_GPADC_MIC_PGA2_GAIN AON_GPADC_MIC_PGA2_GAIN
+#define AON_GPADC_MIC_PGA2_GAIN_POS (21U)
+#define AON_GPADC_MIC_PGA2_GAIN_LEN (2U)
+#define AON_GPADC_MIC_PGA2_GAIN_MSK (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)
+#define AON_GPADC_MIC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS))
+#define AON_GPADC_MICBOOST_32DB_EN AON_GPADC_MICBOOST_32DB_EN
+#define AON_GPADC_MICBOOST_32DB_EN_POS (23U)
+#define AON_GPADC_MICBOOST_32DB_EN_LEN (1U)
+#define AON_GPADC_MICBOOST_32DB_EN_MSK (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)
+#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS))
+#define AON_GPADC_CHIP_SEN_PU AON_GPADC_CHIP_SEN_PU
+#define AON_GPADC_CHIP_SEN_PU_POS (27U)
+#define AON_GPADC_CHIP_SEN_PU_LEN (1U)
+#define AON_GPADC_CHIP_SEN_PU_MSK (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)
+#define AON_GPADC_CHIP_SEN_PU_UMSK (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS))
+#define AON_GPADC_SEN_SEL AON_GPADC_SEN_SEL
+#define AON_GPADC_SEN_SEL_POS (28U)
+#define AON_GPADC_SEN_SEL_LEN (3U)
+#define AON_GPADC_SEN_SEL_MSK (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)
+#define AON_GPADC_SEN_SEL_UMSK (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS))
+#define AON_GPADC_SEN_TEST_EN AON_GPADC_SEN_TEST_EN
+#define AON_GPADC_SEN_TEST_EN_POS (31U)
+#define AON_GPADC_SEN_TEST_EN_LEN (1U)
+#define AON_GPADC_SEN_TEST_EN_MSK (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)
+#define AON_GPADC_SEN_TEST_EN_UMSK (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS))
+
+/* 0x910 : gpadc_reg_config1 */
+#define AON_GPADC_REG_CONFIG1_OFFSET (0x910)
+#define AON_GPADC_CAL_OS_EN AON_GPADC_CAL_OS_EN
+#define AON_GPADC_CAL_OS_EN_POS (0U)
+#define AON_GPADC_CAL_OS_EN_LEN (1U)
+#define AON_GPADC_CAL_OS_EN_MSK (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)
+#define AON_GPADC_CAL_OS_EN_UMSK (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS))
+#define AON_GPADC_CONT_CONV_EN AON_GPADC_CONT_CONV_EN
+#define AON_GPADC_CONT_CONV_EN_POS (1U)
+#define AON_GPADC_CONT_CONV_EN_LEN (1U)
+#define AON_GPADC_CONT_CONV_EN_MSK (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)
+#define AON_GPADC_CONT_CONV_EN_UMSK (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS))
+#define AON_GPADC_RES_SEL AON_GPADC_RES_SEL
+#define AON_GPADC_RES_SEL_POS (2U)
+#define AON_GPADC_RES_SEL_LEN (3U)
+#define AON_GPADC_RES_SEL_MSK (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)
+#define AON_GPADC_RES_SEL_UMSK (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS))
+#define AON_GPADC_VCM_SEL_EN AON_GPADC_VCM_SEL_EN
+#define AON_GPADC_VCM_SEL_EN_POS (8U)
+#define AON_GPADC_VCM_SEL_EN_LEN (1U)
+#define AON_GPADC_VCM_SEL_EN_MSK (((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS)
+#define AON_GPADC_VCM_SEL_EN_UMSK (~(((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS))
+#define AON_GPADC_VCM_HYST_SEL AON_GPADC_VCM_HYST_SEL
+#define AON_GPADC_VCM_HYST_SEL_POS (9U)
+#define AON_GPADC_VCM_HYST_SEL_LEN (1U)
+#define AON_GPADC_VCM_HYST_SEL_MSK (((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS)
+#define AON_GPADC_VCM_HYST_SEL_UMSK (~(((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS))
+#define AON_GPADC_LOWV_DET_EN AON_GPADC_LOWV_DET_EN
+#define AON_GPADC_LOWV_DET_EN_POS (10U)
+#define AON_GPADC_LOWV_DET_EN_LEN (1U)
+#define AON_GPADC_LOWV_DET_EN_MSK (((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS)
+#define AON_GPADC_LOWV_DET_EN_UMSK (~(((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS))
+#define AON_GPADC_PWM_TRG_EN AON_GPADC_PWM_TRG_EN
+#define AON_GPADC_PWM_TRG_EN_POS (11U)
+#define AON_GPADC_PWM_TRG_EN_LEN (1U)
+#define AON_GPADC_PWM_TRG_EN_MSK (((1U << AON_GPADC_PWM_TRG_EN_LEN) - 1) << AON_GPADC_PWM_TRG_EN_POS)
+#define AON_GPADC_PWM_TRG_EN_UMSK (~(((1U << AON_GPADC_PWM_TRG_EN_LEN) - 1) << AON_GPADC_PWM_TRG_EN_POS))
+#define AON_GPADC_CLK_ANA_DLY AON_GPADC_CLK_ANA_DLY
+#define AON_GPADC_CLK_ANA_DLY_POS (12U)
+#define AON_GPADC_CLK_ANA_DLY_LEN (4U)
+#define AON_GPADC_CLK_ANA_DLY_MSK (((1U << AON_GPADC_CLK_ANA_DLY_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_POS)
+#define AON_GPADC_CLK_ANA_DLY_UMSK (~(((1U << AON_GPADC_CLK_ANA_DLY_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_POS))
+#define AON_GPADC_CLK_ANA_DLY_EN AON_GPADC_CLK_ANA_DLY_EN
+#define AON_GPADC_CLK_ANA_DLY_EN_POS (16U)
+#define AON_GPADC_CLK_ANA_DLY_EN_LEN (1U)
+#define AON_GPADC_CLK_ANA_DLY_EN_MSK (((1U << AON_GPADC_CLK_ANA_DLY_EN_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_EN_POS)
+#define AON_GPADC_CLK_ANA_DLY_EN_UMSK (~(((1U << AON_GPADC_CLK_ANA_DLY_EN_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_EN_POS))
+#define AON_GPADC_CLK_ANA_INV AON_GPADC_CLK_ANA_INV
+#define AON_GPADC_CLK_ANA_INV_POS (17U)
+#define AON_GPADC_CLK_ANA_INV_LEN (1U)
+#define AON_GPADC_CLK_ANA_INV_MSK (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)
+#define AON_GPADC_CLK_ANA_INV_UMSK (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS))
+#define AON_GPADC_CLK_DIV_RATIO AON_GPADC_CLK_DIV_RATIO
+#define AON_GPADC_CLK_DIV_RATIO_POS (18U)
+#define AON_GPADC_CLK_DIV_RATIO_LEN (3U)
+#define AON_GPADC_CLK_DIV_RATIO_MSK (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)
+#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS))
+#define AON_GPADC_SCAN_LENGTH AON_GPADC_SCAN_LENGTH
+#define AON_GPADC_SCAN_LENGTH_POS (21U)
+#define AON_GPADC_SCAN_LENGTH_LEN (4U)
+#define AON_GPADC_SCAN_LENGTH_MSK (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)
+#define AON_GPADC_SCAN_LENGTH_UMSK (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS))
+#define AON_GPADC_SCAN_EN AON_GPADC_SCAN_EN
+#define AON_GPADC_SCAN_EN_POS (25U)
+#define AON_GPADC_SCAN_EN_LEN (1U)
+#define AON_GPADC_SCAN_EN_MSK (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)
+#define AON_GPADC_SCAN_EN_UMSK (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS))
+#define AON_GPADC_DITHER_EN AON_GPADC_DITHER_EN
+#define AON_GPADC_DITHER_EN_POS (26U)
+#define AON_GPADC_DITHER_EN_LEN (1U)
+#define AON_GPADC_DITHER_EN_MSK (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)
+#define AON_GPADC_DITHER_EN_UMSK (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS))
+#define AON_GPADC_V11_SEL AON_GPADC_V11_SEL
+#define AON_GPADC_V11_SEL_POS (27U)
+#define AON_GPADC_V11_SEL_LEN (2U)
+#define AON_GPADC_V11_SEL_MSK (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)
+#define AON_GPADC_V11_SEL_UMSK (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS))
+#define AON_GPADC_V18_SEL AON_GPADC_V18_SEL
+#define AON_GPADC_V18_SEL_POS (29U)
+#define AON_GPADC_V18_SEL_LEN (2U)
+#define AON_GPADC_V18_SEL_MSK (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)
+#define AON_GPADC_V18_SEL_UMSK (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS))
+
+/* 0x914 : gpadc_reg_config2 */
+#define AON_GPADC_REG_CONFIG2_OFFSET (0x914)
+#define AON_GPADC_DIFF_MODE AON_GPADC_DIFF_MODE
+#define AON_GPADC_DIFF_MODE_POS (2U)
+#define AON_GPADC_DIFF_MODE_LEN (1U)
+#define AON_GPADC_DIFF_MODE_MSK (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)
+#define AON_GPADC_DIFF_MODE_UMSK (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS))
+#define AON_GPADC_VREF_SEL AON_GPADC_VREF_SEL
+#define AON_GPADC_VREF_SEL_POS (3U)
+#define AON_GPADC_VREF_SEL_LEN (1U)
+#define AON_GPADC_VREF_SEL_MSK (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)
+#define AON_GPADC_VREF_SEL_UMSK (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS))
+#define AON_GPADC_VBAT_EN AON_GPADC_VBAT_EN
+#define AON_GPADC_VBAT_EN_POS (4U)
+#define AON_GPADC_VBAT_EN_LEN (1U)
+#define AON_GPADC_VBAT_EN_MSK (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)
+#define AON_GPADC_VBAT_EN_UMSK (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS))
+#define AON_GPADC_TSEXT_SEL AON_GPADC_TSEXT_SEL
+#define AON_GPADC_TSEXT_SEL_POS (5U)
+#define AON_GPADC_TSEXT_SEL_LEN (1U)
+#define AON_GPADC_TSEXT_SEL_MSK (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)
+#define AON_GPADC_TSEXT_SEL_UMSK (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS))
+#define AON_GPADC_TS_EN AON_GPADC_TS_EN
+#define AON_GPADC_TS_EN_POS (6U)
+#define AON_GPADC_TS_EN_LEN (1U)
+#define AON_GPADC_TS_EN_MSK (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)
+#define AON_GPADC_TS_EN_UMSK (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS))
+#define AON_GPADC_PGA_VCM AON_GPADC_PGA_VCM
+#define AON_GPADC_PGA_VCM_POS (7U)
+#define AON_GPADC_PGA_VCM_LEN (2U)
+#define AON_GPADC_PGA_VCM_MSK (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)
+#define AON_GPADC_PGA_VCM_UMSK (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS))
+#define AON_GPADC_PGA_OS_CAL AON_GPADC_PGA_OS_CAL
+#define AON_GPADC_PGA_OS_CAL_POS (9U)
+#define AON_GPADC_PGA_OS_CAL_LEN (4U)
+#define AON_GPADC_PGA_OS_CAL_MSK (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)
+#define AON_GPADC_PGA_OS_CAL_UMSK (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS))
+#define AON_GPADC_PGA_EN AON_GPADC_PGA_EN
+#define AON_GPADC_PGA_EN_POS (13U)
+#define AON_GPADC_PGA_EN_LEN (1U)
+#define AON_GPADC_PGA_EN_MSK (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)
+#define AON_GPADC_PGA_EN_UMSK (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS))
+#define AON_GPADC_PGA_VCMI_EN AON_GPADC_PGA_VCMI_EN
+#define AON_GPADC_PGA_VCMI_EN_POS (14U)
+#define AON_GPADC_PGA_VCMI_EN_LEN (1U)
+#define AON_GPADC_PGA_VCMI_EN_MSK (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)
+#define AON_GPADC_PGA_VCMI_EN_UMSK (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS))
+#define AON_GPADC_CHOP_MODE AON_GPADC_CHOP_MODE
+#define AON_GPADC_CHOP_MODE_POS (15U)
+#define AON_GPADC_CHOP_MODE_LEN (2U)
+#define AON_GPADC_CHOP_MODE_MSK (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)
+#define AON_GPADC_CHOP_MODE_UMSK (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS))
+#define AON_GPADC_BIAS_SEL AON_GPADC_BIAS_SEL
+#define AON_GPADC_BIAS_SEL_POS (17U)
+#define AON_GPADC_BIAS_SEL_LEN (1U)
+#define AON_GPADC_BIAS_SEL_MSK (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)
+#define AON_GPADC_BIAS_SEL_UMSK (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS))
+#define AON_GPADC_TEST_EN AON_GPADC_TEST_EN
+#define AON_GPADC_TEST_EN_POS (18U)
+#define AON_GPADC_TEST_EN_LEN (1U)
+#define AON_GPADC_TEST_EN_MSK (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)
+#define AON_GPADC_TEST_EN_UMSK (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS))
+#define AON_GPADC_TEST_SEL AON_GPADC_TEST_SEL
+#define AON_GPADC_TEST_SEL_POS (19U)
+#define AON_GPADC_TEST_SEL_LEN (3U)
+#define AON_GPADC_TEST_SEL_MSK (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)
+#define AON_GPADC_TEST_SEL_UMSK (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS))
+#define AON_GPADC_PGA2_GAIN AON_GPADC_PGA2_GAIN
+#define AON_GPADC_PGA2_GAIN_POS (22U)
+#define AON_GPADC_PGA2_GAIN_LEN (3U)
+#define AON_GPADC_PGA2_GAIN_MSK (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)
+#define AON_GPADC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS))
+#define AON_GPADC_PGA1_GAIN AON_GPADC_PGA1_GAIN
+#define AON_GPADC_PGA1_GAIN_POS (25U)
+#define AON_GPADC_PGA1_GAIN_LEN (3U)
+#define AON_GPADC_PGA1_GAIN_MSK (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)
+#define AON_GPADC_PGA1_GAIN_UMSK (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS))
+#define AON_GPADC_DLY_SEL AON_GPADC_DLY_SEL
+#define AON_GPADC_DLY_SEL_POS (28U)
+#define AON_GPADC_DLY_SEL_LEN (3U)
+#define AON_GPADC_DLY_SEL_MSK (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)
+#define AON_GPADC_DLY_SEL_UMSK (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS))
+#define AON_GPADC_TSVBE_LOW AON_GPADC_TSVBE_LOW
+#define AON_GPADC_TSVBE_LOW_POS (31U)
+#define AON_GPADC_TSVBE_LOW_LEN (1U)
+#define AON_GPADC_TSVBE_LOW_MSK (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)
+#define AON_GPADC_TSVBE_LOW_UMSK (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS))
+
+/* 0x918 : adc converation sequence 1 */
+#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918)
+#define AON_GPADC_SCAN_POS_0 AON_GPADC_SCAN_POS_0
+#define AON_GPADC_SCAN_POS_0_POS (0U)
+#define AON_GPADC_SCAN_POS_0_LEN (5U)
+#define AON_GPADC_SCAN_POS_0_MSK (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)
+#define AON_GPADC_SCAN_POS_0_UMSK (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS))
+#define AON_GPADC_SCAN_POS_1 AON_GPADC_SCAN_POS_1
+#define AON_GPADC_SCAN_POS_1_POS (5U)
+#define AON_GPADC_SCAN_POS_1_LEN (5U)
+#define AON_GPADC_SCAN_POS_1_MSK (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)
+#define AON_GPADC_SCAN_POS_1_UMSK (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS))
+#define AON_GPADC_SCAN_POS_2 AON_GPADC_SCAN_POS_2
+#define AON_GPADC_SCAN_POS_2_POS (10U)
+#define AON_GPADC_SCAN_POS_2_LEN (5U)
+#define AON_GPADC_SCAN_POS_2_MSK (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)
+#define AON_GPADC_SCAN_POS_2_UMSK (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS))
+#define AON_GPADC_SCAN_POS_3 AON_GPADC_SCAN_POS_3
+#define AON_GPADC_SCAN_POS_3_POS (15U)
+#define AON_GPADC_SCAN_POS_3_LEN (5U)
+#define AON_GPADC_SCAN_POS_3_MSK (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)
+#define AON_GPADC_SCAN_POS_3_UMSK (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS))
+#define AON_GPADC_SCAN_POS_4 AON_GPADC_SCAN_POS_4
+#define AON_GPADC_SCAN_POS_4_POS (20U)
+#define AON_GPADC_SCAN_POS_4_LEN (5U)
+#define AON_GPADC_SCAN_POS_4_MSK (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)
+#define AON_GPADC_SCAN_POS_4_UMSK (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS))
+#define AON_GPADC_SCAN_POS_5 AON_GPADC_SCAN_POS_5
+#define AON_GPADC_SCAN_POS_5_POS (25U)
+#define AON_GPADC_SCAN_POS_5_LEN (5U)
+#define AON_GPADC_SCAN_POS_5_MSK (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)
+#define AON_GPADC_SCAN_POS_5_UMSK (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS))
+
+/* 0x91C : adc converation sequence 2 */
+#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C)
+#define AON_GPADC_SCAN_POS_6 AON_GPADC_SCAN_POS_6
+#define AON_GPADC_SCAN_POS_6_POS (0U)
+#define AON_GPADC_SCAN_POS_6_LEN (5U)
+#define AON_GPADC_SCAN_POS_6_MSK (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)
+#define AON_GPADC_SCAN_POS_6_UMSK (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS))
+#define AON_GPADC_SCAN_POS_7 AON_GPADC_SCAN_POS_7
+#define AON_GPADC_SCAN_POS_7_POS (5U)
+#define AON_GPADC_SCAN_POS_7_LEN (5U)
+#define AON_GPADC_SCAN_POS_7_MSK (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)
+#define AON_GPADC_SCAN_POS_7_UMSK (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS))
+#define AON_GPADC_SCAN_POS_8 AON_GPADC_SCAN_POS_8
+#define AON_GPADC_SCAN_POS_8_POS (10U)
+#define AON_GPADC_SCAN_POS_8_LEN (5U)
+#define AON_GPADC_SCAN_POS_8_MSK (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)
+#define AON_GPADC_SCAN_POS_8_UMSK (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS))
+#define AON_GPADC_SCAN_POS_9 AON_GPADC_SCAN_POS_9
+#define AON_GPADC_SCAN_POS_9_POS (15U)
+#define AON_GPADC_SCAN_POS_9_LEN (5U)
+#define AON_GPADC_SCAN_POS_9_MSK (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)
+#define AON_GPADC_SCAN_POS_9_UMSK (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS))
+#define AON_GPADC_SCAN_POS_10 AON_GPADC_SCAN_POS_10
+#define AON_GPADC_SCAN_POS_10_POS (20U)
+#define AON_GPADC_SCAN_POS_10_LEN (5U)
+#define AON_GPADC_SCAN_POS_10_MSK (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)
+#define AON_GPADC_SCAN_POS_10_UMSK (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS))
+#define AON_GPADC_SCAN_POS_11 AON_GPADC_SCAN_POS_11
+#define AON_GPADC_SCAN_POS_11_POS (25U)
+#define AON_GPADC_SCAN_POS_11_LEN (5U)
+#define AON_GPADC_SCAN_POS_11_MSK (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)
+#define AON_GPADC_SCAN_POS_11_UMSK (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS))
+
+/* 0x920 : adc converation sequence 3 */
+#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920)
+#define AON_GPADC_SCAN_NEG_0 AON_GPADC_SCAN_NEG_0
+#define AON_GPADC_SCAN_NEG_0_POS (0U)
+#define AON_GPADC_SCAN_NEG_0_LEN (5U)
+#define AON_GPADC_SCAN_NEG_0_MSK (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)
+#define AON_GPADC_SCAN_NEG_0_UMSK (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS))
+#define AON_GPADC_SCAN_NEG_1 AON_GPADC_SCAN_NEG_1
+#define AON_GPADC_SCAN_NEG_1_POS (5U)
+#define AON_GPADC_SCAN_NEG_1_LEN (5U)
+#define AON_GPADC_SCAN_NEG_1_MSK (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)
+#define AON_GPADC_SCAN_NEG_1_UMSK (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS))
+#define AON_GPADC_SCAN_NEG_2 AON_GPADC_SCAN_NEG_2
+#define AON_GPADC_SCAN_NEG_2_POS (10U)
+#define AON_GPADC_SCAN_NEG_2_LEN (5U)
+#define AON_GPADC_SCAN_NEG_2_MSK (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)
+#define AON_GPADC_SCAN_NEG_2_UMSK (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS))
+#define AON_GPADC_SCAN_NEG_3 AON_GPADC_SCAN_NEG_3
+#define AON_GPADC_SCAN_NEG_3_POS (15U)
+#define AON_GPADC_SCAN_NEG_3_LEN (5U)
+#define AON_GPADC_SCAN_NEG_3_MSK (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)
+#define AON_GPADC_SCAN_NEG_3_UMSK (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS))
+#define AON_GPADC_SCAN_NEG_4 AON_GPADC_SCAN_NEG_4
+#define AON_GPADC_SCAN_NEG_4_POS (20U)
+#define AON_GPADC_SCAN_NEG_4_LEN (5U)
+#define AON_GPADC_SCAN_NEG_4_MSK (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)
+#define AON_GPADC_SCAN_NEG_4_UMSK (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS))
+#define AON_GPADC_SCAN_NEG_5 AON_GPADC_SCAN_NEG_5
+#define AON_GPADC_SCAN_NEG_5_POS (25U)
+#define AON_GPADC_SCAN_NEG_5_LEN (5U)
+#define AON_GPADC_SCAN_NEG_5_MSK (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)
+#define AON_GPADC_SCAN_NEG_5_UMSK (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS))
+
+/* 0x924 : adc converation sequence 4 */
+#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924)
+#define AON_GPADC_SCAN_NEG_6 AON_GPADC_SCAN_NEG_6
+#define AON_GPADC_SCAN_NEG_6_POS (0U)
+#define AON_GPADC_SCAN_NEG_6_LEN (5U)
+#define AON_GPADC_SCAN_NEG_6_MSK (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)
+#define AON_GPADC_SCAN_NEG_6_UMSK (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS))
+#define AON_GPADC_SCAN_NEG_7 AON_GPADC_SCAN_NEG_7
+#define AON_GPADC_SCAN_NEG_7_POS (5U)
+#define AON_GPADC_SCAN_NEG_7_LEN (5U)
+#define AON_GPADC_SCAN_NEG_7_MSK (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)
+#define AON_GPADC_SCAN_NEG_7_UMSK (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS))
+#define AON_GPADC_SCAN_NEG_8 AON_GPADC_SCAN_NEG_8
+#define AON_GPADC_SCAN_NEG_8_POS (10U)
+#define AON_GPADC_SCAN_NEG_8_LEN (5U)
+#define AON_GPADC_SCAN_NEG_8_MSK (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)
+#define AON_GPADC_SCAN_NEG_8_UMSK (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS))
+#define AON_GPADC_SCAN_NEG_9 AON_GPADC_SCAN_NEG_9
+#define AON_GPADC_SCAN_NEG_9_POS (15U)
+#define AON_GPADC_SCAN_NEG_9_LEN (5U)
+#define AON_GPADC_SCAN_NEG_9_MSK (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)
+#define AON_GPADC_SCAN_NEG_9_UMSK (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS))
+#define AON_GPADC_SCAN_NEG_10 AON_GPADC_SCAN_NEG_10
+#define AON_GPADC_SCAN_NEG_10_POS (20U)
+#define AON_GPADC_SCAN_NEG_10_LEN (5U)
+#define AON_GPADC_SCAN_NEG_10_MSK (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)
+#define AON_GPADC_SCAN_NEG_10_UMSK (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS))
+#define AON_GPADC_SCAN_NEG_11 AON_GPADC_SCAN_NEG_11
+#define AON_GPADC_SCAN_NEG_11_POS (25U)
+#define AON_GPADC_SCAN_NEG_11_LEN (5U)
+#define AON_GPADC_SCAN_NEG_11_MSK (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)
+#define AON_GPADC_SCAN_NEG_11_UMSK (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS))
+
+/* 0x928 : gpadc_reg_status */
+#define AON_GPADC_REG_STATUS_OFFSET (0x928)
+#define AON_GPADC_DATA_RDY AON_GPADC_DATA_RDY
+#define AON_GPADC_DATA_RDY_POS (0U)
+#define AON_GPADC_DATA_RDY_LEN (1U)
+#define AON_GPADC_DATA_RDY_MSK (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)
+#define AON_GPADC_DATA_RDY_UMSK (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS))
+#define AON_GPADC_RESERVED AON_GPADC_RESERVED
+#define AON_GPADC_RESERVED_POS (16U)
+#define AON_GPADC_RESERVED_LEN (16U)
+#define AON_GPADC_RESERVED_MSK (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)
+#define AON_GPADC_RESERVED_UMSK (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS))
+
+/* 0x92C : gpadc_reg_isr */
+#define AON_GPADC_REG_ISR_OFFSET (0x92C)
+#define AON_GPADC_NEG_SATUR AON_GPADC_NEG_SATUR
+#define AON_GPADC_NEG_SATUR_POS (0U)
+#define AON_GPADC_NEG_SATUR_LEN (1U)
+#define AON_GPADC_NEG_SATUR_MSK (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)
+#define AON_GPADC_NEG_SATUR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS))
+#define AON_GPADC_POS_SATUR AON_GPADC_POS_SATUR
+#define AON_GPADC_POS_SATUR_POS (1U)
+#define AON_GPADC_POS_SATUR_LEN (1U)
+#define AON_GPADC_POS_SATUR_MSK (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)
+#define AON_GPADC_POS_SATUR_UMSK (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS))
+#define AON_GPADC_NEG_SATUR_CLR AON_GPADC_NEG_SATUR_CLR
+#define AON_GPADC_NEG_SATUR_CLR_POS (4U)
+#define AON_GPADC_NEG_SATUR_CLR_LEN (1U)
+#define AON_GPADC_NEG_SATUR_CLR_MSK (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)
+#define AON_GPADC_NEG_SATUR_CLR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS))
+#define AON_GPADC_POS_SATUR_CLR AON_GPADC_POS_SATUR_CLR
+#define AON_GPADC_POS_SATUR_CLR_POS (5U)
+#define AON_GPADC_POS_SATUR_CLR_LEN (1U)
+#define AON_GPADC_POS_SATUR_CLR_MSK (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)
+#define AON_GPADC_POS_SATUR_CLR_UMSK (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS))
+#define AON_GPADC_NEG_SATUR_MASK AON_GPADC_NEG_SATUR_MASK
+#define AON_GPADC_NEG_SATUR_MASK_POS (8U)
+#define AON_GPADC_NEG_SATUR_MASK_LEN (1U)
+#define AON_GPADC_NEG_SATUR_MASK_MSK (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)
+#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS))
+#define AON_GPADC_POS_SATUR_MASK AON_GPADC_POS_SATUR_MASK
+#define AON_GPADC_POS_SATUR_MASK_POS (9U)
+#define AON_GPADC_POS_SATUR_MASK_LEN (1U)
+#define AON_GPADC_POS_SATUR_MASK_MSK (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)
+#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS))
+
+/* 0x930 : gpadc_reg_result */
+#define AON_GPADC_REG_RESULT_OFFSET (0x930)
+#define AON_GPADC_DATA_OUT AON_GPADC_DATA_OUT
+#define AON_GPADC_DATA_OUT_POS (0U)
+#define AON_GPADC_DATA_OUT_LEN (26U)
+#define AON_GPADC_DATA_OUT_MSK (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)
+#define AON_GPADC_DATA_OUT_UMSK (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS))
+
+/* 0x934 : gpadc_reg_raw_result */
+#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934)
+#define AON_GPADC_RAW_DATA AON_GPADC_RAW_DATA
+#define AON_GPADC_RAW_DATA_POS (0U)
+#define AON_GPADC_RAW_DATA_LEN (12U)
+#define AON_GPADC_RAW_DATA_MSK (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)
+#define AON_GPADC_RAW_DATA_UMSK (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS))
+
+/* 0x938 : gpadc_reg_define */
+#define AON_GPADC_REG_DEFINE_OFFSET (0x938)
+#define AON_GPADC_OS_CAL_DATA AON_GPADC_OS_CAL_DATA
+#define AON_GPADC_OS_CAL_DATA_POS (0U)
+#define AON_GPADC_OS_CAL_DATA_LEN (16U)
+#define AON_GPADC_OS_CAL_DATA_MSK (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)
+#define AON_GPADC_OS_CAL_DATA_UMSK (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS))
+
+/* 0x93C : hbncore_resv0 */
+#define AON_HBNCORE_RESV0_OFFSET (0x93C)
+#define AON_HBNCORE_RESV0_DATA AON_HBNCORE_RESV0_DATA
+#define AON_HBNCORE_RESV0_DATA_POS (0U)
+#define AON_HBNCORE_RESV0_DATA_LEN (32U)
+#define AON_HBNCORE_RESV0_DATA_MSK (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)
+#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS))
+
+/* 0x940 : hbncore_resv1 */
+#define AON_HBNCORE_RESV1_OFFSET (0x940)
+#define AON_HBNCORE_RESV1_DATA AON_HBNCORE_RESV1_DATA
+#define AON_HBNCORE_RESV1_DATA_POS (0U)
+#define AON_HBNCORE_RESV1_DATA_LEN (32U)
+#define AON_HBNCORE_RESV1_DATA_MSK (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)
+#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS))
+
+struct aon_reg {
+ /* 0x0 reserved */
+ uint8_t RESERVED0x0[2048];
+
+ /* 0x800 : aon */
+ union {
+ struct {
+ uint32_t aon_resv : 8; /* [ 7: 0], r/w, 0xf */
+ uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */
+ uint32_t pu_aon_dc_tbuf : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_19 : 7; /* [19:13], rsvd, 0x0 */
+ uint32_t ldo11_rt_pulldown : 1; /* [ 20], r/w, 0x0 */
+ uint32_t ldo11_rt_pulldown_sel : 1; /* [ 21], r/w, 0x0 */
+ uint32_t sw_pu_ldo11_rt : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } aon;
+
+ /* 0x804 : aon_common */
+ union {
+ struct {
+ uint32_t tmux_aon : 3; /* [ 2: 0], r/w, 0x0 */
+ uint32_t pmip_dc_tp_out_en_aon : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ten_bg_sys_aon : 1; /* [ 4], r/w, 0x0 */
+ uint32_t ten_dcdc11_0_aon : 1; /* [ 5], r/w, 0x0 */
+ uint32_t ten_dcdc11_1_aon : 1; /* [ 6], r/w, 0x0 */
+ uint32_t ten_dcdc18_0_aon : 1; /* [ 7], r/w, 0x0 */
+ uint32_t ten_dcdc18_1_aon : 1; /* [ 8], r/w, 0x0 */
+ uint32_t ten_ldo12uhs : 1; /* [ 9], r/w, 0x0 */
+ uint32_t ten_ldo18flash : 1; /* [ 10], r/w, 0x0 */
+ uint32_t ten_ldo15cis : 1; /* [ 11], r/w, 0x0 */
+ uint32_t ten_ldo18io_aon : 1; /* [ 12], r/w, 0x0 */
+ uint32_t ten_ldo28cis : 1; /* [ 13], r/w, 0x0 */
+ uint32_t ten_rc32m : 1; /* [ 14], r/w, 0x0 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t ten_ldo15rf_aon : 1; /* [ 16], r/w, 0x0 */
+ uint32_t ten_xtal_aon : 1; /* [ 17], r/w, 0x0 */
+ uint32_t dten_xtal_aon : 1; /* [ 18], r/w, 0x0 */
+ uint32_t ten_mbg_aon : 1; /* [ 19], r/w, 0x0 */
+ uint32_t ten_cip_misc_aon : 1; /* [ 20], r/w, 0x0 */
+ uint32_t ten_aon : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } aon_common;
+
+ /* 0x808 : aon_misc */
+ union {
+ struct {
+ uint32_t sw_soc_en_aon : 1; /* [ 0], r/w, 0x1 */
+ uint32_t sw_wb_en_aon : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } aon_misc;
+
+ /* 0x80c reserved */
+ uint8_t RESERVED0x80c[4];
+
+ /* 0x810 : bg_sys_top */
+ union {
+ struct {
+ uint32_t pu_bg_sys_aon : 1; /* [ 0], r/w, 0x1 */
+ uint32_t istart_ctrl_aon : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bg_sys_top;
+
+ /* 0x814 : dcdc_top_0 */
+ union {
+ struct {
+ uint32_t dcdc11_sstart_time_aon : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t dcdc11_stby_lp_cur_aon : 3; /* [ 6: 4], r/w, 0x2 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t dcdc11_vc_clamp_vth_aon : 3; /* [10: 8], r/w, 0x4 */
+ uint32_t dcdc11_vout_sel_aon : 5; /* [15:11], r/w, 0x8 */
+ uint32_t dcdc11_vout_trim_aon : 4; /* [19:16], r/w, 0x7 */
+ uint32_t dcdc11_vpfm_aon : 4; /* [23:20], r/w, 0x4 */
+ uint32_t dcdc11_zvs_td_opt_aon : 3; /* [26:24], r/w, 0x4 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t dcdc11_vstby_aon : 2; /* [29:28], r/w, 0x1 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dcdc_top_0;
+
+ /* 0x818 : dcdc_top_1 */
+ union {
+ struct {
+ uint32_t dcdc11_nonoverlap_td_aon : 5; /* [ 4: 0], r/w, 0x0 */
+ uint32_t dcdc11_ocp_out_aon : 1; /* [ 5], r, 0x0 */
+ uint32_t dcdc11_ocp_rst_aon : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t dcdc11_ocp_vth_aon : 3; /* [10: 8], r/w, 0x4 */
+ uint32_t dcdc11_osc_2m_mode_aon : 1; /* [ 11], r/w, 0x0 */
+ uint32_t dcdc11_osc_freq_trim_aon : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dcdc11_pulldown_aon : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */
+ uint32_t dcdc11_rc_sel_aon : 4; /* [23:20], r/w, 0x8 */
+ uint32_t dcdc11_rdy_aon : 1; /* [ 24], r, 0x0 */
+ uint32_t reserved_25 : 1; /* [ 25], rsvd, 0x0 */
+ uint32_t dcdc11_slope_curr_sel_aon : 5; /* [30:26], r/w, 0x6 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dcdc_top_1;
+
+ /* 0x81C : ldo11soc_and_dctest */
+ union {
+ struct {
+ uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */
+ uint32_t dcdc11_cfb_sel_aon : 4; /* [ 7: 4], r/w, 0x8 */
+ uint32_t dcdc11_chf_sel_aon : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dcdc11_comp_gm_sel_aon : 3; /* [14:12], r/w, 0x4 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t dcdc11_cs_delay_aon : 3; /* [18:16], r/w, 0x4 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t dcdc11_drv_sr_aon : 2; /* [21:20], r/w, 0x3 */
+ uint32_t dcdc11_en_antiring_aon : 1; /* [ 22], r/w, 0x1 */
+ uint32_t dcdc11_en_osc_inhibit_t2_aon : 1; /* [ 23], r/w, 0x1 */
+ uint32_t dcdc11_en_slow_osc_aon : 1; /* [ 24], r/w, 0x0 */
+ uint32_t dcdc11_en_stby_lp_aon : 1; /* [ 25], r/w, 0x1 */
+ uint32_t dcdc11_en_stop_osc_aon : 1; /* [ 26], r/w, 0x1 */
+ uint32_t dcdc11_force_en_cs_zvs_aon : 1; /* [ 27], r/w, 0x0 */
+ uint32_t dcdc11_isense_trim_aon : 3; /* [30:28], r/w, 0x4 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ldo11soc_and_dctest;
+
+ /* 0x820 : move to 0x2000F000[23] */
+ union {
+ struct {
+ uint32_t dcdc18_sstart_time_aon : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t dcdc18_stby_lp_cur_aon : 3; /* [ 6: 4], r/w, 0x2 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t dcdc18_vc_clamp_vth_aon : 3; /* [10: 8], r/w, 0x4 */
+ uint32_t dcdc18_vout_sel_aon : 5; /* [15:11], r/w, 0x1b */
+ uint32_t dcdc18_vout_trim_aon : 4; /* [19:16], r/w, 0x7 */
+ uint32_t dcdc18_vpfm_aon : 4; /* [23:20], r/w, 0x4 */
+ uint32_t dcdc18_zvs_td_opt_aon : 3; /* [26:24], r/w, 0x4 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t dcdc18_vstby_aon : 2; /* [29:28], r/w, 0x1 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dcdc18_top_0;
+
+ /* 0x824 : dcdc18_top_1 */
+ union {
+ struct {
+ uint32_t dcdc18_nonoverlap_td_aon : 5; /* [ 4: 0], r/w, 0x0 */
+ uint32_t dcdc18_ocp_out_aon : 1; /* [ 5], r, 0x0 */
+ uint32_t dcdc18_ocp_rst_aon : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t dcdc18_ocp_vth_aon : 3; /* [10: 8], r/w, 0x4 */
+ uint32_t dcdc18_osc_2m_mode_aon : 1; /* [ 11], r/w, 0x0 */
+ uint32_t dcdc18_osc_freq_trim_aon : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dcdc18_pulldown_aon : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */
+ uint32_t dcdc18_rc_sel_aon : 4; /* [23:20], r/w, 0x8 */
+ uint32_t dcdc18_rdy_aon : 1; /* [ 24], r, 0x0 */
+ uint32_t reserved_25 : 1; /* [ 25], rsvd, 0x0 */
+ uint32_t dcdc18_slope_curr_sel_aon : 5; /* [30:26], r/w, 0xa */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dcdc18_top_1;
+
+ /* 0x828 : dcdc18_top_2 */
+ union {
+ struct {
+ uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */
+ uint32_t dcdc18_cfb_sel_aon : 4; /* [ 7: 4], r/w, 0x8 */
+ uint32_t dcdc18_chf_sel_aon : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dcdc18_comp_gm_sel_aon : 3; /* [14:12], r/w, 0x4 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t dcdc18_cs_delay_aon : 3; /* [18:16], r/w, 0x4 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t dcdc18_drv_sr_aon : 2; /* [21:20], r/w, 0x3 */
+ uint32_t dcdc18_en_antiring_aon : 1; /* [ 22], r/w, 0x1 */
+ uint32_t dcdc18_en_osc_inhibit_t2_aon : 1; /* [ 23], r/w, 0x0 */
+ uint32_t dcdc18_en_slow_osc_aon : 1; /* [ 24], r/w, 0x0 */
+ uint32_t dcdc18_en_stby_lp_aon : 1; /* [ 25], r/w, 0x1 */
+ uint32_t dcdc18_en_stop_osc_aon : 1; /* [ 26], r/w, 0x1 */
+ uint32_t dcdc18_force_en_cs_zvs_aon : 1; /* [ 27], r/w, 0x0 */
+ uint32_t dcdc18_isense_trim_aon : 3; /* [30:28], r/w, 0x4 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dcdc18_top_2;
+
+ /* 0x82C : psw_irrcv */
+ union {
+ struct {
+ uint32_t pu_psw_irrcv_aon : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_18 : 18; /* [18: 1], rsvd, 0x0 */
+ uint32_t usb20_rref_ext_en_aon : 1; /* [ 19], r/w, 0x0 */
+ uint32_t en_por33_aon : 1; /* [ 20], r/w, 0x0 */
+ uint32_t usb20_rref_hiz_aon : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t usb20_rcal_code_aon : 6; /* [29:24], r/w, 0x1a */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psw_irrcv;
+
+ /* 0x830 reserved */
+ uint8_t RESERVED0x830[80];
+
+ /* 0x880 : rf_top_aon */
+ union {
+ struct {
+ uint32_t pu_mbg_aon : 1; /* [ 0], r/w, 0x1 */
+ uint32_t pu_ldo15rf_aon : 1; /* [ 1], r/w, 0x1 */
+ uint32_t pu_sfreg_aon : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t pu_xtal_buf_aon : 1; /* [ 4], r/w, 0x1 */
+ uint32_t pu_xtal_aon : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t ldo15rf_sstart_sel_aon : 1; /* [ 8], r/w, 0x1 */
+ uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t ldo15rf_pulldown_aon : 1; /* [ 12], r/w, 0x0 */
+ uint32_t ldo15rf_pulldown_sel_aon : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t ldo15rf_vout_sel_aon : 3; /* [18:16], r/w, 0x2 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t ldo15rf_cc_aon : 2; /* [25:24], r/w, 0x0 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t ldo15rf_bypass_aon : 1; /* [ 28], r/w, 0x0 */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } rf_top_aon;
+
+ /* 0x884 : xtal_cfg */
+ union {
+ struct {
+ uint32_t xtal_bk_aon : 2; /* [ 1: 0], r/w, 0x1 */
+ uint32_t xtal_capcode_extra_aon : 1; /* [ 2], r/w, 0x0 */
+ uint32_t xtal_ext_sel_aon : 1; /* [ 3], r/w, 0x0 */
+ uint32_t xtal_buf_en_aon : 4; /* [ 7: 4], r/w, 0xe */
+ uint32_t xtal_buf_hp_aon : 4; /* [11: 8], r/w, 0x0 */
+ uint32_t xtal_fast_startup_aon : 1; /* [ 12], r/w, 0x1 */
+ uint32_t xtal_sleep_aon : 1; /* [ 13], r/w, 0x1 */
+ uint32_t xtal_amp_ctrl_aon : 2; /* [15:14], r/w, 0x3 */
+ uint32_t xtal_capcode_out_aon : 6; /* [21:16], r/w, 0x10 */
+ uint32_t xtal_capcode_in_aon : 6; /* [27:22], r/w, 0x10 */
+ uint32_t xtal_gm_boost_aon : 2; /* [29:28], r/w, 0x3 */
+ uint32_t xtal_rdy_sel_aon : 2; /* [31:30], r/w, 0x2 */
+ } BF;
+ uint32_t WORD;
+ } xtal_cfg;
+
+ /* 0x888 : xtal_cfg2 */
+ union {
+ struct {
+ uint32_t wifi_xtal_ldo33_bypass_aon : 1; /* [ 0], r/w, 0x0 */
+ uint32_t wifi_xtal_ldo33_sel_aon : 3; /* [ 3: 1], r/w, 0x0 */
+ uint32_t wifi_xtal_ldo18_sel_aon : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t wifi_xtal_ldo33_pu_aon : 1; /* [ 6], r/w, 0x1 */
+ uint32_t wifi_xtal_ldo18_pu_aon : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */
+ uint32_t wifi_xtal_reserve : 4; /* [13:10], r/w, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t wifi_xtal_ldo18_short_filter_aon : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_29 : 13; /* [29:17], rsvd, 0x0 */
+ uint32_t xtal_buf_drv_aon : 2; /* [31:30], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } xtal_cfg2;
+
+ /* 0x88C : xtal_cfg3 */
+ union {
+ struct {
+ uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
+ uint32_t wifi_xtal_clk_inv_en_aon : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t wifi_xtal_cml_en_aon : 1; /* [ 16], r/w, 0x0 */
+ uint32_t wifi_xtal_cml_r_sel_aon : 2; /* [18:17], r/w, 0x1 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t wifi_xtal_clk_en_aon : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21_29 : 9; /* [29:21], rsvd, 0x0 */
+ uint32_t wifi_xtal_buf_drv_aon : 2; /* [31:30], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } xtal_cfg3;
+
+ /* 0x890 : tsen */
+ union {
+ struct {
+ uint32_t tsen_refcode_corner : 12; /* [11: 0], r/w, 0x8ff */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t tsen_refcode_rfcal : 12; /* [27:16], r/w, 0x8ff */
+ uint32_t xtal_rdy : 1; /* [ 28], r, 0x1 */
+ uint32_t xtal_inn_cfg_en_aon : 1; /* [ 29], r/w, 0x1 */
+ uint32_t xtal_rdy_int_sel_aon : 2; /* [31:30], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } tsen;
+
+ /* 0x894 reserved */
+ uint8_t RESERVED0x894[48];
+
+ /* 0x8C4 : ldo18io */
+ union {
+ struct {
+ uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
+ uint32_t ldo18io_bypass_iso_aon : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ldo18io_pulldown_aon : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ldo18io_pulldown_sel_aon : 1; /* [ 3], r/w, 0x1 */
+ uint32_t ldo18io_bm_aon : 3; /* [ 6: 4], r/w, 0x3 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t ldo18io_cc_aon : 3; /* [10: 8], r/w, 0x3 */
+ uint32_t ldo18io_ocp_out_aon : 1; /* [ 11], r, 0x0 */
+ uint32_t ldo18io_ocp_th_aon : 3; /* [14:12], r/w, 0x3 */
+ uint32_t ldo18io_ocp_en_aon : 1; /* [ 15], r/w, 0x1 */
+ uint32_t ldo18io_sstart_delay_aon : 3; /* [18:16], r/w, 0x3 */
+ uint32_t ldo18io_sstart_en_aon : 1; /* [ 19], r/w, 0x1 */
+ uint32_t ldo18io_vout_sel_aon : 4; /* [23:20], r/w, 0x5 */
+ uint32_t ldo18io_vout_trim_aon : 4; /* [27:24], r/w, 0x7 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ldo18io;
+
+ /* 0x8c8 reserved */
+ uint8_t RESERVED0x8c8[56];
+
+ /* 0x900 : acomp0_ctrl */
+ union {
+ struct {
+ uint32_t acomp0_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t acomp0_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */
+ uint32_t acomp0_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */
+ uint32_t acomp0_bias_prog : 2; /* [11:10], r/w, 0x0 */
+ uint32_t acomp0_level_sel : 6; /* [17:12], r/w, 0x0 */
+ uint32_t acomp0_neg_sel : 4; /* [21:18], r/w, 0x0 */
+ uint32_t acomp0_pos_sel : 4; /* [25:22], r/w, 0x0 */
+ uint32_t acomp0_muxen : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } acomp0_ctrl;
+
+ /* 0x904 : acomp1_ctrl */
+ union {
+ struct {
+ uint32_t acomp1_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t acomp1_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */
+ uint32_t acomp1_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */
+ uint32_t acomp1_bias_prog : 2; /* [11:10], r/w, 0x0 */
+ uint32_t acomp1_level_sel : 6; /* [17:12], r/w, 0x0 */
+ uint32_t acomp1_neg_sel : 4; /* [21:18], r/w, 0x0 */
+ uint32_t acomp1_pos_sel : 4; /* [25:22], r/w, 0x0 */
+ uint32_t acomp1_muxen : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } acomp1_ctrl;
+
+ /* 0x908 : acomp_ctrl */
+ union {
+ struct {
+ uint32_t acomp1_rstn_ana : 1; /* [ 0], r/w, 0x1 */
+ uint32_t acomp0_rstn_ana : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t acomp1_test_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t acomp0_test_en : 1; /* [ 9], r/w, 0x0 */
+ uint32_t acomp1_test_sel : 2; /* [11:10], r/w, 0x0 */
+ uint32_t acomp0_test_sel : 2; /* [13:12], r/w, 0x0 */
+ uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */
+ uint32_t acomp1_out_raw : 1; /* [ 17], r, 0x0 */
+ uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */
+ uint32_t acomp0_out_raw : 1; /* [ 19], r, 0x0 */
+ uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
+ uint32_t acomp_vref_sel : 6; /* [29:24], r/w, 0x0 */
+ uint32_t acomp_reserved : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } acomp_ctrl;
+
+ /* 0x90C : gpadc_reg_cmd */
+ union {
+ struct {
+ uint32_t gpadc_global_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t gpadc_conv_start : 1; /* [ 1], r/w, 0x0 */
+ uint32_t gpadc_soft_rst : 1; /* [ 2], r/w, 0x0 */
+ uint32_t gpadc_neg_sel : 5; /* [ 7: 3], r/w, 0xf */
+ uint32_t gpadc_pos_sel : 5; /* [12: 8], r/w, 0xf */
+ uint32_t gpadc_neg_gnd : 1; /* [ 13], r/w, 0x0 */
+ uint32_t gpadc_micbias_en : 1; /* [ 14], r/w, 0x0 */
+ uint32_t gpadc_micpga_en : 1; /* [ 15], r/w, 0x0 */
+ uint32_t gpadc_byp_micboost : 1; /* [ 16], r/w, 0x0 */
+ uint32_t gpadc_rcal_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t gpadc_dwa_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t gpadc_mic2_diff : 1; /* [ 19], r/w, 0x0 */
+ uint32_t gpadc_mic1_diff : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpadc_mic_pga2_gain : 2; /* [22:21], r/w, 0x0 */
+ uint32_t gpadc_micboost_32db_en : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reserved_24_26 : 3; /* [26:24], rsvd, 0x0 */
+ uint32_t gpadc_chip_sen_pu : 1; /* [ 27], r/w, 0x0 */
+ uint32_t gpadc_sen_sel : 3; /* [30:28], r/w, 0x0 */
+ uint32_t gpadc_sen_test_en : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_cmd;
+
+ /* 0x910 : gpadc_reg_config1 */
+ union {
+ struct {
+ uint32_t gpadc_cal_os_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t gpadc_cont_conv_en : 1; /* [ 1], r/w, 0x1 */
+ uint32_t gpadc_res_sel : 3; /* [ 4: 2], r/w, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t gpadc_vcm_sel_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t gpadc_vcm_hyst_sel : 1; /* [ 9], r/w, 0x0 */
+ uint32_t gpadc_lowv_det_en : 1; /* [ 10], r/w, 0x0 */
+ uint32_t gpadc_pwm_trg_en : 1; /* [ 11], r/w, 0x0 */
+ uint32_t gpadc_clk_ana_dly : 4; /* [15:12], r/w, 0x0 */
+ uint32_t gpadc_clk_ana_dly_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t gpadc_clk_ana_inv : 1; /* [ 17], r/w, 0x0 */
+ uint32_t gpadc_clk_div_ratio : 3; /* [20:18], r/w, 0x3 */
+ uint32_t gpadc_scan_length : 4; /* [24:21], r/w, 0x0 */
+ uint32_t gpadc_scan_en : 1; /* [ 25], r/w, 0x0 */
+ uint32_t gpadc_dither_en : 1; /* [ 26], r/w, 0x0 */
+ uint32_t gpadc_v11_sel : 2; /* [28:27], r/w, 0x0 */
+ uint32_t gpadc_v18_sel : 2; /* [30:29], r/w, 0x0 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_config1;
+
+ /* 0x914 : gpadc_reg_config2 */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t gpadc_diff_mode : 1; /* [ 2], r/w, 0x0 */
+ uint32_t gpadc_vref_sel : 1; /* [ 3], r/w, 0x0 */
+ uint32_t gpadc_vbat_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t gpadc_tsext_sel : 1; /* [ 5], r/w, 0x0 */
+ uint32_t gpadc_ts_en : 1; /* [ 6], r/w, 0x0 */
+ uint32_t gpadc_pga_vcm : 2; /* [ 8: 7], r/w, 0x2 */
+ uint32_t gpadc_pga_os_cal : 4; /* [12: 9], r/w, 0x8 */
+ uint32_t gpadc_pga_en : 1; /* [ 13], r/w, 0x0 */
+ uint32_t gpadc_pga_vcmi_en : 1; /* [ 14], r/w, 0x0 */
+ uint32_t gpadc_chop_mode : 2; /* [16:15], r/w, 0x3 */
+ uint32_t gpadc_bias_sel : 1; /* [ 17], r/w, 0x0 */
+ uint32_t gpadc_test_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t gpadc_test_sel : 3; /* [21:19], r/w, 0x0 */
+ uint32_t gpadc_pga2_gain : 3; /* [24:22], r/w, 0x0 */
+ uint32_t gpadc_pga1_gain : 3; /* [27:25], r/w, 0x0 */
+ uint32_t gpadc_dly_sel : 3; /* [30:28], r/w, 0x0 */
+ uint32_t gpadc_tsvbe_low : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_config2;
+
+ /* 0x918 : adc converation sequence 1 */
+ union {
+ struct {
+ uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0], r/w, 0xf */
+ uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5], r/w, 0xf */
+ uint32_t gpadc_scan_pos_2 : 5; /* [14:10], r/w, 0xf */
+ uint32_t gpadc_scan_pos_3 : 5; /* [19:15], r/w, 0xf */
+ uint32_t gpadc_scan_pos_4 : 5; /* [24:20], r/w, 0xf */
+ uint32_t gpadc_scan_pos_5 : 5; /* [29:25], r/w, 0xf */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_scn_pos1;
+
+ /* 0x91C : adc converation sequence 2 */
+ union {
+ struct {
+ uint32_t gpadc_scan_pos_6 : 5; /* [ 4: 0], r/w, 0xf */
+ uint32_t gpadc_scan_pos_7 : 5; /* [ 9: 5], r/w, 0xf */
+ uint32_t gpadc_scan_pos_8 : 5; /* [14:10], r/w, 0xf */
+ uint32_t gpadc_scan_pos_9 : 5; /* [19:15], r/w, 0xf */
+ uint32_t gpadc_scan_pos_10 : 5; /* [24:20], r/w, 0xf */
+ uint32_t gpadc_scan_pos_11 : 5; /* [29:25], r/w, 0xf */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_scn_pos2;
+
+ /* 0x920 : adc converation sequence 3 */
+ union {
+ struct {
+ uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0], r/w, 0xf */
+ uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5], r/w, 0xf */
+ uint32_t gpadc_scan_neg_2 : 5; /* [14:10], r/w, 0xf */
+ uint32_t gpadc_scan_neg_3 : 5; /* [19:15], r/w, 0xf */
+ uint32_t gpadc_scan_neg_4 : 5; /* [24:20], r/w, 0xf */
+ uint32_t gpadc_scan_neg_5 : 5; /* [29:25], r/w, 0xf */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_scn_neg1;
+
+ /* 0x924 : adc converation sequence 4 */
+ union {
+ struct {
+ uint32_t gpadc_scan_neg_6 : 5; /* [ 4: 0], r/w, 0xf */
+ uint32_t gpadc_scan_neg_7 : 5; /* [ 9: 5], r/w, 0xf */
+ uint32_t gpadc_scan_neg_8 : 5; /* [14:10], r/w, 0xf */
+ uint32_t gpadc_scan_neg_9 : 5; /* [19:15], r/w, 0xf */
+ uint32_t gpadc_scan_neg_10 : 5; /* [24:20], r/w, 0xf */
+ uint32_t gpadc_scan_neg_11 : 5; /* [29:25], r/w, 0xf */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_scn_neg2;
+
+ /* 0x928 : gpadc_reg_status */
+ union {
+ struct {
+ uint32_t gpadc_data_rdy : 1; /* [ 0], r, 0x0 */
+ uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */
+ uint32_t gpadc_reserved : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_status;
+
+ /* 0x92C : gpadc_reg_isr */
+ union {
+ struct {
+ uint32_t gpadc_neg_satur : 1; /* [ 0], r, 0x0 */
+ uint32_t gpadc_pos_satur : 1; /* [ 1], r, 0x0 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t gpadc_neg_satur_clr : 1; /* [ 4], r/w, 0x0 */
+ uint32_t gpadc_pos_satur_clr : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t gpadc_neg_satur_mask : 1; /* [ 8], r/w, 0x0 */
+ uint32_t gpadc_pos_satur_mask : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_isr;
+
+ /* 0x930 : gpadc_reg_result */
+ union {
+ struct {
+ uint32_t gpadc_data_out : 26; /* [25: 0], r, 0x1ef0000 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_result;
+
+ /* 0x934 : gpadc_reg_raw_result */
+ union {
+ struct {
+ uint32_t gpadc_raw_data : 12; /* [11: 0], r, 0x0 */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_raw_result;
+
+ /* 0x938 : gpadc_reg_define */
+ union {
+ struct {
+ uint32_t gpadc_os_cal_data : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpadc_reg_define;
+
+ /* 0x93C : hbncore_resv0 */
+ union {
+ struct {
+ uint32_t hbncore_resv0_data : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } hbncore_resv0;
+
+ /* 0x940 : hbncore_resv1 */
+ union {
+ struct {
+ uint32_t hbncore_resv1_data : 32; /* [31: 0], r/w, 0xffffffff */
+ } BF;
+ uint32_t WORD;
+ } hbncore_resv1;
+};
+
+typedef volatile struct aon_reg aon_reg_t;
+
+#endif /* __AON_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/bl808.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/bl808.h
new file mode 100644
index 00000000..b96b9b68
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/bl808.h
@@ -0,0 +1,659 @@
+#ifndef __BL808_H__
+#define __BL808_H__
+
+/** @addtogroup Configuration_section_for_RISCV
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Processor and Core Peripherals
+ */
+
+#define CORE_ID_ADDRESS (0xF0000000)
+#define CORE_ID_M0 (0xE9070000)
+#define CORE_ID_D0 (0xDEAD5500)
+#define CORE_ID_LP (0xDEADE902)
+
+#define CORE_M0_JTAG_TCK_PIN (GLB_GPIO_PIN_27)
+#define CORE_M0_JTAG_TMS_PIN (GLB_GPIO_PIN_28)
+#define CORE_M0_JTAG_TCK_FUNC (GPIO_FUN_M_CJTAG)
+#define CORE_M0_JTAG_TMS_FUNC (GPIO_FUN_M_CJTAG)
+
+#define IPC_SYNC_ADDR1 0x40000000
+#define IPC_SYNC_ADDR2 0x40000004
+#define IPC_SYNC_FLAG 0x12345678
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+#ifdef ARCH_ARM
+#define IRQ_NUM_BASE 0
+#endif
+
+#ifdef ARCH_RISCV
+#if (__riscv_xlen == 64)
+#define IRQ_NUM_BASE 16 /* PLIC ===> MEXT_IRQn */
+#else
+#define IRQ_NUM_BASE 16
+#endif
+#endif
+/**
+ * @brief BL808 Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum {
+#ifdef ARCH_ARM
+ /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+#endif
+#ifdef ARCH_RISCV
+ SSOFT_IRQn = 1, /*!< 1 RISCV supervisor software Interrupt */
+ MSOFT_IRQn = 3, /*!< 3 RISCV machine software Interrupt */
+ STIME_IRQn = 5, /*!< 5 RISCV supervisor time Interrupt */
+ MTIME_IRQn = 7, /*!< 7 RISCV machine time Interrupt */
+ SEXT_IRQn = 9, /*!< 9 RISCV S-mode external Interrupt */
+ MEXT_IRQn = 11, /*!< 11 RISCV M-mode external Interrupt */
+ CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending Interrupt */
+#if (__riscv_xlen == 64)
+ HPM_OVF_IRQn = 17, /*!< 17 RISCV HPM counter overflow Interrupt */
+#endif
+#endif
+#if defined(CPU_M0) || defined(CPU_LP)
+#ifdef CPU_LP
+#define CPU_LP_MAX_IRQ_NUM (IRQ_NUM_BASE + 32)
+#endif
+ /****** BL808 specific Interrupt Numbers **********************************************************************/
+ BMX_MCU_BUS_ERR_IRQn = IRQ_NUM_BASE + 0, /*!< bmx mcu bus_err_int Interrupt */
+ BMX_MCU_TO_IRQn = IRQ_NUM_BASE + 1, /*!< bmx_timeout_int|mcu_timeout_int Interrupt */
+ M0_RESERVED2_IRQn = IRQ_NUM_BASE + 2, /*!< reserved Interrupt */
+ IPC_M0_IRQn = IRQ_NUM_BASE + 3, /*!< ipc0_m0_irq Interrupt */
+ AUDIO_IRQn = IRQ_NUM_BASE + 4, /*!< Audio Interrupt */
+ RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5, /*!< RF_TOP_INT0 Interrupt */
+ RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6, /*!< RF_TOP_INT1 Interrupt */
+ LZ4D_IRQn = IRQ_NUM_BASE + 7, /*!< LZ4 decompressor Interrupt */
+ GAUGE_ITF_IRQn = IRQ_NUM_BASE + 8, /*!< gauge_itf_int Interrupt */
+ SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn = IRQ_NUM_BASE + 9, /*!< sec_eng_id1 Interrupt */
+ SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn = IRQ_NUM_BASE + 10, /*!< sec_eng_id0 Interrupt */
+ SEC_ENG_ID1_CDET_IRQn = IRQ_NUM_BASE + 11, /*!< sec_eng_id1_cdet Interrupt */
+ SEC_ENG_ID0_CDET_IRQn = IRQ_NUM_BASE + 12, /*!< sec_eng_id0_cdet Interrupt */
+ SF_CTRL_ID1_IRQn = IRQ_NUM_BASE + 13, /*!< sf_ctrl_id1 Interrupt */
+ SF_CTRL_ID0_IRQn = IRQ_NUM_BASE + 14, /*!< sf_ctrl_id0 Interrupt */
+ DMA0_ALL_IRQn = IRQ_NUM_BASE + 15, /*!< DMA0_INTR_ALL Interrupt */
+ DMA1_ALL_IRQn = IRQ_NUM_BASE + 16, /*!< DMA1_INTR_ALL Interrupt */
+ SDH_IRQn = IRQ_NUM_BASE + 17, /*!< sdh Interrupt */
+ MM_ALL_IRQn = IRQ_NUM_BASE + 18, /*!< MM System All Interrupt */
+ IRTX_IRQn = IRQ_NUM_BASE + 19, /*!< IR TX Interrupt */
+ IRRX_IRQn = IRQ_NUM_BASE + 20, /*!< IR RX Interrupt */
+ USB_IRQn = IRQ_NUM_BASE + 21, /*!< USB Interrupt */
+ AUPDM_TOUCH_IRQn = IRQ_NUM_BASE + 22, /*!< aupdm_touch_int Interrupt */
+ M0_RESERVED23_IRQn = IRQ_NUM_BASE + 23, /*!< reserved Interrupt */
+ EMAC_IRQn = IRQ_NUM_BASE + 24, /*!< EMAC Interrupt */
+ GPADC_DMA_IRQn = IRQ_NUM_BASE + 25, /*!< GPADC_DMA Interrupt */
+ EFUSE_IRQn = IRQ_NUM_BASE + 26, /*!< Efuse Interrupt */
+ SPI0_IRQn = IRQ_NUM_BASE + 27, /*!< SPI0 Interrupt */
+ UART0_IRQn = IRQ_NUM_BASE + 28, /*!< UART0 Interrupt */
+ UART1_IRQn = IRQ_NUM_BASE + 29, /*!< UART1 Interrupt */
+ UART2_IRQn = IRQ_NUM_BASE + 30, /*!< UART2 Interrupt */
+ GPIO_DMA_IRQn = IRQ_NUM_BASE + 31, /*!< GPIO DMA Interrupt */
+ I2C0_IRQn = IRQ_NUM_BASE + 32, /*!< I2C0 Interrupt */
+ PWM_IRQn = IRQ_NUM_BASE + 33, /*!< PWM Interrupt */
+ IPC_RSVD_IRQn = IRQ_NUM_BASE + 34, /*!< ipc reserved Interrupt */
+ IPC_LP_IRQn = IRQ_NUM_BASE + 35, /*!< ipc lp_irq Interrupt */
+ TIMER0_CH0_IRQn = IRQ_NUM_BASE + 36, /*!< Timer0 Channel 0 Interrupt */
+ TIMER0_CH1_IRQn = IRQ_NUM_BASE + 37, /*!< Timer0 Channel 1 Interrupt */
+ TIMER0_WDT_IRQn = IRQ_NUM_BASE + 38, /*!< Timer0 Watch Dog Interrupt */
+ I2C1_IRQn = IRQ_NUM_BASE + 39, /*!< I2C1 Interrupt */
+ I2S_IRQn = IRQ_NUM_BASE + 40, /*!< I2S Interrupt */
+ ANA_OCP_OUT_TO_CPU_0_IRQn = IRQ_NUM_BASE + 41, /*!< ana_ocp_out_to_cpu_irq0 Interrupt */
+ ANA_OCP_OUT_TO_CPU_1_IRQn = IRQ_NUM_BASE + 42, /*!< ana_ocp_out_to_cpu_irq1 Interrupt */
+ ANA_OCP_OUT_TO_CPU_2_IRQn = IRQ_NUM_BASE + 43, /*!< ana_ocp_out_to_cpu_irq2 Interrupt */
+ GPIO_INT0_IRQn = IRQ_NUM_BASE + 44, /*!< GPIO Interrupt */
+ DM_IRQn = IRQ_NUM_BASE + 45, /*!< DM Interrupt */
+ BT_IRQn = IRQ_NUM_BASE + 46, /*!< BT Interrupt */
+ M154_REQ_ACK_IRQn = IRQ_NUM_BASE + 47, /*!< M154 req enh ack Interrupt */
+ M154_INT_IRQn = IRQ_NUM_BASE + 48, /*!< M154 Interrupt */
+ M154_AES_IRQn = IRQ_NUM_BASE + 49, /*!< m154 aes Interrupt */
+ PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50, /*!< PDS Wakeup Interrupt */
+ HBN_OUT0_IRQn = IRQ_NUM_BASE + 51, /*!< Hibernate out 0 Interrupt */
+ HBN_OUT1_IRQn = IRQ_NUM_BASE + 52, /*!< Hibernate out 1 Interrupt */
+ BOR_IRQn = IRQ_NUM_BASE + 53, /*!< BOR Interrupt */
+ WIFI_IRQn = IRQ_NUM_BASE + 54, /*!< WIFI To CPU Interrupt */
+ BZ_PHY_INT_IRQn = IRQ_NUM_BASE + 55, /*!< BZ phy Interrupt */
+ BLE_IRQn = IRQ_NUM_BASE + 56, /*!< BLE Interrupt */
+ MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE + 57, /*!< MAC Tx Rx Timer Interrupt */
+ MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE + 58, /*!< MAC Tx Rx Misc Interrupt */
+ MAC_RX_TRG_IRQn = IRQ_NUM_BASE + 59, /*!< MAC Rx Trigger Interrupt */
+ MAC_TX_TRG_IRQn = IRQ_NUM_BASE + 60, /*!< MAC tx Trigger Interrupt */
+ MAC_GEN_IRQn = IRQ_NUM_BASE + 61, /*!< MAC Gen Interrupt */
+ MAC_PORT_TRG_IRQn = IRQ_NUM_BASE + 62, /*!< MAC Prot Trigger Interrupt */
+ WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE + 63, /*!< WIFI Ipc Interrupt */
+ IRQn_LAST,
+#endif
+
+#if defined(CPU_D0)
+ /****** BL808 specific Interrupt Numbers **********************************************************************/
+ BMX_DSP_BUS_ERR_IRQn = IRQ_NUM_BASE + 0, /*!< BMX DSP BUS Error Interrupt */
+ D0_RESERVED1_IRQn = IRQ_NUM_BASE + 1, /*!< D0 reserved1 Interrupt */
+ D0_RESERVED2_IRQn = IRQ_NUM_BASE + 2, /*!< IPC reserved Interrupt */
+ D0_RESERVED3_IRQn = IRQ_NUM_BASE + 3, /*!< UART4 reserved Interrupt */
+ UART3_IRQn = IRQ_NUM_BASE + 4, /*!< UART3 Interrupt */
+ I2C2_IRQn = IRQ_NUM_BASE + 5, /*!< I2C2 Interrupt */
+ I2C3_IRQn = IRQ_NUM_BASE + 6, /*!< I2C3 Interrupt */
+ SPI1_IRQn = IRQ_NUM_BASE + 7, /*!< SPI1 Interrupt */
+ D0_RESERVED4_IRQn = IRQ_NUM_BASE + 8, /*!< D0 reserved4 Interrupt */
+ D0_RESERVED5_IRQn = IRQ_NUM_BASE + 9, /*!< D0 reserved5 Interrupt */
+ SEOF_INT0_IRQn = IRQ_NUM_BASE + 10, /*!< SEOF INT0 Interrupt */
+ SEOF_INT1_IRQn = IRQ_NUM_BASE + 11, /*!< SEOF INT1 Interrupt */
+ SEOF_INT2_IRQn = IRQ_NUM_BASE + 12, /*!< SEOF INT2 Interrupt */
+ DVP2BUS_INT0_IRQn = IRQ_NUM_BASE + 13, /*!< DVP2BUS INT0 Interrupt */
+ DVP2BUS_INT1_IRQn = IRQ_NUM_BASE + 14, /*!< DVP2BUS INT1 Interrupt */
+ DVP2BUS_INT2_IRQn = IRQ_NUM_BASE + 15, /*!< DVP2BUS INT2 Interrupt */
+ DVP2BUS_INT3_IRQn = IRQ_NUM_BASE + 16, /*!< DVP2BUS INT3 Interrupt */
+ H264_BS_IRQn = IRQ_NUM_BASE + 17, /*!< H264 BS Interrupt */
+ H264_FRAME_IRQn = IRQ_NUM_BASE + 18, /*!< H264 Frame Interrupt */
+ H264_SEQ_DONE_IRQn = IRQ_NUM_BASE + 19, /*!< H264 SEQ Done Interrupt */
+ MJPEG_IRQn = IRQ_NUM_BASE + 20, /*!< MJPEG Interrupt */
+ H264_S_BS_IRQn = IRQ_NUM_BASE + 21, /*!< H264 S BS Interrupt */
+ H264_S_FRAME_IRQn = IRQ_NUM_BASE + 22, /*!< H264 S Frame Interrupt */
+ H264_S_SEQ_DONE_IRQn = IRQ_NUM_BASE + 23, /*!< H264 S SEQ Done Interrupt */
+ DMA2_INT0_IRQn = IRQ_NUM_BASE + 24, /*!< DMA2 INT0 Interrupt */
+ DMA2_INT1_IRQn = IRQ_NUM_BASE + 25, /*!< DMA2 INT1 Interrupt */
+ DMA2_INT2_IRQn = IRQ_NUM_BASE + 26, /*!< DMA2 INT2 Interrupt */
+ DMA2_INT3_IRQn = IRQ_NUM_BASE + 27, /*!< DMA2 INT3 Interrupt */
+ DMA2_INT4_IRQn = IRQ_NUM_BASE + 28, /*!< DMA2 INT4 Interrupt */
+ DMA2_INT5_IRQn = IRQ_NUM_BASE + 29, /*!< DMA2 INT5 Interrupt */
+ DMA2_INT6_IRQn = IRQ_NUM_BASE + 30, /*!< DMA2 INT6 Interrupt */
+ DMA2_INT7_IRQn = IRQ_NUM_BASE + 31, /*!< DMA2 INT7 Interrupt */
+ SDH_MMC1_IRQn = IRQ_NUM_BASE + 32, /*!< SDH MMC1 Interrupt */
+ SDH_MMC3_IRQn = IRQ_NUM_BASE + 33, /*!< SDH MMC3 Interrupt */
+ SDH2PMU_WAKEUP1_IRQn = IRQ_NUM_BASE + 34, /*!< SDH2PMU Wakeup1 Interrupt */
+ SDH2PMU_WAKEUP3_IRQn = IRQ_NUM_BASE + 35, /*!< SDH2PMU Wakeup3 Interrupt */
+ EMAC2_IRQn = IRQ_NUM_BASE + 36, /*!< EMAC2 Interrupt */
+ MIPI_CSI_IRQn = IRQ_NUM_BASE + 37, /*!< MIPI CSI Interrupt */
+ IPC_D0_IRQn = IRQ_NUM_BASE + 38, /*!< IPC D0 Interrupt */
+ APU_IRQn = IRQ_NUM_BASE + 39, /*!< APU Interrupt */
+ MJDEC_IRQn = IRQ_NUM_BASE + 40, /*!< MJDEC Interrupt */
+ DVP2BUS_INT4_IRQn = IRQ_NUM_BASE + 41, /*!< DVP2BUS INT4 Interrupt */
+ DVP2BUS_INT5_IRQn = IRQ_NUM_BASE + 42, /*!< DVP2BUS INT5 Interrupt */
+ DVP2BUS_INT6_IRQn = IRQ_NUM_BASE + 43, /*!< DVP2BUS INT6 Interrupt */
+ DVP2BUS_INT7_IRQn = IRQ_NUM_BASE + 44, /*!< DVP2BUS INT7 Interrupt */
+ DMA2D_INT0_IRQn = IRQ_NUM_BASE + 45, /*!< DMA2D INT0 Interrupt */
+ DMA2D_INT1_IRQn = IRQ_NUM_BASE + 46, /*!< DMA2D INT1 Interrupt */
+ DISPLAY_IRQn = IRQ_NUM_BASE + 47, /*!< Display Interrupt */
+ PWM_IRQn = IRQ_NUM_BASE + 48, /*!< PWM1 Interrupt */
+ SEOF_INT3_IRQn = IRQ_NUM_BASE + 49, /*!< SEOF INT0 Interrupt */
+ RESERVED1_IRQn = IRQ_NUM_BASE + 50, /*!< Reserved Interrupt */
+ RESERVED2_IRQn = IRQ_NUM_BASE + 51, /*!< Reserved Interrupt */
+ OSD_IRQn = IRQ_NUM_BASE + 52, /*!< OSD Interrupt */
+ DBI_IRQn = IRQ_NUM_BASE + 53, /*!< DBI Interrupt */
+ D0_RESERVED6_IRQn = IRQ_NUM_BASE + 54, /*!< D0_RESERVED6 Interrupt */
+ OSDA_BUS_DRAIN_IRQn = IRQ_NUM_BASE + 55, /*!< OSDA Bus Drain Interrupt */
+ OSDB_BUS_DRAIN_IRQn = IRQ_NUM_BASE + 56, /*!< OSDB Bus Drain Interrupt */
+ OSD_PB_IRQn = IRQ_NUM_BASE + 57, /*!< OSD PB Interrupt */
+ D0_RESERVED7_IRQn = IRQ_NUM_BASE + 58, /*!< D0_RESERVED7 Interrupt */
+ MIPI_DSI_IRQn = IRQ_NUM_BASE + 59, /*!< MIPI DSI Interrupt */
+ D0_RESERVED8_IRQn = IRQ_NUM_BASE + 60, /*!< D0_RESERVED8 Interrupt */
+ TIMER1_CH0_IRQn = IRQ_NUM_BASE + 61, /*!< Timer1 Channel 0 Interrupt */
+ TIMER1_CH1_IRQn = IRQ_NUM_BASE + 62, /*!< Timer1 Channel 1 Interrupt */
+ TIMER1_WDT_IRQn = IRQ_NUM_BASE + 63, /*!< Timer1 Watch Dog Interrupt */
+ AUDIO_IRQn = IRQ_NUM_BASE + 64, /*!< Audio Interrupt */
+ WL_ALL_IRQn = IRQ_NUM_BASE + 65, /*!< WL System All Interrupt */
+ PDS_IRQn = IRQ_NUM_BASE + 66, /*!< PDS Interrupt */
+ IRQn_LAST,
+#endif
+} IRQn_Type;
+
+/* Add following macro definition in order to pass the compilation */
+#if defined(CPU_M0) || defined(CPU_LP)
+#define BMX_DSP_BUS_ERR_IRQn (IRQn_LAST)
+#define D0_RESERVED1_IRQn (IRQn_LAST)
+#define D0_RESERVED2_IRQn (IRQn_LAST)
+#define UART3_IRQn (IRQn_LAST)
+#define I2C2_IRQn (IRQn_LAST)
+#define I2C3_IRQn (IRQn_LAST)
+#define SPI1_IRQn (IRQn_LAST)
+#define D0_RESERVED4_IRQn (IRQn_LAST)
+#define D0_RESERVED5_IRQn (IRQn_LAST)
+#define SEOF_INT0_IRQn (IRQn_LAST)
+#define SEOF_INT1_IRQn (IRQn_LAST)
+#define SEOF_INT2_IRQn (IRQn_LAST)
+#define DVP2BUS_INT0_IRQn (IRQn_LAST)
+#define DVP2BUS_INT1_IRQn (IRQn_LAST)
+#define DVP2BUS_INT2_IRQn (IRQn_LAST)
+#define DVP2BUS_INT3_IRQn (IRQn_LAST)
+#define H264_BS_IRQn (IRQn_LAST)
+#define H264_FRAME_IRQn (IRQn_LAST)
+#define H264_SEQ_DONE_IRQn (IRQn_LAST)
+#define MJPEG_IRQn (IRQn_LAST)
+#define H264_S_BS_IRQn (IRQn_LAST)
+#define H264_S_FRAME_IRQn (IRQn_LAST)
+#define H264_S_SEQ_DONE_IRQn (IRQn_LAST)
+#define DMA2_INT0_IRQn (IRQn_LAST)
+#define DMA2_INT1_IRQn (IRQn_LAST)
+#define DMA2_INT2_IRQn (IRQn_LAST)
+#define DMA2_INT3_IRQn (IRQn_LAST)
+#define DMA2_INT4_IRQn (IRQn_LAST)
+#define DMA2_INT5_IRQn (IRQn_LAST)
+#define DMA2_INT6_IRQn (IRQn_LAST)
+#define DMA2_INT7_IRQn (IRQn_LAST)
+#define SDH_MMC1_IRQn (IRQn_LAST)
+#define SDH_MMC3_IRQn (IRQn_LAST)
+#define SDH2PMU_WAKEUP1_IRQn (IRQn_LAST)
+#define SDH2PMU_WAKEUP3_IRQn (IRQn_LAST)
+#define EMAC2_IRQn (IRQn_LAST)
+#define MIPI_CSI_IRQn (IRQn_LAST)
+#define IPC_D0_IRQn (IRQn_LAST)
+#define APU_IRQn (IRQn_LAST)
+#define MJDEC_IRQn (IRQn_LAST)
+#define DVP2BUS_INT4_IRQn (IRQn_LAST)
+#define DVP2BUS_INT5_IRQn (IRQn_LAST)
+#define DVP2BUS_INT6_IRQn (IRQn_LAST)
+#define DVP2BUS_INT7_IRQn (IRQn_LAST)
+#define DMA2D_INT0_IRQn (IRQn_LAST)
+#define DMA2D_INT1_IRQn (IRQn_LAST)
+#define DISPLAY_IRQn (IRQn_LAST)
+#define SEOF_INT3_IRQn (IRQn_LAST)
+#define RESERVED1_IRQn (IRQn_LAST)
+#define RESERVED2_IRQn (IRQn_LAST)
+#define OSD_IRQn (IRQn_LAST)
+#define DBI_IRQn (IRQn_LAST)
+#define D0_RESERVED6_IRQn (IRQn_LAST)
+#define OSDA_BUS_DRAIN_IRQn (IRQn_LAST)
+#define OSDB_BUS_DRAIN_IRQn (IRQn_LAST)
+#define OSD_PB_IRQn (IRQn_LAST)
+#define D0_RESERVED7_IRQn (IRQn_LAST)
+#define MIPI_DSI_IRQn (IRQn_LAST)
+#define D0_RESERVED8_IRQn (IRQn_LAST)
+#define TIMER1_CH0_IRQn (IRQn_LAST)
+#define TIMER1_CH1_IRQn (IRQn_LAST)
+#define TIMER1_WDT_IRQn (IRQn_LAST)
+#define WL_ALL_IRQn (IRQn_LAST)
+#define PDS_IRQn (IRQn_LAST)
+#endif
+
+#if defined(CPU_D0)
+#define BMX_MCU_BUS_ERR_IRQn (IRQn_LAST)
+#define BMX_MCU_TO_IRQn (IRQn_LAST)
+#define M0_RESERVED2_IRQn (IRQn_LAST)
+#define IPC_M0_IRQn (IRQn_LAST)
+#define RF_TOP_INT0_IRQn (IRQn_LAST)
+#define RF_TOP_INT1_IRQn (IRQn_LAST)
+#define LZ4D_IRQn (IRQn_LAST)
+#define GAUGE_ITF_IRQn (IRQn_LAST)
+#define SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn (IRQn_LAST)
+#define SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn (IRQn_LAST)
+#define SEC_ENG_ID1_CDET_IRQn (IRQn_LAST)
+#define SEC_ENG_ID0_CDET_IRQn (IRQn_LAST)
+#define SF_CTRL_ID1_IRQn (IRQn_LAST)
+#define SF_CTRL_ID0_IRQn (IRQn_LAST)
+#define DMA0_ALL_IRQn (IRQn_LAST)
+#define DMA1_ALL_IRQn (IRQn_LAST)
+#define SDH_IRQn (IRQn_LAST)
+#define MM_ALL_IRQn (IRQn_LAST)
+#define IRTX_IRQn (IRQn_LAST)
+#define IRRX_IRQn (IRQn_LAST)
+#define USB_IRQn (IRQn_LAST)
+#define AUPDM_TOUCH_IRQn (IRQn_LAST)
+#define M0_RESERVED23_IRQn (IRQn_LAST)
+#define EMAC_IRQn (IRQn_LAST)
+#define GPADC_DMA_IRQn (IRQn_LAST)
+#define EFUSE_IRQn (IRQn_LAST)
+#define SPI0_IRQn (IRQn_LAST)
+#define UART0_IRQn (IRQn_LAST)
+#define UART1_IRQn (IRQn_LAST)
+#define UART2_IRQn (IRQn_LAST)
+#define GPIO_DMA_IRQn (IRQn_LAST)
+#define I2C0_IRQn (IRQn_LAST)
+#define IPC_RSVD_IRQn (IRQn_LAST)
+#define IPC_LP_IRQn (IRQn_LAST)
+#define TIMER0_CH0_IRQn (IRQn_LAST)
+#define TIMER0_CH1_IRQn (IRQn_LAST)
+#define TIMER0_WDT_IRQn (IRQn_LAST)
+#define I2C1_IRQn (IRQn_LAST)
+#define I2S_IRQn (IRQn_LAST)
+#define ANA_OCP_OUT_TO_CPU_0_IRQn (IRQn_LAST)
+#define ANA_OCP_OUT_TO_CPU_1_IRQn (IRQn_LAST)
+#define ANA_OCP_OUT_TO_CPU_2_IRQn (IRQn_LAST)
+#define GPIO_INT0_IRQn (IRQn_LAST)
+#define DM_IRQn (IRQn_LAST)
+#define BT_IRQn (IRQn_LAST)
+#define M154_REQ_ACK_IRQn (IRQn_LAST)
+#define M154_INT_IRQn (IRQn_LAST)
+#define M154_AES_IRQn (IRQn_LAST)
+#define PDS_WAKEUP_IRQn (IRQn_LAST)
+#define HBN_OUT0_IRQn (IRQn_LAST)
+#define HBN_OUT1_IRQn (IRQn_LAST)
+#define BOR_IRQn (IRQn_LAST)
+#define WIFI_IRQn (IRQn_LAST)
+#define BZ_PHY_INT_IRQn (IRQn_LAST)
+#define BLE_IRQn (IRQn_LAST)
+#define MAC_TXRX_TIMER_IRQn (IRQn_LAST)
+#define MAC_TXRX_MISC_IRQn (IRQn_LAST)
+#define MAC_RX_TRG_IRQn (IRQn_LAST)
+#define MAC_TX_TRG_IRQn (IRQn_LAST)
+#define MAC_GEN_IRQn (IRQn_LAST)
+#define MAC_PORT_TRG_IRQn (IRQn_LAST)
+#define WIFI_IPC_PUBLIC_IRQn (IRQn_LAST)
+#endif
+
+/**
+ * @brief BL808 Memory Map Definitions
+ */
+#define BL808_OCRAM_BASE (0x22020000)
+#define BL808_OCRAM_END (0x22020000 + 64 * 1024)
+#define BL808_OCRAM_CACHEABLE_BASE (0x62020000)
+#define BL808_OCRAM_CACHEABLE_END (0x62020000 + 64 * 1024)
+
+#define BL808_WRAM_BASE (0x22030000)
+#define BL808_WRAM_END (0x22030000 + 160 * 1024)
+#define BL808_WRAM_CACHEABLE_BASE (0x62030000)
+#define BL808_WRAM_CACHEABLE_END (0x62030000 + 160 * 1024)
+
+#define BL808_MCU_ALLRAM_BASE (0x22020000)
+#define BL808_MCU_ALLRAM_END (0x22020000 + 64 * 1024 + 160 * 1024)
+#define BL808_MCU_ALLRAM_CACHEABLE_BASE (0x62020000)
+#define BL808_MCU_ALLRAM_CACHEABLE_END (0x62020000 + 64 * 1024 + 160 * 1024)
+
+#define BL808_DRAM_BASE (0x3EF80000)
+#define BL808_DRAM_END (0x3EF80000 + 512 * 1024)
+#define BL808_DRAM_CACHEABLE_BASE (0x7EF80000)
+#define BL808_DRAM_CACHEABLE_END (0x7EF80000 + 512 * 1024)
+
+#define BL808_VRAM_BASE (0x3F000000)
+#define BL808_VRAM_END (0x3F000000 + 32 * 1024)
+#define BL808_VRAM_CACHEABLE_BASE (0x7F000000)
+#define BL808_VRAM_CACHEABLE_END (0x7F000000 + 32 * 1024)
+
+#define BL808_MM_ALLRAM_BASE (0x3EF80000)
+#define BL808_MM_ALLRAM_END (0x3EF80000 + 512 * 1024 + 32 * 1024)
+#define BL808_MM_ALLRAM_CACHEABLE_BASE (0x7EF80000)
+#define BL808_MM_ALLRAM_CACHEABLE_END (0x7EF80000 + 512 * 1024 + 32 * 1024)
+
+#define BL808_FLASH_XIP_BASE (0x58000000)
+#define BL808_FLASH_XIP_END (0x58000000 + 64 * 1024 * 1024)
+#define BL808_FLASH2_XIP_BASE (0x5C000000)
+#define BL808_FLASH2_XIP_END (0x5C000000 + 64 * 1024 * 1024)
+#define BL808_FLASH_XIP_REMAP0_BASE (0xD8000000)
+#define BL808_FLASH_XIP_REMAP0_END (0xD8000000 + 64 * 1024 * 1024)
+#define BL808_FLASH2_XIP_REMAP0_BASE (0xDC000000)
+#define BL808_FLASH2_XIP_REMAP0_END (0xDC000000 + 64 * 1024 * 1024)
+
+#define BL808_MM_WHOLERAM_BASE (0x3EF80000)
+#define BL808_MM_WHOLERAM_END (0x3EF80000 + 512 * 1024 + 96 * 1024)
+#define BL808_MM_WHOLERAM_CACHEABLE_BASE (0x7EF80000)
+#define BL808_MM_WHOLERAM_CACHEABLE_END (0x7EF80000 + 512 * 1024 + 96 * 1024)
+
+/*@} end of group Memory_Map_Section */
+
+/* BL808 peripherals base address */
+/* WLSYS */
+#define GLB_BASE ((uint32_t)0x20000000)
+#define MIX_BASE ((uint32_t)0x20001000)
+#define GPIP_BASE ((uint32_t)0x20002000)
+#define PHY_BASE ((uint32_t)0x20002800)
+#define AGC_BASE ((uint32_t)0x20002c00)
+#define SEC_DBG_BASE ((uint32_t)0x20003000)
+#define SEC_ENG_BASE ((uint32_t)0x20004000)
+#define TZ1_BASE ((uint32_t)0x20005000)
+#define TZC_SEC_BASE ((uint32_t)0x20005000)
+#define TZ2_BASE ((uint32_t)0x20006000)
+#define TZC_NSEC_BASE ((uint32_t)0x20006000)
+#define EFUSE_BASE ((uint32_t)0x20056000)
+#define EF_DATA_BASE ((uint32_t)0x20056000)
+#define EF_CTRL_BASE ((uint32_t)0x20056000)
+#define CCI_BASE ((uint32_t)0x20008000)
+#define MCU_MISC_BASE ((uint32_t)0x20009000)
+#define L1C_BASE ((uint32_t)0x20009000)
+#define UART0_BASE ((uint32_t)0x2000a000)
+#define UART1_BASE ((uint32_t)0x2000a100)
+#define SPI0_BASE ((uint32_t)0x2000a200)
+#define I2C0_BASE ((uint32_t)0x2000a300)
+#define PWM_BASE ((uint32_t)0x2000a400)
+#define TIMER0_BASE ((uint32_t)0x2000a500)
+#define IR_BASE ((uint32_t)0x2000a600)
+#define CKS_BASE ((uint32_t)0x2000a700)
+#define IPC0_BASE ((uint32_t)0x2000a800)
+#define IPC1_BASE ((uint32_t)0x2000a840)
+#define I2C1_BASE ((uint32_t)0x2000a900)
+#define UART2_BASE ((uint32_t)0x2000aa00)
+#define ISO11898_BASE ((uint32_t)0x2000aa00)
+#define I2S_BASE ((uint32_t)0x2000ab00)
+#define PDM0_BASE ((uint32_t)0x2000a000)
+#define LZ4D_BASE ((uint32_t)0x2000ad00)
+#define QSPI_BASE ((uint32_t)0x2000b000)
+#define SF_CTRL_BASE ((uint32_t)0x2000b000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x2000b600)
+#define DMA0_BASE ((uint32_t)0x2000c000)
+#define PDS_BASE ((uint32_t)0x2000e000)
+#define HBN_BASE ((uint32_t)0x2000f000)
+#define AON_BASE ((uint32_t)0x2000f000)
+#define EMI_MISC_BASE ((uint32_t)0x20050000)
+#define PSRAM_CTRL_BASE ((uint32_t)0x20052000)
+#define USB_BASE ((uint32_t)0x20072000)
+#define AUDIO_BASE ((uint32_t)0x20055000)
+#define SDH_BASE ((uint32_t)0x20060000)
+#define EMAC_BASE ((uint32_t)0x20070000)
+#define DMA1_BASE ((uint32_t)0x20071000)
+
+/* MMSYS */
+#define MM_MISC_BASE ((uint32_t)0x30000000)
+#define DMA2_BASE ((uint32_t)0x30001000)
+#define UART3_BASE ((uint32_t)0x30002000)
+#define I2C2_BASE ((uint32_t)0x30003000)
+#define I2C3_BASE ((uint32_t)0x30004000)
+#define IPC2_BASE ((uint32_t)0x30005000)
+#define DMA2D_BASE ((uint32_t)0x30006000)
+#define CLKRST_CTRL_BASE ((uint32_t)0x30007000)
+#define MM_GLB_BASE ((uint32_t)0x30007000)
+#define SPI1_BASE ((uint32_t)0x30008000)
+#define TIMER1_BASE ((uint32_t)0x30009000)
+#define PSRAM_UHS_BASE ((uint32_t)0x3000f000)
+
+/* SUBSYS */
+#define SUB_MISC_BASE ((uint32_t)0x30010000)
+#define SUB_BASE ((uint32_t)0x30011000)
+#define DVP0_BASE ((uint32_t)0x30012000)
+#define DVP1_BASE ((uint32_t)0x30012100)
+#define DVP2_BASE ((uint32_t)0x30012200)
+#define DVP3_BASE ((uint32_t)0x30012300)
+#define DVP4_BASE ((uint32_t)0x30012400)
+#define DVP5_BASE ((uint32_t)0x30012500)
+#define DVP6_BASE ((uint32_t)0x30012600)
+#define DVP7_BASE ((uint32_t)0x30012700)
+#define DVP_TSRC0_BASE ((uint32_t)0x30012800)
+#define DVP_TSRC1_BASE ((uint32_t)0x30012900)
+#define AXI_CTRL_NR3D_BASE ((uint32_t)0x30012a00)
+#define OSD_PROBE_BASE ((uint32_t)0x30012b00)
+#define OSD_A_BASE ((uint32_t)0x30013000)
+#define OSD_B_BASE ((uint32_t)0x30014000)
+#define OSD_DP_BASE ((uint32_t)0x30015000)
+#define OSD_BLEND0_OFFSET (0x000)
+#define OSD_BLEND1_OFFSET (0x100)
+#define OSD_BLEND2_OFFSET (0x200)
+#define OSD_BLEND3_OFFSET (0x300)
+#define OSD_DRAW_LOW_OFFSET (0x400)
+#define OSD_DRAW_HIGH_OFFSET (0x504)
+#define MIPI_BASE ((uint32_t)0x3001a000)
+#define DBI_BASE ((uint32_t)0x3001b000)
+#define DSI_BASE ((uint32_t)0x3001a100)
+#define CSI_BASE ((uint32_t)0x3001a000)
+
+/* CODEC_SUBSYS */
+#define CODEC_MISC_BASE ((uint32_t)0x30020000)
+#define MJPEG_BASE ((uint32_t)0x30021000)
+#define VIDEO_BASE ((uint32_t)0x30022000)
+#define MJPEG_DEC_BASE ((uint32_t)0x30023000)
+#define BL_CNN_BASE ((uint32_t)0x30024000)
+
+#define HBN_RAM_BASE ((uint32_t)0x20010000)
+
+#define RF_BASE ((uint32_t)0x20001000)
+
+typedef enum {
+ BL_AHB_MASTER_CPU = 0x00,
+ BL_AHB_MASTER_SDU = 0x01,
+ BL_AHB_MASTER_SEC = 0x02,
+ BL_AHB_MASTER_DMA = 0x03,
+ BL_AHB_MASTER_CCI = 0x04,
+ BL_AHB_MASTER_WIFI_PLATFORM = 0x05,
+ BL_AHB_MASTER_WIFI_MAC_PHY = 0x06,
+ BL_AHB_MASTER_WIFI_PHY = 0x07,
+ BL_AHB_MASTER_MAX = 0x08,
+} BL_AHB_Master_Type;
+
+typedef enum {
+ BL_AHB_SLAVE1_GLB = 0x00, //cgen rsvd
+ BL_AHB_SLAVE1_RF_TOP = 0x01, //swrst mix
+ BL_AHB_SLAVE1_GPIP = 0x02,
+ BL_AHB_SLAVE1_SEC_DBG = 0x03,
+ BL_AHB_SLAVE1_SEC_ENG = 0x04,
+ BL_AHB_SLAVE1_TZ = 0x05, //swrst tz1,cgen tz1+tz2
+ BL_AHB_SLAVE1_RSVD6 = 0x06, //swrst tz2,
+ BL_AHB_SLAVE1_EF_CTRL = 0x07,
+ BL_AHB_SLAVE1_CCI = 0x08, //cgen rsvd
+ BL_AHB_SLAVE1_L1C = 0x09, //cgen rsvd
+ BL_AHB_SLAVE1_RSVD10 = 0x0A,
+ BL_AHB_SLAVE1_SF_CTRL = 0x0B,
+ BL_AHB_SLAVE1_DMA = 0x0C,
+ BL_AHB_SLAVE1_SDU = 0x0D, //cgen rsvd
+ BL_AHB_SLAVE1_PDS = 0x0E, //cgen rsvd
+ BL_AHB_SLAVE1_RSVD15 = 0x0F,
+ BL_AHB_SLAVE1_UART0 = 0x10,
+ BL_AHB_SLAVE1_UART1 = 0x11,
+ BL_AHB_SLAVE1_SPI = 0x12,
+ BL_AHB_SLAVE1_I2C = 0x13,
+ BL_AHB_SLAVE1_PWM = 0x14,
+ BL_AHB_SLAVE1_TIMER = 0x15,
+ BL_AHB_SLAVE1_IRR = 0x16,
+ BL_AHB_SLAVE1_CKS = 0x17,
+ BL_AHB_SLAVE1_QDEC = 0x18,
+ BL_AHB_SLAVE1_KYS = 0x19,
+ BL_AHB_SLAVE1_UART2 = 0x1A,
+ BL_AHB_SLAVE1_RSVD27 = 0x1B,
+ BL_AHB_SLAVE1_RSVD28 = 0x1C,
+ BL_AHB_SLAVE1_RSVD29 = 0x1D,
+ BL_AHB_SLAVE1_RSVD30 = 0x1E,
+ BL_AHB_SLAVE1_RSVD31 = 0x1F,
+ BL_AHB_SLAVE1_MAX = 0x20,
+ BL_AHB_SLAVE1_GPADC = 0x21, /* not used for cgen and swrst */
+ BL_AHB_SLAVE1_GPDAC = 0x22, /* not used for cgen and swrst */
+ BL_AHB_SLAVE1_I2S = 0x23, /* not used for cgen and swrst */
+ BL_AHB_SLAVE1_CAM = 0x24, /* not used for cgen and swrst */
+} BL_AHB_Slave1_Type;
+
+typedef enum {
+ BL_AHB_SLAVE2_RSVD0 = 0x00,
+ BL_AHB_SLAVE2_RSVD1 = 0x01,
+ BL_AHB_SLAVE2_RSVD2 = 0x02,
+ BL_AHB_SLAVE2_RSVD3 = 0x03,
+ BL_AHB_SLAVE2_WIFI = 0x04,
+ BL_AHB_SLAVE2_RSVD5 = 0x05,
+ BL_AHB_SLAVE2_RSVD6 = 0x06,
+ BL_AHB_SLAVE2_RSVD7 = 0x07,
+ BL_AHB_SLAVE2_BT_BLE = 0x08,
+ BL_AHB_SLAVE2_M154 = 0x09,
+ BL_AHB_SLAVE2_BT_BLE2 = 0x0A,
+ BL_AHB_SLAVE2_M1542 = 0x0B,
+ BL_AHB_SLAVE2_RSVD12 = 0x0C,
+ BL_AHB_SLAVE2_RSVD13 = 0x0D,
+ BL_AHB_SLAVE2_RSVD14 = 0x0E,
+ BL_AHB_SLAVE2_RSVD15 = 0x0F,
+ BL_AHB_SLAVE2_EXT_EMI_MISC = 0x10,
+ BL_AHB_SLAVE2_EXT_PSRAM0_CTRL = 0x11,
+ BL_AHB_SLAVE2_EXT_PSRAM1_CTRL = 0x12,
+ BL_AHB_SLAVE2_EXT_USB = 0x13,
+ BL_AHB_SLAVE2_EXT_MIX2 = 0x14,
+ BL_AHB_SLAVE2_EXT_AUDIO = 0x15,
+ BL_AHB_SLAVE2_EXT_SDH = 0x16,
+ BL_AHB_SLAVE2_EXT_EMAC = 0x17,
+ BL_AHB_SLAVE2_EXT_DMA2 = 0x18,
+ BL_AHB_SLAVE2_EXT_RSVD25 = 0x19,
+ BL_AHB_SLAVE2_EXT_RSVD26 = 0x1A,
+ BL_AHB_SLAVE2_EXT_RSVD27 = 0x1B,
+ BL_AHB_SLAVE2_MAX = 0x1C,
+} BL_AHB_Slave2_Type;
+
+typedef enum {
+ BL_AHB_SLAVE3_WIFIPLL_240M = 0x00,
+ BL_AHB_SLAVE3_CPUPLL_120M = 0x01,
+ BL_AHB_SLAVE3_CPUPLL_300M = 0x02,
+ BL_AHB_SLAVE3_CPUPLL_600M = 0x03,
+ BL_AHB_SLAVE3_MAX = 0x04,
+} BL_AHB_Slave3_Type;
+
+typedef enum {
+ BL_AHB_SEC_ENG_AES0 = 0,
+ BL_AHB_SEC_ENG_AES1,
+ BL_AHB_SEC_ENG_SHA0,
+ BL_AHB_SEC_ENG_SHA1,
+} BL_AHB_Sec_Eng_Type;
+
+typedef enum {
+ BL_AHB_DMA0_CH0 = 0,
+ BL_AHB_DMA0_CH1,
+ BL_AHB_DMA0_CH2,
+ BL_AHB_DMA0_CH3,
+ BL_AHB_DMA0_CH4,
+ BL_AHB_DMA0_CH5,
+ BL_AHB_DMA0_CH6,
+ BL_AHB_DMA0_CH7,
+} BL_AHB_DMA0_CHNL_Type;
+
+typedef enum {
+ BL_CORE_MASTER_IBUS_CPU = 0,
+ BL_CORE_MASTER_DBUS_CPU,
+ BL_CORE_MASTER_BUS_S2F,
+ BL_CORE_MASTER_MAX,
+} BL_Core_Master_Type;
+
+typedef enum {
+ BL_CORE_SLAVE0_DTCM_CPU = 0,
+ BL_CORE_SLAVE0_MAX,
+} BL_Core_Slave0_Type;
+
+typedef enum {
+ BL_CORE_SLAVE1_XIP_CPU = 0,
+ BL_CORE_SLAVE1_ITCM_CPU,
+ BL_CORE_SLAVE1_ROM,
+ BL_CORE_SLAVE1_MAX,
+} BL_Core_Slave1_Type;
+
+typedef enum {
+ BL_CORE_SLAVE2_F2S = 0,
+ BL_CORE_SLAVE2_MAX,
+} BL_Core_Slave2_Type;
+
+/**
+ * @}
+ */
+#include
+/* ARM CPU include files */
+#ifdef ARCH_ARM
+#ifdef CPU_AP_CM4
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#endif
+#ifdef CPU_NP_CM0
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#endif
+#endif
+/* RISCV CPU include files */
+#ifdef ARCH_RISCV
+#ifdef __GNUC__
+#include
+#endif
+#endif
+
+#endif
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/cci_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/cci_reg.h
new file mode 100644
index 00000000..e6ef09f2
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/cci_reg.h
@@ -0,0 +1,1353 @@
+/**
+ ******************************************************************************
+ * @file cci_reg.h
+ * @version V1.0
+ * @date 2021-07-14
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __CCI_REG_H__
+#define __CCI_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : cci_cfg */
+#define CCI_CFG_OFFSET (0x0)
+#define CCI_EN CCI_EN
+#define CCI_EN_POS (0U)
+#define CCI_EN_LEN (1U)
+#define CCI_EN_MSK (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)
+#define CCI_EN_UMSK (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS))
+#define CCI_SLV_SEL_CCI2 CCI_SLV_SEL_CCI2
+#define CCI_SLV_SEL_CCI2_POS (1U)
+#define CCI_SLV_SEL_CCI2_LEN (1U)
+#define CCI_SLV_SEL_CCI2_MSK (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)
+#define CCI_SLV_SEL_CCI2_UMSK (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS))
+#define CCI_MAS_SEL_CCI2 CCI_MAS_SEL_CCI2
+#define CCI_MAS_SEL_CCI2_POS (2U)
+#define CCI_MAS_SEL_CCI2_LEN (1U)
+#define CCI_MAS_SEL_CCI2_MSK (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)
+#define CCI_MAS_SEL_CCI2_UMSK (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS))
+#define CCI_MAS_HW_MODE CCI_MAS_HW_MODE
+#define CCI_MAS_HW_MODE_POS (3U)
+#define CCI_MAS_HW_MODE_LEN (1U)
+#define CCI_MAS_HW_MODE_MSK (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)
+#define CCI_MAS_HW_MODE_UMSK (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS))
+#define CCI_REG_M_CCI_SCLK_EN CCI_REG_M_CCI_SCLK_EN
+#define CCI_REG_M_CCI_SCLK_EN_POS (4U)
+#define CCI_REG_M_CCI_SCLK_EN_LEN (1U)
+#define CCI_REG_M_CCI_SCLK_EN_MSK (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)
+#define CCI_REG_M_CCI_SCLK_EN_UMSK (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS))
+#define CCI_REG_DIV_M_CCI_SCLK CCI_REG_DIV_M_CCI_SCLK
+#define CCI_REG_DIV_M_CCI_SCLK_POS (5U)
+#define CCI_REG_DIV_M_CCI_SCLK_LEN (2U)
+#define CCI_REG_DIV_M_CCI_SCLK_MSK (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)
+#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS))
+#define CCI_CFG_CCI1_PRE_READ CCI_CFG_CCI1_PRE_READ
+#define CCI_CFG_CCI1_PRE_READ_POS (7U)
+#define CCI_CFG_CCI1_PRE_READ_LEN (1U)
+#define CCI_CFG_CCI1_PRE_READ_MSK (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)
+#define CCI_CFG_CCI1_PRE_READ_UMSK (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS))
+#define CCI_REG_SCCI_CLK_INV CCI_REG_SCCI_CLK_INV
+#define CCI_REG_SCCI_CLK_INV_POS (8U)
+#define CCI_REG_SCCI_CLK_INV_LEN (1U)
+#define CCI_REG_SCCI_CLK_INV_MSK (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)
+#define CCI_REG_SCCI_CLK_INV_UMSK (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS))
+#define CCI_REG_MCCI_CLK_INV CCI_REG_MCCI_CLK_INV
+#define CCI_REG_MCCI_CLK_INV_POS (9U)
+#define CCI_REG_MCCI_CLK_INV_LEN (1U)
+#define CCI_REG_MCCI_CLK_INV_MSK (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)
+#define CCI_REG_MCCI_CLK_INV_UMSK (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS))
+
+/* 0x4 : cci_addr */
+#define CCI_ADDR_OFFSET (0x4)
+#define CCI_APB_CCI_ADDR CCI_APB_CCI_ADDR
+#define CCI_APB_CCI_ADDR_POS (0U)
+#define CCI_APB_CCI_ADDR_LEN (32U)
+#define CCI_APB_CCI_ADDR_MSK (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)
+#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS))
+
+/* 0x8 : cci_wdata */
+#define CCI_WDATA_OFFSET (0x8)
+#define CCI_APB_CCI_WDATA CCI_APB_CCI_WDATA
+#define CCI_APB_CCI_WDATA_POS (0U)
+#define CCI_APB_CCI_WDATA_LEN (32U)
+#define CCI_APB_CCI_WDATA_MSK (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)
+#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS))
+
+/* 0xC : cci_rdata */
+#define CCI_RDATA_OFFSET (0xC)
+#define CCI_APB_CCI_RDATA CCI_APB_CCI_RDATA
+#define CCI_APB_CCI_RDATA_POS (0U)
+#define CCI_APB_CCI_RDATA_LEN (32U)
+#define CCI_APB_CCI_RDATA_MSK (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)
+#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS))
+
+/* 0x10 : cci_ctl */
+#define CCI_CTL_OFFSET (0x10)
+#define CCI_WRITE_FLAG CCI_WRITE_FLAG
+#define CCI_WRITE_FLAG_POS (0U)
+#define CCI_WRITE_FLAG_LEN (1U)
+#define CCI_WRITE_FLAG_MSK (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)
+#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS))
+#define CCI_READ_FLAG CCI_READ_FLAG
+#define CCI_READ_FLAG_POS (1U)
+#define CCI_READ_FLAG_LEN (1U)
+#define CCI_READ_FLAG_MSK (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)
+#define CCI_READ_FLAG_UMSK (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS))
+#define CCI_AHB_STATE CCI_AHB_STATE
+#define CCI_AHB_STATE_POS (2U)
+#define CCI_AHB_STATE_LEN (2U)
+#define CCI_AHB_STATE_MSK (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)
+#define CCI_AHB_STATE_UMSK (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS))
+
+/* 0x750 : audio_pll_cfg0 */
+#define CCI_AUDIO_PLL_CFG0_OFFSET (0x750)
+#define CCI_AUPLL_SDM_RSTB CCI_AUPLL_SDM_RSTB
+#define CCI_AUPLL_SDM_RSTB_POS (0U)
+#define CCI_AUPLL_SDM_RSTB_LEN (1U)
+#define CCI_AUPLL_SDM_RSTB_MSK (((1U << CCI_AUPLL_SDM_RSTB_LEN) - 1) << CCI_AUPLL_SDM_RSTB_POS)
+#define CCI_AUPLL_SDM_RSTB_UMSK (~(((1U << CCI_AUPLL_SDM_RSTB_LEN) - 1) << CCI_AUPLL_SDM_RSTB_POS))
+#define CCI_AUPLL_POSTDIV_RSTB CCI_AUPLL_POSTDIV_RSTB
+#define CCI_AUPLL_POSTDIV_RSTB_POS (1U)
+#define CCI_AUPLL_POSTDIV_RSTB_LEN (1U)
+#define CCI_AUPLL_POSTDIV_RSTB_MSK (((1U << CCI_AUPLL_POSTDIV_RSTB_LEN) - 1) << CCI_AUPLL_POSTDIV_RSTB_POS)
+#define CCI_AUPLL_POSTDIV_RSTB_UMSK (~(((1U << CCI_AUPLL_POSTDIV_RSTB_LEN) - 1) << CCI_AUPLL_POSTDIV_RSTB_POS))
+#define CCI_AUPLL_FBDV_RSTB CCI_AUPLL_FBDV_RSTB
+#define CCI_AUPLL_FBDV_RSTB_POS (2U)
+#define CCI_AUPLL_FBDV_RSTB_LEN (1U)
+#define CCI_AUPLL_FBDV_RSTB_MSK (((1U << CCI_AUPLL_FBDV_RSTB_LEN) - 1) << CCI_AUPLL_FBDV_RSTB_POS)
+#define CCI_AUPLL_FBDV_RSTB_UMSK (~(((1U << CCI_AUPLL_FBDV_RSTB_LEN) - 1) << CCI_AUPLL_FBDV_RSTB_POS))
+#define CCI_AUPLL_REFDIV_RSTB CCI_AUPLL_REFDIV_RSTB
+#define CCI_AUPLL_REFDIV_RSTB_POS (3U)
+#define CCI_AUPLL_REFDIV_RSTB_LEN (1U)
+#define CCI_AUPLL_REFDIV_RSTB_MSK (((1U << CCI_AUPLL_REFDIV_RSTB_LEN) - 1) << CCI_AUPLL_REFDIV_RSTB_POS)
+#define CCI_AUPLL_REFDIV_RSTB_UMSK (~(((1U << CCI_AUPLL_REFDIV_RSTB_LEN) - 1) << CCI_AUPLL_REFDIV_RSTB_POS))
+#define CCI_PU_AUPLL_POSTDIV CCI_PU_AUPLL_POSTDIV
+#define CCI_PU_AUPLL_POSTDIV_POS (4U)
+#define CCI_PU_AUPLL_POSTDIV_LEN (1U)
+#define CCI_PU_AUPLL_POSTDIV_MSK (((1U << CCI_PU_AUPLL_POSTDIV_LEN) - 1) << CCI_PU_AUPLL_POSTDIV_POS)
+#define CCI_PU_AUPLL_POSTDIV_UMSK (~(((1U << CCI_PU_AUPLL_POSTDIV_LEN) - 1) << CCI_PU_AUPLL_POSTDIV_POS))
+#define CCI_PU_AUPLL_FBDV CCI_PU_AUPLL_FBDV
+#define CCI_PU_AUPLL_FBDV_POS (5U)
+#define CCI_PU_AUPLL_FBDV_LEN (1U)
+#define CCI_PU_AUPLL_FBDV_MSK (((1U << CCI_PU_AUPLL_FBDV_LEN) - 1) << CCI_PU_AUPLL_FBDV_POS)
+#define CCI_PU_AUPLL_FBDV_UMSK (~(((1U << CCI_PU_AUPLL_FBDV_LEN) - 1) << CCI_PU_AUPLL_FBDV_POS))
+#define CCI_PU_AUPLL_CLAMP_OP CCI_PU_AUPLL_CLAMP_OP
+#define CCI_PU_AUPLL_CLAMP_OP_POS (6U)
+#define CCI_PU_AUPLL_CLAMP_OP_LEN (1U)
+#define CCI_PU_AUPLL_CLAMP_OP_MSK (((1U << CCI_PU_AUPLL_CLAMP_OP_LEN) - 1) << CCI_PU_AUPLL_CLAMP_OP_POS)
+#define CCI_PU_AUPLL_CLAMP_OP_UMSK (~(((1U << CCI_PU_AUPLL_CLAMP_OP_LEN) - 1) << CCI_PU_AUPLL_CLAMP_OP_POS))
+#define CCI_PU_AUPLL_PFD CCI_PU_AUPLL_PFD
+#define CCI_PU_AUPLL_PFD_POS (7U)
+#define CCI_PU_AUPLL_PFD_LEN (1U)
+#define CCI_PU_AUPLL_PFD_MSK (((1U << CCI_PU_AUPLL_PFD_LEN) - 1) << CCI_PU_AUPLL_PFD_POS)
+#define CCI_PU_AUPLL_PFD_UMSK (~(((1U << CCI_PU_AUPLL_PFD_LEN) - 1) << CCI_PU_AUPLL_PFD_POS))
+#define CCI_PU_AUPLL_CP CCI_PU_AUPLL_CP
+#define CCI_PU_AUPLL_CP_POS (8U)
+#define CCI_PU_AUPLL_CP_LEN (1U)
+#define CCI_PU_AUPLL_CP_MSK (((1U << CCI_PU_AUPLL_CP_LEN) - 1) << CCI_PU_AUPLL_CP_POS)
+#define CCI_PU_AUPLL_CP_UMSK (~(((1U << CCI_PU_AUPLL_CP_LEN) - 1) << CCI_PU_AUPLL_CP_POS))
+#define CCI_PU_AUPLL_SFREG CCI_PU_AUPLL_SFREG
+#define CCI_PU_AUPLL_SFREG_POS (9U)
+#define CCI_PU_AUPLL_SFREG_LEN (1U)
+#define CCI_PU_AUPLL_SFREG_MSK (((1U << CCI_PU_AUPLL_SFREG_LEN) - 1) << CCI_PU_AUPLL_SFREG_POS)
+#define CCI_PU_AUPLL_SFREG_UMSK (~(((1U << CCI_PU_AUPLL_SFREG_LEN) - 1) << CCI_PU_AUPLL_SFREG_POS))
+#define CCI_PU_AUPLL CCI_PU_AUPLL
+#define CCI_PU_AUPLL_POS (10U)
+#define CCI_PU_AUPLL_LEN (1U)
+#define CCI_PU_AUPLL_MSK (((1U << CCI_PU_AUPLL_LEN) - 1) << CCI_PU_AUPLL_POS)
+#define CCI_PU_AUPLL_UMSK (~(((1U << CCI_PU_AUPLL_LEN) - 1) << CCI_PU_AUPLL_POS))
+#define CCI_PU_AUPLL_CLKTREE CCI_PU_AUPLL_CLKTREE
+#define CCI_PU_AUPLL_CLKTREE_POS (11U)
+#define CCI_PU_AUPLL_CLKTREE_LEN (1U)
+#define CCI_PU_AUPLL_CLKTREE_MSK (((1U << CCI_PU_AUPLL_CLKTREE_LEN) - 1) << CCI_PU_AUPLL_CLKTREE_POS)
+#define CCI_PU_AUPLL_CLKTREE_UMSK (~(((1U << CCI_PU_AUPLL_CLKTREE_LEN) - 1) << CCI_PU_AUPLL_CLKTREE_POS))
+
+/* 0x754 : audio_pll_cfg1 */
+#define CCI_AUDIO_PLL_CFG1_OFFSET (0x754)
+#define CCI_AUPLL_POSTDIV CCI_AUPLL_POSTDIV
+#define CCI_AUPLL_POSTDIV_POS (0U)
+#define CCI_AUPLL_POSTDIV_LEN (7U)
+#define CCI_AUPLL_POSTDIV_MSK (((1U << CCI_AUPLL_POSTDIV_LEN) - 1) << CCI_AUPLL_POSTDIV_POS)
+#define CCI_AUPLL_POSTDIV_UMSK (~(((1U << CCI_AUPLL_POSTDIV_LEN) - 1) << CCI_AUPLL_POSTDIV_POS))
+#define CCI_AUPLL_REFDIV_RATIO CCI_AUPLL_REFDIV_RATIO
+#define CCI_AUPLL_REFDIV_RATIO_POS (8U)
+#define CCI_AUPLL_REFDIV_RATIO_LEN (4U)
+#define CCI_AUPLL_REFDIV_RATIO_MSK (((1U << CCI_AUPLL_REFDIV_RATIO_LEN) - 1) << CCI_AUPLL_REFDIV_RATIO_POS)
+#define CCI_AUPLL_REFDIV_RATIO_UMSK (~(((1U << CCI_AUPLL_REFDIV_RATIO_LEN) - 1) << CCI_AUPLL_REFDIV_RATIO_POS))
+#define CCI_AUPLL_REFCLK_SEL CCI_AUPLL_REFCLK_SEL
+#define CCI_AUPLL_REFCLK_SEL_POS (16U)
+#define CCI_AUPLL_REFCLK_SEL_LEN (2U)
+#define CCI_AUPLL_REFCLK_SEL_MSK (((1U << CCI_AUPLL_REFCLK_SEL_LEN) - 1) << CCI_AUPLL_REFCLK_SEL_POS)
+#define CCI_AUPLL_REFCLK_SEL_UMSK (~(((1U << CCI_AUPLL_REFCLK_SEL_LEN) - 1) << CCI_AUPLL_REFCLK_SEL_POS))
+#define CCI_AUPLL_VG11_SEL CCI_AUPLL_VG11_SEL
+#define CCI_AUPLL_VG11_SEL_POS (20U)
+#define CCI_AUPLL_VG11_SEL_LEN (2U)
+#define CCI_AUPLL_VG11_SEL_MSK (((1U << CCI_AUPLL_VG11_SEL_LEN) - 1) << CCI_AUPLL_VG11_SEL_POS)
+#define CCI_AUPLL_VG11_SEL_UMSK (~(((1U << CCI_AUPLL_VG11_SEL_LEN) - 1) << CCI_AUPLL_VG11_SEL_POS))
+#define CCI_AUPLL_VG13_SEL CCI_AUPLL_VG13_SEL
+#define CCI_AUPLL_VG13_SEL_POS (24U)
+#define CCI_AUPLL_VG13_SEL_LEN (2U)
+#define CCI_AUPLL_VG13_SEL_MSK (((1U << CCI_AUPLL_VG13_SEL_LEN) - 1) << CCI_AUPLL_VG13_SEL_POS)
+#define CCI_AUPLL_VG13_SEL_UMSK (~(((1U << CCI_AUPLL_VG13_SEL_LEN) - 1) << CCI_AUPLL_VG13_SEL_POS))
+
+/* 0x758 : audio_pll_cfg2 */
+#define CCI_AUDIO_PLL_CFG2_OFFSET (0x758)
+#define CCI_AUPLL_SEL_CP_BIAS CCI_AUPLL_SEL_CP_BIAS
+#define CCI_AUPLL_SEL_CP_BIAS_POS (0U)
+#define CCI_AUPLL_SEL_CP_BIAS_LEN (1U)
+#define CCI_AUPLL_SEL_CP_BIAS_MSK (((1U << CCI_AUPLL_SEL_CP_BIAS_LEN) - 1) << CCI_AUPLL_SEL_CP_BIAS_POS)
+#define CCI_AUPLL_SEL_CP_BIAS_UMSK (~(((1U << CCI_AUPLL_SEL_CP_BIAS_LEN) - 1) << CCI_AUPLL_SEL_CP_BIAS_POS))
+#define CCI_AUPLL_ICP_5U CCI_AUPLL_ICP_5U
+#define CCI_AUPLL_ICP_5U_POS (4U)
+#define CCI_AUPLL_ICP_5U_LEN (2U)
+#define CCI_AUPLL_ICP_5U_MSK (((1U << CCI_AUPLL_ICP_5U_LEN) - 1) << CCI_AUPLL_ICP_5U_POS)
+#define CCI_AUPLL_ICP_5U_UMSK (~(((1U << CCI_AUPLL_ICP_5U_LEN) - 1) << CCI_AUPLL_ICP_5U_POS))
+#define CCI_AUPLL_ICP_1U CCI_AUPLL_ICP_1U
+#define CCI_AUPLL_ICP_1U_POS (6U)
+#define CCI_AUPLL_ICP_1U_LEN (2U)
+#define CCI_AUPLL_ICP_1U_MSK (((1U << CCI_AUPLL_ICP_1U_LEN) - 1) << CCI_AUPLL_ICP_1U_POS)
+#define CCI_AUPLL_ICP_1U_UMSK (~(((1U << CCI_AUPLL_ICP_1U_LEN) - 1) << CCI_AUPLL_ICP_1U_POS))
+#define CCI_AUPLL_INT_FRAC_SW CCI_AUPLL_INT_FRAC_SW
+#define CCI_AUPLL_INT_FRAC_SW_POS (8U)
+#define CCI_AUPLL_INT_FRAC_SW_LEN (1U)
+#define CCI_AUPLL_INT_FRAC_SW_MSK (((1U << CCI_AUPLL_INT_FRAC_SW_LEN) - 1) << CCI_AUPLL_INT_FRAC_SW_POS)
+#define CCI_AUPLL_INT_FRAC_SW_UMSK (~(((1U << CCI_AUPLL_INT_FRAC_SW_LEN) - 1) << CCI_AUPLL_INT_FRAC_SW_POS))
+#define CCI_AUPLL_CP_STARTUP_EN CCI_AUPLL_CP_STARTUP_EN
+#define CCI_AUPLL_CP_STARTUP_EN_POS (9U)
+#define CCI_AUPLL_CP_STARTUP_EN_LEN (1U)
+#define CCI_AUPLL_CP_STARTUP_EN_MSK (((1U << CCI_AUPLL_CP_STARTUP_EN_LEN) - 1) << CCI_AUPLL_CP_STARTUP_EN_POS)
+#define CCI_AUPLL_CP_STARTUP_EN_UMSK (~(((1U << CCI_AUPLL_CP_STARTUP_EN_LEN) - 1) << CCI_AUPLL_CP_STARTUP_EN_POS))
+#define CCI_AUPLL_CP_OPAMP_EN CCI_AUPLL_CP_OPAMP_EN
+#define CCI_AUPLL_CP_OPAMP_EN_POS (10U)
+#define CCI_AUPLL_CP_OPAMP_EN_LEN (1U)
+#define CCI_AUPLL_CP_OPAMP_EN_MSK (((1U << CCI_AUPLL_CP_OPAMP_EN_LEN) - 1) << CCI_AUPLL_CP_OPAMP_EN_POS)
+#define CCI_AUPLL_CP_OPAMP_EN_UMSK (~(((1U << CCI_AUPLL_CP_OPAMP_EN_LEN) - 1) << CCI_AUPLL_CP_OPAMP_EN_POS))
+
+/* 0x75C : audio_pll_cfg3 */
+#define CCI_AUDIO_PLL_CFG3_OFFSET (0x75C)
+#define CCI_AUPLL_C4_EN CCI_AUPLL_C4_EN
+#define CCI_AUPLL_C4_EN_POS (0U)
+#define CCI_AUPLL_C4_EN_LEN (1U)
+#define CCI_AUPLL_C4_EN_MSK (((1U << CCI_AUPLL_C4_EN_LEN) - 1) << CCI_AUPLL_C4_EN_POS)
+#define CCI_AUPLL_C4_EN_UMSK (~(((1U << CCI_AUPLL_C4_EN_LEN) - 1) << CCI_AUPLL_C4_EN_POS))
+#define CCI_AUPLL_R4 CCI_AUPLL_R4
+#define CCI_AUPLL_R4_POS (4U)
+#define CCI_AUPLL_R4_LEN (2U)
+#define CCI_AUPLL_R4_MSK (((1U << CCI_AUPLL_R4_LEN) - 1) << CCI_AUPLL_R4_POS)
+#define CCI_AUPLL_R4_UMSK (~(((1U << CCI_AUPLL_R4_LEN) - 1) << CCI_AUPLL_R4_POS))
+#define CCI_AUPLL_R4_SHORT CCI_AUPLL_R4_SHORT
+#define CCI_AUPLL_R4_SHORT_POS (8U)
+#define CCI_AUPLL_R4_SHORT_LEN (1U)
+#define CCI_AUPLL_R4_SHORT_MSK (((1U << CCI_AUPLL_R4_SHORT_LEN) - 1) << CCI_AUPLL_R4_SHORT_POS)
+#define CCI_AUPLL_R4_SHORT_UMSK (~(((1U << CCI_AUPLL_R4_SHORT_LEN) - 1) << CCI_AUPLL_R4_SHORT_POS))
+#define CCI_AUPLL_C3 CCI_AUPLL_C3
+#define CCI_AUPLL_C3_POS (12U)
+#define CCI_AUPLL_C3_LEN (2U)
+#define CCI_AUPLL_C3_MSK (((1U << CCI_AUPLL_C3_LEN) - 1) << CCI_AUPLL_C3_POS)
+#define CCI_AUPLL_C3_UMSK (~(((1U << CCI_AUPLL_C3_LEN) - 1) << CCI_AUPLL_C3_POS))
+#define CCI_AUPLL_CZ CCI_AUPLL_CZ
+#define CCI_AUPLL_CZ_POS (14U)
+#define CCI_AUPLL_CZ_LEN (2U)
+#define CCI_AUPLL_CZ_MSK (((1U << CCI_AUPLL_CZ_LEN) - 1) << CCI_AUPLL_CZ_POS)
+#define CCI_AUPLL_CZ_UMSK (~(((1U << CCI_AUPLL_CZ_LEN) - 1) << CCI_AUPLL_CZ_POS))
+#define CCI_AUPLL_RZ CCI_AUPLL_RZ
+#define CCI_AUPLL_RZ_POS (16U)
+#define CCI_AUPLL_RZ_LEN (3U)
+#define CCI_AUPLL_RZ_MSK (((1U << CCI_AUPLL_RZ_LEN) - 1) << CCI_AUPLL_RZ_POS)
+#define CCI_AUPLL_RZ_UMSK (~(((1U << CCI_AUPLL_RZ_LEN) - 1) << CCI_AUPLL_RZ_POS))
+
+/* 0x760 : audio_pll_cfg4 */
+#define CCI_AUDIO_PLL_CFG4_OFFSET (0x760)
+#define CCI_AUPLL_SEL_SAMPLE_CLK CCI_AUPLL_SEL_SAMPLE_CLK
+#define CCI_AUPLL_SEL_SAMPLE_CLK_POS (0U)
+#define CCI_AUPLL_SEL_SAMPLE_CLK_LEN (2U)
+#define CCI_AUPLL_SEL_SAMPLE_CLK_MSK (((1U << CCI_AUPLL_SEL_SAMPLE_CLK_LEN) - 1) << CCI_AUPLL_SEL_SAMPLE_CLK_POS)
+#define CCI_AUPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << CCI_AUPLL_SEL_SAMPLE_CLK_LEN) - 1) << CCI_AUPLL_SEL_SAMPLE_CLK_POS))
+#define CCI_AUPLL_SEL_FB_CLK CCI_AUPLL_SEL_FB_CLK
+#define CCI_AUPLL_SEL_FB_CLK_POS (4U)
+#define CCI_AUPLL_SEL_FB_CLK_LEN (2U)
+#define CCI_AUPLL_SEL_FB_CLK_MSK (((1U << CCI_AUPLL_SEL_FB_CLK_LEN) - 1) << CCI_AUPLL_SEL_FB_CLK_POS)
+#define CCI_AUPLL_SEL_FB_CLK_UMSK (~(((1U << CCI_AUPLL_SEL_FB_CLK_LEN) - 1) << CCI_AUPLL_SEL_FB_CLK_POS))
+#define CCI_AUPLL_SDMCLK_SEL CCI_AUPLL_SDMCLK_SEL
+#define CCI_AUPLL_SDMCLK_SEL_POS (8U)
+#define CCI_AUPLL_SDMCLK_SEL_LEN (1U)
+#define CCI_AUPLL_SDMCLK_SEL_MSK (((1U << CCI_AUPLL_SDMCLK_SEL_LEN) - 1) << CCI_AUPLL_SDMCLK_SEL_POS)
+#define CCI_AUPLL_SDMCLK_SEL_UMSK (~(((1U << CCI_AUPLL_SDMCLK_SEL_LEN) - 1) << CCI_AUPLL_SDMCLK_SEL_POS))
+
+/* 0x764 : audio_pll_cfg5 */
+#define CCI_AUDIO_PLL_CFG5_OFFSET (0x764)
+#define CCI_AUPLL_VCO_SPEED CCI_AUPLL_VCO_SPEED
+#define CCI_AUPLL_VCO_SPEED_POS (0U)
+#define CCI_AUPLL_VCO_SPEED_LEN (3U)
+#define CCI_AUPLL_VCO_SPEED_MSK (((1U << CCI_AUPLL_VCO_SPEED_LEN) - 1) << CCI_AUPLL_VCO_SPEED_POS)
+#define CCI_AUPLL_VCO_SPEED_UMSK (~(((1U << CCI_AUPLL_VCO_SPEED_LEN) - 1) << CCI_AUPLL_VCO_SPEED_POS))
+
+/* 0x768 : audio_pll_cfg6 */
+#define CCI_AUDIO_PLL_CFG6_OFFSET (0x768)
+#define CCI_AUPLL_SDMIN CCI_AUPLL_SDMIN
+#define CCI_AUPLL_SDMIN_POS (0U)
+#define CCI_AUPLL_SDMIN_LEN (19U)
+#define CCI_AUPLL_SDMIN_MSK (((1U << CCI_AUPLL_SDMIN_LEN) - 1) << CCI_AUPLL_SDMIN_POS)
+#define CCI_AUPLL_SDMIN_UMSK (~(((1U << CCI_AUPLL_SDMIN_LEN) - 1) << CCI_AUPLL_SDMIN_POS))
+#define CCI_AUPLL_SDM_BYPASS CCI_AUPLL_SDM_BYPASS
+#define CCI_AUPLL_SDM_BYPASS_POS (24U)
+#define CCI_AUPLL_SDM_BYPASS_LEN (1U)
+#define CCI_AUPLL_SDM_BYPASS_MSK (((1U << CCI_AUPLL_SDM_BYPASS_LEN) - 1) << CCI_AUPLL_SDM_BYPASS_POS)
+#define CCI_AUPLL_SDM_BYPASS_UMSK (~(((1U << CCI_AUPLL_SDM_BYPASS_LEN) - 1) << CCI_AUPLL_SDM_BYPASS_POS))
+
+/* 0x76C : audio_pll_cfg7 */
+#define CCI_AUDIO_PLL_CFG7_OFFSET (0x76C)
+#define CCI_AUPLL_SDM_ORDER_SEL CCI_AUPLL_SDM_ORDER_SEL
+#define CCI_AUPLL_SDM_ORDER_SEL_POS (0U)
+#define CCI_AUPLL_SDM_ORDER_SEL_LEN (1U)
+#define CCI_AUPLL_SDM_ORDER_SEL_MSK (((1U << CCI_AUPLL_SDM_ORDER_SEL_LEN) - 1) << CCI_AUPLL_SDM_ORDER_SEL_POS)
+#define CCI_AUPLL_SDM_ORDER_SEL_UMSK (~(((1U << CCI_AUPLL_SDM_ORDER_SEL_LEN) - 1) << CCI_AUPLL_SDM_ORDER_SEL_POS))
+#define CCI_AUPLL_SDM_SIG_DITH_SEL CCI_AUPLL_SDM_SIG_DITH_SEL
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_POS (16U)
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_LEN (2U)
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_MSK (((1U << CCI_AUPLL_SDM_SIG_DITH_SEL_LEN) - 1) << CCI_AUPLL_SDM_SIG_DITH_SEL_POS)
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_UMSK (~(((1U << CCI_AUPLL_SDM_SIG_DITH_SEL_LEN) - 1) << CCI_AUPLL_SDM_SIG_DITH_SEL_POS))
+
+/* 0x770 : audio_pll_cfg8 */
+#define CCI_AUDIO_PLL_CFG8_OFFSET (0x770)
+#define CCI_AUPLL_EN_DIV1 CCI_AUPLL_EN_DIV1
+#define CCI_AUPLL_EN_DIV1_POS (0U)
+#define CCI_AUPLL_EN_DIV1_LEN (1U)
+#define CCI_AUPLL_EN_DIV1_MSK (((1U << CCI_AUPLL_EN_DIV1_LEN) - 1) << CCI_AUPLL_EN_DIV1_POS)
+#define CCI_AUPLL_EN_DIV1_UMSK (~(((1U << CCI_AUPLL_EN_DIV1_LEN) - 1) << CCI_AUPLL_EN_DIV1_POS))
+#define CCI_AUPLL_EN_DIV2 CCI_AUPLL_EN_DIV2
+#define CCI_AUPLL_EN_DIV2_POS (1U)
+#define CCI_AUPLL_EN_DIV2_LEN (1U)
+#define CCI_AUPLL_EN_DIV2_MSK (((1U << CCI_AUPLL_EN_DIV2_LEN) - 1) << CCI_AUPLL_EN_DIV2_POS)
+#define CCI_AUPLL_EN_DIV2_UMSK (~(((1U << CCI_AUPLL_EN_DIV2_LEN) - 1) << CCI_AUPLL_EN_DIV2_POS))
+#define CCI_AUPLL_EN_DIV2P5 CCI_AUPLL_EN_DIV2P5
+#define CCI_AUPLL_EN_DIV2P5_POS (2U)
+#define CCI_AUPLL_EN_DIV2P5_LEN (1U)
+#define CCI_AUPLL_EN_DIV2P5_MSK (((1U << CCI_AUPLL_EN_DIV2P5_LEN) - 1) << CCI_AUPLL_EN_DIV2P5_POS)
+#define CCI_AUPLL_EN_DIV2P5_UMSK (~(((1U << CCI_AUPLL_EN_DIV2P5_LEN) - 1) << CCI_AUPLL_EN_DIV2P5_POS))
+#define CCI_AUPLL_EN_DIV3 CCI_AUPLL_EN_DIV3
+#define CCI_AUPLL_EN_DIV3_POS (3U)
+#define CCI_AUPLL_EN_DIV3_LEN (1U)
+#define CCI_AUPLL_EN_DIV3_MSK (((1U << CCI_AUPLL_EN_DIV3_LEN) - 1) << CCI_AUPLL_EN_DIV3_POS)
+#define CCI_AUPLL_EN_DIV3_UMSK (~(((1U << CCI_AUPLL_EN_DIV3_LEN) - 1) << CCI_AUPLL_EN_DIV3_POS))
+#define CCI_AUPLL_EN_DIV4 CCI_AUPLL_EN_DIV4
+#define CCI_AUPLL_EN_DIV4_POS (4U)
+#define CCI_AUPLL_EN_DIV4_LEN (1U)
+#define CCI_AUPLL_EN_DIV4_MSK (((1U << CCI_AUPLL_EN_DIV4_LEN) - 1) << CCI_AUPLL_EN_DIV4_POS)
+#define CCI_AUPLL_EN_DIV4_UMSK (~(((1U << CCI_AUPLL_EN_DIV4_LEN) - 1) << CCI_AUPLL_EN_DIV4_POS))
+#define CCI_AUPLL_EN_DIV5 CCI_AUPLL_EN_DIV5
+#define CCI_AUPLL_EN_DIV5_POS (5U)
+#define CCI_AUPLL_EN_DIV5_LEN (1U)
+#define CCI_AUPLL_EN_DIV5_MSK (((1U << CCI_AUPLL_EN_DIV5_LEN) - 1) << CCI_AUPLL_EN_DIV5_POS)
+#define CCI_AUPLL_EN_DIV5_UMSK (~(((1U << CCI_AUPLL_EN_DIV5_LEN) - 1) << CCI_AUPLL_EN_DIV5_POS))
+#define CCI_AUPLL_EN_DIV6 CCI_AUPLL_EN_DIV6
+#define CCI_AUPLL_EN_DIV6_POS (6U)
+#define CCI_AUPLL_EN_DIV6_LEN (1U)
+#define CCI_AUPLL_EN_DIV6_MSK (((1U << CCI_AUPLL_EN_DIV6_LEN) - 1) << CCI_AUPLL_EN_DIV6_POS)
+#define CCI_AUPLL_EN_DIV6_UMSK (~(((1U << CCI_AUPLL_EN_DIV6_LEN) - 1) << CCI_AUPLL_EN_DIV6_POS))
+#define CCI_AUPLL_EN_DIV10 CCI_AUPLL_EN_DIV10
+#define CCI_AUPLL_EN_DIV10_POS (7U)
+#define CCI_AUPLL_EN_DIV10_LEN (1U)
+#define CCI_AUPLL_EN_DIV10_MSK (((1U << CCI_AUPLL_EN_DIV10_LEN) - 1) << CCI_AUPLL_EN_DIV10_POS)
+#define CCI_AUPLL_EN_DIV10_UMSK (~(((1U << CCI_AUPLL_EN_DIV10_LEN) - 1) << CCI_AUPLL_EN_DIV10_POS))
+#define CCI_AUPLL_EN_DIV15 CCI_AUPLL_EN_DIV15
+#define CCI_AUPLL_EN_DIV15_POS (8U)
+#define CCI_AUPLL_EN_DIV15_LEN (1U)
+#define CCI_AUPLL_EN_DIV15_MSK (((1U << CCI_AUPLL_EN_DIV15_LEN) - 1) << CCI_AUPLL_EN_DIV15_POS)
+#define CCI_AUPLL_EN_DIV15_UMSK (~(((1U << CCI_AUPLL_EN_DIV15_LEN) - 1) << CCI_AUPLL_EN_DIV15_POS))
+#define CCI_AUPLL_SEL_DIV1_DIV2 CCI_AUPLL_SEL_DIV1_DIV2
+#define CCI_AUPLL_SEL_DIV1_DIV2_POS (9U)
+#define CCI_AUPLL_SEL_DIV1_DIV2_LEN (1U)
+#define CCI_AUPLL_SEL_DIV1_DIV2_MSK (((1U << CCI_AUPLL_SEL_DIV1_DIV2_LEN) - 1) << CCI_AUPLL_SEL_DIV1_DIV2_POS)
+#define CCI_AUPLL_SEL_DIV1_DIV2_UMSK (~(((1U << CCI_AUPLL_SEL_DIV1_DIV2_LEN) - 1) << CCI_AUPLL_SEL_DIV1_DIV2_POS))
+
+/* 0x774 : audio_pll_cfg9 */
+#define CCI_AUDIO_PLL_CFG9_OFFSET (0x774)
+#define CCI_AUPLL_DC_TP_OUT_EN CCI_AUPLL_DC_TP_OUT_EN
+#define CCI_AUPLL_DC_TP_OUT_EN_POS (0U)
+#define CCI_AUPLL_DC_TP_OUT_EN_LEN (1U)
+#define CCI_AUPLL_DC_TP_OUT_EN_MSK (((1U << CCI_AUPLL_DC_TP_OUT_EN_LEN) - 1) << CCI_AUPLL_DC_TP_OUT_EN_POS)
+#define CCI_AUPLL_DC_TP_OUT_EN_UMSK (~(((1U << CCI_AUPLL_DC_TP_OUT_EN_LEN) - 1) << CCI_AUPLL_DC_TP_OUT_EN_POS))
+#define CCI_TEN_AUPLL CCI_TEN_AUPLL
+#define CCI_TEN_AUPLL_POS (1U)
+#define CCI_TEN_AUPLL_LEN (1U)
+#define CCI_TEN_AUPLL_MSK (((1U << CCI_TEN_AUPLL_LEN) - 1) << CCI_TEN_AUPLL_POS)
+#define CCI_TEN_AUPLL_UMSK (~(((1U << CCI_TEN_AUPLL_LEN) - 1) << CCI_TEN_AUPLL_POS))
+#define CCI_TEN_AUPLL_SFREG CCI_TEN_AUPLL_SFREG
+#define CCI_TEN_AUPLL_SFREG_POS (2U)
+#define CCI_TEN_AUPLL_SFREG_LEN (1U)
+#define CCI_TEN_AUPLL_SFREG_MSK (((1U << CCI_TEN_AUPLL_SFREG_LEN) - 1) << CCI_TEN_AUPLL_SFREG_POS)
+#define CCI_TEN_AUPLL_SFREG_UMSK (~(((1U << CCI_TEN_AUPLL_SFREG_LEN) - 1) << CCI_TEN_AUPLL_SFREG_POS))
+#define CCI_DTEN_AUPLL_FIN CCI_DTEN_AUPLL_FIN
+#define CCI_DTEN_AUPLL_FIN_POS (4U)
+#define CCI_DTEN_AUPLL_FIN_LEN (1U)
+#define CCI_DTEN_AUPLL_FIN_MSK (((1U << CCI_DTEN_AUPLL_FIN_LEN) - 1) << CCI_DTEN_AUPLL_FIN_POS)
+#define CCI_DTEN_AUPLL_FIN_UMSK (~(((1U << CCI_DTEN_AUPLL_FIN_LEN) - 1) << CCI_DTEN_AUPLL_FIN_POS))
+#define CCI_DTEN_AUPLL_FREF CCI_DTEN_AUPLL_FREF
+#define CCI_DTEN_AUPLL_FREF_POS (5U)
+#define CCI_DTEN_AUPLL_FREF_LEN (1U)
+#define CCI_DTEN_AUPLL_FREF_MSK (((1U << CCI_DTEN_AUPLL_FREF_LEN) - 1) << CCI_DTEN_AUPLL_FREF_POS)
+#define CCI_DTEN_AUPLL_FREF_UMSK (~(((1U << CCI_DTEN_AUPLL_FREF_LEN) - 1) << CCI_DTEN_AUPLL_FREF_POS))
+#define CCI_DTEN_AUPLL_FSDM CCI_DTEN_AUPLL_FSDM
+#define CCI_DTEN_AUPLL_FSDM_POS (6U)
+#define CCI_DTEN_AUPLL_FSDM_LEN (1U)
+#define CCI_DTEN_AUPLL_FSDM_MSK (((1U << CCI_DTEN_AUPLL_FSDM_LEN) - 1) << CCI_DTEN_AUPLL_FSDM_POS)
+#define CCI_DTEN_AUPLL_FSDM_UMSK (~(((1U << CCI_DTEN_AUPLL_FSDM_LEN) - 1) << CCI_DTEN_AUPLL_FSDM_POS))
+#define CCI_DTEN_AUPLL_DIV15 CCI_DTEN_AUPLL_DIV15
+#define CCI_DTEN_AUPLL_DIV15_POS (7U)
+#define CCI_DTEN_AUPLL_DIV15_LEN (1U)
+#define CCI_DTEN_AUPLL_DIV15_MSK (((1U << CCI_DTEN_AUPLL_DIV15_LEN) - 1) << CCI_DTEN_AUPLL_DIV15_POS)
+#define CCI_DTEN_AUPLL_DIV15_UMSK (~(((1U << CCI_DTEN_AUPLL_DIV15_LEN) - 1) << CCI_DTEN_AUPLL_DIV15_POS))
+#define CCI_DTEN_AUPLL_DIV5 CCI_DTEN_AUPLL_DIV5
+#define CCI_DTEN_AUPLL_DIV5_POS (8U)
+#define CCI_DTEN_AUPLL_DIV5_LEN (1U)
+#define CCI_DTEN_AUPLL_DIV5_MSK (((1U << CCI_DTEN_AUPLL_DIV5_LEN) - 1) << CCI_DTEN_AUPLL_DIV5_POS)
+#define CCI_DTEN_AUPLL_DIV5_UMSK (~(((1U << CCI_DTEN_AUPLL_DIV5_LEN) - 1) << CCI_DTEN_AUPLL_DIV5_POS))
+#define CCI_DTEN_AUPLL_POSTDIV_CLK CCI_DTEN_AUPLL_POSTDIV_CLK
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_POS (9U)
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_LEN (1U)
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_MSK (((1U << CCI_DTEN_AUPLL_POSTDIV_CLK_LEN) - 1) << CCI_DTEN_AUPLL_POSTDIV_CLK_POS)
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_UMSK (~(((1U << CCI_DTEN_AUPLL_POSTDIV_CLK_LEN) - 1) << CCI_DTEN_AUPLL_POSTDIV_CLK_POS))
+#define CCI_DTEST_AUPLL_PULLDOWN CCI_DTEST_AUPLL_PULLDOWN
+#define CCI_DTEST_AUPLL_PULLDOWN_POS (10U)
+#define CCI_DTEST_AUPLL_PULLDOWN_LEN (1U)
+#define CCI_DTEST_AUPLL_PULLDOWN_MSK (((1U << CCI_DTEST_AUPLL_PULLDOWN_LEN) - 1) << CCI_DTEST_AUPLL_PULLDOWN_POS)
+#define CCI_DTEST_AUPLL_PULLDOWN_UMSK (~(((1U << CCI_DTEST_AUPLL_PULLDOWN_LEN) - 1) << CCI_DTEST_AUPLL_PULLDOWN_POS))
+
+/* 0x778 : audio_pll_cfg10 */
+#define CCI_AUDIO_PLL_CFG10_OFFSET (0x778)
+#define CCI_AUPLL_SSC_EN CCI_AUPLL_SSC_EN
+#define CCI_AUPLL_SSC_EN_POS (0U)
+#define CCI_AUPLL_SSC_EN_LEN (1U)
+#define CCI_AUPLL_SSC_EN_MSK (((1U << CCI_AUPLL_SSC_EN_LEN) - 1) << CCI_AUPLL_SSC_EN_POS)
+#define CCI_AUPLL_SSC_EN_UMSK (~(((1U << CCI_AUPLL_SSC_EN_LEN) - 1) << CCI_AUPLL_SSC_EN_POS))
+#define CCI_AUPLL_SSC_CNT CCI_AUPLL_SSC_CNT
+#define CCI_AUPLL_SSC_CNT_POS (4U)
+#define CCI_AUPLL_SSC_CNT_LEN (8U)
+#define CCI_AUPLL_SSC_CNT_MSK (((1U << CCI_AUPLL_SSC_CNT_LEN) - 1) << CCI_AUPLL_SSC_CNT_POS)
+#define CCI_AUPLL_SSC_CNT_UMSK (~(((1U << CCI_AUPLL_SSC_CNT_LEN) - 1) << CCI_AUPLL_SSC_CNT_POS))
+#define CCI_AUPLL_SSC_GAIN CCI_AUPLL_SSC_GAIN
+#define CCI_AUPLL_SSC_GAIN_POS (12U)
+#define CCI_AUPLL_SSC_GAIN_LEN (3U)
+#define CCI_AUPLL_SSC_GAIN_MSK (((1U << CCI_AUPLL_SSC_GAIN_LEN) - 1) << CCI_AUPLL_SSC_GAIN_POS)
+#define CCI_AUPLL_SSC_GAIN_UMSK (~(((1U << CCI_AUPLL_SSC_GAIN_LEN) - 1) << CCI_AUPLL_SSC_GAIN_POS))
+#define CCI_AUPLL_SSC_START_GATE_EN CCI_AUPLL_SSC_START_GATE_EN
+#define CCI_AUPLL_SSC_START_GATE_EN_POS (16U)
+#define CCI_AUPLL_SSC_START_GATE_EN_LEN (1U)
+#define CCI_AUPLL_SSC_START_GATE_EN_MSK (((1U << CCI_AUPLL_SSC_START_GATE_EN_LEN) - 1) << CCI_AUPLL_SSC_START_GATE_EN_POS)
+#define CCI_AUPLL_SSC_START_GATE_EN_UMSK (~(((1U << CCI_AUPLL_SSC_START_GATE_EN_LEN) - 1) << CCI_AUPLL_SSC_START_GATE_EN_POS))
+#define CCI_AUPLL_SSC_START CCI_AUPLL_SSC_START
+#define CCI_AUPLL_SSC_START_POS (20U)
+#define CCI_AUPLL_SSC_START_LEN (1U)
+#define CCI_AUPLL_SSC_START_MSK (((1U << CCI_AUPLL_SSC_START_LEN) - 1) << CCI_AUPLL_SSC_START_POS)
+#define CCI_AUPLL_SSC_START_UMSK (~(((1U << CCI_AUPLL_SSC_START_LEN) - 1) << CCI_AUPLL_SSC_START_POS))
+
+/* 0x77C : audio_pll_cfg11 */
+#define CCI_AUDIO_PLL_CFG11_OFFSET (0x77C)
+#define CCI_AUPLL_RESV CCI_AUPLL_RESV
+#define CCI_AUPLL_RESV_POS (0U)
+#define CCI_AUPLL_RESV_LEN (16U)
+#define CCI_AUPLL_RESV_MSK (((1U << CCI_AUPLL_RESV_LEN) - 1) << CCI_AUPLL_RESV_POS)
+#define CCI_AUPLL_RESV_UMSK (~(((1U << CCI_AUPLL_RESV_LEN) - 1) << CCI_AUPLL_RESV_POS))
+#define CCI_AUPLL_DL_CTRL_15 CCI_AUPLL_DL_CTRL_15
+#define CCI_AUPLL_DL_CTRL_15_POS (23U)
+#define CCI_AUPLL_DL_CTRL_15_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_15_MSK (((1U << CCI_AUPLL_DL_CTRL_15_LEN) - 1) << CCI_AUPLL_DL_CTRL_15_POS)
+#define CCI_AUPLL_DL_CTRL_15_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_15_LEN) - 1) << CCI_AUPLL_DL_CTRL_15_POS))
+#define CCI_AUPLL_DL_CTRL_10 CCI_AUPLL_DL_CTRL_10
+#define CCI_AUPLL_DL_CTRL_10_POS (24U)
+#define CCI_AUPLL_DL_CTRL_10_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_10_MSK (((1U << CCI_AUPLL_DL_CTRL_10_LEN) - 1) << CCI_AUPLL_DL_CTRL_10_POS)
+#define CCI_AUPLL_DL_CTRL_10_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_10_LEN) - 1) << CCI_AUPLL_DL_CTRL_10_POS))
+#define CCI_AUPLL_DL_CTRL_6 CCI_AUPLL_DL_CTRL_6
+#define CCI_AUPLL_DL_CTRL_6_POS (25U)
+#define CCI_AUPLL_DL_CTRL_6_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_6_MSK (((1U << CCI_AUPLL_DL_CTRL_6_LEN) - 1) << CCI_AUPLL_DL_CTRL_6_POS)
+#define CCI_AUPLL_DL_CTRL_6_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_6_LEN) - 1) << CCI_AUPLL_DL_CTRL_6_POS))
+#define CCI_AUPLL_DL_CTRL_5 CCI_AUPLL_DL_CTRL_5
+#define CCI_AUPLL_DL_CTRL_5_POS (26U)
+#define CCI_AUPLL_DL_CTRL_5_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_5_MSK (((1U << CCI_AUPLL_DL_CTRL_5_LEN) - 1) << CCI_AUPLL_DL_CTRL_5_POS)
+#define CCI_AUPLL_DL_CTRL_5_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_5_LEN) - 1) << CCI_AUPLL_DL_CTRL_5_POS))
+#define CCI_AUPLL_DL_CTRL_4 CCI_AUPLL_DL_CTRL_4
+#define CCI_AUPLL_DL_CTRL_4_POS (27U)
+#define CCI_AUPLL_DL_CTRL_4_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_4_MSK (((1U << CCI_AUPLL_DL_CTRL_4_LEN) - 1) << CCI_AUPLL_DL_CTRL_4_POS)
+#define CCI_AUPLL_DL_CTRL_4_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_4_LEN) - 1) << CCI_AUPLL_DL_CTRL_4_POS))
+#define CCI_AUPLL_DL_CTRL_3 CCI_AUPLL_DL_CTRL_3
+#define CCI_AUPLL_DL_CTRL_3_POS (28U)
+#define CCI_AUPLL_DL_CTRL_3_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_3_MSK (((1U << CCI_AUPLL_DL_CTRL_3_LEN) - 1) << CCI_AUPLL_DL_CTRL_3_POS)
+#define CCI_AUPLL_DL_CTRL_3_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_3_LEN) - 1) << CCI_AUPLL_DL_CTRL_3_POS))
+#define CCI_AUPLL_DL_CTRL_2P5 CCI_AUPLL_DL_CTRL_2P5
+#define CCI_AUPLL_DL_CTRL_2P5_POS (29U)
+#define CCI_AUPLL_DL_CTRL_2P5_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_2P5_MSK (((1U << CCI_AUPLL_DL_CTRL_2P5_LEN) - 1) << CCI_AUPLL_DL_CTRL_2P5_POS)
+#define CCI_AUPLL_DL_CTRL_2P5_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_2P5_LEN) - 1) << CCI_AUPLL_DL_CTRL_2P5_POS))
+#define CCI_AUPLL_DL_CTRL_2 CCI_AUPLL_DL_CTRL_2
+#define CCI_AUPLL_DL_CTRL_2_POS (30U)
+#define CCI_AUPLL_DL_CTRL_2_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_2_MSK (((1U << CCI_AUPLL_DL_CTRL_2_LEN) - 1) << CCI_AUPLL_DL_CTRL_2_POS)
+#define CCI_AUPLL_DL_CTRL_2_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_2_LEN) - 1) << CCI_AUPLL_DL_CTRL_2_POS))
+#define CCI_AUPLL_DL_CTRL_1 CCI_AUPLL_DL_CTRL_1
+#define CCI_AUPLL_DL_CTRL_1_POS (31U)
+#define CCI_AUPLL_DL_CTRL_1_LEN (1U)
+#define CCI_AUPLL_DL_CTRL_1_MSK (((1U << CCI_AUPLL_DL_CTRL_1_LEN) - 1) << CCI_AUPLL_DL_CTRL_1_POS)
+#define CCI_AUPLL_DL_CTRL_1_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_1_LEN) - 1) << CCI_AUPLL_DL_CTRL_1_POS))
+
+/* 0x7D0 : cpu_pll_cfg0 */
+#define CCI_CPU_PLL_CFG0_OFFSET (0x7D0)
+#define CCI_CPUPLL_SDM_RSTB CCI_CPUPLL_SDM_RSTB
+#define CCI_CPUPLL_SDM_RSTB_POS (0U)
+#define CCI_CPUPLL_SDM_RSTB_LEN (1U)
+#define CCI_CPUPLL_SDM_RSTB_MSK (((1U << CCI_CPUPLL_SDM_RSTB_LEN) - 1) << CCI_CPUPLL_SDM_RSTB_POS)
+#define CCI_CPUPLL_SDM_RSTB_UMSK (~(((1U << CCI_CPUPLL_SDM_RSTB_LEN) - 1) << CCI_CPUPLL_SDM_RSTB_POS))
+#define CCI_CPUPLL_POSTDIV_RSTB CCI_CPUPLL_POSTDIV_RSTB
+#define CCI_CPUPLL_POSTDIV_RSTB_POS (1U)
+#define CCI_CPUPLL_POSTDIV_RSTB_LEN (1U)
+#define CCI_CPUPLL_POSTDIV_RSTB_MSK (((1U << CCI_CPUPLL_POSTDIV_RSTB_LEN) - 1) << CCI_CPUPLL_POSTDIV_RSTB_POS)
+#define CCI_CPUPLL_POSTDIV_RSTB_UMSK (~(((1U << CCI_CPUPLL_POSTDIV_RSTB_LEN) - 1) << CCI_CPUPLL_POSTDIV_RSTB_POS))
+#define CCI_CPUPLL_FBDV_RSTB CCI_CPUPLL_FBDV_RSTB
+#define CCI_CPUPLL_FBDV_RSTB_POS (2U)
+#define CCI_CPUPLL_FBDV_RSTB_LEN (1U)
+#define CCI_CPUPLL_FBDV_RSTB_MSK (((1U << CCI_CPUPLL_FBDV_RSTB_LEN) - 1) << CCI_CPUPLL_FBDV_RSTB_POS)
+#define CCI_CPUPLL_FBDV_RSTB_UMSK (~(((1U << CCI_CPUPLL_FBDV_RSTB_LEN) - 1) << CCI_CPUPLL_FBDV_RSTB_POS))
+#define CCI_CPUPLL_REFDIV_RSTB CCI_CPUPLL_REFDIV_RSTB
+#define CCI_CPUPLL_REFDIV_RSTB_POS (3U)
+#define CCI_CPUPLL_REFDIV_RSTB_LEN (1U)
+#define CCI_CPUPLL_REFDIV_RSTB_MSK (((1U << CCI_CPUPLL_REFDIV_RSTB_LEN) - 1) << CCI_CPUPLL_REFDIV_RSTB_POS)
+#define CCI_CPUPLL_REFDIV_RSTB_UMSK (~(((1U << CCI_CPUPLL_REFDIV_RSTB_LEN) - 1) << CCI_CPUPLL_REFDIV_RSTB_POS))
+#define CCI_PU_CPUPLL_POSTDIV CCI_PU_CPUPLL_POSTDIV
+#define CCI_PU_CPUPLL_POSTDIV_POS (4U)
+#define CCI_PU_CPUPLL_POSTDIV_LEN (1U)
+#define CCI_PU_CPUPLL_POSTDIV_MSK (((1U << CCI_PU_CPUPLL_POSTDIV_LEN) - 1) << CCI_PU_CPUPLL_POSTDIV_POS)
+#define CCI_PU_CPUPLL_POSTDIV_UMSK (~(((1U << CCI_PU_CPUPLL_POSTDIV_LEN) - 1) << CCI_PU_CPUPLL_POSTDIV_POS))
+#define CCI_PU_CPUPLL_FBDV CCI_PU_CPUPLL_FBDV
+#define CCI_PU_CPUPLL_FBDV_POS (5U)
+#define CCI_PU_CPUPLL_FBDV_LEN (1U)
+#define CCI_PU_CPUPLL_FBDV_MSK (((1U << CCI_PU_CPUPLL_FBDV_LEN) - 1) << CCI_PU_CPUPLL_FBDV_POS)
+#define CCI_PU_CPUPLL_FBDV_UMSK (~(((1U << CCI_PU_CPUPLL_FBDV_LEN) - 1) << CCI_PU_CPUPLL_FBDV_POS))
+#define CCI_PU_CPUPLL_CLAMP_OP CCI_PU_CPUPLL_CLAMP_OP
+#define CCI_PU_CPUPLL_CLAMP_OP_POS (6U)
+#define CCI_PU_CPUPLL_CLAMP_OP_LEN (1U)
+#define CCI_PU_CPUPLL_CLAMP_OP_MSK (((1U << CCI_PU_CPUPLL_CLAMP_OP_LEN) - 1) << CCI_PU_CPUPLL_CLAMP_OP_POS)
+#define CCI_PU_CPUPLL_CLAMP_OP_UMSK (~(((1U << CCI_PU_CPUPLL_CLAMP_OP_LEN) - 1) << CCI_PU_CPUPLL_CLAMP_OP_POS))
+#define CCI_PU_CPUPLL_PFD CCI_PU_CPUPLL_PFD
+#define CCI_PU_CPUPLL_PFD_POS (7U)
+#define CCI_PU_CPUPLL_PFD_LEN (1U)
+#define CCI_PU_CPUPLL_PFD_MSK (((1U << CCI_PU_CPUPLL_PFD_LEN) - 1) << CCI_PU_CPUPLL_PFD_POS)
+#define CCI_PU_CPUPLL_PFD_UMSK (~(((1U << CCI_PU_CPUPLL_PFD_LEN) - 1) << CCI_PU_CPUPLL_PFD_POS))
+#define CCI_PU_CPUPLL_CP CCI_PU_CPUPLL_CP
+#define CCI_PU_CPUPLL_CP_POS (8U)
+#define CCI_PU_CPUPLL_CP_LEN (1U)
+#define CCI_PU_CPUPLL_CP_MSK (((1U << CCI_PU_CPUPLL_CP_LEN) - 1) << CCI_PU_CPUPLL_CP_POS)
+#define CCI_PU_CPUPLL_CP_UMSK (~(((1U << CCI_PU_CPUPLL_CP_LEN) - 1) << CCI_PU_CPUPLL_CP_POS))
+#define CCI_PU_CPUPLL_SFREG CCI_PU_CPUPLL_SFREG
+#define CCI_PU_CPUPLL_SFREG_POS (9U)
+#define CCI_PU_CPUPLL_SFREG_LEN (1U)
+#define CCI_PU_CPUPLL_SFREG_MSK (((1U << CCI_PU_CPUPLL_SFREG_LEN) - 1) << CCI_PU_CPUPLL_SFREG_POS)
+#define CCI_PU_CPUPLL_SFREG_UMSK (~(((1U << CCI_PU_CPUPLL_SFREG_LEN) - 1) << CCI_PU_CPUPLL_SFREG_POS))
+#define CCI_PU_CPUPLL CCI_PU_CPUPLL
+#define CCI_PU_CPUPLL_POS (10U)
+#define CCI_PU_CPUPLL_LEN (1U)
+#define CCI_PU_CPUPLL_MSK (((1U << CCI_PU_CPUPLL_LEN) - 1) << CCI_PU_CPUPLL_POS)
+#define CCI_PU_CPUPLL_UMSK (~(((1U << CCI_PU_CPUPLL_LEN) - 1) << CCI_PU_CPUPLL_POS))
+#define CCI_PU_CPUPLL_CLKTREE CCI_PU_CPUPLL_CLKTREE
+#define CCI_PU_CPUPLL_CLKTREE_POS (11U)
+#define CCI_PU_CPUPLL_CLKTREE_LEN (1U)
+#define CCI_PU_CPUPLL_CLKTREE_MSK (((1U << CCI_PU_CPUPLL_CLKTREE_LEN) - 1) << CCI_PU_CPUPLL_CLKTREE_POS)
+#define CCI_PU_CPUPLL_CLKTREE_UMSK (~(((1U << CCI_PU_CPUPLL_CLKTREE_LEN) - 1) << CCI_PU_CPUPLL_CLKTREE_POS))
+
+/* 0x7D4 : cpu_pll_cfg1 */
+#define CCI_CPU_PLL_CFG1_OFFSET (0x7D4)
+#define CCI_CPUPLL_POSTDIV CCI_CPUPLL_POSTDIV
+#define CCI_CPUPLL_POSTDIV_POS (0U)
+#define CCI_CPUPLL_POSTDIV_LEN (7U)
+#define CCI_CPUPLL_POSTDIV_MSK (((1U << CCI_CPUPLL_POSTDIV_LEN) - 1) << CCI_CPUPLL_POSTDIV_POS)
+#define CCI_CPUPLL_POSTDIV_UMSK (~(((1U << CCI_CPUPLL_POSTDIV_LEN) - 1) << CCI_CPUPLL_POSTDIV_POS))
+#define CCI_CPUPLL_REFDIV_RATIO CCI_CPUPLL_REFDIV_RATIO
+#define CCI_CPUPLL_REFDIV_RATIO_POS (8U)
+#define CCI_CPUPLL_REFDIV_RATIO_LEN (4U)
+#define CCI_CPUPLL_REFDIV_RATIO_MSK (((1U << CCI_CPUPLL_REFDIV_RATIO_LEN) - 1) << CCI_CPUPLL_REFDIV_RATIO_POS)
+#define CCI_CPUPLL_REFDIV_RATIO_UMSK (~(((1U << CCI_CPUPLL_REFDIV_RATIO_LEN) - 1) << CCI_CPUPLL_REFDIV_RATIO_POS))
+#define CCI_CPUPLL_REFCLK_SEL CCI_CPUPLL_REFCLK_SEL
+#define CCI_CPUPLL_REFCLK_SEL_POS (16U)
+#define CCI_CPUPLL_REFCLK_SEL_LEN (2U)
+#define CCI_CPUPLL_REFCLK_SEL_MSK (((1U << CCI_CPUPLL_REFCLK_SEL_LEN) - 1) << CCI_CPUPLL_REFCLK_SEL_POS)
+#define CCI_CPUPLL_REFCLK_SEL_UMSK (~(((1U << CCI_CPUPLL_REFCLK_SEL_LEN) - 1) << CCI_CPUPLL_REFCLK_SEL_POS))
+#define CCI_CPUPLL_VG11_SEL CCI_CPUPLL_VG11_SEL
+#define CCI_CPUPLL_VG11_SEL_POS (20U)
+#define CCI_CPUPLL_VG11_SEL_LEN (2U)
+#define CCI_CPUPLL_VG11_SEL_MSK (((1U << CCI_CPUPLL_VG11_SEL_LEN) - 1) << CCI_CPUPLL_VG11_SEL_POS)
+#define CCI_CPUPLL_VG11_SEL_UMSK (~(((1U << CCI_CPUPLL_VG11_SEL_LEN) - 1) << CCI_CPUPLL_VG11_SEL_POS))
+#define CCI_CPUPLL_VG13_SEL CCI_CPUPLL_VG13_SEL
+#define CCI_CPUPLL_VG13_SEL_POS (24U)
+#define CCI_CPUPLL_VG13_SEL_LEN (2U)
+#define CCI_CPUPLL_VG13_SEL_MSK (((1U << CCI_CPUPLL_VG13_SEL_LEN) - 1) << CCI_CPUPLL_VG13_SEL_POS)
+#define CCI_CPUPLL_VG13_SEL_UMSK (~(((1U << CCI_CPUPLL_VG13_SEL_LEN) - 1) << CCI_CPUPLL_VG13_SEL_POS))
+
+/* 0x7D8 : cpu_pll_cfg2 */
+#define CCI_CPU_PLL_CFG2_OFFSET (0x7D8)
+#define CCI_CPUPLL_SEL_CP_BIAS CCI_CPUPLL_SEL_CP_BIAS
+#define CCI_CPUPLL_SEL_CP_BIAS_POS (0U)
+#define CCI_CPUPLL_SEL_CP_BIAS_LEN (1U)
+#define CCI_CPUPLL_SEL_CP_BIAS_MSK (((1U << CCI_CPUPLL_SEL_CP_BIAS_LEN) - 1) << CCI_CPUPLL_SEL_CP_BIAS_POS)
+#define CCI_CPUPLL_SEL_CP_BIAS_UMSK (~(((1U << CCI_CPUPLL_SEL_CP_BIAS_LEN) - 1) << CCI_CPUPLL_SEL_CP_BIAS_POS))
+#define CCI_CPUPLL_ICP_5U CCI_CPUPLL_ICP_5U
+#define CCI_CPUPLL_ICP_5U_POS (4U)
+#define CCI_CPUPLL_ICP_5U_LEN (2U)
+#define CCI_CPUPLL_ICP_5U_MSK (((1U << CCI_CPUPLL_ICP_5U_LEN) - 1) << CCI_CPUPLL_ICP_5U_POS)
+#define CCI_CPUPLL_ICP_5U_UMSK (~(((1U << CCI_CPUPLL_ICP_5U_LEN) - 1) << CCI_CPUPLL_ICP_5U_POS))
+#define CCI_CPUPLL_ICP_1U CCI_CPUPLL_ICP_1U
+#define CCI_CPUPLL_ICP_1U_POS (6U)
+#define CCI_CPUPLL_ICP_1U_LEN (2U)
+#define CCI_CPUPLL_ICP_1U_MSK (((1U << CCI_CPUPLL_ICP_1U_LEN) - 1) << CCI_CPUPLL_ICP_1U_POS)
+#define CCI_CPUPLL_ICP_1U_UMSK (~(((1U << CCI_CPUPLL_ICP_1U_LEN) - 1) << CCI_CPUPLL_ICP_1U_POS))
+#define CCI_CPUPLL_INT_FRAC_SW CCI_CPUPLL_INT_FRAC_SW
+#define CCI_CPUPLL_INT_FRAC_SW_POS (8U)
+#define CCI_CPUPLL_INT_FRAC_SW_LEN (1U)
+#define CCI_CPUPLL_INT_FRAC_SW_MSK (((1U << CCI_CPUPLL_INT_FRAC_SW_LEN) - 1) << CCI_CPUPLL_INT_FRAC_SW_POS)
+#define CCI_CPUPLL_INT_FRAC_SW_UMSK (~(((1U << CCI_CPUPLL_INT_FRAC_SW_LEN) - 1) << CCI_CPUPLL_INT_FRAC_SW_POS))
+#define CCI_CPUPLL_CP_STARTUP_EN CCI_CPUPLL_CP_STARTUP_EN
+#define CCI_CPUPLL_CP_STARTUP_EN_POS (9U)
+#define CCI_CPUPLL_CP_STARTUP_EN_LEN (1U)
+#define CCI_CPUPLL_CP_STARTUP_EN_MSK (((1U << CCI_CPUPLL_CP_STARTUP_EN_LEN) - 1) << CCI_CPUPLL_CP_STARTUP_EN_POS)
+#define CCI_CPUPLL_CP_STARTUP_EN_UMSK (~(((1U << CCI_CPUPLL_CP_STARTUP_EN_LEN) - 1) << CCI_CPUPLL_CP_STARTUP_EN_POS))
+#define CCI_CPUPLL_CP_OPAMP_EN CCI_CPUPLL_CP_OPAMP_EN
+#define CCI_CPUPLL_CP_OPAMP_EN_POS (10U)
+#define CCI_CPUPLL_CP_OPAMP_EN_LEN (1U)
+#define CCI_CPUPLL_CP_OPAMP_EN_MSK (((1U << CCI_CPUPLL_CP_OPAMP_EN_LEN) - 1) << CCI_CPUPLL_CP_OPAMP_EN_POS)
+#define CCI_CPUPLL_CP_OPAMP_EN_UMSK (~(((1U << CCI_CPUPLL_CP_OPAMP_EN_LEN) - 1) << CCI_CPUPLL_CP_OPAMP_EN_POS))
+
+/* 0x7DC : cpu_pll_cfg3 */
+#define CCI_CPU_PLL_CFG3_OFFSET (0x7DC)
+#define CCI_CPUPLL_C4_EN CCI_CPUPLL_C4_EN
+#define CCI_CPUPLL_C4_EN_POS (0U)
+#define CCI_CPUPLL_C4_EN_LEN (1U)
+#define CCI_CPUPLL_C4_EN_MSK (((1U << CCI_CPUPLL_C4_EN_LEN) - 1) << CCI_CPUPLL_C4_EN_POS)
+#define CCI_CPUPLL_C4_EN_UMSK (~(((1U << CCI_CPUPLL_C4_EN_LEN) - 1) << CCI_CPUPLL_C4_EN_POS))
+#define CCI_CPUPLL_R4 CCI_CPUPLL_R4
+#define CCI_CPUPLL_R4_POS (4U)
+#define CCI_CPUPLL_R4_LEN (2U)
+#define CCI_CPUPLL_R4_MSK (((1U << CCI_CPUPLL_R4_LEN) - 1) << CCI_CPUPLL_R4_POS)
+#define CCI_CPUPLL_R4_UMSK (~(((1U << CCI_CPUPLL_R4_LEN) - 1) << CCI_CPUPLL_R4_POS))
+#define CCI_CPUPLL_R4_SHORT CCI_CPUPLL_R4_SHORT
+#define CCI_CPUPLL_R4_SHORT_POS (8U)
+#define CCI_CPUPLL_R4_SHORT_LEN (1U)
+#define CCI_CPUPLL_R4_SHORT_MSK (((1U << CCI_CPUPLL_R4_SHORT_LEN) - 1) << CCI_CPUPLL_R4_SHORT_POS)
+#define CCI_CPUPLL_R4_SHORT_UMSK (~(((1U << CCI_CPUPLL_R4_SHORT_LEN) - 1) << CCI_CPUPLL_R4_SHORT_POS))
+#define CCI_CPUPLL_C3 CCI_CPUPLL_C3
+#define CCI_CPUPLL_C3_POS (12U)
+#define CCI_CPUPLL_C3_LEN (2U)
+#define CCI_CPUPLL_C3_MSK (((1U << CCI_CPUPLL_C3_LEN) - 1) << CCI_CPUPLL_C3_POS)
+#define CCI_CPUPLL_C3_UMSK (~(((1U << CCI_CPUPLL_C3_LEN) - 1) << CCI_CPUPLL_C3_POS))
+#define CCI_CPUPLL_CZ CCI_CPUPLL_CZ
+#define CCI_CPUPLL_CZ_POS (14U)
+#define CCI_CPUPLL_CZ_LEN (2U)
+#define CCI_CPUPLL_CZ_MSK (((1U << CCI_CPUPLL_CZ_LEN) - 1) << CCI_CPUPLL_CZ_POS)
+#define CCI_CPUPLL_CZ_UMSK (~(((1U << CCI_CPUPLL_CZ_LEN) - 1) << CCI_CPUPLL_CZ_POS))
+#define CCI_CPUPLL_RZ CCI_CPUPLL_RZ
+#define CCI_CPUPLL_RZ_POS (16U)
+#define CCI_CPUPLL_RZ_LEN (3U)
+#define CCI_CPUPLL_RZ_MSK (((1U << CCI_CPUPLL_RZ_LEN) - 1) << CCI_CPUPLL_RZ_POS)
+#define CCI_CPUPLL_RZ_UMSK (~(((1U << CCI_CPUPLL_RZ_LEN) - 1) << CCI_CPUPLL_RZ_POS))
+
+/* 0x7E0 : cpu_pll_cfg4 */
+#define CCI_CPU_PLL_CFG4_OFFSET (0x7E0)
+#define CCI_CPUPLL_SEL_SAMPLE_CLK CCI_CPUPLL_SEL_SAMPLE_CLK
+#define CCI_CPUPLL_SEL_SAMPLE_CLK_POS (0U)
+#define CCI_CPUPLL_SEL_SAMPLE_CLK_LEN (2U)
+#define CCI_CPUPLL_SEL_SAMPLE_CLK_MSK (((1U << CCI_CPUPLL_SEL_SAMPLE_CLK_LEN) - 1) << CCI_CPUPLL_SEL_SAMPLE_CLK_POS)
+#define CCI_CPUPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << CCI_CPUPLL_SEL_SAMPLE_CLK_LEN) - 1) << CCI_CPUPLL_SEL_SAMPLE_CLK_POS))
+#define CCI_CPUPLL_SEL_FB_CLK CCI_CPUPLL_SEL_FB_CLK
+#define CCI_CPUPLL_SEL_FB_CLK_POS (4U)
+#define CCI_CPUPLL_SEL_FB_CLK_LEN (2U)
+#define CCI_CPUPLL_SEL_FB_CLK_MSK (((1U << CCI_CPUPLL_SEL_FB_CLK_LEN) - 1) << CCI_CPUPLL_SEL_FB_CLK_POS)
+#define CCI_CPUPLL_SEL_FB_CLK_UMSK (~(((1U << CCI_CPUPLL_SEL_FB_CLK_LEN) - 1) << CCI_CPUPLL_SEL_FB_CLK_POS))
+#define CCI_CPUPLL_SDMCLK_SEL CCI_CPUPLL_SDMCLK_SEL
+#define CCI_CPUPLL_SDMCLK_SEL_POS (8U)
+#define CCI_CPUPLL_SDMCLK_SEL_LEN (1U)
+#define CCI_CPUPLL_SDMCLK_SEL_MSK (((1U << CCI_CPUPLL_SDMCLK_SEL_LEN) - 1) << CCI_CPUPLL_SDMCLK_SEL_POS)
+#define CCI_CPUPLL_SDMCLK_SEL_UMSK (~(((1U << CCI_CPUPLL_SDMCLK_SEL_LEN) - 1) << CCI_CPUPLL_SDMCLK_SEL_POS))
+
+/* 0x7E4 : cpu_pll_cfg5 */
+#define CCI_CPU_PLL_CFG5_OFFSET (0x7E4)
+#define CCI_CPUPLL_VCO_SPEED CCI_CPUPLL_VCO_SPEED
+#define CCI_CPUPLL_VCO_SPEED_POS (0U)
+#define CCI_CPUPLL_VCO_SPEED_LEN (3U)
+#define CCI_CPUPLL_VCO_SPEED_MSK (((1U << CCI_CPUPLL_VCO_SPEED_LEN) - 1) << CCI_CPUPLL_VCO_SPEED_POS)
+#define CCI_CPUPLL_VCO_SPEED_UMSK (~(((1U << CCI_CPUPLL_VCO_SPEED_LEN) - 1) << CCI_CPUPLL_VCO_SPEED_POS))
+
+/* 0x7E8 : cpu_pll_cfg6 */
+#define CCI_CPU_PLL_CFG6_OFFSET (0x7E8)
+#define CCI_CPUPLL_SDMIN CCI_CPUPLL_SDMIN
+#define CCI_CPUPLL_SDMIN_POS (0U)
+#define CCI_CPUPLL_SDMIN_LEN (19U)
+#define CCI_CPUPLL_SDMIN_MSK (((1U << CCI_CPUPLL_SDMIN_LEN) - 1) << CCI_CPUPLL_SDMIN_POS)
+#define CCI_CPUPLL_SDMIN_UMSK (~(((1U << CCI_CPUPLL_SDMIN_LEN) - 1) << CCI_CPUPLL_SDMIN_POS))
+#define CCI_CPUPLL_SDM_BYPASS CCI_CPUPLL_SDM_BYPASS
+#define CCI_CPUPLL_SDM_BYPASS_POS (24U)
+#define CCI_CPUPLL_SDM_BYPASS_LEN (1U)
+#define CCI_CPUPLL_SDM_BYPASS_MSK (((1U << CCI_CPUPLL_SDM_BYPASS_LEN) - 1) << CCI_CPUPLL_SDM_BYPASS_POS)
+#define CCI_CPUPLL_SDM_BYPASS_UMSK (~(((1U << CCI_CPUPLL_SDM_BYPASS_LEN) - 1) << CCI_CPUPLL_SDM_BYPASS_POS))
+
+/* 0x7EC : cpu_pll_cfg7 */
+#define CCI_CPU_PLL_CFG7_OFFSET (0x7EC)
+#define CCI_CPUPLL_SDM_ORDER_SEL CCI_CPUPLL_SDM_ORDER_SEL
+#define CCI_CPUPLL_SDM_ORDER_SEL_POS (0U)
+#define CCI_CPUPLL_SDM_ORDER_SEL_LEN (1U)
+#define CCI_CPUPLL_SDM_ORDER_SEL_MSK (((1U << CCI_CPUPLL_SDM_ORDER_SEL_LEN) - 1) << CCI_CPUPLL_SDM_ORDER_SEL_POS)
+#define CCI_CPUPLL_SDM_ORDER_SEL_UMSK (~(((1U << CCI_CPUPLL_SDM_ORDER_SEL_LEN) - 1) << CCI_CPUPLL_SDM_ORDER_SEL_POS))
+#define CCI_CPUPLL_SDM_SIG_DITH_SEL CCI_CPUPLL_SDM_SIG_DITH_SEL
+#define CCI_CPUPLL_SDM_SIG_DITH_SEL_POS (16U)
+#define CCI_CPUPLL_SDM_SIG_DITH_SEL_LEN (2U)
+#define CCI_CPUPLL_SDM_SIG_DITH_SEL_MSK (((1U << CCI_CPUPLL_SDM_SIG_DITH_SEL_LEN) - 1) << CCI_CPUPLL_SDM_SIG_DITH_SEL_POS)
+#define CCI_CPUPLL_SDM_SIG_DITH_SEL_UMSK (~(((1U << CCI_CPUPLL_SDM_SIG_DITH_SEL_LEN) - 1) << CCI_CPUPLL_SDM_SIG_DITH_SEL_POS))
+
+/* 0x7F0 : cpu_pll_cfg8 */
+#define CCI_CPU_PLL_CFG8_OFFSET (0x7F0)
+#define CCI_CPUPLL_EN_DIV1 CCI_CPUPLL_EN_DIV1
+#define CCI_CPUPLL_EN_DIV1_POS (0U)
+#define CCI_CPUPLL_EN_DIV1_LEN (1U)
+#define CCI_CPUPLL_EN_DIV1_MSK (((1U << CCI_CPUPLL_EN_DIV1_LEN) - 1) << CCI_CPUPLL_EN_DIV1_POS)
+#define CCI_CPUPLL_EN_DIV1_UMSK (~(((1U << CCI_CPUPLL_EN_DIV1_LEN) - 1) << CCI_CPUPLL_EN_DIV1_POS))
+#define CCI_CPUPLL_EN_DIV2 CCI_CPUPLL_EN_DIV2
+#define CCI_CPUPLL_EN_DIV2_POS (1U)
+#define CCI_CPUPLL_EN_DIV2_LEN (1U)
+#define CCI_CPUPLL_EN_DIV2_MSK (((1U << CCI_CPUPLL_EN_DIV2_LEN) - 1) << CCI_CPUPLL_EN_DIV2_POS)
+#define CCI_CPUPLL_EN_DIV2_UMSK (~(((1U << CCI_CPUPLL_EN_DIV2_LEN) - 1) << CCI_CPUPLL_EN_DIV2_POS))
+#define CCI_CPUPLL_EN_DIV2P5 CCI_CPUPLL_EN_DIV2P5
+#define CCI_CPUPLL_EN_DIV2P5_POS (2U)
+#define CCI_CPUPLL_EN_DIV2P5_LEN (1U)
+#define CCI_CPUPLL_EN_DIV2P5_MSK (((1U << CCI_CPUPLL_EN_DIV2P5_LEN) - 1) << CCI_CPUPLL_EN_DIV2P5_POS)
+#define CCI_CPUPLL_EN_DIV2P5_UMSK (~(((1U << CCI_CPUPLL_EN_DIV2P5_LEN) - 1) << CCI_CPUPLL_EN_DIV2P5_POS))
+#define CCI_CPUPLL_EN_DIV3 CCI_CPUPLL_EN_DIV3
+#define CCI_CPUPLL_EN_DIV3_POS (3U)
+#define CCI_CPUPLL_EN_DIV3_LEN (1U)
+#define CCI_CPUPLL_EN_DIV3_MSK (((1U << CCI_CPUPLL_EN_DIV3_LEN) - 1) << CCI_CPUPLL_EN_DIV3_POS)
+#define CCI_CPUPLL_EN_DIV3_UMSK (~(((1U << CCI_CPUPLL_EN_DIV3_LEN) - 1) << CCI_CPUPLL_EN_DIV3_POS))
+#define CCI_CPUPLL_EN_DIV4 CCI_CPUPLL_EN_DIV4
+#define CCI_CPUPLL_EN_DIV4_POS (4U)
+#define CCI_CPUPLL_EN_DIV4_LEN (1U)
+#define CCI_CPUPLL_EN_DIV4_MSK (((1U << CCI_CPUPLL_EN_DIV4_LEN) - 1) << CCI_CPUPLL_EN_DIV4_POS)
+#define CCI_CPUPLL_EN_DIV4_UMSK (~(((1U << CCI_CPUPLL_EN_DIV4_LEN) - 1) << CCI_CPUPLL_EN_DIV4_POS))
+#define CCI_CPUPLL_EN_DIV5 CCI_CPUPLL_EN_DIV5
+#define CCI_CPUPLL_EN_DIV5_POS (5U)
+#define CCI_CPUPLL_EN_DIV5_LEN (1U)
+#define CCI_CPUPLL_EN_DIV5_MSK (((1U << CCI_CPUPLL_EN_DIV5_LEN) - 1) << CCI_CPUPLL_EN_DIV5_POS)
+#define CCI_CPUPLL_EN_DIV5_UMSK (~(((1U << CCI_CPUPLL_EN_DIV5_LEN) - 1) << CCI_CPUPLL_EN_DIV5_POS))
+#define CCI_CPUPLL_EN_DIV6 CCI_CPUPLL_EN_DIV6
+#define CCI_CPUPLL_EN_DIV6_POS (6U)
+#define CCI_CPUPLL_EN_DIV6_LEN (1U)
+#define CCI_CPUPLL_EN_DIV6_MSK (((1U << CCI_CPUPLL_EN_DIV6_LEN) - 1) << CCI_CPUPLL_EN_DIV6_POS)
+#define CCI_CPUPLL_EN_DIV6_UMSK (~(((1U << CCI_CPUPLL_EN_DIV6_LEN) - 1) << CCI_CPUPLL_EN_DIV6_POS))
+#define CCI_CPUPLL_EN_DIV10 CCI_CPUPLL_EN_DIV10
+#define CCI_CPUPLL_EN_DIV10_POS (7U)
+#define CCI_CPUPLL_EN_DIV10_LEN (1U)
+#define CCI_CPUPLL_EN_DIV10_MSK (((1U << CCI_CPUPLL_EN_DIV10_LEN) - 1) << CCI_CPUPLL_EN_DIV10_POS)
+#define CCI_CPUPLL_EN_DIV10_UMSK (~(((1U << CCI_CPUPLL_EN_DIV10_LEN) - 1) << CCI_CPUPLL_EN_DIV10_POS))
+#define CCI_CPUPLL_EN_DIV15 CCI_CPUPLL_EN_DIV15
+#define CCI_CPUPLL_EN_DIV15_POS (8U)
+#define CCI_CPUPLL_EN_DIV15_LEN (1U)
+#define CCI_CPUPLL_EN_DIV15_MSK (((1U << CCI_CPUPLL_EN_DIV15_LEN) - 1) << CCI_CPUPLL_EN_DIV15_POS)
+#define CCI_CPUPLL_EN_DIV15_UMSK (~(((1U << CCI_CPUPLL_EN_DIV15_LEN) - 1) << CCI_CPUPLL_EN_DIV15_POS))
+#define CCI_CPUPLL_SEL_DIV1_DIV2 CCI_CPUPLL_SEL_DIV1_DIV2
+#define CCI_CPUPLL_SEL_DIV1_DIV2_POS (9U)
+#define CCI_CPUPLL_SEL_DIV1_DIV2_LEN (1U)
+#define CCI_CPUPLL_SEL_DIV1_DIV2_MSK (((1U << CCI_CPUPLL_SEL_DIV1_DIV2_LEN) - 1) << CCI_CPUPLL_SEL_DIV1_DIV2_POS)
+#define CCI_CPUPLL_SEL_DIV1_DIV2_UMSK (~(((1U << CCI_CPUPLL_SEL_DIV1_DIV2_LEN) - 1) << CCI_CPUPLL_SEL_DIV1_DIV2_POS))
+
+/* 0x7F4 : cpu_pll_cfg9 */
+#define CCI_CPU_PLL_CFG9_OFFSET (0x7F4)
+#define CCI_CPUPLL_DC_TP_OUT_EN CCI_CPUPLL_DC_TP_OUT_EN
+#define CCI_CPUPLL_DC_TP_OUT_EN_POS (0U)
+#define CCI_CPUPLL_DC_TP_OUT_EN_LEN (1U)
+#define CCI_CPUPLL_DC_TP_OUT_EN_MSK (((1U << CCI_CPUPLL_DC_TP_OUT_EN_LEN) - 1) << CCI_CPUPLL_DC_TP_OUT_EN_POS)
+#define CCI_CPUPLL_DC_TP_OUT_EN_UMSK (~(((1U << CCI_CPUPLL_DC_TP_OUT_EN_LEN) - 1) << CCI_CPUPLL_DC_TP_OUT_EN_POS))
+#define CCI_TEN_CPUPLL CCI_TEN_CPUPLL
+#define CCI_TEN_CPUPLL_POS (1U)
+#define CCI_TEN_CPUPLL_LEN (1U)
+#define CCI_TEN_CPUPLL_MSK (((1U << CCI_TEN_CPUPLL_LEN) - 1) << CCI_TEN_CPUPLL_POS)
+#define CCI_TEN_CPUPLL_UMSK (~(((1U << CCI_TEN_CPUPLL_LEN) - 1) << CCI_TEN_CPUPLL_POS))
+#define CCI_TEN_CPUPLL_SFREG CCI_TEN_CPUPLL_SFREG
+#define CCI_TEN_CPUPLL_SFREG_POS (2U)
+#define CCI_TEN_CPUPLL_SFREG_LEN (1U)
+#define CCI_TEN_CPUPLL_SFREG_MSK (((1U << CCI_TEN_CPUPLL_SFREG_LEN) - 1) << CCI_TEN_CPUPLL_SFREG_POS)
+#define CCI_TEN_CPUPLL_SFREG_UMSK (~(((1U << CCI_TEN_CPUPLL_SFREG_LEN) - 1) << CCI_TEN_CPUPLL_SFREG_POS))
+#define CCI_DTEN_CPUPLL_FIN CCI_DTEN_CPUPLL_FIN
+#define CCI_DTEN_CPUPLL_FIN_POS (4U)
+#define CCI_DTEN_CPUPLL_FIN_LEN (1U)
+#define CCI_DTEN_CPUPLL_FIN_MSK (((1U << CCI_DTEN_CPUPLL_FIN_LEN) - 1) << CCI_DTEN_CPUPLL_FIN_POS)
+#define CCI_DTEN_CPUPLL_FIN_UMSK (~(((1U << CCI_DTEN_CPUPLL_FIN_LEN) - 1) << CCI_DTEN_CPUPLL_FIN_POS))
+#define CCI_DTEN_CPUPLL_FREF CCI_DTEN_CPUPLL_FREF
+#define CCI_DTEN_CPUPLL_FREF_POS (5U)
+#define CCI_DTEN_CPUPLL_FREF_LEN (1U)
+#define CCI_DTEN_CPUPLL_FREF_MSK (((1U << CCI_DTEN_CPUPLL_FREF_LEN) - 1) << CCI_DTEN_CPUPLL_FREF_POS)
+#define CCI_DTEN_CPUPLL_FREF_UMSK (~(((1U << CCI_DTEN_CPUPLL_FREF_LEN) - 1) << CCI_DTEN_CPUPLL_FREF_POS))
+#define CCI_DTEN_CPUPLL_FSDM CCI_DTEN_CPUPLL_FSDM
+#define CCI_DTEN_CPUPLL_FSDM_POS (6U)
+#define CCI_DTEN_CPUPLL_FSDM_LEN (1U)
+#define CCI_DTEN_CPUPLL_FSDM_MSK (((1U << CCI_DTEN_CPUPLL_FSDM_LEN) - 1) << CCI_DTEN_CPUPLL_FSDM_POS)
+#define CCI_DTEN_CPUPLL_FSDM_UMSK (~(((1U << CCI_DTEN_CPUPLL_FSDM_LEN) - 1) << CCI_DTEN_CPUPLL_FSDM_POS))
+#define CCI_DTEN_CPUPLL_DIV15 CCI_DTEN_CPUPLL_DIV15
+#define CCI_DTEN_CPUPLL_DIV15_POS (7U)
+#define CCI_DTEN_CPUPLL_DIV15_LEN (1U)
+#define CCI_DTEN_CPUPLL_DIV15_MSK (((1U << CCI_DTEN_CPUPLL_DIV15_LEN) - 1) << CCI_DTEN_CPUPLL_DIV15_POS)
+#define CCI_DTEN_CPUPLL_DIV15_UMSK (~(((1U << CCI_DTEN_CPUPLL_DIV15_LEN) - 1) << CCI_DTEN_CPUPLL_DIV15_POS))
+#define CCI_DTEN_CPUPLL_DIV5 CCI_DTEN_CPUPLL_DIV5
+#define CCI_DTEN_CPUPLL_DIV5_POS (8U)
+#define CCI_DTEN_CPUPLL_DIV5_LEN (1U)
+#define CCI_DTEN_CPUPLL_DIV5_MSK (((1U << CCI_DTEN_CPUPLL_DIV5_LEN) - 1) << CCI_DTEN_CPUPLL_DIV5_POS)
+#define CCI_DTEN_CPUPLL_DIV5_UMSK (~(((1U << CCI_DTEN_CPUPLL_DIV5_LEN) - 1) << CCI_DTEN_CPUPLL_DIV5_POS))
+#define CCI_DTEN_CPUPLL_POSTDIV_CLK CCI_DTEN_CPUPLL_POSTDIV_CLK
+#define CCI_DTEN_CPUPLL_POSTDIV_CLK_POS (9U)
+#define CCI_DTEN_CPUPLL_POSTDIV_CLK_LEN (1U)
+#define CCI_DTEN_CPUPLL_POSTDIV_CLK_MSK (((1U << CCI_DTEN_CPUPLL_POSTDIV_CLK_LEN) - 1) << CCI_DTEN_CPUPLL_POSTDIV_CLK_POS)
+#define CCI_DTEN_CPUPLL_POSTDIV_CLK_UMSK (~(((1U << CCI_DTEN_CPUPLL_POSTDIV_CLK_LEN) - 1) << CCI_DTEN_CPUPLL_POSTDIV_CLK_POS))
+#define CCI_DTEST_CPUPLL_PULLDOWN CCI_DTEST_CPUPLL_PULLDOWN
+#define CCI_DTEST_CPUPLL_PULLDOWN_POS (10U)
+#define CCI_DTEST_CPUPLL_PULLDOWN_LEN (1U)
+#define CCI_DTEST_CPUPLL_PULLDOWN_MSK (((1U << CCI_DTEST_CPUPLL_PULLDOWN_LEN) - 1) << CCI_DTEST_CPUPLL_PULLDOWN_POS)
+#define CCI_DTEST_CPUPLL_PULLDOWN_UMSK (~(((1U << CCI_DTEST_CPUPLL_PULLDOWN_LEN) - 1) << CCI_DTEST_CPUPLL_PULLDOWN_POS))
+
+/* 0x7F8 : cpu_pll_cfg10 */
+#define CCI_CPU_PLL_CFG10_OFFSET (0x7F8)
+#define CCI_CPUPLL_SSC_EN CCI_CPUPLL_SSC_EN
+#define CCI_CPUPLL_SSC_EN_POS (0U)
+#define CCI_CPUPLL_SSC_EN_LEN (1U)
+#define CCI_CPUPLL_SSC_EN_MSK (((1U << CCI_CPUPLL_SSC_EN_LEN) - 1) << CCI_CPUPLL_SSC_EN_POS)
+#define CCI_CPUPLL_SSC_EN_UMSK (~(((1U << CCI_CPUPLL_SSC_EN_LEN) - 1) << CCI_CPUPLL_SSC_EN_POS))
+#define CCI_CPUPLL_SSC_CNT CCI_CPUPLL_SSC_CNT
+#define CCI_CPUPLL_SSC_CNT_POS (4U)
+#define CCI_CPUPLL_SSC_CNT_LEN (8U)
+#define CCI_CPUPLL_SSC_CNT_MSK (((1U << CCI_CPUPLL_SSC_CNT_LEN) - 1) << CCI_CPUPLL_SSC_CNT_POS)
+#define CCI_CPUPLL_SSC_CNT_UMSK (~(((1U << CCI_CPUPLL_SSC_CNT_LEN) - 1) << CCI_CPUPLL_SSC_CNT_POS))
+#define CCI_CPUPLL_SSC_GAIN CCI_CPUPLL_SSC_GAIN
+#define CCI_CPUPLL_SSC_GAIN_POS (12U)
+#define CCI_CPUPLL_SSC_GAIN_LEN (3U)
+#define CCI_CPUPLL_SSC_GAIN_MSK (((1U << CCI_CPUPLL_SSC_GAIN_LEN) - 1) << CCI_CPUPLL_SSC_GAIN_POS)
+#define CCI_CPUPLL_SSC_GAIN_UMSK (~(((1U << CCI_CPUPLL_SSC_GAIN_LEN) - 1) << CCI_CPUPLL_SSC_GAIN_POS))
+#define CCI_CPUPLL_SSC_START_GATE_EN CCI_CPUPLL_SSC_START_GATE_EN
+#define CCI_CPUPLL_SSC_START_GATE_EN_POS (16U)
+#define CCI_CPUPLL_SSC_START_GATE_EN_LEN (1U)
+#define CCI_CPUPLL_SSC_START_GATE_EN_MSK (((1U << CCI_CPUPLL_SSC_START_GATE_EN_LEN) - 1) << CCI_CPUPLL_SSC_START_GATE_EN_POS)
+#define CCI_CPUPLL_SSC_START_GATE_EN_UMSK (~(((1U << CCI_CPUPLL_SSC_START_GATE_EN_LEN) - 1) << CCI_CPUPLL_SSC_START_GATE_EN_POS))
+#define CCI_CPUPLL_SSC_START CCI_CPUPLL_SSC_START
+#define CCI_CPUPLL_SSC_START_POS (20U)
+#define CCI_CPUPLL_SSC_START_LEN (1U)
+#define CCI_CPUPLL_SSC_START_MSK (((1U << CCI_CPUPLL_SSC_START_LEN) - 1) << CCI_CPUPLL_SSC_START_POS)
+#define CCI_CPUPLL_SSC_START_UMSK (~(((1U << CCI_CPUPLL_SSC_START_LEN) - 1) << CCI_CPUPLL_SSC_START_POS))
+
+/* 0x7FC : cpu_pll_cfg11 */
+#define CCI_CPU_PLL_CFG11_OFFSET (0x7FC)
+#define CCI_CPUPLL_RESV CCI_CPUPLL_RESV
+#define CCI_CPUPLL_RESV_POS (0U)
+#define CCI_CPUPLL_RESV_LEN (16U)
+#define CCI_CPUPLL_RESV_MSK (((1U << CCI_CPUPLL_RESV_LEN) - 1) << CCI_CPUPLL_RESV_POS)
+#define CCI_CPUPLL_RESV_UMSK (~(((1U << CCI_CPUPLL_RESV_LEN) - 1) << CCI_CPUPLL_RESV_POS))
+#define CCI_CPUPLL_DL_CTRL_15 CCI_CPUPLL_DL_CTRL_15
+#define CCI_CPUPLL_DL_CTRL_15_POS (23U)
+#define CCI_CPUPLL_DL_CTRL_15_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_15_MSK (((1U << CCI_CPUPLL_DL_CTRL_15_LEN) - 1) << CCI_CPUPLL_DL_CTRL_15_POS)
+#define CCI_CPUPLL_DL_CTRL_15_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_15_LEN) - 1) << CCI_CPUPLL_DL_CTRL_15_POS))
+#define CCI_CPUPLL_DL_CTRL_10 CCI_CPUPLL_DL_CTRL_10
+#define CCI_CPUPLL_DL_CTRL_10_POS (24U)
+#define CCI_CPUPLL_DL_CTRL_10_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_10_MSK (((1U << CCI_CPUPLL_DL_CTRL_10_LEN) - 1) << CCI_CPUPLL_DL_CTRL_10_POS)
+#define CCI_CPUPLL_DL_CTRL_10_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_10_LEN) - 1) << CCI_CPUPLL_DL_CTRL_10_POS))
+#define CCI_CPUPLL_DL_CTRL_6 CCI_CPUPLL_DL_CTRL_6
+#define CCI_CPUPLL_DL_CTRL_6_POS (25U)
+#define CCI_CPUPLL_DL_CTRL_6_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_6_MSK (((1U << CCI_CPUPLL_DL_CTRL_6_LEN) - 1) << CCI_CPUPLL_DL_CTRL_6_POS)
+#define CCI_CPUPLL_DL_CTRL_6_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_6_LEN) - 1) << CCI_CPUPLL_DL_CTRL_6_POS))
+#define CCI_CPUPLL_DL_CTRL_5 CCI_CPUPLL_DL_CTRL_5
+#define CCI_CPUPLL_DL_CTRL_5_POS (26U)
+#define CCI_CPUPLL_DL_CTRL_5_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_5_MSK (((1U << CCI_CPUPLL_DL_CTRL_5_LEN) - 1) << CCI_CPUPLL_DL_CTRL_5_POS)
+#define CCI_CPUPLL_DL_CTRL_5_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_5_LEN) - 1) << CCI_CPUPLL_DL_CTRL_5_POS))
+#define CCI_CPUPLL_DL_CTRL_4 CCI_CPUPLL_DL_CTRL_4
+#define CCI_CPUPLL_DL_CTRL_4_POS (27U)
+#define CCI_CPUPLL_DL_CTRL_4_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_4_MSK (((1U << CCI_CPUPLL_DL_CTRL_4_LEN) - 1) << CCI_CPUPLL_DL_CTRL_4_POS)
+#define CCI_CPUPLL_DL_CTRL_4_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_4_LEN) - 1) << CCI_CPUPLL_DL_CTRL_4_POS))
+#define CCI_CPUPLL_DL_CTRL_3 CCI_CPUPLL_DL_CTRL_3
+#define CCI_CPUPLL_DL_CTRL_3_POS (28U)
+#define CCI_CPUPLL_DL_CTRL_3_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_3_MSK (((1U << CCI_CPUPLL_DL_CTRL_3_LEN) - 1) << CCI_CPUPLL_DL_CTRL_3_POS)
+#define CCI_CPUPLL_DL_CTRL_3_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_3_LEN) - 1) << CCI_CPUPLL_DL_CTRL_3_POS))
+#define CCI_CPUPLL_DL_CTRL_2P5 CCI_CPUPLL_DL_CTRL_2P5
+#define CCI_CPUPLL_DL_CTRL_2P5_POS (29U)
+#define CCI_CPUPLL_DL_CTRL_2P5_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_2P5_MSK (((1U << CCI_CPUPLL_DL_CTRL_2P5_LEN) - 1) << CCI_CPUPLL_DL_CTRL_2P5_POS)
+#define CCI_CPUPLL_DL_CTRL_2P5_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_2P5_LEN) - 1) << CCI_CPUPLL_DL_CTRL_2P5_POS))
+#define CCI_CPUPLL_DL_CTRL_2 CCI_CPUPLL_DL_CTRL_2
+#define CCI_CPUPLL_DL_CTRL_2_POS (30U)
+#define CCI_CPUPLL_DL_CTRL_2_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_2_MSK (((1U << CCI_CPUPLL_DL_CTRL_2_LEN) - 1) << CCI_CPUPLL_DL_CTRL_2_POS)
+#define CCI_CPUPLL_DL_CTRL_2_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_2_LEN) - 1) << CCI_CPUPLL_DL_CTRL_2_POS))
+#define CCI_CPUPLL_DL_CTRL_1 CCI_CPUPLL_DL_CTRL_1
+#define CCI_CPUPLL_DL_CTRL_1_POS (31U)
+#define CCI_CPUPLL_DL_CTRL_1_LEN (1U)
+#define CCI_CPUPLL_DL_CTRL_1_MSK (((1U << CCI_CPUPLL_DL_CTRL_1_LEN) - 1) << CCI_CPUPLL_DL_CTRL_1_POS)
+#define CCI_CPUPLL_DL_CTRL_1_UMSK (~(((1U << CCI_CPUPLL_DL_CTRL_1_LEN) - 1) << CCI_CPUPLL_DL_CTRL_1_POS))
+
+struct cci_reg {
+ /* 0x0 : cci_cfg */
+ union {
+ struct {
+ uint32_t cci_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t cci_slv_sel_cci2 : 1; /* [ 1], r/w, 0x0 */
+ uint32_t cci_mas_sel_cci2 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t cci_mas_hw_mode : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg_m_cci_sclk_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_div_m_cci_sclk : 2; /* [ 6: 5], r/w, 0x1 */
+ uint32_t cfg_cci1_pre_read : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_scci_clk_inv : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_mcci_clk_inv : 1; /* [ 9], r/w, 0x1 */
+ uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cci_cfg;
+
+ /* 0x4 : cci_addr */
+ union {
+ struct {
+ uint32_t apb_cci_addr : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cci_addr;
+
+ /* 0x8 : cci_wdata */
+ union {
+ struct {
+ uint32_t apb_cci_wdata : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cci_wdata;
+
+ /* 0xC : cci_rdata */
+ union {
+ struct {
+ uint32_t apb_cci_rdata : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cci_rdata;
+
+ /* 0x10 : cci_ctl */
+ union {
+ struct {
+ uint32_t cci_write_flag : 1; /* [ 0], r, 0x0 */
+ uint32_t cci_read_flag : 1; /* [ 1], r, 0x0 */
+ uint32_t ahb_state : 2; /* [ 3: 2], r, 0x0 */
+ uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cci_ctl;
+
+ /* 0x14 reserved */
+ uint8_t RESERVED0x14[1852];
+
+ /* 0x750 : audio_pll_cfg0 */
+ union {
+ struct {
+ uint32_t aupll_sdm_rstb : 1; /* [ 0], r/w, 0x1 */
+ uint32_t aupll_postdiv_rstb : 1; /* [ 1], r/w, 0x1 */
+ uint32_t aupll_fbdv_rstb : 1; /* [ 2], r/w, 0x1 */
+ uint32_t aupll_refdiv_rstb : 1; /* [ 3], r/w, 0x1 */
+ uint32_t pu_aupll_postdiv : 1; /* [ 4], r/w, 0x1 */
+ uint32_t pu_aupll_fbdv : 1; /* [ 5], r/w, 0x1 */
+ uint32_t pu_aupll_clamp_op : 1; /* [ 6], r/w, 0x1 */
+ uint32_t pu_aupll_pfd : 1; /* [ 7], r/w, 0x1 */
+ uint32_t pu_aupll_cp : 1; /* [ 8], r/w, 0x1 */
+ uint32_t pu_aupll_sfreg : 1; /* [ 9], r/w, 0x0 */
+ uint32_t pu_aupll : 1; /* [ 10], r/w, 0x0 */
+ uint32_t pu_aupll_clktree : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg0;
+
+ /* 0x754 : audio_pll_cfg1 */
+ union {
+ struct {
+ uint32_t aupll_postdiv : 7; /* [ 6: 0], r/w, 0x12 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t aupll_refdiv_ratio : 4; /* [11: 8], r/w, 0x4 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t aupll_refclk_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
+ uint32_t aupll_vg11_sel : 2; /* [21:20], r/w, 0x1 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t aupll_vg13_sel : 2; /* [25:24], r/w, 0x1 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg1;
+
+ /* 0x758 : audio_pll_cfg2 */
+ union {
+ struct {
+ uint32_t aupll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t aupll_icp_5u : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t aupll_icp_1u : 2; /* [ 7: 6], r/w, 0x1 */
+ uint32_t aupll_int_frac_sw : 1; /* [ 8], r/w, 0x1 */
+ uint32_t aupll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t aupll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg2;
+
+ /* 0x75C : audio_pll_cfg3 */
+ union {
+ struct {
+ uint32_t aupll_c4_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t aupll_r4 : 2; /* [ 5: 4], r/w, 0x2 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t aupll_r4_short : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t aupll_c3 : 2; /* [13:12], r/w, 0x2 */
+ uint32_t aupll_cz : 2; /* [15:14], r/w, 0x2 */
+ uint32_t aupll_rz : 3; /* [18:16], r/w, 0x5 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg3;
+
+ /* 0x760 : audio_pll_cfg4 */
+ union {
+ struct {
+ uint32_t aupll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t aupll_sel_fb_clk : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t aupll_sdmclk_sel : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg4;
+
+ /* 0x764 : audio_pll_cfg5 */
+ union {
+ struct {
+ uint32_t aupll_vco_speed : 3; /* [ 2: 0], r/w, 0x3 */
+ uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg5;
+
+ /* 0x768 : audio_pll_cfg6 */
+ union {
+ struct {
+ uint32_t aupll_sdmin : 19; /* [18: 0], r/w, 0x161e5 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t aupll_sdm_bypass : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg6;
+
+ /* 0x76C : audio_pll_cfg7 */
+ union {
+ struct {
+ uint32_t aupll_sdm_order_sel : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */
+ uint32_t aupll_sdm_sig_dith_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg7;
+
+ /* 0x770 : audio_pll_cfg8 */
+ union {
+ struct {
+ uint32_t aupll_en_div1 : 1; /* [ 0], r/w, 0x0 */
+ uint32_t aupll_en_div2 : 1; /* [ 1], r/w, 0x0 */
+ uint32_t aupll_en_div2p5 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t aupll_en_div3 : 1; /* [ 3], r/w, 0x0 */
+ uint32_t aupll_en_div4 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t aupll_en_div5 : 1; /* [ 5], r/w, 0x0 */
+ uint32_t aupll_en_div6 : 1; /* [ 6], r/w, 0x0 */
+ uint32_t aupll_en_div10 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t aupll_en_div15 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t aupll_sel_div1_div2 : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg8;
+
+ /* 0x774 : audio_pll_cfg9 */
+ union {
+ struct {
+ uint32_t aupll_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t ten_aupll : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ten_aupll_sfreg : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t dten_aupll_fin : 1; /* [ 4], r/w, 0x0 */
+ uint32_t dten_aupll_fref : 1; /* [ 5], r/w, 0x0 */
+ uint32_t dten_aupll_fsdm : 1; /* [ 6], r/w, 0x0 */
+ uint32_t dten_aupll_div15 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t dten_aupll_div5 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t dten_aupll_postdiv_clk : 1; /* [ 9], r/w, 0x0 */
+ uint32_t dtest_aupll_pulldown : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg9;
+
+ /* 0x778 : audio_pll_cfg10 */
+ union {
+ struct {
+ uint32_t aupll_ssc_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t aupll_ssc_cnt : 8; /* [11: 4], r/w, 0x64 */
+ uint32_t aupll_ssc_gain : 3; /* [14:12], r/w, 0x4 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t aupll_ssc_start_gate_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */
+ uint32_t aupll_ssc_start : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg10;
+
+ /* 0x77C : audio_pll_cfg11 */
+ union {
+ struct {
+ uint32_t aupll_resv : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reserved_16_22 : 7; /* [22:16], rsvd, 0x0 */
+ uint32_t aupll_dl_ctrl_15 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_10 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_6 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_5 : 1; /* [ 26], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_4 : 1; /* [ 27], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_3 : 1; /* [ 28], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_2p5 : 1; /* [ 29], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_2 : 1; /* [ 30], r/w, 0x0 */
+ uint32_t aupll_dl_ctrl_1 : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_pll_cfg11;
+
+ /* 0x780 reserved */
+ uint8_t RESERVED0x780[80];
+
+ /* 0x7D0 : cpu_pll_cfg0 */
+ union {
+ struct {
+ uint32_t cpupll_sdm_rstb : 1; /* [ 0], r/w, 0x1 */
+ uint32_t cpupll_postdiv_rstb : 1; /* [ 1], r/w, 0x1 */
+ uint32_t cpupll_fbdv_rstb : 1; /* [ 2], r/w, 0x1 */
+ uint32_t cpupll_refdiv_rstb : 1; /* [ 3], r/w, 0x1 */
+ uint32_t pu_cpupll_postdiv : 1; /* [ 4], r/w, 0x0 */
+ uint32_t pu_cpupll_fbdv : 1; /* [ 5], r/w, 0x1 */
+ uint32_t pu_cpupll_clamp_op : 1; /* [ 6], r/w, 0x1 */
+ uint32_t pu_cpupll_pfd : 1; /* [ 7], r/w, 0x1 */
+ uint32_t pu_cpupll_cp : 1; /* [ 8], r/w, 0x1 */
+ uint32_t pu_cpupll_sfreg : 1; /* [ 9], r/w, 0x0 */
+ uint32_t pu_cpupll : 1; /* [ 10], r/w, 0x0 */
+ uint32_t pu_cpupll_clktree : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg0;
+
+ /* 0x7D4 : cpu_pll_cfg1 */
+ union {
+ struct {
+ uint32_t cpupll_postdiv : 7; /* [ 6: 0], r/w, 0x18 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t cpupll_refdiv_ratio : 4; /* [11: 8], r/w, 0x4 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t cpupll_refclk_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
+ uint32_t cpupll_vg11_sel : 2; /* [21:20], r/w, 0x1 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t cpupll_vg13_sel : 2; /* [25:24], r/w, 0x1 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg1;
+
+ /* 0x7D8 : cpu_pll_cfg2 */
+ union {
+ struct {
+ uint32_t cpupll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t cpupll_icp_5u : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t cpupll_icp_1u : 2; /* [ 7: 6], r/w, 0x1 */
+ uint32_t cpupll_int_frac_sw : 1; /* [ 8], r/w, 0x1 */
+ uint32_t cpupll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t cpupll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg2;
+
+ /* 0x7DC : cpu_pll_cfg3 */
+ union {
+ struct {
+ uint32_t cpupll_c4_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t cpupll_r4 : 2; /* [ 5: 4], r/w, 0x2 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t cpupll_r4_short : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t cpupll_c3 : 2; /* [13:12], r/w, 0x2 */
+ uint32_t cpupll_cz : 2; /* [15:14], r/w, 0x2 */
+ uint32_t cpupll_rz : 3; /* [18:16], r/w, 0x5 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg3;
+
+ /* 0x7E0 : cpu_pll_cfg4 */
+ union {
+ struct {
+ uint32_t cpupll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t cpupll_sel_fb_clk : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t cpupll_sdmclk_sel : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg4;
+
+ /* 0x7E4 : cpu_pll_cfg5 */
+ union {
+ struct {
+ uint32_t cpupll_vco_speed : 3; /* [ 2: 0], r/w, 0x3 */
+ uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg5;
+
+ /* 0x7E8 : cpu_pll_cfg6 */
+ union {
+ struct {
+ uint32_t cpupll_sdmin : 19; /* [18: 0], r/w, 0x161e5 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t cpupll_sdm_bypass : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg6;
+
+ /* 0x7EC : cpu_pll_cfg7 */
+ union {
+ struct {
+ uint32_t cpupll_sdm_order_sel : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */
+ uint32_t cpupll_sdm_sig_dith_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg7;
+
+ /* 0x7F0 : cpu_pll_cfg8 */
+ union {
+ struct {
+ uint32_t cpupll_en_div1 : 1; /* [ 0], r/w, 0x1 */
+ uint32_t cpupll_en_div2 : 1; /* [ 1], r/w, 0x0 */
+ uint32_t cpupll_en_div2p5 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t cpupll_en_div3 : 1; /* [ 3], r/w, 0x0 */
+ uint32_t cpupll_en_div4 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t cpupll_en_div5 : 1; /* [ 5], r/w, 0x0 */
+ uint32_t cpupll_en_div6 : 1; /* [ 6], r/w, 0x0 */
+ uint32_t cpupll_en_div10 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t cpupll_en_div15 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t cpupll_sel_div1_div2 : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg8;
+
+ /* 0x7F4 : cpu_pll_cfg9 */
+ union {
+ struct {
+ uint32_t cpupll_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t ten_cpupll : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ten_cpupll_sfreg : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t dten_cpupll_fin : 1; /* [ 4], r/w, 0x0 */
+ uint32_t dten_cpupll_fref : 1; /* [ 5], r/w, 0x0 */
+ uint32_t dten_cpupll_fsdm : 1; /* [ 6], r/w, 0x0 */
+ uint32_t dten_cpupll_div15 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t dten_cpupll_div5 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t dten_cpupll_postdiv_clk : 1; /* [ 9], r/w, 0x0 */
+ uint32_t dtest_cpupll_pulldown : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg9;
+
+ /* 0x7F8 : cpu_pll_cfg10 */
+ union {
+ struct {
+ uint32_t cpupll_ssc_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t cpupll_ssc_cnt : 8; /* [11: 4], r/w, 0x64 */
+ uint32_t cpupll_ssc_gain : 3; /* [14:12], r/w, 0x4 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t cpupll_ssc_start_gate_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */
+ uint32_t cpupll_ssc_start : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg10;
+
+ /* 0x7FC : cpu_pll_cfg11 */
+ union {
+ struct {
+ uint32_t cpupll_resv : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reserved_16_22 : 7; /* [22:16], rsvd, 0x0 */
+ uint32_t cpupll_dl_ctrl_15 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_10 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_6 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_5 : 1; /* [ 26], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_4 : 1; /* [ 27], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_3 : 1; /* [ 28], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_2p5 : 1; /* [ 29], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_2 : 1; /* [ 30], r/w, 0x0 */
+ uint32_t cpupll_dl_ctrl_1 : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_pll_cfg11;
+};
+
+typedef volatile struct cci_reg cci_reg_t;
+
+#endif /* __CCI_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/codec_misc_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/codec_misc_reg.h
new file mode 100644
index 00000000..9fadafc0
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/codec_misc_reg.h
@@ -0,0 +1,342 @@
+/**
+ ******************************************************************************
+ * @file codec_misc_reg.h
+ * @version V1.0
+ * @date 2021-05-11
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __CODEC_MISC_REG_H__
+#define __CODEC_MISC_REG_H__
+
+#include "bl808.h"
+
+/* 0x00 : codec_bus_ctrl */
+#define CODEC_MISC_CODEC_BUS_CTRL_OFFSET (0x00)
+#define CODEC_MISC_RG_PCLK_FORCE_ON CODEC_MISC_RG_PCLK_FORCE_ON
+#define CODEC_MISC_RG_PCLK_FORCE_ON_POS (0U)
+#define CODEC_MISC_RG_PCLK_FORCE_ON_LEN (16U)
+#define CODEC_MISC_RG_PCLK_FORCE_ON_MSK (((1U << CODEC_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << CODEC_MISC_RG_PCLK_FORCE_ON_POS)
+#define CODEC_MISC_RG_PCLK_FORCE_ON_UMSK (~(((1U << CODEC_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << CODEC_MISC_RG_PCLK_FORCE_ON_POS))
+
+/* 0x04 : codec_qos_ctrl */
+#define CODEC_MISC_CODEC_QOS_CTRL_OFFSET (0x04)
+#define CODEC_MISC_REG_JENC_AWQOS CODEC_MISC_REG_JENC_AWQOS
+#define CODEC_MISC_REG_JENC_AWQOS_POS (0U)
+#define CODEC_MISC_REG_JENC_AWQOS_LEN (1U)
+#define CODEC_MISC_REG_JENC_AWQOS_MSK (((1U << CODEC_MISC_REG_JENC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JENC_AWQOS_POS)
+#define CODEC_MISC_REG_JENC_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_JENC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JENC_AWQOS_POS))
+#define CODEC_MISC_REG_JENC_ARQOS CODEC_MISC_REG_JENC_ARQOS
+#define CODEC_MISC_REG_JENC_ARQOS_POS (1U)
+#define CODEC_MISC_REG_JENC_ARQOS_LEN (1U)
+#define CODEC_MISC_REG_JENC_ARQOS_MSK (((1U << CODEC_MISC_REG_JENC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JENC_ARQOS_POS)
+#define CODEC_MISC_REG_JENC_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_JENC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JENC_ARQOS_POS))
+#define CODEC_MISC_REG_JDEC_AWQOS CODEC_MISC_REG_JDEC_AWQOS
+#define CODEC_MISC_REG_JDEC_AWQOS_POS (2U)
+#define CODEC_MISC_REG_JDEC_AWQOS_LEN (1U)
+#define CODEC_MISC_REG_JDEC_AWQOS_MSK (((1U << CODEC_MISC_REG_JDEC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_AWQOS_POS)
+#define CODEC_MISC_REG_JDEC_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_JDEC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_AWQOS_POS))
+#define CODEC_MISC_REG_JDEC_ARQOS CODEC_MISC_REG_JDEC_ARQOS
+#define CODEC_MISC_REG_JDEC_ARQOS_POS (3U)
+#define CODEC_MISC_REG_JDEC_ARQOS_LEN (1U)
+#define CODEC_MISC_REG_JDEC_ARQOS_MSK (((1U << CODEC_MISC_REG_JDEC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_ARQOS_POS)
+#define CODEC_MISC_REG_JDEC_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_JDEC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_ARQOS_POS))
+#define CODEC_MISC_REG_VDO0_AWQOS CODEC_MISC_REG_VDO0_AWQOS
+#define CODEC_MISC_REG_VDO0_AWQOS_POS (4U)
+#define CODEC_MISC_REG_VDO0_AWQOS_LEN (1U)
+#define CODEC_MISC_REG_VDO0_AWQOS_MSK (((1U << CODEC_MISC_REG_VDO0_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_AWQOS_POS)
+#define CODEC_MISC_REG_VDO0_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO0_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_AWQOS_POS))
+#define CODEC_MISC_REG_VDO0_ARQOS CODEC_MISC_REG_VDO0_ARQOS
+#define CODEC_MISC_REG_VDO0_ARQOS_POS (5U)
+#define CODEC_MISC_REG_VDO0_ARQOS_LEN (1U)
+#define CODEC_MISC_REG_VDO0_ARQOS_MSK (((1U << CODEC_MISC_REG_VDO0_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_ARQOS_POS)
+#define CODEC_MISC_REG_VDO0_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO0_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_ARQOS_POS))
+#define CODEC_MISC_REG_VDO1_AWQOS CODEC_MISC_REG_VDO1_AWQOS
+#define CODEC_MISC_REG_VDO1_AWQOS_POS (6U)
+#define CODEC_MISC_REG_VDO1_AWQOS_LEN (1U)
+#define CODEC_MISC_REG_VDO1_AWQOS_MSK (((1U << CODEC_MISC_REG_VDO1_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_AWQOS_POS)
+#define CODEC_MISC_REG_VDO1_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO1_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_AWQOS_POS))
+#define CODEC_MISC_REG_VDO1_ARQOS CODEC_MISC_REG_VDO1_ARQOS
+#define CODEC_MISC_REG_VDO1_ARQOS_POS (7U)
+#define CODEC_MISC_REG_VDO1_ARQOS_LEN (1U)
+#define CODEC_MISC_REG_VDO1_ARQOS_MSK (((1U << CODEC_MISC_REG_VDO1_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_ARQOS_POS)
+#define CODEC_MISC_REG_VDO1_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO1_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_ARQOS_POS))
+#define CODEC_MISC_REG_REF_AWQOS CODEC_MISC_REG_REF_AWQOS
+#define CODEC_MISC_REG_REF_AWQOS_POS (8U)
+#define CODEC_MISC_REG_REF_AWQOS_LEN (1U)
+#define CODEC_MISC_REG_REF_AWQOS_MSK (((1U << CODEC_MISC_REG_REF_AWQOS_LEN) - 1) << CODEC_MISC_REG_REF_AWQOS_POS)
+#define CODEC_MISC_REG_REF_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_REF_AWQOS_LEN) - 1) << CODEC_MISC_REG_REF_AWQOS_POS))
+#define CODEC_MISC_REG_REF_ARQOS CODEC_MISC_REG_REF_ARQOS
+#define CODEC_MISC_REG_REF_ARQOS_POS (9U)
+#define CODEC_MISC_REG_REF_ARQOS_LEN (1U)
+#define CODEC_MISC_REG_REF_ARQOS_MSK (((1U << CODEC_MISC_REG_REF_ARQOS_LEN) - 1) << CODEC_MISC_REG_REF_ARQOS_POS)
+#define CODEC_MISC_REG_REF_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_REF_ARQOS_LEN) - 1) << CODEC_MISC_REG_REF_ARQOS_POS))
+#define CODEC_MISC_REG_CNN_AWQOS CODEC_MISC_REG_CNN_AWQOS
+#define CODEC_MISC_REG_CNN_AWQOS_POS (10U)
+#define CODEC_MISC_REG_CNN_AWQOS_LEN (1U)
+#define CODEC_MISC_REG_CNN_AWQOS_MSK (((1U << CODEC_MISC_REG_CNN_AWQOS_LEN) - 1) << CODEC_MISC_REG_CNN_AWQOS_POS)
+#define CODEC_MISC_REG_CNN_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_CNN_AWQOS_LEN) - 1) << CODEC_MISC_REG_CNN_AWQOS_POS))
+#define CODEC_MISC_REG_CNN_ARQOS CODEC_MISC_REG_CNN_ARQOS
+#define CODEC_MISC_REG_CNN_ARQOS_POS (11U)
+#define CODEC_MISC_REG_CNN_ARQOS_LEN (1U)
+#define CODEC_MISC_REG_CNN_ARQOS_MSK (((1U << CODEC_MISC_REG_CNN_ARQOS_LEN) - 1) << CODEC_MISC_REG_CNN_ARQOS_POS)
+#define CODEC_MISC_REG_CNN_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_CNN_ARQOS_LEN) - 1) << CODEC_MISC_REG_CNN_ARQOS_POS))
+
+/* 0x08 : codec_bus_thre */
+#define CODEC_MISC_CODEC_BUS_THRE_OFFSET (0x08)
+#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM
+#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_POS (0U)
+#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_LEN (2U)
+#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_MSK (((1U << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_POS)
+#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_POS))
+#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT CODEC_MISC_REG_X_WTHRE_BLAI2EXT
+#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_POS (2U)
+#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_LEN (2U)
+#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_MSK (((1U << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_POS)
+#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_POS))
+#define CODEC_MISC_REG_X_WTHRE_VDO2PB CODEC_MISC_REG_X_WTHRE_VDO2PB
+#define CODEC_MISC_REG_X_WTHRE_VDO2PB_POS (4U)
+#define CODEC_MISC_REG_X_WTHRE_VDO2PB_LEN (2U)
+#define CODEC_MISC_REG_X_WTHRE_VDO2PB_MSK (((1U << CODEC_MISC_REG_X_WTHRE_VDO2PB_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PB_POS)
+#define CODEC_MISC_REG_X_WTHRE_VDO2PB_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_VDO2PB_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PB_POS))
+#define CODEC_MISC_REG_X_WTHRE_VDO2PA CODEC_MISC_REG_X_WTHRE_VDO2PA
+#define CODEC_MISC_REG_X_WTHRE_VDO2PA_POS (6U)
+#define CODEC_MISC_REG_X_WTHRE_VDO2PA_LEN (2U)
+#define CODEC_MISC_REG_X_WTHRE_VDO2PA_MSK (((1U << CODEC_MISC_REG_X_WTHRE_VDO2PA_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PA_POS)
+#define CODEC_MISC_REG_X_WTHRE_VDO2PA_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_VDO2PA_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PA_POS))
+#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM
+#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_POS (8U)
+#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_LEN (2U)
+#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_MSK (((1U << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_POS)
+#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_POS))
+
+/* 0x10 : codec_bus_dec_err */
+#define CODEC_MISC_CODEC_BUS_DEC_ERR_OFFSET (0x10)
+#define CODEC_MISC_REG_DEC_ERR_CLR CODEC_MISC_REG_DEC_ERR_CLR
+#define CODEC_MISC_REG_DEC_ERR_CLR_POS (0U)
+#define CODEC_MISC_REG_DEC_ERR_CLR_LEN (1U)
+#define CODEC_MISC_REG_DEC_ERR_CLR_MSK (((1U << CODEC_MISC_REG_DEC_ERR_CLR_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_CLR_POS)
+#define CODEC_MISC_REG_DEC_ERR_CLR_UMSK (~(((1U << CODEC_MISC_REG_DEC_ERR_CLR_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_CLR_POS))
+#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST CODEC_MISC_REG_DEC_ERR_LATCH_LAST
+#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_POS (1U)
+#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_LEN (1U)
+#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_MSK (((1U << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_POS)
+#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_UMSK (~(((1U << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_POS))
+#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT CODEC_MISC_CODEC_HS_DEC_ERR_LAT
+#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_POS (8U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_LEN (1U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_POS)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_POS))
+#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE CODEC_MISC_CODEC_HS_DEC_ERR_WRITE
+#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_POS (9U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_LEN (1U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_POS)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_POS))
+#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC CODEC_MISC_CODEC_HS_DEC_ERR_SRC
+#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_POS (12U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_LEN (2U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_POS)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_POS))
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ID CODEC_MISC_CODEC_HS_DEC_ERR_ID
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_POS (16U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_LEN (1U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ID_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ID_POS)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ID_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ID_POS))
+
+/* 0x14 : codec_bus_dec_err_addr */
+#define CODEC_MISC_CODEC_BUS_DEC_ERR_ADDR_OFFSET (0x14)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR CODEC_MISC_CODEC_HS_DEC_ERR_ADDR
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_POS (0U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_LEN (32U)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_POS)
+#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_POS))
+
+/* 0x20 : blai_lmtr_rd */
+#define CODEC_MISC_BLAI_LMTR_RD_OFFSET (0x20)
+#define CODEC_MISC_REG_BLAI_RCMD_CNT CODEC_MISC_REG_BLAI_RCMD_CNT
+#define CODEC_MISC_REG_BLAI_RCMD_CNT_POS (0U)
+#define CODEC_MISC_REG_BLAI_RCMD_CNT_LEN (16U)
+#define CODEC_MISC_REG_BLAI_RCMD_CNT_MSK (((1U << CODEC_MISC_REG_BLAI_RCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_CNT_POS)
+#define CODEC_MISC_REG_BLAI_RCMD_CNT_UMSK (~(((1U << CODEC_MISC_REG_BLAI_RCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_CNT_POS))
+#define CODEC_MISC_REG_BLAI_RCMD_MODE CODEC_MISC_REG_BLAI_RCMD_MODE
+#define CODEC_MISC_REG_BLAI_RCMD_MODE_POS (31U)
+#define CODEC_MISC_REG_BLAI_RCMD_MODE_LEN (1U)
+#define CODEC_MISC_REG_BLAI_RCMD_MODE_MSK (((1U << CODEC_MISC_REG_BLAI_RCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_MODE_POS)
+#define CODEC_MISC_REG_BLAI_RCMD_MODE_UMSK (~(((1U << CODEC_MISC_REG_BLAI_RCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_MODE_POS))
+
+/* 0x24 : blai_lmtr_wr */
+#define CODEC_MISC_BLAI_LMTR_WR_OFFSET (0x24)
+#define CODEC_MISC_REG_BLAI_WCMD_CNT CODEC_MISC_REG_BLAI_WCMD_CNT
+#define CODEC_MISC_REG_BLAI_WCMD_CNT_POS (0U)
+#define CODEC_MISC_REG_BLAI_WCMD_CNT_LEN (16U)
+#define CODEC_MISC_REG_BLAI_WCMD_CNT_MSK (((1U << CODEC_MISC_REG_BLAI_WCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_CNT_POS)
+#define CODEC_MISC_REG_BLAI_WCMD_CNT_UMSK (~(((1U << CODEC_MISC_REG_BLAI_WCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_CNT_POS))
+#define CODEC_MISC_REG_BLAI_WCMD_MODE CODEC_MISC_REG_BLAI_WCMD_MODE
+#define CODEC_MISC_REG_BLAI_WCMD_MODE_POS (31U)
+#define CODEC_MISC_REG_BLAI_WCMD_MODE_LEN (1U)
+#define CODEC_MISC_REG_BLAI_WCMD_MODE_MSK (((1U << CODEC_MISC_REG_BLAI_WCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_MODE_POS)
+#define CODEC_MISC_REG_BLAI_WCMD_MODE_UMSK (~(((1U << CODEC_MISC_REG_BLAI_WCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_MODE_POS))
+
+/* 0x28 : id_selection */
+#define CODEC_MISC_ID_SELECTION_OFFSET (0x28)
+#define CODEC_MISC_RG_JENC_ID_SEL CODEC_MISC_RG_JENC_ID_SEL
+#define CODEC_MISC_RG_JENC_ID_SEL_POS (0U)
+#define CODEC_MISC_RG_JENC_ID_SEL_LEN (1U)
+#define CODEC_MISC_RG_JENC_ID_SEL_MSK (((1U << CODEC_MISC_RG_JENC_ID_SEL_LEN) - 1) << CODEC_MISC_RG_JENC_ID_SEL_POS)
+#define CODEC_MISC_RG_JENC_ID_SEL_UMSK (~(((1U << CODEC_MISC_RG_JENC_ID_SEL_LEN) - 1) << CODEC_MISC_RG_JENC_ID_SEL_POS))
+
+/* 0xFC : CODEC_MISC_Dummy */
+#define CODEC_MISC_DUMMY_OFFSET (0xFC)
+#define CODEC_MISC_DUMMY_REG CODEC_MISC_DUMMY_REG
+#define CODEC_MISC_DUMMY_REG_POS (0U)
+#define CODEC_MISC_DUMMY_REG_LEN (32U)
+#define CODEC_MISC_DUMMY_REG_MSK (((1U << CODEC_MISC_DUMMY_REG_LEN) - 1) << CODEC_MISC_DUMMY_REG_POS)
+#define CODEC_MISC_DUMMY_REG_UMSK (~(((1U << CODEC_MISC_DUMMY_REG_LEN) - 1) << CODEC_MISC_DUMMY_REG_POS))
+
+struct codec_misc_reg {
+ /* 0x00 : codec_bus_ctrl */
+ union {
+ struct {
+ uint32_t rg_pclk_force_on : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } codec_bus_ctrl;
+
+ /* 0x04 : codec_qos_ctrl */
+ union {
+ struct {
+ uint32_t reg_jenc_awqos : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_jenc_arqos : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_jdec_awqos : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_jdec_arqos : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg_vdo0_awqos : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_vdo0_arqos : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_vdo1_awqos : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_vdo1_arqos : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_ref_awqos : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_ref_arqos : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg_cnn_awqos : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg_cnn_arqos : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } codec_qos_ctrl;
+
+ /* 0x08 : codec_bus_thre */
+ union {
+ struct {
+ uint32_t reg_x_wthre_blai2sysram : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reg_x_wthre_blai2ext : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_x_wthre_vdo2pb : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t reg_x_wthre_vdo2pa : 2; /* [ 7: 6], r/w, 0x0 */
+ uint32_t reg_x_wthre_vdo2sysram : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } codec_bus_thre;
+
+ /* 0xc reserved */
+ uint8_t RESERVED0xc[20];
+
+ /* 0x10 : codec_bus_dec_err */
+ union {
+ struct
+ {
+ uint32_t reg_dec_err_clr : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_dec_err_latch_last : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t codec_hs_dec_err_lat : 1; /* [ 8], r, 0x0 */
+ uint32_t codec_hs_dec_err_write : 1; /* [ 9], r, 0x0 */
+ uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */
+ uint32_t codec_hs_dec_err_src : 2; /* [13:12], r, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t codec_hs_dec_err_id : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } codec_bus_dec_err;
+
+ /* 0x14 : codec_bus_dec_err_addr */
+ union {
+ struct
+ {
+ uint32_t codec_hs_dec_err_addr : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } codec_bus_dec_err_addr;
+
+ /* 0x18 reserved */
+ uint8_t RESERVED0x18[8];
+
+ /* 0x20 : blai_lmtr_rd */
+ union {
+ struct {
+ uint32_t reg_blai_rcmd_cnt : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */
+ uint32_t reg_blai_rcmd_mode : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } blai_lmtr_rd;
+
+ /* 0x24 : blai_lmtr_wr */
+ union {
+ struct {
+ uint32_t reg_blai_wcmd_cnt : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */
+ uint32_t reg_blai_wcmd_mode : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } blai_lmtr_wr;
+
+ /* 0x28 : id_selection */
+ union {
+ struct {
+ uint32_t rg_jenc_id_sel : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } id_selection;
+
+ /* 0x2c reserved */
+ uint8_t RESERVED0x2c[208];
+
+ /* 0xFC : CODEC_MISC_Dummy */
+ union {
+ struct {
+ uint32_t dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */
+ } BF;
+ uint32_t WORD;
+ } CODEC_MISC_Dummy;
+};
+
+typedef volatile struct codec_misc_reg codec_misc_reg_t;
+
+#endif /* __CODEC_MISC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_ctrl_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_ctrl_reg.h
new file mode 100644
index 00000000..515e14ec
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_ctrl_reg.h
@@ -0,0 +1,942 @@
+/**
+ ******************************************************************************
+ * @file ef_ctrl_reg.h
+ * @version V1.0
+ * @date 2021-07-31
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __EF_CTRL_REG_H__
+#define __EF_CTRL_REG_H__
+
+#include "bl808.h"
+
+/* 0x800 : ef_if_ctrl_0 */
+#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
+#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY
+#define EF_CTRL_EF_IF_0_BUSY_POS (2U)
+#define EF_CTRL_EF_IF_0_BUSY_LEN (1U)
+#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
+#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
+#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW
+#define EF_CTRL_EF_IF_0_RW_POS (3U)
+#define EF_CTRL_EF_IF_0_RW_LEN (1U)
+#define EF_CTRL_EF_IF_0_RW_MSK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
+#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
+#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG
+#define EF_CTRL_EF_IF_0_TRIG_POS (4U)
+#define EF_CTRL_EF_IF_0_TRIG_LEN (1U)
+#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
+#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
+#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN
+#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
+#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG
+#define EF_CTRL_EF_IF_POR_DIG_POS (16U)
+#define EF_CTRL_EF_IF_POR_DIG_LEN (1U)
+#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
+#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
+#define EF_CTRL_EF_PCLK_FORCE_ON EF_CTRL_EF_PCLK_FORCE_ON
+#define EF_CTRL_EF_PCLK_FORCE_ON_POS (17U)
+#define EF_CTRL_EF_PCLK_FORCE_ON_LEN (1U)
+#define EF_CTRL_EF_PCLK_FORCE_ON_MSK (((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS)
+#define EF_CTRL_EF_PCLK_FORCE_ON_UMSK (~(((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS))
+#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN
+#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
+#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT
+#define EF_CTRL_EF_IF_0_INT_POS (20U)
+#define EF_CTRL_EF_IF_0_INT_LEN (1U)
+#define EF_CTRL_EF_IF_0_INT_MSK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
+#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
+#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR
+#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U)
+#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U)
+#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
+#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
+#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET
+#define EF_CTRL_EF_IF_0_INT_SET_POS (22U)
+#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U)
+#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
+#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
+
+/* 0x804 : ef_if_cyc_0 */
+#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804)
+#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY
+#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS))
+#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT
+#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS))
+#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR
+#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS
+#define EF_CTRL_EF_IF_CYC_CS_POS (18U)
+#define EF_CTRL_EF_IF_CYC_CS_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)
+#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS))
+
+/* 0x808 : ef_if_cyc_1 */
+#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808)
+#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI
+#define EF_CTRL_EF_IF_CYC_PI_POS (0U)
+#define EF_CTRL_EF_IF_CYC_PI_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)
+#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS))
+#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP
+#define EF_CTRL_EF_IF_CYC_PP_POS (6U)
+#define EF_CTRL_EF_IF_CYC_PP_LEN (8U)
+#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)
+#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS))
+#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR
+#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS
+#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)
+#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS))
+
+/* 0x80C : ef_if_0_manual */
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C)
+#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS (0U)
+#define EF_CTRL_EF_IF_A_LEN (10U)
+#define EF_CTRL_EF_IF_A_MSK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMSK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS (10U)
+#define EF_CTRL_EF_IF_PD_LEN (1U)
+#define EF_CTRL_EF_IF_PD_MSK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMSK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS (11U)
+#define EF_CTRL_EF_IF_PS_LEN (1U)
+#define EF_CTRL_EF_IF_PS_MSK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMSK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS (12U)
+#define EF_CTRL_EF_IF_STROBE_LEN (1U)
+#define EF_CTRL_EF_IF_STROBE_MSK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS (13U)
+#define EF_CTRL_EF_IF_PGENB_LEN (1U)
+#define EF_CTRL_EF_IF_PGENB_MSK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS (14U)
+#define EF_CTRL_EF_IF_LOAD_LEN (1U)
+#define EF_CTRL_EF_IF_LOAD_MSK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS (15U)
+#define EF_CTRL_EF_IF_CSB_LEN (1U)
+#define EF_CTRL_EF_IF_CSB_MSK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q
+#define EF_CTRL_EF_IF_0_Q_POS (16U)
+#define EF_CTRL_EF_IF_0_Q_LEN (8U)
+#define EF_CTRL_EF_IF_0_Q_MSK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
+#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+
+/* 0x810 : ef_if_0_status */
+#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
+#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS
+#define EF_CTRL_EF_IF_0_STATUS_POS (0U)
+#define EF_CTRL_EF_IF_0_STATUS_LEN (32U)
+#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)
+#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS))
+
+/* 0x814 : ef_if_cfg_0 */
+#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814)
+#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE
+#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)
+#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS))
+#define EF_CTRL_EF_IF_AI_DIS EF_CTRL_EF_IF_AI_DIS
+#define EF_CTRL_EF_IF_AI_DIS_POS (2U)
+#define EF_CTRL_EF_IF_AI_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_AI_DIS_MSK (((1U << EF_CTRL_EF_IF_AI_DIS_LEN) - 1) << EF_CTRL_EF_IF_AI_DIS_POS)
+#define EF_CTRL_EF_IF_AI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_AI_DIS_LEN) - 1) << EF_CTRL_EF_IF_AI_DIS_POS))
+#define EF_CTRL_EF_IF_CPU0_DIS EF_CTRL_EF_IF_CPU0_DIS
+#define EF_CTRL_EF_IF_CPU0_DIS_POS (3U)
+#define EF_CTRL_EF_IF_CPU0_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_CPU0_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU0_DIS_POS)
+#define EF_CTRL_EF_IF_CPU0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU0_DIS_POS))
+#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN
+#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U)
+#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U)
+#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)
+#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS))
+#define EF_CTRL_EF_IF_UART_DIS EF_CTRL_EF_IF_UART_DIS
+#define EF_CTRL_EF_IF_UART_DIS_POS (6U)
+#define EF_CTRL_EF_IF_UART_DIS_LEN (4U)
+#define EF_CTRL_EF_IF_UART_DIS_MSK (((1U << EF_CTRL_EF_IF_UART_DIS_LEN) - 1) << EF_CTRL_EF_IF_UART_DIS_POS)
+#define EF_CTRL_EF_IF_UART_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_UART_DIS_LEN) - 1) << EF_CTRL_EF_IF_UART_DIS_POS))
+#define EF_CTRL_EF_IF_BLE2_DIS EF_CTRL_EF_IF_BLE2_DIS
+#define EF_CTRL_EF_IF_BLE2_DIS_POS (10U)
+#define EF_CTRL_EF_IF_BLE2_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_BLE2_DIS_MSK (((1U << EF_CTRL_EF_IF_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE2_DIS_POS)
+#define EF_CTRL_EF_IF_BLE2_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE2_DIS_POS))
+#define EF_CTRL_EF_IF_M1542_DIS EF_CTRL_EF_IF_M1542_DIS
+#define EF_CTRL_EF_IF_M1542_DIS_POS (11U)
+#define EF_CTRL_EF_IF_M1542_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_M1542_DIS_MSK (((1U << EF_CTRL_EF_IF_M1542_DIS_LEN) - 1) << EF_CTRL_EF_IF_M1542_DIS_POS)
+#define EF_CTRL_EF_IF_M1542_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_M1542_DIS_LEN) - 1) << EF_CTRL_EF_IF_M1542_DIS_POS))
+#define EF_CTRL_EF_IF_SF_KEY_RE_SEL EF_CTRL_EF_IF_SF_KEY_RE_SEL
+#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_POS (12U)
+#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_LEN (2U)
+#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_MSK (((1U << EF_CTRL_EF_IF_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_RE_SEL_POS)
+#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_RE_SEL_POS))
+#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS
+#define EF_CTRL_EF_IF_SDU_DIS_POS (14U)
+#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)
+#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS))
+#define EF_CTRL_EF_IF_BTDM_DIS EF_CTRL_EF_IF_BTDM_DIS
+#define EF_CTRL_EF_IF_BTDM_DIS_POS (15U)
+#define EF_CTRL_EF_IF_BTDM_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_BTDM_DIS_MSK (((1U << EF_CTRL_EF_IF_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_IF_BTDM_DIS_POS)
+#define EF_CTRL_EF_IF_BTDM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_IF_BTDM_DIS_POS))
+#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS
+#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U)
+#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)
+#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS))
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS
+#define EF_CTRL_EF_IF_CAM_DIS_POS (18U)
+#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)
+#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS))
+#define EF_CTRL_EF_IF_M154_DIS EF_CTRL_EF_IF_M154_DIS
+#define EF_CTRL_EF_IF_M154_DIS_POS (19U)
+#define EF_CTRL_EF_IF_M154_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_M154_DIS_MSK (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)
+#define EF_CTRL_EF_IF_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS))
+#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS
+#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U)
+#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)
+#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS))
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS
+#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE
+#define EF_CTRL_EF_IF_DBG_MODE_POS (28U)
+#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U)
+#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)
+#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS))
+
+/* 0x818 : ef_sw_cfg_0 */
+#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818)
+#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE
+#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)
+#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS))
+#define EF_CTRL_EF_SW_AI_DIS EF_CTRL_EF_SW_AI_DIS
+#define EF_CTRL_EF_SW_AI_DIS_POS (2U)
+#define EF_CTRL_EF_SW_AI_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_AI_DIS_MSK (((1U << EF_CTRL_EF_SW_AI_DIS_LEN) - 1) << EF_CTRL_EF_SW_AI_DIS_POS)
+#define EF_CTRL_EF_SW_AI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_AI_DIS_LEN) - 1) << EF_CTRL_EF_SW_AI_DIS_POS))
+#define EF_CTRL_EF_SW_CPU0_DIS EF_CTRL_EF_SW_CPU0_DIS
+#define EF_CTRL_EF_SW_CPU0_DIS_POS (3U)
+#define EF_CTRL_EF_SW_CPU0_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_CPU0_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU0_DIS_POS)
+#define EF_CTRL_EF_SW_CPU0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU0_DIS_POS))
+#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN
+#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U)
+#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U)
+#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)
+#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS))
+#define EF_CTRL_EF_SW_UART_DIS EF_CTRL_EF_SW_UART_DIS
+#define EF_CTRL_EF_SW_UART_DIS_POS (6U)
+#define EF_CTRL_EF_SW_UART_DIS_LEN (4U)
+#define EF_CTRL_EF_SW_UART_DIS_MSK (((1U << EF_CTRL_EF_SW_UART_DIS_LEN) - 1) << EF_CTRL_EF_SW_UART_DIS_POS)
+#define EF_CTRL_EF_SW_UART_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_UART_DIS_LEN) - 1) << EF_CTRL_EF_SW_UART_DIS_POS))
+#define EF_CTRL_EF_SW_BLE2_DIS EF_CTRL_EF_SW_BLE2_DIS
+#define EF_CTRL_EF_SW_BLE2_DIS_POS (10U)
+#define EF_CTRL_EF_SW_BLE2_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_BLE2_DIS_MSK (((1U << EF_CTRL_EF_SW_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE2_DIS_POS)
+#define EF_CTRL_EF_SW_BLE2_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE2_DIS_POS))
+#define EF_CTRL_EF_SW_M1542_DIS EF_CTRL_EF_SW_M1542_DIS
+#define EF_CTRL_EF_SW_M1542_DIS_POS (11U)
+#define EF_CTRL_EF_SW_M1542_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_M1542_DIS_MSK (((1U << EF_CTRL_EF_SW_M1542_DIS_LEN) - 1) << EF_CTRL_EF_SW_M1542_DIS_POS)
+#define EF_CTRL_EF_SW_M1542_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_M1542_DIS_LEN) - 1) << EF_CTRL_EF_SW_M1542_DIS_POS))
+#define EF_CTRL_EF_SW_SF_KEY_RE_SEL EF_CTRL_EF_SW_SF_KEY_RE_SEL
+#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_POS (12U)
+#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_LEN (2U)
+#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_MSK (((1U << EF_CTRL_EF_SW_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_RE_SEL_POS)
+#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_UMSK (~(((1U << EF_CTRL_EF_SW_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_RE_SEL_POS))
+#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS
+#define EF_CTRL_EF_SW_SDU_DIS_POS (14U)
+#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)
+#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS))
+#define EF_CTRL_EF_SW_BTDM_DIS EF_CTRL_EF_SW_BTDM_DIS
+#define EF_CTRL_EF_SW_BTDM_DIS_POS (15U)
+#define EF_CTRL_EF_SW_BTDM_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_BTDM_DIS_MSK (((1U << EF_CTRL_EF_SW_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_SW_BTDM_DIS_POS)
+#define EF_CTRL_EF_SW_BTDM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_SW_BTDM_DIS_POS))
+#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS
+#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U)
+#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)
+#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS))
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS
+#define EF_CTRL_EF_SW_CAM_DIS_POS (18U)
+#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)
+#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS))
+#define EF_CTRL_EF_SW_M154_DIS EF_CTRL_EF_SW_M154_DIS
+#define EF_CTRL_EF_SW_M154_DIS_POS (19U)
+#define EF_CTRL_EF_SW_M154_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_M154_DIS_MSK (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)
+#define EF_CTRL_EF_SW_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS))
+#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS
+#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U)
+#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)
+#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS))
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS
+#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE
+#define EF_CTRL_EF_SW_DBG_MODE_POS (28U)
+#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U)
+#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)
+#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS))
+
+/* 0x81C : ef_reserved */
+#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
+#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED
+#define EF_CTRL_EF_RESERVED_POS (0U)
+#define EF_CTRL_EF_RESERVED_LEN (32U)
+#define EF_CTRL_EF_RESERVED_MSK (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)
+#define EF_CTRL_EF_RESERVED_UMSK (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS))
+
+/* 0x820 : ef_if_sw_usage_0 */
+#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x820)
+#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0
+#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)
+#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS))
+
+/* 0x824 : ef_if_sw_usage_1 */
+#define EF_CTRL_EF_IF_SW_USAGE_1_OFFSET (0x824)
+#define EF_CTRL_EF_IF_SW_USAGE_1 EF_CTRL_EF_IF_SW_USAGE_1
+#define EF_CTRL_EF_IF_SW_USAGE_1_POS (0U)
+#define EF_CTRL_EF_IF_SW_USAGE_1_LEN (32U)
+#define EF_CTRL_EF_IF_SW_USAGE_1_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS)
+#define EF_CTRL_EF_IF_SW_USAGE_1_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS))
+
+/* 0x900 : ef_if_ctrl_1 */
+#define EF_CTRL_EF_IF_CTRL_1_OFFSET (0x900)
+#define EF_CTRL_EF_IF_1_BUSY EF_CTRL_EF_IF_1_BUSY
+#define EF_CTRL_EF_IF_1_BUSY_POS (2U)
+#define EF_CTRL_EF_IF_1_BUSY_LEN (1U)
+#define EF_CTRL_EF_IF_1_BUSY_MSK (((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS)
+#define EF_CTRL_EF_IF_1_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS))
+#define EF_CTRL_EF_IF_1_RW EF_CTRL_EF_IF_1_RW
+#define EF_CTRL_EF_IF_1_RW_POS (3U)
+#define EF_CTRL_EF_IF_1_RW_LEN (1U)
+#define EF_CTRL_EF_IF_1_RW_MSK (((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS)
+#define EF_CTRL_EF_IF_1_RW_UMSK (~(((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS))
+#define EF_CTRL_EF_IF_1_TRIG EF_CTRL_EF_IF_1_TRIG
+#define EF_CTRL_EF_IF_1_TRIG_POS (4U)
+#define EF_CTRL_EF_IF_1_TRIG_LEN (1U)
+#define EF_CTRL_EF_IF_1_TRIG_MSK (((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS)
+#define EF_CTRL_EF_IF_1_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS))
+#define EF_CTRL_EF_IF_1_MANUAL_EN EF_CTRL_EF_IF_1_MANUAL_EN
+#define EF_CTRL_EF_IF_1_MANUAL_EN_POS (5U)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_LEN (1U)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_1_CYC_MODIFY EF_CTRL_EF_IF_1_CYC_MODIFY
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_POS (6U)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_LEN (1U)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS))
+#define EF_CTRL_EF_IF_1_INT EF_CTRL_EF_IF_1_INT
+#define EF_CTRL_EF_IF_1_INT_POS (20U)
+#define EF_CTRL_EF_IF_1_INT_LEN (1U)
+#define EF_CTRL_EF_IF_1_INT_MSK (((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS)
+#define EF_CTRL_EF_IF_1_INT_UMSK (~(((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS))
+#define EF_CTRL_EF_IF_1_INT_CLR EF_CTRL_EF_IF_1_INT_CLR
+#define EF_CTRL_EF_IF_1_INT_CLR_POS (21U)
+#define EF_CTRL_EF_IF_1_INT_CLR_LEN (1U)
+#define EF_CTRL_EF_IF_1_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS)
+#define EF_CTRL_EF_IF_1_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS))
+#define EF_CTRL_EF_IF_1_INT_SET EF_CTRL_EF_IF_1_INT_SET
+#define EF_CTRL_EF_IF_1_INT_SET_POS (22U)
+#define EF_CTRL_EF_IF_1_INT_SET_LEN (1U)
+#define EF_CTRL_EF_IF_1_INT_SET_MSK (((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS)
+#define EF_CTRL_EF_IF_1_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS))
+
+/* 0x904 : ef_if_1_manual */
+#define EF_CTRL_EF_IF_1_MANUAL_OFFSET (0x904)
+#define EF_CTRL_EF_IF_1_Q EF_CTRL_EF_IF_1_Q
+#define EF_CTRL_EF_IF_1_Q_POS (16U)
+#define EF_CTRL_EF_IF_1_Q_LEN (8U)
+#define EF_CTRL_EF_IF_1_Q_MSK (((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS)
+#define EF_CTRL_EF_IF_1_Q_UMSK (~(((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS))
+
+/* 0x908 : ef_if_1_status */
+#define EF_CTRL_EF_IF_1_STATUS_OFFSET (0x908)
+#define EF_CTRL_EF_IF_1_STATUS EF_CTRL_EF_IF_1_STATUS
+#define EF_CTRL_EF_IF_1_STATUS_POS (0U)
+#define EF_CTRL_EF_IF_1_STATUS_LEN (32U)
+#define EF_CTRL_EF_IF_1_STATUS_MSK (((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS)
+#define EF_CTRL_EF_IF_1_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS))
+
+/* 0x910 : ef_if_ctrl_2 */
+#define EF_CTRL_EF_IF_CTRL_2_OFFSET (0x910)
+
+/* 0x914 : ef_if_2_manual */
+#define EF_CTRL_EF_IF_2_MANUAL_OFFSET (0x914)
+
+/* 0x918 : ef_if_2_status */
+#define EF_CTRL_EF_IF_2_STATUS_OFFSET (0x918)
+
+/* 0xA00 : ef_crc_ctrl_0 */
+#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00)
+#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY
+#define EF_CTRL_EF_CRC_BUSY_POS (0U)
+#define EF_CTRL_EF_CRC_BUSY_LEN (1U)
+#define EF_CTRL_EF_CRC_BUSY_MSK (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)
+#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS))
+#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG
+#define EF_CTRL_EF_CRC_TRIG_POS (1U)
+#define EF_CTRL_EF_CRC_TRIG_LEN (1U)
+#define EF_CTRL_EF_CRC_TRIG_MSK (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)
+#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS))
+#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN
+#define EF_CTRL_EF_CRC_EN_POS (2U)
+#define EF_CTRL_EF_CRC_EN_LEN (1U)
+#define EF_CTRL_EF_CRC_EN_MSK (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)
+#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS))
+#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE
+#define EF_CTRL_EF_CRC_MODE_POS (3U)
+#define EF_CTRL_EF_CRC_MODE_LEN (1U)
+#define EF_CTRL_EF_CRC_MODE_MSK (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)
+#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS))
+#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR
+#define EF_CTRL_EF_CRC_ERROR_POS (4U)
+#define EF_CTRL_EF_CRC_ERROR_LEN (1U)
+#define EF_CTRL_EF_CRC_ERROR_MSK (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)
+#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS))
+#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT
+#define EF_CTRL_EF_CRC_INT_POS (8U)
+#define EF_CTRL_EF_CRC_INT_LEN (1U)
+#define EF_CTRL_EF_CRC_INT_MSK (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)
+#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS))
+#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR
+#define EF_CTRL_EF_CRC_INT_CLR_POS (9U)
+#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U)
+#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)
+#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS))
+#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET
+#define EF_CTRL_EF_CRC_INT_SET_POS (10U)
+#define EF_CTRL_EF_CRC_INT_SET_LEN (1U)
+#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)
+#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS))
+#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK
+#define EF_CTRL_EF_CRC_LOCK_POS (11U)
+#define EF_CTRL_EF_CRC_LOCK_LEN (1U)
+#define EF_CTRL_EF_CRC_LOCK_MSK (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)
+#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS))
+#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N
+#define EF_CTRL_EF_CRC_SLP_N_POS (16U)
+#define EF_CTRL_EF_CRC_SLP_N_LEN (16U)
+#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)
+#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS))
+
+/* 0xA04 : ef_crc_ctrl_1 */
+#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04)
+#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN
+#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS))
+
+/* 0xA08 : ef_crc_ctrl_2 */
+#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08)
+#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN
+#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS))
+
+/* 0xA0C : ef_crc_ctrl_3 */
+#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
+#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV
+#define EF_CTRL_EF_CRC_IV_POS (0U)
+#define EF_CTRL_EF_CRC_IV_LEN (32U)
+#define EF_CTRL_EF_CRC_IV_MSK (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)
+#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS))
+
+/* 0xA10 : ef_crc_ctrl_4 */
+#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
+#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN
+#define EF_CTRL_EF_CRC_GOLDEN_POS (0U)
+#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U)
+#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)
+#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS))
+
+/* 0xA14 : ef_crc_ctrl_5 */
+#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
+#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT
+#define EF_CTRL_EF_CRC_DOUT_POS (0U)
+#define EF_CTRL_EF_CRC_DOUT_LEN (32U)
+#define EF_CTRL_EF_CRC_DOUT_MSK (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)
+#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS))
+
+struct ef_ctrl_reg {
+ /* 0x0 reserved */
+ uint8_t RESERVED0x0[2048];
+
+ /* 0x800 : ef_if_ctrl_0 */
+ union {
+ struct {
+ uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */
+ uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */
+ uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */
+ uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */
+ uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */
+ uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */
+ uint32_t ef_pclk_force_on : 1; /* [ 17], r/w, 0x0 */
+ uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */
+ uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */
+ uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */
+ uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */
+ uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_ctrl_0;
+
+ /* 0x804 : ef_if_cyc_0 */
+ union {
+ struct {
+ uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */
+ uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */
+ uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */
+ uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */
+ uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_cyc_0;
+
+ /* 0x808 : ef_if_cyc_1 */
+ union {
+ struct {
+ uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */
+ uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */
+ uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */
+ uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */
+ uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_cyc_1;
+
+ /* 0x80C : ef_if_0_manual */
+ union {
+ struct {
+ uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */
+ uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */
+ uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */
+ uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */
+ uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */
+ uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */
+ uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */
+ uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_0_manual;
+
+ /* 0x810 : ef_if_0_status */
+ union {
+ struct {
+ uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_0_status;
+
+ /* 0x814 : ef_if_cfg_0 */
+ union {
+ struct {
+ uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */
+ uint32_t ef_if_ai_dis : 1; /* [ 2], r, 0x0 */
+ uint32_t ef_if_cpu0_dis : 1; /* [ 3], r, 0x0 */
+ uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */
+ uint32_t ef_if_uart_dis : 4; /* [ 9: 6], r, 0x0 */
+ uint32_t ef_if_ble2_dis : 1; /* [ 10], r, 0x0 */
+ uint32_t ef_if_m1542_dis : 1; /* [ 11], r, 0x0 */
+ uint32_t ef_if_sf_key_re_sel : 2; /* [13:12], r, 0x0 */
+ uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */
+ uint32_t ef_if_btdm_dis : 1; /* [ 15], r, 0x0 */
+ uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */
+ uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */
+ uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */
+ uint32_t ef_if_m154_dis : 1; /* [ 19], r, 0x0 */
+ uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */
+ uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */
+ uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */
+ uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */
+ uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */
+ uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */
+ uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_cfg_0;
+
+ /* 0x818 : ef_sw_cfg_0 */
+ union {
+ struct {
+ uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t ef_sw_ai_dis : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ef_sw_cpu0_dis : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t ef_sw_uart_dis : 4; /* [ 9: 6], r/w, 0x0 */
+ uint32_t ef_sw_ble2_dis : 1; /* [ 10], r/w, 0x0 */
+ uint32_t ef_sw_m1542_dis : 1; /* [ 11], r/w, 0x0 */
+ uint32_t ef_sw_sf_key_re_sel : 2; /* [13:12], r/w, 0x0 */
+ uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */
+ uint32_t ef_sw_btdm_dis : 1; /* [ 15], r/w, 0x0 */
+ uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */
+ uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */
+ uint32_t ef_sw_m154_dis : 1; /* [ 19], r/w, 0x0 */
+ uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */
+ uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */
+ uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */
+ uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */
+ uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */
+ uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
+ uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_sw_cfg_0;
+
+ /* 0x81C : ef_reserved */
+ union {
+ struct {
+ uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */
+ } BF;
+ uint32_t WORD;
+ } ef_reserved;
+
+ /* 0x820 : ef_if_sw_usage_0 */
+ union {
+ struct {
+ uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_sw_usage_0;
+
+ /* 0x824 : ef_if_sw_usage_1 */
+ union {
+ struct {
+ uint32_t ef_if_sw_usage_1 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_sw_usage_1;
+
+ /* 0x828 reserved */
+ uint8_t RESERVED0x828[216];
+
+ /* 0x900 : ef_if_ctrl_1 */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t ef_if_1_busy : 1; /* [ 2], r, 0x0 */
+ uint32_t ef_if_1_rw : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ef_if_1_trig : 1; /* [ 4], r/w, 0x0 */
+ uint32_t ef_if_1_manual_en : 1; /* [ 5], r/w, 0x0 */
+ uint32_t ef_if_1_cyc_modify : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7_19 : 13; /* [19: 7], rsvd, 0x0 */
+ uint32_t ef_if_1_int : 1; /* [ 20], r, 0x0 */
+ uint32_t ef_if_1_int_clr : 1; /* [ 21], r/w, 0x1 */
+ uint32_t ef_if_1_int_set : 1; /* [ 22], r/w, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_ctrl_1;
+
+ /* 0x904 : ef_if_1_manual */
+ union {
+ struct {
+ uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */
+ uint32_t ef_if_1_q : 8; /* [23:16], r, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_1_manual;
+
+ /* 0x908 : ef_if_1_status */
+ union {
+ struct {
+ uint32_t ef_if_1_status : 32; /* [31: 0], r, 0xe400 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_1_status;
+
+ /* 0x90c reserved */
+ uint8_t RESERVED0x90c[4];
+
+ /* 0x910 : ef_if_ctrl_2 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_ctrl_2;
+
+ /* 0x914 : ef_if_2_manual */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_2_manual;
+
+ /* 0x918 : ef_if_2_status */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_if_2_status;
+
+ /* 0x91c reserved */
+ uint8_t RESERVED0x91c[228];
+
+ /* 0xA00 : ef_crc_ctrl_0 */
+ union {
+ struct {
+ uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */
+ uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */
+ uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */
+ uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */
+ uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */
+ uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */
+ uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */
+ uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */
+ uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */
+ uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */
+ } BF;
+ uint32_t WORD;
+ } ef_crc_ctrl_0;
+
+ /* 0xA04 : ef_crc_ctrl_1 */
+ union {
+ struct {
+ uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */
+ } BF;
+ uint32_t WORD;
+ } ef_crc_ctrl_1;
+
+ /* 0xA08 : ef_crc_ctrl_2 */
+ union {
+ struct {
+ uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */
+ } BF;
+ uint32_t WORD;
+ } ef_crc_ctrl_2;
+
+ /* 0xA0C : ef_crc_ctrl_3 */
+ union {
+ struct {
+ uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */
+ } BF;
+ uint32_t WORD;
+ } ef_crc_ctrl_3;
+
+ /* 0xA10 : ef_crc_ctrl_4 */
+ union {
+ struct {
+ uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */
+ } BF;
+ uint32_t WORD;
+ } ef_crc_ctrl_4;
+
+ /* 0xA14 : ef_crc_ctrl_5 */
+ union {
+ struct {
+ uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */
+ } BF;
+ uint32_t WORD;
+ } ef_crc_ctrl_5;
+};
+
+typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t;
+
+#endif /* __EF_CTRL_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_data_0_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_data_0_reg.h
new file mode 100644
index 00000000..0708eb1a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_data_0_reg.h
@@ -0,0 +1,797 @@
+/**
+ ******************************************************************************
+ * @file ef_data_0_reg.h
+ * @version V1.0
+ * @date 2021-07-31
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __EF_DATA_0_REG_H__
+#define __EF_DATA_0_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : ef_cfg_0 */
+#define EF_DATA_0_EF_CFG_0_OFFSET (0x0)
+#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE
+#define EF_DATA_0_EF_SF_AES_MODE_POS (0U)
+#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U)
+#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)
+#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS))
+#define EF_DATA_0_EF_AI_DIS EF_DATA_0_EF_AI_DIS
+#define EF_DATA_0_EF_AI_DIS_POS (2U)
+#define EF_DATA_0_EF_AI_DIS_LEN (1U)
+#define EF_DATA_0_EF_AI_DIS_MSK (((1U << EF_DATA_0_EF_AI_DIS_LEN) - 1) << EF_DATA_0_EF_AI_DIS_POS)
+#define EF_DATA_0_EF_AI_DIS_UMSK (~(((1U << EF_DATA_0_EF_AI_DIS_LEN) - 1) << EF_DATA_0_EF_AI_DIS_POS))
+#define EF_DATA_0_EF_CPU0_DIS EF_DATA_0_EF_CPU0_DIS
+#define EF_DATA_0_EF_CPU0_DIS_POS (3U)
+#define EF_DATA_0_EF_CPU0_DIS_LEN (1U)
+#define EF_DATA_0_EF_CPU0_DIS_MSK (((1U << EF_DATA_0_EF_CPU0_DIS_LEN) - 1) << EF_DATA_0_EF_CPU0_DIS_POS)
+#define EF_DATA_0_EF_CPU0_DIS_UMSK (~(((1U << EF_DATA_0_EF_CPU0_DIS_LEN) - 1) << EF_DATA_0_EF_CPU0_DIS_POS))
+#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN
+#define EF_DATA_0_EF_SBOOT_EN_POS (4U)
+#define EF_DATA_0_EF_SBOOT_EN_LEN (2U)
+#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)
+#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS))
+#define EF_DATA_0_EF_UART_DIS EF_DATA_0_EF_UART_DIS
+#define EF_DATA_0_EF_UART_DIS_POS (6U)
+#define EF_DATA_0_EF_UART_DIS_LEN (4U)
+#define EF_DATA_0_EF_UART_DIS_MSK (((1U << EF_DATA_0_EF_UART_DIS_LEN) - 1) << EF_DATA_0_EF_UART_DIS_POS)
+#define EF_DATA_0_EF_UART_DIS_UMSK (~(((1U << EF_DATA_0_EF_UART_DIS_LEN) - 1) << EF_DATA_0_EF_UART_DIS_POS))
+#define EF_DATA_0_EF_NO_XTAL EF_DATA_0_EF_NO_XTAL
+#define EF_DATA_0_EF_NO_XTAL_POS (10U)
+#define EF_DATA_0_EF_NO_XTAL_LEN (1U)
+#define EF_DATA_0_EF_NO_XTAL_MSK (((1U << EF_DATA_0_EF_NO_XTAL_LEN) - 1) << EF_DATA_0_EF_NO_XTAL_POS)
+#define EF_DATA_0_EF_NO_XTAL_UMSK (~(((1U << EF_DATA_0_EF_NO_XTAL_LEN) - 1) << EF_DATA_0_EF_NO_XTAL_POS))
+#define EF_DATA_0_EF_FORCE_NO_TRIM EF_DATA_0_EF_FORCE_NO_TRIM
+#define EF_DATA_0_EF_FORCE_NO_TRIM_POS (11U)
+#define EF_DATA_0_EF_FORCE_NO_TRIM_LEN (1U)
+#define EF_DATA_0_EF_FORCE_NO_TRIM_MSK (((1U << EF_DATA_0_EF_FORCE_NO_TRIM_LEN) - 1) << EF_DATA_0_EF_FORCE_NO_TRIM_POS)
+#define EF_DATA_0_EF_FORCE_NO_TRIM_UMSK (~(((1U << EF_DATA_0_EF_FORCE_NO_TRIM_LEN) - 1) << EF_DATA_0_EF_FORCE_NO_TRIM_POS))
+#define EF_DATA_0_EF_SF_KEY_RE_SEL EF_DATA_0_EF_SF_KEY_RE_SEL
+#define EF_DATA_0_EF_SF_KEY_RE_SEL_POS (12U)
+#define EF_DATA_0_EF_SF_KEY_RE_SEL_LEN (2U)
+#define EF_DATA_0_EF_SF_KEY_RE_SEL_MSK (((1U << EF_DATA_0_EF_SF_KEY_RE_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_RE_SEL_POS)
+#define EF_DATA_0_EF_SF_KEY_RE_SEL_UMSK (~(((1U << EF_DATA_0_EF_SF_KEY_RE_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_RE_SEL_POS))
+#define EF_DATA_0_EF_SDU_DIS EF_DATA_0_EF_SDU_DIS
+#define EF_DATA_0_EF_SDU_DIS_POS (14U)
+#define EF_DATA_0_EF_SDU_DIS_LEN (1U)
+#define EF_DATA_0_EF_SDU_DIS_MSK (((1U << EF_DATA_0_EF_SDU_DIS_LEN) - 1) << EF_DATA_0_EF_SDU_DIS_POS)
+#define EF_DATA_0_EF_SDU_DIS_UMSK (~(((1U << EF_DATA_0_EF_SDU_DIS_LEN) - 1) << EF_DATA_0_EF_SDU_DIS_POS))
+#define EF_DATA_0_EF_BTDM_DIS EF_DATA_0_EF_BTDM_DIS
+#define EF_DATA_0_EF_BTDM_DIS_POS (15U)
+#define EF_DATA_0_EF_BTDM_DIS_LEN (1U)
+#define EF_DATA_0_EF_BTDM_DIS_MSK (((1U << EF_DATA_0_EF_BTDM_DIS_LEN) - 1) << EF_DATA_0_EF_BTDM_DIS_POS)
+#define EF_DATA_0_EF_BTDM_DIS_UMSK (~(((1U << EF_DATA_0_EF_BTDM_DIS_LEN) - 1) << EF_DATA_0_EF_BTDM_DIS_POS))
+#define EF_DATA_0_EF_WIFI_DIS EF_DATA_0_EF_WIFI_DIS
+#define EF_DATA_0_EF_WIFI_DIS_POS (16U)
+#define EF_DATA_0_EF_WIFI_DIS_LEN (1U)
+#define EF_DATA_0_EF_WIFI_DIS_MSK (((1U << EF_DATA_0_EF_WIFI_DIS_LEN) - 1) << EF_DATA_0_EF_WIFI_DIS_POS)
+#define EF_DATA_0_EF_WIFI_DIS_UMSK (~(((1U << EF_DATA_0_EF_WIFI_DIS_LEN) - 1) << EF_DATA_0_EF_WIFI_DIS_POS))
+#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN
+#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U)
+#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U)
+#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)
+#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS))
+#define EF_DATA_0_EF_CAM_DIS EF_DATA_0_EF_CAM_DIS
+#define EF_DATA_0_EF_CAM_DIS_POS (18U)
+#define EF_DATA_0_EF_CAM_DIS_LEN (1U)
+#define EF_DATA_0_EF_CAM_DIS_MSK (((1U << EF_DATA_0_EF_CAM_DIS_LEN) - 1) << EF_DATA_0_EF_CAM_DIS_POS)
+#define EF_DATA_0_EF_CAM_DIS_UMSK (~(((1U << EF_DATA_0_EF_CAM_DIS_LEN) - 1) << EF_DATA_0_EF_CAM_DIS_POS))
+#define EF_DATA_0_EF_M154_DIS EF_DATA_0_EF_M154_DIS
+#define EF_DATA_0_EF_M154_DIS_POS (19U)
+#define EF_DATA_0_EF_M154_DIS_LEN (1U)
+#define EF_DATA_0_EF_M154_DIS_MSK (((1U << EF_DATA_0_EF_M154_DIS_LEN) - 1) << EF_DATA_0_EF_M154_DIS_POS)
+#define EF_DATA_0_EF_M154_DIS_UMSK (~(((1U << EF_DATA_0_EF_M154_DIS_LEN) - 1) << EF_DATA_0_EF_M154_DIS_POS))
+#define EF_DATA_0_EF_CPU1_DIS EF_DATA_0_EF_CPU1_DIS
+#define EF_DATA_0_EF_CPU1_DIS_POS (20U)
+#define EF_DATA_0_EF_CPU1_DIS_LEN (1U)
+#define EF_DATA_0_EF_CPU1_DIS_MSK (((1U << EF_DATA_0_EF_CPU1_DIS_LEN) - 1) << EF_DATA_0_EF_CPU1_DIS_POS)
+#define EF_DATA_0_EF_CPU1_DIS_UMSK (~(((1U << EF_DATA_0_EF_CPU1_DIS_LEN) - 1) << EF_DATA_0_EF_CPU1_DIS_POS))
+#define EF_DATA_0_EF_CPU_RST_DBG_DIS EF_DATA_0_EF_CPU_RST_DBG_DIS
+#define EF_DATA_0_EF_CPU_RST_DBG_DIS_POS (21U)
+#define EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN (1U)
+#define EF_DATA_0_EF_CPU_RST_DBG_DIS_MSK (((1U << EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_CPU_RST_DBG_DIS_POS)
+#define EF_DATA_0_EF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_CPU_RST_DBG_DIS_POS))
+#define EF_DATA_0_EF_SE_DBG_DIS EF_DATA_0_EF_SE_DBG_DIS
+#define EF_DATA_0_EF_SE_DBG_DIS_POS (22U)
+#define EF_DATA_0_EF_SE_DBG_DIS_LEN (1U)
+#define EF_DATA_0_EF_SE_DBG_DIS_MSK (((1U << EF_DATA_0_EF_SE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_SE_DBG_DIS_POS)
+#define EF_DATA_0_EF_SE_DBG_DIS_UMSK (~(((1U << EF_DATA_0_EF_SE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_SE_DBG_DIS_POS))
+#define EF_DATA_0_EF_EFUSE_DBG_DIS EF_DATA_0_EF_EFUSE_DBG_DIS
+#define EF_DATA_0_EF_EFUSE_DBG_DIS_POS (23U)
+#define EF_DATA_0_EF_EFUSE_DBG_DIS_LEN (1U)
+#define EF_DATA_0_EF_EFUSE_DBG_DIS_MSK (((1U << EF_DATA_0_EF_EFUSE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_EFUSE_DBG_DIS_POS)
+#define EF_DATA_0_EF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_DATA_0_EF_EFUSE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_EFUSE_DBG_DIS_POS))
+#define EF_DATA_0_EF_DBG_JTAG_1_DIS EF_DATA_0_EF_DBG_JTAG_1_DIS
+#define EF_DATA_0_EF_DBG_JTAG_1_DIS_POS (24U)
+#define EF_DATA_0_EF_DBG_JTAG_1_DIS_LEN (2U)
+#define EF_DATA_0_EF_DBG_JTAG_1_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_1_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_1_DIS_POS)
+#define EF_DATA_0_EF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_1_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_1_DIS_POS))
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U)
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U)
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS))
+#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE
+#define EF_DATA_0_EF_DBG_MODE_POS (28U)
+#define EF_DATA_0_EF_DBG_MODE_LEN (4U)
+#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)
+#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS))
+
+/* 0x4 : ef_dbg_pwd_low */
+#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4)
+#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW
+#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U)
+#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U)
+#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)
+#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS))
+
+/* 0x8 : ef_dbg_pwd_high */
+#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8)
+#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH
+#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U)
+#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U)
+#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)
+#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS))
+
+/* 0xC : ef_dbg_pwd2_low */
+#define EF_DATA_0_EF_DBG_PWD2_LOW_OFFSET (0xC)
+#define EF_DATA_0_EF_DBG_PWD2_LOW EF_DATA_0_EF_DBG_PWD2_LOW
+#define EF_DATA_0_EF_DBG_PWD2_LOW_POS (0U)
+#define EF_DATA_0_EF_DBG_PWD2_LOW_LEN (32U)
+#define EF_DATA_0_EF_DBG_PWD2_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD2_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_LOW_POS)
+#define EF_DATA_0_EF_DBG_PWD2_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD2_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_LOW_POS))
+
+/* 0x10 : ef_dbg_pwd2_high */
+#define EF_DATA_0_EF_DBG_PWD2_HIGH_OFFSET (0x10)
+#define EF_DATA_0_EF_DBG_PWD2_HIGH EF_DATA_0_EF_DBG_PWD2_HIGH
+#define EF_DATA_0_EF_DBG_PWD2_HIGH_POS (0U)
+#define EF_DATA_0_EF_DBG_PWD2_HIGH_LEN (32U)
+#define EF_DATA_0_EF_DBG_PWD2_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD2_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_HIGH_POS)
+#define EF_DATA_0_EF_DBG_PWD2_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD2_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_HIGH_POS))
+
+/* 0x14 : ef_wifi_mac_low */
+#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14)
+#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW
+#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U)
+#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U)
+#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)
+#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS))
+
+/* 0x18 : ef_wifi_mac_high */
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS))
+
+/* 0x1C : ef_key_slot_0_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS))
+
+/* 0x20 : ef_key_slot_0_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS))
+
+/* 0x24 : ef_key_slot_0_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS))
+
+/* 0x28 : ef_key_slot_0_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS))
+
+/* 0x2C : ef_key_slot_1_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS))
+
+/* 0x30 : ef_key_slot_1_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS))
+
+/* 0x34 : ef_key_slot_1_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS))
+
+/* 0x38 : ef_key_slot_1_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS))
+
+/* 0x3C : ef_key_slot_2_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS))
+
+/* 0x40 : ef_key_slot_2_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS))
+
+/* 0x44 : ef_key_slot_2_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS))
+
+/* 0x48 : ef_key_slot_2_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS))
+
+/* 0x4C : ef_key_slot_3_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS))
+
+/* 0x50 : ef_key_slot_3_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS))
+
+/* 0x54 : ef_key_slot_3_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS))
+
+/* 0x58 : ef_key_slot_3_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS))
+
+/* 0x5C : ef_sw_usage_0 */
+#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x5C)
+#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0
+#define EF_DATA_0_EF_SW_USAGE_0_POS (0U)
+#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U)
+#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)
+#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS))
+
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (8U)
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U)
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS))
+
+/* 0x60 : ef_sw_usage_1 */
+#define EF_DATA_0_EF_SW_USAGE_1_OFFSET (0x60)
+#define EF_DATA_0_EF_SW_USAGE_1 EF_DATA_0_EF_SW_USAGE_1
+#define EF_DATA_0_EF_SW_USAGE_1_POS (0U)
+#define EF_DATA_0_EF_SW_USAGE_1_LEN (32U)
+#define EF_DATA_0_EF_SW_USAGE_1_MSK (((1U << EF_DATA_0_EF_SW_USAGE_1_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_1_POS)
+#define EF_DATA_0_EF_SW_USAGE_1_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_1_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_1_POS))
+
+/* 0x64 : ef_sw_usage_2 */
+#define EF_DATA_0_EF_SW_USAGE_2_OFFSET (0x64)
+#define EF_DATA_0_EF_SW_USAGE_2 EF_DATA_0_EF_SW_USAGE_2
+#define EF_DATA_0_EF_SW_USAGE_2_POS (0U)
+#define EF_DATA_0_EF_SW_USAGE_2_LEN (32U)
+#define EF_DATA_0_EF_SW_USAGE_2_MSK (((1U << EF_DATA_0_EF_SW_USAGE_2_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_2_POS)
+#define EF_DATA_0_EF_SW_USAGE_2_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_2_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_2_POS))
+
+/* 0x68 : ef_sw_usage_3 */
+#define EF_DATA_0_EF_SW_USAGE_3_OFFSET (0x68)
+#define EF_DATA_0_EF_SW_USAGE_3 EF_DATA_0_EF_SW_USAGE_3
+#define EF_DATA_0_EF_SW_USAGE_3_POS (0U)
+#define EF_DATA_0_EF_SW_USAGE_3_LEN (32U)
+#define EF_DATA_0_EF_SW_USAGE_3_MSK (((1U << EF_DATA_0_EF_SW_USAGE_3_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_3_POS)
+#define EF_DATA_0_EF_SW_USAGE_3_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_3_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_3_POS))
+
+/* 0x6C : ef_key_slot_11_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_11_W0_OFFSET (0x6C)
+#define EF_DATA_0_EF_KEY_SLOT_11_W0 EF_DATA_0_EF_KEY_SLOT_11_W0
+#define EF_DATA_0_EF_KEY_SLOT_11_W0_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W0_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_11_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W0_POS))
+
+/* 0x70 : ef_key_slot_11_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET (0x70)
+#define EF_DATA_0_EF_KEY_SLOT_11_W1 EF_DATA_0_EF_KEY_SLOT_11_W1
+#define EF_DATA_0_EF_KEY_SLOT_11_W1_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W1_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_11_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W1_POS))
+
+/* 0x74 : ef_key_slot_11_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET (0x74)
+#define EF_DATA_0_EF_KEY_SLOT_11_W2 EF_DATA_0_EF_KEY_SLOT_11_W2
+#define EF_DATA_0_EF_KEY_SLOT_11_W2_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W2_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_11_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W2_POS))
+
+/* 0x78 : ef_key_slot_11_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_11_W3_OFFSET (0x78)
+#define EF_DATA_0_EF_KEY_SLOT_11_W3 EF_DATA_0_EF_KEY_SLOT_11_W3
+#define EF_DATA_0_EF_KEY_SLOT_11_W3_POS (0U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W3_LEN (32U)
+#define EF_DATA_0_EF_KEY_SLOT_11_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_11_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W3_POS))
+
+/* 0x7C : ef_data_0_lock */
+#define EF_DATA_0_LOCK_OFFSET (0x7C)
+#define EF_DATA_0_EF_SEC_LIFECYCLE EF_DATA_0_EF_SEC_LIFECYCLE
+#define EF_DATA_0_EF_SEC_LIFECYCLE_POS (0U)
+#define EF_DATA_0_EF_SEC_LIFECYCLE_LEN (4U)
+#define EF_DATA_0_EF_SEC_LIFECYCLE_MSK (((1U << EF_DATA_0_EF_SEC_LIFECYCLE_LEN) - 1) << EF_DATA_0_EF_SEC_LIFECYCLE_POS)
+#define EF_DATA_0_EF_SEC_LIFECYCLE_UMSK (~(((1U << EF_DATA_0_EF_SEC_LIFECYCLE_LEN) - 1) << EF_DATA_0_EF_SEC_LIFECYCLE_POS))
+#define EF_DATA_0_WR_LOCK_RSVD_0 EF_DATA_0_WR_LOCK_RSVD_0
+#define EF_DATA_0_WR_LOCK_RSVD_0_POS (4U)
+#define EF_DATA_0_WR_LOCK_RSVD_0_LEN (10U)
+#define EF_DATA_0_WR_LOCK_RSVD_0_MSK (((1U << EF_DATA_0_WR_LOCK_RSVD_0_LEN) - 1) << EF_DATA_0_WR_LOCK_RSVD_0_POS)
+#define EF_DATA_0_WR_LOCK_RSVD_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_RSVD_0_LEN) - 1) << EF_DATA_0_WR_LOCK_RSVD_0_POS))
+#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (14U)
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U)
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS))
+#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD
+#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (15U)
+#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U)
+#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)
+#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS))
+#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (16U)
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U)
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (17U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (18U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (19U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (20U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (21U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS))
+#define EF_DATA_0_WR_LOCK_SW_USAGE_1 EF_DATA_0_WR_LOCK_SW_USAGE_1
+#define EF_DATA_0_WR_LOCK_SW_USAGE_1_POS (22U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_1_LEN (1U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_1_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_1_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_1_POS)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_1_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_1_POS))
+#define EF_DATA_0_WR_LOCK_SW_USAGE_2 EF_DATA_0_WR_LOCK_SW_USAGE_2
+#define EF_DATA_0_WR_LOCK_SW_USAGE_2_POS (23U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_2_LEN (1U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_2_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_2_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_2_POS)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_2_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_2_POS))
+#define EF_DATA_0_WR_LOCK_SW_USAGE_3 EF_DATA_0_WR_LOCK_SW_USAGE_3
+#define EF_DATA_0_WR_LOCK_SW_USAGE_3_POS (24U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_3_LEN (1U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_3_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_3_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_3_POS)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_3_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_3_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_11 EF_DATA_0_WR_LOCK_KEY_SLOT_11
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_POS (25U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_LEN (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_11_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_11_POS))
+#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD
+#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (26U)
+#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U)
+#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)
+#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (27U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (28U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (29U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (30U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_11 EF_DATA_0_RD_LOCK_KEY_SLOT_11
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_POS (31U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_LEN (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_11_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_11_POS))
+
+struct ef_data_0_reg {
+ /* 0x0 : ef_cfg_0 */
+ union {
+ struct {
+ uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t ef_ai_dis : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ef_cpu0_dis : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t ef_uart_dis : 4; /* [ 9: 6], r/w, 0x0 */
+ uint32_t ef_ble2_dis : 1; /* [ 10], r/w, 0x0 */
+ uint32_t ef_m1542_dis : 1; /* [ 11], r/w, 0x0 */
+ uint32_t ef_sf_key_re_sel : 2; /* [13:12], r/w, 0x0 */
+ uint32_t ef_sdu_dis : 1; /* [ 14], r/w, 0x0 */
+ uint32_t ef_btdm_dis : 1; /* [ 15], r/w, 0x0 */
+ uint32_t ef_wifi_dis : 1; /* [ 16], r/w, 0x0 */
+ uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t ef_cam_dis : 1; /* [ 18], r/w, 0x0 */
+ uint32_t ef_m154_dis : 1; /* [ 19], r/w, 0x0 */
+ uint32_t ef_cpu1_dis : 1; /* [ 20], r/w, 0x0 */
+ uint32_t ef_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */
+ uint32_t ef_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */
+ uint32_t ef_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */
+ uint32_t ef_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */
+ uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
+ uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_cfg_0;
+
+ /* 0x4 : ef_dbg_pwd_low */
+ union {
+ struct {
+ uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_dbg_pwd_low;
+
+ /* 0x8 : ef_dbg_pwd_high */
+ union {
+ struct {
+ uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_dbg_pwd_high;
+
+ /* 0xC : ef_dbg_pwd2_low */
+ union {
+ struct {
+ uint32_t ef_dbg_pwd2_low : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_dbg_pwd2_low;
+
+ /* 0x10 : ef_dbg_pwd2_high */
+ union {
+ struct {
+ uint32_t ef_dbg_pwd2_high : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_dbg_pwd2_high;
+
+ /* 0x14 : ef_wifi_mac_low */
+ union {
+ struct {
+ uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_wifi_mac_low;
+
+ /* 0x18 : ef_wifi_mac_high */
+ union {
+ struct {
+ uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_wifi_mac_high;
+
+ /* 0x1C : ef_key_slot_0_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_0_w0;
+
+ /* 0x20 : ef_key_slot_0_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_0_w1;
+
+ /* 0x24 : ef_key_slot_0_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_0_w2;
+
+ /* 0x28 : ef_key_slot_0_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_0_w3;
+
+ /* 0x2C : ef_key_slot_1_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_1_w0;
+
+ /* 0x30 : ef_key_slot_1_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_1_w1;
+
+ /* 0x34 : ef_key_slot_1_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_1_w2;
+
+ /* 0x38 : ef_key_slot_1_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_1_w3;
+
+ /* 0x3C : ef_key_slot_2_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_2_w0;
+
+ /* 0x40 : ef_key_slot_2_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_2_w1;
+
+ /* 0x44 : ef_key_slot_2_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_2_w2;
+
+ /* 0x48 : ef_key_slot_2_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_2_w3;
+
+ /* 0x4C : ef_key_slot_3_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_3_w0;
+
+ /* 0x50 : ef_key_slot_3_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_3_w1;
+
+ /* 0x54 : ef_key_slot_3_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_3_w2;
+
+ /* 0x58 : ef_key_slot_3_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_3_w3;
+
+ /* 0x5C : ef_sw_usage_0 */
+ union {
+ struct {
+ uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_sw_usage_0;
+
+ /* 0x60 : ef_sw_usage_1 */
+ union {
+ struct {
+ uint32_t ef_sw_usage_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_sw_usage_1;
+
+ /* 0x64 : ef_sw_usage_2 */
+ union {
+ struct {
+ uint32_t ef_sw_usage_2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_sw_usage_2;
+
+ /* 0x68 : ef_sw_usage_3 */
+ union {
+ struct {
+ uint32_t ef_sw_usage_3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_sw_usage_3;
+
+ /* 0x6C : ef_key_slot_11_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_11_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_11_w0;
+
+ /* 0x70 : ef_key_slot_11_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_11_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_11_w1;
+
+ /* 0x74 : ef_key_slot_11_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_11_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_11_w2;
+
+ /* 0x78 : ef_key_slot_11_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_11_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_11_w3;
+
+ /* 0x7C : ef_data_0_lock */
+ union {
+ struct {
+ uint32_t ef_sec_lifecycle : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t wr_lock_rsvd_0 : 10; /* [13: 4], r/w, 0x0 */
+ uint32_t wr_lock_boot_mode : 1; /* [ 14], r/w, 0x0 */
+ uint32_t wr_lock_dbg_pwd : 1; /* [ 15], r/w, 0x0 */
+ uint32_t wr_lock_wifi_mac : 1; /* [ 16], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_0 : 1; /* [ 17], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_1 : 1; /* [ 18], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_2 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_3 : 1; /* [ 20], r/w, 0x0 */
+ uint32_t wr_lock_sw_usage_0 : 1; /* [ 21], r/w, 0x0 */
+ uint32_t wr_lock_sw_usage_1 : 1; /* [ 22], r/w, 0x0 */
+ uint32_t wr_lock_sw_usage_2 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t wr_lock_sw_usage_3 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_11 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t rd_lock_dbg_pwd : 1; /* [ 26], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_0 : 1; /* [ 27], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_1 : 1; /* [ 28], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_2 : 1; /* [ 29], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_3 : 1; /* [ 30], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_11 : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_data_0_lock;
+};
+
+typedef volatile struct ef_data_0_reg ef_data_0_reg_t;
+
+#endif /* __EF_DATA_0_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_data_1_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_data_1_reg.h
new file mode 100644
index 00000000..325f03c3
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ef_data_1_reg.h
@@ -0,0 +1,662 @@
+/**
+ ******************************************************************************
+ * @file ef_data_1_reg.h
+ * @version V1.0
+ * @date 2021-07-31
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __EF_DATA_1_REG_H__
+#define __EF_DATA_1_REG_H__
+
+#include "bl808.h"
+
+/* 0x80 : ef_key_slot_4_w0 */
+#define EF_DATA_1_EF_KEY_SLOT_4_W0_OFFSET (0x80)
+#define EF_DATA_1_EF_KEY_SLOT_4_W0 EF_DATA_1_EF_KEY_SLOT_4_W0
+#define EF_DATA_1_EF_KEY_SLOT_4_W0_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W0_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W0_POS)
+#define EF_DATA_1_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W0_POS))
+
+/* 0x84 : ef_key_slot_4_w1 */
+#define EF_DATA_1_EF_KEY_SLOT_4_W1_OFFSET (0x84)
+#define EF_DATA_1_EF_KEY_SLOT_4_W1 EF_DATA_1_EF_KEY_SLOT_4_W1
+#define EF_DATA_1_EF_KEY_SLOT_4_W1_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W1_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W1_POS)
+#define EF_DATA_1_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W1_POS))
+
+/* 0x88 : ef_key_slot_4_w2 */
+#define EF_DATA_1_EF_KEY_SLOT_4_W2_OFFSET (0x88)
+#define EF_DATA_1_EF_KEY_SLOT_4_W2 EF_DATA_1_EF_KEY_SLOT_4_W2
+#define EF_DATA_1_EF_KEY_SLOT_4_W2_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W2_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W2_POS)
+#define EF_DATA_1_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W2_POS))
+
+/* 0x8C : ef_key_slot_4_w3 */
+#define EF_DATA_1_EF_KEY_SLOT_4_W3_OFFSET (0x8C)
+#define EF_DATA_1_EF_KEY_SLOT_4_W3 EF_DATA_1_EF_KEY_SLOT_4_W3
+#define EF_DATA_1_EF_KEY_SLOT_4_W3_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W3_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W3_POS)
+#define EF_DATA_1_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W3_POS))
+
+/* 0x90 : ef_key_slot_5_w0 */
+#define EF_DATA_1_EF_KEY_SLOT_5_W0_OFFSET (0x90)
+#define EF_DATA_1_EF_KEY_SLOT_5_W0 EF_DATA_1_EF_KEY_SLOT_5_W0
+#define EF_DATA_1_EF_KEY_SLOT_5_W0_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W0_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W0_POS)
+#define EF_DATA_1_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W0_POS))
+
+/* 0x94 : ef_key_slot_5_w1 */
+#define EF_DATA_1_EF_KEY_SLOT_5_W1_OFFSET (0x94)
+#define EF_DATA_1_EF_KEY_SLOT_5_W1 EF_DATA_1_EF_KEY_SLOT_5_W1
+#define EF_DATA_1_EF_KEY_SLOT_5_W1_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W1_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W1_POS)
+#define EF_DATA_1_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W1_POS))
+
+/* 0x98 : ef_key_slot_5_w2 */
+#define EF_DATA_1_EF_KEY_SLOT_5_W2_OFFSET (0x98)
+#define EF_DATA_1_EF_KEY_SLOT_5_W2 EF_DATA_1_EF_KEY_SLOT_5_W2
+#define EF_DATA_1_EF_KEY_SLOT_5_W2_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W2_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W2_POS)
+#define EF_DATA_1_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W2_POS))
+
+/* 0x9C : ef_key_slot_5_w3 */
+#define EF_DATA_1_EF_KEY_SLOT_5_W3_OFFSET (0x9C)
+#define EF_DATA_1_EF_KEY_SLOT_5_W3 EF_DATA_1_EF_KEY_SLOT_5_W3
+#define EF_DATA_1_EF_KEY_SLOT_5_W3_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W3_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W3_POS)
+#define EF_DATA_1_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W3_POS))
+
+/* 0xA0 : ef_key_slot_6_w0 */
+#define EF_DATA_1_EF_KEY_SLOT_6_W0_OFFSET (0xA0)
+#define EF_DATA_1_EF_KEY_SLOT_6_W0 EF_DATA_1_EF_KEY_SLOT_6_W0
+#define EF_DATA_1_EF_KEY_SLOT_6_W0_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W0_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W0_POS)
+#define EF_DATA_1_EF_KEY_SLOT_6_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W0_POS))
+
+/* 0xA4 : ef_key_slot_6_w1 */
+#define EF_DATA_1_EF_KEY_SLOT_6_W1_OFFSET (0xA4)
+#define EF_DATA_1_EF_KEY_SLOT_6_W1 EF_DATA_1_EF_KEY_SLOT_6_W1
+#define EF_DATA_1_EF_KEY_SLOT_6_W1_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W1_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W1_POS)
+#define EF_DATA_1_EF_KEY_SLOT_6_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W1_POS))
+
+/* 0xA8 : ef_key_slot_6_w2 */
+#define EF_DATA_1_EF_KEY_SLOT_6_W2_OFFSET (0xA8)
+#define EF_DATA_1_EF_KEY_SLOT_6_W2 EF_DATA_1_EF_KEY_SLOT_6_W2
+#define EF_DATA_1_EF_KEY_SLOT_6_W2_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W2_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W2_POS)
+#define EF_DATA_1_EF_KEY_SLOT_6_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W2_POS))
+
+/* 0xAC : ef_key_slot_6_w3 */
+#define EF_DATA_1_EF_KEY_SLOT_6_W3_OFFSET (0xAC)
+#define EF_DATA_1_EF_KEY_SLOT_6_W3 EF_DATA_1_EF_KEY_SLOT_6_W3
+#define EF_DATA_1_EF_KEY_SLOT_6_W3_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W3_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_6_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W3_POS)
+#define EF_DATA_1_EF_KEY_SLOT_6_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W3_POS))
+
+/* 0xB0 : ef_key_slot_7_w0 */
+#define EF_DATA_1_EF_KEY_SLOT_7_W0_OFFSET (0xB0)
+#define EF_DATA_1_EF_KEY_SLOT_7_W0 EF_DATA_1_EF_KEY_SLOT_7_W0
+#define EF_DATA_1_EF_KEY_SLOT_7_W0_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W0_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W0_POS)
+#define EF_DATA_1_EF_KEY_SLOT_7_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W0_POS))
+
+/* 0xB4 : ef_key_slot_7_w1 */
+#define EF_DATA_1_EF_KEY_SLOT_7_W1_OFFSET (0xB4)
+#define EF_DATA_1_EF_KEY_SLOT_7_W1 EF_DATA_1_EF_KEY_SLOT_7_W1
+#define EF_DATA_1_EF_KEY_SLOT_7_W1_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W1_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W1_POS)
+#define EF_DATA_1_EF_KEY_SLOT_7_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W1_POS))
+
+/* 0xB8 : ef_key_slot_7_w2 */
+#define EF_DATA_1_EF_KEY_SLOT_7_W2_OFFSET (0xB8)
+#define EF_DATA_1_EF_KEY_SLOT_7_W2 EF_DATA_1_EF_KEY_SLOT_7_W2
+#define EF_DATA_1_EF_KEY_SLOT_7_W2_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W2_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W2_POS)
+#define EF_DATA_1_EF_KEY_SLOT_7_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W2_POS))
+
+/* 0xBC : ef_key_slot_7_w3 */
+#define EF_DATA_1_EF_KEY_SLOT_7_W3_OFFSET (0xBC)
+#define EF_DATA_1_EF_KEY_SLOT_7_W3 EF_DATA_1_EF_KEY_SLOT_7_W3
+#define EF_DATA_1_EF_KEY_SLOT_7_W3_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W3_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_7_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W3_POS)
+#define EF_DATA_1_EF_KEY_SLOT_7_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W3_POS))
+
+/* 0xC0 : ef_key_slot_8_w0 */
+#define EF_DATA_1_EF_KEY_SLOT_8_W0_OFFSET (0xC0)
+#define EF_DATA_1_EF_KEY_SLOT_8_W0 EF_DATA_1_EF_KEY_SLOT_8_W0
+#define EF_DATA_1_EF_KEY_SLOT_8_W0_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W0_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W0_POS)
+#define EF_DATA_1_EF_KEY_SLOT_8_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W0_POS))
+
+/* 0xC4 : ef_key_slot_8_w1 */
+#define EF_DATA_1_EF_KEY_SLOT_8_W1_OFFSET (0xC4)
+#define EF_DATA_1_EF_KEY_SLOT_8_W1 EF_DATA_1_EF_KEY_SLOT_8_W1
+#define EF_DATA_1_EF_KEY_SLOT_8_W1_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W1_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W1_POS)
+#define EF_DATA_1_EF_KEY_SLOT_8_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W1_POS))
+
+/* 0xC8 : ef_key_slot_8_w2 */
+#define EF_DATA_1_EF_KEY_SLOT_8_W2_OFFSET (0xC8)
+#define EF_DATA_1_EF_KEY_SLOT_8_W2 EF_DATA_1_EF_KEY_SLOT_8_W2
+#define EF_DATA_1_EF_KEY_SLOT_8_W2_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W2_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W2_POS)
+#define EF_DATA_1_EF_KEY_SLOT_8_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W2_POS))
+
+/* 0xCC : ef_key_slot_8_w3 */
+#define EF_DATA_1_EF_KEY_SLOT_8_W3_OFFSET (0xCC)
+#define EF_DATA_1_EF_KEY_SLOT_8_W3 EF_DATA_1_EF_KEY_SLOT_8_W3
+#define EF_DATA_1_EF_KEY_SLOT_8_W3_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W3_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_8_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W3_POS)
+#define EF_DATA_1_EF_KEY_SLOT_8_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W3_POS))
+
+/* 0xD0 : ef_key_slot_9_w0 */
+#define EF_DATA_1_EF_KEY_SLOT_9_W0_OFFSET (0xD0)
+#define EF_DATA_1_EF_KEY_SLOT_9_W0 EF_DATA_1_EF_KEY_SLOT_9_W0
+#define EF_DATA_1_EF_KEY_SLOT_9_W0_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W0_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W0_POS)
+#define EF_DATA_1_EF_KEY_SLOT_9_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W0_POS))
+
+/* 0xD4 : ef_key_slot_9_w1 */
+#define EF_DATA_1_EF_KEY_SLOT_9_W1_OFFSET (0xD4)
+#define EF_DATA_1_EF_KEY_SLOT_9_W1 EF_DATA_1_EF_KEY_SLOT_9_W1
+#define EF_DATA_1_EF_KEY_SLOT_9_W1_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W1_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W1_POS)
+#define EF_DATA_1_EF_KEY_SLOT_9_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W1_POS))
+
+/* 0xD8 : ef_key_slot_9_w2 */
+#define EF_DATA_1_EF_KEY_SLOT_9_W2_OFFSET (0xD8)
+#define EF_DATA_1_EF_KEY_SLOT_9_W2 EF_DATA_1_EF_KEY_SLOT_9_W2
+#define EF_DATA_1_EF_KEY_SLOT_9_W2_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W2_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W2_POS)
+#define EF_DATA_1_EF_KEY_SLOT_9_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W2_POS))
+
+/* 0xDC : ef_key_slot_9_w3 */
+#define EF_DATA_1_EF_KEY_SLOT_9_W3_OFFSET (0xDC)
+#define EF_DATA_1_EF_KEY_SLOT_9_W3 EF_DATA_1_EF_KEY_SLOT_9_W3
+#define EF_DATA_1_EF_KEY_SLOT_9_W3_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W3_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_9_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W3_POS)
+#define EF_DATA_1_EF_KEY_SLOT_9_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W3_POS))
+
+/* 0xE0 : ef_key_slot_10_w0 */
+#define EF_DATA_1_EF_KEY_SLOT_10_W0_OFFSET (0xE0)
+#define EF_DATA_1_EF_KEY_SLOT_10_W0 EF_DATA_1_EF_KEY_SLOT_10_W0
+#define EF_DATA_1_EF_KEY_SLOT_10_W0_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W0_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W0_POS)
+#define EF_DATA_1_EF_KEY_SLOT_10_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W0_POS))
+
+/* 0xE4 : ef_key_slot_10_w1 */
+#define EF_DATA_1_EF_KEY_SLOT_10_W1_OFFSET (0xE4)
+#define EF_DATA_1_EF_KEY_SLOT_10_W1 EF_DATA_1_EF_KEY_SLOT_10_W1
+#define EF_DATA_1_EF_KEY_SLOT_10_W1_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W1_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W1_POS)
+#define EF_DATA_1_EF_KEY_SLOT_10_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W1_POS))
+
+/* 0xE8 : ef_key_slot_10_w2 */
+#define EF_DATA_1_EF_KEY_SLOT_10_W2_OFFSET (0xE8)
+#define EF_DATA_1_EF_KEY_SLOT_10_W2 EF_DATA_1_EF_KEY_SLOT_10_W2
+#define EF_DATA_1_EF_KEY_SLOT_10_W2_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W2_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W2_POS)
+#define EF_DATA_1_EF_KEY_SLOT_10_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W2_POS))
+
+/* 0xEC : ef_key_slot_10_w3 */
+#define EF_DATA_1_EF_KEY_SLOT_10_W3_OFFSET (0xEC)
+#define EF_DATA_1_EF_KEY_SLOT_10_W3 EF_DATA_1_EF_KEY_SLOT_10_W3
+#define EF_DATA_1_EF_KEY_SLOT_10_W3_POS (0U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W3_LEN (32U)
+#define EF_DATA_1_EF_KEY_SLOT_10_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W3_POS)
+#define EF_DATA_1_EF_KEY_SLOT_10_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W3_POS))
+
+/* 0xF0 : ef_dat_1_rsvd_0 */
+#define EF_DATA_1_EF_DAT_1_RSVD_0_OFFSET (0xF0)
+#define EF_DATA_1_EF_DAT_1_RSVD_0 EF_DATA_1_EF_DAT_1_RSVD_0
+#define EF_DATA_1_EF_DAT_1_RSVD_0_POS (0U)
+#define EF_DATA_1_EF_DAT_1_RSVD_0_LEN (32U)
+#define EF_DATA_1_EF_DAT_1_RSVD_0_MSK (((1U << EF_DATA_1_EF_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_0_POS)
+#define EF_DATA_1_EF_DAT_1_RSVD_0_UMSK (~(((1U << EF_DATA_1_EF_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_0_POS))
+
+/* 0xF4 : ef_dat_1_rsvd_1 */
+#define EF_DATA_1_EF_DAT_1_RSVD_1_OFFSET (0xF4)
+#define EF_DATA_1_EF_DAT_1_RSVD_1 EF_DATA_1_EF_DAT_1_RSVD_1
+#define EF_DATA_1_EF_DAT_1_RSVD_1_POS (0U)
+#define EF_DATA_1_EF_DAT_1_RSVD_1_LEN (32U)
+#define EF_DATA_1_EF_DAT_1_RSVD_1_MSK (((1U << EF_DATA_1_EF_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_1_POS)
+#define EF_DATA_1_EF_DAT_1_RSVD_1_UMSK (~(((1U << EF_DATA_1_EF_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_1_POS))
+
+/* 0xF8 : ef_dat_1_rsvd_2 */
+#define EF_DATA_1_EF_DAT_1_RSVD_2_OFFSET (0xF8)
+#define EF_DATA_1_EF_DAT_1_RSVD_2 EF_DATA_1_EF_DAT_1_RSVD_2
+#define EF_DATA_1_EF_DAT_1_RSVD_2_POS (0U)
+#define EF_DATA_1_EF_DAT_1_RSVD_2_LEN (32U)
+#define EF_DATA_1_EF_DAT_1_RSVD_2_MSK (((1U << EF_DATA_1_EF_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_2_POS)
+#define EF_DATA_1_EF_DAT_1_RSVD_2_UMSK (~(((1U << EF_DATA_1_EF_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_2_POS))
+
+/* 0xFC : ef_data_1_lock */
+#define EF_DATA_1_LOCK_OFFSET (0xFC)
+#define EF_DATA_1_WR_LOCK_RSVD_1 EF_DATA_1_WR_LOCK_RSVD_1
+#define EF_DATA_1_WR_LOCK_RSVD_1_POS (0U)
+#define EF_DATA_1_WR_LOCK_RSVD_1_LEN (15U)
+#define EF_DATA_1_WR_LOCK_RSVD_1_MSK (((1U << EF_DATA_1_WR_LOCK_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_RSVD_1_POS)
+#define EF_DATA_1_WR_LOCK_RSVD_1_UMSK (~(((1U << EF_DATA_1_WR_LOCK_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_RSVD_1_POS))
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_4 EF_DATA_1_WR_LOCK_KEY_SLOT_4
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_POS (15U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_LEN (1U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_4_POS)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_4_POS))
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_5 EF_DATA_1_WR_LOCK_KEY_SLOT_5
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_POS (16U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_LEN (1U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_5_POS)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_5_POS))
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_6 EF_DATA_1_WR_LOCK_KEY_SLOT_6
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS (17U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN (1U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS))
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_7 EF_DATA_1_WR_LOCK_KEY_SLOT_7
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS (18U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN (1U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS))
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_8 EF_DATA_1_WR_LOCK_KEY_SLOT_8
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS (19U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN (1U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS))
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_9 EF_DATA_1_WR_LOCK_KEY_SLOT_9
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS (20U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN (1U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS))
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_10 EF_DATA_1_WR_LOCK_KEY_SLOT_10
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_POS (21U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_LEN (1U)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_10_POS)
+#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_10_POS))
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0 EF_DATA_1_WR_LOCK_DAT_1_RSVD_0
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_POS (22U)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_LEN (1U)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_MSK (((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_POS)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_UMSK (~(((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_POS))
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1 EF_DATA_1_WR_LOCK_DAT_1_RSVD_1
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_POS (23U)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_LEN (1U)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_MSK (((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_POS)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_UMSK (~(((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_POS))
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2 EF_DATA_1_WR_LOCK_DAT_1_RSVD_2
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_POS (24U)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_LEN (1U)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_MSK (((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_POS)
+#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_UMSK (~(((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_POS))
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_4 EF_DATA_1_RD_LOCK_KEY_SLOT_4
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_POS (25U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_LEN (1U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_4_POS)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_4_POS))
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_5 EF_DATA_1_RD_LOCK_KEY_SLOT_5
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_POS (26U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_LEN (1U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_5_POS)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_5_POS))
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_6 EF_DATA_1_RD_LOCK_KEY_SLOT_6
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS (27U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN (1U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS))
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_7 EF_DATA_1_RD_LOCK_KEY_SLOT_7
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS (28U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN (1U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS))
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_8 EF_DATA_1_RD_LOCK_KEY_SLOT_8
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS (29U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN (1U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS))
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_9 EF_DATA_1_RD_LOCK_KEY_SLOT_9
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS (30U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN (1U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS))
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_10 EF_DATA_1_RD_LOCK_KEY_SLOT_10
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_POS (31U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_LEN (1U)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_10_POS)
+#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_10_POS))
+
+struct ef_data_1_reg {
+ /* 0x0 reserved */
+ uint8_t RESERVED0x0[128];
+
+ /* 0x80 : ef_key_slot_4_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_4_w0;
+
+ /* 0x84 : ef_key_slot_4_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_4_w1;
+
+ /* 0x88 : ef_key_slot_4_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_4_w2;
+
+ /* 0x8C : ef_key_slot_4_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_4_w3;
+
+ /* 0x90 : ef_key_slot_5_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_5_w0;
+
+ /* 0x94 : ef_key_slot_5_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_5_w1;
+
+ /* 0x98 : ef_key_slot_5_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_5_w2;
+
+ /* 0x9C : ef_key_slot_5_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_5_w3;
+
+ /* 0xA0 : ef_key_slot_6_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_6_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_6_w0;
+
+ /* 0xA4 : ef_key_slot_6_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_6_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_6_w1;
+
+ /* 0xA8 : ef_key_slot_6_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_6_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_6_w2;
+
+ /* 0xAC : ef_key_slot_6_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_6_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_6_w3;
+
+ /* 0xB0 : ef_key_slot_7_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_7_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_7_w0;
+
+ /* 0xB4 : ef_key_slot_7_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_7_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_7_w1;
+
+ /* 0xB8 : ef_key_slot_7_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_7_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_7_w2;
+
+ /* 0xBC : ef_key_slot_7_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_7_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_7_w3;
+
+ /* 0xC0 : ef_key_slot_8_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_8_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_8_w0;
+
+ /* 0xC4 : ef_key_slot_8_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_8_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_8_w1;
+
+ /* 0xC8 : ef_key_slot_8_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_8_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_8_w2;
+
+ /* 0xCC : ef_key_slot_8_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_8_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_8_w3;
+
+ /* 0xD0 : ef_key_slot_9_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_9_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_9_w0;
+
+ /* 0xD4 : ef_key_slot_9_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_9_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_9_w1;
+
+ /* 0xD8 : ef_key_slot_9_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_9_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_9_w2;
+
+ /* 0xDC : ef_key_slot_9_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_9_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_9_w3;
+
+ /* 0xE0 : ef_key_slot_10_w0 */
+ union {
+ struct {
+ uint32_t ef_key_slot_10_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_10_w0;
+
+ /* 0xE4 : ef_key_slot_10_w1 */
+ union {
+ struct {
+ uint32_t ef_key_slot_10_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_10_w1;
+
+ /* 0xE8 : ef_key_slot_10_w2 */
+ union {
+ struct {
+ uint32_t ef_key_slot_10_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_10_w2;
+
+ /* 0xEC : ef_key_slot_10_w3 */
+ union {
+ struct {
+ uint32_t ef_key_slot_10_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_key_slot_10_w3;
+
+ /* 0xF0 : ef_dat_1_rsvd_0 */
+ union {
+ struct {
+ uint32_t ef_dat_1_rsvd_0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_dat_1_rsvd_0;
+
+ /* 0xF4 : ef_dat_1_rsvd_1 */
+ union {
+ struct {
+ uint32_t ef_dat_1_rsvd_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_dat_1_rsvd_1;
+
+ /* 0xF8 : ef_dat_1_rsvd_2 */
+ union {
+ struct {
+ uint32_t ef_dat_1_rsvd_2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_dat_1_rsvd_2;
+
+ /* 0xFC : ef_data_1_lock */
+ union {
+ struct {
+ uint32_t wr_lock_rsvd_1 : 15; /* [14: 0], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_4 : 1; /* [ 15], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_5 : 1; /* [ 16], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_6 : 1; /* [ 17], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_7 : 1; /* [ 18], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_8 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_9 : 1; /* [ 20], r/w, 0x0 */
+ uint32_t wr_lock_key_slot_10 : 1; /* [ 21], r/w, 0x0 */
+ uint32_t wr_lock_dat_1_rsvd_0 : 1; /* [ 22], r/w, 0x0 */
+ uint32_t wr_lock_dat_1_rsvd_1 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t wr_lock_dat_1_rsvd_2 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_4 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_5 : 1; /* [ 26], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_6 : 1; /* [ 27], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_7 : 1; /* [ 28], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_8 : 1; /* [ 29], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_9 : 1; /* [ 30], r/w, 0x0 */
+ uint32_t rd_lock_key_slot_10 : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ef_data_1_lock;
+};
+
+typedef volatile struct ef_data_1_reg ef_data_1_reg_t;
+
+#endif /* __EF_DATA_1_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/glb_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/glb_reg.h
new file mode 100644
index 00000000..7e518f59
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/glb_reg.h
@@ -0,0 +1,13190 @@
+/**
+ ******************************************************************************
+ * @file glb_reg.h
+ * @version V1.0
+ * @date 2021-09-10
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __GLB_REG_H__
+#define __GLB_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : soc_info0 */
+#define GLB_SOC_INFO0_OFFSET (0x0)
+#define GLB_CHIP_RDY GLB_CHIP_RDY
+#define GLB_CHIP_RDY_POS (27U)
+#define GLB_CHIP_RDY_LEN (1U)
+#define GLB_CHIP_RDY_MSK (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
+#define GLB_CHIP_RDY_UMSK (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
+#define GLB_ID GLB_ID
+#define GLB_ID_POS (28U)
+#define GLB_ID_LEN (4U)
+#define GLB_ID_MSK (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
+#define GLB_ID_UMSK (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))
+
+/* 0x50 : core_cfg16 */
+#define GLB_CORE_CFG16_OFFSET (0x50)
+#define GLB_NP_INT_STA0 GLB_NP_INT_STA0
+#define GLB_NP_INT_STA0_POS (0U)
+#define GLB_NP_INT_STA0_LEN (32U)
+#define GLB_NP_INT_STA0_MSK (((1U << GLB_NP_INT_STA0_LEN) - 1) << GLB_NP_INT_STA0_POS)
+#define GLB_NP_INT_STA0_UMSK (~(((1U << GLB_NP_INT_STA0_LEN) - 1) << GLB_NP_INT_STA0_POS))
+
+/* 0x54 : core_cfg17 */
+#define GLB_CORE_CFG17_OFFSET (0x54)
+#define GLB_NP_INT_STA1 GLB_NP_INT_STA1
+#define GLB_NP_INT_STA1_POS (0U)
+#define GLB_NP_INT_STA1_LEN (32U)
+#define GLB_NP_INT_STA1_MSK (((1U << GLB_NP_INT_STA1_LEN) - 1) << GLB_NP_INT_STA1_POS)
+#define GLB_NP_INT_STA1_UMSK (~(((1U << GLB_NP_INT_STA1_LEN) - 1) << GLB_NP_INT_STA1_POS))
+
+/* 0x58 : core_cfg18 */
+#define GLB_CORE_CFG18_OFFSET (0x58)
+#define GLB_NP_INT_MASK0 GLB_NP_INT_MASK0
+#define GLB_NP_INT_MASK0_POS (0U)
+#define GLB_NP_INT_MASK0_LEN (32U)
+#define GLB_NP_INT_MASK0_MSK (((1U << GLB_NP_INT_MASK0_LEN) - 1) << GLB_NP_INT_MASK0_POS)
+#define GLB_NP_INT_MASK0_UMSK (~(((1U << GLB_NP_INT_MASK0_LEN) - 1) << GLB_NP_INT_MASK0_POS))
+
+/* 0x5C : core_cfg19 */
+#define GLB_CORE_CFG19_OFFSET (0x5C)
+#define GLB_NP_INT_MASK1 GLB_NP_INT_MASK1
+#define GLB_NP_INT_MASK1_POS (0U)
+#define GLB_NP_INT_MASK1_LEN (32U)
+#define GLB_NP_INT_MASK1_MSK (((1U << GLB_NP_INT_MASK1_LEN) - 1) << GLB_NP_INT_MASK1_POS)
+#define GLB_NP_INT_MASK1_UMSK (~(((1U << GLB_NP_INT_MASK1_LEN) - 1) << GLB_NP_INT_MASK1_POS))
+
+/* 0x60 : core_cfg20 */
+#define GLB_CORE_CFG20_OFFSET (0x60)
+#define GLB_NP_INT_CLR0 GLB_NP_INT_CLR0
+#define GLB_NP_INT_CLR0_POS (0U)
+#define GLB_NP_INT_CLR0_LEN (32U)
+#define GLB_NP_INT_CLR0_MSK (((1U << GLB_NP_INT_CLR0_LEN) - 1) << GLB_NP_INT_CLR0_POS)
+#define GLB_NP_INT_CLR0_UMSK (~(((1U << GLB_NP_INT_CLR0_LEN) - 1) << GLB_NP_INT_CLR0_POS))
+
+/* 0x64 : core_cfg21 */
+#define GLB_CORE_CFG21_OFFSET (0x64)
+#define GLB_NP_INT_CLR1 GLB_NP_INT_CLR1
+#define GLB_NP_INT_CLR1_POS (0U)
+#define GLB_NP_INT_CLR1_LEN (32U)
+#define GLB_NP_INT_CLR1_MSK (((1U << GLB_NP_INT_CLR1_LEN) - 1) << GLB_NP_INT_CLR1_POS)
+#define GLB_NP_INT_CLR1_UMSK (~(((1U << GLB_NP_INT_CLR1_LEN) - 1) << GLB_NP_INT_CLR1_POS))
+
+/* 0x68 : core_cfg22 */
+#define GLB_CORE_CFG22_OFFSET (0x68)
+#define GLB_REG_E902_INT_EN0 GLB_REG_E902_INT_EN0
+#define GLB_REG_E902_INT_EN0_POS (0U)
+#define GLB_REG_E902_INT_EN0_LEN (32U)
+#define GLB_REG_E902_INT_EN0_MSK (((1U << GLB_REG_E902_INT_EN0_LEN) - 1) << GLB_REG_E902_INT_EN0_POS)
+#define GLB_REG_E902_INT_EN0_UMSK (~(((1U << GLB_REG_E902_INT_EN0_LEN) - 1) << GLB_REG_E902_INT_EN0_POS))
+
+/* 0x6C : core_cfg23 */
+#define GLB_CORE_CFG23_OFFSET (0x6C)
+#define GLB_REG_E902_INT_EN1 GLB_REG_E902_INT_EN1
+#define GLB_REG_E902_INT_EN1_POS (0U)
+#define GLB_REG_E902_INT_EN1_LEN (32U)
+#define GLB_REG_E902_INT_EN1_MSK (((1U << GLB_REG_E902_INT_EN1_LEN) - 1) << GLB_REG_E902_INT_EN1_POS)
+#define GLB_REG_E902_INT_EN1_UMSK (~(((1U << GLB_REG_E902_INT_EN1_LEN) - 1) << GLB_REG_E902_INT_EN1_POS))
+
+/* 0x70 : core_cfg24 */
+#define GLB_CORE_CFG24_OFFSET (0x70)
+#define GLB_STS_E902_INT_BUS_0 GLB_STS_E902_INT_BUS_0
+#define GLB_STS_E902_INT_BUS_0_POS (0U)
+#define GLB_STS_E902_INT_BUS_0_LEN (32U)
+#define GLB_STS_E902_INT_BUS_0_MSK (((1U << GLB_STS_E902_INT_BUS_0_LEN) - 1) << GLB_STS_E902_INT_BUS_0_POS)
+#define GLB_STS_E902_INT_BUS_0_UMSK (~(((1U << GLB_STS_E902_INT_BUS_0_LEN) - 1) << GLB_STS_E902_INT_BUS_0_POS))
+
+/* 0x74 : core_cfg25 */
+#define GLB_CORE_CFG25_OFFSET (0x74)
+#define GLB_STS_E902_INT_BUS_1 GLB_STS_E902_INT_BUS_1
+#define GLB_STS_E902_INT_BUS_1_POS (0U)
+#define GLB_STS_E902_INT_BUS_1_LEN (32U)
+#define GLB_STS_E902_INT_BUS_1_MSK (((1U << GLB_STS_E902_INT_BUS_1_LEN) - 1) << GLB_STS_E902_INT_BUS_1_POS)
+#define GLB_STS_E902_INT_BUS_1_UMSK (~(((1U << GLB_STS_E902_INT_BUS_1_LEN) - 1) << GLB_STS_E902_INT_BUS_1_POS))
+
+/* 0x90 : sys_cfg0 */
+#define GLB_SYS_CFG0_OFFSET (0x90)
+#define GLB_REG_PLL_EN GLB_REG_PLL_EN
+#define GLB_REG_PLL_EN_POS (0U)
+#define GLB_REG_PLL_EN_LEN (1U)
+#define GLB_REG_PLL_EN_MSK (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
+#define GLB_REG_PLL_EN_UMSK (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
+#define GLB_REG_FCLK_EN GLB_REG_FCLK_EN
+#define GLB_REG_FCLK_EN_POS (1U)
+#define GLB_REG_FCLK_EN_LEN (1U)
+#define GLB_REG_FCLK_EN_MSK (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
+#define GLB_REG_FCLK_EN_UMSK (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
+#define GLB_REG_HCLK_EN GLB_REG_HCLK_EN
+#define GLB_REG_HCLK_EN_POS (2U)
+#define GLB_REG_HCLK_EN_LEN (1U)
+#define GLB_REG_HCLK_EN_MSK (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
+#define GLB_REG_HCLK_EN_UMSK (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
+#define GLB_REG_BCLK_EN GLB_REG_BCLK_EN
+#define GLB_REG_BCLK_EN_POS (3U)
+#define GLB_REG_BCLK_EN_LEN (1U)
+#define GLB_REG_BCLK_EN_MSK (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
+#define GLB_REG_BCLK_EN_UMSK (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
+#define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL
+#define GLB_HBN_ROOT_CLK_SEL_POS (6U)
+#define GLB_HBN_ROOT_CLK_SEL_LEN (2U)
+#define GLB_HBN_ROOT_CLK_SEL_MSK (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
+#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
+#define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV
+#define GLB_REG_HCLK_DIV_POS (8U)
+#define GLB_REG_HCLK_DIV_LEN (8U)
+#define GLB_REG_HCLK_DIV_MSK (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
+#define GLB_REG_HCLK_DIV_UMSK (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
+#define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV
+#define GLB_REG_BCLK_DIV_POS (16U)
+#define GLB_REG_BCLK_DIV_LEN (8U)
+#define GLB_REG_BCLK_DIV_MSK (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
+#define GLB_REG_BCLK_DIV_UMSK (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
+
+/* 0x94 : sys_cfg1 */
+#define GLB_SYS_CFG1_OFFSET (0x94)
+#define GLB_REG_BCLK_DIV_ACT_PULSE GLB_REG_BCLK_DIV_ACT_PULSE
+#define GLB_REG_BCLK_DIV_ACT_PULSE_POS (0U)
+#define GLB_REG_BCLK_DIV_ACT_PULSE_LEN (1U)
+#define GLB_REG_BCLK_DIV_ACT_PULSE_MSK (((1U << GLB_REG_BCLK_DIV_ACT_PULSE_LEN) - 1) << GLB_REG_BCLK_DIV_ACT_PULSE_POS)
+#define GLB_REG_BCLK_DIV_ACT_PULSE_UMSK (~(((1U << GLB_REG_BCLK_DIV_ACT_PULSE_LEN) - 1) << GLB_REG_BCLK_DIV_ACT_PULSE_POS))
+#define GLB_REG_BCLK_DIV_BYPASS GLB_REG_BCLK_DIV_BYPASS
+#define GLB_REG_BCLK_DIV_BYPASS_POS (1U)
+#define GLB_REG_BCLK_DIV_BYPASS_LEN (1U)
+#define GLB_REG_BCLK_DIV_BYPASS_MSK (((1U << GLB_REG_BCLK_DIV_BYPASS_LEN) - 1) << GLB_REG_BCLK_DIV_BYPASS_POS)
+#define GLB_REG_BCLK_DIV_BYPASS_UMSK (~(((1U << GLB_REG_BCLK_DIV_BYPASS_LEN) - 1) << GLB_REG_BCLK_DIV_BYPASS_POS))
+#define GLB_STS_BCLK_PROT_DONE GLB_STS_BCLK_PROT_DONE
+#define GLB_STS_BCLK_PROT_DONE_POS (2U)
+#define GLB_STS_BCLK_PROT_DONE_LEN (1U)
+#define GLB_STS_BCLK_PROT_DONE_MSK (((1U << GLB_STS_BCLK_PROT_DONE_LEN) - 1) << GLB_STS_BCLK_PROT_DONE_POS)
+#define GLB_STS_BCLK_PROT_DONE_UMSK (~(((1U << GLB_STS_BCLK_PROT_DONE_LEN) - 1) << GLB_STS_BCLK_PROT_DONE_POS))
+#define GLB_REG_BCLK_SW_DONE_CNT GLB_REG_BCLK_SW_DONE_CNT
+#define GLB_REG_BCLK_SW_DONE_CNT_POS (4U)
+#define GLB_REG_BCLK_SW_DONE_CNT_LEN (4U)
+#define GLB_REG_BCLK_SW_DONE_CNT_MSK (((1U << GLB_REG_BCLK_SW_DONE_CNT_LEN) - 1) << GLB_REG_BCLK_SW_DONE_CNT_POS)
+#define GLB_REG_BCLK_SW_DONE_CNT_UMSK (~(((1U << GLB_REG_BCLK_SW_DONE_CNT_LEN) - 1) << GLB_REG_BCLK_SW_DONE_CNT_POS))
+#define GLB_REG_PICO_CLK_DIV_ACT_PULSE GLB_REG_PICO_CLK_DIV_ACT_PULSE
+#define GLB_REG_PICO_CLK_DIV_ACT_PULSE_POS (16U)
+#define GLB_REG_PICO_CLK_DIV_ACT_PULSE_LEN (1U)
+#define GLB_REG_PICO_CLK_DIV_ACT_PULSE_MSK (((1U << GLB_REG_PICO_CLK_DIV_ACT_PULSE_LEN) - 1) << GLB_REG_PICO_CLK_DIV_ACT_PULSE_POS)
+#define GLB_REG_PICO_CLK_DIV_ACT_PULSE_UMSK (~(((1U << GLB_REG_PICO_CLK_DIV_ACT_PULSE_LEN) - 1) << GLB_REG_PICO_CLK_DIV_ACT_PULSE_POS))
+#define GLB_REG_PICO_CLK_DIV_BYPASS GLB_REG_PICO_CLK_DIV_BYPASS
+#define GLB_REG_PICO_CLK_DIV_BYPASS_POS (17U)
+#define GLB_REG_PICO_CLK_DIV_BYPASS_LEN (1U)
+#define GLB_REG_PICO_CLK_DIV_BYPASS_MSK (((1U << GLB_REG_PICO_CLK_DIV_BYPASS_LEN) - 1) << GLB_REG_PICO_CLK_DIV_BYPASS_POS)
+#define GLB_REG_PICO_CLK_DIV_BYPASS_UMSK (~(((1U << GLB_REG_PICO_CLK_DIV_BYPASS_LEN) - 1) << GLB_REG_PICO_CLK_DIV_BYPASS_POS))
+#define GLB_STS_PICO_CLK_PROT_DONE GLB_STS_PICO_CLK_PROT_DONE
+#define GLB_STS_PICO_CLK_PROT_DONE_POS (18U)
+#define GLB_STS_PICO_CLK_PROT_DONE_LEN (1U)
+#define GLB_STS_PICO_CLK_PROT_DONE_MSK (((1U << GLB_STS_PICO_CLK_PROT_DONE_LEN) - 1) << GLB_STS_PICO_CLK_PROT_DONE_POS)
+#define GLB_STS_PICO_CLK_PROT_DONE_UMSK (~(((1U << GLB_STS_PICO_CLK_PROT_DONE_LEN) - 1) << GLB_STS_PICO_CLK_PROT_DONE_POS))
+#define GLB_REG_PICO_CLK_SW_DONE_CNT GLB_REG_PICO_CLK_SW_DONE_CNT
+#define GLB_REG_PICO_CLK_SW_DONE_CNT_POS (20U)
+#define GLB_REG_PICO_CLK_SW_DONE_CNT_LEN (4U)
+#define GLB_REG_PICO_CLK_SW_DONE_CNT_MSK (((1U << GLB_REG_PICO_CLK_SW_DONE_CNT_LEN) - 1) << GLB_REG_PICO_CLK_SW_DONE_CNT_POS)
+#define GLB_REG_PICO_CLK_SW_DONE_CNT_UMSK (~(((1U << GLB_REG_PICO_CLK_SW_DONE_CNT_LEN) - 1) << GLB_REG_PICO_CLK_SW_DONE_CNT_POS))
+#define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE
+#define GLB_FCLK_SW_STATE_POS (24U)
+#define GLB_FCLK_SW_STATE_LEN (3U)
+#define GLB_FCLK_SW_STATE_MSK (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
+#define GLB_FCLK_SW_STATE_UMSK (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
+
+/* 0xA0 : bus_cfg0 */
+#define GLB_BUS_CFG0_OFFSET (0xA0)
+#define GLB_RG_APB2_PCK_FORCE GLB_RG_APB2_PCK_FORCE
+#define GLB_RG_APB2_PCK_FORCE_POS (0U)
+#define GLB_RG_APB2_PCK_FORCE_LEN (16U)
+#define GLB_RG_APB2_PCK_FORCE_MSK (((1U << GLB_RG_APB2_PCK_FORCE_LEN) - 1) << GLB_RG_APB2_PCK_FORCE_POS)
+#define GLB_RG_APB2_PCK_FORCE_UMSK (~(((1U << GLB_RG_APB2_PCK_FORCE_LEN) - 1) << GLB_RG_APB2_PCK_FORCE_POS))
+
+/* 0xE0 : emi_cfg0 */
+#define GLB_EMI_CFG0_OFFSET (0xE0)
+#define GLB_REG_EMI_CLK_EN GLB_REG_EMI_CLK_EN
+#define GLB_REG_EMI_CLK_EN_POS (9U)
+#define GLB_REG_EMI_CLK_EN_LEN (1U)
+#define GLB_REG_EMI_CLK_EN_MSK (((1U << GLB_REG_EMI_CLK_EN_LEN) - 1) << GLB_REG_EMI_CLK_EN_POS)
+#define GLB_REG_EMI_CLK_EN_UMSK (~(((1U << GLB_REG_EMI_CLK_EN_LEN) - 1) << GLB_REG_EMI_CLK_EN_POS))
+#define GLB_REG_EMI_CLK_SEL GLB_REG_EMI_CLK_SEL
+#define GLB_REG_EMI_CLK_SEL_POS (14U)
+#define GLB_REG_EMI_CLK_SEL_LEN (3U)
+#define GLB_REG_EMI_CLK_SEL_MSK (((1U << GLB_REG_EMI_CLK_SEL_LEN) - 1) << GLB_REG_EMI_CLK_SEL_POS)
+#define GLB_REG_EMI_CLK_SEL_UMSK (~(((1U << GLB_REG_EMI_CLK_SEL_LEN) - 1) << GLB_REG_EMI_CLK_SEL_POS))
+#define GLB_REG_EMI_CLK_DIV GLB_REG_EMI_CLK_DIV
+#define GLB_REG_EMI_CLK_DIV_POS (22U)
+#define GLB_REG_EMI_CLK_DIV_LEN (2U)
+#define GLB_REG_EMI_CLK_DIV_MSK (((1U << GLB_REG_EMI_CLK_DIV_LEN) - 1) << GLB_REG_EMI_CLK_DIV_POS)
+#define GLB_REG_EMI_CLK_DIV_UMSK (~(((1U << GLB_REG_EMI_CLK_DIV_LEN) - 1) << GLB_REG_EMI_CLK_DIV_POS))
+
+/* 0xF0 : rtc_cfg0 */
+#define GLB_RTC_CFG0_OFFSET (0xF0)
+#define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV
+#define GLB_CPU_RTC_DIV_POS (0U)
+#define GLB_CPU_RTC_DIV_LEN (17U)
+#define GLB_CPU_RTC_DIV_MSK (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
+#define GLB_CPU_RTC_DIV_UMSK (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
+#define GLB_CPU_RTC_EN GLB_CPU_RTC_EN
+#define GLB_CPU_RTC_EN_POS (18U)
+#define GLB_CPU_RTC_EN_LEN (1U)
+#define GLB_CPU_RTC_EN_MSK (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
+#define GLB_CPU_RTC_EN_UMSK (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
+#define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL
+#define GLB_CPU_RTC_SEL_POS (19U)
+#define GLB_CPU_RTC_SEL_LEN (1U)
+#define GLB_CPU_RTC_SEL_MSK (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
+#define GLB_CPU_RTC_SEL_UMSK (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
+
+/* 0x110 : adc_cfg0 */
+#define GLB_ADC_CFG0_OFFSET (0x110)
+#define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV
+#define GLB_GPADC_32M_CLK_DIV_POS (0U)
+#define GLB_GPADC_32M_CLK_DIV_LEN (6U)
+#define GLB_GPADC_32M_CLK_DIV_MSK (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
+#define GLB_GPADC_32M_CLK_DIV_UMSK (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
+#define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL
+#define GLB_GPADC_32M_CLK_SEL_POS (7U)
+#define GLB_GPADC_32M_CLK_SEL_LEN (1U)
+#define GLB_GPADC_32M_CLK_SEL_MSK (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
+#define GLB_GPADC_32M_CLK_SEL_UMSK (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
+#define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN
+#define GLB_GPADC_32M_DIV_EN_POS (8U)
+#define GLB_GPADC_32M_DIV_EN_LEN (1U)
+#define GLB_GPADC_32M_DIV_EN_MSK (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
+#define GLB_GPADC_32M_DIV_EN_UMSK (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
+
+/* 0x120 : dac_cfg0 */
+#define GLB_DAC_CFG0_OFFSET (0x120)
+#define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA
+#define GLB_GPDACA_RSTN_ANA_POS (0U)
+#define GLB_GPDACA_RSTN_ANA_LEN (1U)
+#define GLB_GPDACA_RSTN_ANA_MSK (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
+#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
+#define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA
+#define GLB_GPDACB_RSTN_ANA_POS (1U)
+#define GLB_GPDACB_RSTN_ANA_LEN (1U)
+#define GLB_GPDACB_RSTN_ANA_MSK (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
+#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
+#define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN
+#define GLB_GPDAC_TEST_EN_POS (7U)
+#define GLB_GPDAC_TEST_EN_LEN (1U)
+#define GLB_GPDAC_TEST_EN_MSK (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
+#define GLB_GPDAC_TEST_EN_UMSK (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
+#define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL
+#define GLB_GPDAC_REF_SEL_POS (8U)
+#define GLB_GPDAC_REF_SEL_LEN (1U)
+#define GLB_GPDAC_REF_SEL_MSK (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
+#define GLB_GPDAC_REF_SEL_UMSK (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
+#define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL
+#define GLB_GPDAC_TEST_SEL_POS (9U)
+#define GLB_GPDAC_TEST_SEL_LEN (3U)
+#define GLB_GPDAC_TEST_SEL_MSK (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
+#define GLB_GPDAC_TEST_SEL_UMSK (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
+#define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED
+#define GLB_GPDAC_RESERVED_POS (24U)
+#define GLB_GPDAC_RESERVED_LEN (8U)
+#define GLB_GPDAC_RESERVED_MSK (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
+#define GLB_GPDAC_RESERVED_UMSK (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
+
+/* 0x124 : dac_cfg1 */
+#define GLB_DAC_CFG1_OFFSET (0x124)
+#define GLB_GPDAC_A_EN GLB_GPDAC_A_EN
+#define GLB_GPDAC_A_EN_POS (0U)
+#define GLB_GPDAC_A_EN_LEN (1U)
+#define GLB_GPDAC_A_EN_MSK (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
+#define GLB_GPDAC_A_EN_UMSK (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
+#define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN
+#define GLB_GPDAC_IOA_EN_POS (1U)
+#define GLB_GPDAC_IOA_EN_LEN (1U)
+#define GLB_GPDAC_IOA_EN_MSK (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
+#define GLB_GPDAC_IOA_EN_UMSK (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
+#define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG
+#define GLB_GPDAC_A_RNG_POS (18U)
+#define GLB_GPDAC_A_RNG_LEN (2U)
+#define GLB_GPDAC_A_RNG_MSK (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
+#define GLB_GPDAC_A_RNG_UMSK (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
+#define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX
+#define GLB_GPDAC_A_OUTMUX_POS (20U)
+#define GLB_GPDAC_A_OUTMUX_LEN (3U)
+#define GLB_GPDAC_A_OUTMUX_MSK (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
+#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
+
+/* 0x128 : dac_cfg2 */
+#define GLB_DAC_CFG2_OFFSET (0x128)
+#define GLB_GPDAC_B_EN GLB_GPDAC_B_EN
+#define GLB_GPDAC_B_EN_POS (0U)
+#define GLB_GPDAC_B_EN_LEN (1U)
+#define GLB_GPDAC_B_EN_MSK (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
+#define GLB_GPDAC_B_EN_UMSK (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
+#define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN
+#define GLB_GPDAC_IOB_EN_POS (1U)
+#define GLB_GPDAC_IOB_EN_LEN (1U)
+#define GLB_GPDAC_IOB_EN_MSK (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
+#define GLB_GPDAC_IOB_EN_UMSK (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
+#define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG
+#define GLB_GPDAC_B_RNG_POS (18U)
+#define GLB_GPDAC_B_RNG_LEN (2U)
+#define GLB_GPDAC_B_RNG_MSK (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
+#define GLB_GPDAC_B_RNG_UMSK (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
+#define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX
+#define GLB_GPDAC_B_OUTMUX_POS (20U)
+#define GLB_GPDAC_B_OUTMUX_LEN (3U)
+#define GLB_GPDAC_B_OUTMUX_MSK (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
+#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
+
+/* 0x12C : dac_cfg3 */
+#define GLB_DAC_CFG3_OFFSET (0x12C)
+#define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA
+#define GLB_GPDAC_B_DATA_POS (0U)
+#define GLB_GPDAC_B_DATA_LEN (10U)
+#define GLB_GPDAC_B_DATA_MSK (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
+#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
+#define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA
+#define GLB_GPDAC_A_DATA_POS (16U)
+#define GLB_GPDAC_A_DATA_LEN (10U)
+#define GLB_GPDAC_A_DATA_MSK (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
+#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
+
+/* 0x130 : dma_cfg0 */
+#define GLB_DMA_CFG0_OFFSET (0x130)
+#define GLB_DMA_CLK_EN GLB_DMA_CLK_EN
+#define GLB_DMA_CLK_EN_POS (24U)
+#define GLB_DMA_CLK_EN_LEN (8U)
+#define GLB_DMA_CLK_EN_MSK (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
+#define GLB_DMA_CLK_EN_UMSK (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
+
+/* 0x134 : dma_cfg1 */
+#define GLB_DMA_CFG1_OFFSET (0x134)
+#define GLB_DMA2_CLK_EN GLB_DMA2_CLK_EN
+#define GLB_DMA2_CLK_EN_POS (24U)
+#define GLB_DMA2_CLK_EN_LEN (8U)
+#define GLB_DMA2_CLK_EN_MSK (((1U << GLB_DMA2_CLK_EN_LEN) - 1) << GLB_DMA2_CLK_EN_POS)
+#define GLB_DMA2_CLK_EN_UMSK (~(((1U << GLB_DMA2_CLK_EN_LEN) - 1) << GLB_DMA2_CLK_EN_POS))
+
+/* 0x138 : dma_cfg2 */
+#define GLB_DMA_CFG2_OFFSET (0x138)
+#define GLB_REG_DMA_CN_SEL GLB_REG_DMA_CN_SEL
+#define GLB_REG_DMA_CN_SEL_POS (0U)
+#define GLB_REG_DMA_CN_SEL_LEN (32U)
+#define GLB_REG_DMA_CN_SEL_MSK (((1U << GLB_REG_DMA_CN_SEL_LEN) - 1) << GLB_REG_DMA_CN_SEL_POS)
+#define GLB_REG_DMA_CN_SEL_UMSK (~(((1U << GLB_REG_DMA_CN_SEL_LEN) - 1) << GLB_REG_DMA_CN_SEL_POS))
+
+/* 0x140 : ir_cfg0 */
+#define GLB_IR_CFG0_OFFSET (0x140)
+#define GLB_IR_CLK_DIV GLB_IR_CLK_DIV
+#define GLB_IR_CLK_DIV_POS (16U)
+#define GLB_IR_CLK_DIV_LEN (6U)
+#define GLB_IR_CLK_DIV_MSK (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
+#define GLB_IR_CLK_DIV_UMSK (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
+#define GLB_IR_CLK_EN GLB_IR_CLK_EN
+#define GLB_IR_CLK_EN_POS (23U)
+#define GLB_IR_CLK_EN_LEN (1U)
+#define GLB_IR_CLK_EN_MSK (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
+#define GLB_IR_CLK_EN_UMSK (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
+
+/* 0x144 : ir_cfg1 */
+#define GLB_IR_CFG1_OFFSET (0x144)
+#define GLB_LED_DIN_REG GLB_LED_DIN_REG
+#define GLB_LED_DIN_REG_POS (0U)
+#define GLB_LED_DIN_REG_LEN (1U)
+#define GLB_LED_DIN_REG_MSK (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
+#define GLB_LED_DIN_REG_UMSK (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
+#define GLB_LED_DIN_SEL GLB_LED_DIN_SEL
+#define GLB_LED_DIN_SEL_POS (1U)
+#define GLB_LED_DIN_SEL_LEN (1U)
+#define GLB_LED_DIN_SEL_MSK (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
+#define GLB_LED_DIN_SEL_UMSK (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
+#define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL
+#define GLB_LED_DIN_POLARITY_SEL_POS (2U)
+#define GLB_LED_DIN_POLARITY_SEL_LEN (1U)
+#define GLB_LED_DIN_POLARITY_SEL_MSK (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
+#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS))
+#define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS
+#define GLB_LEDDRV_IBIAS_POS (4U)
+#define GLB_LEDDRV_IBIAS_LEN (4U)
+#define GLB_LEDDRV_IBIAS_MSK (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
+#define GLB_LEDDRV_IBIAS_UMSK (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
+#define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL
+#define GLB_IR_RX_GPIO_SEL_POS (8U)
+#define GLB_IR_RX_GPIO_SEL_LEN (4U)
+#define GLB_IR_RX_GPIO_SEL_MSK (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
+#define GLB_IR_RX_GPIO_SEL_UMSK (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
+#define GLB_PU_LEDDRV GLB_PU_LEDDRV
+#define GLB_PU_LEDDRV_POS (31U)
+#define GLB_PU_LEDDRV_LEN (1U)
+#define GLB_PU_LEDDRV_MSK (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
+#define GLB_PU_LEDDRV_UMSK (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
+
+/* 0x150 : uart_cfg0 */
+#define GLB_UART_CFG0_OFFSET (0x150)
+#define GLB_UART_CLK_DIV GLB_UART_CLK_DIV
+#define GLB_UART_CLK_DIV_POS (0U)
+#define GLB_UART_CLK_DIV_LEN (3U)
+#define GLB_UART_CLK_DIV_MSK (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
+#define GLB_UART_CLK_DIV_UMSK (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
+#define GLB_UART_CLK_EN GLB_UART_CLK_EN
+#define GLB_UART_CLK_EN_POS (4U)
+#define GLB_UART_CLK_EN_LEN (1U)
+#define GLB_UART_CLK_EN_MSK (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
+#define GLB_UART_CLK_EN_UMSK (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
+#define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL
+#define GLB_HBN_UART_CLK_SEL_POS (7U)
+#define GLB_HBN_UART_CLK_SEL_LEN (1U)
+#define GLB_HBN_UART_CLK_SEL_MSK (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
+#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
+#define GLB_HBN_UART_CLK_SEL2 GLB_HBN_UART_CLK_SEL2
+#define GLB_HBN_UART_CLK_SEL2_POS (22U)
+#define GLB_HBN_UART_CLK_SEL2_LEN (1U)
+#define GLB_HBN_UART_CLK_SEL2_MSK (((1U << GLB_HBN_UART_CLK_SEL2_LEN) - 1) << GLB_HBN_UART_CLK_SEL2_POS)
+#define GLB_HBN_UART_CLK_SEL2_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL2_LEN) - 1) << GLB_HBN_UART_CLK_SEL2_POS))
+#define GLB_UART2_IO_SEL GLB_UART2_IO_SEL
+#define GLB_UART2_IO_SEL_POS (24U)
+#define GLB_UART2_IO_SEL_LEN (1U)
+#define GLB_UART2_IO_SEL_MSK (((1U << GLB_UART2_IO_SEL_LEN) - 1) << GLB_UART2_IO_SEL_POS)
+#define GLB_UART2_IO_SEL_UMSK (~(((1U << GLB_UART2_IO_SEL_LEN) - 1) << GLB_UART2_IO_SEL_POS))
+
+/* 0x154 : uart_cfg1 */
+#define GLB_UART_CFG1_OFFSET (0x154)
+#define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL
+#define GLB_UART_SIG_0_SEL_POS (0U)
+#define GLB_UART_SIG_0_SEL_LEN (4U)
+#define GLB_UART_SIG_0_SEL_MSK (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
+#define GLB_UART_SIG_0_SEL_UMSK (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
+#define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL
+#define GLB_UART_SIG_1_SEL_POS (4U)
+#define GLB_UART_SIG_1_SEL_LEN (4U)
+#define GLB_UART_SIG_1_SEL_MSK (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
+#define GLB_UART_SIG_1_SEL_UMSK (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
+#define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL
+#define GLB_UART_SIG_2_SEL_POS (8U)
+#define GLB_UART_SIG_2_SEL_LEN (4U)
+#define GLB_UART_SIG_2_SEL_MSK (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
+#define GLB_UART_SIG_2_SEL_UMSK (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
+#define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL
+#define GLB_UART_SIG_3_SEL_POS (12U)
+#define GLB_UART_SIG_3_SEL_LEN (4U)
+#define GLB_UART_SIG_3_SEL_MSK (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
+#define GLB_UART_SIG_3_SEL_UMSK (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
+#define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL
+#define GLB_UART_SIG_4_SEL_POS (16U)
+#define GLB_UART_SIG_4_SEL_LEN (4U)
+#define GLB_UART_SIG_4_SEL_MSK (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
+#define GLB_UART_SIG_4_SEL_UMSK (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
+#define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL
+#define GLB_UART_SIG_5_SEL_POS (20U)
+#define GLB_UART_SIG_5_SEL_LEN (4U)
+#define GLB_UART_SIG_5_SEL_MSK (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
+#define GLB_UART_SIG_5_SEL_UMSK (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
+#define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL
+#define GLB_UART_SIG_6_SEL_POS (24U)
+#define GLB_UART_SIG_6_SEL_LEN (4U)
+#define GLB_UART_SIG_6_SEL_MSK (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
+#define GLB_UART_SIG_6_SEL_UMSK (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
+#define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL
+#define GLB_UART_SIG_7_SEL_POS (28U)
+#define GLB_UART_SIG_7_SEL_LEN (4U)
+#define GLB_UART_SIG_7_SEL_MSK (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
+#define GLB_UART_SIG_7_SEL_UMSK (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
+
+/* 0x158 : uart_cfg2 */
+#define GLB_UART_CFG2_OFFSET (0x158)
+#define GLB_UART_SIG_8_SEL GLB_UART_SIG_8_SEL
+#define GLB_UART_SIG_8_SEL_POS (0U)
+#define GLB_UART_SIG_8_SEL_LEN (4U)
+#define GLB_UART_SIG_8_SEL_MSK (((1U << GLB_UART_SIG_8_SEL_LEN) - 1) << GLB_UART_SIG_8_SEL_POS)
+#define GLB_UART_SIG_8_SEL_UMSK (~(((1U << GLB_UART_SIG_8_SEL_LEN) - 1) << GLB_UART_SIG_8_SEL_POS))
+#define GLB_UART_SIG_9_SEL GLB_UART_SIG_9_SEL
+#define GLB_UART_SIG_9_SEL_POS (4U)
+#define GLB_UART_SIG_9_SEL_LEN (4U)
+#define GLB_UART_SIG_9_SEL_MSK (((1U << GLB_UART_SIG_9_SEL_LEN) - 1) << GLB_UART_SIG_9_SEL_POS)
+#define GLB_UART_SIG_9_SEL_UMSK (~(((1U << GLB_UART_SIG_9_SEL_LEN) - 1) << GLB_UART_SIG_9_SEL_POS))
+#define GLB_UART_SIG_10_SEL GLB_UART_SIG_10_SEL
+#define GLB_UART_SIG_10_SEL_POS (8U)
+#define GLB_UART_SIG_10_SEL_LEN (4U)
+#define GLB_UART_SIG_10_SEL_MSK (((1U << GLB_UART_SIG_10_SEL_LEN) - 1) << GLB_UART_SIG_10_SEL_POS)
+#define GLB_UART_SIG_10_SEL_UMSK (~(((1U << GLB_UART_SIG_10_SEL_LEN) - 1) << GLB_UART_SIG_10_SEL_POS))
+#define GLB_UART_SIG_11_SEL GLB_UART_SIG_11_SEL
+#define GLB_UART_SIG_11_SEL_POS (12U)
+#define GLB_UART_SIG_11_SEL_LEN (4U)
+#define GLB_UART_SIG_11_SEL_MSK (((1U << GLB_UART_SIG_11_SEL_LEN) - 1) << GLB_UART_SIG_11_SEL_POS)
+#define GLB_UART_SIG_11_SEL_UMSK (~(((1U << GLB_UART_SIG_11_SEL_LEN) - 1) << GLB_UART_SIG_11_SEL_POS))
+
+/* 0x170 : sf_cfg0 */
+#define GLB_SF_CFG0_OFFSET (0x170)
+#define GLB_SF_CLK_DIV GLB_SF_CLK_DIV
+#define GLB_SF_CLK_DIV_POS (8U)
+#define GLB_SF_CLK_DIV_LEN (3U)
+#define GLB_SF_CLK_DIV_MSK (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
+#define GLB_SF_CLK_DIV_UMSK (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
+#define GLB_SF_CLK_EN GLB_SF_CLK_EN
+#define GLB_SF_CLK_EN_POS (11U)
+#define GLB_SF_CLK_EN_LEN (1U)
+#define GLB_SF_CLK_EN_MSK (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
+#define GLB_SF_CLK_EN_UMSK (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
+#define GLB_SF_CLK_SEL GLB_SF_CLK_SEL
+#define GLB_SF_CLK_SEL_POS (12U)
+#define GLB_SF_CLK_SEL_LEN (2U)
+#define GLB_SF_CLK_SEL_MSK (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
+#define GLB_SF_CLK_SEL_UMSK (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
+#define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2
+#define GLB_SF_CLK_SEL2_POS (14U)
+#define GLB_SF_CLK_SEL2_LEN (2U)
+#define GLB_SF_CLK_SEL2_MSK (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
+#define GLB_SF_CLK_SEL2_UMSK (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
+
+/* 0x180 : i2c_cfg0 */
+#define GLB_I2C_CFG0_OFFSET (0x180)
+#define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV
+#define GLB_I2C_CLK_DIV_POS (16U)
+#define GLB_I2C_CLK_DIV_LEN (8U)
+#define GLB_I2C_CLK_DIV_MSK (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
+#define GLB_I2C_CLK_DIV_UMSK (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
+#define GLB_I2C_CLK_EN GLB_I2C_CLK_EN
+#define GLB_I2C_CLK_EN_POS (24U)
+#define GLB_I2C_CLK_EN_LEN (1U)
+#define GLB_I2C_CLK_EN_MSK (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
+#define GLB_I2C_CLK_EN_UMSK (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
+#define GLB_I2C_CLK_SEL GLB_I2C_CLK_SEL
+#define GLB_I2C_CLK_SEL_POS (25U)
+#define GLB_I2C_CLK_SEL_LEN (1U)
+#define GLB_I2C_CLK_SEL_MSK (((1U << GLB_I2C_CLK_SEL_LEN) - 1) << GLB_I2C_CLK_SEL_POS)
+#define GLB_I2C_CLK_SEL_UMSK (~(((1U << GLB_I2C_CLK_SEL_LEN) - 1) << GLB_I2C_CLK_SEL_POS))
+
+/* 0x190 : i2s_cfg0 */
+#define GLB_I2S_CFG0_OFFSET (0x190)
+#define GLB_REG_I2S_REF_CLK_DIV GLB_REG_I2S_REF_CLK_DIV
+#define GLB_REG_I2S_REF_CLK_DIV_POS (0U)
+#define GLB_REG_I2S_REF_CLK_DIV_LEN (6U)
+#define GLB_REG_I2S_REF_CLK_DIV_MSK (((1U << GLB_REG_I2S_REF_CLK_DIV_LEN) - 1) << GLB_REG_I2S_REF_CLK_DIV_POS)
+#define GLB_REG_I2S_REF_CLK_DIV_UMSK (~(((1U << GLB_REG_I2S_REF_CLK_DIV_LEN) - 1) << GLB_REG_I2S_REF_CLK_DIV_POS))
+#define GLB_REG_I2S_DI_REF_CLK_SEL GLB_REG_I2S_DI_REF_CLK_SEL
+#define GLB_REG_I2S_DI_REF_CLK_SEL_POS (6U)
+#define GLB_REG_I2S_DI_REF_CLK_SEL_LEN (1U)
+#define GLB_REG_I2S_DI_REF_CLK_SEL_MSK (((1U << GLB_REG_I2S_DI_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DI_REF_CLK_SEL_POS)
+#define GLB_REG_I2S_DI_REF_CLK_SEL_UMSK (~(((1U << GLB_REG_I2S_DI_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DI_REF_CLK_SEL_POS))
+#define GLB_REG_I2S_REF_CLK_EN GLB_REG_I2S_REF_CLK_EN
+#define GLB_REG_I2S_REF_CLK_EN_POS (7U)
+#define GLB_REG_I2S_REF_CLK_EN_LEN (1U)
+#define GLB_REG_I2S_REF_CLK_EN_MSK (((1U << GLB_REG_I2S_REF_CLK_EN_LEN) - 1) << GLB_REG_I2S_REF_CLK_EN_POS)
+#define GLB_REG_I2S_REF_CLK_EN_UMSK (~(((1U << GLB_REG_I2S_REF_CLK_EN_LEN) - 1) << GLB_REG_I2S_REF_CLK_EN_POS))
+#define GLB_REG_I2S_DO_REF_CLK_SEL GLB_REG_I2S_DO_REF_CLK_SEL
+#define GLB_REG_I2S_DO_REF_CLK_SEL_POS (8U)
+#define GLB_REG_I2S_DO_REF_CLK_SEL_LEN (1U)
+#define GLB_REG_I2S_DO_REF_CLK_SEL_MSK (((1U << GLB_REG_I2S_DO_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DO_REF_CLK_SEL_POS)
+#define GLB_REG_I2S_DO_REF_CLK_SEL_UMSK (~(((1U << GLB_REG_I2S_DO_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DO_REF_CLK_SEL_POS))
+
+/* 0x1B0 : spi_cfg0 */
+#define GLB_SPI_CFG0_OFFSET (0x1B0)
+#define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV
+#define GLB_SPI_CLK_DIV_POS (0U)
+#define GLB_SPI_CLK_DIV_LEN (5U)
+#define GLB_SPI_CLK_DIV_MSK (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
+#define GLB_SPI_CLK_DIV_UMSK (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
+#define GLB_SPI_CLK_EN GLB_SPI_CLK_EN
+#define GLB_SPI_CLK_EN_POS (8U)
+#define GLB_SPI_CLK_EN_LEN (1U)
+#define GLB_SPI_CLK_EN_MSK (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
+#define GLB_SPI_CLK_EN_UMSK (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
+#define GLB_SPI_CLK_SEL GLB_SPI_CLK_SEL
+#define GLB_SPI_CLK_SEL_POS (9U)
+#define GLB_SPI_CLK_SEL_LEN (1U)
+#define GLB_SPI_CLK_SEL_MSK (((1U << GLB_SPI_CLK_SEL_LEN) - 1) << GLB_SPI_CLK_SEL_POS)
+#define GLB_SPI_CLK_SEL_UMSK (~(((1U << GLB_SPI_CLK_SEL_LEN) - 1) << GLB_SPI_CLK_SEL_POS))
+#define GLB_SPI_SWAP_SET GLB_SPI_SWAP_SET
+#define GLB_SPI_SWAP_SET_POS (16U)
+#define GLB_SPI_SWAP_SET_LEN (4U)
+#define GLB_SPI_SWAP_SET_MSK (((1U << GLB_SPI_SWAP_SET_LEN) - 1) << GLB_SPI_SWAP_SET_POS)
+#define GLB_SPI_SWAP_SET_UMSK (~(((1U << GLB_SPI_SWAP_SET_LEN) - 1) << GLB_SPI_SWAP_SET_POS))
+
+/* 0x1C0 : qdec_cfg0 */
+#define GLB_QDEC_CFG0_OFFSET (0x1C0)
+
+/* 0x1D0 : pwm_cfg0 */
+#define GLB_PWM_CFG0_OFFSET (0x1D0)
+#define GLB_REG_PWM1_IO_SEL GLB_REG_PWM1_IO_SEL
+#define GLB_REG_PWM1_IO_SEL_POS (0U)
+#define GLB_REG_PWM1_IO_SEL_LEN (1U)
+#define GLB_REG_PWM1_IO_SEL_MSK (((1U << GLB_REG_PWM1_IO_SEL_LEN) - 1) << GLB_REG_PWM1_IO_SEL_POS)
+#define GLB_REG_PWM1_IO_SEL_UMSK (~(((1U << GLB_REG_PWM1_IO_SEL_LEN) - 1) << GLB_REG_PWM1_IO_SEL_POS))
+#define GLB_REG_PWM2_IO_SEL GLB_REG_PWM2_IO_SEL
+#define GLB_REG_PWM2_IO_SEL_POS (1U)
+#define GLB_REG_PWM2_IO_SEL_LEN (1U)
+#define GLB_REG_PWM2_IO_SEL_MSK (((1U << GLB_REG_PWM2_IO_SEL_LEN) - 1) << GLB_REG_PWM2_IO_SEL_POS)
+#define GLB_REG_PWM2_IO_SEL_UMSK (~(((1U << GLB_REG_PWM2_IO_SEL_LEN) - 1) << GLB_REG_PWM2_IO_SEL_POS))
+
+/* 0x1E0 : pdm_cfg0 */
+#define GLB_PDM_CFG0_OFFSET (0x1E0)
+#define GLB_REG_PDM_IO_SEL GLB_REG_PDM_IO_SEL
+#define GLB_REG_PDM_IO_SEL_POS (0U)
+#define GLB_REG_PDM_IO_SEL_LEN (1U)
+#define GLB_REG_PDM_IO_SEL_MSK (((1U << GLB_REG_PDM_IO_SEL_LEN) - 1) << GLB_REG_PDM_IO_SEL_POS)
+#define GLB_REG_PDM_IO_SEL_UMSK (~(((1U << GLB_REG_PDM_IO_SEL_LEN) - 1) << GLB_REG_PDM_IO_SEL_POS))
+
+/* 0x250 : dig_clk_cfg0 */
+#define GLB_DIG_CLK_CFG0_OFFSET (0x250)
+#define GLB_DIG_32K_DIV GLB_DIG_32K_DIV
+#define GLB_DIG_32K_DIV_POS (0U)
+#define GLB_DIG_32K_DIV_LEN (11U)
+#define GLB_DIG_32K_DIV_MSK (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
+#define GLB_DIG_32K_DIV_UMSK (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
+#define GLB_DIG_32K_EN GLB_DIG_32K_EN
+#define GLB_DIG_32K_EN_POS (12U)
+#define GLB_DIG_32K_EN_LEN (1U)
+#define GLB_DIG_32K_EN_MSK (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
+#define GLB_DIG_32K_EN_UMSK (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
+#define GLB_DIG_32K_COMP GLB_DIG_32K_COMP
+#define GLB_DIG_32K_COMP_POS (13U)
+#define GLB_DIG_32K_COMP_LEN (1U)
+#define GLB_DIG_32K_COMP_MSK (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
+#define GLB_DIG_32K_COMP_UMSK (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
+#define GLB_DIG_512K_DIV GLB_DIG_512K_DIV
+#define GLB_DIG_512K_DIV_POS (16U)
+#define GLB_DIG_512K_DIV_LEN (7U)
+#define GLB_DIG_512K_DIV_MSK (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
+#define GLB_DIG_512K_DIV_UMSK (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
+#define GLB_DIG_512K_EN GLB_DIG_512K_EN
+#define GLB_DIG_512K_EN_POS (24U)
+#define GLB_DIG_512K_EN_LEN (1U)
+#define GLB_DIG_512K_EN_MSK (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
+#define GLB_DIG_512K_EN_UMSK (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
+#define GLB_DIG_512K_COMP GLB_DIG_512K_COMP
+#define GLB_DIG_512K_COMP_POS (25U)
+#define GLB_DIG_512K_COMP_LEN (1U)
+#define GLB_DIG_512K_COMP_MSK (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
+#define GLB_DIG_512K_COMP_UMSK (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
+#define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL
+#define GLB_DIG_CLK_SRC_SEL_POS (28U)
+#define GLB_DIG_CLK_SRC_SEL_LEN (2U)
+#define GLB_DIG_CLK_SRC_SEL_MSK (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
+#define GLB_DIG_CLK_SRC_SEL_UMSK (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
+#define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP
+#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_MSK (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)
+#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS))
+
+/* 0x254 : dig_clk_cfg1 */
+#define GLB_DIG_CLK_CFG1_OFFSET (0x254)
+#define GLB_REG_MM_MUXPLL_160M_SEL GLB_REG_MM_MUXPLL_160M_SEL
+#define GLB_REG_MM_MUXPLL_160M_SEL_POS (0U)
+#define GLB_REG_MM_MUXPLL_160M_SEL_LEN (1U)
+#define GLB_REG_MM_MUXPLL_160M_SEL_MSK (((1U << GLB_REG_MM_MUXPLL_160M_SEL_LEN) - 1) << GLB_REG_MM_MUXPLL_160M_SEL_POS)
+#define GLB_REG_MM_MUXPLL_160M_SEL_UMSK (~(((1U << GLB_REG_MM_MUXPLL_160M_SEL_LEN) - 1) << GLB_REG_MM_MUXPLL_160M_SEL_POS))
+#define GLB_REG_MM_MUXPLL_240M_SEL GLB_REG_MM_MUXPLL_240M_SEL
+#define GLB_REG_MM_MUXPLL_240M_SEL_POS (1U)
+#define GLB_REG_MM_MUXPLL_240M_SEL_LEN (1U)
+#define GLB_REG_MM_MUXPLL_240M_SEL_MSK (((1U << GLB_REG_MM_MUXPLL_240M_SEL_LEN) - 1) << GLB_REG_MM_MUXPLL_240M_SEL_POS)
+#define GLB_REG_MM_MUXPLL_240M_SEL_UMSK (~(((1U << GLB_REG_MM_MUXPLL_240M_SEL_LEN) - 1) << GLB_REG_MM_MUXPLL_240M_SEL_POS))
+#define GLB_REG_MM_MUXPLL_320M_SEL GLB_REG_MM_MUXPLL_320M_SEL
+#define GLB_REG_MM_MUXPLL_320M_SEL_POS (2U)
+#define GLB_REG_MM_MUXPLL_320M_SEL_LEN (1U)
+#define GLB_REG_MM_MUXPLL_320M_SEL_MSK (((1U << GLB_REG_MM_MUXPLL_320M_SEL_LEN) - 1) << GLB_REG_MM_MUXPLL_320M_SEL_POS)
+#define GLB_REG_MM_MUXPLL_320M_SEL_UMSK (~(((1U << GLB_REG_MM_MUXPLL_320M_SEL_LEN) - 1) << GLB_REG_MM_MUXPLL_320M_SEL_POS))
+#define GLB_REG_TOP_MUXPLL_80M_SEL GLB_REG_TOP_MUXPLL_80M_SEL
+#define GLB_REG_TOP_MUXPLL_80M_SEL_POS (8U)
+#define GLB_REG_TOP_MUXPLL_80M_SEL_LEN (2U)
+#define GLB_REG_TOP_MUXPLL_80M_SEL_MSK (((1U << GLB_REG_TOP_MUXPLL_80M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_80M_SEL_POS)
+#define GLB_REG_TOP_MUXPLL_80M_SEL_UMSK (~(((1U << GLB_REG_TOP_MUXPLL_80M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_80M_SEL_POS))
+#define GLB_REG_TOP_MUXPLL_160M_SEL GLB_REG_TOP_MUXPLL_160M_SEL
+#define GLB_REG_TOP_MUXPLL_160M_SEL_POS (10U)
+#define GLB_REG_TOP_MUXPLL_160M_SEL_LEN (2U)
+#define GLB_REG_TOP_MUXPLL_160M_SEL_MSK (((1U << GLB_REG_TOP_MUXPLL_160M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_160M_SEL_POS)
+#define GLB_REG_TOP_MUXPLL_160M_SEL_UMSK (~(((1U << GLB_REG_TOP_MUXPLL_160M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_160M_SEL_POS))
+
+/* 0x258 : dig_clk_cfg2 */
+#define GLB_DIG_CLK_CFG2_OFFSET (0x258)
+#define GLB_CHIP_CLK_OUT_0_SEL GLB_CHIP_CLK_OUT_0_SEL
+#define GLB_CHIP_CLK_OUT_0_SEL_POS (0U)
+#define GLB_CHIP_CLK_OUT_0_SEL_LEN (2U)
+#define GLB_CHIP_CLK_OUT_0_SEL_MSK (((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS)
+#define GLB_CHIP_CLK_OUT_0_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS))
+#define GLB_CHIP_CLK_OUT_1_SEL GLB_CHIP_CLK_OUT_1_SEL
+#define GLB_CHIP_CLK_OUT_1_SEL_POS (2U)
+#define GLB_CHIP_CLK_OUT_1_SEL_LEN (2U)
+#define GLB_CHIP_CLK_OUT_1_SEL_MSK (((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS)
+#define GLB_CHIP_CLK_OUT_1_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS))
+#define GLB_CHIP_CLK_OUT_2_SEL GLB_CHIP_CLK_OUT_2_SEL
+#define GLB_CHIP_CLK_OUT_2_SEL_POS (4U)
+#define GLB_CHIP_CLK_OUT_2_SEL_LEN (2U)
+#define GLB_CHIP_CLK_OUT_2_SEL_MSK (((1U << GLB_CHIP_CLK_OUT_2_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_2_SEL_POS)
+#define GLB_CHIP_CLK_OUT_2_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_2_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_2_SEL_POS))
+#define GLB_CHIP_CLK_OUT_3_SEL GLB_CHIP_CLK_OUT_3_SEL
+#define GLB_CHIP_CLK_OUT_3_SEL_POS (6U)
+#define GLB_CHIP_CLK_OUT_3_SEL_LEN (2U)
+#define GLB_CHIP_CLK_OUT_3_SEL_MSK (((1U << GLB_CHIP_CLK_OUT_3_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_3_SEL_POS)
+#define GLB_CHIP_CLK_OUT_3_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_3_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_3_SEL_POS))
+#define GLB_CHIP_CLK_OUT_0_EN GLB_CHIP_CLK_OUT_0_EN
+#define GLB_CHIP_CLK_OUT_0_EN_POS (8U)
+#define GLB_CHIP_CLK_OUT_0_EN_LEN (1U)
+#define GLB_CHIP_CLK_OUT_0_EN_MSK (((1U << GLB_CHIP_CLK_OUT_0_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_0_EN_POS)
+#define GLB_CHIP_CLK_OUT_0_EN_UMSK (~(((1U << GLB_CHIP_CLK_OUT_0_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_0_EN_POS))
+#define GLB_CHIP_CLK_OUT_1_EN GLB_CHIP_CLK_OUT_1_EN
+#define GLB_CHIP_CLK_OUT_1_EN_POS (9U)
+#define GLB_CHIP_CLK_OUT_1_EN_LEN (1U)
+#define GLB_CHIP_CLK_OUT_1_EN_MSK (((1U << GLB_CHIP_CLK_OUT_1_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_1_EN_POS)
+#define GLB_CHIP_CLK_OUT_1_EN_UMSK (~(((1U << GLB_CHIP_CLK_OUT_1_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_1_EN_POS))
+#define GLB_CHIP_CLK_OUT_2_EN GLB_CHIP_CLK_OUT_2_EN
+#define GLB_CHIP_CLK_OUT_2_EN_POS (10U)
+#define GLB_CHIP_CLK_OUT_2_EN_LEN (1U)
+#define GLB_CHIP_CLK_OUT_2_EN_MSK (((1U << GLB_CHIP_CLK_OUT_2_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_2_EN_POS)
+#define GLB_CHIP_CLK_OUT_2_EN_UMSK (~(((1U << GLB_CHIP_CLK_OUT_2_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_2_EN_POS))
+#define GLB_CHIP_CLK_OUT_3_EN GLB_CHIP_CLK_OUT_3_EN
+#define GLB_CHIP_CLK_OUT_3_EN_POS (11U)
+#define GLB_CHIP_CLK_OUT_3_EN_LEN (1U)
+#define GLB_CHIP_CLK_OUT_3_EN_MSK (((1U << GLB_CHIP_CLK_OUT_3_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_3_EN_POS)
+#define GLB_CHIP_CLK_OUT_3_EN_UMSK (~(((1U << GLB_CHIP_CLK_OUT_3_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_3_EN_POS))
+#define GLB_GPIO_TMR_CLK_SEL GLB_GPIO_TMR_CLK_SEL
+#define GLB_GPIO_TMR_CLK_SEL_POS (12U)
+#define GLB_GPIO_TMR_CLK_SEL_LEN (2U)
+#define GLB_GPIO_TMR_CLK_SEL_MSK (((1U << GLB_GPIO_TMR_CLK_SEL_LEN) - 1) << GLB_GPIO_TMR_CLK_SEL_POS)
+#define GLB_GPIO_TMR_CLK_SEL_UMSK (~(((1U << GLB_GPIO_TMR_CLK_SEL_LEN) - 1) << GLB_GPIO_TMR_CLK_SEL_POS))
+#define GLB_GPIO_MM_TMR_CLK_SEL GLB_GPIO_MM_TMR_CLK_SEL
+#define GLB_GPIO_MM_TMR_CLK_SEL_POS (14U)
+#define GLB_GPIO_MM_TMR_CLK_SEL_LEN (2U)
+#define GLB_GPIO_MM_TMR_CLK_SEL_MSK (((1U << GLB_GPIO_MM_TMR_CLK_SEL_LEN) - 1) << GLB_GPIO_MM_TMR_CLK_SEL_POS)
+#define GLB_GPIO_MM_TMR_CLK_SEL_UMSK (~(((1U << GLB_GPIO_MM_TMR_CLK_SEL_LEN) - 1) << GLB_GPIO_MM_TMR_CLK_SEL_POS))
+
+/* 0x25C : dig_clk_cfg3 */
+#define GLB_DIG_CLK_CFG3_OFFSET (0x25C)
+#define GLB_DSI_TXCLKESC_SEL GLB_DSI_TXCLKESC_SEL
+#define GLB_DSI_TXCLKESC_SEL_POS (0U)
+#define GLB_DSI_TXCLKESC_SEL_LEN (1U)
+#define GLB_DSI_TXCLKESC_SEL_MSK (((1U << GLB_DSI_TXCLKESC_SEL_LEN) - 1) << GLB_DSI_TXCLKESC_SEL_POS)
+#define GLB_DSI_TXCLKESC_SEL_UMSK (~(((1U << GLB_DSI_TXCLKESC_SEL_LEN) - 1) << GLB_DSI_TXCLKESC_SEL_POS))
+#define GLB_CSI_TXCLKESC_SEL GLB_CSI_TXCLKESC_SEL
+#define GLB_CSI_TXCLKESC_SEL_POS (1U)
+#define GLB_CSI_TXCLKESC_SEL_LEN (1U)
+#define GLB_CSI_TXCLKESC_SEL_MSK (((1U << GLB_CSI_TXCLKESC_SEL_LEN) - 1) << GLB_CSI_TXCLKESC_SEL_POS)
+#define GLB_CSI_TXCLKESC_SEL_UMSK (~(((1U << GLB_CSI_TXCLKESC_SEL_LEN) - 1) << GLB_CSI_TXCLKESC_SEL_POS))
+
+/* 0x260 : rf_cfg0 */
+#define GLB_RF_CFG0_OFFSET (0x260)
+#define GLB_CFG_INV_RF2_TEST_CLK_O GLB_CFG_INV_RF2_TEST_CLK_O
+#define GLB_CFG_INV_RF2_TEST_CLK_O_POS (9U)
+#define GLB_CFG_INV_RF2_TEST_CLK_O_LEN (1U)
+#define GLB_CFG_INV_RF2_TEST_CLK_O_MSK (((1U << GLB_CFG_INV_RF2_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF2_TEST_CLK_O_POS)
+#define GLB_CFG_INV_RF2_TEST_CLK_O_UMSK (~(((1U << GLB_CFG_INV_RF2_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF2_TEST_CLK_O_POS))
+
+/* 0x2E0 : dbg_cfg0 */
+#define GLB_DBG_CFG0_OFFSET (0x2E0)
+#define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL
+#define GLB_REG_DBG_LL_CTRL_POS (0U)
+#define GLB_REG_DBG_LL_CTRL_LEN (30U)
+#define GLB_REG_DBG_LL_CTRL_MSK (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
+#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
+#define GLB_REG_DBG_LL_SEL GLB_REG_DBG_LL_SEL
+#define GLB_REG_DBG_LL_SEL_POS (30U)
+#define GLB_REG_DBG_LL_SEL_LEN (2U)
+#define GLB_REG_DBG_LL_SEL_MSK (((1U << GLB_REG_DBG_LL_SEL_LEN) - 1) << GLB_REG_DBG_LL_SEL_POS)
+#define GLB_REG_DBG_LL_SEL_UMSK (~(((1U << GLB_REG_DBG_LL_SEL_LEN) - 1) << GLB_REG_DBG_LL_SEL_POS))
+
+/* 0x2E4 : dbg_cfg1 */
+#define GLB_DBG_CFG1_OFFSET (0x2E4)
+#define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL
+#define GLB_REG_DBG_LH_CTRL_POS (0U)
+#define GLB_REG_DBG_LH_CTRL_LEN (30U)
+#define GLB_REG_DBG_LH_CTRL_MSK (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
+#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
+#define GLB_REG_DBG_LH_SEL GLB_REG_DBG_LH_SEL
+#define GLB_REG_DBG_LH_SEL_POS (30U)
+#define GLB_REG_DBG_LH_SEL_LEN (2U)
+#define GLB_REG_DBG_LH_SEL_MSK (((1U << GLB_REG_DBG_LH_SEL_LEN) - 1) << GLB_REG_DBG_LH_SEL_POS)
+#define GLB_REG_DBG_LH_SEL_UMSK (~(((1U << GLB_REG_DBG_LH_SEL_LEN) - 1) << GLB_REG_DBG_LH_SEL_POS))
+
+/* 0x2E8 : dbg_cfg2 */
+#define GLB_DBG_CFG2_OFFSET (0x2E8)
+#define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL
+#define GLB_REG_DBG_HL_CTRL_POS (0U)
+#define GLB_REG_DBG_HL_CTRL_LEN (30U)
+#define GLB_REG_DBG_HL_CTRL_MSK (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
+#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
+#define GLB_REG_DBG_HL_SEL GLB_REG_DBG_HL_SEL
+#define GLB_REG_DBG_HL_SEL_POS (30U)
+#define GLB_REG_DBG_HL_SEL_LEN (2U)
+#define GLB_REG_DBG_HL_SEL_MSK (((1U << GLB_REG_DBG_HL_SEL_LEN) - 1) << GLB_REG_DBG_HL_SEL_POS)
+#define GLB_REG_DBG_HL_SEL_UMSK (~(((1U << GLB_REG_DBG_HL_SEL_LEN) - 1) << GLB_REG_DBG_HL_SEL_POS))
+
+/* 0x2EC : dbg_cfg3 */
+#define GLB_DBG_CFG3_OFFSET (0x2EC)
+#define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL
+#define GLB_REG_DBG_HH_CTRL_POS (0U)
+#define GLB_REG_DBG_HH_CTRL_LEN (30U)
+#define GLB_REG_DBG_HH_CTRL_MSK (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
+#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
+#define GLB_REG_DBG_HH_SEL GLB_REG_DBG_HH_SEL
+#define GLB_REG_DBG_HH_SEL_POS (30U)
+#define GLB_REG_DBG_HH_SEL_LEN (2U)
+#define GLB_REG_DBG_HH_SEL_MSK (((1U << GLB_REG_DBG_HH_SEL_LEN) - 1) << GLB_REG_DBG_HH_SEL_POS)
+#define GLB_REG_DBG_HH_SEL_UMSK (~(((1U << GLB_REG_DBG_HH_SEL_LEN) - 1) << GLB_REG_DBG_HH_SEL_POS))
+
+/* 0x2F0 : dbg_cfg4 */
+#define GLB_DBG_CFG4_OFFSET (0x2F0)
+#define GLB_DEBUG_OE GLB_DEBUG_OE
+#define GLB_DEBUG_OE_POS (0U)
+#define GLB_DEBUG_OE_LEN (1U)
+#define GLB_DEBUG_OE_MSK (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
+#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
+#define GLB_DEBUG_I GLB_DEBUG_I
+#define GLB_DEBUG_I_POS (1U)
+#define GLB_DEBUG_I_LEN (31U)
+#define GLB_DEBUG_I_MSK (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
+#define GLB_DEBUG_I_UMSK (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
+
+/* 0x300 : mbist_cfg0 */
+#define GLB_MBIST_CFG0_OFFSET (0x300)
+#define GLB_MBIST_MODE GLB_MBIST_MODE
+#define GLB_MBIST_MODE_POS (0U)
+#define GLB_MBIST_MODE_LEN (1U)
+#define GLB_MBIST_MODE_MSK (((1U << GLB_MBIST_MODE_LEN) - 1) << GLB_MBIST_MODE_POS)
+#define GLB_MBIST_MODE_UMSK (~(((1U << GLB_MBIST_MODE_LEN) - 1) << GLB_MBIST_MODE_POS))
+
+/* 0x320 : bmx_cfg0 */
+#define GLB_BMX_CFG0_OFFSET (0x320)
+#define GLB_REG_BMX_TIMEOUT_EN GLB_REG_BMX_TIMEOUT_EN
+#define GLB_REG_BMX_TIMEOUT_EN_POS (0U)
+#define GLB_REG_BMX_TIMEOUT_EN_LEN (5U)
+#define GLB_REG_BMX_TIMEOUT_EN_MSK (((1U << GLB_REG_BMX_TIMEOUT_EN_LEN) - 1) << GLB_REG_BMX_TIMEOUT_EN_POS)
+#define GLB_REG_BMX_TIMEOUT_EN_UMSK (~(((1U << GLB_REG_BMX_TIMEOUT_EN_LEN) - 1) << GLB_REG_BMX_TIMEOUT_EN_POS))
+#define GLB_REG_BMX_ARB_MODE GLB_REG_BMX_ARB_MODE
+#define GLB_REG_BMX_ARB_MODE_POS (5U)
+#define GLB_REG_BMX_ARB_MODE_LEN (1U)
+#define GLB_REG_BMX_ARB_MODE_MSK (((1U << GLB_REG_BMX_ARB_MODE_LEN) - 1) << GLB_REG_BMX_ARB_MODE_POS)
+#define GLB_REG_BMX_ARB_MODE_UMSK (~(((1U << GLB_REG_BMX_ARB_MODE_LEN) - 1) << GLB_REG_BMX_ARB_MODE_POS))
+#define GLB_REG_BMX_TIMEOUT_CLR GLB_REG_BMX_TIMEOUT_CLR
+#define GLB_REG_BMX_TIMEOUT_CLR_POS (6U)
+#define GLB_REG_BMX_TIMEOUT_CLR_LEN (1U)
+#define GLB_REG_BMX_TIMEOUT_CLR_MSK (((1U << GLB_REG_BMX_TIMEOUT_CLR_LEN) - 1) << GLB_REG_BMX_TIMEOUT_CLR_POS)
+#define GLB_REG_BMX_TIMEOUT_CLR_UMSK (~(((1U << GLB_REG_BMX_TIMEOUT_CLR_LEN) - 1) << GLB_REG_BMX_TIMEOUT_CLR_POS))
+#define GLB_REG_H_WTHRE_HW2EXT GLB_REG_H_WTHRE_HW2EXT
+#define GLB_REG_H_WTHRE_HW2EXT_POS (7U)
+#define GLB_REG_H_WTHRE_HW2EXT_LEN (2U)
+#define GLB_REG_H_WTHRE_HW2EXT_MSK (((1U << GLB_REG_H_WTHRE_HW2EXT_LEN) - 1) << GLB_REG_H_WTHRE_HW2EXT_POS)
+#define GLB_REG_H_WTHRE_HW2EXT_UMSK (~(((1U << GLB_REG_H_WTHRE_HW2EXT_LEN) - 1) << GLB_REG_H_WTHRE_HW2EXT_POS))
+#define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS
+#define GLB_BMX_BUSY_OPTION_DIS_POS (9U)
+#define GLB_BMX_BUSY_OPTION_DIS_LEN (1U)
+#define GLB_BMX_BUSY_OPTION_DIS_MSK (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
+#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS))
+#define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS
+#define GLB_BMX_GATING_DIS_POS (10U)
+#define GLB_BMX_GATING_DIS_LEN (1U)
+#define GLB_BMX_GATING_DIS_MSK (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
+#define GLB_BMX_GATING_DIS_UMSK (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
+#define GLB_STS_BMX_TIMEOUT_STS GLB_STS_BMX_TIMEOUT_STS
+#define GLB_STS_BMX_TIMEOUT_STS_POS (11U)
+#define GLB_STS_BMX_TIMEOUT_STS_LEN (5U)
+#define GLB_STS_BMX_TIMEOUT_STS_MSK (((1U << GLB_STS_BMX_TIMEOUT_STS_LEN) - 1) << GLB_STS_BMX_TIMEOUT_STS_POS)
+#define GLB_STS_BMX_TIMEOUT_STS_UMSK (~(((1U << GLB_STS_BMX_TIMEOUT_STS_LEN) - 1) << GLB_STS_BMX_TIMEOUT_STS_POS))
+#define GLB_PDS_APB_CFG GLB_PDS_APB_CFG
+#define GLB_PDS_APB_CFG_POS (16U)
+#define GLB_PDS_APB_CFG_LEN (8U)
+#define GLB_PDS_APB_CFG_MSK (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
+#define GLB_PDS_APB_CFG_UMSK (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
+#define GLB_HBN_APB_CFG GLB_HBN_APB_CFG
+#define GLB_HBN_APB_CFG_POS (24U)
+#define GLB_HBN_APB_CFG_LEN (8U)
+#define GLB_HBN_APB_CFG_MSK (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
+#define GLB_HBN_APB_CFG_UMSK (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
+
+/* 0x324 : bmx_cfg1 */
+#define GLB_BMX_CFG1_OFFSET (0x324)
+#define GLB_REG_BMX_BERR_INT_EN GLB_REG_BMX_BERR_INT_EN
+#define GLB_REG_BMX_BERR_INT_EN_POS (0U)
+#define GLB_REG_BMX_BERR_INT_EN_LEN (1U)
+#define GLB_REG_BMX_BERR_INT_EN_MSK (((1U << GLB_REG_BMX_BERR_INT_EN_LEN) - 1) << GLB_REG_BMX_BERR_INT_EN_POS)
+#define GLB_REG_BMX_BERR_INT_EN_UMSK (~(((1U << GLB_REG_BMX_BERR_INT_EN_LEN) - 1) << GLB_REG_BMX_BERR_INT_EN_POS))
+#define GLB_REG_MCU_BERR_INT_EN GLB_REG_MCU_BERR_INT_EN
+#define GLB_REG_MCU_BERR_INT_EN_POS (1U)
+#define GLB_REG_MCU_BERR_INT_EN_LEN (1U)
+#define GLB_REG_MCU_BERR_INT_EN_MSK (((1U << GLB_REG_MCU_BERR_INT_EN_LEN) - 1) << GLB_REG_MCU_BERR_INT_EN_POS)
+#define GLB_REG_MCU_BERR_INT_EN_UMSK (~(((1U << GLB_REG_MCU_BERR_INT_EN_LEN) - 1) << GLB_REG_MCU_BERR_INT_EN_POS))
+#define GLB_REG_BMX_QOS_CPU GLB_REG_BMX_QOS_CPU
+#define GLB_REG_BMX_QOS_CPU_POS (16U)
+#define GLB_REG_BMX_QOS_CPU_LEN (1U)
+#define GLB_REG_BMX_QOS_CPU_MSK (((1U << GLB_REG_BMX_QOS_CPU_LEN) - 1) << GLB_REG_BMX_QOS_CPU_POS)
+#define GLB_REG_BMX_QOS_CPU_UMSK (~(((1U << GLB_REG_BMX_QOS_CPU_LEN) - 1) << GLB_REG_BMX_QOS_CPU_POS))
+#define GLB_REG_BMX_QOS_SDU GLB_REG_BMX_QOS_SDU
+#define GLB_REG_BMX_QOS_SDU_POS (17U)
+#define GLB_REG_BMX_QOS_SDU_LEN (1U)
+#define GLB_REG_BMX_QOS_SDU_MSK (((1U << GLB_REG_BMX_QOS_SDU_LEN) - 1) << GLB_REG_BMX_QOS_SDU_POS)
+#define GLB_REG_BMX_QOS_SDU_UMSK (~(((1U << GLB_REG_BMX_QOS_SDU_LEN) - 1) << GLB_REG_BMX_QOS_SDU_POS))
+#define GLB_REG_BMX_QOS_SEC0 GLB_REG_BMX_QOS_SEC0
+#define GLB_REG_BMX_QOS_SEC0_POS (18U)
+#define GLB_REG_BMX_QOS_SEC0_LEN (1U)
+#define GLB_REG_BMX_QOS_SEC0_MSK (((1U << GLB_REG_BMX_QOS_SEC0_LEN) - 1) << GLB_REG_BMX_QOS_SEC0_POS)
+#define GLB_REG_BMX_QOS_SEC0_UMSK (~(((1U << GLB_REG_BMX_QOS_SEC0_LEN) - 1) << GLB_REG_BMX_QOS_SEC0_POS))
+#define GLB_REG_BMX_QOS_SEC1 GLB_REG_BMX_QOS_SEC1
+#define GLB_REG_BMX_QOS_SEC1_POS (19U)
+#define GLB_REG_BMX_QOS_SEC1_LEN (1U)
+#define GLB_REG_BMX_QOS_SEC1_MSK (((1U << GLB_REG_BMX_QOS_SEC1_LEN) - 1) << GLB_REG_BMX_QOS_SEC1_POS)
+#define GLB_REG_BMX_QOS_SEC1_UMSK (~(((1U << GLB_REG_BMX_QOS_SEC1_LEN) - 1) << GLB_REG_BMX_QOS_SEC1_POS))
+#define GLB_REG_BMX_QOS_SEC2 GLB_REG_BMX_QOS_SEC2
+#define GLB_REG_BMX_QOS_SEC2_POS (20U)
+#define GLB_REG_BMX_QOS_SEC2_LEN (1U)
+#define GLB_REG_BMX_QOS_SEC2_MSK (((1U << GLB_REG_BMX_QOS_SEC2_LEN) - 1) << GLB_REG_BMX_QOS_SEC2_POS)
+#define GLB_REG_BMX_QOS_SEC2_UMSK (~(((1U << GLB_REG_BMX_QOS_SEC2_LEN) - 1) << GLB_REG_BMX_QOS_SEC2_POS))
+#define GLB_REG_BMX_QOS_DMA GLB_REG_BMX_QOS_DMA
+#define GLB_REG_BMX_QOS_DMA_POS (21U)
+#define GLB_REG_BMX_QOS_DMA_LEN (1U)
+#define GLB_REG_BMX_QOS_DMA_MSK (((1U << GLB_REG_BMX_QOS_DMA_LEN) - 1) << GLB_REG_BMX_QOS_DMA_POS)
+#define GLB_REG_BMX_QOS_DMA_UMSK (~(((1U << GLB_REG_BMX_QOS_DMA_LEN) - 1) << GLB_REG_BMX_QOS_DMA_POS))
+#define GLB_REG_BMX_QOS_CCI GLB_REG_BMX_QOS_CCI
+#define GLB_REG_BMX_QOS_CCI_POS (22U)
+#define GLB_REG_BMX_QOS_CCI_LEN (1U)
+#define GLB_REG_BMX_QOS_CCI_MSK (((1U << GLB_REG_BMX_QOS_CCI_LEN) - 1) << GLB_REG_BMX_QOS_CCI_POS)
+#define GLB_REG_BMX_QOS_CCI_UMSK (~(((1U << GLB_REG_BMX_QOS_CCI_LEN) - 1) << GLB_REG_BMX_QOS_CCI_POS))
+#define GLB_REG_BMX_QOS_PLDMA GLB_REG_BMX_QOS_PLDMA
+#define GLB_REG_BMX_QOS_PLDMA_POS (23U)
+#define GLB_REG_BMX_QOS_PLDMA_LEN (1U)
+#define GLB_REG_BMX_QOS_PLDMA_MSK (((1U << GLB_REG_BMX_QOS_PLDMA_LEN) - 1) << GLB_REG_BMX_QOS_PLDMA_POS)
+#define GLB_REG_BMX_QOS_PLDMA_UMSK (~(((1U << GLB_REG_BMX_QOS_PLDMA_LEN) - 1) << GLB_REG_BMX_QOS_PLDMA_POS))
+#define GLB_REG_BMX_QOS_BLEM GLB_REG_BMX_QOS_BLEM
+#define GLB_REG_BMX_QOS_BLEM_POS (24U)
+#define GLB_REG_BMX_QOS_BLEM_LEN (1U)
+#define GLB_REG_BMX_QOS_BLEM_MSK (((1U << GLB_REG_BMX_QOS_BLEM_LEN) - 1) << GLB_REG_BMX_QOS_BLEM_POS)
+#define GLB_REG_BMX_QOS_BLEM_UMSK (~(((1U << GLB_REG_BMX_QOS_BLEM_LEN) - 1) << GLB_REG_BMX_QOS_BLEM_POS))
+#define GLB_REG_BMX_QOS_EMACA GLB_REG_BMX_QOS_EMACA
+#define GLB_REG_BMX_QOS_EMACA_POS (25U)
+#define GLB_REG_BMX_QOS_EMACA_LEN (1U)
+#define GLB_REG_BMX_QOS_EMACA_MSK (((1U << GLB_REG_BMX_QOS_EMACA_LEN) - 1) << GLB_REG_BMX_QOS_EMACA_POS)
+#define GLB_REG_BMX_QOS_EMACA_UMSK (~(((1U << GLB_REG_BMX_QOS_EMACA_LEN) - 1) << GLB_REG_BMX_QOS_EMACA_POS))
+#define GLB_REG_BMX_QOS_DMA2 GLB_REG_BMX_QOS_DMA2
+#define GLB_REG_BMX_QOS_DMA2_POS (26U)
+#define GLB_REG_BMX_QOS_DMA2_LEN (1U)
+#define GLB_REG_BMX_QOS_DMA2_MSK (((1U << GLB_REG_BMX_QOS_DMA2_LEN) - 1) << GLB_REG_BMX_QOS_DMA2_POS)
+#define GLB_REG_BMX_QOS_DMA2_UMSK (~(((1U << GLB_REG_BMX_QOS_DMA2_LEN) - 1) << GLB_REG_BMX_QOS_DMA2_POS))
+#define GLB_REG_BMX_QOS_SDHM GLB_REG_BMX_QOS_SDHM
+#define GLB_REG_BMX_QOS_SDHM_POS (27U)
+#define GLB_REG_BMX_QOS_SDHM_LEN (1U)
+#define GLB_REG_BMX_QOS_SDHM_MSK (((1U << GLB_REG_BMX_QOS_SDHM_LEN) - 1) << GLB_REG_BMX_QOS_SDHM_POS)
+#define GLB_REG_BMX_QOS_SDHM_UMSK (~(((1U << GLB_REG_BMX_QOS_SDHM_LEN) - 1) << GLB_REG_BMX_QOS_SDHM_POS))
+#define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL
+#define GLB_BMX_DBG_SEL_POS (28U)
+#define GLB_BMX_DBG_SEL_LEN (4U)
+#define GLB_BMX_DBG_SEL_MSK (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
+#define GLB_BMX_DBG_SEL_UMSK (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
+
+/* 0x328 : bmx_cfg2 */
+#define GLB_BMX_CFG2_OFFSET (0x328)
+#define GLB_REG_BMX_BERR_EN GLB_REG_BMX_BERR_EN
+#define GLB_REG_BMX_BERR_EN_POS (0U)
+#define GLB_REG_BMX_BERR_EN_LEN (14U)
+#define GLB_REG_BMX_BERR_EN_MSK (((1U << GLB_REG_BMX_BERR_EN_LEN) - 1) << GLB_REG_BMX_BERR_EN_POS)
+#define GLB_REG_BMX_BERR_EN_UMSK (~(((1U << GLB_REG_BMX_BERR_EN_LEN) - 1) << GLB_REG_BMX_BERR_EN_POS))
+#define GLB_REG_MCU_BERR_EN GLB_REG_MCU_BERR_EN
+#define GLB_REG_MCU_BERR_EN_POS (16U)
+#define GLB_REG_MCU_BERR_EN_LEN (1U)
+#define GLB_REG_MCU_BERR_EN_MSK (((1U << GLB_REG_MCU_BERR_EN_LEN) - 1) << GLB_REG_MCU_BERR_EN_POS)
+#define GLB_REG_MCU_BERR_EN_UMSK (~(((1U << GLB_REG_MCU_BERR_EN_LEN) - 1) << GLB_REG_MCU_BERR_EN_POS))
+
+/* 0x32C : bmx_cfg3 */
+#define GLB_BMX_CFG3_OFFSET (0x32C)
+#define GLB_REG_BMX_BERR_CLR GLB_REG_BMX_BERR_CLR
+#define GLB_REG_BMX_BERR_CLR_POS (0U)
+#define GLB_REG_BMX_BERR_CLR_LEN (1U)
+#define GLB_REG_BMX_BERR_CLR_MSK (((1U << GLB_REG_BMX_BERR_CLR_LEN) - 1) << GLB_REG_BMX_BERR_CLR_POS)
+#define GLB_REG_BMX_BERR_CLR_UMSK (~(((1U << GLB_REG_BMX_BERR_CLR_LEN) - 1) << GLB_REG_BMX_BERR_CLR_POS))
+#define GLB_REG_BMX_BERR_LAST GLB_REG_BMX_BERR_LAST
+#define GLB_REG_BMX_BERR_LAST_POS (1U)
+#define GLB_REG_BMX_BERR_LAST_LEN (1U)
+#define GLB_REG_BMX_BERR_LAST_MSK (((1U << GLB_REG_BMX_BERR_LAST_LEN) - 1) << GLB_REG_BMX_BERR_LAST_POS)
+#define GLB_REG_BMX_BERR_LAST_UMSK (~(((1U << GLB_REG_BMX_BERR_LAST_LEN) - 1) << GLB_REG_BMX_BERR_LAST_POS))
+#define GLB_REG_MCU_BERR_CLR GLB_REG_MCU_BERR_CLR
+#define GLB_REG_MCU_BERR_CLR_POS (8U)
+#define GLB_REG_MCU_BERR_CLR_LEN (1U)
+#define GLB_REG_MCU_BERR_CLR_MSK (((1U << GLB_REG_MCU_BERR_CLR_LEN) - 1) << GLB_REG_MCU_BERR_CLR_POS)
+#define GLB_REG_MCU_BERR_CLR_UMSK (~(((1U << GLB_REG_MCU_BERR_CLR_LEN) - 1) << GLB_REG_MCU_BERR_CLR_POS))
+#define GLB_REG_MCU_BERR_LAST GLB_REG_MCU_BERR_LAST
+#define GLB_REG_MCU_BERR_LAST_POS (9U)
+#define GLB_REG_MCU_BERR_LAST_LEN (1U)
+#define GLB_REG_MCU_BERR_LAST_MSK (((1U << GLB_REG_MCU_BERR_LAST_LEN) - 1) << GLB_REG_MCU_BERR_LAST_POS)
+#define GLB_REG_MCU_BERR_LAST_UMSK (~(((1U << GLB_REG_MCU_BERR_LAST_LEN) - 1) << GLB_REG_MCU_BERR_LAST_POS))
+#define GLB_STS_BMX_BERR GLB_STS_BMX_BERR
+#define GLB_STS_BMX_BERR_POS (16U)
+#define GLB_STS_BMX_BERR_LEN (1U)
+#define GLB_STS_BMX_BERR_MSK (((1U << GLB_STS_BMX_BERR_LEN) - 1) << GLB_STS_BMX_BERR_POS)
+#define GLB_STS_BMX_BERR_UMSK (~(((1U << GLB_STS_BMX_BERR_LEN) - 1) << GLB_STS_BMX_BERR_POS))
+#define GLB_STS_MCU_BERR GLB_STS_MCU_BERR
+#define GLB_STS_MCU_BERR_POS (17U)
+#define GLB_STS_MCU_BERR_LEN (1U)
+#define GLB_STS_MCU_BERR_MSK (((1U << GLB_STS_MCU_BERR_LEN) - 1) << GLB_STS_MCU_BERR_POS)
+#define GLB_STS_MCU_BERR_UMSK (~(((1U << GLB_STS_MCU_BERR_LEN) - 1) << GLB_STS_MCU_BERR_POS))
+#define GLB_STS_BMX_BERR_WRITE GLB_STS_BMX_BERR_WRITE
+#define GLB_STS_BMX_BERR_WRITE_POS (24U)
+#define GLB_STS_BMX_BERR_WRITE_LEN (1U)
+#define GLB_STS_BMX_BERR_WRITE_MSK (((1U << GLB_STS_BMX_BERR_WRITE_LEN) - 1) << GLB_STS_BMX_BERR_WRITE_POS)
+#define GLB_STS_BMX_BERR_WRITE_UMSK (~(((1U << GLB_STS_BMX_BERR_WRITE_LEN) - 1) << GLB_STS_BMX_BERR_WRITE_POS))
+#define GLB_STS_MCU_BERR_WRITE GLB_STS_MCU_BERR_WRITE
+#define GLB_STS_MCU_BERR_WRITE_POS (25U)
+#define GLB_STS_MCU_BERR_WRITE_LEN (1U)
+#define GLB_STS_MCU_BERR_WRITE_MSK (((1U << GLB_STS_MCU_BERR_WRITE_LEN) - 1) << GLB_STS_MCU_BERR_WRITE_POS)
+#define GLB_STS_MCU_BERR_WRITE_UMSK (~(((1U << GLB_STS_MCU_BERR_WRITE_LEN) - 1) << GLB_STS_MCU_BERR_WRITE_POS))
+
+/* 0x330 : bmx_cfg4 */
+#define GLB_BMX_CFG4_OFFSET (0x330)
+#define GLB_STS_BMX_BERR_SRC GLB_STS_BMX_BERR_SRC
+#define GLB_STS_BMX_BERR_SRC_POS (0U)
+#define GLB_STS_BMX_BERR_SRC_LEN (14U)
+#define GLB_STS_BMX_BERR_SRC_MSK (((1U << GLB_STS_BMX_BERR_SRC_LEN) - 1) << GLB_STS_BMX_BERR_SRC_POS)
+#define GLB_STS_BMX_BERR_SRC_UMSK (~(((1U << GLB_STS_BMX_BERR_SRC_LEN) - 1) << GLB_STS_BMX_BERR_SRC_POS))
+#define GLB_STS_MCU_BERR_SRC GLB_STS_MCU_BERR_SRC
+#define GLB_STS_MCU_BERR_SRC_POS (16U)
+#define GLB_STS_MCU_BERR_SRC_LEN (1U)
+#define GLB_STS_MCU_BERR_SRC_MSK (((1U << GLB_STS_MCU_BERR_SRC_LEN) - 1) << GLB_STS_MCU_BERR_SRC_POS)
+#define GLB_STS_MCU_BERR_SRC_UMSK (~(((1U << GLB_STS_MCU_BERR_SRC_LEN) - 1) << GLB_STS_MCU_BERR_SRC_POS))
+#define GLB_STS_MCU_BERR_ID GLB_STS_MCU_BERR_ID
+#define GLB_STS_MCU_BERR_ID_POS (24U)
+#define GLB_STS_MCU_BERR_ID_LEN (8U)
+#define GLB_STS_MCU_BERR_ID_MSK (((1U << GLB_STS_MCU_BERR_ID_LEN) - 1) << GLB_STS_MCU_BERR_ID_POS)
+#define GLB_STS_MCU_BERR_ID_UMSK (~(((1U << GLB_STS_MCU_BERR_ID_LEN) - 1) << GLB_STS_MCU_BERR_ID_POS))
+
+/* 0x334 : bmx_cfg5 */
+#define GLB_BMX_CFG5_OFFSET (0x334)
+#define GLB_STS_BMX_BERR_ADDR GLB_STS_BMX_BERR_ADDR
+#define GLB_STS_BMX_BERR_ADDR_POS (0U)
+#define GLB_STS_BMX_BERR_ADDR_LEN (32U)
+#define GLB_STS_BMX_BERR_ADDR_MSK (((1U << GLB_STS_BMX_BERR_ADDR_LEN) - 1) << GLB_STS_BMX_BERR_ADDR_POS)
+#define GLB_STS_BMX_BERR_ADDR_UMSK (~(((1U << GLB_STS_BMX_BERR_ADDR_LEN) - 1) << GLB_STS_BMX_BERR_ADDR_POS))
+
+/* 0x338 : bmx_cfg6 */
+#define GLB_BMX_CFG6_OFFSET (0x338)
+#define GLB_STS_MCU_BERR_ADDR GLB_STS_MCU_BERR_ADDR
+#define GLB_STS_MCU_BERR_ADDR_POS (0U)
+#define GLB_STS_MCU_BERR_ADDR_LEN (32U)
+#define GLB_STS_MCU_BERR_ADDR_MSK (((1U << GLB_STS_MCU_BERR_ADDR_LEN) - 1) << GLB_STS_MCU_BERR_ADDR_POS)
+#define GLB_STS_MCU_BERR_ADDR_UMSK (~(((1U << GLB_STS_MCU_BERR_ADDR_LEN) - 1) << GLB_STS_MCU_BERR_ADDR_POS))
+
+/* 0x340 : audio_cfg0 */
+#define GLB_AUDIO_CFG0_OFFSET (0x340)
+#define GLB_REG_AUDIO_PDM_CLK_DIV GLB_REG_AUDIO_PDM_CLK_DIV
+#define GLB_REG_AUDIO_PDM_CLK_DIV_POS (0U)
+#define GLB_REG_AUDIO_PDM_CLK_DIV_LEN (6U)
+#define GLB_REG_AUDIO_PDM_CLK_DIV_MSK (((1U << GLB_REG_AUDIO_PDM_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_PDM_CLK_DIV_POS)
+#define GLB_REG_AUDIO_PDM_CLK_DIV_UMSK (~(((1U << GLB_REG_AUDIO_PDM_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_PDM_CLK_DIV_POS))
+#define GLB_REG_AUDIO_PDM_CLK_EN GLB_REG_AUDIO_PDM_CLK_EN
+#define GLB_REG_AUDIO_PDM_CLK_EN_POS (7U)
+#define GLB_REG_AUDIO_PDM_CLK_EN_LEN (1U)
+#define GLB_REG_AUDIO_PDM_CLK_EN_MSK (((1U << GLB_REG_AUDIO_PDM_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_PDM_CLK_EN_POS)
+#define GLB_REG_AUDIO_PDM_CLK_EN_UMSK (~(((1U << GLB_REG_AUDIO_PDM_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_PDM_CLK_EN_POS))
+#define GLB_REG_AUDIO_ADC_CLK_DIV GLB_REG_AUDIO_ADC_CLK_DIV
+#define GLB_REG_AUDIO_ADC_CLK_DIV_POS (8U)
+#define GLB_REG_AUDIO_ADC_CLK_DIV_LEN (6U)
+#define GLB_REG_AUDIO_ADC_CLK_DIV_MSK (((1U << GLB_REG_AUDIO_ADC_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_DIV_POS)
+#define GLB_REG_AUDIO_ADC_CLK_DIV_UMSK (~(((1U << GLB_REG_AUDIO_ADC_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_DIV_POS))
+#define GLB_REG_AUDIO_ADC_CLK_EN GLB_REG_AUDIO_ADC_CLK_EN
+#define GLB_REG_AUDIO_ADC_CLK_EN_POS (15U)
+#define GLB_REG_AUDIO_ADC_CLK_EN_LEN (1U)
+#define GLB_REG_AUDIO_ADC_CLK_EN_MSK (((1U << GLB_REG_AUDIO_ADC_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_EN_POS)
+#define GLB_REG_AUDIO_ADC_CLK_EN_UMSK (~(((1U << GLB_REG_AUDIO_ADC_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_EN_POS))
+#define GLB_REG_AUDIO_DAC_CLK_DIV GLB_REG_AUDIO_DAC_CLK_DIV
+#define GLB_REG_AUDIO_DAC_CLK_DIV_POS (16U)
+#define GLB_REG_AUDIO_DAC_CLK_DIV_LEN (6U)
+#define GLB_REG_AUDIO_DAC_CLK_DIV_MSK (((1U << GLB_REG_AUDIO_DAC_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_DAC_CLK_DIV_POS)
+#define GLB_REG_AUDIO_DAC_CLK_DIV_UMSK (~(((1U << GLB_REG_AUDIO_DAC_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_DAC_CLK_DIV_POS))
+#define GLB_REG_AUDIO_DAC_CLK_EN GLB_REG_AUDIO_DAC_CLK_EN
+#define GLB_REG_AUDIO_DAC_CLK_EN_POS (23U)
+#define GLB_REG_AUDIO_DAC_CLK_EN_LEN (1U)
+#define GLB_REG_AUDIO_DAC_CLK_EN_MSK (((1U << GLB_REG_AUDIO_DAC_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_DAC_CLK_EN_POS)
+#define GLB_REG_AUDIO_DAC_CLK_EN_UMSK (~(((1U << GLB_REG_AUDIO_DAC_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_DAC_CLK_EN_POS))
+#define GLB_REG_AUDIO_AUTO_DIV_EN GLB_REG_AUDIO_AUTO_DIV_EN
+#define GLB_REG_AUDIO_AUTO_DIV_EN_POS (31U)
+#define GLB_REG_AUDIO_AUTO_DIV_EN_LEN (1U)
+#define GLB_REG_AUDIO_AUTO_DIV_EN_MSK (((1U << GLB_REG_AUDIO_AUTO_DIV_EN_LEN) - 1) << GLB_REG_AUDIO_AUTO_DIV_EN_POS)
+#define GLB_REG_AUDIO_AUTO_DIV_EN_UMSK (~(((1U << GLB_REG_AUDIO_AUTO_DIV_EN_LEN) - 1) << GLB_REG_AUDIO_AUTO_DIV_EN_POS))
+
+/* 0x344 : audio_cfg1 */
+#define GLB_AUDIO_CFG1_OFFSET (0x344)
+#define GLB_REG_PADC_CLK_DIV GLB_REG_PADC_CLK_DIV
+#define GLB_REG_PADC_CLK_DIV_POS (0U)
+#define GLB_REG_PADC_CLK_DIV_LEN (10U)
+#define GLB_REG_PADC_CLK_DIV_MSK (((1U << GLB_REG_PADC_CLK_DIV_LEN) - 1) << GLB_REG_PADC_CLK_DIV_POS)
+#define GLB_REG_PADC_CLK_DIV_UMSK (~(((1U << GLB_REG_PADC_CLK_DIV_LEN) - 1) << GLB_REG_PADC_CLK_DIV_POS))
+#define GLB_REG_PADC_CLK_EN GLB_REG_PADC_CLK_EN
+#define GLB_REG_PADC_CLK_EN_POS (10U)
+#define GLB_REG_PADC_CLK_EN_LEN (1U)
+#define GLB_REG_PADC_CLK_EN_MSK (((1U << GLB_REG_PADC_CLK_EN_LEN) - 1) << GLB_REG_PADC_CLK_EN_POS)
+#define GLB_REG_PADC_CLK_EN_UMSK (~(((1U << GLB_REG_PADC_CLK_EN_LEN) - 1) << GLB_REG_PADC_CLK_EN_POS))
+
+/* 0x390 : eth_cfg0 */
+#define GLB_ETH_CFG0_OFFSET (0x390)
+#define GLB_CFG_SEL_ETH_REF_CLK_O GLB_CFG_SEL_ETH_REF_CLK_O
+#define GLB_CFG_SEL_ETH_REF_CLK_O_POS (5U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_LEN (1U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_MSK (((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_REF_CLK_O GLB_CFG_INV_ETH_REF_CLK_O
+#define GLB_CFG_INV_ETH_REF_CLK_O_POS (6U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_LEN (1U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_MSK (((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS)
+#define GLB_CFG_INV_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_TX_CLK GLB_CFG_INV_ETH_TX_CLK
+#define GLB_CFG_INV_ETH_TX_CLK_POS (7U)
+#define GLB_CFG_INV_ETH_TX_CLK_LEN (1U)
+#define GLB_CFG_INV_ETH_TX_CLK_MSK (((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS)
+#define GLB_CFG_INV_ETH_TX_CLK_UMSK (~(((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS))
+#define GLB_CFG_INV_ETH_RX_CLK GLB_CFG_INV_ETH_RX_CLK
+#define GLB_CFG_INV_ETH_RX_CLK_POS (10U)
+#define GLB_CFG_INV_ETH_RX_CLK_LEN (1U)
+#define GLB_CFG_INV_ETH_RX_CLK_MSK (((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS)
+#define GLB_CFG_INV_ETH_RX_CLK_UMSK (~(((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS))
+
+/* 0x420 : cam_cfg0 */
+#define GLB_CAM_CFG0_OFFSET (0x420)
+#define GLB_REG_CAM_REF_CLK_EN GLB_REG_CAM_REF_CLK_EN
+#define GLB_REG_CAM_REF_CLK_EN_POS (27U)
+#define GLB_REG_CAM_REF_CLK_EN_LEN (1U)
+#define GLB_REG_CAM_REF_CLK_EN_MSK (((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS)
+#define GLB_REG_CAM_REF_CLK_EN_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS))
+#define GLB_REG_CAM_REF_CLK_SRC_SEL GLB_REG_CAM_REF_CLK_SRC_SEL
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_POS (28U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_LEN (2U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_MSK (((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS))
+#define GLB_REG_CAM_REF_CLK_DIV GLB_REG_CAM_REF_CLK_DIV
+#define GLB_REG_CAM_REF_CLK_DIV_POS (30U)
+#define GLB_REG_CAM_REF_CLK_DIV_LEN (2U)
+#define GLB_REG_CAM_REF_CLK_DIV_MSK (((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS)
+#define GLB_REG_CAM_REF_CLK_DIV_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS))
+
+/* 0x430 : sdh_cfg0 */
+#define GLB_SDH_CFG0_OFFSET (0x430)
+#define GLB_REG_SDH_CLK_DIV GLB_REG_SDH_CLK_DIV
+#define GLB_REG_SDH_CLK_DIV_POS (9U)
+#define GLB_REG_SDH_CLK_DIV_LEN (3U)
+#define GLB_REG_SDH_CLK_DIV_MSK (((1U << GLB_REG_SDH_CLK_DIV_LEN) - 1) << GLB_REG_SDH_CLK_DIV_POS)
+#define GLB_REG_SDH_CLK_DIV_UMSK (~(((1U << GLB_REG_SDH_CLK_DIV_LEN) - 1) << GLB_REG_SDH_CLK_DIV_POS))
+#define GLB_REG_SDH_CLK_SEL GLB_REG_SDH_CLK_SEL
+#define GLB_REG_SDH_CLK_SEL_POS (12U)
+#define GLB_REG_SDH_CLK_SEL_LEN (1U)
+#define GLB_REG_SDH_CLK_SEL_MSK (((1U << GLB_REG_SDH_CLK_SEL_LEN) - 1) << GLB_REG_SDH_CLK_SEL_POS)
+#define GLB_REG_SDH_CLK_SEL_UMSK (~(((1U << GLB_REG_SDH_CLK_SEL_LEN) - 1) << GLB_REG_SDH_CLK_SEL_POS))
+#define GLB_REG_SDH_CLK_EN GLB_REG_SDH_CLK_EN
+#define GLB_REG_SDH_CLK_EN_POS (13U)
+#define GLB_REG_SDH_CLK_EN_LEN (1U)
+#define GLB_REG_SDH_CLK_EN_MSK (((1U << GLB_REG_SDH_CLK_EN_LEN) - 1) << GLB_REG_SDH_CLK_EN_POS)
+#define GLB_REG_SDH_CLK_EN_UMSK (~(((1U << GLB_REG_SDH_CLK_EN_LEN) - 1) << GLB_REG_SDH_CLK_EN_POS))
+
+/* 0x490 : tzc_cfg0 */
+#define GLB_TZC_CFG0_OFFSET (0x490)
+#define GLB_TZC_GLB_PWRON_RST_LOCK GLB_TZC_GLB_PWRON_RST_LOCK
+#define GLB_TZC_GLB_PWRON_RST_LOCK_POS (12U)
+#define GLB_TZC_GLB_PWRON_RST_LOCK_LEN (1U)
+#define GLB_TZC_GLB_PWRON_RST_LOCK_MSK (((1U << GLB_TZC_GLB_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_PWRON_RST_LOCK_POS)
+#define GLB_TZC_GLB_PWRON_RST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_PWRON_RST_LOCK_POS))
+#define GLB_TZC_GLB_CPU_RESET_LOCK GLB_TZC_GLB_CPU_RESET_LOCK
+#define GLB_TZC_GLB_CPU_RESET_LOCK_POS (13U)
+#define GLB_TZC_GLB_CPU_RESET_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CPU_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CPU_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU_RESET_LOCK_POS))
+#define GLB_TZC_GLB_SYS_RESET_LOCK GLB_TZC_GLB_SYS_RESET_LOCK
+#define GLB_TZC_GLB_SYS_RESET_LOCK_POS (14U)
+#define GLB_TZC_GLB_SYS_RESET_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SYS_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_SYS_RESET_LOCK_POS)
+#define GLB_TZC_GLB_SYS_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_SYS_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CPU2_RESET_LOCK GLB_TZC_GLB_CPU2_RESET_LOCK
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_POS (15U)
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CPU2_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU2_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CPU2_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU2_RESET_LOCK_POS))
+#define GLB_TZC_GLB_PWR_LOCK GLB_TZC_GLB_PWR_LOCK
+#define GLB_TZC_GLB_PWR_LOCK_POS (21U)
+#define GLB_TZC_GLB_PWR_LOCK_LEN (1U)
+#define GLB_TZC_GLB_PWR_LOCK_MSK (((1U << GLB_TZC_GLB_PWR_LOCK_LEN) - 1) << GLB_TZC_GLB_PWR_LOCK_POS)
+#define GLB_TZC_GLB_PWR_LOCK_UMSK (~(((1U << GLB_TZC_GLB_PWR_LOCK_LEN) - 1) << GLB_TZC_GLB_PWR_LOCK_POS))
+#define GLB_TZC_GLB_INT_LOCK GLB_TZC_GLB_INT_LOCK
+#define GLB_TZC_GLB_INT_LOCK_POS (22U)
+#define GLB_TZC_GLB_INT_LOCK_LEN (1U)
+#define GLB_TZC_GLB_INT_LOCK_MSK (((1U << GLB_TZC_GLB_INT_LOCK_LEN) - 1) << GLB_TZC_GLB_INT_LOCK_POS)
+#define GLB_TZC_GLB_INT_LOCK_UMSK (~(((1U << GLB_TZC_GLB_INT_LOCK_LEN) - 1) << GLB_TZC_GLB_INT_LOCK_POS))
+#define GLB_TZC_GLB_CPUPLL_LOCK GLB_TZC_GLB_CPUPLL_LOCK
+#define GLB_TZC_GLB_CPUPLL_LOCK_POS (24U)
+#define GLB_TZC_GLB_CPUPLL_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CPUPLL_LOCK_MSK (((1U << GLB_TZC_GLB_CPUPLL_LOCK_LEN) - 1) << GLB_TZC_GLB_CPUPLL_LOCK_POS)
+#define GLB_TZC_GLB_CPUPLL_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CPUPLL_LOCK_LEN) - 1) << GLB_TZC_GLB_CPUPLL_LOCK_POS))
+#define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK
+#define GLB_TZC_GLB_MISC_LOCK_POS (25U)
+#define GLB_TZC_GLB_MISC_LOCK_LEN (1U)
+#define GLB_TZC_GLB_MISC_LOCK_MSK (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
+#define GLB_TZC_GLB_MISC_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
+#define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK
+#define GLB_TZC_GLB_SRAM_LOCK_POS (26U)
+#define GLB_TZC_GLB_SRAM_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SRAM_LOCK_MSK (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
+#define GLB_TZC_GLB_SRAM_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_LOCK GLB_TZC_GLB_SWRST_LOCK
+#define GLB_TZC_GLB_SWRST_LOCK_POS (27U)
+#define GLB_TZC_GLB_SWRST_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_LOCK_POS))
+#define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK
+#define GLB_TZC_GLB_BMX_LOCK_POS (28U)
+#define GLB_TZC_GLB_BMX_LOCK_LEN (1U)
+#define GLB_TZC_GLB_BMX_LOCK_MSK (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
+#define GLB_TZC_GLB_BMX_LOCK_UMSK (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
+#define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK
+#define GLB_TZC_GLB_DBG_LOCK_POS (29U)
+#define GLB_TZC_GLB_DBG_LOCK_LEN (1U)
+#define GLB_TZC_GLB_DBG_LOCK_MSK (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
+#define GLB_TZC_GLB_DBG_LOCK_UMSK (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
+#define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK
+#define GLB_TZC_GLB_MBIST_LOCK_POS (30U)
+#define GLB_TZC_GLB_MBIST_LOCK_LEN (1U)
+#define GLB_TZC_GLB_MBIST_LOCK_MSK (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
+#define GLB_TZC_GLB_MBIST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
+#define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK
+#define GLB_TZC_GLB_CLK_LOCK_POS (31U)
+#define GLB_TZC_GLB_CLK_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CLK_LOCK_MSK (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
+#define GLB_TZC_GLB_CLK_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
+
+/* 0x510 : glb_parm_cfg0 */
+#define GLB_PARM_CFG0_OFFSET (0x510)
+#define GLB_REG_BD_EN GLB_REG_BD_EN
+#define GLB_REG_BD_EN_POS (0U)
+#define GLB_REG_BD_EN_LEN (1U)
+#define GLB_REG_BD_EN_MSK (((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)
+#define GLB_REG_BD_EN_UMSK (~(((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS))
+#define GLB_UART_SWAP_SET GLB_UART_SWAP_SET
+#define GLB_UART_SWAP_SET_POS (2U)
+#define GLB_UART_SWAP_SET_LEN (4U)
+#define GLB_UART_SWAP_SET_MSK (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
+#define GLB_UART_SWAP_SET_UMSK (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
+#define GLB_SWAP_SFLASH_IO_3_IO_0 GLB_SWAP_SFLASH_IO_3_IO_0
+#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS))
+#define GLB_SEL_EMBEDDED_SFLASH GLB_SEL_EMBEDDED_SFLASH
+#define GLB_SEL_EMBEDDED_SFLASH_POS (9U)
+#define GLB_SEL_EMBEDDED_SFLASH_LEN (1U)
+#define GLB_SEL_EMBEDDED_SFLASH_MSK (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)
+#define GLB_SEL_EMBEDDED_SFLASH_UMSK (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS))
+#define GLB_REG_SEL_PSRAM0_X16 GLB_REG_SEL_PSRAM0_X16
+#define GLB_REG_SEL_PSRAM0_X16_POS (11U)
+#define GLB_REG_SEL_PSRAM0_X16_LEN (1U)
+#define GLB_REG_SEL_PSRAM0_X16_MSK (((1U << GLB_REG_SEL_PSRAM0_X16_LEN) - 1) << GLB_REG_SEL_PSRAM0_X16_POS)
+#define GLB_REG_SEL_PSRAM0_X16_UMSK (~(((1U << GLB_REG_SEL_PSRAM0_X16_LEN) - 1) << GLB_REG_SEL_PSRAM0_X16_POS))
+#define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE
+#define GLB_REG_SPI_0_MASTER_MODE_POS (12U)
+#define GLB_REG_SPI_0_MASTER_MODE_LEN (1U)
+#define GLB_REG_SPI_0_MASTER_MODE_MSK (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)
+#define GLB_REG_SPI_0_MASTER_MODE_UMSK (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS))
+#define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP
+#define GLB_REG_SPI_0_SWAP_POS (13U)
+#define GLB_REG_SPI_0_SWAP_LEN (1U)
+#define GLB_REG_SPI_0_SWAP_MSK (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
+#define GLB_REG_SPI_0_SWAP_UMSK (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
+#define GLB_REG_SEL_DBI_TYPE_C GLB_REG_SEL_DBI_TYPE_C
+#define GLB_REG_SEL_DBI_TYPE_C_POS (14U)
+#define GLB_REG_SEL_DBI_TYPE_C_LEN (1U)
+#define GLB_REG_SEL_DBI_TYPE_C_MSK (((1U << GLB_REG_SEL_DBI_TYPE_C_LEN) - 1) << GLB_REG_SEL_DBI_TYPE_C_POS)
+#define GLB_REG_SEL_DBI_TYPE_C_UMSK (~(((1U << GLB_REG_SEL_DBI_TYPE_C_LEN) - 1) << GLB_REG_SEL_DBI_TYPE_C_POS))
+#define GLB_ANT_SWITCH_SEL GLB_ANT_SWITCH_SEL
+#define GLB_ANT_SWITCH_SEL_POS (15U)
+#define GLB_ANT_SWITCH_SEL_LEN (1U)
+#define GLB_ANT_SWITCH_SEL_MSK (((1U << GLB_ANT_SWITCH_SEL_LEN) - 1) << GLB_ANT_SWITCH_SEL_POS)
+#define GLB_ANT_SWITCH_SEL_UMSK (~(((1U << GLB_ANT_SWITCH_SEL_LEN) - 1) << GLB_ANT_SWITCH_SEL_POS))
+#define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI
+#define GLB_P1_ADC_TEST_WITH_CCI_POS (17U)
+#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1U)
+#define GLB_P1_ADC_TEST_WITH_CCI_MSK (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
+#define GLB_P1_ADC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS))
+#define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI
+#define GLB_P2_DAC_TEST_WITH_CCI_POS (18U)
+#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1U)
+#define GLB_P2_DAC_TEST_WITH_CCI_MSK (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
+#define GLB_P2_DAC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS))
+#define GLB_P3_CCI_USE_IO_2_5 GLB_P3_CCI_USE_IO_2_5
+#define GLB_P3_CCI_USE_IO_2_5_POS (19U)
+#define GLB_P3_CCI_USE_IO_2_5_LEN (1U)
+#define GLB_P3_CCI_USE_IO_2_5_MSK (((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)
+#define GLB_P3_CCI_USE_IO_2_5_UMSK (~(((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS))
+#define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG
+#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_MSK (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)
+#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS))
+#define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG
+#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_MSK (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)
+#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS))
+#define GLB_P6_SDH_USE_IO_0_5 GLB_P6_SDH_USE_IO_0_5
+#define GLB_P6_SDH_USE_IO_0_5_POS (22U)
+#define GLB_P6_SDH_USE_IO_0_5_LEN (1U)
+#define GLB_P6_SDH_USE_IO_0_5_MSK (((1U << GLB_P6_SDH_USE_IO_0_5_LEN) - 1) << GLB_P6_SDH_USE_IO_0_5_POS)
+#define GLB_P6_SDH_USE_IO_0_5_UMSK (~(((1U << GLB_P6_SDH_USE_IO_0_5_LEN) - 1) << GLB_P6_SDH_USE_IO_0_5_POS))
+#define GLB_P7_JTAG_USE_IO_2_5 GLB_P7_JTAG_USE_IO_2_5
+#define GLB_P7_JTAG_USE_IO_2_5_POS (23U)
+#define GLB_P7_JTAG_USE_IO_2_5_LEN (1U)
+#define GLB_P7_JTAG_USE_IO_2_5_MSK (((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)
+#define GLB_P7_JTAG_USE_IO_2_5_UMSK (~(((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS))
+#define GLB_RF1_TEST_MODE GLB_RF1_TEST_MODE
+#define GLB_RF1_TEST_MODE_POS (25U)
+#define GLB_RF1_TEST_MODE_LEN (2U)
+#define GLB_RF1_TEST_MODE_MSK (((1U << GLB_RF1_TEST_MODE_LEN) - 1) << GLB_RF1_TEST_MODE_POS)
+#define GLB_RF1_TEST_MODE_UMSK (~(((1U << GLB_RF1_TEST_MODE_LEN) - 1) << GLB_RF1_TEST_MODE_POS))
+#define GLB_REG_MM_SPI_MASTER_MODE GLB_REG_MM_SPI_MASTER_MODE
+#define GLB_REG_MM_SPI_MASTER_MODE_POS (27U)
+#define GLB_REG_MM_SPI_MASTER_MODE_LEN (1U)
+#define GLB_REG_MM_SPI_MASTER_MODE_MSK (((1U << GLB_REG_MM_SPI_MASTER_MODE_LEN) - 1) << GLB_REG_MM_SPI_MASTER_MODE_POS)
+#define GLB_REG_MM_SPI_MASTER_MODE_UMSK (~(((1U << GLB_REG_MM_SPI_MASTER_MODE_LEN) - 1) << GLB_REG_MM_SPI_MASTER_MODE_POS))
+#define GLB_REG_MM_SPI_SWAP GLB_REG_MM_SPI_SWAP
+#define GLB_REG_MM_SPI_SWAP_POS (28U)
+#define GLB_REG_MM_SPI_SWAP_LEN (1U)
+#define GLB_REG_MM_SPI_SWAP_MSK (((1U << GLB_REG_MM_SPI_SWAP_LEN) - 1) << GLB_REG_MM_SPI_SWAP_POS)
+#define GLB_REG_MM_SPI_SWAP_UMSK (~(((1U << GLB_REG_MM_SPI_SWAP_LEN) - 1) << GLB_REG_MM_SPI_SWAP_POS))
+#define GLB_AUDIO_TEST_MODE GLB_AUDIO_TEST_MODE
+#define GLB_AUDIO_TEST_MODE_POS (29U)
+#define GLB_AUDIO_TEST_MODE_LEN (1U)
+#define GLB_AUDIO_TEST_MODE_MSK (((1U << GLB_AUDIO_TEST_MODE_LEN) - 1) << GLB_AUDIO_TEST_MODE_POS)
+#define GLB_AUDIO_TEST_MODE_UMSK (~(((1U << GLB_AUDIO_TEST_MODE_LEN) - 1) << GLB_AUDIO_TEST_MODE_POS))
+#define GLB_SEL_RF_AUDIO_TEST GLB_SEL_RF_AUDIO_TEST
+#define GLB_SEL_RF_AUDIO_TEST_POS (30U)
+#define GLB_SEL_RF_AUDIO_TEST_LEN (2U)
+#define GLB_SEL_RF_AUDIO_TEST_MSK (((1U << GLB_SEL_RF_AUDIO_TEST_LEN) - 1) << GLB_SEL_RF_AUDIO_TEST_POS)
+#define GLB_SEL_RF_AUDIO_TEST_UMSK (~(((1U << GLB_SEL_RF_AUDIO_TEST_LEN) - 1) << GLB_SEL_RF_AUDIO_TEST_POS))
+
+/* 0x520 : debug_cfg0 */
+#define GLB_DEBUG_CFG0_OFFSET (0x520)
+
+/* 0x524 : debug_cfg1 */
+#define GLB_DEBUG_CFG1_OFFSET (0x524)
+#define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE
+#define GLB_DEBUG_NDRESET_GATE_POS (20U)
+#define GLB_DEBUG_NDRESET_GATE_LEN (1U)
+#define GLB_DEBUG_NDRESET_GATE_MSK (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
+#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
+
+/* 0x530 : reset_sts0 */
+#define GLB_RESET_STS0_OFFSET (0x530)
+#define GLB_TOP_RESET_RECORDER GLB_TOP_RESET_RECORDER
+#define GLB_TOP_RESET_RECORDER_POS (0U)
+#define GLB_TOP_RESET_RECORDER_LEN (7U)
+#define GLB_TOP_RESET_RECORDER_MSK (((1U << GLB_TOP_RESET_RECORDER_LEN) - 1) << GLB_TOP_RESET_RECORDER_POS)
+#define GLB_TOP_RESET_RECORDER_UMSK (~(((1U << GLB_TOP_RESET_RECORDER_LEN) - 1) << GLB_TOP_RESET_RECORDER_POS))
+#define GLB_CLR_TOP_RESET_RECORDER GLB_CLR_TOP_RESET_RECORDER
+#define GLB_CLR_TOP_RESET_RECORDER_POS (7U)
+#define GLB_CLR_TOP_RESET_RECORDER_LEN (1U)
+#define GLB_CLR_TOP_RESET_RECORDER_MSK (((1U << GLB_CLR_TOP_RESET_RECORDER_LEN) - 1) << GLB_CLR_TOP_RESET_RECORDER_POS)
+#define GLB_CLR_TOP_RESET_RECORDER_UMSK (~(((1U << GLB_CLR_TOP_RESET_RECORDER_LEN) - 1) << GLB_CLR_TOP_RESET_RECORDER_POS))
+
+/* 0x540 : swrst_s1_ext + swrst_s3 + swrst_s2 */
+#define GLB_SWRST_CFG0_OFFSET (0x540)
+#define GLB_SWRST_S00 GLB_SWRST_S00
+#define GLB_SWRST_S00_POS (0U)
+#define GLB_SWRST_S00_LEN (1U)
+#define GLB_SWRST_S00_MSK (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
+#define GLB_SWRST_S00_UMSK (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
+#define GLB_SWRST_S01 GLB_SWRST_S01
+#define GLB_SWRST_S01_POS (1U)
+#define GLB_SWRST_S01_LEN (1U)
+#define GLB_SWRST_S01_MSK (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
+#define GLB_SWRST_S01_UMSK (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
+#define GLB_SWRST_S20 GLB_SWRST_S20
+#define GLB_SWRST_S20_POS (4U)
+#define GLB_SWRST_S20_LEN (1U)
+#define GLB_SWRST_S20_MSK (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
+#define GLB_SWRST_S20_UMSK (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
+#define GLB_SWRST_S30 GLB_SWRST_S30
+#define GLB_SWRST_S30_POS (8U)
+#define GLB_SWRST_S30_LEN (1U)
+#define GLB_SWRST_S30_MSK (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
+#define GLB_SWRST_S30_UMSK (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
+#define GLB_SWRST_S31 GLB_SWRST_S31
+#define GLB_SWRST_S31_POS (9U)
+#define GLB_SWRST_S31_LEN (1U)
+#define GLB_SWRST_S31_MSK (((1U << GLB_SWRST_S31_LEN) - 1) << GLB_SWRST_S31_POS)
+#define GLB_SWRST_S31_UMSK (~(((1U << GLB_SWRST_S31_LEN) - 1) << GLB_SWRST_S31_POS))
+#define GLB_SWRST_S32 GLB_SWRST_S32
+#define GLB_SWRST_S32_POS (10U)
+#define GLB_SWRST_S32_LEN (1U)
+#define GLB_SWRST_S32_MSK (((1U << GLB_SWRST_S32_LEN) - 1) << GLB_SWRST_S32_POS)
+#define GLB_SWRST_S32_UMSK (~(((1U << GLB_SWRST_S32_LEN) - 1) << GLB_SWRST_S32_POS))
+#define GLB_SWRST_S33 GLB_SWRST_S33
+#define GLB_SWRST_S33_POS (11U)
+#define GLB_SWRST_S33_LEN (1U)
+#define GLB_SWRST_S33_MSK (((1U << GLB_SWRST_S33_LEN) - 1) << GLB_SWRST_S33_POS)
+#define GLB_SWRST_S33_UMSK (~(((1U << GLB_SWRST_S33_LEN) - 1) << GLB_SWRST_S33_POS))
+#define GLB_SWRST_S1_EXT_EMI_MISC GLB_SWRST_S1_EXT_EMI_MISC
+#define GLB_SWRST_S1_EXT_EMI_MISC_POS (16U)
+#define GLB_SWRST_S1_EXT_EMI_MISC_LEN (1U)
+#define GLB_SWRST_S1_EXT_EMI_MISC_MSK (((1U << GLB_SWRST_S1_EXT_EMI_MISC_LEN) - 1) << GLB_SWRST_S1_EXT_EMI_MISC_POS)
+#define GLB_SWRST_S1_EXT_EMI_MISC_UMSK (~(((1U << GLB_SWRST_S1_EXT_EMI_MISC_LEN) - 1) << GLB_SWRST_S1_EXT_EMI_MISC_POS))
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL GLB_SWRST_S1_EXT_PSRAM0_CTRL
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_POS (17U)
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_LEN (1U)
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_MSK (((1U << GLB_SWRST_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM0_CTRL_POS)
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_UMSK (~(((1U << GLB_SWRST_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM0_CTRL_POS))
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL GLB_SWRST_S1_EXT_PSRAM1_CTRL
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_POS (18U)
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_LEN (1U)
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_MSK (((1U << GLB_SWRST_S1_EXT_PSRAM1_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM1_CTRL_POS)
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_UMSK (~(((1U << GLB_SWRST_S1_EXT_PSRAM1_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM1_CTRL_POS))
+#define GLB_SWRST_S1_EXT_USB GLB_SWRST_S1_EXT_USB
+#define GLB_SWRST_S1_EXT_USB_POS (19U)
+#define GLB_SWRST_S1_EXT_USB_LEN (1U)
+#define GLB_SWRST_S1_EXT_USB_MSK (((1U << GLB_SWRST_S1_EXT_USB_LEN) - 1) << GLB_SWRST_S1_EXT_USB_POS)
+#define GLB_SWRST_S1_EXT_USB_UMSK (~(((1U << GLB_SWRST_S1_EXT_USB_LEN) - 1) << GLB_SWRST_S1_EXT_USB_POS))
+#define GLB_SWRST_S1_EXT_MIX2 GLB_SWRST_S1_EXT_MIX2
+#define GLB_SWRST_S1_EXT_MIX2_POS (20U)
+#define GLB_SWRST_S1_EXT_MIX2_LEN (1U)
+#define GLB_SWRST_S1_EXT_MIX2_MSK (((1U << GLB_SWRST_S1_EXT_MIX2_LEN) - 1) << GLB_SWRST_S1_EXT_MIX2_POS)
+#define GLB_SWRST_S1_EXT_MIX2_UMSK (~(((1U << GLB_SWRST_S1_EXT_MIX2_LEN) - 1) << GLB_SWRST_S1_EXT_MIX2_POS))
+#define GLB_SWRST_S1_EXT_AUDIO GLB_SWRST_S1_EXT_AUDIO
+#define GLB_SWRST_S1_EXT_AUDIO_POS (21U)
+#define GLB_SWRST_S1_EXT_AUDIO_LEN (1U)
+#define GLB_SWRST_S1_EXT_AUDIO_MSK (((1U << GLB_SWRST_S1_EXT_AUDIO_LEN) - 1) << GLB_SWRST_S1_EXT_AUDIO_POS)
+#define GLB_SWRST_S1_EXT_AUDIO_UMSK (~(((1U << GLB_SWRST_S1_EXT_AUDIO_LEN) - 1) << GLB_SWRST_S1_EXT_AUDIO_POS))
+#define GLB_SWRST_S1_EXT_SDH GLB_SWRST_S1_EXT_SDH
+#define GLB_SWRST_S1_EXT_SDH_POS (22U)
+#define GLB_SWRST_S1_EXT_SDH_LEN (1U)
+#define GLB_SWRST_S1_EXT_SDH_MSK (((1U << GLB_SWRST_S1_EXT_SDH_LEN) - 1) << GLB_SWRST_S1_EXT_SDH_POS)
+#define GLB_SWRST_S1_EXT_SDH_UMSK (~(((1U << GLB_SWRST_S1_EXT_SDH_LEN) - 1) << GLB_SWRST_S1_EXT_SDH_POS))
+#define GLB_SWRST_S1_EXT_EMAC GLB_SWRST_S1_EXT_EMAC
+#define GLB_SWRST_S1_EXT_EMAC_POS (23U)
+#define GLB_SWRST_S1_EXT_EMAC_LEN (1U)
+#define GLB_SWRST_S1_EXT_EMAC_MSK (((1U << GLB_SWRST_S1_EXT_EMAC_LEN) - 1) << GLB_SWRST_S1_EXT_EMAC_POS)
+#define GLB_SWRST_S1_EXT_EMAC_UMSK (~(((1U << GLB_SWRST_S1_EXT_EMAC_LEN) - 1) << GLB_SWRST_S1_EXT_EMAC_POS))
+#define GLB_SWRST_S1_EXT_DMA2 GLB_SWRST_S1_EXT_DMA2
+#define GLB_SWRST_S1_EXT_DMA2_POS (24U)
+#define GLB_SWRST_S1_EXT_DMA2_LEN (1U)
+#define GLB_SWRST_S1_EXT_DMA2_MSK (((1U << GLB_SWRST_S1_EXT_DMA2_LEN) - 1) << GLB_SWRST_S1_EXT_DMA2_POS)
+#define GLB_SWRST_S1_EXT_DMA2_UMSK (~(((1U << GLB_SWRST_S1_EXT_DMA2_LEN) - 1) << GLB_SWRST_S1_EXT_DMA2_POS))
+
+/* 0x544 : swrst_s1 */
+#define GLB_SWRST_CFG1_OFFSET (0x544)
+#define GLB_SWRST_S10 GLB_SWRST_S10
+#define GLB_SWRST_S10_POS (0U)
+#define GLB_SWRST_S10_LEN (1U)
+#define GLB_SWRST_S10_MSK (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
+#define GLB_SWRST_S10_UMSK (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
+#define GLB_SWRST_S11 GLB_SWRST_S11
+#define GLB_SWRST_S11_POS (1U)
+#define GLB_SWRST_S11_LEN (1U)
+#define GLB_SWRST_S11_MSK (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
+#define GLB_SWRST_S11_UMSK (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
+#define GLB_SWRST_S12 GLB_SWRST_S12
+#define GLB_SWRST_S12_POS (2U)
+#define GLB_SWRST_S12_LEN (1U)
+#define GLB_SWRST_S12_MSK (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
+#define GLB_SWRST_S12_UMSK (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
+#define GLB_SWRST_S13 GLB_SWRST_S13
+#define GLB_SWRST_S13_POS (3U)
+#define GLB_SWRST_S13_LEN (1U)
+#define GLB_SWRST_S13_MSK (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
+#define GLB_SWRST_S13_UMSK (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
+#define GLB_SWRST_S14 GLB_SWRST_S14
+#define GLB_SWRST_S14_POS (4U)
+#define GLB_SWRST_S14_LEN (1U)
+#define GLB_SWRST_S14_MSK (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
+#define GLB_SWRST_S14_UMSK (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
+#define GLB_SWRST_S15 GLB_SWRST_S15
+#define GLB_SWRST_S15_POS (5U)
+#define GLB_SWRST_S15_LEN (1U)
+#define GLB_SWRST_S15_MSK (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
+#define GLB_SWRST_S15_UMSK (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
+#define GLB_SWRST_S16 GLB_SWRST_S16
+#define GLB_SWRST_S16_POS (6U)
+#define GLB_SWRST_S16_LEN (1U)
+#define GLB_SWRST_S16_MSK (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
+#define GLB_SWRST_S16_UMSK (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
+#define GLB_SWRST_S17 GLB_SWRST_S17
+#define GLB_SWRST_S17_POS (7U)
+#define GLB_SWRST_S17_LEN (1U)
+#define GLB_SWRST_S17_MSK (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
+#define GLB_SWRST_S17_UMSK (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
+#define GLB_SWRST_S18 GLB_SWRST_S18
+#define GLB_SWRST_S18_POS (8U)
+#define GLB_SWRST_S18_LEN (1U)
+#define GLB_SWRST_S18_MSK (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
+#define GLB_SWRST_S18_UMSK (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
+#define GLB_SWRST_S19 GLB_SWRST_S19
+#define GLB_SWRST_S19_POS (9U)
+#define GLB_SWRST_S19_LEN (1U)
+#define GLB_SWRST_S19_MSK (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
+#define GLB_SWRST_S19_UMSK (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
+#define GLB_SWRST_S1A GLB_SWRST_S1A
+#define GLB_SWRST_S1A_POS (10U)
+#define GLB_SWRST_S1A_LEN (1U)
+#define GLB_SWRST_S1A_MSK (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
+#define GLB_SWRST_S1A_UMSK (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
+#define GLB_SWRST_S1B GLB_SWRST_S1B
+#define GLB_SWRST_S1B_POS (11U)
+#define GLB_SWRST_S1B_LEN (1U)
+#define GLB_SWRST_S1B_MSK (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
+#define GLB_SWRST_S1B_UMSK (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
+#define GLB_SWRST_S1C GLB_SWRST_S1C
+#define GLB_SWRST_S1C_POS (12U)
+#define GLB_SWRST_S1C_LEN (1U)
+#define GLB_SWRST_S1C_MSK (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
+#define GLB_SWRST_S1C_UMSK (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
+#define GLB_SWRST_S1D GLB_SWRST_S1D
+#define GLB_SWRST_S1D_POS (13U)
+#define GLB_SWRST_S1D_LEN (1U)
+#define GLB_SWRST_S1D_MSK (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
+#define GLB_SWRST_S1D_UMSK (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
+#define GLB_SWRST_S1E GLB_SWRST_S1E
+#define GLB_SWRST_S1E_POS (14U)
+#define GLB_SWRST_S1E_LEN (1U)
+#define GLB_SWRST_S1E_MSK (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
+#define GLB_SWRST_S1E_UMSK (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
+#define GLB_SWRST_S1F GLB_SWRST_S1F
+#define GLB_SWRST_S1F_POS (15U)
+#define GLB_SWRST_S1F_LEN (1U)
+#define GLB_SWRST_S1F_MSK (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
+#define GLB_SWRST_S1F_UMSK (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
+#define GLB_SWRST_S1A0 GLB_SWRST_S1A0
+#define GLB_SWRST_S1A0_POS (16U)
+#define GLB_SWRST_S1A0_LEN (1U)
+#define GLB_SWRST_S1A0_MSK (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
+#define GLB_SWRST_S1A0_UMSK (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
+#define GLB_SWRST_S1A1 GLB_SWRST_S1A1
+#define GLB_SWRST_S1A1_POS (17U)
+#define GLB_SWRST_S1A1_LEN (1U)
+#define GLB_SWRST_S1A1_MSK (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
+#define GLB_SWRST_S1A1_UMSK (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
+#define GLB_SWRST_S1A2 GLB_SWRST_S1A2
+#define GLB_SWRST_S1A2_POS (18U)
+#define GLB_SWRST_S1A2_LEN (1U)
+#define GLB_SWRST_S1A2_MSK (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
+#define GLB_SWRST_S1A2_UMSK (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
+#define GLB_SWRST_S1A3 GLB_SWRST_S1A3
+#define GLB_SWRST_S1A3_POS (19U)
+#define GLB_SWRST_S1A3_LEN (1U)
+#define GLB_SWRST_S1A3_MSK (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
+#define GLB_SWRST_S1A3_UMSK (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
+#define GLB_SWRST_S1A4 GLB_SWRST_S1A4
+#define GLB_SWRST_S1A4_POS (20U)
+#define GLB_SWRST_S1A4_LEN (1U)
+#define GLB_SWRST_S1A4_MSK (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
+#define GLB_SWRST_S1A4_UMSK (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
+#define GLB_SWRST_S1A5 GLB_SWRST_S1A5
+#define GLB_SWRST_S1A5_POS (21U)
+#define GLB_SWRST_S1A5_LEN (1U)
+#define GLB_SWRST_S1A5_MSK (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
+#define GLB_SWRST_S1A5_UMSK (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
+#define GLB_SWRST_S1A6 GLB_SWRST_S1A6
+#define GLB_SWRST_S1A6_POS (22U)
+#define GLB_SWRST_S1A6_LEN (1U)
+#define GLB_SWRST_S1A6_MSK (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
+#define GLB_SWRST_S1A6_UMSK (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
+#define GLB_SWRST_S1A7 GLB_SWRST_S1A7
+#define GLB_SWRST_S1A7_POS (23U)
+#define GLB_SWRST_S1A7_LEN (1U)
+#define GLB_SWRST_S1A7_MSK (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
+#define GLB_SWRST_S1A7_UMSK (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
+#define GLB_SWRST_S1A8 GLB_SWRST_S1A8
+#define GLB_SWRST_S1A8_POS (24U)
+#define GLB_SWRST_S1A8_LEN (1U)
+#define GLB_SWRST_S1A8_MSK (((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS)
+#define GLB_SWRST_S1A8_UMSK (~(((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS))
+#define GLB_SWRST_S1A9 GLB_SWRST_S1A9
+#define GLB_SWRST_S1A9_POS (25U)
+#define GLB_SWRST_S1A9_LEN (1U)
+#define GLB_SWRST_S1A9_MSK (((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS)
+#define GLB_SWRST_S1A9_UMSK (~(((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS))
+#define GLB_SWRST_S1AA GLB_SWRST_S1AA
+#define GLB_SWRST_S1AA_POS (26U)
+#define GLB_SWRST_S1AA_LEN (1U)
+#define GLB_SWRST_S1AA_MSK (((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS)
+#define GLB_SWRST_S1AA_UMSK (~(((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS))
+#define GLB_SWRST_S1AB GLB_SWRST_S1AB
+#define GLB_SWRST_S1AB_POS (27U)
+#define GLB_SWRST_S1AB_LEN (1U)
+#define GLB_SWRST_S1AB_MSK (((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS)
+#define GLB_SWRST_S1AB_UMSK (~(((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS))
+#define GLB_SWRST_S1AC GLB_SWRST_S1AC
+#define GLB_SWRST_S1AC_POS (28U)
+#define GLB_SWRST_S1AC_LEN (1U)
+#define GLB_SWRST_S1AC_MSK (((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS)
+#define GLB_SWRST_S1AC_UMSK (~(((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS))
+#define GLB_SWRST_S1AD GLB_SWRST_S1AD
+#define GLB_SWRST_S1AD_POS (29U)
+#define GLB_SWRST_S1AD_LEN (1U)
+#define GLB_SWRST_S1AD_MSK (((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS)
+#define GLB_SWRST_S1AD_UMSK (~(((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS))
+#define GLB_SWRST_S1AE GLB_SWRST_S1AE
+#define GLB_SWRST_S1AE_POS (30U)
+#define GLB_SWRST_S1AE_LEN (1U)
+#define GLB_SWRST_S1AE_MSK (((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS)
+#define GLB_SWRST_S1AE_UMSK (~(((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS))
+#define GLB_SWRST_S1AF GLB_SWRST_S1AF
+#define GLB_SWRST_S1AF_POS (31U)
+#define GLB_SWRST_S1AF_LEN (1U)
+#define GLB_SWRST_S1AF_MSK (((1U << GLB_SWRST_S1AF_LEN) - 1) << GLB_SWRST_S1AF_POS)
+#define GLB_SWRST_S1AF_UMSK (~(((1U << GLB_SWRST_S1AF_LEN) - 1) << GLB_SWRST_S1AF_POS))
+
+/* 0x548 : swrst_cfg2 */
+#define GLB_SWRST_CFG2_OFFSET (0x548)
+#define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST
+#define GLB_REG_CTRL_PWRON_RST_POS (0U)
+#define GLB_REG_CTRL_PWRON_RST_LEN (1U)
+#define GLB_REG_CTRL_PWRON_RST_MSK (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
+#define GLB_REG_CTRL_PWRON_RST_UMSK (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
+#define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET
+#define GLB_REG_CTRL_CPU_RESET_POS (1U)
+#define GLB_REG_CTRL_CPU_RESET_LEN (1U)
+#define GLB_REG_CTRL_CPU_RESET_MSK (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
+#define GLB_REG_CTRL_CPU_RESET_UMSK (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
+#define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET
+#define GLB_REG_CTRL_SYS_RESET_POS (2U)
+#define GLB_REG_CTRL_SYS_RESET_LEN (1U)
+#define GLB_REG_CTRL_SYS_RESET_MSK (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
+#define GLB_REG_CTRL_SYS_RESET_UMSK (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
+#define GLB_REG_CTRL_PICO_RESET GLB_REG_CTRL_PICO_RESET
+#define GLB_REG_CTRL_PICO_RESET_POS (3U)
+#define GLB_REG_CTRL_PICO_RESET_LEN (1U)
+#define GLB_REG_CTRL_PICO_RESET_MSK (((1U << GLB_REG_CTRL_PICO_RESET_LEN) - 1) << GLB_REG_CTRL_PICO_RESET_POS)
+#define GLB_REG_CTRL_PICO_RESET_UMSK (~(((1U << GLB_REG_CTRL_PICO_RESET_LEN) - 1) << GLB_REG_CTRL_PICO_RESET_POS))
+#define GLB_REG_CTRL_CPU2_RESET GLB_REG_CTRL_CPU2_RESET
+#define GLB_REG_CTRL_CPU2_RESET_POS (4U)
+#define GLB_REG_CTRL_CPU2_RESET_LEN (1U)
+#define GLB_REG_CTRL_CPU2_RESET_MSK (((1U << GLB_REG_CTRL_CPU2_RESET_LEN) - 1) << GLB_REG_CTRL_CPU2_RESET_POS)
+#define GLB_REG_CTRL_CPU2_RESET_UMSK (~(((1U << GLB_REG_CTRL_CPU2_RESET_LEN) - 1) << GLB_REG_CTRL_CPU2_RESET_POS))
+#define GLB_REG_CTRL_CHIP_RESET GLB_REG_CTRL_CHIP_RESET
+#define GLB_REG_CTRL_CHIP_RESET_POS (5U)
+#define GLB_REG_CTRL_CHIP_RESET_LEN (1U)
+#define GLB_REG_CTRL_CHIP_RESET_MSK (((1U << GLB_REG_CTRL_CHIP_RESET_LEN) - 1) << GLB_REG_CTRL_CHIP_RESET_POS)
+#define GLB_REG_CTRL_CHIP_RESET_UMSK (~(((1U << GLB_REG_CTRL_CHIP_RESET_LEN) - 1) << GLB_REG_CTRL_CHIP_RESET_POS))
+#define GLB_REG_WL_WDT_RESET_MM_EN GLB_REG_WL_WDT_RESET_MM_EN
+#define GLB_REG_WL_WDT_RESET_MM_EN_POS (6U)
+#define GLB_REG_WL_WDT_RESET_MM_EN_LEN (1U)
+#define GLB_REG_WL_WDT_RESET_MM_EN_MSK (((1U << GLB_REG_WL_WDT_RESET_MM_EN_LEN) - 1) << GLB_REG_WL_WDT_RESET_MM_EN_POS)
+#define GLB_REG_WL_WDT_RESET_MM_EN_UMSK (~(((1U << GLB_REG_WL_WDT_RESET_MM_EN_LEN) - 1) << GLB_REG_WL_WDT_RESET_MM_EN_POS))
+#define GLB_REG_MMWDT2WL_RST_MSK GLB_REG_MMWDT2WL_RST_MSK
+#define GLB_REG_MMWDT2WL_RST_MSK_POS (7U)
+#define GLB_REG_MMWDT2WL_RST_MSK_LEN (1U)
+#define GLB_REG_MMWDT2WL_RST_MSK_MSK (((1U << GLB_REG_MMWDT2WL_RST_MSK_LEN) - 1) << GLB_REG_MMWDT2WL_RST_MSK_POS)
+#define GLB_REG_MMWDT2WL_RST_MSK_UMSK (~(((1U << GLB_REG_MMWDT2WL_RST_MSK_LEN) - 1) << GLB_REG_MMWDT2WL_RST_MSK_POS))
+#define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL
+#define GLB_PKA_CLK_SEL_POS (24U)
+#define GLB_PKA_CLK_SEL_LEN (1U)
+#define GLB_PKA_CLK_SEL_MSK (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
+#define GLB_PKA_CLK_SEL_UMSK (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
+#define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY
+#define GLB_REG_CTRL_RESET_DUMMY_POS (28U)
+#define GLB_REG_CTRL_RESET_DUMMY_LEN (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_MSK (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
+#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS))
+
+/* 0x54C : Disable hreset */
+#define GLB_SWRST_CFG3_OFFSET (0x54C)
+#define GLB_DISRST_S12 GLB_DISRST_S12
+#define GLB_DISRST_S12_POS (2U)
+#define GLB_DISRST_S12_LEN (1U)
+#define GLB_DISRST_S12_MSK (((1U << GLB_DISRST_S12_LEN) - 1) << GLB_DISRST_S12_POS)
+#define GLB_DISRST_S12_UMSK (~(((1U << GLB_DISRST_S12_LEN) - 1) << GLB_DISRST_S12_POS))
+#define GLB_DISRST_S14 GLB_DISRST_S14
+#define GLB_DISRST_S14_POS (4U)
+#define GLB_DISRST_S14_LEN (1U)
+#define GLB_DISRST_S14_MSK (((1U << GLB_DISRST_S14_LEN) - 1) << GLB_DISRST_S14_POS)
+#define GLB_DISRST_S14_UMSK (~(((1U << GLB_DISRST_S14_LEN) - 1) << GLB_DISRST_S14_POS))
+#define GLB_DISRST_S18 GLB_DISRST_S18
+#define GLB_DISRST_S18_POS (8U)
+#define GLB_DISRST_S18_LEN (1U)
+#define GLB_DISRST_S18_MSK (((1U << GLB_DISRST_S18_LEN) - 1) << GLB_DISRST_S18_POS)
+#define GLB_DISRST_S18_UMSK (~(((1U << GLB_DISRST_S18_LEN) - 1) << GLB_DISRST_S18_POS))
+#define GLB_DISRST_S1B GLB_DISRST_S1B
+#define GLB_DISRST_S1B_POS (11U)
+#define GLB_DISRST_S1B_LEN (1U)
+#define GLB_DISRST_S1B_MSK (((1U << GLB_DISRST_S1B_LEN) - 1) << GLB_DISRST_S1B_POS)
+#define GLB_DISRST_S1B_UMSK (~(((1U << GLB_DISRST_S1B_LEN) - 1) << GLB_DISRST_S1B_POS))
+#define GLB_DISRST_S1A0 GLB_DISRST_S1A0
+#define GLB_DISRST_S1A0_POS (16U)
+#define GLB_DISRST_S1A0_LEN (1U)
+#define GLB_DISRST_S1A0_MSK (((1U << GLB_DISRST_S1A0_LEN) - 1) << GLB_DISRST_S1A0_POS)
+#define GLB_DISRST_S1A0_UMSK (~(((1U << GLB_DISRST_S1A0_LEN) - 1) << GLB_DISRST_S1A0_POS))
+#define GLB_DISRST_S1A1 GLB_DISRST_S1A1
+#define GLB_DISRST_S1A1_POS (17U)
+#define GLB_DISRST_S1A1_LEN (1U)
+#define GLB_DISRST_S1A1_MSK (((1U << GLB_DISRST_S1A1_LEN) - 1) << GLB_DISRST_S1A1_POS)
+#define GLB_DISRST_S1A1_UMSK (~(((1U << GLB_DISRST_S1A1_LEN) - 1) << GLB_DISRST_S1A1_POS))
+#define GLB_DISRST_S1A2 GLB_DISRST_S1A2
+#define GLB_DISRST_S1A2_POS (18U)
+#define GLB_DISRST_S1A2_LEN (1U)
+#define GLB_DISRST_S1A2_MSK (((1U << GLB_DISRST_S1A2_LEN) - 1) << GLB_DISRST_S1A2_POS)
+#define GLB_DISRST_S1A2_UMSK (~(((1U << GLB_DISRST_S1A2_LEN) - 1) << GLB_DISRST_S1A2_POS))
+#define GLB_DISRST_S1A3 GLB_DISRST_S1A3
+#define GLB_DISRST_S1A3_POS (19U)
+#define GLB_DISRST_S1A3_LEN (1U)
+#define GLB_DISRST_S1A3_MSK (((1U << GLB_DISRST_S1A3_LEN) - 1) << GLB_DISRST_S1A3_POS)
+#define GLB_DISRST_S1A3_UMSK (~(((1U << GLB_DISRST_S1A3_LEN) - 1) << GLB_DISRST_S1A3_POS))
+#define GLB_DISRST_S1A4 GLB_DISRST_S1A4
+#define GLB_DISRST_S1A4_POS (20U)
+#define GLB_DISRST_S1A4_LEN (1U)
+#define GLB_DISRST_S1A4_MSK (((1U << GLB_DISRST_S1A4_LEN) - 1) << GLB_DISRST_S1A4_POS)
+#define GLB_DISRST_S1A4_UMSK (~(((1U << GLB_DISRST_S1A4_LEN) - 1) << GLB_DISRST_S1A4_POS))
+#define GLB_DISRST_S1A5 GLB_DISRST_S1A5
+#define GLB_DISRST_S1A5_POS (21U)
+#define GLB_DISRST_S1A5_LEN (1U)
+#define GLB_DISRST_S1A5_MSK (((1U << GLB_DISRST_S1A5_LEN) - 1) << GLB_DISRST_S1A5_POS)
+#define GLB_DISRST_S1A5_UMSK (~(((1U << GLB_DISRST_S1A5_LEN) - 1) << GLB_DISRST_S1A5_POS))
+#define GLB_DISRST_S1A6 GLB_DISRST_S1A6
+#define GLB_DISRST_S1A6_POS (22U)
+#define GLB_DISRST_S1A6_LEN (1U)
+#define GLB_DISRST_S1A6_MSK (((1U << GLB_DISRST_S1A6_LEN) - 1) << GLB_DISRST_S1A6_POS)
+#define GLB_DISRST_S1A6_UMSK (~(((1U << GLB_DISRST_S1A6_LEN) - 1) << GLB_DISRST_S1A6_POS))
+#define GLB_DISRST_S1A7 GLB_DISRST_S1A7
+#define GLB_DISRST_S1A7_POS (23U)
+#define GLB_DISRST_S1A7_LEN (1U)
+#define GLB_DISRST_S1A7_MSK (((1U << GLB_DISRST_S1A7_LEN) - 1) << GLB_DISRST_S1A7_POS)
+#define GLB_DISRST_S1A7_UMSK (~(((1U << GLB_DISRST_S1A7_LEN) - 1) << GLB_DISRST_S1A7_POS))
+#define GLB_DISRST_S1A8 GLB_DISRST_S1A8
+#define GLB_DISRST_S1A8_POS (24U)
+#define GLB_DISRST_S1A8_LEN (1U)
+#define GLB_DISRST_S1A8_MSK (((1U << GLB_DISRST_S1A8_LEN) - 1) << GLB_DISRST_S1A8_POS)
+#define GLB_DISRST_S1A8_UMSK (~(((1U << GLB_DISRST_S1A8_LEN) - 1) << GLB_DISRST_S1A8_POS))
+#define GLB_DISRST_S1A9 GLB_DISRST_S1A9
+#define GLB_DISRST_S1A9_POS (25U)
+#define GLB_DISRST_S1A9_LEN (1U)
+#define GLB_DISRST_S1A9_MSK (((1U << GLB_DISRST_S1A9_LEN) - 1) << GLB_DISRST_S1A9_POS)
+#define GLB_DISRST_S1A9_UMSK (~(((1U << GLB_DISRST_S1A9_LEN) - 1) << GLB_DISRST_S1A9_POS))
+#define GLB_DISRST_S1AA GLB_DISRST_S1AA
+#define GLB_DISRST_S1AA_POS (26U)
+#define GLB_DISRST_S1AA_LEN (1U)
+#define GLB_DISRST_S1AA_MSK (((1U << GLB_DISRST_S1AA_LEN) - 1) << GLB_DISRST_S1AA_POS)
+#define GLB_DISRST_S1AA_UMSK (~(((1U << GLB_DISRST_S1AA_LEN) - 1) << GLB_DISRST_S1AA_POS))
+
+/* 0x580 : cgen_m */
+#define GLB_CGEN_CFG0_OFFSET (0x580)
+#define GLB_CGEN_M_CPU GLB_CGEN_M_CPU
+#define GLB_CGEN_M_CPU_POS (0U)
+#define GLB_CGEN_M_CPU_LEN (1U)
+#define GLB_CGEN_M_CPU_MSK (((1U << GLB_CGEN_M_CPU_LEN) - 1) << GLB_CGEN_M_CPU_POS)
+#define GLB_CGEN_M_CPU_UMSK (~(((1U << GLB_CGEN_M_CPU_LEN) - 1) << GLB_CGEN_M_CPU_POS))
+#define GLB_CGEN_M_SDU GLB_CGEN_M_SDU
+#define GLB_CGEN_M_SDU_POS (1U)
+#define GLB_CGEN_M_SDU_LEN (1U)
+#define GLB_CGEN_M_SDU_MSK (((1U << GLB_CGEN_M_SDU_LEN) - 1) << GLB_CGEN_M_SDU_POS)
+#define GLB_CGEN_M_SDU_UMSK (~(((1U << GLB_CGEN_M_SDU_LEN) - 1) << GLB_CGEN_M_SDU_POS))
+#define GLB_CGEN_M_SEC GLB_CGEN_M_SEC
+#define GLB_CGEN_M_SEC_POS (2U)
+#define GLB_CGEN_M_SEC_LEN (1U)
+#define GLB_CGEN_M_SEC_MSK (((1U << GLB_CGEN_M_SEC_LEN) - 1) << GLB_CGEN_M_SEC_POS)
+#define GLB_CGEN_M_SEC_UMSK (~(((1U << GLB_CGEN_M_SEC_LEN) - 1) << GLB_CGEN_M_SEC_POS))
+#define GLB_CGEN_M_DMA GLB_CGEN_M_DMA
+#define GLB_CGEN_M_DMA_POS (3U)
+#define GLB_CGEN_M_DMA_LEN (1U)
+#define GLB_CGEN_M_DMA_MSK (((1U << GLB_CGEN_M_DMA_LEN) - 1) << GLB_CGEN_M_DMA_POS)
+#define GLB_CGEN_M_DMA_UMSK (~(((1U << GLB_CGEN_M_DMA_LEN) - 1) << GLB_CGEN_M_DMA_POS))
+#define GLB_CGEN_M_CCI GLB_CGEN_M_CCI
+#define GLB_CGEN_M_CCI_POS (4U)
+#define GLB_CGEN_M_CCI_LEN (1U)
+#define GLB_CGEN_M_CCI_MSK (((1U << GLB_CGEN_M_CCI_LEN) - 1) << GLB_CGEN_M_CCI_POS)
+#define GLB_CGEN_M_CCI_UMSK (~(((1U << GLB_CGEN_M_CCI_LEN) - 1) << GLB_CGEN_M_CCI_POS))
+
+/* 0x584 : cgen_s1a + cgen_s1 */
+#define GLB_CGEN_CFG1_OFFSET (0x584)
+#define GLB_CGEN_S1_RSVD0 GLB_CGEN_S1_RSVD0
+#define GLB_CGEN_S1_RSVD0_POS (0U)
+#define GLB_CGEN_S1_RSVD0_LEN (1U)
+#define GLB_CGEN_S1_RSVD0_MSK (((1U << GLB_CGEN_S1_RSVD0_LEN) - 1) << GLB_CGEN_S1_RSVD0_POS)
+#define GLB_CGEN_S1_RSVD0_UMSK (~(((1U << GLB_CGEN_S1_RSVD0_LEN) - 1) << GLB_CGEN_S1_RSVD0_POS))
+#define GLB_CGEN_S1_GPIP GLB_CGEN_S1_GPIP
+#define GLB_CGEN_S1_GPIP_POS (2U)
+#define GLB_CGEN_S1_GPIP_LEN (1U)
+#define GLB_CGEN_S1_GPIP_MSK (((1U << GLB_CGEN_S1_GPIP_LEN) - 1) << GLB_CGEN_S1_GPIP_POS)
+#define GLB_CGEN_S1_GPIP_UMSK (~(((1U << GLB_CGEN_S1_GPIP_LEN) - 1) << GLB_CGEN_S1_GPIP_POS))
+#define GLB_CGEN_S1_SEC_DBG GLB_CGEN_S1_SEC_DBG
+#define GLB_CGEN_S1_SEC_DBG_POS (3U)
+#define GLB_CGEN_S1_SEC_DBG_LEN (1U)
+#define GLB_CGEN_S1_SEC_DBG_MSK (((1U << GLB_CGEN_S1_SEC_DBG_LEN) - 1) << GLB_CGEN_S1_SEC_DBG_POS)
+#define GLB_CGEN_S1_SEC_DBG_UMSK (~(((1U << GLB_CGEN_S1_SEC_DBG_LEN) - 1) << GLB_CGEN_S1_SEC_DBG_POS))
+#define GLB_CGEN_S1_SEC_ENG GLB_CGEN_S1_SEC_ENG
+#define GLB_CGEN_S1_SEC_ENG_POS (4U)
+#define GLB_CGEN_S1_SEC_ENG_LEN (1U)
+#define GLB_CGEN_S1_SEC_ENG_MSK (((1U << GLB_CGEN_S1_SEC_ENG_LEN) - 1) << GLB_CGEN_S1_SEC_ENG_POS)
+#define GLB_CGEN_S1_SEC_ENG_UMSK (~(((1U << GLB_CGEN_S1_SEC_ENG_LEN) - 1) << GLB_CGEN_S1_SEC_ENG_POS))
+#define GLB_CGEN_S1_TZ GLB_CGEN_S1_TZ
+#define GLB_CGEN_S1_TZ_POS (5U)
+#define GLB_CGEN_S1_TZ_LEN (1U)
+#define GLB_CGEN_S1_TZ_MSK (((1U << GLB_CGEN_S1_TZ_LEN) - 1) << GLB_CGEN_S1_TZ_POS)
+#define GLB_CGEN_S1_TZ_UMSK (~(((1U << GLB_CGEN_S1_TZ_LEN) - 1) << GLB_CGEN_S1_TZ_POS))
+#define GLB_CGEN_S1_RSVD6 GLB_CGEN_S1_RSVD6
+#define GLB_CGEN_S1_RSVD6_POS (6U)
+#define GLB_CGEN_S1_RSVD6_LEN (1U)
+#define GLB_CGEN_S1_RSVD6_MSK (((1U << GLB_CGEN_S1_RSVD6_LEN) - 1) << GLB_CGEN_S1_RSVD6_POS)
+#define GLB_CGEN_S1_RSVD6_UMSK (~(((1U << GLB_CGEN_S1_RSVD6_LEN) - 1) << GLB_CGEN_S1_RSVD6_POS))
+#define GLB_CGEN_S1_EF_CTRL GLB_CGEN_S1_EF_CTRL
+#define GLB_CGEN_S1_EF_CTRL_POS (7U)
+#define GLB_CGEN_S1_EF_CTRL_LEN (1U)
+#define GLB_CGEN_S1_EF_CTRL_MSK (((1U << GLB_CGEN_S1_EF_CTRL_LEN) - 1) << GLB_CGEN_S1_EF_CTRL_POS)
+#define GLB_CGEN_S1_EF_CTRL_UMSK (~(((1U << GLB_CGEN_S1_EF_CTRL_LEN) - 1) << GLB_CGEN_S1_EF_CTRL_POS))
+#define GLB_CGEN_S1_RSVD8 GLB_CGEN_S1_RSVD8
+#define GLB_CGEN_S1_RSVD8_POS (8U)
+#define GLB_CGEN_S1_RSVD8_LEN (1U)
+#define GLB_CGEN_S1_RSVD8_MSK (((1U << GLB_CGEN_S1_RSVD8_LEN) - 1) << GLB_CGEN_S1_RSVD8_POS)
+#define GLB_CGEN_S1_RSVD8_UMSK (~(((1U << GLB_CGEN_S1_RSVD8_LEN) - 1) << GLB_CGEN_S1_RSVD8_POS))
+#define GLB_CGEN_S1_RSVD9 GLB_CGEN_S1_RSVD9
+#define GLB_CGEN_S1_RSVD9_POS (9U)
+#define GLB_CGEN_S1_RSVD9_LEN (1U)
+#define GLB_CGEN_S1_RSVD9_MSK (((1U << GLB_CGEN_S1_RSVD9_LEN) - 1) << GLB_CGEN_S1_RSVD9_POS)
+#define GLB_CGEN_S1_RSVD9_UMSK (~(((1U << GLB_CGEN_S1_RSVD9_LEN) - 1) << GLB_CGEN_S1_RSVD9_POS))
+#define GLB_CGEN_S1_RSVD10 GLB_CGEN_S1_RSVD10
+#define GLB_CGEN_S1_RSVD10_POS (10U)
+#define GLB_CGEN_S1_RSVD10_LEN (1U)
+#define GLB_CGEN_S1_RSVD10_MSK (((1U << GLB_CGEN_S1_RSVD10_LEN) - 1) << GLB_CGEN_S1_RSVD10_POS)
+#define GLB_CGEN_S1_RSVD10_UMSK (~(((1U << GLB_CGEN_S1_RSVD10_LEN) - 1) << GLB_CGEN_S1_RSVD10_POS))
+#define GLB_CGEN_S1_SF_CTRL GLB_CGEN_S1_SF_CTRL
+#define GLB_CGEN_S1_SF_CTRL_POS (11U)
+#define GLB_CGEN_S1_SF_CTRL_LEN (1U)
+#define GLB_CGEN_S1_SF_CTRL_MSK (((1U << GLB_CGEN_S1_SF_CTRL_LEN) - 1) << GLB_CGEN_S1_SF_CTRL_POS)
+#define GLB_CGEN_S1_SF_CTRL_UMSK (~(((1U << GLB_CGEN_S1_SF_CTRL_LEN) - 1) << GLB_CGEN_S1_SF_CTRL_POS))
+#define GLB_CGEN_S1_DMA GLB_CGEN_S1_DMA
+#define GLB_CGEN_S1_DMA_POS (12U)
+#define GLB_CGEN_S1_DMA_LEN (1U)
+#define GLB_CGEN_S1_DMA_MSK (((1U << GLB_CGEN_S1_DMA_LEN) - 1) << GLB_CGEN_S1_DMA_POS)
+#define GLB_CGEN_S1_DMA_UMSK (~(((1U << GLB_CGEN_S1_DMA_LEN) - 1) << GLB_CGEN_S1_DMA_POS))
+#define GLB_CGEN_S1_RSVD13 GLB_CGEN_S1_RSVD13
+#define GLB_CGEN_S1_RSVD13_POS (13U)
+#define GLB_CGEN_S1_RSVD13_LEN (1U)
+#define GLB_CGEN_S1_RSVD13_MSK (((1U << GLB_CGEN_S1_RSVD13_LEN) - 1) << GLB_CGEN_S1_RSVD13_POS)
+#define GLB_CGEN_S1_RSVD13_UMSK (~(((1U << GLB_CGEN_S1_RSVD13_LEN) - 1) << GLB_CGEN_S1_RSVD13_POS))
+#define GLB_CGEN_S1_RSVD14 GLB_CGEN_S1_RSVD14
+#define GLB_CGEN_S1_RSVD14_POS (14U)
+#define GLB_CGEN_S1_RSVD14_LEN (1U)
+#define GLB_CGEN_S1_RSVD14_MSK (((1U << GLB_CGEN_S1_RSVD14_LEN) - 1) << GLB_CGEN_S1_RSVD14_POS)
+#define GLB_CGEN_S1_RSVD14_UMSK (~(((1U << GLB_CGEN_S1_RSVD14_LEN) - 1) << GLB_CGEN_S1_RSVD14_POS))
+#define GLB_CGEN_S1_RSVD15 GLB_CGEN_S1_RSVD15
+#define GLB_CGEN_S1_RSVD15_POS (15U)
+#define GLB_CGEN_S1_RSVD15_LEN (1U)
+#define GLB_CGEN_S1_RSVD15_MSK (((1U << GLB_CGEN_S1_RSVD15_LEN) - 1) << GLB_CGEN_S1_RSVD15_POS)
+#define GLB_CGEN_S1_RSVD15_UMSK (~(((1U << GLB_CGEN_S1_RSVD15_LEN) - 1) << GLB_CGEN_S1_RSVD15_POS))
+#define GLB_CGEN_S1A_UART0 GLB_CGEN_S1A_UART0
+#define GLB_CGEN_S1A_UART0_POS (16U)
+#define GLB_CGEN_S1A_UART0_LEN (1U)
+#define GLB_CGEN_S1A_UART0_MSK (((1U << GLB_CGEN_S1A_UART0_LEN) - 1) << GLB_CGEN_S1A_UART0_POS)
+#define GLB_CGEN_S1A_UART0_UMSK (~(((1U << GLB_CGEN_S1A_UART0_LEN) - 1) << GLB_CGEN_S1A_UART0_POS))
+#define GLB_CGEN_S1A_UART1 GLB_CGEN_S1A_UART1
+#define GLB_CGEN_S1A_UART1_POS (17U)
+#define GLB_CGEN_S1A_UART1_LEN (1U)
+#define GLB_CGEN_S1A_UART1_MSK (((1U << GLB_CGEN_S1A_UART1_LEN) - 1) << GLB_CGEN_S1A_UART1_POS)
+#define GLB_CGEN_S1A_UART1_UMSK (~(((1U << GLB_CGEN_S1A_UART1_LEN) - 1) << GLB_CGEN_S1A_UART1_POS))
+#define GLB_CGEN_S1A_SPI GLB_CGEN_S1A_SPI
+#define GLB_CGEN_S1A_SPI_POS (18U)
+#define GLB_CGEN_S1A_SPI_LEN (1U)
+#define GLB_CGEN_S1A_SPI_MSK (((1U << GLB_CGEN_S1A_SPI_LEN) - 1) << GLB_CGEN_S1A_SPI_POS)
+#define GLB_CGEN_S1A_SPI_UMSK (~(((1U << GLB_CGEN_S1A_SPI_LEN) - 1) << GLB_CGEN_S1A_SPI_POS))
+#define GLB_CGEN_S1A_I2C GLB_CGEN_S1A_I2C
+#define GLB_CGEN_S1A_I2C_POS (19U)
+#define GLB_CGEN_S1A_I2C_LEN (1U)
+#define GLB_CGEN_S1A_I2C_MSK (((1U << GLB_CGEN_S1A_I2C_LEN) - 1) << GLB_CGEN_S1A_I2C_POS)
+#define GLB_CGEN_S1A_I2C_UMSK (~(((1U << GLB_CGEN_S1A_I2C_LEN) - 1) << GLB_CGEN_S1A_I2C_POS))
+#define GLB_CGEN_S1A_PWM GLB_CGEN_S1A_PWM
+#define GLB_CGEN_S1A_PWM_POS (20U)
+#define GLB_CGEN_S1A_PWM_LEN (1U)
+#define GLB_CGEN_S1A_PWM_MSK (((1U << GLB_CGEN_S1A_PWM_LEN) - 1) << GLB_CGEN_S1A_PWM_POS)
+#define GLB_CGEN_S1A_PWM_UMSK (~(((1U << GLB_CGEN_S1A_PWM_LEN) - 1) << GLB_CGEN_S1A_PWM_POS))
+#define GLB_CGEN_S1A_TIMER GLB_CGEN_S1A_TIMER
+#define GLB_CGEN_S1A_TIMER_POS (21U)
+#define GLB_CGEN_S1A_TIMER_LEN (1U)
+#define GLB_CGEN_S1A_TIMER_MSK (((1U << GLB_CGEN_S1A_TIMER_LEN) - 1) << GLB_CGEN_S1A_TIMER_POS)
+#define GLB_CGEN_S1A_TIMER_UMSK (~(((1U << GLB_CGEN_S1A_TIMER_LEN) - 1) << GLB_CGEN_S1A_TIMER_POS))
+#define GLB_CGEN_S1A_IR GLB_CGEN_S1A_IR
+#define GLB_CGEN_S1A_IR_POS (22U)
+#define GLB_CGEN_S1A_IR_LEN (1U)
+#define GLB_CGEN_S1A_IR_MSK (((1U << GLB_CGEN_S1A_IR_LEN) - 1) << GLB_CGEN_S1A_IR_POS)
+#define GLB_CGEN_S1A_IR_UMSK (~(((1U << GLB_CGEN_S1A_IR_LEN) - 1) << GLB_CGEN_S1A_IR_POS))
+#define GLB_CGEN_S1A_CKS GLB_CGEN_S1A_CKS
+#define GLB_CGEN_S1A_CKS_POS (23U)
+#define GLB_CGEN_S1A_CKS_LEN (1U)
+#define GLB_CGEN_S1A_CKS_MSK (((1U << GLB_CGEN_S1A_CKS_LEN) - 1) << GLB_CGEN_S1A_CKS_POS)
+#define GLB_CGEN_S1A_CKS_UMSK (~(((1U << GLB_CGEN_S1A_CKS_LEN) - 1) << GLB_CGEN_S1A_CKS_POS))
+#define GLB_CGEN_S1A_RSVD8 GLB_CGEN_S1A_RSVD8
+#define GLB_CGEN_S1A_RSVD8_POS (24U)
+#define GLB_CGEN_S1A_RSVD8_LEN (1U)
+#define GLB_CGEN_S1A_RSVD8_MSK (((1U << GLB_CGEN_S1A_RSVD8_LEN) - 1) << GLB_CGEN_S1A_RSVD8_POS)
+#define GLB_CGEN_S1A_RSVD8_UMSK (~(((1U << GLB_CGEN_S1A_RSVD8_LEN) - 1) << GLB_CGEN_S1A_RSVD8_POS))
+#define GLB_CGEN_S1A_I2C1 GLB_CGEN_S1A_I2C1
+#define GLB_CGEN_S1A_I2C1_POS (25U)
+#define GLB_CGEN_S1A_I2C1_LEN (1U)
+#define GLB_CGEN_S1A_I2C1_MSK (((1U << GLB_CGEN_S1A_I2C1_LEN) - 1) << GLB_CGEN_S1A_I2C1_POS)
+#define GLB_CGEN_S1A_I2C1_UMSK (~(((1U << GLB_CGEN_S1A_I2C1_LEN) - 1) << GLB_CGEN_S1A_I2C1_POS))
+#define GLB_CGEN_S1A_UART2 GLB_CGEN_S1A_UART2
+#define GLB_CGEN_S1A_UART2_POS (26U)
+#define GLB_CGEN_S1A_UART2_LEN (1U)
+#define GLB_CGEN_S1A_UART2_MSK (((1U << GLB_CGEN_S1A_UART2_LEN) - 1) << GLB_CGEN_S1A_UART2_POS)
+#define GLB_CGEN_S1A_UART2_UMSK (~(((1U << GLB_CGEN_S1A_UART2_LEN) - 1) << GLB_CGEN_S1A_UART2_POS))
+#define GLB_CGEN_S1A_RSVD11 GLB_CGEN_S1A_RSVD11
+#define GLB_CGEN_S1A_RSVD11_POS (27U)
+#define GLB_CGEN_S1A_RSVD11_LEN (1U)
+#define GLB_CGEN_S1A_RSVD11_MSK (((1U << GLB_CGEN_S1A_RSVD11_LEN) - 1) << GLB_CGEN_S1A_RSVD11_POS)
+#define GLB_CGEN_S1A_RSVD11_UMSK (~(((1U << GLB_CGEN_S1A_RSVD11_LEN) - 1) << GLB_CGEN_S1A_RSVD11_POS))
+#define GLB_CGEN_S1A_RSVD12 GLB_CGEN_S1A_RSVD12
+#define GLB_CGEN_S1A_RSVD12_POS (28U)
+#define GLB_CGEN_S1A_RSVD12_LEN (1U)
+#define GLB_CGEN_S1A_RSVD12_MSK (((1U << GLB_CGEN_S1A_RSVD12_LEN) - 1) << GLB_CGEN_S1A_RSVD12_POS)
+#define GLB_CGEN_S1A_RSVD12_UMSK (~(((1U << GLB_CGEN_S1A_RSVD12_LEN) - 1) << GLB_CGEN_S1A_RSVD12_POS))
+#define GLB_CGEN_S1A_RSVD13 GLB_CGEN_S1A_RSVD13
+#define GLB_CGEN_S1A_RSVD13_POS (29U)
+#define GLB_CGEN_S1A_RSVD13_LEN (1U)
+#define GLB_CGEN_S1A_RSVD13_MSK (((1U << GLB_CGEN_S1A_RSVD13_LEN) - 1) << GLB_CGEN_S1A_RSVD13_POS)
+#define GLB_CGEN_S1A_RSVD13_UMSK (~(((1U << GLB_CGEN_S1A_RSVD13_LEN) - 1) << GLB_CGEN_S1A_RSVD13_POS))
+#define GLB_CGEN_S1A_RSVD14 GLB_CGEN_S1A_RSVD14
+#define GLB_CGEN_S1A_RSVD14_POS (30U)
+#define GLB_CGEN_S1A_RSVD14_LEN (1U)
+#define GLB_CGEN_S1A_RSVD14_MSK (((1U << GLB_CGEN_S1A_RSVD14_LEN) - 1) << GLB_CGEN_S1A_RSVD14_POS)
+#define GLB_CGEN_S1A_RSVD14_UMSK (~(((1U << GLB_CGEN_S1A_RSVD14_LEN) - 1) << GLB_CGEN_S1A_RSVD14_POS))
+#define GLB_CGEN_S1A_RSVD15 GLB_CGEN_S1A_RSVD15
+#define GLB_CGEN_S1A_RSVD15_POS (31U)
+#define GLB_CGEN_S1A_RSVD15_LEN (1U)
+#define GLB_CGEN_S1A_RSVD15_MSK (((1U << GLB_CGEN_S1A_RSVD15_LEN) - 1) << GLB_CGEN_S1A_RSVD15_POS)
+#define GLB_CGEN_S1A_RSVD15_UMSK (~(((1U << GLB_CGEN_S1A_RSVD15_LEN) - 1) << GLB_CGEN_S1A_RSVD15_POS))
+
+/* 0x588 : cgen_s1_ext + cgen_s3 */
+#define GLB_CGEN_CFG2_OFFSET (0x588)
+#define GLB_CGEN_S0 GLB_CGEN_S0
+#define GLB_CGEN_S0_POS (0U)
+#define GLB_CGEN_S0_LEN (1U)
+#define GLB_CGEN_S0_MSK (((1U << GLB_CGEN_S0_LEN) - 1) << GLB_CGEN_S0_POS)
+#define GLB_CGEN_S0_UMSK (~(((1U << GLB_CGEN_S0_LEN) - 1) << GLB_CGEN_S0_POS))
+#define GLB_CGEN_S2_WIFI GLB_CGEN_S2_WIFI
+#define GLB_CGEN_S2_WIFI_POS (4U)
+#define GLB_CGEN_S2_WIFI_LEN (1U)
+#define GLB_CGEN_S2_WIFI_MSK (((1U << GLB_CGEN_S2_WIFI_LEN) - 1) << GLB_CGEN_S2_WIFI_POS)
+#define GLB_CGEN_S2_WIFI_UMSK (~(((1U << GLB_CGEN_S2_WIFI_LEN) - 1) << GLB_CGEN_S2_WIFI_POS))
+#define GLB_CGEN_S3_BT_BLE2 GLB_CGEN_S3_BT_BLE2
+#define GLB_CGEN_S3_BT_BLE2_POS (10U)
+#define GLB_CGEN_S3_BT_BLE2_LEN (1U)
+#define GLB_CGEN_S3_BT_BLE2_MSK (((1U << GLB_CGEN_S3_BT_BLE2_LEN) - 1) << GLB_CGEN_S3_BT_BLE2_POS)
+#define GLB_CGEN_S3_BT_BLE2_UMSK (~(((1U << GLB_CGEN_S3_BT_BLE2_LEN) - 1) << GLB_CGEN_S3_BT_BLE2_POS))
+#define GLB_CGEN_S3_M1542 GLB_CGEN_S3_M1542
+#define GLB_CGEN_S3_M1542_POS (11U)
+#define GLB_CGEN_S3_M1542_LEN (1U)
+#define GLB_CGEN_S3_M1542_MSK (((1U << GLB_CGEN_S3_M1542_LEN) - 1) << GLB_CGEN_S3_M1542_POS)
+#define GLB_CGEN_S3_M1542_UMSK (~(((1U << GLB_CGEN_S3_M1542_LEN) - 1) << GLB_CGEN_S3_M1542_POS))
+#define GLB_CGEN_S1_EXT_EMI_MISC GLB_CGEN_S1_EXT_EMI_MISC
+#define GLB_CGEN_S1_EXT_EMI_MISC_POS (16U)
+#define GLB_CGEN_S1_EXT_EMI_MISC_LEN (1U)
+#define GLB_CGEN_S1_EXT_EMI_MISC_MSK (((1U << GLB_CGEN_S1_EXT_EMI_MISC_LEN) - 1) << GLB_CGEN_S1_EXT_EMI_MISC_POS)
+#define GLB_CGEN_S1_EXT_EMI_MISC_UMSK (~(((1U << GLB_CGEN_S1_EXT_EMI_MISC_LEN) - 1) << GLB_CGEN_S1_EXT_EMI_MISC_POS))
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL GLB_CGEN_S1_EXT_PSRAM0_CTRL
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_POS (17U)
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_LEN (1U)
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_MSK (((1U << GLB_CGEN_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM0_CTRL_POS)
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_UMSK (~(((1U << GLB_CGEN_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM0_CTRL_POS))
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL GLB_CGEN_S1_EXT_PSRAM_CTRL
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_POS (18U)
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_LEN (1U)
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_MSK (((1U << GLB_CGEN_S1_EXT_PSRAM_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM_CTRL_POS)
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_UMSK (~(((1U << GLB_CGEN_S1_EXT_PSRAM_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM_CTRL_POS))
+#define GLB_CGEN_S1_EXT_USB GLB_CGEN_S1_EXT_USB
+#define GLB_CGEN_S1_EXT_USB_POS (19U)
+#define GLB_CGEN_S1_EXT_USB_LEN (1U)
+#define GLB_CGEN_S1_EXT_USB_MSK (((1U << GLB_CGEN_S1_EXT_USB_LEN) - 1) << GLB_CGEN_S1_EXT_USB_POS)
+#define GLB_CGEN_S1_EXT_USB_UMSK (~(((1U << GLB_CGEN_S1_EXT_USB_LEN) - 1) << GLB_CGEN_S1_EXT_USB_POS))
+#define GLB_CGEN_S1_EXT_MIX2 GLB_CGEN_S1_EXT_MIX2
+#define GLB_CGEN_S1_EXT_MIX2_POS (20U)
+#define GLB_CGEN_S1_EXT_MIX2_LEN (1U)
+#define GLB_CGEN_S1_EXT_MIX2_MSK (((1U << GLB_CGEN_S1_EXT_MIX2_LEN) - 1) << GLB_CGEN_S1_EXT_MIX2_POS)
+#define GLB_CGEN_S1_EXT_MIX2_UMSK (~(((1U << GLB_CGEN_S1_EXT_MIX2_LEN) - 1) << GLB_CGEN_S1_EXT_MIX2_POS))
+#define GLB_CGEN_S1_EXT_AUDIO GLB_CGEN_S1_EXT_AUDIO
+#define GLB_CGEN_S1_EXT_AUDIO_POS (21U)
+#define GLB_CGEN_S1_EXT_AUDIO_LEN (1U)
+#define GLB_CGEN_S1_EXT_AUDIO_MSK (((1U << GLB_CGEN_S1_EXT_AUDIO_LEN) - 1) << GLB_CGEN_S1_EXT_AUDIO_POS)
+#define GLB_CGEN_S1_EXT_AUDIO_UMSK (~(((1U << GLB_CGEN_S1_EXT_AUDIO_LEN) - 1) << GLB_CGEN_S1_EXT_AUDIO_POS))
+#define GLB_CGEN_S1_EXT_SDH GLB_CGEN_S1_EXT_SDH
+#define GLB_CGEN_S1_EXT_SDH_POS (22U)
+#define GLB_CGEN_S1_EXT_SDH_LEN (1U)
+#define GLB_CGEN_S1_EXT_SDH_MSK (((1U << GLB_CGEN_S1_EXT_SDH_LEN) - 1) << GLB_CGEN_S1_EXT_SDH_POS)
+#define GLB_CGEN_S1_EXT_SDH_UMSK (~(((1U << GLB_CGEN_S1_EXT_SDH_LEN) - 1) << GLB_CGEN_S1_EXT_SDH_POS))
+#define GLB_CGEN_S1_EXT_EMAC GLB_CGEN_S1_EXT_EMAC
+#define GLB_CGEN_S1_EXT_EMAC_POS (23U)
+#define GLB_CGEN_S1_EXT_EMAC_LEN (1U)
+#define GLB_CGEN_S1_EXT_EMAC_MSK (((1U << GLB_CGEN_S1_EXT_EMAC_LEN) - 1) << GLB_CGEN_S1_EXT_EMAC_POS)
+#define GLB_CGEN_S1_EXT_EMAC_UMSK (~(((1U << GLB_CGEN_S1_EXT_EMAC_LEN) - 1) << GLB_CGEN_S1_EXT_EMAC_POS))
+#define GLB_CGEN_S1_EXT_DMA2 GLB_CGEN_S1_EXT_DMA2
+#define GLB_CGEN_S1_EXT_DMA2_POS (24U)
+#define GLB_CGEN_S1_EXT_DMA2_LEN (1U)
+#define GLB_CGEN_S1_EXT_DMA2_MSK (((1U << GLB_CGEN_S1_EXT_DMA2_LEN) - 1) << GLB_CGEN_S1_EXT_DMA2_POS)
+#define GLB_CGEN_S1_EXT_DMA2_UMSK (~(((1U << GLB_CGEN_S1_EXT_DMA2_LEN) - 1) << GLB_CGEN_S1_EXT_DMA2_POS))
+#define GLB_CGEN_S1_EXT_RSVD9 GLB_CGEN_S1_EXT_RSVD9
+#define GLB_CGEN_S1_EXT_RSVD9_POS (25U)
+#define GLB_CGEN_S1_EXT_RSVD9_LEN (1U)
+#define GLB_CGEN_S1_EXT_RSVD9_MSK (((1U << GLB_CGEN_S1_EXT_RSVD9_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD9_POS)
+#define GLB_CGEN_S1_EXT_RSVD9_UMSK (~(((1U << GLB_CGEN_S1_EXT_RSVD9_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD9_POS))
+#define GLB_CGEN_S1_EXT_RSVD10 GLB_CGEN_S1_EXT_RSVD10
+#define GLB_CGEN_S1_EXT_RSVD10_POS (26U)
+#define GLB_CGEN_S1_EXT_RSVD10_LEN (1U)
+#define GLB_CGEN_S1_EXT_RSVD10_MSK (((1U << GLB_CGEN_S1_EXT_RSVD10_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD10_POS)
+#define GLB_CGEN_S1_EXT_RSVD10_UMSK (~(((1U << GLB_CGEN_S1_EXT_RSVD10_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD10_POS))
+#define GLB_CGEN_S1_EXT_RSVD11 GLB_CGEN_S1_EXT_RSVD11
+#define GLB_CGEN_S1_EXT_RSVD11_POS (27U)
+#define GLB_CGEN_S1_EXT_RSVD11_LEN (1U)
+#define GLB_CGEN_S1_EXT_RSVD11_MSK (((1U << GLB_CGEN_S1_EXT_RSVD11_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD11_POS)
+#define GLB_CGEN_S1_EXT_RSVD11_UMSK (~(((1U << GLB_CGEN_S1_EXT_RSVD11_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD11_POS))
+
+/* 0x58C : cgen_cfg3 */
+#define GLB_CGEN_CFG3_OFFSET (0x58C)
+#define GLB_CGEN_MM_WIFIPLL_160M GLB_CGEN_MM_WIFIPLL_160M
+#define GLB_CGEN_MM_WIFIPLL_160M_POS (0U)
+#define GLB_CGEN_MM_WIFIPLL_160M_LEN (1U)
+#define GLB_CGEN_MM_WIFIPLL_160M_MSK (((1U << GLB_CGEN_MM_WIFIPLL_160M_LEN) - 1) << GLB_CGEN_MM_WIFIPLL_160M_POS)
+#define GLB_CGEN_MM_WIFIPLL_160M_UMSK (~(((1U << GLB_CGEN_MM_WIFIPLL_160M_LEN) - 1) << GLB_CGEN_MM_WIFIPLL_160M_POS))
+#define GLB_CGEN_MM_WIFIPLL_240M GLB_CGEN_MM_WIFIPLL_240M
+#define GLB_CGEN_MM_WIFIPLL_240M_POS (1U)
+#define GLB_CGEN_MM_WIFIPLL_240M_LEN (1U)
+#define GLB_CGEN_MM_WIFIPLL_240M_MSK (((1U << GLB_CGEN_MM_WIFIPLL_240M_LEN) - 1) << GLB_CGEN_MM_WIFIPLL_240M_POS)
+#define GLB_CGEN_MM_WIFIPLL_240M_UMSK (~(((1U << GLB_CGEN_MM_WIFIPLL_240M_LEN) - 1) << GLB_CGEN_MM_WIFIPLL_240M_POS))
+#define GLB_CGEN_MM_WIFIPLL_320M GLB_CGEN_MM_WIFIPLL_320M
+#define GLB_CGEN_MM_WIFIPLL_320M_POS (2U)
+#define GLB_CGEN_MM_WIFIPLL_320M_LEN (1U)
+#define GLB_CGEN_MM_WIFIPLL_320M_MSK (((1U << GLB_CGEN_MM_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_MM_WIFIPLL_320M_POS)
+#define GLB_CGEN_MM_WIFIPLL_320M_UMSK (~(((1U << GLB_CGEN_MM_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_MM_WIFIPLL_320M_POS))
+#define GLB_CGEN_MM_AUPLL_DIV1 GLB_CGEN_MM_AUPLL_DIV1
+#define GLB_CGEN_MM_AUPLL_DIV1_POS (3U)
+#define GLB_CGEN_MM_AUPLL_DIV1_LEN (1U)
+#define GLB_CGEN_MM_AUPLL_DIV1_MSK (((1U << GLB_CGEN_MM_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_MM_AUPLL_DIV1_POS)
+#define GLB_CGEN_MM_AUPLL_DIV1_UMSK (~(((1U << GLB_CGEN_MM_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_MM_AUPLL_DIV1_POS))
+#define GLB_CGEN_MM_AUPLL_DIV2 GLB_CGEN_MM_AUPLL_DIV2
+#define GLB_CGEN_MM_AUPLL_DIV2_POS (4U)
+#define GLB_CGEN_MM_AUPLL_DIV2_LEN (1U)
+#define GLB_CGEN_MM_AUPLL_DIV2_MSK (((1U << GLB_CGEN_MM_AUPLL_DIV2_LEN) - 1) << GLB_CGEN_MM_AUPLL_DIV2_POS)
+#define GLB_CGEN_MM_AUPLL_DIV2_UMSK (~(((1U << GLB_CGEN_MM_AUPLL_DIV2_LEN) - 1) << GLB_CGEN_MM_AUPLL_DIV2_POS))
+#define GLB_CGEN_EMI_CPUPLL_400M GLB_CGEN_EMI_CPUPLL_400M
+#define GLB_CGEN_EMI_CPUPLL_400M_POS (5U)
+#define GLB_CGEN_EMI_CPUPLL_400M_LEN (1U)
+#define GLB_CGEN_EMI_CPUPLL_400M_MSK (((1U << GLB_CGEN_EMI_CPUPLL_400M_LEN) - 1) << GLB_CGEN_EMI_CPUPLL_400M_POS)
+#define GLB_CGEN_EMI_CPUPLL_400M_UMSK (~(((1U << GLB_CGEN_EMI_CPUPLL_400M_LEN) - 1) << GLB_CGEN_EMI_CPUPLL_400M_POS))
+#define GLB_CGEN_EMI_CPUPLL_200M GLB_CGEN_EMI_CPUPLL_200M
+#define GLB_CGEN_EMI_CPUPLL_200M_POS (6U)
+#define GLB_CGEN_EMI_CPUPLL_200M_LEN (1U)
+#define GLB_CGEN_EMI_CPUPLL_200M_MSK (((1U << GLB_CGEN_EMI_CPUPLL_200M_LEN) - 1) << GLB_CGEN_EMI_CPUPLL_200M_POS)
+#define GLB_CGEN_EMI_CPUPLL_200M_UMSK (~(((1U << GLB_CGEN_EMI_CPUPLL_200M_LEN) - 1) << GLB_CGEN_EMI_CPUPLL_200M_POS))
+#define GLB_CGEN_EMI_WIFIPLL_320M GLB_CGEN_EMI_WIFIPLL_320M
+#define GLB_CGEN_EMI_WIFIPLL_320M_POS (7U)
+#define GLB_CGEN_EMI_WIFIPLL_320M_LEN (1U)
+#define GLB_CGEN_EMI_WIFIPLL_320M_MSK (((1U << GLB_CGEN_EMI_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_EMI_WIFIPLL_320M_POS)
+#define GLB_CGEN_EMI_WIFIPLL_320M_UMSK (~(((1U << GLB_CGEN_EMI_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_EMI_WIFIPLL_320M_POS))
+#define GLB_CGEN_EMI_AUPLL_DIV1 GLB_CGEN_EMI_AUPLL_DIV1
+#define GLB_CGEN_EMI_AUPLL_DIV1_POS (8U)
+#define GLB_CGEN_EMI_AUPLL_DIV1_LEN (1U)
+#define GLB_CGEN_EMI_AUPLL_DIV1_MSK (((1U << GLB_CGEN_EMI_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_EMI_AUPLL_DIV1_POS)
+#define GLB_CGEN_EMI_AUPLL_DIV1_UMSK (~(((1U << GLB_CGEN_EMI_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_EMI_AUPLL_DIV1_POS))
+#define GLB_CGEN_TOP_CPUPLL_80M GLB_CGEN_TOP_CPUPLL_80M
+#define GLB_CGEN_TOP_CPUPLL_80M_POS (9U)
+#define GLB_CGEN_TOP_CPUPLL_80M_LEN (1U)
+#define GLB_CGEN_TOP_CPUPLL_80M_MSK (((1U << GLB_CGEN_TOP_CPUPLL_80M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_80M_POS)
+#define GLB_CGEN_TOP_CPUPLL_80M_UMSK (~(((1U << GLB_CGEN_TOP_CPUPLL_80M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_80M_POS))
+#define GLB_CGEN_TOP_CPUPLL_100M GLB_CGEN_TOP_CPUPLL_100M
+#define GLB_CGEN_TOP_CPUPLL_100M_POS (10U)
+#define GLB_CGEN_TOP_CPUPLL_100M_LEN (1U)
+#define GLB_CGEN_TOP_CPUPLL_100M_MSK (((1U << GLB_CGEN_TOP_CPUPLL_100M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_100M_POS)
+#define GLB_CGEN_TOP_CPUPLL_100M_UMSK (~(((1U << GLB_CGEN_TOP_CPUPLL_100M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_100M_POS))
+#define GLB_CGEN_TOP_CPUPLL_160M GLB_CGEN_TOP_CPUPLL_160M
+#define GLB_CGEN_TOP_CPUPLL_160M_POS (11U)
+#define GLB_CGEN_TOP_CPUPLL_160M_LEN (1U)
+#define GLB_CGEN_TOP_CPUPLL_160M_MSK (((1U << GLB_CGEN_TOP_CPUPLL_160M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_160M_POS)
+#define GLB_CGEN_TOP_CPUPLL_160M_UMSK (~(((1U << GLB_CGEN_TOP_CPUPLL_160M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_160M_POS))
+#define GLB_CGEN_TOP_CPUPLL_400M GLB_CGEN_TOP_CPUPLL_400M
+#define GLB_CGEN_TOP_CPUPLL_400M_POS (12U)
+#define GLB_CGEN_TOP_CPUPLL_400M_LEN (1U)
+#define GLB_CGEN_TOP_CPUPLL_400M_MSK (((1U << GLB_CGEN_TOP_CPUPLL_400M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_400M_POS)
+#define GLB_CGEN_TOP_CPUPLL_400M_UMSK (~(((1U << GLB_CGEN_TOP_CPUPLL_400M_LEN) - 1) << GLB_CGEN_TOP_CPUPLL_400M_POS))
+#define GLB_CGEN_TOP_WIFIPLL_240M GLB_CGEN_TOP_WIFIPLL_240M
+#define GLB_CGEN_TOP_WIFIPLL_240M_POS (13U)
+#define GLB_CGEN_TOP_WIFIPLL_240M_LEN (1U)
+#define GLB_CGEN_TOP_WIFIPLL_240M_MSK (((1U << GLB_CGEN_TOP_WIFIPLL_240M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_240M_POS)
+#define GLB_CGEN_TOP_WIFIPLL_240M_UMSK (~(((1U << GLB_CGEN_TOP_WIFIPLL_240M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_240M_POS))
+#define GLB_CGEN_TOP_WIFIPLL_320M GLB_CGEN_TOP_WIFIPLL_320M
+#define GLB_CGEN_TOP_WIFIPLL_320M_POS (14U)
+#define GLB_CGEN_TOP_WIFIPLL_320M_LEN (1U)
+#define GLB_CGEN_TOP_WIFIPLL_320M_MSK (((1U << GLB_CGEN_TOP_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_320M_POS)
+#define GLB_CGEN_TOP_WIFIPLL_320M_UMSK (~(((1U << GLB_CGEN_TOP_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_320M_POS))
+#define GLB_CGEN_TOP_AUPLL_DIV2 GLB_CGEN_TOP_AUPLL_DIV2
+#define GLB_CGEN_TOP_AUPLL_DIV2_POS (15U)
+#define GLB_CGEN_TOP_AUPLL_DIV2_LEN (1U)
+#define GLB_CGEN_TOP_AUPLL_DIV2_MSK (((1U << GLB_CGEN_TOP_AUPLL_DIV2_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV2_POS)
+#define GLB_CGEN_TOP_AUPLL_DIV2_UMSK (~(((1U << GLB_CGEN_TOP_AUPLL_DIV2_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV2_POS))
+#define GLB_CGEN_TOP_AUPLL_DIV1 GLB_CGEN_TOP_AUPLL_DIV1
+#define GLB_CGEN_TOP_AUPLL_DIV1_POS (16U)
+#define GLB_CGEN_TOP_AUPLL_DIV1_LEN (1U)
+#define GLB_CGEN_TOP_AUPLL_DIV1_MSK (((1U << GLB_CGEN_TOP_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV1_POS)
+#define GLB_CGEN_TOP_AUPLL_DIV1_UMSK (~(((1U << GLB_CGEN_TOP_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV1_POS))
+
+/* 0x5C0 : hw_rsv0 */
+#define GLB_HW_RSV0_OFFSET (0x5C0)
+
+/* 0x5C4 : hw_rsv1 */
+#define GLB_HW_RSV1_OFFSET (0x5C4)
+
+/* 0x5C8 : hw_rsv2 */
+#define GLB_HW_RSV2_OFFSET (0x5C8)
+
+/* 0x5CC : hw_rsv3 */
+#define GLB_HW_RSV3_OFFSET (0x5CC)
+
+/* 0x600 : reg_sram_ret */
+#define GLB_SRAM_CFG0_OFFSET (0x600)
+#define GLB_CR_MCU_CACHE_RET GLB_CR_MCU_CACHE_RET
+#define GLB_CR_MCU_CACHE_RET_POS (0U)
+#define GLB_CR_MCU_CACHE_RET_LEN (2U)
+#define GLB_CR_MCU_CACHE_RET_MSK (((1U << GLB_CR_MCU_CACHE_RET_LEN) - 1) << GLB_CR_MCU_CACHE_RET_POS)
+#define GLB_CR_MCU_CACHE_RET_UMSK (~(((1U << GLB_CR_MCU_CACHE_RET_LEN) - 1) << GLB_CR_MCU_CACHE_RET_POS))
+#define GLB_CR_MCU_HSRAM_RET GLB_CR_MCU_HSRAM_RET
+#define GLB_CR_MCU_HSRAM_RET_POS (2U)
+#define GLB_CR_MCU_HSRAM_RET_LEN (4U)
+#define GLB_CR_MCU_HSRAM_RET_MSK (((1U << GLB_CR_MCU_HSRAM_RET_LEN) - 1) << GLB_CR_MCU_HSRAM_RET_POS)
+#define GLB_CR_MCU_HSRAM_RET_UMSK (~(((1U << GLB_CR_MCU_HSRAM_RET_LEN) - 1) << GLB_CR_MCU_HSRAM_RET_POS))
+#define GLB_CR_WB_RAM_RET GLB_CR_WB_RAM_RET
+#define GLB_CR_WB_RAM_RET_POS (8U)
+#define GLB_CR_WB_RAM_RET_LEN (1U)
+#define GLB_CR_WB_RAM_RET_MSK (((1U << GLB_CR_WB_RAM_RET_LEN) - 1) << GLB_CR_WB_RAM_RET_POS)
+#define GLB_CR_WB_RAM_RET_UMSK (~(((1U << GLB_CR_WB_RAM_RET_LEN) - 1) << GLB_CR_WB_RAM_RET_POS))
+#define GLB_CR_MISC_RAM_RET GLB_CR_MISC_RAM_RET
+#define GLB_CR_MISC_RAM_RET_POS (9U)
+#define GLB_CR_MISC_RAM_RET_LEN (2U)
+#define GLB_CR_MISC_RAM_RET_MSK (((1U << GLB_CR_MISC_RAM_RET_LEN) - 1) << GLB_CR_MISC_RAM_RET_POS)
+#define GLB_CR_MISC_RAM_RET_UMSK (~(((1U << GLB_CR_MISC_RAM_RET_LEN) - 1) << GLB_CR_MISC_RAM_RET_POS))
+
+/* 0x604 : reg_sram_slp */
+#define GLB_SRAM_CFG1_OFFSET (0x604)
+#define GLB_CR_MCU_CACHE_SLP GLB_CR_MCU_CACHE_SLP
+#define GLB_CR_MCU_CACHE_SLP_POS (0U)
+#define GLB_CR_MCU_CACHE_SLP_LEN (2U)
+#define GLB_CR_MCU_CACHE_SLP_MSK (((1U << GLB_CR_MCU_CACHE_SLP_LEN) - 1) << GLB_CR_MCU_CACHE_SLP_POS)
+#define GLB_CR_MCU_CACHE_SLP_UMSK (~(((1U << GLB_CR_MCU_CACHE_SLP_LEN) - 1) << GLB_CR_MCU_CACHE_SLP_POS))
+#define GLB_CR_MCU_HSRAM_SLP GLB_CR_MCU_HSRAM_SLP
+#define GLB_CR_MCU_HSRAM_SLP_POS (2U)
+#define GLB_CR_MCU_HSRAM_SLP_LEN (4U)
+#define GLB_CR_MCU_HSRAM_SLP_MSK (((1U << GLB_CR_MCU_HSRAM_SLP_LEN) - 1) << GLB_CR_MCU_HSRAM_SLP_POS)
+#define GLB_CR_MCU_HSRAM_SLP_UMSK (~(((1U << GLB_CR_MCU_HSRAM_SLP_LEN) - 1) << GLB_CR_MCU_HSRAM_SLP_POS))
+#define GLB_CR_MCU_ROM_SLP GLB_CR_MCU_ROM_SLP
+#define GLB_CR_MCU_ROM_SLP_POS (6U)
+#define GLB_CR_MCU_ROM_SLP_LEN (2U)
+#define GLB_CR_MCU_ROM_SLP_MSK (((1U << GLB_CR_MCU_ROM_SLP_LEN) - 1) << GLB_CR_MCU_ROM_SLP_POS)
+#define GLB_CR_MCU_ROM_SLP_UMSK (~(((1U << GLB_CR_MCU_ROM_SLP_LEN) - 1) << GLB_CR_MCU_ROM_SLP_POS))
+#define GLB_CR_WB_RAM_SLP GLB_CR_WB_RAM_SLP
+#define GLB_CR_WB_RAM_SLP_POS (8U)
+#define GLB_CR_WB_RAM_SLP_LEN (1U)
+#define GLB_CR_WB_RAM_SLP_MSK (((1U << GLB_CR_WB_RAM_SLP_LEN) - 1) << GLB_CR_WB_RAM_SLP_POS)
+#define GLB_CR_WB_RAM_SLP_UMSK (~(((1U << GLB_CR_WB_RAM_SLP_LEN) - 1) << GLB_CR_WB_RAM_SLP_POS))
+#define GLB_CR_MISC_RAM_SLP GLB_CR_MISC_RAM_SLP
+#define GLB_CR_MISC_RAM_SLP_POS (9U)
+#define GLB_CR_MISC_RAM_SLP_LEN (2U)
+#define GLB_CR_MISC_RAM_SLP_MSK (((1U << GLB_CR_MISC_RAM_SLP_LEN) - 1) << GLB_CR_MISC_RAM_SLP_POS)
+#define GLB_CR_MISC_RAM_SLP_UMSK (~(((1U << GLB_CR_MISC_RAM_SLP_LEN) - 1) << GLB_CR_MISC_RAM_SLP_POS))
+
+/* 0x608 : reg_sram_parm */
+#define GLB_SRAM_CFG2_OFFSET (0x608)
+#define GLB_CR_MCU_CACHE_DVSE GLB_CR_MCU_CACHE_DVSE
+#define GLB_CR_MCU_CACHE_DVSE_POS (0U)
+#define GLB_CR_MCU_CACHE_DVSE_LEN (1U)
+#define GLB_CR_MCU_CACHE_DVSE_MSK (((1U << GLB_CR_MCU_CACHE_DVSE_LEN) - 1) << GLB_CR_MCU_CACHE_DVSE_POS)
+#define GLB_CR_MCU_CACHE_DVSE_UMSK (~(((1U << GLB_CR_MCU_CACHE_DVSE_LEN) - 1) << GLB_CR_MCU_CACHE_DVSE_POS))
+#define GLB_CR_MCU_HSRAM_DVSE GLB_CR_MCU_HSRAM_DVSE
+#define GLB_CR_MCU_HSRAM_DVSE_POS (1U)
+#define GLB_CR_MCU_HSRAM_DVSE_LEN (1U)
+#define GLB_CR_MCU_HSRAM_DVSE_MSK (((1U << GLB_CR_MCU_HSRAM_DVSE_LEN) - 1) << GLB_CR_MCU_HSRAM_DVSE_POS)
+#define GLB_CR_MCU_HSRAM_DVSE_UMSK (~(((1U << GLB_CR_MCU_HSRAM_DVSE_LEN) - 1) << GLB_CR_MCU_HSRAM_DVSE_POS))
+#define GLB_CR_MCU_ROM_DVSE GLB_CR_MCU_ROM_DVSE
+#define GLB_CR_MCU_ROM_DVSE_POS (2U)
+#define GLB_CR_MCU_ROM_DVSE_LEN (1U)
+#define GLB_CR_MCU_ROM_DVSE_MSK (((1U << GLB_CR_MCU_ROM_DVSE_LEN) - 1) << GLB_CR_MCU_ROM_DVSE_POS)
+#define GLB_CR_MCU_ROM_DVSE_UMSK (~(((1U << GLB_CR_MCU_ROM_DVSE_LEN) - 1) << GLB_CR_MCU_ROM_DVSE_POS))
+#define GLB_CR_WB_RAM_DVSE GLB_CR_WB_RAM_DVSE
+#define GLB_CR_WB_RAM_DVSE_POS (3U)
+#define GLB_CR_WB_RAM_DVSE_LEN (1U)
+#define GLB_CR_WB_RAM_DVSE_MSK (((1U << GLB_CR_WB_RAM_DVSE_LEN) - 1) << GLB_CR_WB_RAM_DVSE_POS)
+#define GLB_CR_WB_RAM_DVSE_UMSK (~(((1U << GLB_CR_WB_RAM_DVSE_LEN) - 1) << GLB_CR_WB_RAM_DVSE_POS))
+#define GLB_CR_MISC_RAM_DVSE GLB_CR_MISC_RAM_DVSE
+#define GLB_CR_MISC_RAM_DVSE_POS (4U)
+#define GLB_CR_MISC_RAM_DVSE_LEN (1U)
+#define GLB_CR_MISC_RAM_DVSE_MSK (((1U << GLB_CR_MISC_RAM_DVSE_LEN) - 1) << GLB_CR_MISC_RAM_DVSE_POS)
+#define GLB_CR_MISC_RAM_DVSE_UMSK (~(((1U << GLB_CR_MISC_RAM_DVSE_LEN) - 1) << GLB_CR_MISC_RAM_DVSE_POS))
+#define GLB_CR_OCRAM_DVSE GLB_CR_OCRAM_DVSE
+#define GLB_CR_OCRAM_DVSE_POS (5U)
+#define GLB_CR_OCRAM_DVSE_LEN (1U)
+#define GLB_CR_OCRAM_DVSE_MSK (((1U << GLB_CR_OCRAM_DVSE_LEN) - 1) << GLB_CR_OCRAM_DVSE_POS)
+#define GLB_CR_OCRAM_DVSE_UMSK (~(((1U << GLB_CR_OCRAM_DVSE_LEN) - 1) << GLB_CR_OCRAM_DVSE_POS))
+#define GLB_CR_WRAM_DVSE GLB_CR_WRAM_DVSE
+#define GLB_CR_WRAM_DVSE_POS (6U)
+#define GLB_CR_WRAM_DVSE_LEN (1U)
+#define GLB_CR_WRAM_DVSE_MSK (((1U << GLB_CR_WRAM_DVSE_LEN) - 1) << GLB_CR_WRAM_DVSE_POS)
+#define GLB_CR_WRAM_DVSE_UMSK (~(((1U << GLB_CR_WRAM_DVSE_LEN) - 1) << GLB_CR_WRAM_DVSE_POS))
+#define GLB_CR_MCU_CACHE_NAP GLB_CR_MCU_CACHE_NAP
+#define GLB_CR_MCU_CACHE_NAP_POS (8U)
+#define GLB_CR_MCU_CACHE_NAP_LEN (1U)
+#define GLB_CR_MCU_CACHE_NAP_MSK (((1U << GLB_CR_MCU_CACHE_NAP_LEN) - 1) << GLB_CR_MCU_CACHE_NAP_POS)
+#define GLB_CR_MCU_CACHE_NAP_UMSK (~(((1U << GLB_CR_MCU_CACHE_NAP_LEN) - 1) << GLB_CR_MCU_CACHE_NAP_POS))
+#define GLB_CR_MCU_HSRAM_NAP GLB_CR_MCU_HSRAM_NAP
+#define GLB_CR_MCU_HSRAM_NAP_POS (9U)
+#define GLB_CR_MCU_HSRAM_NAP_LEN (1U)
+#define GLB_CR_MCU_HSRAM_NAP_MSK (((1U << GLB_CR_MCU_HSRAM_NAP_LEN) - 1) << GLB_CR_MCU_HSRAM_NAP_POS)
+#define GLB_CR_MCU_HSRAM_NAP_UMSK (~(((1U << GLB_CR_MCU_HSRAM_NAP_LEN) - 1) << GLB_CR_MCU_HSRAM_NAP_POS))
+#define GLB_CR_WB_RAM_NAP GLB_CR_WB_RAM_NAP
+#define GLB_CR_WB_RAM_NAP_POS (11U)
+#define GLB_CR_WB_RAM_NAP_LEN (1U)
+#define GLB_CR_WB_RAM_NAP_MSK (((1U << GLB_CR_WB_RAM_NAP_LEN) - 1) << GLB_CR_WB_RAM_NAP_POS)
+#define GLB_CR_WB_RAM_NAP_UMSK (~(((1U << GLB_CR_WB_RAM_NAP_LEN) - 1) << GLB_CR_WB_RAM_NAP_POS))
+#define GLB_CR_MISC_RAM_NAP GLB_CR_MISC_RAM_NAP
+#define GLB_CR_MISC_RAM_NAP_POS (12U)
+#define GLB_CR_MISC_RAM_NAP_LEN (1U)
+#define GLB_CR_MISC_RAM_NAP_MSK (((1U << GLB_CR_MISC_RAM_NAP_LEN) - 1) << GLB_CR_MISC_RAM_NAP_POS)
+#define GLB_CR_MISC_RAM_NAP_UMSK (~(((1U << GLB_CR_MISC_RAM_NAP_LEN) - 1) << GLB_CR_MISC_RAM_NAP_POS))
+#define GLB_CR_OCRAM_NAP GLB_CR_OCRAM_NAP
+#define GLB_CR_OCRAM_NAP_POS (13U)
+#define GLB_CR_OCRAM_NAP_LEN (1U)
+#define GLB_CR_OCRAM_NAP_MSK (((1U << GLB_CR_OCRAM_NAP_LEN) - 1) << GLB_CR_OCRAM_NAP_POS)
+#define GLB_CR_OCRAM_NAP_UMSK (~(((1U << GLB_CR_OCRAM_NAP_LEN) - 1) << GLB_CR_OCRAM_NAP_POS))
+#define GLB_CR_WRAM_NAP GLB_CR_WRAM_NAP
+#define GLB_CR_WRAM_NAP_POS (14U)
+#define GLB_CR_WRAM_NAP_LEN (1U)
+#define GLB_CR_WRAM_NAP_MSK (((1U << GLB_CR_WRAM_NAP_LEN) - 1) << GLB_CR_WRAM_NAP_POS)
+#define GLB_CR_WRAM_NAP_UMSK (~(((1U << GLB_CR_WRAM_NAP_LEN) - 1) << GLB_CR_WRAM_NAP_POS))
+
+/* 0x60C : sram_cfg3 */
+#define GLB_SRAM_CFG3_OFFSET (0x60C)
+#define GLB_EM_SEL GLB_EM_SEL
+#define GLB_EM_SEL_POS (0U)
+#define GLB_EM_SEL_LEN (8U)
+#define GLB_EM_SEL_MSK (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
+#define GLB_EM_SEL_UMSK (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
+#define GLB_REG_VRAM_SEL GLB_REG_VRAM_SEL
+#define GLB_REG_VRAM_SEL_POS (28U)
+#define GLB_REG_VRAM_SEL_LEN (2U)
+#define GLB_REG_VRAM_SEL_MSK (((1U << GLB_REG_VRAM_SEL_LEN) - 1) << GLB_REG_VRAM_SEL_POS)
+#define GLB_REG_VRAM_SEL_UMSK (~(((1U << GLB_REG_VRAM_SEL_LEN) - 1) << GLB_REG_VRAM_SEL_POS))
+
+/* 0x610 : reg_sram_parm2 */
+#define GLB_SRAM_CFG4_OFFSET (0x610)
+#define GLB_CR_MCU_CACHE_DVS GLB_CR_MCU_CACHE_DVS
+#define GLB_CR_MCU_CACHE_DVS_POS (0U)
+#define GLB_CR_MCU_CACHE_DVS_LEN (4U)
+#define GLB_CR_MCU_CACHE_DVS_MSK (((1U << GLB_CR_MCU_CACHE_DVS_LEN) - 1) << GLB_CR_MCU_CACHE_DVS_POS)
+#define GLB_CR_MCU_CACHE_DVS_UMSK (~(((1U << GLB_CR_MCU_CACHE_DVS_LEN) - 1) << GLB_CR_MCU_CACHE_DVS_POS))
+#define GLB_CR_MCU_HSRAM_DVS GLB_CR_MCU_HSRAM_DVS
+#define GLB_CR_MCU_HSRAM_DVS_POS (4U)
+#define GLB_CR_MCU_HSRAM_DVS_LEN (4U)
+#define GLB_CR_MCU_HSRAM_DVS_MSK (((1U << GLB_CR_MCU_HSRAM_DVS_LEN) - 1) << GLB_CR_MCU_HSRAM_DVS_POS)
+#define GLB_CR_MCU_HSRAM_DVS_UMSK (~(((1U << GLB_CR_MCU_HSRAM_DVS_LEN) - 1) << GLB_CR_MCU_HSRAM_DVS_POS))
+#define GLB_CR_MCU_ROM_DVS GLB_CR_MCU_ROM_DVS
+#define GLB_CR_MCU_ROM_DVS_POS (8U)
+#define GLB_CR_MCU_ROM_DVS_LEN (4U)
+#define GLB_CR_MCU_ROM_DVS_MSK (((1U << GLB_CR_MCU_ROM_DVS_LEN) - 1) << GLB_CR_MCU_ROM_DVS_POS)
+#define GLB_CR_MCU_ROM_DVS_UMSK (~(((1U << GLB_CR_MCU_ROM_DVS_LEN) - 1) << GLB_CR_MCU_ROM_DVS_POS))
+#define GLB_CR_WB_RAM_DVS GLB_CR_WB_RAM_DVS
+#define GLB_CR_WB_RAM_DVS_POS (12U)
+#define GLB_CR_WB_RAM_DVS_LEN (4U)
+#define GLB_CR_WB_RAM_DVS_MSK (((1U << GLB_CR_WB_RAM_DVS_LEN) - 1) << GLB_CR_WB_RAM_DVS_POS)
+#define GLB_CR_WB_RAM_DVS_UMSK (~(((1U << GLB_CR_WB_RAM_DVS_LEN) - 1) << GLB_CR_WB_RAM_DVS_POS))
+#define GLB_CR_MISC_RAM_DVS GLB_CR_MISC_RAM_DVS
+#define GLB_CR_MISC_RAM_DVS_POS (16U)
+#define GLB_CR_MISC_RAM_DVS_LEN (4U)
+#define GLB_CR_MISC_RAM_DVS_MSK (((1U << GLB_CR_MISC_RAM_DVS_LEN) - 1) << GLB_CR_MISC_RAM_DVS_POS)
+#define GLB_CR_MISC_RAM_DVS_UMSK (~(((1U << GLB_CR_MISC_RAM_DVS_LEN) - 1) << GLB_CR_MISC_RAM_DVS_POS))
+#define GLB_CR_OCRAM_DVS GLB_CR_OCRAM_DVS
+#define GLB_CR_OCRAM_DVS_POS (20U)
+#define GLB_CR_OCRAM_DVS_LEN (4U)
+#define GLB_CR_OCRAM_DVS_MSK (((1U << GLB_CR_OCRAM_DVS_LEN) - 1) << GLB_CR_OCRAM_DVS_POS)
+#define GLB_CR_OCRAM_DVS_UMSK (~(((1U << GLB_CR_OCRAM_DVS_LEN) - 1) << GLB_CR_OCRAM_DVS_POS))
+#define GLB_CR_WRAM_DVS GLB_CR_WRAM_DVS
+#define GLB_CR_WRAM_DVS_POS (24U)
+#define GLB_CR_WRAM_DVS_LEN (4U)
+#define GLB_CR_WRAM_DVS_MSK (((1U << GLB_CR_WRAM_DVS_LEN) - 1) << GLB_CR_WRAM_DVS_POS)
+#define GLB_CR_WRAM_DVS_UMSK (~(((1U << GLB_CR_WRAM_DVS_LEN) - 1) << GLB_CR_WRAM_DVS_POS))
+
+/* 0x620 : psram_cfg0 */
+#define GLB_PSRAM_CFG0_OFFSET (0x620)
+#define GLB_REG_PSRAMB_CLK_EN GLB_REG_PSRAMB_CLK_EN
+#define GLB_REG_PSRAMB_CLK_EN_POS (27U)
+#define GLB_REG_PSRAMB_CLK_EN_LEN (1U)
+#define GLB_REG_PSRAMB_CLK_EN_MSK (((1U << GLB_REG_PSRAMB_CLK_EN_LEN) - 1) << GLB_REG_PSRAMB_CLK_EN_POS)
+#define GLB_REG_PSRAMB_CLK_EN_UMSK (~(((1U << GLB_REG_PSRAMB_CLK_EN_LEN) - 1) << GLB_REG_PSRAMB_CLK_EN_POS))
+#define GLB_REG_PSRAMB_CLK_SEL GLB_REG_PSRAMB_CLK_SEL
+#define GLB_REG_PSRAMB_CLK_SEL_POS (28U)
+#define GLB_REG_PSRAMB_CLK_SEL_LEN (2U)
+#define GLB_REG_PSRAMB_CLK_SEL_MSK (((1U << GLB_REG_PSRAMB_CLK_SEL_LEN) - 1) << GLB_REG_PSRAMB_CLK_SEL_POS)
+#define GLB_REG_PSRAMB_CLK_SEL_UMSK (~(((1U << GLB_REG_PSRAMB_CLK_SEL_LEN) - 1) << GLB_REG_PSRAMB_CLK_SEL_POS))
+#define GLB_REG_PSRAMB_CLK_DIV GLB_REG_PSRAMB_CLK_DIV
+#define GLB_REG_PSRAMB_CLK_DIV_POS (30U)
+#define GLB_REG_PSRAMB_CLK_DIV_LEN (2U)
+#define GLB_REG_PSRAMB_CLK_DIV_MSK (((1U << GLB_REG_PSRAMB_CLK_DIV_LEN) - 1) << GLB_REG_PSRAMB_CLK_DIV_POS)
+#define GLB_REG_PSRAMB_CLK_DIV_UMSK (~(((1U << GLB_REG_PSRAMB_CLK_DIV_LEN) - 1) << GLB_REG_PSRAMB_CLK_DIV_POS))
+
+/* 0x6C0 : ldo28cis */
+#define GLB_LDO28CIS_OFFSET (0x6C0)
+#define GLB_PU_LDO28CIS GLB_PU_LDO28CIS
+#define GLB_PU_LDO28CIS_POS (0U)
+#define GLB_PU_LDO28CIS_LEN (1U)
+#define GLB_PU_LDO28CIS_MSK (((1U << GLB_PU_LDO28CIS_LEN) - 1) << GLB_PU_LDO28CIS_POS)
+#define GLB_PU_LDO28CIS_UMSK (~(((1U << GLB_PU_LDO28CIS_LEN) - 1) << GLB_PU_LDO28CIS_POS))
+#define GLB_LDO28CIS_BYPASS GLB_LDO28CIS_BYPASS
+#define GLB_LDO28CIS_BYPASS_POS (1U)
+#define GLB_LDO28CIS_BYPASS_LEN (1U)
+#define GLB_LDO28CIS_BYPASS_MSK (((1U << GLB_LDO28CIS_BYPASS_LEN) - 1) << GLB_LDO28CIS_BYPASS_POS)
+#define GLB_LDO28CIS_BYPASS_UMSK (~(((1U << GLB_LDO28CIS_BYPASS_LEN) - 1) << GLB_LDO28CIS_BYPASS_POS))
+#define GLB_LDO28CIS_PULLDOWN GLB_LDO28CIS_PULLDOWN
+#define GLB_LDO28CIS_PULLDOWN_POS (2U)
+#define GLB_LDO28CIS_PULLDOWN_LEN (1U)
+#define GLB_LDO28CIS_PULLDOWN_MSK (((1U << GLB_LDO28CIS_PULLDOWN_LEN) - 1) << GLB_LDO28CIS_PULLDOWN_POS)
+#define GLB_LDO28CIS_PULLDOWN_UMSK (~(((1U << GLB_LDO28CIS_PULLDOWN_LEN) - 1) << GLB_LDO28CIS_PULLDOWN_POS))
+#define GLB_LDO28CIS_PULLDOWN_SEL GLB_LDO28CIS_PULLDOWN_SEL
+#define GLB_LDO28CIS_PULLDOWN_SEL_POS (3U)
+#define GLB_LDO28CIS_PULLDOWN_SEL_LEN (1U)
+#define GLB_LDO28CIS_PULLDOWN_SEL_MSK (((1U << GLB_LDO28CIS_PULLDOWN_SEL_LEN) - 1) << GLB_LDO28CIS_PULLDOWN_SEL_POS)
+#define GLB_LDO28CIS_PULLDOWN_SEL_UMSK (~(((1U << GLB_LDO28CIS_PULLDOWN_SEL_LEN) - 1) << GLB_LDO28CIS_PULLDOWN_SEL_POS))
+#define GLB_LDO28CIS_BM GLB_LDO28CIS_BM
+#define GLB_LDO28CIS_BM_POS (4U)
+#define GLB_LDO28CIS_BM_LEN (3U)
+#define GLB_LDO28CIS_BM_MSK (((1U << GLB_LDO28CIS_BM_LEN) - 1) << GLB_LDO28CIS_BM_POS)
+#define GLB_LDO28CIS_BM_UMSK (~(((1U << GLB_LDO28CIS_BM_LEN) - 1) << GLB_LDO28CIS_BM_POS))
+#define GLB_LDO28CIS_CC GLB_LDO28CIS_CC
+#define GLB_LDO28CIS_CC_POS (8U)
+#define GLB_LDO28CIS_CC_LEN (3U)
+#define GLB_LDO28CIS_CC_MSK (((1U << GLB_LDO28CIS_CC_LEN) - 1) << GLB_LDO28CIS_CC_POS)
+#define GLB_LDO28CIS_CC_UMSK (~(((1U << GLB_LDO28CIS_CC_LEN) - 1) << GLB_LDO28CIS_CC_POS))
+#define GLB_LDO28CIS_OCP_OUT GLB_LDO28CIS_OCP_OUT
+#define GLB_LDO28CIS_OCP_OUT_POS (11U)
+#define GLB_LDO28CIS_OCP_OUT_LEN (1U)
+#define GLB_LDO28CIS_OCP_OUT_MSK (((1U << GLB_LDO28CIS_OCP_OUT_LEN) - 1) << GLB_LDO28CIS_OCP_OUT_POS)
+#define GLB_LDO28CIS_OCP_OUT_UMSK (~(((1U << GLB_LDO28CIS_OCP_OUT_LEN) - 1) << GLB_LDO28CIS_OCP_OUT_POS))
+#define GLB_LDO28CIS_OCP_TH GLB_LDO28CIS_OCP_TH
+#define GLB_LDO28CIS_OCP_TH_POS (12U)
+#define GLB_LDO28CIS_OCP_TH_LEN (3U)
+#define GLB_LDO28CIS_OCP_TH_MSK (((1U << GLB_LDO28CIS_OCP_TH_LEN) - 1) << GLB_LDO28CIS_OCP_TH_POS)
+#define GLB_LDO28CIS_OCP_TH_UMSK (~(((1U << GLB_LDO28CIS_OCP_TH_LEN) - 1) << GLB_LDO28CIS_OCP_TH_POS))
+#define GLB_LDO28CIS_OCP_EN GLB_LDO28CIS_OCP_EN
+#define GLB_LDO28CIS_OCP_EN_POS (15U)
+#define GLB_LDO28CIS_OCP_EN_LEN (1U)
+#define GLB_LDO28CIS_OCP_EN_MSK (((1U << GLB_LDO28CIS_OCP_EN_LEN) - 1) << GLB_LDO28CIS_OCP_EN_POS)
+#define GLB_LDO28CIS_OCP_EN_UMSK (~(((1U << GLB_LDO28CIS_OCP_EN_LEN) - 1) << GLB_LDO28CIS_OCP_EN_POS))
+#define GLB_LDO28CIS_SSTART_DELAY GLB_LDO28CIS_SSTART_DELAY
+#define GLB_LDO28CIS_SSTART_DELAY_POS (16U)
+#define GLB_LDO28CIS_SSTART_DELAY_LEN (3U)
+#define GLB_LDO28CIS_SSTART_DELAY_MSK (((1U << GLB_LDO28CIS_SSTART_DELAY_LEN) - 1) << GLB_LDO28CIS_SSTART_DELAY_POS)
+#define GLB_LDO28CIS_SSTART_DELAY_UMSK (~(((1U << GLB_LDO28CIS_SSTART_DELAY_LEN) - 1) << GLB_LDO28CIS_SSTART_DELAY_POS))
+#define GLB_LDO28CIS_SSTART_EN GLB_LDO28CIS_SSTART_EN
+#define GLB_LDO28CIS_SSTART_EN_POS (19U)
+#define GLB_LDO28CIS_SSTART_EN_LEN (1U)
+#define GLB_LDO28CIS_SSTART_EN_MSK (((1U << GLB_LDO28CIS_SSTART_EN_LEN) - 1) << GLB_LDO28CIS_SSTART_EN_POS)
+#define GLB_LDO28CIS_SSTART_EN_UMSK (~(((1U << GLB_LDO28CIS_SSTART_EN_LEN) - 1) << GLB_LDO28CIS_SSTART_EN_POS))
+#define GLB_LDO28CIS_VOUT_SEL GLB_LDO28CIS_VOUT_SEL
+#define GLB_LDO28CIS_VOUT_SEL_POS (20U)
+#define GLB_LDO28CIS_VOUT_SEL_LEN (4U)
+#define GLB_LDO28CIS_VOUT_SEL_MSK (((1U << GLB_LDO28CIS_VOUT_SEL_LEN) - 1) << GLB_LDO28CIS_VOUT_SEL_POS)
+#define GLB_LDO28CIS_VOUT_SEL_UMSK (~(((1U << GLB_LDO28CIS_VOUT_SEL_LEN) - 1) << GLB_LDO28CIS_VOUT_SEL_POS))
+#define GLB_LDO28CIS_VOUT_TRIM GLB_LDO28CIS_VOUT_TRIM
+#define GLB_LDO28CIS_VOUT_TRIM_POS (24U)
+#define GLB_LDO28CIS_VOUT_TRIM_LEN (4U)
+#define GLB_LDO28CIS_VOUT_TRIM_MSK (((1U << GLB_LDO28CIS_VOUT_TRIM_LEN) - 1) << GLB_LDO28CIS_VOUT_TRIM_POS)
+#define GLB_LDO28CIS_VOUT_TRIM_UMSK (~(((1U << GLB_LDO28CIS_VOUT_TRIM_LEN) - 1) << GLB_LDO28CIS_VOUT_TRIM_POS))
+
+/* 0x6C4 : ldo18io */
+#define GLB_LDO18IO_OFFSET (0x6C4)
+
+/* 0x6C8 : ldo15cis */
+#define GLB_LDO15CIS_OFFSET (0x6C8)
+#define GLB_PU_LDO15CIS GLB_PU_LDO15CIS
+#define GLB_PU_LDO15CIS_POS (0U)
+#define GLB_PU_LDO15CIS_LEN (1U)
+#define GLB_PU_LDO15CIS_MSK (((1U << GLB_PU_LDO15CIS_LEN) - 1) << GLB_PU_LDO15CIS_POS)
+#define GLB_PU_LDO15CIS_UMSK (~(((1U << GLB_PU_LDO15CIS_LEN) - 1) << GLB_PU_LDO15CIS_POS))
+#define GLB_LDO15CIS_BYPASS GLB_LDO15CIS_BYPASS
+#define GLB_LDO15CIS_BYPASS_POS (1U)
+#define GLB_LDO15CIS_BYPASS_LEN (1U)
+#define GLB_LDO15CIS_BYPASS_MSK (((1U << GLB_LDO15CIS_BYPASS_LEN) - 1) << GLB_LDO15CIS_BYPASS_POS)
+#define GLB_LDO15CIS_BYPASS_UMSK (~(((1U << GLB_LDO15CIS_BYPASS_LEN) - 1) << GLB_LDO15CIS_BYPASS_POS))
+#define GLB_LDO15CIS_PULLDOWN GLB_LDO15CIS_PULLDOWN
+#define GLB_LDO15CIS_PULLDOWN_POS (2U)
+#define GLB_LDO15CIS_PULLDOWN_LEN (1U)
+#define GLB_LDO15CIS_PULLDOWN_MSK (((1U << GLB_LDO15CIS_PULLDOWN_LEN) - 1) << GLB_LDO15CIS_PULLDOWN_POS)
+#define GLB_LDO15CIS_PULLDOWN_UMSK (~(((1U << GLB_LDO15CIS_PULLDOWN_LEN) - 1) << GLB_LDO15CIS_PULLDOWN_POS))
+#define GLB_LDO15CIS_PULLDOWN_SEL GLB_LDO15CIS_PULLDOWN_SEL
+#define GLB_LDO15CIS_PULLDOWN_SEL_POS (3U)
+#define GLB_LDO15CIS_PULLDOWN_SEL_LEN (1U)
+#define GLB_LDO15CIS_PULLDOWN_SEL_MSK (((1U << GLB_LDO15CIS_PULLDOWN_SEL_LEN) - 1) << GLB_LDO15CIS_PULLDOWN_SEL_POS)
+#define GLB_LDO15CIS_PULLDOWN_SEL_UMSK (~(((1U << GLB_LDO15CIS_PULLDOWN_SEL_LEN) - 1) << GLB_LDO15CIS_PULLDOWN_SEL_POS))
+#define GLB_LDO15CIS_BM GLB_LDO15CIS_BM
+#define GLB_LDO15CIS_BM_POS (4U)
+#define GLB_LDO15CIS_BM_LEN (3U)
+#define GLB_LDO15CIS_BM_MSK (((1U << GLB_LDO15CIS_BM_LEN) - 1) << GLB_LDO15CIS_BM_POS)
+#define GLB_LDO15CIS_BM_UMSK (~(((1U << GLB_LDO15CIS_BM_LEN) - 1) << GLB_LDO15CIS_BM_POS))
+#define GLB_LDO15CIS_CC GLB_LDO15CIS_CC
+#define GLB_LDO15CIS_CC_POS (8U)
+#define GLB_LDO15CIS_CC_LEN (3U)
+#define GLB_LDO15CIS_CC_MSK (((1U << GLB_LDO15CIS_CC_LEN) - 1) << GLB_LDO15CIS_CC_POS)
+#define GLB_LDO15CIS_CC_UMSK (~(((1U << GLB_LDO15CIS_CC_LEN) - 1) << GLB_LDO15CIS_CC_POS))
+#define GLB_LDO15CIS_OCP_OUT GLB_LDO15CIS_OCP_OUT
+#define GLB_LDO15CIS_OCP_OUT_POS (11U)
+#define GLB_LDO15CIS_OCP_OUT_LEN (1U)
+#define GLB_LDO15CIS_OCP_OUT_MSK (((1U << GLB_LDO15CIS_OCP_OUT_LEN) - 1) << GLB_LDO15CIS_OCP_OUT_POS)
+#define GLB_LDO15CIS_OCP_OUT_UMSK (~(((1U << GLB_LDO15CIS_OCP_OUT_LEN) - 1) << GLB_LDO15CIS_OCP_OUT_POS))
+#define GLB_LDO15CIS_OCP_TH GLB_LDO15CIS_OCP_TH
+#define GLB_LDO15CIS_OCP_TH_POS (12U)
+#define GLB_LDO15CIS_OCP_TH_LEN (3U)
+#define GLB_LDO15CIS_OCP_TH_MSK (((1U << GLB_LDO15CIS_OCP_TH_LEN) - 1) << GLB_LDO15CIS_OCP_TH_POS)
+#define GLB_LDO15CIS_OCP_TH_UMSK (~(((1U << GLB_LDO15CIS_OCP_TH_LEN) - 1) << GLB_LDO15CIS_OCP_TH_POS))
+#define GLB_LDO15CIS_OCP_EN GLB_LDO15CIS_OCP_EN
+#define GLB_LDO15CIS_OCP_EN_POS (15U)
+#define GLB_LDO15CIS_OCP_EN_LEN (1U)
+#define GLB_LDO15CIS_OCP_EN_MSK (((1U << GLB_LDO15CIS_OCP_EN_LEN) - 1) << GLB_LDO15CIS_OCP_EN_POS)
+#define GLB_LDO15CIS_OCP_EN_UMSK (~(((1U << GLB_LDO15CIS_OCP_EN_LEN) - 1) << GLB_LDO15CIS_OCP_EN_POS))
+#define GLB_LDO15CIS_SSTART_DELAY GLB_LDO15CIS_SSTART_DELAY
+#define GLB_LDO15CIS_SSTART_DELAY_POS (16U)
+#define GLB_LDO15CIS_SSTART_DELAY_LEN (3U)
+#define GLB_LDO15CIS_SSTART_DELAY_MSK (((1U << GLB_LDO15CIS_SSTART_DELAY_LEN) - 1) << GLB_LDO15CIS_SSTART_DELAY_POS)
+#define GLB_LDO15CIS_SSTART_DELAY_UMSK (~(((1U << GLB_LDO15CIS_SSTART_DELAY_LEN) - 1) << GLB_LDO15CIS_SSTART_DELAY_POS))
+#define GLB_LDO15CIS_SSTART_EN GLB_LDO15CIS_SSTART_EN
+#define GLB_LDO15CIS_SSTART_EN_POS (19U)
+#define GLB_LDO15CIS_SSTART_EN_LEN (1U)
+#define GLB_LDO15CIS_SSTART_EN_MSK (((1U << GLB_LDO15CIS_SSTART_EN_LEN) - 1) << GLB_LDO15CIS_SSTART_EN_POS)
+#define GLB_LDO15CIS_SSTART_EN_UMSK (~(((1U << GLB_LDO15CIS_SSTART_EN_LEN) - 1) << GLB_LDO15CIS_SSTART_EN_POS))
+#define GLB_LDO15CIS_VOUT_SEL GLB_LDO15CIS_VOUT_SEL
+#define GLB_LDO15CIS_VOUT_SEL_POS (20U)
+#define GLB_LDO15CIS_VOUT_SEL_LEN (4U)
+#define GLB_LDO15CIS_VOUT_SEL_MSK (((1U << GLB_LDO15CIS_VOUT_SEL_LEN) - 1) << GLB_LDO15CIS_VOUT_SEL_POS)
+#define GLB_LDO15CIS_VOUT_SEL_UMSK (~(((1U << GLB_LDO15CIS_VOUT_SEL_LEN) - 1) << GLB_LDO15CIS_VOUT_SEL_POS))
+#define GLB_LDO15CIS_VOUT_TRIM GLB_LDO15CIS_VOUT_TRIM
+#define GLB_LDO15CIS_VOUT_TRIM_POS (24U)
+#define GLB_LDO15CIS_VOUT_TRIM_LEN (4U)
+#define GLB_LDO15CIS_VOUT_TRIM_MSK (((1U << GLB_LDO15CIS_VOUT_TRIM_LEN) - 1) << GLB_LDO15CIS_VOUT_TRIM_POS)
+#define GLB_LDO15CIS_VOUT_TRIM_UMSK (~(((1U << GLB_LDO15CIS_VOUT_TRIM_LEN) - 1) << GLB_LDO15CIS_VOUT_TRIM_POS))
+
+/* 0x6CC : ldo18flash */
+#define GLB_LDO18FLASH_OFFSET (0x6CC)
+#define GLB_PU_LDO18FLASH GLB_PU_LDO18FLASH
+#define GLB_PU_LDO18FLASH_POS (0U)
+#define GLB_PU_LDO18FLASH_LEN (1U)
+#define GLB_PU_LDO18FLASH_MSK (((1U << GLB_PU_LDO18FLASH_LEN) - 1) << GLB_PU_LDO18FLASH_POS)
+#define GLB_PU_LDO18FLASH_UMSK (~(((1U << GLB_PU_LDO18FLASH_LEN) - 1) << GLB_PU_LDO18FLASH_POS))
+#define GLB_LDO18FLASH_BYPASS GLB_LDO18FLASH_BYPASS
+#define GLB_LDO18FLASH_BYPASS_POS (1U)
+#define GLB_LDO18FLASH_BYPASS_LEN (1U)
+#define GLB_LDO18FLASH_BYPASS_MSK (((1U << GLB_LDO18FLASH_BYPASS_LEN) - 1) << GLB_LDO18FLASH_BYPASS_POS)
+#define GLB_LDO18FLASH_BYPASS_UMSK (~(((1U << GLB_LDO18FLASH_BYPASS_LEN) - 1) << GLB_LDO18FLASH_BYPASS_POS))
+#define GLB_LDO18FLASH_PULLDOWN GLB_LDO18FLASH_PULLDOWN
+#define GLB_LDO18FLASH_PULLDOWN_POS (2U)
+#define GLB_LDO18FLASH_PULLDOWN_LEN (1U)
+#define GLB_LDO18FLASH_PULLDOWN_MSK (((1U << GLB_LDO18FLASH_PULLDOWN_LEN) - 1) << GLB_LDO18FLASH_PULLDOWN_POS)
+#define GLB_LDO18FLASH_PULLDOWN_UMSK (~(((1U << GLB_LDO18FLASH_PULLDOWN_LEN) - 1) << GLB_LDO18FLASH_PULLDOWN_POS))
+#define GLB_LDO18FLASH_PULLDOWN_SEL GLB_LDO18FLASH_PULLDOWN_SEL
+#define GLB_LDO18FLASH_PULLDOWN_SEL_POS (3U)
+#define GLB_LDO18FLASH_PULLDOWN_SEL_LEN (1U)
+#define GLB_LDO18FLASH_PULLDOWN_SEL_MSK (((1U << GLB_LDO18FLASH_PULLDOWN_SEL_LEN) - 1) << GLB_LDO18FLASH_PULLDOWN_SEL_POS)
+#define GLB_LDO18FLASH_PULLDOWN_SEL_UMSK (~(((1U << GLB_LDO18FLASH_PULLDOWN_SEL_LEN) - 1) << GLB_LDO18FLASH_PULLDOWN_SEL_POS))
+#define GLB_LDO18FLASH_BM GLB_LDO18FLASH_BM
+#define GLB_LDO18FLASH_BM_POS (4U)
+#define GLB_LDO18FLASH_BM_LEN (3U)
+#define GLB_LDO18FLASH_BM_MSK (((1U << GLB_LDO18FLASH_BM_LEN) - 1) << GLB_LDO18FLASH_BM_POS)
+#define GLB_LDO18FLASH_BM_UMSK (~(((1U << GLB_LDO18FLASH_BM_LEN) - 1) << GLB_LDO18FLASH_BM_POS))
+#define GLB_LDO18FLASH_CC GLB_LDO18FLASH_CC
+#define GLB_LDO18FLASH_CC_POS (8U)
+#define GLB_LDO18FLASH_CC_LEN (3U)
+#define GLB_LDO18FLASH_CC_MSK (((1U << GLB_LDO18FLASH_CC_LEN) - 1) << GLB_LDO18FLASH_CC_POS)
+#define GLB_LDO18FLASH_CC_UMSK (~(((1U << GLB_LDO18FLASH_CC_LEN) - 1) << GLB_LDO18FLASH_CC_POS))
+#define GLB_LDO18FLASH_OCP_OUT GLB_LDO18FLASH_OCP_OUT
+#define GLB_LDO18FLASH_OCP_OUT_POS (11U)
+#define GLB_LDO18FLASH_OCP_OUT_LEN (1U)
+#define GLB_LDO18FLASH_OCP_OUT_MSK (((1U << GLB_LDO18FLASH_OCP_OUT_LEN) - 1) << GLB_LDO18FLASH_OCP_OUT_POS)
+#define GLB_LDO18FLASH_OCP_OUT_UMSK (~(((1U << GLB_LDO18FLASH_OCP_OUT_LEN) - 1) << GLB_LDO18FLASH_OCP_OUT_POS))
+#define GLB_LDO18FLASH_OCP_TH GLB_LDO18FLASH_OCP_TH
+#define GLB_LDO18FLASH_OCP_TH_POS (12U)
+#define GLB_LDO18FLASH_OCP_TH_LEN (3U)
+#define GLB_LDO18FLASH_OCP_TH_MSK (((1U << GLB_LDO18FLASH_OCP_TH_LEN) - 1) << GLB_LDO18FLASH_OCP_TH_POS)
+#define GLB_LDO18FLASH_OCP_TH_UMSK (~(((1U << GLB_LDO18FLASH_OCP_TH_LEN) - 1) << GLB_LDO18FLASH_OCP_TH_POS))
+#define GLB_LDO18FLASH_OCP_EN GLB_LDO18FLASH_OCP_EN
+#define GLB_LDO18FLASH_OCP_EN_POS (15U)
+#define GLB_LDO18FLASH_OCP_EN_LEN (1U)
+#define GLB_LDO18FLASH_OCP_EN_MSK (((1U << GLB_LDO18FLASH_OCP_EN_LEN) - 1) << GLB_LDO18FLASH_OCP_EN_POS)
+#define GLB_LDO18FLASH_OCP_EN_UMSK (~(((1U << GLB_LDO18FLASH_OCP_EN_LEN) - 1) << GLB_LDO18FLASH_OCP_EN_POS))
+#define GLB_LDO18FLASH_SSTART_DELAY GLB_LDO18FLASH_SSTART_DELAY
+#define GLB_LDO18FLASH_SSTART_DELAY_POS (16U)
+#define GLB_LDO18FLASH_SSTART_DELAY_LEN (3U)
+#define GLB_LDO18FLASH_SSTART_DELAY_MSK (((1U << GLB_LDO18FLASH_SSTART_DELAY_LEN) - 1) << GLB_LDO18FLASH_SSTART_DELAY_POS)
+#define GLB_LDO18FLASH_SSTART_DELAY_UMSK (~(((1U << GLB_LDO18FLASH_SSTART_DELAY_LEN) - 1) << GLB_LDO18FLASH_SSTART_DELAY_POS))
+#define GLB_LDO18FLASH_SSTART_EN GLB_LDO18FLASH_SSTART_EN
+#define GLB_LDO18FLASH_SSTART_EN_POS (19U)
+#define GLB_LDO18FLASH_SSTART_EN_LEN (1U)
+#define GLB_LDO18FLASH_SSTART_EN_MSK (((1U << GLB_LDO18FLASH_SSTART_EN_LEN) - 1) << GLB_LDO18FLASH_SSTART_EN_POS)
+#define GLB_LDO18FLASH_SSTART_EN_UMSK (~(((1U << GLB_LDO18FLASH_SSTART_EN_LEN) - 1) << GLB_LDO18FLASH_SSTART_EN_POS))
+#define GLB_LDO18FLASH_VOUT_SEL GLB_LDO18FLASH_VOUT_SEL
+#define GLB_LDO18FLASH_VOUT_SEL_POS (20U)
+#define GLB_LDO18FLASH_VOUT_SEL_LEN (4U)
+#define GLB_LDO18FLASH_VOUT_SEL_MSK (((1U << GLB_LDO18FLASH_VOUT_SEL_LEN) - 1) << GLB_LDO18FLASH_VOUT_SEL_POS)
+#define GLB_LDO18FLASH_VOUT_SEL_UMSK (~(((1U << GLB_LDO18FLASH_VOUT_SEL_LEN) - 1) << GLB_LDO18FLASH_VOUT_SEL_POS))
+#define GLB_LDO18FLASH_VOUT_TRIM GLB_LDO18FLASH_VOUT_TRIM
+#define GLB_LDO18FLASH_VOUT_TRIM_POS (24U)
+#define GLB_LDO18FLASH_VOUT_TRIM_LEN (4U)
+#define GLB_LDO18FLASH_VOUT_TRIM_MSK (((1U << GLB_LDO18FLASH_VOUT_TRIM_LEN) - 1) << GLB_LDO18FLASH_VOUT_TRIM_POS)
+#define GLB_LDO18FLASH_VOUT_TRIM_UMSK (~(((1U << GLB_LDO18FLASH_VOUT_TRIM_LEN) - 1) << GLB_LDO18FLASH_VOUT_TRIM_POS))
+
+/* 0x6D0 : ldo12uhs */
+#define GLB_LDO12UHS_OFFSET (0x6D0)
+#define GLB_PU_LDO12UHS GLB_PU_LDO12UHS
+#define GLB_PU_LDO12UHS_POS (0U)
+#define GLB_PU_LDO12UHS_LEN (1U)
+#define GLB_PU_LDO12UHS_MSK (((1U << GLB_PU_LDO12UHS_LEN) - 1) << GLB_PU_LDO12UHS_POS)
+#define GLB_PU_LDO12UHS_UMSK (~(((1U << GLB_PU_LDO12UHS_LEN) - 1) << GLB_PU_LDO12UHS_POS))
+#define GLB_LDO12UHS_BYPASS GLB_LDO12UHS_BYPASS
+#define GLB_LDO12UHS_BYPASS_POS (1U)
+#define GLB_LDO12UHS_BYPASS_LEN (1U)
+#define GLB_LDO12UHS_BYPASS_MSK (((1U << GLB_LDO12UHS_BYPASS_LEN) - 1) << GLB_LDO12UHS_BYPASS_POS)
+#define GLB_LDO12UHS_BYPASS_UMSK (~(((1U << GLB_LDO12UHS_BYPASS_LEN) - 1) << GLB_LDO12UHS_BYPASS_POS))
+#define GLB_LDO12UHS_PULLDOWN GLB_LDO12UHS_PULLDOWN
+#define GLB_LDO12UHS_PULLDOWN_POS (2U)
+#define GLB_LDO12UHS_PULLDOWN_LEN (1U)
+#define GLB_LDO12UHS_PULLDOWN_MSK (((1U << GLB_LDO12UHS_PULLDOWN_LEN) - 1) << GLB_LDO12UHS_PULLDOWN_POS)
+#define GLB_LDO12UHS_PULLDOWN_UMSK (~(((1U << GLB_LDO12UHS_PULLDOWN_LEN) - 1) << GLB_LDO12UHS_PULLDOWN_POS))
+#define GLB_LDO12UHS_PULLDOWN_SEL GLB_LDO12UHS_PULLDOWN_SEL
+#define GLB_LDO12UHS_PULLDOWN_SEL_POS (3U)
+#define GLB_LDO12UHS_PULLDOWN_SEL_LEN (1U)
+#define GLB_LDO12UHS_PULLDOWN_SEL_MSK (((1U << GLB_LDO12UHS_PULLDOWN_SEL_LEN) - 1) << GLB_LDO12UHS_PULLDOWN_SEL_POS)
+#define GLB_LDO12UHS_PULLDOWN_SEL_UMSK (~(((1U << GLB_LDO12UHS_PULLDOWN_SEL_LEN) - 1) << GLB_LDO12UHS_PULLDOWN_SEL_POS))
+#define GLB_LDO12UHS_BM GLB_LDO12UHS_BM
+#define GLB_LDO12UHS_BM_POS (4U)
+#define GLB_LDO12UHS_BM_LEN (3U)
+#define GLB_LDO12UHS_BM_MSK (((1U << GLB_LDO12UHS_BM_LEN) - 1) << GLB_LDO12UHS_BM_POS)
+#define GLB_LDO12UHS_BM_UMSK (~(((1U << GLB_LDO12UHS_BM_LEN) - 1) << GLB_LDO12UHS_BM_POS))
+#define GLB_LDO12UHS_CC GLB_LDO12UHS_CC
+#define GLB_LDO12UHS_CC_POS (8U)
+#define GLB_LDO12UHS_CC_LEN (3U)
+#define GLB_LDO12UHS_CC_MSK (((1U << GLB_LDO12UHS_CC_LEN) - 1) << GLB_LDO12UHS_CC_POS)
+#define GLB_LDO12UHS_CC_UMSK (~(((1U << GLB_LDO12UHS_CC_LEN) - 1) << GLB_LDO12UHS_CC_POS))
+#define GLB_LDO12UHS_OCP_OUT GLB_LDO12UHS_OCP_OUT
+#define GLB_LDO12UHS_OCP_OUT_POS (11U)
+#define GLB_LDO12UHS_OCP_OUT_LEN (1U)
+#define GLB_LDO12UHS_OCP_OUT_MSK (((1U << GLB_LDO12UHS_OCP_OUT_LEN) - 1) << GLB_LDO12UHS_OCP_OUT_POS)
+#define GLB_LDO12UHS_OCP_OUT_UMSK (~(((1U << GLB_LDO12UHS_OCP_OUT_LEN) - 1) << GLB_LDO12UHS_OCP_OUT_POS))
+#define GLB_LDO12UHS_OCP_TH GLB_LDO12UHS_OCP_TH
+#define GLB_LDO12UHS_OCP_TH_POS (12U)
+#define GLB_LDO12UHS_OCP_TH_LEN (3U)
+#define GLB_LDO12UHS_OCP_TH_MSK (((1U << GLB_LDO12UHS_OCP_TH_LEN) - 1) << GLB_LDO12UHS_OCP_TH_POS)
+#define GLB_LDO12UHS_OCP_TH_UMSK (~(((1U << GLB_LDO12UHS_OCP_TH_LEN) - 1) << GLB_LDO12UHS_OCP_TH_POS))
+#define GLB_LDO12UHS_OCP_EN GLB_LDO12UHS_OCP_EN
+#define GLB_LDO12UHS_OCP_EN_POS (15U)
+#define GLB_LDO12UHS_OCP_EN_LEN (1U)
+#define GLB_LDO12UHS_OCP_EN_MSK (((1U << GLB_LDO12UHS_OCP_EN_LEN) - 1) << GLB_LDO12UHS_OCP_EN_POS)
+#define GLB_LDO12UHS_OCP_EN_UMSK (~(((1U << GLB_LDO12UHS_OCP_EN_LEN) - 1) << GLB_LDO12UHS_OCP_EN_POS))
+#define GLB_LDO12UHS_SSTART_DELAY GLB_LDO12UHS_SSTART_DELAY
+#define GLB_LDO12UHS_SSTART_DELAY_POS (16U)
+#define GLB_LDO12UHS_SSTART_DELAY_LEN (3U)
+#define GLB_LDO12UHS_SSTART_DELAY_MSK (((1U << GLB_LDO12UHS_SSTART_DELAY_LEN) - 1) << GLB_LDO12UHS_SSTART_DELAY_POS)
+#define GLB_LDO12UHS_SSTART_DELAY_UMSK (~(((1U << GLB_LDO12UHS_SSTART_DELAY_LEN) - 1) << GLB_LDO12UHS_SSTART_DELAY_POS))
+#define GLB_LDO12UHS_SSTART_EN GLB_LDO12UHS_SSTART_EN
+#define GLB_LDO12UHS_SSTART_EN_POS (19U)
+#define GLB_LDO12UHS_SSTART_EN_LEN (1U)
+#define GLB_LDO12UHS_SSTART_EN_MSK (((1U << GLB_LDO12UHS_SSTART_EN_LEN) - 1) << GLB_LDO12UHS_SSTART_EN_POS)
+#define GLB_LDO12UHS_SSTART_EN_UMSK (~(((1U << GLB_LDO12UHS_SSTART_EN_LEN) - 1) << GLB_LDO12UHS_SSTART_EN_POS))
+#define GLB_LDO12UHS_VOUT_SEL GLB_LDO12UHS_VOUT_SEL
+#define GLB_LDO12UHS_VOUT_SEL_POS (20U)
+#define GLB_LDO12UHS_VOUT_SEL_LEN (4U)
+#define GLB_LDO12UHS_VOUT_SEL_MSK (((1U << GLB_LDO12UHS_VOUT_SEL_LEN) - 1) << GLB_LDO12UHS_VOUT_SEL_POS)
+#define GLB_LDO12UHS_VOUT_SEL_UMSK (~(((1U << GLB_LDO12UHS_VOUT_SEL_LEN) - 1) << GLB_LDO12UHS_VOUT_SEL_POS))
+#define GLB_LDO12UHS_VOUT_TRIM GLB_LDO12UHS_VOUT_TRIM
+#define GLB_LDO12UHS_VOUT_TRIM_POS (24U)
+#define GLB_LDO12UHS_VOUT_TRIM_LEN (4U)
+#define GLB_LDO12UHS_VOUT_TRIM_MSK (((1U << GLB_LDO12UHS_VOUT_TRIM_LEN) - 1) << GLB_LDO12UHS_VOUT_TRIM_POS)
+#define GLB_LDO12UHS_VOUT_TRIM_UMSK (~(((1U << GLB_LDO12UHS_VOUT_TRIM_LEN) - 1) << GLB_LDO12UHS_VOUT_TRIM_POS))
+
+/* 0x6F0 : proc_mon */
+#define GLB_PROC_MON_OFFSET (0x6F0)
+#define GLB_PU_PROC_MON GLB_PU_PROC_MON
+#define GLB_PU_PROC_MON_POS (0U)
+#define GLB_PU_PROC_MON_LEN (1U)
+#define GLB_PU_PROC_MON_MSK (((1U << GLB_PU_PROC_MON_LEN) - 1) << GLB_PU_PROC_MON_POS)
+#define GLB_PU_PROC_MON_UMSK (~(((1U << GLB_PU_PROC_MON_LEN) - 1) << GLB_PU_PROC_MON_POS))
+#define GLB_OSC_EN_RVT GLB_OSC_EN_RVT
+#define GLB_OSC_EN_RVT_POS (1U)
+#define GLB_OSC_EN_RVT_LEN (1U)
+#define GLB_OSC_EN_RVT_MSK (((1U << GLB_OSC_EN_RVT_LEN) - 1) << GLB_OSC_EN_RVT_POS)
+#define GLB_OSC_EN_RVT_UMSK (~(((1U << GLB_OSC_EN_RVT_LEN) - 1) << GLB_OSC_EN_RVT_POS))
+#define GLB_OSC_EN_LVT GLB_OSC_EN_LVT
+#define GLB_OSC_EN_LVT_POS (2U)
+#define GLB_OSC_EN_LVT_LEN (1U)
+#define GLB_OSC_EN_LVT_MSK (((1U << GLB_OSC_EN_LVT_LEN) - 1) << GLB_OSC_EN_LVT_POS)
+#define GLB_OSC_EN_LVT_UMSK (~(((1U << GLB_OSC_EN_LVT_LEN) - 1) << GLB_OSC_EN_LVT_POS))
+#define GLB_OSC_SEL GLB_OSC_SEL
+#define GLB_OSC_SEL_POS (3U)
+#define GLB_OSC_SEL_LEN (1U)
+#define GLB_OSC_SEL_MSK (((1U << GLB_OSC_SEL_LEN) - 1) << GLB_OSC_SEL_POS)
+#define GLB_OSC_SEL_UMSK (~(((1U << GLB_OSC_SEL_LEN) - 1) << GLB_OSC_SEL_POS))
+#define GLB_RSTN_RINGCOUNT GLB_RSTN_RINGCOUNT
+#define GLB_RSTN_RINGCOUNT_POS (4U)
+#define GLB_RSTN_RINGCOUNT_LEN (1U)
+#define GLB_RSTN_RINGCOUNT_MSK (((1U << GLB_RSTN_RINGCOUNT_LEN) - 1) << GLB_RSTN_RINGCOUNT_POS)
+#define GLB_RSTN_RINGCOUNT_UMSK (~(((1U << GLB_RSTN_RINGCOUNT_LEN) - 1) << GLB_RSTN_RINGCOUNT_POS))
+#define GLB_RSTN_REFCOUNT GLB_RSTN_REFCOUNT
+#define GLB_RSTN_REFCOUNT_POS (5U)
+#define GLB_RSTN_REFCOUNT_LEN (1U)
+#define GLB_RSTN_REFCOUNT_MSK (((1U << GLB_RSTN_REFCOUNT_LEN) - 1) << GLB_RSTN_REFCOUNT_POS)
+#define GLB_RSTN_REFCOUNT_UMSK (~(((1U << GLB_RSTN_REFCOUNT_LEN) - 1) << GLB_RSTN_REFCOUNT_POS))
+#define GLB_REFCOUNT_DIV_ONEHOT GLB_REFCOUNT_DIV_ONEHOT
+#define GLB_REFCOUNT_DIV_ONEHOT_POS (8U)
+#define GLB_REFCOUNT_DIV_ONEHOT_LEN (4U)
+#define GLB_REFCOUNT_DIV_ONEHOT_MSK (((1U << GLB_REFCOUNT_DIV_ONEHOT_LEN) - 1) << GLB_REFCOUNT_DIV_ONEHOT_POS)
+#define GLB_REFCOUNT_DIV_ONEHOT_UMSK (~(((1U << GLB_REFCOUNT_DIV_ONEHOT_LEN) - 1) << GLB_REFCOUNT_DIV_ONEHOT_POS))
+#define GLB_RING_FREQ GLB_RING_FREQ
+#define GLB_RING_FREQ_POS (12U)
+#define GLB_RING_FREQ_LEN (16U)
+#define GLB_RING_FREQ_MSK (((1U << GLB_RING_FREQ_LEN) - 1) << GLB_RING_FREQ_POS)
+#define GLB_RING_FREQ_UMSK (~(((1U << GLB_RING_FREQ_LEN) - 1) << GLB_RING_FREQ_POS))
+#define GLB_RING_FREQ_RDY GLB_RING_FREQ_RDY
+#define GLB_RING_FREQ_RDY_POS (28U)
+#define GLB_RING_FREQ_RDY_LEN (1U)
+#define GLB_RING_FREQ_RDY_MSK (((1U << GLB_RING_FREQ_RDY_LEN) - 1) << GLB_RING_FREQ_RDY_POS)
+#define GLB_RING_FREQ_RDY_UMSK (~(((1U << GLB_RING_FREQ_RDY_LEN) - 1) << GLB_RING_FREQ_RDY_POS))
+
+/* 0x700 : dll_cfg0 */
+#define GLB_DLL_CFG0_OFFSET (0x700)
+
+/* 0x790 : mipi_pll_cfg0 */
+#define GLB_MIPI_PLL_CFG0_OFFSET (0x790)
+#define GLB_MIPIPLL_SDM_RSTB GLB_MIPIPLL_SDM_RSTB
+#define GLB_MIPIPLL_SDM_RSTB_POS (0U)
+#define GLB_MIPIPLL_SDM_RSTB_LEN (1U)
+#define GLB_MIPIPLL_SDM_RSTB_MSK (((1U << GLB_MIPIPLL_SDM_RSTB_LEN) - 1) << GLB_MIPIPLL_SDM_RSTB_POS)
+#define GLB_MIPIPLL_SDM_RSTB_UMSK (~(((1U << GLB_MIPIPLL_SDM_RSTB_LEN) - 1) << GLB_MIPIPLL_SDM_RSTB_POS))
+#define GLB_MIPIPLL_FBDV_RSTB GLB_MIPIPLL_FBDV_RSTB
+#define GLB_MIPIPLL_FBDV_RSTB_POS (2U)
+#define GLB_MIPIPLL_FBDV_RSTB_LEN (1U)
+#define GLB_MIPIPLL_FBDV_RSTB_MSK (((1U << GLB_MIPIPLL_FBDV_RSTB_LEN) - 1) << GLB_MIPIPLL_FBDV_RSTB_POS)
+#define GLB_MIPIPLL_FBDV_RSTB_UMSK (~(((1U << GLB_MIPIPLL_FBDV_RSTB_LEN) - 1) << GLB_MIPIPLL_FBDV_RSTB_POS))
+#define GLB_PU_MIPIPLL_FBDV GLB_PU_MIPIPLL_FBDV
+#define GLB_PU_MIPIPLL_FBDV_POS (5U)
+#define GLB_PU_MIPIPLL_FBDV_LEN (1U)
+#define GLB_PU_MIPIPLL_FBDV_MSK (((1U << GLB_PU_MIPIPLL_FBDV_LEN) - 1) << GLB_PU_MIPIPLL_FBDV_POS)
+#define GLB_PU_MIPIPLL_FBDV_UMSK (~(((1U << GLB_PU_MIPIPLL_FBDV_LEN) - 1) << GLB_PU_MIPIPLL_FBDV_POS))
+#define GLB_PU_MIPIPLL_CP GLB_PU_MIPIPLL_CP
+#define GLB_PU_MIPIPLL_CP_POS (8U)
+#define GLB_PU_MIPIPLL_CP_LEN (1U)
+#define GLB_PU_MIPIPLL_CP_MSK (((1U << GLB_PU_MIPIPLL_CP_LEN) - 1) << GLB_PU_MIPIPLL_CP_POS)
+#define GLB_PU_MIPIPLL_CP_UMSK (~(((1U << GLB_PU_MIPIPLL_CP_LEN) - 1) << GLB_PU_MIPIPLL_CP_POS))
+#define GLB_PU_MIPIPLL_SFREG GLB_PU_MIPIPLL_SFREG
+#define GLB_PU_MIPIPLL_SFREG_POS (9U)
+#define GLB_PU_MIPIPLL_SFREG_LEN (1U)
+#define GLB_PU_MIPIPLL_SFREG_MSK (((1U << GLB_PU_MIPIPLL_SFREG_LEN) - 1) << GLB_PU_MIPIPLL_SFREG_POS)
+#define GLB_PU_MIPIPLL_SFREG_UMSK (~(((1U << GLB_PU_MIPIPLL_SFREG_LEN) - 1) << GLB_PU_MIPIPLL_SFREG_POS))
+#define GLB_PU_MIPIPLL GLB_PU_MIPIPLL
+#define GLB_PU_MIPIPLL_POS (10U)
+#define GLB_PU_MIPIPLL_LEN (1U)
+#define GLB_PU_MIPIPLL_MSK (((1U << GLB_PU_MIPIPLL_LEN) - 1) << GLB_PU_MIPIPLL_POS)
+#define GLB_PU_MIPIPLL_UMSK (~(((1U << GLB_PU_MIPIPLL_LEN) - 1) << GLB_PU_MIPIPLL_POS))
+
+/* 0x794 : mipi_pll_cfg1 */
+#define GLB_MIPI_PLL_CFG1_OFFSET (0x794)
+#define GLB_MIPIPLL_EVEN_DIV_RATIO GLB_MIPIPLL_EVEN_DIV_RATIO
+#define GLB_MIPIPLL_EVEN_DIV_RATIO_POS (0U)
+#define GLB_MIPIPLL_EVEN_DIV_RATIO_LEN (7U)
+#define GLB_MIPIPLL_EVEN_DIV_RATIO_MSK (((1U << GLB_MIPIPLL_EVEN_DIV_RATIO_LEN) - 1) << GLB_MIPIPLL_EVEN_DIV_RATIO_POS)
+#define GLB_MIPIPLL_EVEN_DIV_RATIO_UMSK (~(((1U << GLB_MIPIPLL_EVEN_DIV_RATIO_LEN) - 1) << GLB_MIPIPLL_EVEN_DIV_RATIO_POS))
+#define GLB_MIPIPLL_EVEN_DIV_EN GLB_MIPIPLL_EVEN_DIV_EN
+#define GLB_MIPIPLL_EVEN_DIV_EN_POS (7U)
+#define GLB_MIPIPLL_EVEN_DIV_EN_LEN (1U)
+#define GLB_MIPIPLL_EVEN_DIV_EN_MSK (((1U << GLB_MIPIPLL_EVEN_DIV_EN_LEN) - 1) << GLB_MIPIPLL_EVEN_DIV_EN_POS)
+#define GLB_MIPIPLL_EVEN_DIV_EN_UMSK (~(((1U << GLB_MIPIPLL_EVEN_DIV_EN_LEN) - 1) << GLB_MIPIPLL_EVEN_DIV_EN_POS))
+#define GLB_MIPIPLL_REFDIV_RATIO GLB_MIPIPLL_REFDIV_RATIO
+#define GLB_MIPIPLL_REFDIV_RATIO_POS (8U)
+#define GLB_MIPIPLL_REFDIV_RATIO_LEN (4U)
+#define GLB_MIPIPLL_REFDIV_RATIO_MSK (((1U << GLB_MIPIPLL_REFDIV_RATIO_LEN) - 1) << GLB_MIPIPLL_REFDIV_RATIO_POS)
+#define GLB_MIPIPLL_REFDIV_RATIO_UMSK (~(((1U << GLB_MIPIPLL_REFDIV_RATIO_LEN) - 1) << GLB_MIPIPLL_REFDIV_RATIO_POS))
+#define GLB_MIPIPLL_REFCLK_SEL GLB_MIPIPLL_REFCLK_SEL
+#define GLB_MIPIPLL_REFCLK_SEL_POS (16U)
+#define GLB_MIPIPLL_REFCLK_SEL_LEN (2U)
+#define GLB_MIPIPLL_REFCLK_SEL_MSK (((1U << GLB_MIPIPLL_REFCLK_SEL_LEN) - 1) << GLB_MIPIPLL_REFCLK_SEL_POS)
+#define GLB_MIPIPLL_REFCLK_SEL_UMSK (~(((1U << GLB_MIPIPLL_REFCLK_SEL_LEN) - 1) << GLB_MIPIPLL_REFCLK_SEL_POS))
+#define GLB_MIPIPLL_VG11_SEL GLB_MIPIPLL_VG11_SEL
+#define GLB_MIPIPLL_VG11_SEL_POS (20U)
+#define GLB_MIPIPLL_VG11_SEL_LEN (2U)
+#define GLB_MIPIPLL_VG11_SEL_MSK (((1U << GLB_MIPIPLL_VG11_SEL_LEN) - 1) << GLB_MIPIPLL_VG11_SEL_POS)
+#define GLB_MIPIPLL_VG11_SEL_UMSK (~(((1U << GLB_MIPIPLL_VG11_SEL_LEN) - 1) << GLB_MIPIPLL_VG11_SEL_POS))
+#define GLB_MIPIPLL_VG13_SEL GLB_MIPIPLL_VG13_SEL
+#define GLB_MIPIPLL_VG13_SEL_POS (24U)
+#define GLB_MIPIPLL_VG13_SEL_LEN (2U)
+#define GLB_MIPIPLL_VG13_SEL_MSK (((1U << GLB_MIPIPLL_VG13_SEL_LEN) - 1) << GLB_MIPIPLL_VG13_SEL_POS)
+#define GLB_MIPIPLL_VG13_SEL_UMSK (~(((1U << GLB_MIPIPLL_VG13_SEL_LEN) - 1) << GLB_MIPIPLL_VG13_SEL_POS))
+
+/* 0x798 : mipi_pll_cfg2 */
+#define GLB_MIPI_PLL_CFG2_OFFSET (0x798)
+#define GLB_MIPIPLL_SEL_CP_BIAS GLB_MIPIPLL_SEL_CP_BIAS
+#define GLB_MIPIPLL_SEL_CP_BIAS_POS (0U)
+#define GLB_MIPIPLL_SEL_CP_BIAS_LEN (1U)
+#define GLB_MIPIPLL_SEL_CP_BIAS_MSK (((1U << GLB_MIPIPLL_SEL_CP_BIAS_LEN) - 1) << GLB_MIPIPLL_SEL_CP_BIAS_POS)
+#define GLB_MIPIPLL_SEL_CP_BIAS_UMSK (~(((1U << GLB_MIPIPLL_SEL_CP_BIAS_LEN) - 1) << GLB_MIPIPLL_SEL_CP_BIAS_POS))
+#define GLB_MIPIPLL_ICP_5U GLB_MIPIPLL_ICP_5U
+#define GLB_MIPIPLL_ICP_5U_POS (4U)
+#define GLB_MIPIPLL_ICP_5U_LEN (2U)
+#define GLB_MIPIPLL_ICP_5U_MSK (((1U << GLB_MIPIPLL_ICP_5U_LEN) - 1) << GLB_MIPIPLL_ICP_5U_POS)
+#define GLB_MIPIPLL_ICP_5U_UMSK (~(((1U << GLB_MIPIPLL_ICP_5U_LEN) - 1) << GLB_MIPIPLL_ICP_5U_POS))
+#define GLB_MIPIPLL_ICP_1U GLB_MIPIPLL_ICP_1U
+#define GLB_MIPIPLL_ICP_1U_POS (6U)
+#define GLB_MIPIPLL_ICP_1U_LEN (2U)
+#define GLB_MIPIPLL_ICP_1U_MSK (((1U << GLB_MIPIPLL_ICP_1U_LEN) - 1) << GLB_MIPIPLL_ICP_1U_POS)
+#define GLB_MIPIPLL_ICP_1U_UMSK (~(((1U << GLB_MIPIPLL_ICP_1U_LEN) - 1) << GLB_MIPIPLL_ICP_1U_POS))
+#define GLB_MIPIPLL_INT_FRAC_SW GLB_MIPIPLL_INT_FRAC_SW
+#define GLB_MIPIPLL_INT_FRAC_SW_POS (8U)
+#define GLB_MIPIPLL_INT_FRAC_SW_LEN (1U)
+#define GLB_MIPIPLL_INT_FRAC_SW_MSK (((1U << GLB_MIPIPLL_INT_FRAC_SW_LEN) - 1) << GLB_MIPIPLL_INT_FRAC_SW_POS)
+#define GLB_MIPIPLL_INT_FRAC_SW_UMSK (~(((1U << GLB_MIPIPLL_INT_FRAC_SW_LEN) - 1) << GLB_MIPIPLL_INT_FRAC_SW_POS))
+#define GLB_MIPIPLL_CP_STARTUP_EN GLB_MIPIPLL_CP_STARTUP_EN
+#define GLB_MIPIPLL_CP_STARTUP_EN_POS (9U)
+#define GLB_MIPIPLL_CP_STARTUP_EN_LEN (1U)
+#define GLB_MIPIPLL_CP_STARTUP_EN_MSK (((1U << GLB_MIPIPLL_CP_STARTUP_EN_LEN) - 1) << GLB_MIPIPLL_CP_STARTUP_EN_POS)
+#define GLB_MIPIPLL_CP_STARTUP_EN_UMSK (~(((1U << GLB_MIPIPLL_CP_STARTUP_EN_LEN) - 1) << GLB_MIPIPLL_CP_STARTUP_EN_POS))
+#define GLB_MIPIPLL_CP_OPAMP_EN GLB_MIPIPLL_CP_OPAMP_EN
+#define GLB_MIPIPLL_CP_OPAMP_EN_POS (10U)
+#define GLB_MIPIPLL_CP_OPAMP_EN_LEN (1U)
+#define GLB_MIPIPLL_CP_OPAMP_EN_MSK (((1U << GLB_MIPIPLL_CP_OPAMP_EN_LEN) - 1) << GLB_MIPIPLL_CP_OPAMP_EN_POS)
+#define GLB_MIPIPLL_CP_OPAMP_EN_UMSK (~(((1U << GLB_MIPIPLL_CP_OPAMP_EN_LEN) - 1) << GLB_MIPIPLL_CP_OPAMP_EN_POS))
+#define GLB_MIPIPLL_CP_OTA_EN GLB_MIPIPLL_CP_OTA_EN
+#define GLB_MIPIPLL_CP_OTA_EN_POS (11U)
+#define GLB_MIPIPLL_CP_OTA_EN_LEN (1U)
+#define GLB_MIPIPLL_CP_OTA_EN_MSK (((1U << GLB_MIPIPLL_CP_OTA_EN_LEN) - 1) << GLB_MIPIPLL_CP_OTA_EN_POS)
+#define GLB_MIPIPLL_CP_OTA_EN_UMSK (~(((1U << GLB_MIPIPLL_CP_OTA_EN_LEN) - 1) << GLB_MIPIPLL_CP_OTA_EN_POS))
+#define GLB_MIPIPLL_PFD_EN GLB_MIPIPLL_PFD_EN
+#define GLB_MIPIPLL_PFD_EN_POS (12U)
+#define GLB_MIPIPLL_PFD_EN_LEN (1U)
+#define GLB_MIPIPLL_PFD_EN_MSK (((1U << GLB_MIPIPLL_PFD_EN_LEN) - 1) << GLB_MIPIPLL_PFD_EN_POS)
+#define GLB_MIPIPLL_PFD_EN_UMSK (~(((1U << GLB_MIPIPLL_PFD_EN_LEN) - 1) << GLB_MIPIPLL_PFD_EN_POS))
+
+/* 0x79C : mipi_pll_cfg3 */
+#define GLB_MIPI_PLL_CFG3_OFFSET (0x79C)
+#define GLB_MIPIPLL_C4_EN GLB_MIPIPLL_C4_EN
+#define GLB_MIPIPLL_C4_EN_POS (0U)
+#define GLB_MIPIPLL_C4_EN_LEN (1U)
+#define GLB_MIPIPLL_C4_EN_MSK (((1U << GLB_MIPIPLL_C4_EN_LEN) - 1) << GLB_MIPIPLL_C4_EN_POS)
+#define GLB_MIPIPLL_C4_EN_UMSK (~(((1U << GLB_MIPIPLL_C4_EN_LEN) - 1) << GLB_MIPIPLL_C4_EN_POS))
+#define GLB_MIPIPLL_R4 GLB_MIPIPLL_R4
+#define GLB_MIPIPLL_R4_POS (4U)
+#define GLB_MIPIPLL_R4_LEN (2U)
+#define GLB_MIPIPLL_R4_MSK (((1U << GLB_MIPIPLL_R4_LEN) - 1) << GLB_MIPIPLL_R4_POS)
+#define GLB_MIPIPLL_R4_UMSK (~(((1U << GLB_MIPIPLL_R4_LEN) - 1) << GLB_MIPIPLL_R4_POS))
+#define GLB_MIPIPLL_R4_SHORT GLB_MIPIPLL_R4_SHORT
+#define GLB_MIPIPLL_R4_SHORT_POS (8U)
+#define GLB_MIPIPLL_R4_SHORT_LEN (1U)
+#define GLB_MIPIPLL_R4_SHORT_MSK (((1U << GLB_MIPIPLL_R4_SHORT_LEN) - 1) << GLB_MIPIPLL_R4_SHORT_POS)
+#define GLB_MIPIPLL_R4_SHORT_UMSK (~(((1U << GLB_MIPIPLL_R4_SHORT_LEN) - 1) << GLB_MIPIPLL_R4_SHORT_POS))
+#define GLB_MIPIPLL_C3 GLB_MIPIPLL_C3
+#define GLB_MIPIPLL_C3_POS (12U)
+#define GLB_MIPIPLL_C3_LEN (2U)
+#define GLB_MIPIPLL_C3_MSK (((1U << GLB_MIPIPLL_C3_LEN) - 1) << GLB_MIPIPLL_C3_POS)
+#define GLB_MIPIPLL_C3_UMSK (~(((1U << GLB_MIPIPLL_C3_LEN) - 1) << GLB_MIPIPLL_C3_POS))
+#define GLB_MIPIPLL_CZ GLB_MIPIPLL_CZ
+#define GLB_MIPIPLL_CZ_POS (14U)
+#define GLB_MIPIPLL_CZ_LEN (2U)
+#define GLB_MIPIPLL_CZ_MSK (((1U << GLB_MIPIPLL_CZ_LEN) - 1) << GLB_MIPIPLL_CZ_POS)
+#define GLB_MIPIPLL_CZ_UMSK (~(((1U << GLB_MIPIPLL_CZ_LEN) - 1) << GLB_MIPIPLL_CZ_POS))
+#define GLB_MIPIPLL_RZ GLB_MIPIPLL_RZ
+#define GLB_MIPIPLL_RZ_POS (16U)
+#define GLB_MIPIPLL_RZ_LEN (3U)
+#define GLB_MIPIPLL_RZ_MSK (((1U << GLB_MIPIPLL_RZ_LEN) - 1) << GLB_MIPIPLL_RZ_POS)
+#define GLB_MIPIPLL_RZ_UMSK (~(((1U << GLB_MIPIPLL_RZ_LEN) - 1) << GLB_MIPIPLL_RZ_POS))
+#define GLB_MIPIPLL_LF_TEST_EN GLB_MIPIPLL_LF_TEST_EN
+#define GLB_MIPIPLL_LF_TEST_EN_POS (19U)
+#define GLB_MIPIPLL_LF_TEST_EN_LEN (1U)
+#define GLB_MIPIPLL_LF_TEST_EN_MSK (((1U << GLB_MIPIPLL_LF_TEST_EN_LEN) - 1) << GLB_MIPIPLL_LF_TEST_EN_POS)
+#define GLB_MIPIPLL_LF_TEST_EN_UMSK (~(((1U << GLB_MIPIPLL_LF_TEST_EN_LEN) - 1) << GLB_MIPIPLL_LF_TEST_EN_POS))
+#define GLB_MIPIPLL_FAST_LOCK_EN GLB_MIPIPLL_FAST_LOCK_EN
+#define GLB_MIPIPLL_FAST_LOCK_EN_POS (20U)
+#define GLB_MIPIPLL_FAST_LOCK_EN_LEN (1U)
+#define GLB_MIPIPLL_FAST_LOCK_EN_MSK (((1U << GLB_MIPIPLL_FAST_LOCK_EN_LEN) - 1) << GLB_MIPIPLL_FAST_LOCK_EN_POS)
+#define GLB_MIPIPLL_FAST_LOCK_EN_UMSK (~(((1U << GLB_MIPIPLL_FAST_LOCK_EN_LEN) - 1) << GLB_MIPIPLL_FAST_LOCK_EN_POS))
+
+/* 0x7A0 : mipi_pll_cfg4 */
+#define GLB_MIPI_PLL_CFG4_OFFSET (0x7A0)
+#define GLB_MIPIPLL_SEL_SAMPLE_CLK GLB_MIPIPLL_SEL_SAMPLE_CLK
+#define GLB_MIPIPLL_SEL_SAMPLE_CLK_POS (0U)
+#define GLB_MIPIPLL_SEL_SAMPLE_CLK_LEN (2U)
+#define GLB_MIPIPLL_SEL_SAMPLE_CLK_MSK (((1U << GLB_MIPIPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_MIPIPLL_SEL_SAMPLE_CLK_POS)
+#define GLB_MIPIPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << GLB_MIPIPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_MIPIPLL_SEL_SAMPLE_CLK_POS))
+#define GLB_MIPIPLL_SEL_FB_CLK GLB_MIPIPLL_SEL_FB_CLK
+#define GLB_MIPIPLL_SEL_FB_CLK_POS (4U)
+#define GLB_MIPIPLL_SEL_FB_CLK_LEN (2U)
+#define GLB_MIPIPLL_SEL_FB_CLK_MSK (((1U << GLB_MIPIPLL_SEL_FB_CLK_LEN) - 1) << GLB_MIPIPLL_SEL_FB_CLK_POS)
+#define GLB_MIPIPLL_SEL_FB_CLK_UMSK (~(((1U << GLB_MIPIPLL_SEL_FB_CLK_LEN) - 1) << GLB_MIPIPLL_SEL_FB_CLK_POS))
+#define GLB_MIPIPLL_LOCK_DET_EN GLB_MIPIPLL_LOCK_DET_EN
+#define GLB_MIPIPLL_LOCK_DET_EN_POS (8U)
+#define GLB_MIPIPLL_LOCK_DET_EN_LEN (1U)
+#define GLB_MIPIPLL_LOCK_DET_EN_MSK (((1U << GLB_MIPIPLL_LOCK_DET_EN_LEN) - 1) << GLB_MIPIPLL_LOCK_DET_EN_POS)
+#define GLB_MIPIPLL_LOCK_DET_EN_UMSK (~(((1U << GLB_MIPIPLL_LOCK_DET_EN_LEN) - 1) << GLB_MIPIPLL_LOCK_DET_EN_POS))
+#define GLB_MIPIPLL_LOCK_CLK_SEL GLB_MIPIPLL_LOCK_CLK_SEL
+#define GLB_MIPIPLL_LOCK_CLK_SEL_POS (9U)
+#define GLB_MIPIPLL_LOCK_CLK_SEL_LEN (2U)
+#define GLB_MIPIPLL_LOCK_CLK_SEL_MSK (((1U << GLB_MIPIPLL_LOCK_CLK_SEL_LEN) - 1) << GLB_MIPIPLL_LOCK_CLK_SEL_POS)
+#define GLB_MIPIPLL_LOCK_CLK_SEL_UMSK (~(((1U << GLB_MIPIPLL_LOCK_CLK_SEL_LEN) - 1) << GLB_MIPIPLL_LOCK_CLK_SEL_POS))
+#define GLB_MIPIPLL_LOCK_CLK_INV_EN GLB_MIPIPLL_LOCK_CLK_INV_EN
+#define GLB_MIPIPLL_LOCK_CLK_INV_EN_POS (12U)
+#define GLB_MIPIPLL_LOCK_CLK_INV_EN_LEN (1U)
+#define GLB_MIPIPLL_LOCK_CLK_INV_EN_MSK (((1U << GLB_MIPIPLL_LOCK_CLK_INV_EN_LEN) - 1) << GLB_MIPIPLL_LOCK_CLK_INV_EN_POS)
+#define GLB_MIPIPLL_LOCK_CLK_INV_EN_UMSK (~(((1U << GLB_MIPIPLL_LOCK_CLK_INV_EN_LEN) - 1) << GLB_MIPIPLL_LOCK_CLK_INV_EN_POS))
+#define GLB_MIPIPLL_LOCK_WIN_SEL GLB_MIPIPLL_LOCK_WIN_SEL
+#define GLB_MIPIPLL_LOCK_WIN_SEL_POS (15U)
+#define GLB_MIPIPLL_LOCK_WIN_SEL_LEN (2U)
+#define GLB_MIPIPLL_LOCK_WIN_SEL_MSK (((1U << GLB_MIPIPLL_LOCK_WIN_SEL_LEN) - 1) << GLB_MIPIPLL_LOCK_WIN_SEL_POS)
+#define GLB_MIPIPLL_LOCK_WIN_SEL_UMSK (~(((1U << GLB_MIPIPLL_LOCK_WIN_SEL_LEN) - 1) << GLB_MIPIPLL_LOCK_WIN_SEL_POS))
+
+/* 0x7A4 : mipi_pll_cfg5 */
+#define GLB_MIPI_PLL_CFG5_OFFSET (0x7A4)
+#define GLB_MIPIPLL_VCO_SPEED GLB_MIPIPLL_VCO_SPEED
+#define GLB_MIPIPLL_VCO_SPEED_POS (0U)
+#define GLB_MIPIPLL_VCO_SPEED_LEN (3U)
+#define GLB_MIPIPLL_VCO_SPEED_MSK (((1U << GLB_MIPIPLL_VCO_SPEED_LEN) - 1) << GLB_MIPIPLL_VCO_SPEED_POS)
+#define GLB_MIPIPLL_VCO_SPEED_UMSK (~(((1U << GLB_MIPIPLL_VCO_SPEED_LEN) - 1) << GLB_MIPIPLL_VCO_SPEED_POS))
+#define GLB_MIPIPLL_VCO_VDD_CTRL GLB_MIPIPLL_VCO_VDD_CTRL
+#define GLB_MIPIPLL_VCO_VDD_CTRL_POS (3U)
+#define GLB_MIPIPLL_VCO_VDD_CTRL_LEN (2U)
+#define GLB_MIPIPLL_VCO_VDD_CTRL_MSK (((1U << GLB_MIPIPLL_VCO_VDD_CTRL_LEN) - 1) << GLB_MIPIPLL_VCO_VDD_CTRL_POS)
+#define GLB_MIPIPLL_VCO_VDD_CTRL_UMSK (~(((1U << GLB_MIPIPLL_VCO_VDD_CTRL_LEN) - 1) << GLB_MIPIPLL_VCO_VDD_CTRL_POS))
+#define GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA
+#define GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_POS (5U)
+#define GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_LEN (1U)
+#define GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_MSK (((1U << GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_LEN) - 1) << GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_POS)
+#define GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_UMSK (~(((1U << GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_LEN) - 1) << GLB_MIPIPLL_VCO_VDD_CTRL_EXTRA_POS))
+#define GLB_MIPIPLL_VCO_POSTDIV_SEL GLB_MIPIPLL_VCO_POSTDIV_SEL
+#define GLB_MIPIPLL_VCO_POSTDIV_SEL_POS (7U)
+#define GLB_MIPIPLL_VCO_POSTDIV_SEL_LEN (3U)
+#define GLB_MIPIPLL_VCO_POSTDIV_SEL_MSK (((1U << GLB_MIPIPLL_VCO_POSTDIV_SEL_LEN) - 1) << GLB_MIPIPLL_VCO_POSTDIV_SEL_POS)
+#define GLB_MIPIPLL_VCO_POSTDIV_SEL_UMSK (~(((1U << GLB_MIPIPLL_VCO_POSTDIV_SEL_LEN) - 1) << GLB_MIPIPLL_VCO_POSTDIV_SEL_POS))
+#define GLB_MIPIPLL_VCO_POSTDIV_CLK_EN GLB_MIPIPLL_VCO_POSTDIV_CLK_EN
+#define GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_POS (10U)
+#define GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_LEN (1U)
+#define GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_MSK (((1U << GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_LEN) - 1) << GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_POS)
+#define GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_UMSK (~(((1U << GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_LEN) - 1) << GLB_MIPIPLL_VCO_POSTDIV_CLK_EN_POS))
+
+/* 0x7A8 : mipi_pll_cfg6 */
+#define GLB_MIPI_PLL_CFG6_OFFSET (0x7A8)
+#define GLB_MIPIPLL_SDMIN GLB_MIPIPLL_SDMIN
+#define GLB_MIPIPLL_SDMIN_POS (0U)
+#define GLB_MIPIPLL_SDMIN_LEN (19U)
+#define GLB_MIPIPLL_SDMIN_MSK (((1U << GLB_MIPIPLL_SDMIN_LEN) - 1) << GLB_MIPIPLL_SDMIN_POS)
+#define GLB_MIPIPLL_SDMIN_UMSK (~(((1U << GLB_MIPIPLL_SDMIN_LEN) - 1) << GLB_MIPIPLL_SDMIN_POS))
+#define GLB_MIPIPLL_SDM_BYPASS GLB_MIPIPLL_SDM_BYPASS
+#define GLB_MIPIPLL_SDM_BYPASS_POS (24U)
+#define GLB_MIPIPLL_SDM_BYPASS_LEN (1U)
+#define GLB_MIPIPLL_SDM_BYPASS_MSK (((1U << GLB_MIPIPLL_SDM_BYPASS_LEN) - 1) << GLB_MIPIPLL_SDM_BYPASS_POS)
+#define GLB_MIPIPLL_SDM_BYPASS_UMSK (~(((1U << GLB_MIPIPLL_SDM_BYPASS_LEN) - 1) << GLB_MIPIPLL_SDM_BYPASS_POS))
+
+/* 0x7AC : mipi_pll_cfg7 */
+#define GLB_MIPI_PLL_CFG7_OFFSET (0x7AC)
+#define GLB_MIPIPLL_SDM_ORDER_SEL GLB_MIPIPLL_SDM_ORDER_SEL
+#define GLB_MIPIPLL_SDM_ORDER_SEL_POS (0U)
+#define GLB_MIPIPLL_SDM_ORDER_SEL_LEN (1U)
+#define GLB_MIPIPLL_SDM_ORDER_SEL_MSK (((1U << GLB_MIPIPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_MIPIPLL_SDM_ORDER_SEL_POS)
+#define GLB_MIPIPLL_SDM_ORDER_SEL_UMSK (~(((1U << GLB_MIPIPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_MIPIPLL_SDM_ORDER_SEL_POS))
+#define GLB_MIPIPLL_SDM_DITH_SEL GLB_MIPIPLL_SDM_DITH_SEL
+#define GLB_MIPIPLL_SDM_DITH_SEL_POS (1U)
+#define GLB_MIPIPLL_SDM_DITH_SEL_LEN (2U)
+#define GLB_MIPIPLL_SDM_DITH_SEL_MSK (((1U << GLB_MIPIPLL_SDM_DITH_SEL_LEN) - 1) << GLB_MIPIPLL_SDM_DITH_SEL_POS)
+#define GLB_MIPIPLL_SDM_DITH_SEL_UMSK (~(((1U << GLB_MIPIPLL_SDM_DITH_SEL_LEN) - 1) << GLB_MIPIPLL_SDM_DITH_SEL_POS))
+
+/* 0x7B0 : mipi_pll_cfg8 */
+#define GLB_MIPI_PLL_CFG8_OFFSET (0x7B0)
+#define GLB_MIPIPLL_DC_TP_OUT_EN GLB_MIPIPLL_DC_TP_OUT_EN
+#define GLB_MIPIPLL_DC_TP_OUT_EN_POS (0U)
+#define GLB_MIPIPLL_DC_TP_OUT_EN_LEN (1U)
+#define GLB_MIPIPLL_DC_TP_OUT_EN_MSK (((1U << GLB_MIPIPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_MIPIPLL_DC_TP_OUT_EN_POS)
+#define GLB_MIPIPLL_DC_TP_OUT_EN_UMSK (~(((1U << GLB_MIPIPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_MIPIPLL_DC_TP_OUT_EN_POS))
+#define GLB_MIPIPLL_TEN GLB_MIPIPLL_TEN
+#define GLB_MIPIPLL_TEN_POS (1U)
+#define GLB_MIPIPLL_TEN_LEN (1U)
+#define GLB_MIPIPLL_TEN_MSK (((1U << GLB_MIPIPLL_TEN_LEN) - 1) << GLB_MIPIPLL_TEN_POS)
+#define GLB_MIPIPLL_TEN_UMSK (~(((1U << GLB_MIPIPLL_TEN_LEN) - 1) << GLB_MIPIPLL_TEN_POS))
+#define GLB_MIPIPLL_TEN_SFREG GLB_MIPIPLL_TEN_SFREG
+#define GLB_MIPIPLL_TEN_SFREG_POS (2U)
+#define GLB_MIPIPLL_TEN_SFREG_LEN (1U)
+#define GLB_MIPIPLL_TEN_SFREG_MSK (((1U << GLB_MIPIPLL_TEN_SFREG_LEN) - 1) << GLB_MIPIPLL_TEN_SFREG_POS)
+#define GLB_MIPIPLL_TEN_SFREG_UMSK (~(((1U << GLB_MIPIPLL_TEN_SFREG_LEN) - 1) << GLB_MIPIPLL_TEN_SFREG_POS))
+#define GLB_MIPIPLL_DTEN_CKIN GLB_MIPIPLL_DTEN_CKIN
+#define GLB_MIPIPLL_DTEN_CKIN_POS (4U)
+#define GLB_MIPIPLL_DTEN_CKIN_LEN (1U)
+#define GLB_MIPIPLL_DTEN_CKIN_MSK (((1U << GLB_MIPIPLL_DTEN_CKIN_LEN) - 1) << GLB_MIPIPLL_DTEN_CKIN_POS)
+#define GLB_MIPIPLL_DTEN_CKIN_UMSK (~(((1U << GLB_MIPIPLL_DTEN_CKIN_LEN) - 1) << GLB_MIPIPLL_DTEN_CKIN_POS))
+#define GLB_MIPIPLL_DTEN_FREF GLB_MIPIPLL_DTEN_FREF
+#define GLB_MIPIPLL_DTEN_FREF_POS (5U)
+#define GLB_MIPIPLL_DTEN_FREF_LEN (1U)
+#define GLB_MIPIPLL_DTEN_FREF_MSK (((1U << GLB_MIPIPLL_DTEN_FREF_LEN) - 1) << GLB_MIPIPLL_DTEN_FREF_POS)
+#define GLB_MIPIPLL_DTEN_FREF_UMSK (~(((1U << GLB_MIPIPLL_DTEN_FREF_LEN) - 1) << GLB_MIPIPLL_DTEN_FREF_POS))
+#define GLB_MIPIPLL_DTEN_FSDM GLB_MIPIPLL_DTEN_FSDM
+#define GLB_MIPIPLL_DTEN_FSDM_POS (6U)
+#define GLB_MIPIPLL_DTEN_FSDM_LEN (1U)
+#define GLB_MIPIPLL_DTEN_FSDM_MSK (((1U << GLB_MIPIPLL_DTEN_FSDM_LEN) - 1) << GLB_MIPIPLL_DTEN_FSDM_POS)
+#define GLB_MIPIPLL_DTEN_FSDM_UMSK (~(((1U << GLB_MIPIPLL_DTEN_FSDM_LEN) - 1) << GLB_MIPIPLL_DTEN_FSDM_POS))
+#define GLB_MIPIPLL_DTEN_PUPLL GLB_MIPIPLL_DTEN_PUPLL
+#define GLB_MIPIPLL_DTEN_PUPLL_POS (7U)
+#define GLB_MIPIPLL_DTEN_PUPLL_LEN (1U)
+#define GLB_MIPIPLL_DTEN_PUPLL_MSK (((1U << GLB_MIPIPLL_DTEN_PUPLL_LEN) - 1) << GLB_MIPIPLL_DTEN_PUPLL_POS)
+#define GLB_MIPIPLL_DTEN_PUPLL_UMSK (~(((1U << GLB_MIPIPLL_DTEN_PUPLL_LEN) - 1) << GLB_MIPIPLL_DTEN_PUPLL_POS))
+#define GLB_MIPIPLL_DTEN_PLL_LOCKED GLB_MIPIPLL_DTEN_PLL_LOCKED
+#define GLB_MIPIPLL_DTEN_PLL_LOCKED_POS (8U)
+#define GLB_MIPIPLL_DTEN_PLL_LOCKED_LEN (1U)
+#define GLB_MIPIPLL_DTEN_PLL_LOCKED_MSK (((1U << GLB_MIPIPLL_DTEN_PLL_LOCKED_LEN) - 1) << GLB_MIPIPLL_DTEN_PLL_LOCKED_POS)
+#define GLB_MIPIPLL_DTEN_PLL_LOCKED_UMSK (~(((1U << GLB_MIPIPLL_DTEN_PLL_LOCKED_LEN) - 1) << GLB_MIPIPLL_DTEN_PLL_LOCKED_POS))
+#define GLB_MIPIPLL_DTEST_PULL_DOWN GLB_MIPIPLL_DTEST_PULL_DOWN
+#define GLB_MIPIPLL_DTEST_PULL_DOWN_POS (10U)
+#define GLB_MIPIPLL_DTEST_PULL_DOWN_LEN (1U)
+#define GLB_MIPIPLL_DTEST_PULL_DOWN_MSK (((1U << GLB_MIPIPLL_DTEST_PULL_DOWN_LEN) - 1) << GLB_MIPIPLL_DTEST_PULL_DOWN_POS)
+#define GLB_MIPIPLL_DTEST_PULL_DOWN_UMSK (~(((1U << GLB_MIPIPLL_DTEST_PULL_DOWN_LEN) - 1) << GLB_MIPIPLL_DTEST_PULL_DOWN_POS))
+
+/* 0x7B4 : mipi_pll_cfg9 */
+#define GLB_MIPI_PLL_CFG9_OFFSET (0x7B4)
+#define GLB_MIPIPLL_SSC_EN GLB_MIPIPLL_SSC_EN
+#define GLB_MIPIPLL_SSC_EN_POS (0U)
+#define GLB_MIPIPLL_SSC_EN_LEN (1U)
+#define GLB_MIPIPLL_SSC_EN_MSK (((1U << GLB_MIPIPLL_SSC_EN_LEN) - 1) << GLB_MIPIPLL_SSC_EN_POS)
+#define GLB_MIPIPLL_SSC_EN_UMSK (~(((1U << GLB_MIPIPLL_SSC_EN_LEN) - 1) << GLB_MIPIPLL_SSC_EN_POS))
+#define GLB_MIPIPLL_SSC_CNT GLB_MIPIPLL_SSC_CNT
+#define GLB_MIPIPLL_SSC_CNT_POS (4U)
+#define GLB_MIPIPLL_SSC_CNT_LEN (8U)
+#define GLB_MIPIPLL_SSC_CNT_MSK (((1U << GLB_MIPIPLL_SSC_CNT_LEN) - 1) << GLB_MIPIPLL_SSC_CNT_POS)
+#define GLB_MIPIPLL_SSC_CNT_UMSK (~(((1U << GLB_MIPIPLL_SSC_CNT_LEN) - 1) << GLB_MIPIPLL_SSC_CNT_POS))
+#define GLB_MIPIPLL_SSC_GAIN GLB_MIPIPLL_SSC_GAIN
+#define GLB_MIPIPLL_SSC_GAIN_POS (12U)
+#define GLB_MIPIPLL_SSC_GAIN_LEN (3U)
+#define GLB_MIPIPLL_SSC_GAIN_MSK (((1U << GLB_MIPIPLL_SSC_GAIN_LEN) - 1) << GLB_MIPIPLL_SSC_GAIN_POS)
+#define GLB_MIPIPLL_SSC_GAIN_UMSK (~(((1U << GLB_MIPIPLL_SSC_GAIN_LEN) - 1) << GLB_MIPIPLL_SSC_GAIN_POS))
+#define GLB_MIPIPLL_SSC_START_GATE_EN GLB_MIPIPLL_SSC_START_GATE_EN
+#define GLB_MIPIPLL_SSC_START_GATE_EN_POS (16U)
+#define GLB_MIPIPLL_SSC_START_GATE_EN_LEN (1U)
+#define GLB_MIPIPLL_SSC_START_GATE_EN_MSK (((1U << GLB_MIPIPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_MIPIPLL_SSC_START_GATE_EN_POS)
+#define GLB_MIPIPLL_SSC_START_GATE_EN_UMSK (~(((1U << GLB_MIPIPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_MIPIPLL_SSC_START_GATE_EN_POS))
+
+/* 0x7D0 : uhs_pll_cfg0 */
+#define GLB_UHS_PLL_CFG0_OFFSET (0x7D0)
+#define GLB_UHSPLL_SDM_RSTB GLB_UHSPLL_SDM_RSTB
+#define GLB_UHSPLL_SDM_RSTB_POS (0U)
+#define GLB_UHSPLL_SDM_RSTB_LEN (1U)
+#define GLB_UHSPLL_SDM_RSTB_MSK (((1U << GLB_UHSPLL_SDM_RSTB_LEN) - 1) << GLB_UHSPLL_SDM_RSTB_POS)
+#define GLB_UHSPLL_SDM_RSTB_UMSK (~(((1U << GLB_UHSPLL_SDM_RSTB_LEN) - 1) << GLB_UHSPLL_SDM_RSTB_POS))
+#define GLB_UHSPLL_FBDV_RSTB GLB_UHSPLL_FBDV_RSTB
+#define GLB_UHSPLL_FBDV_RSTB_POS (2U)
+#define GLB_UHSPLL_FBDV_RSTB_LEN (1U)
+#define GLB_UHSPLL_FBDV_RSTB_MSK (((1U << GLB_UHSPLL_FBDV_RSTB_LEN) - 1) << GLB_UHSPLL_FBDV_RSTB_POS)
+#define GLB_UHSPLL_FBDV_RSTB_UMSK (~(((1U << GLB_UHSPLL_FBDV_RSTB_LEN) - 1) << GLB_UHSPLL_FBDV_RSTB_POS))
+#define GLB_PU_UHSPLL_FBDV GLB_PU_UHSPLL_FBDV
+#define GLB_PU_UHSPLL_FBDV_POS (5U)
+#define GLB_PU_UHSPLL_FBDV_LEN (1U)
+#define GLB_PU_UHSPLL_FBDV_MSK (((1U << GLB_PU_UHSPLL_FBDV_LEN) - 1) << GLB_PU_UHSPLL_FBDV_POS)
+#define GLB_PU_UHSPLL_FBDV_UMSK (~(((1U << GLB_PU_UHSPLL_FBDV_LEN) - 1) << GLB_PU_UHSPLL_FBDV_POS))
+#define GLB_PU_UHSPLL_CP GLB_PU_UHSPLL_CP
+#define GLB_PU_UHSPLL_CP_POS (8U)
+#define GLB_PU_UHSPLL_CP_LEN (1U)
+#define GLB_PU_UHSPLL_CP_MSK (((1U << GLB_PU_UHSPLL_CP_LEN) - 1) << GLB_PU_UHSPLL_CP_POS)
+#define GLB_PU_UHSPLL_CP_UMSK (~(((1U << GLB_PU_UHSPLL_CP_LEN) - 1) << GLB_PU_UHSPLL_CP_POS))
+#define GLB_PU_UHSPLL_SFREG GLB_PU_UHSPLL_SFREG
+#define GLB_PU_UHSPLL_SFREG_POS (9U)
+#define GLB_PU_UHSPLL_SFREG_LEN (1U)
+#define GLB_PU_UHSPLL_SFREG_MSK (((1U << GLB_PU_UHSPLL_SFREG_LEN) - 1) << GLB_PU_UHSPLL_SFREG_POS)
+#define GLB_PU_UHSPLL_SFREG_UMSK (~(((1U << GLB_PU_UHSPLL_SFREG_LEN) - 1) << GLB_PU_UHSPLL_SFREG_POS))
+#define GLB_PU_UHSPLL GLB_PU_UHSPLL
+#define GLB_PU_UHSPLL_POS (10U)
+#define GLB_PU_UHSPLL_LEN (1U)
+#define GLB_PU_UHSPLL_MSK (((1U << GLB_PU_UHSPLL_LEN) - 1) << GLB_PU_UHSPLL_POS)
+#define GLB_PU_UHSPLL_UMSK (~(((1U << GLB_PU_UHSPLL_LEN) - 1) << GLB_PU_UHSPLL_POS))
+
+/* 0x7D4 : uhs_pll_cfg1 */
+#define GLB_UHS_PLL_CFG1_OFFSET (0x7D4)
+#define GLB_UHSPLL_EVEN_DIV_RATIO GLB_UHSPLL_EVEN_DIV_RATIO
+#define GLB_UHSPLL_EVEN_DIV_RATIO_POS (0U)
+#define GLB_UHSPLL_EVEN_DIV_RATIO_LEN (7U)
+#define GLB_UHSPLL_EVEN_DIV_RATIO_MSK (((1U << GLB_UHSPLL_EVEN_DIV_RATIO_LEN) - 1) << GLB_UHSPLL_EVEN_DIV_RATIO_POS)
+#define GLB_UHSPLL_EVEN_DIV_RATIO_UMSK (~(((1U << GLB_UHSPLL_EVEN_DIV_RATIO_LEN) - 1) << GLB_UHSPLL_EVEN_DIV_RATIO_POS))
+#define GLB_UHSPLL_EVEN_DIV_EN GLB_UHSPLL_EVEN_DIV_EN
+#define GLB_UHSPLL_EVEN_DIV_EN_POS (7U)
+#define GLB_UHSPLL_EVEN_DIV_EN_LEN (1U)
+#define GLB_UHSPLL_EVEN_DIV_EN_MSK (((1U << GLB_UHSPLL_EVEN_DIV_EN_LEN) - 1) << GLB_UHSPLL_EVEN_DIV_EN_POS)
+#define GLB_UHSPLL_EVEN_DIV_EN_UMSK (~(((1U << GLB_UHSPLL_EVEN_DIV_EN_LEN) - 1) << GLB_UHSPLL_EVEN_DIV_EN_POS))
+#define GLB_UHSPLL_REFDIV_RATIO GLB_UHSPLL_REFDIV_RATIO
+#define GLB_UHSPLL_REFDIV_RATIO_POS (8U)
+#define GLB_UHSPLL_REFDIV_RATIO_LEN (4U)
+#define GLB_UHSPLL_REFDIV_RATIO_MSK (((1U << GLB_UHSPLL_REFDIV_RATIO_LEN) - 1) << GLB_UHSPLL_REFDIV_RATIO_POS)
+#define GLB_UHSPLL_REFDIV_RATIO_UMSK (~(((1U << GLB_UHSPLL_REFDIV_RATIO_LEN) - 1) << GLB_UHSPLL_REFDIV_RATIO_POS))
+#define GLB_UHSPLL_REFCLK_SEL GLB_UHSPLL_REFCLK_SEL
+#define GLB_UHSPLL_REFCLK_SEL_POS (16U)
+#define GLB_UHSPLL_REFCLK_SEL_LEN (2U)
+#define GLB_UHSPLL_REFCLK_SEL_MSK (((1U << GLB_UHSPLL_REFCLK_SEL_LEN) - 1) << GLB_UHSPLL_REFCLK_SEL_POS)
+#define GLB_UHSPLL_REFCLK_SEL_UMSK (~(((1U << GLB_UHSPLL_REFCLK_SEL_LEN) - 1) << GLB_UHSPLL_REFCLK_SEL_POS))
+#define GLB_UHSPLL_VG11_SEL GLB_UHSPLL_VG11_SEL
+#define GLB_UHSPLL_VG11_SEL_POS (20U)
+#define GLB_UHSPLL_VG11_SEL_LEN (2U)
+#define GLB_UHSPLL_VG11_SEL_MSK (((1U << GLB_UHSPLL_VG11_SEL_LEN) - 1) << GLB_UHSPLL_VG11_SEL_POS)
+#define GLB_UHSPLL_VG11_SEL_UMSK (~(((1U << GLB_UHSPLL_VG11_SEL_LEN) - 1) << GLB_UHSPLL_VG11_SEL_POS))
+#define GLB_UHSPLL_VG13_SEL GLB_UHSPLL_VG13_SEL
+#define GLB_UHSPLL_VG13_SEL_POS (24U)
+#define GLB_UHSPLL_VG13_SEL_LEN (2U)
+#define GLB_UHSPLL_VG13_SEL_MSK (((1U << GLB_UHSPLL_VG13_SEL_LEN) - 1) << GLB_UHSPLL_VG13_SEL_POS)
+#define GLB_UHSPLL_VG13_SEL_UMSK (~(((1U << GLB_UHSPLL_VG13_SEL_LEN) - 1) << GLB_UHSPLL_VG13_SEL_POS))
+
+/* 0x7D8 : uhs_pll_cfg2 */
+#define GLB_UHS_PLL_CFG2_OFFSET (0x7D8)
+#define GLB_UHSPLL_SEL_CP_BIAS GLB_UHSPLL_SEL_CP_BIAS
+#define GLB_UHSPLL_SEL_CP_BIAS_POS (0U)
+#define GLB_UHSPLL_SEL_CP_BIAS_LEN (1U)
+#define GLB_UHSPLL_SEL_CP_BIAS_MSK (((1U << GLB_UHSPLL_SEL_CP_BIAS_LEN) - 1) << GLB_UHSPLL_SEL_CP_BIAS_POS)
+#define GLB_UHSPLL_SEL_CP_BIAS_UMSK (~(((1U << GLB_UHSPLL_SEL_CP_BIAS_LEN) - 1) << GLB_UHSPLL_SEL_CP_BIAS_POS))
+#define GLB_UHSPLL_ICP_5U GLB_UHSPLL_ICP_5U
+#define GLB_UHSPLL_ICP_5U_POS (4U)
+#define GLB_UHSPLL_ICP_5U_LEN (2U)
+#define GLB_UHSPLL_ICP_5U_MSK (((1U << GLB_UHSPLL_ICP_5U_LEN) - 1) << GLB_UHSPLL_ICP_5U_POS)
+#define GLB_UHSPLL_ICP_5U_UMSK (~(((1U << GLB_UHSPLL_ICP_5U_LEN) - 1) << GLB_UHSPLL_ICP_5U_POS))
+#define GLB_UHSPLL_ICP_1U GLB_UHSPLL_ICP_1U
+#define GLB_UHSPLL_ICP_1U_POS (6U)
+#define GLB_UHSPLL_ICP_1U_LEN (2U)
+#define GLB_UHSPLL_ICP_1U_MSK (((1U << GLB_UHSPLL_ICP_1U_LEN) - 1) << GLB_UHSPLL_ICP_1U_POS)
+#define GLB_UHSPLL_ICP_1U_UMSK (~(((1U << GLB_UHSPLL_ICP_1U_LEN) - 1) << GLB_UHSPLL_ICP_1U_POS))
+#define GLB_UHSPLL_INT_FRAC_SW GLB_UHSPLL_INT_FRAC_SW
+#define GLB_UHSPLL_INT_FRAC_SW_POS (8U)
+#define GLB_UHSPLL_INT_FRAC_SW_LEN (1U)
+#define GLB_UHSPLL_INT_FRAC_SW_MSK (((1U << GLB_UHSPLL_INT_FRAC_SW_LEN) - 1) << GLB_UHSPLL_INT_FRAC_SW_POS)
+#define GLB_UHSPLL_INT_FRAC_SW_UMSK (~(((1U << GLB_UHSPLL_INT_FRAC_SW_LEN) - 1) << GLB_UHSPLL_INT_FRAC_SW_POS))
+#define GLB_UHSPLL_CP_STARTUP_EN GLB_UHSPLL_CP_STARTUP_EN
+#define GLB_UHSPLL_CP_STARTUP_EN_POS (9U)
+#define GLB_UHSPLL_CP_STARTUP_EN_LEN (1U)
+#define GLB_UHSPLL_CP_STARTUP_EN_MSK (((1U << GLB_UHSPLL_CP_STARTUP_EN_LEN) - 1) << GLB_UHSPLL_CP_STARTUP_EN_POS)
+#define GLB_UHSPLL_CP_STARTUP_EN_UMSK (~(((1U << GLB_UHSPLL_CP_STARTUP_EN_LEN) - 1) << GLB_UHSPLL_CP_STARTUP_EN_POS))
+#define GLB_UHSPLL_CP_OPAMP_EN GLB_UHSPLL_CP_OPAMP_EN
+#define GLB_UHSPLL_CP_OPAMP_EN_POS (10U)
+#define GLB_UHSPLL_CP_OPAMP_EN_LEN (1U)
+#define GLB_UHSPLL_CP_OPAMP_EN_MSK (((1U << GLB_UHSPLL_CP_OPAMP_EN_LEN) - 1) << GLB_UHSPLL_CP_OPAMP_EN_POS)
+#define GLB_UHSPLL_CP_OPAMP_EN_UMSK (~(((1U << GLB_UHSPLL_CP_OPAMP_EN_LEN) - 1) << GLB_UHSPLL_CP_OPAMP_EN_POS))
+#define GLB_UHSPLL_CP_OTA_EN GLB_UHSPLL_CP_OTA_EN
+#define GLB_UHSPLL_CP_OTA_EN_POS (11U)
+#define GLB_UHSPLL_CP_OTA_EN_LEN (1U)
+#define GLB_UHSPLL_CP_OTA_EN_MSK (((1U << GLB_UHSPLL_CP_OTA_EN_LEN) - 1) << GLB_UHSPLL_CP_OTA_EN_POS)
+#define GLB_UHSPLL_CP_OTA_EN_UMSK (~(((1U << GLB_UHSPLL_CP_OTA_EN_LEN) - 1) << GLB_UHSPLL_CP_OTA_EN_POS))
+#define GLB_UHSPLL_PFD_EN GLB_UHSPLL_PFD_EN
+#define GLB_UHSPLL_PFD_EN_POS (12U)
+#define GLB_UHSPLL_PFD_EN_LEN (1U)
+#define GLB_UHSPLL_PFD_EN_MSK (((1U << GLB_UHSPLL_PFD_EN_LEN) - 1) << GLB_UHSPLL_PFD_EN_POS)
+#define GLB_UHSPLL_PFD_EN_UMSK (~(((1U << GLB_UHSPLL_PFD_EN_LEN) - 1) << GLB_UHSPLL_PFD_EN_POS))
+
+/* 0x7DC : uhs_pll_cfg3 */
+#define GLB_UHS_PLL_CFG3_OFFSET (0x7DC)
+#define GLB_UHSPLL_C4_EN GLB_UHSPLL_C4_EN
+#define GLB_UHSPLL_C4_EN_POS (0U)
+#define GLB_UHSPLL_C4_EN_LEN (1U)
+#define GLB_UHSPLL_C4_EN_MSK (((1U << GLB_UHSPLL_C4_EN_LEN) - 1) << GLB_UHSPLL_C4_EN_POS)
+#define GLB_UHSPLL_C4_EN_UMSK (~(((1U << GLB_UHSPLL_C4_EN_LEN) - 1) << GLB_UHSPLL_C4_EN_POS))
+#define GLB_UHSPLL_R4 GLB_UHSPLL_R4
+#define GLB_UHSPLL_R4_POS (4U)
+#define GLB_UHSPLL_R4_LEN (2U)
+#define GLB_UHSPLL_R4_MSK (((1U << GLB_UHSPLL_R4_LEN) - 1) << GLB_UHSPLL_R4_POS)
+#define GLB_UHSPLL_R4_UMSK (~(((1U << GLB_UHSPLL_R4_LEN) - 1) << GLB_UHSPLL_R4_POS))
+#define GLB_UHSPLL_R4_SHORT GLB_UHSPLL_R4_SHORT
+#define GLB_UHSPLL_R4_SHORT_POS (8U)
+#define GLB_UHSPLL_R4_SHORT_LEN (1U)
+#define GLB_UHSPLL_R4_SHORT_MSK (((1U << GLB_UHSPLL_R4_SHORT_LEN) - 1) << GLB_UHSPLL_R4_SHORT_POS)
+#define GLB_UHSPLL_R4_SHORT_UMSK (~(((1U << GLB_UHSPLL_R4_SHORT_LEN) - 1) << GLB_UHSPLL_R4_SHORT_POS))
+#define GLB_UHSPLL_C3 GLB_UHSPLL_C3
+#define GLB_UHSPLL_C3_POS (12U)
+#define GLB_UHSPLL_C3_LEN (2U)
+#define GLB_UHSPLL_C3_MSK (((1U << GLB_UHSPLL_C3_LEN) - 1) << GLB_UHSPLL_C3_POS)
+#define GLB_UHSPLL_C3_UMSK (~(((1U << GLB_UHSPLL_C3_LEN) - 1) << GLB_UHSPLL_C3_POS))
+#define GLB_UHSPLL_CZ GLB_UHSPLL_CZ
+#define GLB_UHSPLL_CZ_POS (14U)
+#define GLB_UHSPLL_CZ_LEN (2U)
+#define GLB_UHSPLL_CZ_MSK (((1U << GLB_UHSPLL_CZ_LEN) - 1) << GLB_UHSPLL_CZ_POS)
+#define GLB_UHSPLL_CZ_UMSK (~(((1U << GLB_UHSPLL_CZ_LEN) - 1) << GLB_UHSPLL_CZ_POS))
+#define GLB_UHSPLL_RZ GLB_UHSPLL_RZ
+#define GLB_UHSPLL_RZ_POS (16U)
+#define GLB_UHSPLL_RZ_LEN (3U)
+#define GLB_UHSPLL_RZ_MSK (((1U << GLB_UHSPLL_RZ_LEN) - 1) << GLB_UHSPLL_RZ_POS)
+#define GLB_UHSPLL_RZ_UMSK (~(((1U << GLB_UHSPLL_RZ_LEN) - 1) << GLB_UHSPLL_RZ_POS))
+#define GLB_UHSPLL_LF_TEST_EN GLB_UHSPLL_LF_TEST_EN
+#define GLB_UHSPLL_LF_TEST_EN_POS (19U)
+#define GLB_UHSPLL_LF_TEST_EN_LEN (1U)
+#define GLB_UHSPLL_LF_TEST_EN_MSK (((1U << GLB_UHSPLL_LF_TEST_EN_LEN) - 1) << GLB_UHSPLL_LF_TEST_EN_POS)
+#define GLB_UHSPLL_LF_TEST_EN_UMSK (~(((1U << GLB_UHSPLL_LF_TEST_EN_LEN) - 1) << GLB_UHSPLL_LF_TEST_EN_POS))
+#define GLB_UHSPLL_FAST_LOCK_EN GLB_UHSPLL_FAST_LOCK_EN
+#define GLB_UHSPLL_FAST_LOCK_EN_POS (20U)
+#define GLB_UHSPLL_FAST_LOCK_EN_LEN (1U)
+#define GLB_UHSPLL_FAST_LOCK_EN_MSK (((1U << GLB_UHSPLL_FAST_LOCK_EN_LEN) - 1) << GLB_UHSPLL_FAST_LOCK_EN_POS)
+#define GLB_UHSPLL_FAST_LOCK_EN_UMSK (~(((1U << GLB_UHSPLL_FAST_LOCK_EN_LEN) - 1) << GLB_UHSPLL_FAST_LOCK_EN_POS))
+
+/* 0x7E0 : uhs_pll_cfg4 */
+#define GLB_UHS_PLL_CFG4_OFFSET (0x7E0)
+#define GLB_UHSPLL_SEL_SAMPLE_CLK GLB_UHSPLL_SEL_SAMPLE_CLK
+#define GLB_UHSPLL_SEL_SAMPLE_CLK_POS (0U)
+#define GLB_UHSPLL_SEL_SAMPLE_CLK_LEN (2U)
+#define GLB_UHSPLL_SEL_SAMPLE_CLK_MSK (((1U << GLB_UHSPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_UHSPLL_SEL_SAMPLE_CLK_POS)
+#define GLB_UHSPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << GLB_UHSPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_UHSPLL_SEL_SAMPLE_CLK_POS))
+#define GLB_UHSPLL_SEL_FB_CLK GLB_UHSPLL_SEL_FB_CLK
+#define GLB_UHSPLL_SEL_FB_CLK_POS (4U)
+#define GLB_UHSPLL_SEL_FB_CLK_LEN (2U)
+#define GLB_UHSPLL_SEL_FB_CLK_MSK (((1U << GLB_UHSPLL_SEL_FB_CLK_LEN) - 1) << GLB_UHSPLL_SEL_FB_CLK_POS)
+#define GLB_UHSPLL_SEL_FB_CLK_UMSK (~(((1U << GLB_UHSPLL_SEL_FB_CLK_LEN) - 1) << GLB_UHSPLL_SEL_FB_CLK_POS))
+#define GLB_UHSPLL_LOCK_DET_EN GLB_UHSPLL_LOCK_DET_EN
+#define GLB_UHSPLL_LOCK_DET_EN_POS (8U)
+#define GLB_UHSPLL_LOCK_DET_EN_LEN (1U)
+#define GLB_UHSPLL_LOCK_DET_EN_MSK (((1U << GLB_UHSPLL_LOCK_DET_EN_LEN) - 1) << GLB_UHSPLL_LOCK_DET_EN_POS)
+#define GLB_UHSPLL_LOCK_DET_EN_UMSK (~(((1U << GLB_UHSPLL_LOCK_DET_EN_LEN) - 1) << GLB_UHSPLL_LOCK_DET_EN_POS))
+#define GLB_UHSPLL_LOCK_CLK_SEL GLB_UHSPLL_LOCK_CLK_SEL
+#define GLB_UHSPLL_LOCK_CLK_SEL_POS (9U)
+#define GLB_UHSPLL_LOCK_CLK_SEL_LEN (2U)
+#define GLB_UHSPLL_LOCK_CLK_SEL_MSK (((1U << GLB_UHSPLL_LOCK_CLK_SEL_LEN) - 1) << GLB_UHSPLL_LOCK_CLK_SEL_POS)
+#define GLB_UHSPLL_LOCK_CLK_SEL_UMSK (~(((1U << GLB_UHSPLL_LOCK_CLK_SEL_LEN) - 1) << GLB_UHSPLL_LOCK_CLK_SEL_POS))
+#define GLB_UHSPLL_LOCK_CLK_INV_EN GLB_UHSPLL_LOCK_CLK_INV_EN
+#define GLB_UHSPLL_LOCK_CLK_INV_EN_POS (12U)
+#define GLB_UHSPLL_LOCK_CLK_INV_EN_LEN (1U)
+#define GLB_UHSPLL_LOCK_CLK_INV_EN_MSK (((1U << GLB_UHSPLL_LOCK_CLK_INV_EN_LEN) - 1) << GLB_UHSPLL_LOCK_CLK_INV_EN_POS)
+#define GLB_UHSPLL_LOCK_CLK_INV_EN_UMSK (~(((1U << GLB_UHSPLL_LOCK_CLK_INV_EN_LEN) - 1) << GLB_UHSPLL_LOCK_CLK_INV_EN_POS))
+#define GLB_UHSPLL_LOCK_WIN_SEL GLB_UHSPLL_LOCK_WIN_SEL
+#define GLB_UHSPLL_LOCK_WIN_SEL_POS (15U)
+#define GLB_UHSPLL_LOCK_WIN_SEL_LEN (2U)
+#define GLB_UHSPLL_LOCK_WIN_SEL_MSK (((1U << GLB_UHSPLL_LOCK_WIN_SEL_LEN) - 1) << GLB_UHSPLL_LOCK_WIN_SEL_POS)
+#define GLB_UHSPLL_LOCK_WIN_SEL_UMSK (~(((1U << GLB_UHSPLL_LOCK_WIN_SEL_LEN) - 1) << GLB_UHSPLL_LOCK_WIN_SEL_POS))
+
+/* 0x7E4 : uhs_pll_cfg5 */
+#define GLB_UHS_PLL_CFG5_OFFSET (0x7E4)
+#define GLB_UHSPLL_VCO_SPEED GLB_UHSPLL_VCO_SPEED
+#define GLB_UHSPLL_VCO_SPEED_POS (0U)
+#define GLB_UHSPLL_VCO_SPEED_LEN (3U)
+#define GLB_UHSPLL_VCO_SPEED_MSK (((1U << GLB_UHSPLL_VCO_SPEED_LEN) - 1) << GLB_UHSPLL_VCO_SPEED_POS)
+#define GLB_UHSPLL_VCO_SPEED_UMSK (~(((1U << GLB_UHSPLL_VCO_SPEED_LEN) - 1) << GLB_UHSPLL_VCO_SPEED_POS))
+#define GLB_UHSPLL_VCO_VDD_CTRL GLB_UHSPLL_VCO_VDD_CTRL
+#define GLB_UHSPLL_VCO_VDD_CTRL_POS (3U)
+#define GLB_UHSPLL_VCO_VDD_CTRL_LEN (2U)
+#define GLB_UHSPLL_VCO_VDD_CTRL_MSK (((1U << GLB_UHSPLL_VCO_VDD_CTRL_LEN) - 1) << GLB_UHSPLL_VCO_VDD_CTRL_POS)
+#define GLB_UHSPLL_VCO_VDD_CTRL_UMSK (~(((1U << GLB_UHSPLL_VCO_VDD_CTRL_LEN) - 1) << GLB_UHSPLL_VCO_VDD_CTRL_POS))
+#define GLB_UHSPLL_VCO_VDD_CTRL_EXTRA GLB_UHSPLL_VCO_VDD_CTRL_EXTRA
+#define GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_POS (5U)
+#define GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_LEN (1U)
+#define GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_MSK (((1U << GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_LEN) - 1) << GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_POS)
+#define GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_UMSK (~(((1U << GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_LEN) - 1) << GLB_UHSPLL_VCO_VDD_CTRL_EXTRA_POS))
+#define GLB_UHSPLL_VCO_POSTDIV_SEL GLB_UHSPLL_VCO_POSTDIV_SEL
+#define GLB_UHSPLL_VCO_POSTDIV_SEL_POS (7U)
+#define GLB_UHSPLL_VCO_POSTDIV_SEL_LEN (3U)
+#define GLB_UHSPLL_VCO_POSTDIV_SEL_MSK (((1U << GLB_UHSPLL_VCO_POSTDIV_SEL_LEN) - 1) << GLB_UHSPLL_VCO_POSTDIV_SEL_POS)
+#define GLB_UHSPLL_VCO_POSTDIV_SEL_UMSK (~(((1U << GLB_UHSPLL_VCO_POSTDIV_SEL_LEN) - 1) << GLB_UHSPLL_VCO_POSTDIV_SEL_POS))
+#define GLB_UHSPLL_VCO_POSTDIV_CLK_EN GLB_UHSPLL_VCO_POSTDIV_CLK_EN
+#define GLB_UHSPLL_VCO_POSTDIV_CLK_EN_POS (10U)
+#define GLB_UHSPLL_VCO_POSTDIV_CLK_EN_LEN (1U)
+#define GLB_UHSPLL_VCO_POSTDIV_CLK_EN_MSK (((1U << GLB_UHSPLL_VCO_POSTDIV_CLK_EN_LEN) - 1) << GLB_UHSPLL_VCO_POSTDIV_CLK_EN_POS)
+#define GLB_UHSPLL_VCO_POSTDIV_CLK_EN_UMSK (~(((1U << GLB_UHSPLL_VCO_POSTDIV_CLK_EN_LEN) - 1) << GLB_UHSPLL_VCO_POSTDIV_CLK_EN_POS))
+
+/* 0x7E8 : uhs_pll_cfg6 */
+#define GLB_UHS_PLL_CFG6_OFFSET (0x7E8)
+#define GLB_UHSPLL_SDMIN GLB_UHSPLL_SDMIN
+#define GLB_UHSPLL_SDMIN_POS (0U)
+#define GLB_UHSPLL_SDMIN_LEN (19U)
+#define GLB_UHSPLL_SDMIN_MSK (((1U << GLB_UHSPLL_SDMIN_LEN) - 1) << GLB_UHSPLL_SDMIN_POS)
+#define GLB_UHSPLL_SDMIN_UMSK (~(((1U << GLB_UHSPLL_SDMIN_LEN) - 1) << GLB_UHSPLL_SDMIN_POS))
+#define GLB_UHSPLL_SDM_BYPASS GLB_UHSPLL_SDM_BYPASS
+#define GLB_UHSPLL_SDM_BYPASS_POS (24U)
+#define GLB_UHSPLL_SDM_BYPASS_LEN (1U)
+#define GLB_UHSPLL_SDM_BYPASS_MSK (((1U << GLB_UHSPLL_SDM_BYPASS_LEN) - 1) << GLB_UHSPLL_SDM_BYPASS_POS)
+#define GLB_UHSPLL_SDM_BYPASS_UMSK (~(((1U << GLB_UHSPLL_SDM_BYPASS_LEN) - 1) << GLB_UHSPLL_SDM_BYPASS_POS))
+
+/* 0x7EC : uhs_pll_cfg7 */
+#define GLB_UHS_PLL_CFG7_OFFSET (0x7EC)
+#define GLB_UHSPLL_SDM_ORDER_SEL GLB_UHSPLL_SDM_ORDER_SEL
+#define GLB_UHSPLL_SDM_ORDER_SEL_POS (0U)
+#define GLB_UHSPLL_SDM_ORDER_SEL_LEN (1U)
+#define GLB_UHSPLL_SDM_ORDER_SEL_MSK (((1U << GLB_UHSPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_UHSPLL_SDM_ORDER_SEL_POS)
+#define GLB_UHSPLL_SDM_ORDER_SEL_UMSK (~(((1U << GLB_UHSPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_UHSPLL_SDM_ORDER_SEL_POS))
+#define GLB_UHSPLL_SDM_DITH_SEL GLB_UHSPLL_SDM_DITH_SEL
+#define GLB_UHSPLL_SDM_DITH_SEL_POS (1U)
+#define GLB_UHSPLL_SDM_DITH_SEL_LEN (2U)
+#define GLB_UHSPLL_SDM_DITH_SEL_MSK (((1U << GLB_UHSPLL_SDM_DITH_SEL_LEN) - 1) << GLB_UHSPLL_SDM_DITH_SEL_POS)
+#define GLB_UHSPLL_SDM_DITH_SEL_UMSK (~(((1U << GLB_UHSPLL_SDM_DITH_SEL_LEN) - 1) << GLB_UHSPLL_SDM_DITH_SEL_POS))
+
+/* 0x7F0 : uhs_pll_cfg8 */
+#define GLB_UHS_PLL_CFG8_OFFSET (0x7F0)
+#define GLB_UHSPLL_DC_TP_OUT_EN GLB_UHSPLL_DC_TP_OUT_EN
+#define GLB_UHSPLL_DC_TP_OUT_EN_POS (0U)
+#define GLB_UHSPLL_DC_TP_OUT_EN_LEN (1U)
+#define GLB_UHSPLL_DC_TP_OUT_EN_MSK (((1U << GLB_UHSPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_UHSPLL_DC_TP_OUT_EN_POS)
+#define GLB_UHSPLL_DC_TP_OUT_EN_UMSK (~(((1U << GLB_UHSPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_UHSPLL_DC_TP_OUT_EN_POS))
+#define GLB_UHSPLL_TEN GLB_UHSPLL_TEN
+#define GLB_UHSPLL_TEN_POS (1U)
+#define GLB_UHSPLL_TEN_LEN (1U)
+#define GLB_UHSPLL_TEN_MSK (((1U << GLB_UHSPLL_TEN_LEN) - 1) << GLB_UHSPLL_TEN_POS)
+#define GLB_UHSPLL_TEN_UMSK (~(((1U << GLB_UHSPLL_TEN_LEN) - 1) << GLB_UHSPLL_TEN_POS))
+#define GLB_UHSPLL_TEN_SFREG GLB_UHSPLL_TEN_SFREG
+#define GLB_UHSPLL_TEN_SFREG_POS (2U)
+#define GLB_UHSPLL_TEN_SFREG_LEN (1U)
+#define GLB_UHSPLL_TEN_SFREG_MSK (((1U << GLB_UHSPLL_TEN_SFREG_LEN) - 1) << GLB_UHSPLL_TEN_SFREG_POS)
+#define GLB_UHSPLL_TEN_SFREG_UMSK (~(((1U << GLB_UHSPLL_TEN_SFREG_LEN) - 1) << GLB_UHSPLL_TEN_SFREG_POS))
+#define GLB_UHSPLL_DTEN_CKIN GLB_UHSPLL_DTEN_CKIN
+#define GLB_UHSPLL_DTEN_CKIN_POS (4U)
+#define GLB_UHSPLL_DTEN_CKIN_LEN (1U)
+#define GLB_UHSPLL_DTEN_CKIN_MSK (((1U << GLB_UHSPLL_DTEN_CKIN_LEN) - 1) << GLB_UHSPLL_DTEN_CKIN_POS)
+#define GLB_UHSPLL_DTEN_CKIN_UMSK (~(((1U << GLB_UHSPLL_DTEN_CKIN_LEN) - 1) << GLB_UHSPLL_DTEN_CKIN_POS))
+#define GLB_UHSPLL_DTEN_FREF GLB_UHSPLL_DTEN_FREF
+#define GLB_UHSPLL_DTEN_FREF_POS (5U)
+#define GLB_UHSPLL_DTEN_FREF_LEN (1U)
+#define GLB_UHSPLL_DTEN_FREF_MSK (((1U << GLB_UHSPLL_DTEN_FREF_LEN) - 1) << GLB_UHSPLL_DTEN_FREF_POS)
+#define GLB_UHSPLL_DTEN_FREF_UMSK (~(((1U << GLB_UHSPLL_DTEN_FREF_LEN) - 1) << GLB_UHSPLL_DTEN_FREF_POS))
+#define GLB_UHSPLL_DTEN_FSDM GLB_UHSPLL_DTEN_FSDM
+#define GLB_UHSPLL_DTEN_FSDM_POS (6U)
+#define GLB_UHSPLL_DTEN_FSDM_LEN (1U)
+#define GLB_UHSPLL_DTEN_FSDM_MSK (((1U << GLB_UHSPLL_DTEN_FSDM_LEN) - 1) << GLB_UHSPLL_DTEN_FSDM_POS)
+#define GLB_UHSPLL_DTEN_FSDM_UMSK (~(((1U << GLB_UHSPLL_DTEN_FSDM_LEN) - 1) << GLB_UHSPLL_DTEN_FSDM_POS))
+#define GLB_UHSPLL_DTEN_PUPLL GLB_UHSPLL_DTEN_PUPLL
+#define GLB_UHSPLL_DTEN_PUPLL_POS (7U)
+#define GLB_UHSPLL_DTEN_PUPLL_LEN (1U)
+#define GLB_UHSPLL_DTEN_PUPLL_MSK (((1U << GLB_UHSPLL_DTEN_PUPLL_LEN) - 1) << GLB_UHSPLL_DTEN_PUPLL_POS)
+#define GLB_UHSPLL_DTEN_PUPLL_UMSK (~(((1U << GLB_UHSPLL_DTEN_PUPLL_LEN) - 1) << GLB_UHSPLL_DTEN_PUPLL_POS))
+#define GLB_UHSPLL_DTEN_PLL_LOCKED GLB_UHSPLL_DTEN_PLL_LOCKED
+#define GLB_UHSPLL_DTEN_PLL_LOCKED_POS (8U)
+#define GLB_UHSPLL_DTEN_PLL_LOCKED_LEN (1U)
+#define GLB_UHSPLL_DTEN_PLL_LOCKED_MSK (((1U << GLB_UHSPLL_DTEN_PLL_LOCKED_LEN) - 1) << GLB_UHSPLL_DTEN_PLL_LOCKED_POS)
+#define GLB_UHSPLL_DTEN_PLL_LOCKED_UMSK (~(((1U << GLB_UHSPLL_DTEN_PLL_LOCKED_LEN) - 1) << GLB_UHSPLL_DTEN_PLL_LOCKED_POS))
+#define GLB_UHSPLL_DTEST_PULL_DOWN GLB_UHSPLL_DTEST_PULL_DOWN
+#define GLB_UHSPLL_DTEST_PULL_DOWN_POS (10U)
+#define GLB_UHSPLL_DTEST_PULL_DOWN_LEN (1U)
+#define GLB_UHSPLL_DTEST_PULL_DOWN_MSK (((1U << GLB_UHSPLL_DTEST_PULL_DOWN_LEN) - 1) << GLB_UHSPLL_DTEST_PULL_DOWN_POS)
+#define GLB_UHSPLL_DTEST_PULL_DOWN_UMSK (~(((1U << GLB_UHSPLL_DTEST_PULL_DOWN_LEN) - 1) << GLB_UHSPLL_DTEST_PULL_DOWN_POS))
+
+/* 0x7F4 : uhs_pll_cfg9 */
+#define GLB_UHS_PLL_CFG9_OFFSET (0x7F4)
+#define GLB_UHSPLL_SSC_EN GLB_UHSPLL_SSC_EN
+#define GLB_UHSPLL_SSC_EN_POS (0U)
+#define GLB_UHSPLL_SSC_EN_LEN (1U)
+#define GLB_UHSPLL_SSC_EN_MSK (((1U << GLB_UHSPLL_SSC_EN_LEN) - 1) << GLB_UHSPLL_SSC_EN_POS)
+#define GLB_UHSPLL_SSC_EN_UMSK (~(((1U << GLB_UHSPLL_SSC_EN_LEN) - 1) << GLB_UHSPLL_SSC_EN_POS))
+#define GLB_UHSPLL_SSC_CNT GLB_UHSPLL_SSC_CNT
+#define GLB_UHSPLL_SSC_CNT_POS (4U)
+#define GLB_UHSPLL_SSC_CNT_LEN (8U)
+#define GLB_UHSPLL_SSC_CNT_MSK (((1U << GLB_UHSPLL_SSC_CNT_LEN) - 1) << GLB_UHSPLL_SSC_CNT_POS)
+#define GLB_UHSPLL_SSC_CNT_UMSK (~(((1U << GLB_UHSPLL_SSC_CNT_LEN) - 1) << GLB_UHSPLL_SSC_CNT_POS))
+#define GLB_UHSPLL_SSC_GAIN GLB_UHSPLL_SSC_GAIN
+#define GLB_UHSPLL_SSC_GAIN_POS (12U)
+#define GLB_UHSPLL_SSC_GAIN_LEN (3U)
+#define GLB_UHSPLL_SSC_GAIN_MSK (((1U << GLB_UHSPLL_SSC_GAIN_LEN) - 1) << GLB_UHSPLL_SSC_GAIN_POS)
+#define GLB_UHSPLL_SSC_GAIN_UMSK (~(((1U << GLB_UHSPLL_SSC_GAIN_LEN) - 1) << GLB_UHSPLL_SSC_GAIN_POS))
+#define GLB_UHSPLL_SSC_START_GATE_EN GLB_UHSPLL_SSC_START_GATE_EN
+#define GLB_UHSPLL_SSC_START_GATE_EN_POS (16U)
+#define GLB_UHSPLL_SSC_START_GATE_EN_LEN (1U)
+#define GLB_UHSPLL_SSC_START_GATE_EN_MSK (((1U << GLB_UHSPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_UHSPLL_SSC_START_GATE_EN_POS)
+#define GLB_UHSPLL_SSC_START_GATE_EN_UMSK (~(((1U << GLB_UHSPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_UHSPLL_SSC_START_GATE_EN_POS))
+
+/* 0x810 : wifi_pll_cfg0 */
+#define GLB_WIFI_PLL_CFG0_OFFSET (0x810)
+#define GLB_WIFIPLL_SDM_RSTB GLB_WIFIPLL_SDM_RSTB
+#define GLB_WIFIPLL_SDM_RSTB_POS (0U)
+#define GLB_WIFIPLL_SDM_RSTB_LEN (1U)
+#define GLB_WIFIPLL_SDM_RSTB_MSK (((1U << GLB_WIFIPLL_SDM_RSTB_LEN) - 1) << GLB_WIFIPLL_SDM_RSTB_POS)
+#define GLB_WIFIPLL_SDM_RSTB_UMSK (~(((1U << GLB_WIFIPLL_SDM_RSTB_LEN) - 1) << GLB_WIFIPLL_SDM_RSTB_POS))
+#define GLB_WIFIPLL_POSTDIV_RSTB GLB_WIFIPLL_POSTDIV_RSTB
+#define GLB_WIFIPLL_POSTDIV_RSTB_POS (1U)
+#define GLB_WIFIPLL_POSTDIV_RSTB_LEN (1U)
+#define GLB_WIFIPLL_POSTDIV_RSTB_MSK (((1U << GLB_WIFIPLL_POSTDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_POSTDIV_RSTB_POS)
+#define GLB_WIFIPLL_POSTDIV_RSTB_UMSK (~(((1U << GLB_WIFIPLL_POSTDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_POSTDIV_RSTB_POS))
+#define GLB_WIFIPLL_FBDV_RSTB GLB_WIFIPLL_FBDV_RSTB
+#define GLB_WIFIPLL_FBDV_RSTB_POS (2U)
+#define GLB_WIFIPLL_FBDV_RSTB_LEN (1U)
+#define GLB_WIFIPLL_FBDV_RSTB_MSK (((1U << GLB_WIFIPLL_FBDV_RSTB_LEN) - 1) << GLB_WIFIPLL_FBDV_RSTB_POS)
+#define GLB_WIFIPLL_FBDV_RSTB_UMSK (~(((1U << GLB_WIFIPLL_FBDV_RSTB_LEN) - 1) << GLB_WIFIPLL_FBDV_RSTB_POS))
+#define GLB_WIFIPLL_REFDIV_RSTB GLB_WIFIPLL_REFDIV_RSTB
+#define GLB_WIFIPLL_REFDIV_RSTB_POS (3U)
+#define GLB_WIFIPLL_REFDIV_RSTB_LEN (1U)
+#define GLB_WIFIPLL_REFDIV_RSTB_MSK (((1U << GLB_WIFIPLL_REFDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_REFDIV_RSTB_POS)
+#define GLB_WIFIPLL_REFDIV_RSTB_UMSK (~(((1U << GLB_WIFIPLL_REFDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_REFDIV_RSTB_POS))
+#define GLB_PU_WIFIPLL_POSTDIV GLB_PU_WIFIPLL_POSTDIV
+#define GLB_PU_WIFIPLL_POSTDIV_POS (4U)
+#define GLB_PU_WIFIPLL_POSTDIV_LEN (1U)
+#define GLB_PU_WIFIPLL_POSTDIV_MSK (((1U << GLB_PU_WIFIPLL_POSTDIV_LEN) - 1) << GLB_PU_WIFIPLL_POSTDIV_POS)
+#define GLB_PU_WIFIPLL_POSTDIV_UMSK (~(((1U << GLB_PU_WIFIPLL_POSTDIV_LEN) - 1) << GLB_PU_WIFIPLL_POSTDIV_POS))
+#define GLB_PU_WIFIPLL_FBDV GLB_PU_WIFIPLL_FBDV
+#define GLB_PU_WIFIPLL_FBDV_POS (5U)
+#define GLB_PU_WIFIPLL_FBDV_LEN (1U)
+#define GLB_PU_WIFIPLL_FBDV_MSK (((1U << GLB_PU_WIFIPLL_FBDV_LEN) - 1) << GLB_PU_WIFIPLL_FBDV_POS)
+#define GLB_PU_WIFIPLL_FBDV_UMSK (~(((1U << GLB_PU_WIFIPLL_FBDV_LEN) - 1) << GLB_PU_WIFIPLL_FBDV_POS))
+#define GLB_PU_WIFIPLL_CLAMP_OP GLB_PU_WIFIPLL_CLAMP_OP
+#define GLB_PU_WIFIPLL_CLAMP_OP_POS (6U)
+#define GLB_PU_WIFIPLL_CLAMP_OP_LEN (1U)
+#define GLB_PU_WIFIPLL_CLAMP_OP_MSK (((1U << GLB_PU_WIFIPLL_CLAMP_OP_LEN) - 1) << GLB_PU_WIFIPLL_CLAMP_OP_POS)
+#define GLB_PU_WIFIPLL_CLAMP_OP_UMSK (~(((1U << GLB_PU_WIFIPLL_CLAMP_OP_LEN) - 1) << GLB_PU_WIFIPLL_CLAMP_OP_POS))
+#define GLB_PU_WIFIPLL_PFD GLB_PU_WIFIPLL_PFD
+#define GLB_PU_WIFIPLL_PFD_POS (7U)
+#define GLB_PU_WIFIPLL_PFD_LEN (1U)
+#define GLB_PU_WIFIPLL_PFD_MSK (((1U << GLB_PU_WIFIPLL_PFD_LEN) - 1) << GLB_PU_WIFIPLL_PFD_POS)
+#define GLB_PU_WIFIPLL_PFD_UMSK (~(((1U << GLB_PU_WIFIPLL_PFD_LEN) - 1) << GLB_PU_WIFIPLL_PFD_POS))
+#define GLB_PU_WIFIPLL_CP GLB_PU_WIFIPLL_CP
+#define GLB_PU_WIFIPLL_CP_POS (8U)
+#define GLB_PU_WIFIPLL_CP_LEN (1U)
+#define GLB_PU_WIFIPLL_CP_MSK (((1U << GLB_PU_WIFIPLL_CP_LEN) - 1) << GLB_PU_WIFIPLL_CP_POS)
+#define GLB_PU_WIFIPLL_CP_UMSK (~(((1U << GLB_PU_WIFIPLL_CP_LEN) - 1) << GLB_PU_WIFIPLL_CP_POS))
+#define GLB_PU_WIFIPLL_SFREG GLB_PU_WIFIPLL_SFREG
+#define GLB_PU_WIFIPLL_SFREG_POS (9U)
+#define GLB_PU_WIFIPLL_SFREG_LEN (1U)
+#define GLB_PU_WIFIPLL_SFREG_MSK (((1U << GLB_PU_WIFIPLL_SFREG_LEN) - 1) << GLB_PU_WIFIPLL_SFREG_POS)
+#define GLB_PU_WIFIPLL_SFREG_UMSK (~(((1U << GLB_PU_WIFIPLL_SFREG_LEN) - 1) << GLB_PU_WIFIPLL_SFREG_POS))
+#define GLB_PU_WIFIPLL GLB_PU_WIFIPLL
+#define GLB_PU_WIFIPLL_POS (10U)
+#define GLB_PU_WIFIPLL_LEN (1U)
+#define GLB_PU_WIFIPLL_MSK (((1U << GLB_PU_WIFIPLL_LEN) - 1) << GLB_PU_WIFIPLL_POS)
+#define GLB_PU_WIFIPLL_UMSK (~(((1U << GLB_PU_WIFIPLL_LEN) - 1) << GLB_PU_WIFIPLL_POS))
+#define GLB_PU_WIFIPLL_CLKTREE GLB_PU_WIFIPLL_CLKTREE
+#define GLB_PU_WIFIPLL_CLKTREE_POS (11U)
+#define GLB_PU_WIFIPLL_CLKTREE_LEN (1U)
+#define GLB_PU_WIFIPLL_CLKTREE_MSK (((1U << GLB_PU_WIFIPLL_CLKTREE_LEN) - 1) << GLB_PU_WIFIPLL_CLKTREE_POS)
+#define GLB_PU_WIFIPLL_CLKTREE_UMSK (~(((1U << GLB_PU_WIFIPLL_CLKTREE_LEN) - 1) << GLB_PU_WIFIPLL_CLKTREE_POS))
+
+/* 0x814 : wifi_pll_cfg1 */
+#define GLB_WIFI_PLL_CFG1_OFFSET (0x814)
+#define GLB_WIFIPLL_POSTDIV GLB_WIFIPLL_POSTDIV
+#define GLB_WIFIPLL_POSTDIV_POS (0U)
+#define GLB_WIFIPLL_POSTDIV_LEN (7U)
+#define GLB_WIFIPLL_POSTDIV_MSK (((1U << GLB_WIFIPLL_POSTDIV_LEN) - 1) << GLB_WIFIPLL_POSTDIV_POS)
+#define GLB_WIFIPLL_POSTDIV_UMSK (~(((1U << GLB_WIFIPLL_POSTDIV_LEN) - 1) << GLB_WIFIPLL_POSTDIV_POS))
+#define GLB_WIFIPLL_REFDIV_RATIO GLB_WIFIPLL_REFDIV_RATIO
+#define GLB_WIFIPLL_REFDIV_RATIO_POS (8U)
+#define GLB_WIFIPLL_REFDIV_RATIO_LEN (4U)
+#define GLB_WIFIPLL_REFDIV_RATIO_MSK (((1U << GLB_WIFIPLL_REFDIV_RATIO_LEN) - 1) << GLB_WIFIPLL_REFDIV_RATIO_POS)
+#define GLB_WIFIPLL_REFDIV_RATIO_UMSK (~(((1U << GLB_WIFIPLL_REFDIV_RATIO_LEN) - 1) << GLB_WIFIPLL_REFDIV_RATIO_POS))
+#define GLB_WIFIPLL_REFCLK_SEL GLB_WIFIPLL_REFCLK_SEL
+#define GLB_WIFIPLL_REFCLK_SEL_POS (16U)
+#define GLB_WIFIPLL_REFCLK_SEL_LEN (2U)
+#define GLB_WIFIPLL_REFCLK_SEL_MSK (((1U << GLB_WIFIPLL_REFCLK_SEL_LEN) - 1) << GLB_WIFIPLL_REFCLK_SEL_POS)
+#define GLB_WIFIPLL_REFCLK_SEL_UMSK (~(((1U << GLB_WIFIPLL_REFCLK_SEL_LEN) - 1) << GLB_WIFIPLL_REFCLK_SEL_POS))
+#define GLB_WIFIPLL_VG11_SEL GLB_WIFIPLL_VG11_SEL
+#define GLB_WIFIPLL_VG11_SEL_POS (20U)
+#define GLB_WIFIPLL_VG11_SEL_LEN (2U)
+#define GLB_WIFIPLL_VG11_SEL_MSK (((1U << GLB_WIFIPLL_VG11_SEL_LEN) - 1) << GLB_WIFIPLL_VG11_SEL_POS)
+#define GLB_WIFIPLL_VG11_SEL_UMSK (~(((1U << GLB_WIFIPLL_VG11_SEL_LEN) - 1) << GLB_WIFIPLL_VG11_SEL_POS))
+#define GLB_WIFIPLL_VG13_SEL GLB_WIFIPLL_VG13_SEL
+#define GLB_WIFIPLL_VG13_SEL_POS (24U)
+#define GLB_WIFIPLL_VG13_SEL_LEN (2U)
+#define GLB_WIFIPLL_VG13_SEL_MSK (((1U << GLB_WIFIPLL_VG13_SEL_LEN) - 1) << GLB_WIFIPLL_VG13_SEL_POS)
+#define GLB_WIFIPLL_VG13_SEL_UMSK (~(((1U << GLB_WIFIPLL_VG13_SEL_LEN) - 1) << GLB_WIFIPLL_VG13_SEL_POS))
+
+/* 0x818 : wifi_pll_cfg2 */
+#define GLB_WIFI_PLL_CFG2_OFFSET (0x818)
+#define GLB_WIFIPLL_SEL_CP_BIAS GLB_WIFIPLL_SEL_CP_BIAS
+#define GLB_WIFIPLL_SEL_CP_BIAS_POS (0U)
+#define GLB_WIFIPLL_SEL_CP_BIAS_LEN (1U)
+#define GLB_WIFIPLL_SEL_CP_BIAS_MSK (((1U << GLB_WIFIPLL_SEL_CP_BIAS_LEN) - 1) << GLB_WIFIPLL_SEL_CP_BIAS_POS)
+#define GLB_WIFIPLL_SEL_CP_BIAS_UMSK (~(((1U << GLB_WIFIPLL_SEL_CP_BIAS_LEN) - 1) << GLB_WIFIPLL_SEL_CP_BIAS_POS))
+#define GLB_WIFIPLL_ICP_5U GLB_WIFIPLL_ICP_5U
+#define GLB_WIFIPLL_ICP_5U_POS (4U)
+#define GLB_WIFIPLL_ICP_5U_LEN (2U)
+#define GLB_WIFIPLL_ICP_5U_MSK (((1U << GLB_WIFIPLL_ICP_5U_LEN) - 1) << GLB_WIFIPLL_ICP_5U_POS)
+#define GLB_WIFIPLL_ICP_5U_UMSK (~(((1U << GLB_WIFIPLL_ICP_5U_LEN) - 1) << GLB_WIFIPLL_ICP_5U_POS))
+#define GLB_WIFIPLL_ICP_1U GLB_WIFIPLL_ICP_1U
+#define GLB_WIFIPLL_ICP_1U_POS (6U)
+#define GLB_WIFIPLL_ICP_1U_LEN (2U)
+#define GLB_WIFIPLL_ICP_1U_MSK (((1U << GLB_WIFIPLL_ICP_1U_LEN) - 1) << GLB_WIFIPLL_ICP_1U_POS)
+#define GLB_WIFIPLL_ICP_1U_UMSK (~(((1U << GLB_WIFIPLL_ICP_1U_LEN) - 1) << GLB_WIFIPLL_ICP_1U_POS))
+#define GLB_WIFIPLL_INT_FRAC_SW GLB_WIFIPLL_INT_FRAC_SW
+#define GLB_WIFIPLL_INT_FRAC_SW_POS (8U)
+#define GLB_WIFIPLL_INT_FRAC_SW_LEN (1U)
+#define GLB_WIFIPLL_INT_FRAC_SW_MSK (((1U << GLB_WIFIPLL_INT_FRAC_SW_LEN) - 1) << GLB_WIFIPLL_INT_FRAC_SW_POS)
+#define GLB_WIFIPLL_INT_FRAC_SW_UMSK (~(((1U << GLB_WIFIPLL_INT_FRAC_SW_LEN) - 1) << GLB_WIFIPLL_INT_FRAC_SW_POS))
+#define GLB_WIFIPLL_CP_STARTUP_EN GLB_WIFIPLL_CP_STARTUP_EN
+#define GLB_WIFIPLL_CP_STARTUP_EN_POS (9U)
+#define GLB_WIFIPLL_CP_STARTUP_EN_LEN (1U)
+#define GLB_WIFIPLL_CP_STARTUP_EN_MSK (((1U << GLB_WIFIPLL_CP_STARTUP_EN_LEN) - 1) << GLB_WIFIPLL_CP_STARTUP_EN_POS)
+#define GLB_WIFIPLL_CP_STARTUP_EN_UMSK (~(((1U << GLB_WIFIPLL_CP_STARTUP_EN_LEN) - 1) << GLB_WIFIPLL_CP_STARTUP_EN_POS))
+#define GLB_WIFIPLL_CP_OPAMP_EN GLB_WIFIPLL_CP_OPAMP_EN
+#define GLB_WIFIPLL_CP_OPAMP_EN_POS (10U)
+#define GLB_WIFIPLL_CP_OPAMP_EN_LEN (1U)
+#define GLB_WIFIPLL_CP_OPAMP_EN_MSK (((1U << GLB_WIFIPLL_CP_OPAMP_EN_LEN) - 1) << GLB_WIFIPLL_CP_OPAMP_EN_POS)
+#define GLB_WIFIPLL_CP_OPAMP_EN_UMSK (~(((1U << GLB_WIFIPLL_CP_OPAMP_EN_LEN) - 1) << GLB_WIFIPLL_CP_OPAMP_EN_POS))
+
+/* 0x81C : wifi_pll_cfg3 */
+#define GLB_WIFI_PLL_CFG3_OFFSET (0x81C)
+#define GLB_WIFIPLL_C4_EN GLB_WIFIPLL_C4_EN
+#define GLB_WIFIPLL_C4_EN_POS (0U)
+#define GLB_WIFIPLL_C4_EN_LEN (1U)
+#define GLB_WIFIPLL_C4_EN_MSK (((1U << GLB_WIFIPLL_C4_EN_LEN) - 1) << GLB_WIFIPLL_C4_EN_POS)
+#define GLB_WIFIPLL_C4_EN_UMSK (~(((1U << GLB_WIFIPLL_C4_EN_LEN) - 1) << GLB_WIFIPLL_C4_EN_POS))
+#define GLB_WIFIPLL_R4 GLB_WIFIPLL_R4
+#define GLB_WIFIPLL_R4_POS (4U)
+#define GLB_WIFIPLL_R4_LEN (2U)
+#define GLB_WIFIPLL_R4_MSK (((1U << GLB_WIFIPLL_R4_LEN) - 1) << GLB_WIFIPLL_R4_POS)
+#define GLB_WIFIPLL_R4_UMSK (~(((1U << GLB_WIFIPLL_R4_LEN) - 1) << GLB_WIFIPLL_R4_POS))
+#define GLB_WIFIPLL_R4_SHORT GLB_WIFIPLL_R4_SHORT
+#define GLB_WIFIPLL_R4_SHORT_POS (8U)
+#define GLB_WIFIPLL_R4_SHORT_LEN (1U)
+#define GLB_WIFIPLL_R4_SHORT_MSK (((1U << GLB_WIFIPLL_R4_SHORT_LEN) - 1) << GLB_WIFIPLL_R4_SHORT_POS)
+#define GLB_WIFIPLL_R4_SHORT_UMSK (~(((1U << GLB_WIFIPLL_R4_SHORT_LEN) - 1) << GLB_WIFIPLL_R4_SHORT_POS))
+#define GLB_WIFIPLL_C3 GLB_WIFIPLL_C3
+#define GLB_WIFIPLL_C3_POS (12U)
+#define GLB_WIFIPLL_C3_LEN (2U)
+#define GLB_WIFIPLL_C3_MSK (((1U << GLB_WIFIPLL_C3_LEN) - 1) << GLB_WIFIPLL_C3_POS)
+#define GLB_WIFIPLL_C3_UMSK (~(((1U << GLB_WIFIPLL_C3_LEN) - 1) << GLB_WIFIPLL_C3_POS))
+#define GLB_WIFIPLL_CZ GLB_WIFIPLL_CZ
+#define GLB_WIFIPLL_CZ_POS (14U)
+#define GLB_WIFIPLL_CZ_LEN (2U)
+#define GLB_WIFIPLL_CZ_MSK (((1U << GLB_WIFIPLL_CZ_LEN) - 1) << GLB_WIFIPLL_CZ_POS)
+#define GLB_WIFIPLL_CZ_UMSK (~(((1U << GLB_WIFIPLL_CZ_LEN) - 1) << GLB_WIFIPLL_CZ_POS))
+#define GLB_WIFIPLL_RZ GLB_WIFIPLL_RZ
+#define GLB_WIFIPLL_RZ_POS (16U)
+#define GLB_WIFIPLL_RZ_LEN (3U)
+#define GLB_WIFIPLL_RZ_MSK (((1U << GLB_WIFIPLL_RZ_LEN) - 1) << GLB_WIFIPLL_RZ_POS)
+#define GLB_WIFIPLL_RZ_UMSK (~(((1U << GLB_WIFIPLL_RZ_LEN) - 1) << GLB_WIFIPLL_RZ_POS))
+
+/* 0x820 : wifi_pll_cfg4 */
+#define GLB_WIFI_PLL_CFG4_OFFSET (0x820)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK GLB_WIFIPLL_SEL_SAMPLE_CLK
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_POS (0U)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_LEN (2U)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_MSK (((1U << GLB_WIFIPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_SAMPLE_CLK_POS)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << GLB_WIFIPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_SAMPLE_CLK_POS))
+#define GLB_WIFIPLL_SEL_FB_CLK GLB_WIFIPLL_SEL_FB_CLK
+#define GLB_WIFIPLL_SEL_FB_CLK_POS (4U)
+#define GLB_WIFIPLL_SEL_FB_CLK_LEN (2U)
+#define GLB_WIFIPLL_SEL_FB_CLK_MSK (((1U << GLB_WIFIPLL_SEL_FB_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_FB_CLK_POS)
+#define GLB_WIFIPLL_SEL_FB_CLK_UMSK (~(((1U << GLB_WIFIPLL_SEL_FB_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_FB_CLK_POS))
+#define GLB_WIFIPLL_SDMCLK_SEL GLB_WIFIPLL_SDMCLK_SEL
+#define GLB_WIFIPLL_SDMCLK_SEL_POS (8U)
+#define GLB_WIFIPLL_SDMCLK_SEL_LEN (1U)
+#define GLB_WIFIPLL_SDMCLK_SEL_MSK (((1U << GLB_WIFIPLL_SDMCLK_SEL_LEN) - 1) << GLB_WIFIPLL_SDMCLK_SEL_POS)
+#define GLB_WIFIPLL_SDMCLK_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDMCLK_SEL_LEN) - 1) << GLB_WIFIPLL_SDMCLK_SEL_POS))
+
+/* 0x824 : wifi_pll_cfg5 */
+#define GLB_WIFI_PLL_CFG5_OFFSET (0x824)
+#define GLB_WIFIPLL_VCO_SPEED GLB_WIFIPLL_VCO_SPEED
+#define GLB_WIFIPLL_VCO_SPEED_POS (0U)
+#define GLB_WIFIPLL_VCO_SPEED_LEN (3U)
+#define GLB_WIFIPLL_VCO_SPEED_MSK (((1U << GLB_WIFIPLL_VCO_SPEED_LEN) - 1) << GLB_WIFIPLL_VCO_SPEED_POS)
+#define GLB_WIFIPLL_VCO_SPEED_UMSK (~(((1U << GLB_WIFIPLL_VCO_SPEED_LEN) - 1) << GLB_WIFIPLL_VCO_SPEED_POS))
+#define GLB_WIFIPLL_VCO_DIV1_EN GLB_WIFIPLL_VCO_DIV1_EN
+#define GLB_WIFIPLL_VCO_DIV1_EN_POS (4U)
+#define GLB_WIFIPLL_VCO_DIV1_EN_LEN (1U)
+#define GLB_WIFIPLL_VCO_DIV1_EN_MSK (((1U << GLB_WIFIPLL_VCO_DIV1_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV1_EN_POS)
+#define GLB_WIFIPLL_VCO_DIV1_EN_UMSK (~(((1U << GLB_WIFIPLL_VCO_DIV1_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV1_EN_POS))
+#define GLB_WIFIPLL_VCO_DIV2_EN GLB_WIFIPLL_VCO_DIV2_EN
+#define GLB_WIFIPLL_VCO_DIV2_EN_POS (8U)
+#define GLB_WIFIPLL_VCO_DIV2_EN_LEN (1U)
+#define GLB_WIFIPLL_VCO_DIV2_EN_MSK (((1U << GLB_WIFIPLL_VCO_DIV2_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV2_EN_POS)
+#define GLB_WIFIPLL_VCO_DIV2_EN_UMSK (~(((1U << GLB_WIFIPLL_VCO_DIV2_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV2_EN_POS))
+#define GLB_WIFIPLL_VCO_DIV3_EN GLB_WIFIPLL_VCO_DIV3_EN
+#define GLB_WIFIPLL_VCO_DIV3_EN_POS (12U)
+#define GLB_WIFIPLL_VCO_DIV3_EN_LEN (1U)
+#define GLB_WIFIPLL_VCO_DIV3_EN_MSK (((1U << GLB_WIFIPLL_VCO_DIV3_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV3_EN_POS)
+#define GLB_WIFIPLL_VCO_DIV3_EN_UMSK (~(((1U << GLB_WIFIPLL_VCO_DIV3_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV3_EN_POS))
+
+/* 0x828 : wifi_pll_cfg6 */
+#define GLB_WIFI_PLL_CFG6_OFFSET (0x828)
+#define GLB_WIFIPLL_SDMIN GLB_WIFIPLL_SDMIN
+#define GLB_WIFIPLL_SDMIN_POS (0U)
+#define GLB_WIFIPLL_SDMIN_LEN (26U)
+#define GLB_WIFIPLL_SDMIN_MSK (((1U << GLB_WIFIPLL_SDMIN_LEN) - 1) << GLB_WIFIPLL_SDMIN_POS)
+#define GLB_WIFIPLL_SDMIN_UMSK (~(((1U << GLB_WIFIPLL_SDMIN_LEN) - 1) << GLB_WIFIPLL_SDMIN_POS))
+#define GLB_WIFIPLL_SDM_BYPASS GLB_WIFIPLL_SDM_BYPASS
+#define GLB_WIFIPLL_SDM_BYPASS_POS (28U)
+#define GLB_WIFIPLL_SDM_BYPASS_LEN (1U)
+#define GLB_WIFIPLL_SDM_BYPASS_MSK (((1U << GLB_WIFIPLL_SDM_BYPASS_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_POS)
+#define GLB_WIFIPLL_SDM_BYPASS_UMSK (~(((1U << GLB_WIFIPLL_SDM_BYPASS_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_POS))
+#define GLB_WIFIPLL_SDM_BYPASS_HW GLB_WIFIPLL_SDM_BYPASS_HW
+#define GLB_WIFIPLL_SDM_BYPASS_HW_POS (29U)
+#define GLB_WIFIPLL_SDM_BYPASS_HW_LEN (1U)
+#define GLB_WIFIPLL_SDM_BYPASS_HW_MSK (((1U << GLB_WIFIPLL_SDM_BYPASS_HW_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_HW_POS)
+#define GLB_WIFIPLL_SDM_BYPASS_HW_UMSK (~(((1U << GLB_WIFIPLL_SDM_BYPASS_HW_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_HW_POS))
+#define GLB_WIFIPLL_SDM_CTRL_HW GLB_WIFIPLL_SDM_CTRL_HW
+#define GLB_WIFIPLL_SDM_CTRL_HW_POS (31U)
+#define GLB_WIFIPLL_SDM_CTRL_HW_LEN (1U)
+#define GLB_WIFIPLL_SDM_CTRL_HW_MSK (((1U << GLB_WIFIPLL_SDM_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_SDM_CTRL_HW_POS)
+#define GLB_WIFIPLL_SDM_CTRL_HW_UMSK (~(((1U << GLB_WIFIPLL_SDM_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_SDM_CTRL_HW_POS))
+
+/* 0x82C : wifi_pll_cfg7 */
+#define GLB_WIFI_PLL_CFG7_OFFSET (0x82C)
+#define GLB_WIFIPLL_SDM_ORDER_SEL GLB_WIFIPLL_SDM_ORDER_SEL
+#define GLB_WIFIPLL_SDM_ORDER_SEL_POS (0U)
+#define GLB_WIFIPLL_SDM_ORDER_SEL_LEN (2U)
+#define GLB_WIFIPLL_SDM_ORDER_SEL_MSK (((1U << GLB_WIFIPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_ORDER_SEL_POS)
+#define GLB_WIFIPLL_SDM_ORDER_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_ORDER_SEL_POS))
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL GLB_WIFIPLL_SDM_NOI_PRBS_SEL
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_POS (4U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_LEN (2U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_MSK (((1U << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_POS)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_POS))
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN GLB_WIFIPLL_SDM_NOI_PRBS_EN
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_POS (8U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_LEN (1U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_MSK (((1U << GLB_WIFIPLL_SDM_NOI_PRBS_EN_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_EN_POS)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_UMSK (~(((1U << GLB_WIFIPLL_SDM_NOI_PRBS_EN_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_EN_POS))
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL GLB_WIFIPLL_SDM_SIG_PRBS_SEL
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_POS (12U)
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_LEN (2U)
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_MSK (((1U << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_POS)
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_POS))
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL GLB_WIFIPLL_SDM_SIG_DITH_SEL
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_POS (16U)
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_LEN (2U)
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_MSK (((1U << GLB_WIFIPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_DITH_SEL_POS)
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_DITH_SEL_POS))
+
+/* 0x830 : wifi_pll_cfg8 */
+#define GLB_WIFI_PLL_CFG8_OFFSET (0x830)
+#define GLB_WIFIPLL_EN_DIV2 GLB_WIFIPLL_EN_DIV2
+#define GLB_WIFIPLL_EN_DIV2_POS (0U)
+#define GLB_WIFIPLL_EN_DIV2_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV2_MSK (((1U << GLB_WIFIPLL_EN_DIV2_LEN) - 1) << GLB_WIFIPLL_EN_DIV2_POS)
+#define GLB_WIFIPLL_EN_DIV2_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV2_LEN) - 1) << GLB_WIFIPLL_EN_DIV2_POS))
+#define GLB_WIFIPLL_EN_DIV4 GLB_WIFIPLL_EN_DIV4
+#define GLB_WIFIPLL_EN_DIV4_POS (1U)
+#define GLB_WIFIPLL_EN_DIV4_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV4_MSK (((1U << GLB_WIFIPLL_EN_DIV4_LEN) - 1) << GLB_WIFIPLL_EN_DIV4_POS)
+#define GLB_WIFIPLL_EN_DIV4_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV4_LEN) - 1) << GLB_WIFIPLL_EN_DIV4_POS))
+#define GLB_WIFIPLL_EN_DIV5 GLB_WIFIPLL_EN_DIV5
+#define GLB_WIFIPLL_EN_DIV5_POS (2U)
+#define GLB_WIFIPLL_EN_DIV5_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV5_MSK (((1U << GLB_WIFIPLL_EN_DIV5_LEN) - 1) << GLB_WIFIPLL_EN_DIV5_POS)
+#define GLB_WIFIPLL_EN_DIV5_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV5_LEN) - 1) << GLB_WIFIPLL_EN_DIV5_POS))
+#define GLB_WIFIPLL_EN_DIV6 GLB_WIFIPLL_EN_DIV6
+#define GLB_WIFIPLL_EN_DIV6_POS (3U)
+#define GLB_WIFIPLL_EN_DIV6_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV6_MSK (((1U << GLB_WIFIPLL_EN_DIV6_LEN) - 1) << GLB_WIFIPLL_EN_DIV6_POS)
+#define GLB_WIFIPLL_EN_DIV6_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV6_LEN) - 1) << GLB_WIFIPLL_EN_DIV6_POS))
+#define GLB_WIFIPLL_EN_DIV8 GLB_WIFIPLL_EN_DIV8
+#define GLB_WIFIPLL_EN_DIV8_POS (4U)
+#define GLB_WIFIPLL_EN_DIV8_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV8_MSK (((1U << GLB_WIFIPLL_EN_DIV8_LEN) - 1) << GLB_WIFIPLL_EN_DIV8_POS)
+#define GLB_WIFIPLL_EN_DIV8_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV8_LEN) - 1) << GLB_WIFIPLL_EN_DIV8_POS))
+#define GLB_WIFIPLL_EN_DIV10 GLB_WIFIPLL_EN_DIV10
+#define GLB_WIFIPLL_EN_DIV10_POS (5U)
+#define GLB_WIFIPLL_EN_DIV10_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV10_MSK (((1U << GLB_WIFIPLL_EN_DIV10_LEN) - 1) << GLB_WIFIPLL_EN_DIV10_POS)
+#define GLB_WIFIPLL_EN_DIV10_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV10_LEN) - 1) << GLB_WIFIPLL_EN_DIV10_POS))
+#define GLB_WIFIPLL_EN_DIV12 GLB_WIFIPLL_EN_DIV12
+#define GLB_WIFIPLL_EN_DIV12_POS (6U)
+#define GLB_WIFIPLL_EN_DIV12_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV12_MSK (((1U << GLB_WIFIPLL_EN_DIV12_LEN) - 1) << GLB_WIFIPLL_EN_DIV12_POS)
+#define GLB_WIFIPLL_EN_DIV12_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV12_LEN) - 1) << GLB_WIFIPLL_EN_DIV12_POS))
+#define GLB_WIFIPLL_EN_DIV20 GLB_WIFIPLL_EN_DIV20
+#define GLB_WIFIPLL_EN_DIV20_POS (7U)
+#define GLB_WIFIPLL_EN_DIV20_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV20_MSK (((1U << GLB_WIFIPLL_EN_DIV20_LEN) - 1) << GLB_WIFIPLL_EN_DIV20_POS)
+#define GLB_WIFIPLL_EN_DIV20_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV20_LEN) - 1) << GLB_WIFIPLL_EN_DIV20_POS))
+#define GLB_WIFIPLL_EN_DIV30 GLB_WIFIPLL_EN_DIV30
+#define GLB_WIFIPLL_EN_DIV30_POS (8U)
+#define GLB_WIFIPLL_EN_DIV30_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV30_MSK (((1U << GLB_WIFIPLL_EN_DIV30_LEN) - 1) << GLB_WIFIPLL_EN_DIV30_POS)
+#define GLB_WIFIPLL_EN_DIV30_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV30_LEN) - 1) << GLB_WIFIPLL_EN_DIV30_POS))
+#define GLB_WIFIPLL_SEL_DIV2_DIV4 GLB_WIFIPLL_SEL_DIV2_DIV4
+#define GLB_WIFIPLL_SEL_DIV2_DIV4_POS (9U)
+#define GLB_WIFIPLL_SEL_DIV2_DIV4_LEN (1U)
+#define GLB_WIFIPLL_SEL_DIV2_DIV4_MSK (((1U << GLB_WIFIPLL_SEL_DIV2_DIV4_LEN) - 1) << GLB_WIFIPLL_SEL_DIV2_DIV4_POS)
+#define GLB_WIFIPLL_SEL_DIV2_DIV4_UMSK (~(((1U << GLB_WIFIPLL_SEL_DIV2_DIV4_LEN) - 1) << GLB_WIFIPLL_SEL_DIV2_DIV4_POS))
+#define GLB_EN_WIFIPLL_DIV30_BZ_ADC GLB_EN_WIFIPLL_DIV30_BZ_ADC
+#define GLB_EN_WIFIPLL_DIV30_BZ_ADC_POS (10U)
+#define GLB_EN_WIFIPLL_DIV30_BZ_ADC_LEN (1U)
+#define GLB_EN_WIFIPLL_DIV30_BZ_ADC_MSK (((1U << GLB_EN_WIFIPLL_DIV30_BZ_ADC_LEN) - 1) << GLB_EN_WIFIPLL_DIV30_BZ_ADC_POS)
+#define GLB_EN_WIFIPLL_DIV30_BZ_ADC_UMSK (~(((1U << GLB_EN_WIFIPLL_DIV30_BZ_ADC_LEN) - 1) << GLB_EN_WIFIPLL_DIV30_BZ_ADC_POS))
+#define GLB_WIFIPLL_EN_DIV2_HW GLB_WIFIPLL_EN_DIV2_HW
+#define GLB_WIFIPLL_EN_DIV2_HW_POS (12U)
+#define GLB_WIFIPLL_EN_DIV2_HW_LEN (1U)
+#define GLB_WIFIPLL_EN_DIV2_HW_MSK (((1U << GLB_WIFIPLL_EN_DIV2_HW_LEN) - 1) << GLB_WIFIPLL_EN_DIV2_HW_POS)
+#define GLB_WIFIPLL_EN_DIV2_HW_UMSK (~(((1U << GLB_WIFIPLL_EN_DIV2_HW_LEN) - 1) << GLB_WIFIPLL_EN_DIV2_HW_POS))
+#define GLB_WIFIPLL_EN_CTRL_HW GLB_WIFIPLL_EN_CTRL_HW
+#define GLB_WIFIPLL_EN_CTRL_HW_POS (31U)
+#define GLB_WIFIPLL_EN_CTRL_HW_LEN (1U)
+#define GLB_WIFIPLL_EN_CTRL_HW_MSK (((1U << GLB_WIFIPLL_EN_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_EN_CTRL_HW_POS)
+#define GLB_WIFIPLL_EN_CTRL_HW_UMSK (~(((1U << GLB_WIFIPLL_EN_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_EN_CTRL_HW_POS))
+
+/* 0x834 : wifi_pll_cfg9 */
+#define GLB_WIFI_PLL_CFG9_OFFSET (0x834)
+#define GLB_WIFIPLL_DC_TP_OUT_EN GLB_WIFIPLL_DC_TP_OUT_EN
+#define GLB_WIFIPLL_DC_TP_OUT_EN_POS (0U)
+#define GLB_WIFIPLL_DC_TP_OUT_EN_LEN (1U)
+#define GLB_WIFIPLL_DC_TP_OUT_EN_MSK (((1U << GLB_WIFIPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_WIFIPLL_DC_TP_OUT_EN_POS)
+#define GLB_WIFIPLL_DC_TP_OUT_EN_UMSK (~(((1U << GLB_WIFIPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_WIFIPLL_DC_TP_OUT_EN_POS))
+#define GLB_TEN_WIFIPLL GLB_TEN_WIFIPLL
+#define GLB_TEN_WIFIPLL_POS (1U)
+#define GLB_TEN_WIFIPLL_LEN (1U)
+#define GLB_TEN_WIFIPLL_MSK (((1U << GLB_TEN_WIFIPLL_LEN) - 1) << GLB_TEN_WIFIPLL_POS)
+#define GLB_TEN_WIFIPLL_UMSK (~(((1U << GLB_TEN_WIFIPLL_LEN) - 1) << GLB_TEN_WIFIPLL_POS))
+#define GLB_TEN_WIFIPLL_SFREG GLB_TEN_WIFIPLL_SFREG
+#define GLB_TEN_WIFIPLL_SFREG_POS (2U)
+#define GLB_TEN_WIFIPLL_SFREG_LEN (1U)
+#define GLB_TEN_WIFIPLL_SFREG_MSK (((1U << GLB_TEN_WIFIPLL_SFREG_LEN) - 1) << GLB_TEN_WIFIPLL_SFREG_POS)
+#define GLB_TEN_WIFIPLL_SFREG_UMSK (~(((1U << GLB_TEN_WIFIPLL_SFREG_LEN) - 1) << GLB_TEN_WIFIPLL_SFREG_POS))
+#define GLB_DTEN_WIFIPLL_FIN GLB_DTEN_WIFIPLL_FIN
+#define GLB_DTEN_WIFIPLL_FIN_POS (4U)
+#define GLB_DTEN_WIFIPLL_FIN_LEN (1U)
+#define GLB_DTEN_WIFIPLL_FIN_MSK (((1U << GLB_DTEN_WIFIPLL_FIN_LEN) - 1) << GLB_DTEN_WIFIPLL_FIN_POS)
+#define GLB_DTEN_WIFIPLL_FIN_UMSK (~(((1U << GLB_DTEN_WIFIPLL_FIN_LEN) - 1) << GLB_DTEN_WIFIPLL_FIN_POS))
+#define GLB_DTEN_WIFIPLL_FREF GLB_DTEN_WIFIPLL_FREF
+#define GLB_DTEN_WIFIPLL_FREF_POS (5U)
+#define GLB_DTEN_WIFIPLL_FREF_LEN (1U)
+#define GLB_DTEN_WIFIPLL_FREF_MSK (((1U << GLB_DTEN_WIFIPLL_FREF_LEN) - 1) << GLB_DTEN_WIFIPLL_FREF_POS)
+#define GLB_DTEN_WIFIPLL_FREF_UMSK (~(((1U << GLB_DTEN_WIFIPLL_FREF_LEN) - 1) << GLB_DTEN_WIFIPLL_FREF_POS))
+#define GLB_DTEN_WIFIPLL_FSDM GLB_DTEN_WIFIPLL_FSDM
+#define GLB_DTEN_WIFIPLL_FSDM_POS (6U)
+#define GLB_DTEN_WIFIPLL_FSDM_LEN (1U)
+#define GLB_DTEN_WIFIPLL_FSDM_MSK (((1U << GLB_DTEN_WIFIPLL_FSDM_LEN) - 1) << GLB_DTEN_WIFIPLL_FSDM_POS)
+#define GLB_DTEN_WIFIPLL_FSDM_UMSK (~(((1U << GLB_DTEN_WIFIPLL_FSDM_LEN) - 1) << GLB_DTEN_WIFIPLL_FSDM_POS))
+#define GLB_DTEN_WIFIPLL_DIV30 GLB_DTEN_WIFIPLL_DIV30
+#define GLB_DTEN_WIFIPLL_DIV30_POS (7U)
+#define GLB_DTEN_WIFIPLL_DIV30_LEN (1U)
+#define GLB_DTEN_WIFIPLL_DIV30_MSK (((1U << GLB_DTEN_WIFIPLL_DIV30_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV30_POS)
+#define GLB_DTEN_WIFIPLL_DIV30_UMSK (~(((1U << GLB_DTEN_WIFIPLL_DIV30_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV30_POS))
+#define GLB_DTEN_WIFIPLL_DIV10 GLB_DTEN_WIFIPLL_DIV10
+#define GLB_DTEN_WIFIPLL_DIV10_POS (8U)
+#define GLB_DTEN_WIFIPLL_DIV10_LEN (1U)
+#define GLB_DTEN_WIFIPLL_DIV10_MSK (((1U << GLB_DTEN_WIFIPLL_DIV10_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV10_POS)
+#define GLB_DTEN_WIFIPLL_DIV10_UMSK (~(((1U << GLB_DTEN_WIFIPLL_DIV10_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV10_POS))
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK GLB_DTEN_WIFIPLL_POSTDIV_CLK
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_POS (9U)
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_LEN (1U)
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_MSK (((1U << GLB_DTEN_WIFIPLL_POSTDIV_CLK_LEN) - 1) << GLB_DTEN_WIFIPLL_POSTDIV_CLK_POS)
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_UMSK (~(((1U << GLB_DTEN_WIFIPLL_POSTDIV_CLK_LEN) - 1) << GLB_DTEN_WIFIPLL_POSTDIV_CLK_POS))
+#define GLB_USBPLL_DTEST_PCLK_EN GLB_USBPLL_DTEST_PCLK_EN
+#define GLB_USBPLL_DTEST_PCLK_EN_POS (10U)
+#define GLB_USBPLL_DTEST_PCLK_EN_LEN (1U)
+#define GLB_USBPLL_DTEST_PCLK_EN_MSK (((1U << GLB_USBPLL_DTEST_PCLK_EN_LEN) - 1) << GLB_USBPLL_DTEST_PCLK_EN_POS)
+#define GLB_USBPLL_DTEST_PCLK_EN_UMSK (~(((1U << GLB_USBPLL_DTEST_PCLK_EN_LEN) - 1) << GLB_USBPLL_DTEST_PCLK_EN_POS))
+#define GLB_USBPLL_DTEST_CLKOUT_EN GLB_USBPLL_DTEST_CLKOUT_EN
+#define GLB_USBPLL_DTEST_CLKOUT_EN_POS (11U)
+#define GLB_USBPLL_DTEST_CLKOUT_EN_LEN (1U)
+#define GLB_USBPLL_DTEST_CLKOUT_EN_MSK (((1U << GLB_USBPLL_DTEST_CLKOUT_EN_LEN) - 1) << GLB_USBPLL_DTEST_CLKOUT_EN_POS)
+#define GLB_USBPLL_DTEST_CLKOUT_EN_UMSK (~(((1U << GLB_USBPLL_DTEST_CLKOUT_EN_LEN) - 1) << GLB_USBPLL_DTEST_CLKOUT_EN_POS))
+#define GLB_DTEST_WIFIPLL_PULLDOWN GLB_DTEST_WIFIPLL_PULLDOWN
+#define GLB_DTEST_WIFIPLL_PULLDOWN_POS (12U)
+#define GLB_DTEST_WIFIPLL_PULLDOWN_LEN (1U)
+#define GLB_DTEST_WIFIPLL_PULLDOWN_MSK (((1U << GLB_DTEST_WIFIPLL_PULLDOWN_LEN) - 1) << GLB_DTEST_WIFIPLL_PULLDOWN_POS)
+#define GLB_DTEST_WIFIPLL_PULLDOWN_UMSK (~(((1U << GLB_DTEST_WIFIPLL_PULLDOWN_LEN) - 1) << GLB_DTEST_WIFIPLL_PULLDOWN_POS))
+
+/* 0x838 : wifi_pll_cfg10 */
+#define GLB_WIFI_PLL_CFG10_OFFSET (0x838)
+#define GLB_USBPLL_SSC_START GLB_USBPLL_SSC_START
+#define GLB_USBPLL_SSC_START_POS (2U)
+#define GLB_USBPLL_SSC_START_LEN (1U)
+#define GLB_USBPLL_SSC_START_MSK (((1U << GLB_USBPLL_SSC_START_LEN) - 1) << GLB_USBPLL_SSC_START_POS)
+#define GLB_USBPLL_SSC_START_UMSK (~(((1U << GLB_USBPLL_SSC_START_LEN) - 1) << GLB_USBPLL_SSC_START_POS))
+#define GLB_USBPLL_SSC_START_GATE_EN GLB_USBPLL_SSC_START_GATE_EN
+#define GLB_USBPLL_SSC_START_GATE_EN_POS (3U)
+#define GLB_USBPLL_SSC_START_GATE_EN_LEN (1U)
+#define GLB_USBPLL_SSC_START_GATE_EN_MSK (((1U << GLB_USBPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_USBPLL_SSC_START_GATE_EN_POS)
+#define GLB_USBPLL_SSC_START_GATE_EN_UMSK (~(((1U << GLB_USBPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_USBPLL_SSC_START_GATE_EN_POS))
+#define GLB_USBPLL_SSC_GAIN GLB_USBPLL_SSC_GAIN
+#define GLB_USBPLL_SSC_GAIN_POS (4U)
+#define GLB_USBPLL_SSC_GAIN_LEN (3U)
+#define GLB_USBPLL_SSC_GAIN_MSK (((1U << GLB_USBPLL_SSC_GAIN_LEN) - 1) << GLB_USBPLL_SSC_GAIN_POS)
+#define GLB_USBPLL_SSC_GAIN_UMSK (~(((1U << GLB_USBPLL_SSC_GAIN_LEN) - 1) << GLB_USBPLL_SSC_GAIN_POS))
+#define GLB_USBPLL_SSC_EN GLB_USBPLL_SSC_EN
+#define GLB_USBPLL_SSC_EN_POS (8U)
+#define GLB_USBPLL_SSC_EN_LEN (1U)
+#define GLB_USBPLL_SSC_EN_MSK (((1U << GLB_USBPLL_SSC_EN_LEN) - 1) << GLB_USBPLL_SSC_EN_POS)
+#define GLB_USBPLL_SSC_EN_UMSK (~(((1U << GLB_USBPLL_SSC_EN_LEN) - 1) << GLB_USBPLL_SSC_EN_POS))
+#define GLB_USBPLL_SDM_BYPASS GLB_USBPLL_SDM_BYPASS
+#define GLB_USBPLL_SDM_BYPASS_POS (9U)
+#define GLB_USBPLL_SDM_BYPASS_LEN (1U)
+#define GLB_USBPLL_SDM_BYPASS_MSK (((1U << GLB_USBPLL_SDM_BYPASS_LEN) - 1) << GLB_USBPLL_SDM_BYPASS_POS)
+#define GLB_USBPLL_SDM_BYPASS_UMSK (~(((1U << GLB_USBPLL_SDM_BYPASS_LEN) - 1) << GLB_USBPLL_SDM_BYPASS_POS))
+#define GLB_USBPLL_SDM_ORDER_SEL GLB_USBPLL_SDM_ORDER_SEL
+#define GLB_USBPLL_SDM_ORDER_SEL_POS (10U)
+#define GLB_USBPLL_SDM_ORDER_SEL_LEN (1U)
+#define GLB_USBPLL_SDM_ORDER_SEL_MSK (((1U << GLB_USBPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_USBPLL_SDM_ORDER_SEL_POS)
+#define GLB_USBPLL_SDM_ORDER_SEL_UMSK (~(((1U << GLB_USBPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_USBPLL_SDM_ORDER_SEL_POS))
+#define GLB_USBPLL_SDM_SIG_DITH_SEL GLB_USBPLL_SDM_SIG_DITH_SEL
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_POS (16U)
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_LEN (2U)
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_MSK (((1U << GLB_USBPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_USBPLL_SDM_SIG_DITH_SEL_POS)
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_UMSK (~(((1U << GLB_USBPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_USBPLL_SDM_SIG_DITH_SEL_POS))
+#define GLB_USBPLL_DIV2_EN GLB_USBPLL_DIV2_EN
+#define GLB_USBPLL_DIV2_EN_POS (20U)
+#define GLB_USBPLL_DIV2_EN_LEN (1U)
+#define GLB_USBPLL_DIV2_EN_MSK (((1U << GLB_USBPLL_DIV2_EN_LEN) - 1) << GLB_USBPLL_DIV2_EN_POS)
+#define GLB_USBPLL_DIV2_EN_UMSK (~(((1U << GLB_USBPLL_DIV2_EN_LEN) - 1) << GLB_USBPLL_DIV2_EN_POS))
+#define GLB_USBPLL_CLKOUT_EN GLB_USBPLL_CLKOUT_EN
+#define GLB_USBPLL_CLKOUT_EN_POS (21U)
+#define GLB_USBPLL_CLKOUT_EN_LEN (1U)
+#define GLB_USBPLL_CLKOUT_EN_MSK (((1U << GLB_USBPLL_CLKOUT_EN_LEN) - 1) << GLB_USBPLL_CLKOUT_EN_POS)
+#define GLB_USBPLL_CLKOUT_EN_UMSK (~(((1U << GLB_USBPLL_CLKOUT_EN_LEN) - 1) << GLB_USBPLL_CLKOUT_EN_POS))
+#define GLB_USBPLL_SEL_SAMPLE_CLK GLB_USBPLL_SEL_SAMPLE_CLK
+#define GLB_USBPLL_SEL_SAMPLE_CLK_POS (24U)
+#define GLB_USBPLL_SEL_SAMPLE_CLK_LEN (2U)
+#define GLB_USBPLL_SEL_SAMPLE_CLK_MSK (((1U << GLB_USBPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_USBPLL_SEL_SAMPLE_CLK_POS)
+#define GLB_USBPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << GLB_USBPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_USBPLL_SEL_SAMPLE_CLK_POS))
+#define GLB_USBPLL_RSTB GLB_USBPLL_RSTB
+#define GLB_USBPLL_RSTB_POS (28U)
+#define GLB_USBPLL_RSTB_LEN (1U)
+#define GLB_USBPLL_RSTB_MSK (((1U << GLB_USBPLL_RSTB_LEN) - 1) << GLB_USBPLL_RSTB_POS)
+#define GLB_USBPLL_RSTB_UMSK (~(((1U << GLB_USBPLL_RSTB_LEN) - 1) << GLB_USBPLL_RSTB_POS))
+#define GLB_PU_USBPLL_MMDIV GLB_PU_USBPLL_MMDIV
+#define GLB_PU_USBPLL_MMDIV_POS (29U)
+#define GLB_PU_USBPLL_MMDIV_LEN (1U)
+#define GLB_PU_USBPLL_MMDIV_MSK (((1U << GLB_PU_USBPLL_MMDIV_LEN) - 1) << GLB_PU_USBPLL_MMDIV_POS)
+#define GLB_PU_USBPLL_MMDIV_UMSK (~(((1U << GLB_PU_USBPLL_MMDIV_LEN) - 1) << GLB_PU_USBPLL_MMDIV_POS))
+
+/* 0x83C : wifi_pll_cfg11 */
+#define GLB_WIFI_PLL_CFG11_OFFSET (0x83C)
+#define GLB_USBPLL_SDMIN GLB_USBPLL_SDMIN
+#define GLB_USBPLL_SDMIN_POS (0U)
+#define GLB_USBPLL_SDMIN_LEN (19U)
+#define GLB_USBPLL_SDMIN_MSK (((1U << GLB_USBPLL_SDMIN_LEN) - 1) << GLB_USBPLL_SDMIN_POS)
+#define GLB_USBPLL_SDMIN_UMSK (~(((1U << GLB_USBPLL_SDMIN_LEN) - 1) << GLB_USBPLL_SDMIN_POS))
+
+/* 0x840 : wifi_pll_cfg12 */
+#define GLB_WIFI_PLL_CFG12_OFFSET (0x840)
+#define GLB_USBPLL_SSC_CNT GLB_USBPLL_SSC_CNT
+#define GLB_USBPLL_SSC_CNT_POS (0U)
+#define GLB_USBPLL_SSC_CNT_LEN (9U)
+#define GLB_USBPLL_SSC_CNT_MSK (((1U << GLB_USBPLL_SSC_CNT_LEN) - 1) << GLB_USBPLL_SSC_CNT_POS)
+#define GLB_USBPLL_SSC_CNT_UMSK (~(((1U << GLB_USBPLL_SSC_CNT_LEN) - 1) << GLB_USBPLL_SSC_CNT_POS))
+
+/* 0x844 : wifi_pll_cfg13 */
+#define GLB_WIFI_PLL_CFG13_OFFSET (0x844)
+#define GLB_WIFIPLL_RESV GLB_WIFIPLL_RESV
+#define GLB_WIFIPLL_RESV_POS (0U)
+#define GLB_WIFIPLL_RESV_LEN (16U)
+#define GLB_WIFIPLL_RESV_MSK (((1U << GLB_WIFIPLL_RESV_LEN) - 1) << GLB_WIFIPLL_RESV_POS)
+#define GLB_WIFIPLL_RESV_UMSK (~(((1U << GLB_WIFIPLL_RESV_LEN) - 1) << GLB_WIFIPLL_RESV_POS))
+#define GLB_USBPLL_DL_CTRL GLB_USBPLL_DL_CTRL
+#define GLB_USBPLL_DL_CTRL_POS (21U)
+#define GLB_USBPLL_DL_CTRL_LEN (1U)
+#define GLB_USBPLL_DL_CTRL_MSK (((1U << GLB_USBPLL_DL_CTRL_LEN) - 1) << GLB_USBPLL_DL_CTRL_POS)
+#define GLB_USBPLL_DL_CTRL_UMSK (~(((1U << GLB_USBPLL_DL_CTRL_LEN) - 1) << GLB_USBPLL_DL_CTRL_POS))
+#define GLB_WIFIPLL_DL_CTRL_30_BZ_ADC GLB_WIFIPLL_DL_CTRL_30_BZ_ADC
+#define GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_POS (22U)
+#define GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_MSK (((1U << GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_POS)
+#define GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_30_BZ_ADC_POS))
+#define GLB_WIFIPLL_DL_CTRL_30 GLB_WIFIPLL_DL_CTRL_30
+#define GLB_WIFIPLL_DL_CTRL_30_POS (23U)
+#define GLB_WIFIPLL_DL_CTRL_30_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_30_MSK (((1U << GLB_WIFIPLL_DL_CTRL_30_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_30_POS)
+#define GLB_WIFIPLL_DL_CTRL_30_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_30_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_30_POS))
+#define GLB_WIFIPLL_DL_CTRL_20 GLB_WIFIPLL_DL_CTRL_20
+#define GLB_WIFIPLL_DL_CTRL_20_POS (24U)
+#define GLB_WIFIPLL_DL_CTRL_20_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_20_MSK (((1U << GLB_WIFIPLL_DL_CTRL_20_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_20_POS)
+#define GLB_WIFIPLL_DL_CTRL_20_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_20_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_20_POS))
+#define GLB_WIFIPLL_DL_CTRL_12 GLB_WIFIPLL_DL_CTRL_12
+#define GLB_WIFIPLL_DL_CTRL_12_POS (25U)
+#define GLB_WIFIPLL_DL_CTRL_12_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_12_MSK (((1U << GLB_WIFIPLL_DL_CTRL_12_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_12_POS)
+#define GLB_WIFIPLL_DL_CTRL_12_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_12_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_12_POS))
+#define GLB_WIFIPLL_DL_CTRL_10 GLB_WIFIPLL_DL_CTRL_10
+#define GLB_WIFIPLL_DL_CTRL_10_POS (26U)
+#define GLB_WIFIPLL_DL_CTRL_10_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_10_MSK (((1U << GLB_WIFIPLL_DL_CTRL_10_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_10_POS)
+#define GLB_WIFIPLL_DL_CTRL_10_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_10_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_10_POS))
+#define GLB_WIFIPLL_DL_CTRL_8 GLB_WIFIPLL_DL_CTRL_8
+#define GLB_WIFIPLL_DL_CTRL_8_POS (27U)
+#define GLB_WIFIPLL_DL_CTRL_8_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_8_MSK (((1U << GLB_WIFIPLL_DL_CTRL_8_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_8_POS)
+#define GLB_WIFIPLL_DL_CTRL_8_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_8_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_8_POS))
+#define GLB_WIFIPLL_DL_CTRL_6 GLB_WIFIPLL_DL_CTRL_6
+#define GLB_WIFIPLL_DL_CTRL_6_POS (28U)
+#define GLB_WIFIPLL_DL_CTRL_6_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_6_MSK (((1U << GLB_WIFIPLL_DL_CTRL_6_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_6_POS)
+#define GLB_WIFIPLL_DL_CTRL_6_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_6_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_6_POS))
+#define GLB_WIFIPLL_DL_CTRL_5 GLB_WIFIPLL_DL_CTRL_5
+#define GLB_WIFIPLL_DL_CTRL_5_POS (29U)
+#define GLB_WIFIPLL_DL_CTRL_5_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_5_MSK (((1U << GLB_WIFIPLL_DL_CTRL_5_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_5_POS)
+#define GLB_WIFIPLL_DL_CTRL_5_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_5_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_5_POS))
+#define GLB_WIFIPLL_DL_CTRL_4 GLB_WIFIPLL_DL_CTRL_4
+#define GLB_WIFIPLL_DL_CTRL_4_POS (30U)
+#define GLB_WIFIPLL_DL_CTRL_4_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_4_MSK (((1U << GLB_WIFIPLL_DL_CTRL_4_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_4_POS)
+#define GLB_WIFIPLL_DL_CTRL_4_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_4_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_4_POS))
+#define GLB_WIFIPLL_DL_CTRL_2 GLB_WIFIPLL_DL_CTRL_2
+#define GLB_WIFIPLL_DL_CTRL_2_POS (31U)
+#define GLB_WIFIPLL_DL_CTRL_2_LEN (1U)
+#define GLB_WIFIPLL_DL_CTRL_2_MSK (((1U << GLB_WIFIPLL_DL_CTRL_2_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_2_POS)
+#define GLB_WIFIPLL_DL_CTRL_2_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_2_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_2_POS))
+
+/* 0x8A4 : gauge */
+#define GLB_GAUGE_OFFSET (0x8A4)
+#define GLB_GAUGE_RESERVE GLB_GAUGE_RESERVE
+#define GLB_GAUGE_RESERVE_POS (0U)
+#define GLB_GAUGE_RESERVE_LEN (3U)
+#define GLB_GAUGE_RESERVE_MSK (((1U << GLB_GAUGE_RESERVE_LEN) - 1) << GLB_GAUGE_RESERVE_POS)
+#define GLB_GAUGE_RESERVE_UMSK (~(((1U << GLB_GAUGE_RESERVE_LEN) - 1) << GLB_GAUGE_RESERVE_POS))
+#define GLB_GAUGE_ICTRL_ADC GLB_GAUGE_ICTRL_ADC
+#define GLB_GAUGE_ICTRL_ADC_POS (3U)
+#define GLB_GAUGE_ICTRL_ADC_LEN (2U)
+#define GLB_GAUGE_ICTRL_ADC_MSK (((1U << GLB_GAUGE_ICTRL_ADC_LEN) - 1) << GLB_GAUGE_ICTRL_ADC_POS)
+#define GLB_GAUGE_ICTRL_ADC_UMSK (~(((1U << GLB_GAUGE_ICTRL_ADC_LEN) - 1) << GLB_GAUGE_ICTRL_ADC_POS))
+#define GLB_GAUGE_DEM_EN GLB_GAUGE_DEM_EN
+#define GLB_GAUGE_DEM_EN_POS (5U)
+#define GLB_GAUGE_DEM_EN_LEN (1U)
+#define GLB_GAUGE_DEM_EN_MSK (((1U << GLB_GAUGE_DEM_EN_LEN) - 1) << GLB_GAUGE_DEM_EN_POS)
+#define GLB_GAUGE_DEM_EN_UMSK (~(((1U << GLB_GAUGE_DEM_EN_LEN) - 1) << GLB_GAUGE_DEM_EN_POS))
+#define GLB_GAUGE_CKB_EN GLB_GAUGE_CKB_EN
+#define GLB_GAUGE_CKB_EN_POS (6U)
+#define GLB_GAUGE_CKB_EN_LEN (1U)
+#define GLB_GAUGE_CKB_EN_MSK (((1U << GLB_GAUGE_CKB_EN_LEN) - 1) << GLB_GAUGE_CKB_EN_POS)
+#define GLB_GAUGE_CKB_EN_UMSK (~(((1U << GLB_GAUGE_CKB_EN_LEN) - 1) << GLB_GAUGE_CKB_EN_POS))
+#define GLB_GAUGE_CHOP_PHAS GLB_GAUGE_CHOP_PHAS
+#define GLB_GAUGE_CHOP_PHAS_POS (7U)
+#define GLB_GAUGE_CHOP_PHAS_LEN (1U)
+#define GLB_GAUGE_CHOP_PHAS_MSK (((1U << GLB_GAUGE_CHOP_PHAS_LEN) - 1) << GLB_GAUGE_CHOP_PHAS_POS)
+#define GLB_GAUGE_CHOP_PHAS_UMSK (~(((1U << GLB_GAUGE_CHOP_PHAS_LEN) - 1) << GLB_GAUGE_CHOP_PHAS_POS))
+#define GLB_GAUGE_CHOP_FREQ GLB_GAUGE_CHOP_FREQ
+#define GLB_GAUGE_CHOP_FREQ_POS (8U)
+#define GLB_GAUGE_CHOP_FREQ_LEN (3U)
+#define GLB_GAUGE_CHOP_FREQ_MSK (((1U << GLB_GAUGE_CHOP_FREQ_LEN) - 1) << GLB_GAUGE_CHOP_FREQ_POS)
+#define GLB_GAUGE_CHOP_FREQ_UMSK (~(((1U << GLB_GAUGE_CHOP_FREQ_LEN) - 1) << GLB_GAUGE_CHOP_FREQ_POS))
+#define GLB_GAUGE_CHOP_EN GLB_GAUGE_CHOP_EN
+#define GLB_GAUGE_CHOP_EN_POS (11U)
+#define GLB_GAUGE_CHOP_EN_LEN (1U)
+#define GLB_GAUGE_CHOP_EN_MSK (((1U << GLB_GAUGE_CHOP_EN_LEN) - 1) << GLB_GAUGE_CHOP_EN_POS)
+#define GLB_GAUGE_CHOP_EN_UMSK (~(((1U << GLB_GAUGE_CHOP_EN_LEN) - 1) << GLB_GAUGE_CHOP_EN_POS))
+#define GLB_GAUGE_SEL_EDGE GLB_GAUGE_SEL_EDGE
+#define GLB_GAUGE_SEL_EDGE_POS (12U)
+#define GLB_GAUGE_SEL_EDGE_LEN (1U)
+#define GLB_GAUGE_SEL_EDGE_MSK (((1U << GLB_GAUGE_SEL_EDGE_LEN) - 1) << GLB_GAUGE_SEL_EDGE_POS)
+#define GLB_GAUGE_SEL_EDGE_UMSK (~(((1U << GLB_GAUGE_SEL_EDGE_LEN) - 1) << GLB_GAUGE_SEL_EDGE_POS))
+#define GLB_GAUGE_QUAN_GAIN GLB_GAUGE_QUAN_GAIN
+#define GLB_GAUGE_QUAN_GAIN_POS (13U)
+#define GLB_GAUGE_QUAN_GAIN_LEN (2U)
+#define GLB_GAUGE_QUAN_GAIN_MSK (((1U << GLB_GAUGE_QUAN_GAIN_LEN) - 1) << GLB_GAUGE_QUAN_GAIN_POS)
+#define GLB_GAUGE_QUAN_GAIN_UMSK (~(((1U << GLB_GAUGE_QUAN_GAIN_LEN) - 1) << GLB_GAUGE_QUAN_GAIN_POS))
+#define GLB_GAUGE_SDM_PU GLB_GAUGE_SDM_PU
+#define GLB_GAUGE_SDM_PU_POS (15U)
+#define GLB_GAUGE_SDM_PU_LEN (1U)
+#define GLB_GAUGE_SDM_PU_MSK (((1U << GLB_GAUGE_SDM_PU_LEN) - 1) << GLB_GAUGE_SDM_PU_POS)
+#define GLB_GAUGE_SDM_PU_UMSK (~(((1U << GLB_GAUGE_SDM_PU_LEN) - 1) << GLB_GAUGE_SDM_PU_POS))
+#define GLB_GAUGE_CHANNEL_SEL GLB_GAUGE_CHANNEL_SEL
+#define GLB_GAUGE_CHANNEL_SEL_POS (16U)
+#define GLB_GAUGE_CHANNEL_SEL_LEN (1U)
+#define GLB_GAUGE_CHANNEL_SEL_MSK (((1U << GLB_GAUGE_CHANNEL_SEL_LEN) - 1) << GLB_GAUGE_CHANNEL_SEL_POS)
+#define GLB_GAUGE_CHANNEL_SEL_UMSK (~(((1U << GLB_GAUGE_CHANNEL_SEL_LEN) - 1) << GLB_GAUGE_CHANNEL_SEL_POS))
+#define GLB_GAUGE_CHANNEL_EN GLB_GAUGE_CHANNEL_EN
+#define GLB_GAUGE_CHANNEL_EN_POS (17U)
+#define GLB_GAUGE_CHANNEL_EN_LEN (1U)
+#define GLB_GAUGE_CHANNEL_EN_MSK (((1U << GLB_GAUGE_CHANNEL_EN_LEN) - 1) << GLB_GAUGE_CHANNEL_EN_POS)
+#define GLB_GAUGE_CHANNEL_EN_UMSK (~(((1U << GLB_GAUGE_CHANNEL_EN_LEN) - 1) << GLB_GAUGE_CHANNEL_EN_POS))
+#define GLB_GAUGE_LP_MODE GLB_GAUGE_LP_MODE
+#define GLB_GAUGE_LP_MODE_POS (18U)
+#define GLB_GAUGE_LP_MODE_LEN (1U)
+#define GLB_GAUGE_LP_MODE_MSK (((1U << GLB_GAUGE_LP_MODE_LEN) - 1) << GLB_GAUGE_LP_MODE_POS)
+#define GLB_GAUGE_LP_MODE_UMSK (~(((1U << GLB_GAUGE_LP_MODE_LEN) - 1) << GLB_GAUGE_LP_MODE_POS))
+#define GLB_TMUX_GAUGE_POWER GLB_TMUX_GAUGE_POWER
+#define GLB_TMUX_GAUGE_POWER_POS (20U)
+#define GLB_TMUX_GAUGE_POWER_LEN (3U)
+#define GLB_TMUX_GAUGE_POWER_MSK (((1U << GLB_TMUX_GAUGE_POWER_LEN) - 1) << GLB_TMUX_GAUGE_POWER_POS)
+#define GLB_TMUX_GAUGE_POWER_UMSK (~(((1U << GLB_TMUX_GAUGE_POWER_LEN) - 1) << GLB_TMUX_GAUGE_POWER_POS))
+#define GLB_TEN_GAUGE_POWER GLB_TEN_GAUGE_POWER
+#define GLB_TEN_GAUGE_POWER_POS (23U)
+#define GLB_TEN_GAUGE_POWER_LEN (1U)
+#define GLB_TEN_GAUGE_POWER_MSK (((1U << GLB_TEN_GAUGE_POWER_LEN) - 1) << GLB_TEN_GAUGE_POWER_POS)
+#define GLB_TEN_GAUGE_POWER_UMSK (~(((1U << GLB_TEN_GAUGE_POWER_LEN) - 1) << GLB_TEN_GAUGE_POWER_POS))
+#define GLB_NTC_BIAS_SEL GLB_NTC_BIAS_SEL
+#define GLB_NTC_BIAS_SEL_POS (24U)
+#define GLB_NTC_BIAS_SEL_LEN (4U)
+#define GLB_NTC_BIAS_SEL_MSK (((1U << GLB_NTC_BIAS_SEL_LEN) - 1) << GLB_NTC_BIAS_SEL_POS)
+#define GLB_NTC_BIAS_SEL_UMSK (~(((1U << GLB_NTC_BIAS_SEL_LEN) - 1) << GLB_NTC_BIAS_SEL_POS))
+#define GLB_NTC_BIAS_EN GLB_NTC_BIAS_EN
+#define GLB_NTC_BIAS_EN_POS (28U)
+#define GLB_NTC_BIAS_EN_LEN (1U)
+#define GLB_NTC_BIAS_EN_MSK (((1U << GLB_NTC_BIAS_EN_LEN) - 1) << GLB_NTC_BIAS_EN_POS)
+#define GLB_NTC_BIAS_EN_UMSK (~(((1U << GLB_NTC_BIAS_EN_LEN) - 1) << GLB_NTC_BIAS_EN_POS))
+#define GLB_GAUGE_LDO_PU GLB_GAUGE_LDO_PU
+#define GLB_GAUGE_LDO_PU_POS (29U)
+#define GLB_GAUGE_LDO_PU_LEN (1U)
+#define GLB_GAUGE_LDO_PU_MSK (((1U << GLB_GAUGE_LDO_PU_LEN) - 1) << GLB_GAUGE_LDO_PU_POS)
+#define GLB_GAUGE_LDO_PU_UMSK (~(((1U << GLB_GAUGE_LDO_PU_LEN) - 1) << GLB_GAUGE_LDO_PU_POS))
+#define GLB_GAUGE_VCM_PU GLB_GAUGE_VCM_PU
+#define GLB_GAUGE_VCM_PU_POS (30U)
+#define GLB_GAUGE_VCM_PU_LEN (1U)
+#define GLB_GAUGE_VCM_PU_MSK (((1U << GLB_GAUGE_VCM_PU_LEN) - 1) << GLB_GAUGE_VCM_PU_POS)
+#define GLB_GAUGE_VCM_PU_UMSK (~(((1U << GLB_GAUGE_VCM_PU_LEN) - 1) << GLB_GAUGE_VCM_PU_POS))
+#define GLB_GAUGE_BG_PU GLB_GAUGE_BG_PU
+#define GLB_GAUGE_BG_PU_POS (31U)
+#define GLB_GAUGE_BG_PU_LEN (1U)
+#define GLB_GAUGE_BG_PU_MSK (((1U << GLB_GAUGE_BG_PU_LEN) - 1) << GLB_GAUGE_BG_PU_POS)
+#define GLB_GAUGE_BG_PU_UMSK (~(((1U << GLB_GAUGE_BG_PU_LEN) - 1) << GLB_GAUGE_BG_PU_POS))
+
+/* 0x8B8 : gauge_rx_fifo_ctrl */
+#define GLB_GAUGE_RX_FIFO_CTRL_OFFSET (0x8B8)
+#define GLB_GAUGE_RX_FIFO_FLUSH GLB_GAUGE_RX_FIFO_FLUSH
+#define GLB_GAUGE_RX_FIFO_FLUSH_POS (0U)
+#define GLB_GAUGE_RX_FIFO_FLUSH_LEN (1U)
+#define GLB_GAUGE_RX_FIFO_FLUSH_MSK (((1U << GLB_GAUGE_RX_FIFO_FLUSH_LEN) - 1) << GLB_GAUGE_RX_FIFO_FLUSH_POS)
+#define GLB_GAUGE_RX_FIFO_FLUSH_UMSK (~(((1U << GLB_GAUGE_RX_FIFO_FLUSH_LEN) - 1) << GLB_GAUGE_RX_FIFO_FLUSH_POS))
+#define GLB_GAUGE_RXO_INT_EN GLB_GAUGE_RXO_INT_EN
+#define GLB_GAUGE_RXO_INT_EN_POS (1U)
+#define GLB_GAUGE_RXO_INT_EN_LEN (1U)
+#define GLB_GAUGE_RXO_INT_EN_MSK (((1U << GLB_GAUGE_RXO_INT_EN_LEN) - 1) << GLB_GAUGE_RXO_INT_EN_POS)
+#define GLB_GAUGE_RXO_INT_EN_UMSK (~(((1U << GLB_GAUGE_RXO_INT_EN_LEN) - 1) << GLB_GAUGE_RXO_INT_EN_POS))
+#define GLB_GAUGE_RXU_INT_EN GLB_GAUGE_RXU_INT_EN
+#define GLB_GAUGE_RXU_INT_EN_POS (2U)
+#define GLB_GAUGE_RXU_INT_EN_LEN (1U)
+#define GLB_GAUGE_RXU_INT_EN_MSK (((1U << GLB_GAUGE_RXU_INT_EN_LEN) - 1) << GLB_GAUGE_RXU_INT_EN_POS)
+#define GLB_GAUGE_RXU_INT_EN_UMSK (~(((1U << GLB_GAUGE_RXU_INT_EN_LEN) - 1) << GLB_GAUGE_RXU_INT_EN_POS))
+#define GLB_GAUGE_RXA_INT_EN GLB_GAUGE_RXA_INT_EN
+#define GLB_GAUGE_RXA_INT_EN_POS (3U)
+#define GLB_GAUGE_RXA_INT_EN_LEN (1U)
+#define GLB_GAUGE_RXA_INT_EN_MSK (((1U << GLB_GAUGE_RXA_INT_EN_LEN) - 1) << GLB_GAUGE_RXA_INT_EN_POS)
+#define GLB_GAUGE_RXA_INT_EN_UMSK (~(((1U << GLB_GAUGE_RXA_INT_EN_LEN) - 1) << GLB_GAUGE_RXA_INT_EN_POS))
+#define GLB_GAUGE_RX_DRQ_EN GLB_GAUGE_RX_DRQ_EN
+#define GLB_GAUGE_RX_DRQ_EN_POS (4U)
+#define GLB_GAUGE_RX_DRQ_EN_LEN (1U)
+#define GLB_GAUGE_RX_DRQ_EN_MSK (((1U << GLB_GAUGE_RX_DRQ_EN_LEN) - 1) << GLB_GAUGE_RX_DRQ_EN_POS)
+#define GLB_GAUGE_RX_DRQ_EN_UMSK (~(((1U << GLB_GAUGE_RX_DRQ_EN_LEN) - 1) << GLB_GAUGE_RX_DRQ_EN_POS))
+#define GLB_GAUGE_RX_DATA_RES GLB_GAUGE_RX_DATA_RES
+#define GLB_GAUGE_RX_DATA_RES_POS (5U)
+#define GLB_GAUGE_RX_DATA_RES_LEN (1U)
+#define GLB_GAUGE_RX_DATA_RES_MSK (((1U << GLB_GAUGE_RX_DATA_RES_LEN) - 1) << GLB_GAUGE_RX_DATA_RES_POS)
+#define GLB_GAUGE_RX_DATA_RES_UMSK (~(((1U << GLB_GAUGE_RX_DATA_RES_LEN) - 1) << GLB_GAUGE_RX_DATA_RES_POS))
+#define GLB_GAUGE_RX_CH_EN GLB_GAUGE_RX_CH_EN
+#define GLB_GAUGE_RX_CH_EN_POS (8U)
+#define GLB_GAUGE_RX_CH_EN_LEN (1U)
+#define GLB_GAUGE_RX_CH_EN_MSK (((1U << GLB_GAUGE_RX_CH_EN_LEN) - 1) << GLB_GAUGE_RX_CH_EN_POS)
+#define GLB_GAUGE_RX_CH_EN_UMSK (~(((1U << GLB_GAUGE_RX_CH_EN_LEN) - 1) << GLB_GAUGE_RX_CH_EN_POS))
+#define GLB_GAUGE_RX_DRQ_CNT GLB_GAUGE_RX_DRQ_CNT
+#define GLB_GAUGE_RX_DRQ_CNT_POS (14U)
+#define GLB_GAUGE_RX_DRQ_CNT_LEN (2U)
+#define GLB_GAUGE_RX_DRQ_CNT_MSK (((1U << GLB_GAUGE_RX_DRQ_CNT_LEN) - 1) << GLB_GAUGE_RX_DRQ_CNT_POS)
+#define GLB_GAUGE_RX_DRQ_CNT_UMSK (~(((1U << GLB_GAUGE_RX_DRQ_CNT_LEN) - 1) << GLB_GAUGE_RX_DRQ_CNT_POS))
+#define GLB_GAUGE_RX_TRG_LEVEL GLB_GAUGE_RX_TRG_LEVEL
+#define GLB_GAUGE_RX_TRG_LEVEL_POS (16U)
+#define GLB_GAUGE_RX_TRG_LEVEL_LEN (3U)
+#define GLB_GAUGE_RX_TRG_LEVEL_MSK (((1U << GLB_GAUGE_RX_TRG_LEVEL_LEN) - 1) << GLB_GAUGE_RX_TRG_LEVEL_POS)
+#define GLB_GAUGE_RX_TRG_LEVEL_UMSK (~(((1U << GLB_GAUGE_RX_TRG_LEVEL_LEN) - 1) << GLB_GAUGE_RX_TRG_LEVEL_POS))
+#define GLB_GAUGE_RX_DATA_MODE GLB_GAUGE_RX_DATA_MODE
+#define GLB_GAUGE_RX_DATA_MODE_POS (24U)
+#define GLB_GAUGE_RX_DATA_MODE_LEN (2U)
+#define GLB_GAUGE_RX_DATA_MODE_MSK (((1U << GLB_GAUGE_RX_DATA_MODE_LEN) - 1) << GLB_GAUGE_RX_DATA_MODE_POS)
+#define GLB_GAUGE_RX_DATA_MODE_UMSK (~(((1U << GLB_GAUGE_RX_DATA_MODE_LEN) - 1) << GLB_GAUGE_RX_DATA_MODE_POS))
+
+/* 0x8BC : gauge_rx_fifo_status */
+#define GLB_GAUGE_RX_FIFO_STATUS_OFFSET (0x8BC)
+#define GLB_GAUGE_RXO_INT GLB_GAUGE_RXO_INT
+#define GLB_GAUGE_RXO_INT_POS (1U)
+#define GLB_GAUGE_RXO_INT_LEN (1U)
+#define GLB_GAUGE_RXO_INT_MSK (((1U << GLB_GAUGE_RXO_INT_LEN) - 1) << GLB_GAUGE_RXO_INT_POS)
+#define GLB_GAUGE_RXO_INT_UMSK (~(((1U << GLB_GAUGE_RXO_INT_LEN) - 1) << GLB_GAUGE_RXO_INT_POS))
+#define GLB_GAUGE_RXU_INT GLB_GAUGE_RXU_INT
+#define GLB_GAUGE_RXU_INT_POS (2U)
+#define GLB_GAUGE_RXU_INT_LEN (1U)
+#define GLB_GAUGE_RXU_INT_MSK (((1U << GLB_GAUGE_RXU_INT_LEN) - 1) << GLB_GAUGE_RXU_INT_POS)
+#define GLB_GAUGE_RXU_INT_UMSK (~(((1U << GLB_GAUGE_RXU_INT_LEN) - 1) << GLB_GAUGE_RXU_INT_POS))
+#define GLB_GAUGE_RXA_INT GLB_GAUGE_RXA_INT
+#define GLB_GAUGE_RXA_INT_POS (4U)
+#define GLB_GAUGE_RXA_INT_LEN (1U)
+#define GLB_GAUGE_RXA_INT_MSK (((1U << GLB_GAUGE_RXA_INT_LEN) - 1) << GLB_GAUGE_RXA_INT_POS)
+#define GLB_GAUGE_RXA_INT_UMSK (~(((1U << GLB_GAUGE_RXA_INT_LEN) - 1) << GLB_GAUGE_RXA_INT_POS))
+#define GLB_GAUGE_RXA_CNT GLB_GAUGE_RXA_CNT
+#define GLB_GAUGE_RXA_CNT_POS (16U)
+#define GLB_GAUGE_RXA_CNT_LEN (3U)
+#define GLB_GAUGE_RXA_CNT_MSK (((1U << GLB_GAUGE_RXA_CNT_LEN) - 1) << GLB_GAUGE_RXA_CNT_POS)
+#define GLB_GAUGE_RXA_CNT_UMSK (~(((1U << GLB_GAUGE_RXA_CNT_LEN) - 1) << GLB_GAUGE_RXA_CNT_POS))
+#define GLB_GAUGE_RXA GLB_GAUGE_RXA
+#define GLB_GAUGE_RXA_POS (24U)
+#define GLB_GAUGE_RXA_LEN (1U)
+#define GLB_GAUGE_RXA_MSK (((1U << GLB_GAUGE_RXA_LEN) - 1) << GLB_GAUGE_RXA_POS)
+#define GLB_GAUGE_RXA_UMSK (~(((1U << GLB_GAUGE_RXA_LEN) - 1) << GLB_GAUGE_RXA_POS))
+
+/* 0x8C0 : gauge_rx_fifo_data */
+#define GLB_GAUGE_RX_FIFO_DATA_OFFSET (0x8C0)
+#define GLB_GAUGE_RX_DATA GLB_GAUGE_RX_DATA
+#define GLB_GAUGE_RX_DATA_POS (0U)
+#define GLB_GAUGE_RX_DATA_LEN (32U)
+#define GLB_GAUGE_RX_DATA_MSK (((1U << GLB_GAUGE_RX_DATA_LEN) - 1) << GLB_GAUGE_RX_DATA_POS)
+#define GLB_GAUGE_RX_DATA_UMSK (~(((1U << GLB_GAUGE_RX_DATA_LEN) - 1) << GLB_GAUGE_RX_DATA_POS))
+
+/* 0x8C4 : gpio_cfg0 */
+#define GLB_GPIO_CFG0_OFFSET (0x8C4)
+#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS (0U)
+#define GLB_REG_GPIO_0_IE_LEN (1U)
+#define GLB_REG_GPIO_0_IE_MSK (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS (1U)
+#define GLB_REG_GPIO_0_SMT_LEN (1U)
+#define GLB_REG_GPIO_0_SMT_MSK (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS (2U)
+#define GLB_REG_GPIO_0_DRV_LEN (2U)
+#define GLB_REG_GPIO_0_DRV_MSK (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS (4U)
+#define GLB_REG_GPIO_0_PU_LEN (1U)
+#define GLB_REG_GPIO_0_PU_MSK (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS (5U)
+#define GLB_REG_GPIO_0_PD_LEN (1U)
+#define GLB_REG_GPIO_0_PD_MSK (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE
+#define GLB_REG_GPIO_0_OE_POS (6U)
+#define GLB_REG_GPIO_0_OE_LEN (1U)
+#define GLB_REG_GPIO_0_OE_MSK (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
+#define GLB_REG_GPIO_0_OE_UMSK (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_0_INT_MODE_SET GLB_REG_GPIO_0_INT_MODE_SET
+#define GLB_REG_GPIO_0_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_0_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_0_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_0_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_0_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_0_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_0_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_0_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_0_INT_CLR GLB_REG_GPIO_0_INT_CLR
+#define GLB_REG_GPIO_0_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_0_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_0_INT_CLR_MSK (((1U << GLB_REG_GPIO_0_INT_CLR_LEN) - 1) << GLB_REG_GPIO_0_INT_CLR_POS)
+#define GLB_REG_GPIO_0_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_0_INT_CLR_LEN) - 1) << GLB_REG_GPIO_0_INT_CLR_POS))
+#define GLB_GPIO_0_INT_STAT GLB_GPIO_0_INT_STAT
+#define GLB_GPIO_0_INT_STAT_POS (21U)
+#define GLB_GPIO_0_INT_STAT_LEN (1U)
+#define GLB_GPIO_0_INT_STAT_MSK (((1U << GLB_GPIO_0_INT_STAT_LEN) - 1) << GLB_GPIO_0_INT_STAT_POS)
+#define GLB_GPIO_0_INT_STAT_UMSK (~(((1U << GLB_GPIO_0_INT_STAT_LEN) - 1) << GLB_GPIO_0_INT_STAT_POS))
+#define GLB_REG_GPIO_0_INT_MASK GLB_REG_GPIO_0_INT_MASK
+#define GLB_REG_GPIO_0_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_0_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_0_INT_MASK_MSK (((1U << GLB_REG_GPIO_0_INT_MASK_LEN) - 1) << GLB_REG_GPIO_0_INT_MASK_POS)
+#define GLB_REG_GPIO_0_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_0_INT_MASK_LEN) - 1) << GLB_REG_GPIO_0_INT_MASK_POS))
+#define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O
+#define GLB_REG_GPIO_0_O_POS (24U)
+#define GLB_REG_GPIO_0_O_LEN (1U)
+#define GLB_REG_GPIO_0_O_MSK (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
+#define GLB_REG_GPIO_0_O_UMSK (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
+#define GLB_REG_GPIO_0_SET GLB_REG_GPIO_0_SET
+#define GLB_REG_GPIO_0_SET_POS (25U)
+#define GLB_REG_GPIO_0_SET_LEN (1U)
+#define GLB_REG_GPIO_0_SET_MSK (((1U << GLB_REG_GPIO_0_SET_LEN) - 1) << GLB_REG_GPIO_0_SET_POS)
+#define GLB_REG_GPIO_0_SET_UMSK (~(((1U << GLB_REG_GPIO_0_SET_LEN) - 1) << GLB_REG_GPIO_0_SET_POS))
+#define GLB_REG_GPIO_0_CLR GLB_REG_GPIO_0_CLR
+#define GLB_REG_GPIO_0_CLR_POS (26U)
+#define GLB_REG_GPIO_0_CLR_LEN (1U)
+#define GLB_REG_GPIO_0_CLR_MSK (((1U << GLB_REG_GPIO_0_CLR_LEN) - 1) << GLB_REG_GPIO_0_CLR_POS)
+#define GLB_REG_GPIO_0_CLR_UMSK (~(((1U << GLB_REG_GPIO_0_CLR_LEN) - 1) << GLB_REG_GPIO_0_CLR_POS))
+#define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I
+#define GLB_REG_GPIO_0_I_POS (28U)
+#define GLB_REG_GPIO_0_I_LEN (1U)
+#define GLB_REG_GPIO_0_I_MSK (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
+#define GLB_REG_GPIO_0_I_UMSK (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
+#define GLB_REG_GPIO_0_MODE GLB_REG_GPIO_0_MODE
+#define GLB_REG_GPIO_0_MODE_POS (30U)
+#define GLB_REG_GPIO_0_MODE_LEN (2U)
+#define GLB_REG_GPIO_0_MODE_MSK (((1U << GLB_REG_GPIO_0_MODE_LEN) - 1) << GLB_REG_GPIO_0_MODE_POS)
+#define GLB_REG_GPIO_0_MODE_UMSK (~(((1U << GLB_REG_GPIO_0_MODE_LEN) - 1) << GLB_REG_GPIO_0_MODE_POS))
+
+/* 0x8C8 : gpio_cfg1 */
+#define GLB_GPIO_CFG1_OFFSET (0x8C8)
+#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS (0U)
+#define GLB_REG_GPIO_1_IE_LEN (1U)
+#define GLB_REG_GPIO_1_IE_MSK (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS (1U)
+#define GLB_REG_GPIO_1_SMT_LEN (1U)
+#define GLB_REG_GPIO_1_SMT_MSK (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS (2U)
+#define GLB_REG_GPIO_1_DRV_LEN (2U)
+#define GLB_REG_GPIO_1_DRV_MSK (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS (4U)
+#define GLB_REG_GPIO_1_PU_LEN (1U)
+#define GLB_REG_GPIO_1_PU_MSK (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS (5U)
+#define GLB_REG_GPIO_1_PD_LEN (1U)
+#define GLB_REG_GPIO_1_PD_MSK (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE
+#define GLB_REG_GPIO_1_OE_POS (6U)
+#define GLB_REG_GPIO_1_OE_LEN (1U)
+#define GLB_REG_GPIO_1_OE_MSK (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
+#define GLB_REG_GPIO_1_OE_UMSK (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_INT_MODE_SET GLB_REG_GPIO_1_INT_MODE_SET
+#define GLB_REG_GPIO_1_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_1_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_1_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_1_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_1_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_1_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_1_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_1_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_1_INT_CLR GLB_REG_GPIO_1_INT_CLR
+#define GLB_REG_GPIO_1_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_1_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_1_INT_CLR_MSK (((1U << GLB_REG_GPIO_1_INT_CLR_LEN) - 1) << GLB_REG_GPIO_1_INT_CLR_POS)
+#define GLB_REG_GPIO_1_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_1_INT_CLR_LEN) - 1) << GLB_REG_GPIO_1_INT_CLR_POS))
+#define GLB_GPIO_1_INT_STAT GLB_GPIO_1_INT_STAT
+#define GLB_GPIO_1_INT_STAT_POS (21U)
+#define GLB_GPIO_1_INT_STAT_LEN (1U)
+#define GLB_GPIO_1_INT_STAT_MSK (((1U << GLB_GPIO_1_INT_STAT_LEN) - 1) << GLB_GPIO_1_INT_STAT_POS)
+#define GLB_GPIO_1_INT_STAT_UMSK (~(((1U << GLB_GPIO_1_INT_STAT_LEN) - 1) << GLB_GPIO_1_INT_STAT_POS))
+#define GLB_REG_GPIO_1_INT_MASK GLB_REG_GPIO_1_INT_MASK
+#define GLB_REG_GPIO_1_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_1_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_1_INT_MASK_MSK (((1U << GLB_REG_GPIO_1_INT_MASK_LEN) - 1) << GLB_REG_GPIO_1_INT_MASK_POS)
+#define GLB_REG_GPIO_1_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_1_INT_MASK_LEN) - 1) << GLB_REG_GPIO_1_INT_MASK_POS))
+#define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O
+#define GLB_REG_GPIO_1_O_POS (24U)
+#define GLB_REG_GPIO_1_O_LEN (1U)
+#define GLB_REG_GPIO_1_O_MSK (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
+#define GLB_REG_GPIO_1_O_UMSK (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
+#define GLB_REG_GPIO_1_SET GLB_REG_GPIO_1_SET
+#define GLB_REG_GPIO_1_SET_POS (25U)
+#define GLB_REG_GPIO_1_SET_LEN (1U)
+#define GLB_REG_GPIO_1_SET_MSK (((1U << GLB_REG_GPIO_1_SET_LEN) - 1) << GLB_REG_GPIO_1_SET_POS)
+#define GLB_REG_GPIO_1_SET_UMSK (~(((1U << GLB_REG_GPIO_1_SET_LEN) - 1) << GLB_REG_GPIO_1_SET_POS))
+#define GLB_REG_GPIO_1_CLR GLB_REG_GPIO_1_CLR
+#define GLB_REG_GPIO_1_CLR_POS (26U)
+#define GLB_REG_GPIO_1_CLR_LEN (1U)
+#define GLB_REG_GPIO_1_CLR_MSK (((1U << GLB_REG_GPIO_1_CLR_LEN) - 1) << GLB_REG_GPIO_1_CLR_POS)
+#define GLB_REG_GPIO_1_CLR_UMSK (~(((1U << GLB_REG_GPIO_1_CLR_LEN) - 1) << GLB_REG_GPIO_1_CLR_POS))
+#define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I
+#define GLB_REG_GPIO_1_I_POS (28U)
+#define GLB_REG_GPIO_1_I_LEN (1U)
+#define GLB_REG_GPIO_1_I_MSK (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
+#define GLB_REG_GPIO_1_I_UMSK (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
+#define GLB_REG_GPIO_1_MODE GLB_REG_GPIO_1_MODE
+#define GLB_REG_GPIO_1_MODE_POS (30U)
+#define GLB_REG_GPIO_1_MODE_LEN (2U)
+#define GLB_REG_GPIO_1_MODE_MSK (((1U << GLB_REG_GPIO_1_MODE_LEN) - 1) << GLB_REG_GPIO_1_MODE_POS)
+#define GLB_REG_GPIO_1_MODE_UMSK (~(((1U << GLB_REG_GPIO_1_MODE_LEN) - 1) << GLB_REG_GPIO_1_MODE_POS))
+
+/* 0x8CC : gpio_cfg2 */
+#define GLB_GPIO_CFG2_OFFSET (0x8CC)
+#define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE
+#define GLB_REG_GPIO_2_IE_POS (0U)
+#define GLB_REG_GPIO_2_IE_LEN (1U)
+#define GLB_REG_GPIO_2_IE_MSK (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
+#define GLB_REG_GPIO_2_IE_UMSK (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
+#define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT
+#define GLB_REG_GPIO_2_SMT_POS (1U)
+#define GLB_REG_GPIO_2_SMT_LEN (1U)
+#define GLB_REG_GPIO_2_SMT_MSK (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
+#define GLB_REG_GPIO_2_SMT_UMSK (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
+#define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV
+#define GLB_REG_GPIO_2_DRV_POS (2U)
+#define GLB_REG_GPIO_2_DRV_LEN (2U)
+#define GLB_REG_GPIO_2_DRV_MSK (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
+#define GLB_REG_GPIO_2_DRV_UMSK (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
+#define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU
+#define GLB_REG_GPIO_2_PU_POS (4U)
+#define GLB_REG_GPIO_2_PU_LEN (1U)
+#define GLB_REG_GPIO_2_PU_MSK (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
+#define GLB_REG_GPIO_2_PU_UMSK (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
+#define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD
+#define GLB_REG_GPIO_2_PD_POS (5U)
+#define GLB_REG_GPIO_2_PD_LEN (1U)
+#define GLB_REG_GPIO_2_PD_MSK (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
+#define GLB_REG_GPIO_2_PD_UMSK (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
+#define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE
+#define GLB_REG_GPIO_2_OE_POS (6U)
+#define GLB_REG_GPIO_2_OE_LEN (1U)
+#define GLB_REG_GPIO_2_OE_MSK (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
+#define GLB_REG_GPIO_2_OE_UMSK (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
+#define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL
+#define GLB_REG_GPIO_2_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_2_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_2_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
+#define GLB_REG_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
+#define GLB_REG_GPIO_2_INT_MODE_SET GLB_REG_GPIO_2_INT_MODE_SET
+#define GLB_REG_GPIO_2_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_2_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_2_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_2_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_2_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_2_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_2_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_2_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_2_INT_CLR GLB_REG_GPIO_2_INT_CLR
+#define GLB_REG_GPIO_2_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_2_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_2_INT_CLR_MSK (((1U << GLB_REG_GPIO_2_INT_CLR_LEN) - 1) << GLB_REG_GPIO_2_INT_CLR_POS)
+#define GLB_REG_GPIO_2_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_2_INT_CLR_LEN) - 1) << GLB_REG_GPIO_2_INT_CLR_POS))
+#define GLB_GPIO_2_INT_STAT GLB_GPIO_2_INT_STAT
+#define GLB_GPIO_2_INT_STAT_POS (21U)
+#define GLB_GPIO_2_INT_STAT_LEN (1U)
+#define GLB_GPIO_2_INT_STAT_MSK (((1U << GLB_GPIO_2_INT_STAT_LEN) - 1) << GLB_GPIO_2_INT_STAT_POS)
+#define GLB_GPIO_2_INT_STAT_UMSK (~(((1U << GLB_GPIO_2_INT_STAT_LEN) - 1) << GLB_GPIO_2_INT_STAT_POS))
+#define GLB_REG_GPIO_2_INT_MASK GLB_REG_GPIO_2_INT_MASK
+#define GLB_REG_GPIO_2_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_2_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_2_INT_MASK_MSK (((1U << GLB_REG_GPIO_2_INT_MASK_LEN) - 1) << GLB_REG_GPIO_2_INT_MASK_POS)
+#define GLB_REG_GPIO_2_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_2_INT_MASK_LEN) - 1) << GLB_REG_GPIO_2_INT_MASK_POS))
+#define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O
+#define GLB_REG_GPIO_2_O_POS (24U)
+#define GLB_REG_GPIO_2_O_LEN (1U)
+#define GLB_REG_GPIO_2_O_MSK (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
+#define GLB_REG_GPIO_2_O_UMSK (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
+#define GLB_REG_GPIO_2_SET GLB_REG_GPIO_2_SET
+#define GLB_REG_GPIO_2_SET_POS (25U)
+#define GLB_REG_GPIO_2_SET_LEN (1U)
+#define GLB_REG_GPIO_2_SET_MSK (((1U << GLB_REG_GPIO_2_SET_LEN) - 1) << GLB_REG_GPIO_2_SET_POS)
+#define GLB_REG_GPIO_2_SET_UMSK (~(((1U << GLB_REG_GPIO_2_SET_LEN) - 1) << GLB_REG_GPIO_2_SET_POS))
+#define GLB_REG_GPIO_2_CLR GLB_REG_GPIO_2_CLR
+#define GLB_REG_GPIO_2_CLR_POS (26U)
+#define GLB_REG_GPIO_2_CLR_LEN (1U)
+#define GLB_REG_GPIO_2_CLR_MSK (((1U << GLB_REG_GPIO_2_CLR_LEN) - 1) << GLB_REG_GPIO_2_CLR_POS)
+#define GLB_REG_GPIO_2_CLR_UMSK (~(((1U << GLB_REG_GPIO_2_CLR_LEN) - 1) << GLB_REG_GPIO_2_CLR_POS))
+#define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I
+#define GLB_REG_GPIO_2_I_POS (28U)
+#define GLB_REG_GPIO_2_I_LEN (1U)
+#define GLB_REG_GPIO_2_I_MSK (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
+#define GLB_REG_GPIO_2_I_UMSK (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
+#define GLB_REG_GPIO_2_MODE GLB_REG_GPIO_2_MODE
+#define GLB_REG_GPIO_2_MODE_POS (30U)
+#define GLB_REG_GPIO_2_MODE_LEN (2U)
+#define GLB_REG_GPIO_2_MODE_MSK (((1U << GLB_REG_GPIO_2_MODE_LEN) - 1) << GLB_REG_GPIO_2_MODE_POS)
+#define GLB_REG_GPIO_2_MODE_UMSK (~(((1U << GLB_REG_GPIO_2_MODE_LEN) - 1) << GLB_REG_GPIO_2_MODE_POS))
+
+/* 0x8D0 : gpio_cfg3 */
+#define GLB_GPIO_CFG3_OFFSET (0x8D0)
+#define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE
+#define GLB_REG_GPIO_3_IE_POS (0U)
+#define GLB_REG_GPIO_3_IE_LEN (1U)
+#define GLB_REG_GPIO_3_IE_MSK (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
+#define GLB_REG_GPIO_3_IE_UMSK (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
+#define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT
+#define GLB_REG_GPIO_3_SMT_POS (1U)
+#define GLB_REG_GPIO_3_SMT_LEN (1U)
+#define GLB_REG_GPIO_3_SMT_MSK (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
+#define GLB_REG_GPIO_3_SMT_UMSK (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
+#define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV
+#define GLB_REG_GPIO_3_DRV_POS (2U)
+#define GLB_REG_GPIO_3_DRV_LEN (2U)
+#define GLB_REG_GPIO_3_DRV_MSK (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
+#define GLB_REG_GPIO_3_DRV_UMSK (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
+#define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU
+#define GLB_REG_GPIO_3_PU_POS (4U)
+#define GLB_REG_GPIO_3_PU_LEN (1U)
+#define GLB_REG_GPIO_3_PU_MSK (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
+#define GLB_REG_GPIO_3_PU_UMSK (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
+#define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD
+#define GLB_REG_GPIO_3_PD_POS (5U)
+#define GLB_REG_GPIO_3_PD_LEN (1U)
+#define GLB_REG_GPIO_3_PD_MSK (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
+#define GLB_REG_GPIO_3_PD_UMSK (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
+#define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE
+#define GLB_REG_GPIO_3_OE_POS (6U)
+#define GLB_REG_GPIO_3_OE_LEN (1U)
+#define GLB_REG_GPIO_3_OE_MSK (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
+#define GLB_REG_GPIO_3_OE_UMSK (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
+#define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL
+#define GLB_REG_GPIO_3_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_3_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_3_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
+#define GLB_REG_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))
+#define GLB_REG_GPIO_3_INT_MODE_SET GLB_REG_GPIO_3_INT_MODE_SET
+#define GLB_REG_GPIO_3_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_3_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_3_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_3_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_3_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_3_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_3_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_3_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_3_INT_CLR GLB_REG_GPIO_3_INT_CLR
+#define GLB_REG_GPIO_3_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_3_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_3_INT_CLR_MSK (((1U << GLB_REG_GPIO_3_INT_CLR_LEN) - 1) << GLB_REG_GPIO_3_INT_CLR_POS)
+#define GLB_REG_GPIO_3_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_3_INT_CLR_LEN) - 1) << GLB_REG_GPIO_3_INT_CLR_POS))
+#define GLB_GPIO_3_INT_STAT GLB_GPIO_3_INT_STAT
+#define GLB_GPIO_3_INT_STAT_POS (21U)
+#define GLB_GPIO_3_INT_STAT_LEN (1U)
+#define GLB_GPIO_3_INT_STAT_MSK (((1U << GLB_GPIO_3_INT_STAT_LEN) - 1) << GLB_GPIO_3_INT_STAT_POS)
+#define GLB_GPIO_3_INT_STAT_UMSK (~(((1U << GLB_GPIO_3_INT_STAT_LEN) - 1) << GLB_GPIO_3_INT_STAT_POS))
+#define GLB_REG_GPIO_3_INT_MASK GLB_REG_GPIO_3_INT_MASK
+#define GLB_REG_GPIO_3_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_3_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_3_INT_MASK_MSK (((1U << GLB_REG_GPIO_3_INT_MASK_LEN) - 1) << GLB_REG_GPIO_3_INT_MASK_POS)
+#define GLB_REG_GPIO_3_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_3_INT_MASK_LEN) - 1) << GLB_REG_GPIO_3_INT_MASK_POS))
+#define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O
+#define GLB_REG_GPIO_3_O_POS (24U)
+#define GLB_REG_GPIO_3_O_LEN (1U)
+#define GLB_REG_GPIO_3_O_MSK (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
+#define GLB_REG_GPIO_3_O_UMSK (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
+#define GLB_REG_GPIO_3_SET GLB_REG_GPIO_3_SET
+#define GLB_REG_GPIO_3_SET_POS (25U)
+#define GLB_REG_GPIO_3_SET_LEN (1U)
+#define GLB_REG_GPIO_3_SET_MSK (((1U << GLB_REG_GPIO_3_SET_LEN) - 1) << GLB_REG_GPIO_3_SET_POS)
+#define GLB_REG_GPIO_3_SET_UMSK (~(((1U << GLB_REG_GPIO_3_SET_LEN) - 1) << GLB_REG_GPIO_3_SET_POS))
+#define GLB_REG_GPIO_3_CLR GLB_REG_GPIO_3_CLR
+#define GLB_REG_GPIO_3_CLR_POS (26U)
+#define GLB_REG_GPIO_3_CLR_LEN (1U)
+#define GLB_REG_GPIO_3_CLR_MSK (((1U << GLB_REG_GPIO_3_CLR_LEN) - 1) << GLB_REG_GPIO_3_CLR_POS)
+#define GLB_REG_GPIO_3_CLR_UMSK (~(((1U << GLB_REG_GPIO_3_CLR_LEN) - 1) << GLB_REG_GPIO_3_CLR_POS))
+#define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I
+#define GLB_REG_GPIO_3_I_POS (28U)
+#define GLB_REG_GPIO_3_I_LEN (1U)
+#define GLB_REG_GPIO_3_I_MSK (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
+#define GLB_REG_GPIO_3_I_UMSK (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
+#define GLB_REG_GPIO_3_MODE GLB_REG_GPIO_3_MODE
+#define GLB_REG_GPIO_3_MODE_POS (30U)
+#define GLB_REG_GPIO_3_MODE_LEN (2U)
+#define GLB_REG_GPIO_3_MODE_MSK (((1U << GLB_REG_GPIO_3_MODE_LEN) - 1) << GLB_REG_GPIO_3_MODE_POS)
+#define GLB_REG_GPIO_3_MODE_UMSK (~(((1U << GLB_REG_GPIO_3_MODE_LEN) - 1) << GLB_REG_GPIO_3_MODE_POS))
+
+/* 0x8D4 : gpio_cfg4 */
+#define GLB_GPIO_CFG4_OFFSET (0x8D4)
+#define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE
+#define GLB_REG_GPIO_4_IE_POS (0U)
+#define GLB_REG_GPIO_4_IE_LEN (1U)
+#define GLB_REG_GPIO_4_IE_MSK (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
+#define GLB_REG_GPIO_4_IE_UMSK (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
+#define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT
+#define GLB_REG_GPIO_4_SMT_POS (1U)
+#define GLB_REG_GPIO_4_SMT_LEN (1U)
+#define GLB_REG_GPIO_4_SMT_MSK (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
+#define GLB_REG_GPIO_4_SMT_UMSK (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
+#define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV
+#define GLB_REG_GPIO_4_DRV_POS (2U)
+#define GLB_REG_GPIO_4_DRV_LEN (2U)
+#define GLB_REG_GPIO_4_DRV_MSK (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
+#define GLB_REG_GPIO_4_DRV_UMSK (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
+#define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU
+#define GLB_REG_GPIO_4_PU_POS (4U)
+#define GLB_REG_GPIO_4_PU_LEN (1U)
+#define GLB_REG_GPIO_4_PU_MSK (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
+#define GLB_REG_GPIO_4_PU_UMSK (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
+#define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD
+#define GLB_REG_GPIO_4_PD_POS (5U)
+#define GLB_REG_GPIO_4_PD_LEN (1U)
+#define GLB_REG_GPIO_4_PD_MSK (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
+#define GLB_REG_GPIO_4_PD_UMSK (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
+#define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE
+#define GLB_REG_GPIO_4_OE_POS (6U)
+#define GLB_REG_GPIO_4_OE_LEN (1U)
+#define GLB_REG_GPIO_4_OE_MSK (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
+#define GLB_REG_GPIO_4_OE_UMSK (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
+#define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL
+#define GLB_REG_GPIO_4_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_4_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_4_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
+#define GLB_REG_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
+#define GLB_REG_GPIO_4_INT_MODE_SET GLB_REG_GPIO_4_INT_MODE_SET
+#define GLB_REG_GPIO_4_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_4_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_4_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_4_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_4_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_4_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_4_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_4_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_4_INT_CLR GLB_REG_GPIO_4_INT_CLR
+#define GLB_REG_GPIO_4_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_4_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_4_INT_CLR_MSK (((1U << GLB_REG_GPIO_4_INT_CLR_LEN) - 1) << GLB_REG_GPIO_4_INT_CLR_POS)
+#define GLB_REG_GPIO_4_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_4_INT_CLR_LEN) - 1) << GLB_REG_GPIO_4_INT_CLR_POS))
+#define GLB_GPIO_4_INT_STAT GLB_GPIO_4_INT_STAT
+#define GLB_GPIO_4_INT_STAT_POS (21U)
+#define GLB_GPIO_4_INT_STAT_LEN (1U)
+#define GLB_GPIO_4_INT_STAT_MSK (((1U << GLB_GPIO_4_INT_STAT_LEN) - 1) << GLB_GPIO_4_INT_STAT_POS)
+#define GLB_GPIO_4_INT_STAT_UMSK (~(((1U << GLB_GPIO_4_INT_STAT_LEN) - 1) << GLB_GPIO_4_INT_STAT_POS))
+#define GLB_REG_GPIO_4_INT_MASK GLB_REG_GPIO_4_INT_MASK
+#define GLB_REG_GPIO_4_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_4_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_4_INT_MASK_MSK (((1U << GLB_REG_GPIO_4_INT_MASK_LEN) - 1) << GLB_REG_GPIO_4_INT_MASK_POS)
+#define GLB_REG_GPIO_4_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_4_INT_MASK_LEN) - 1) << GLB_REG_GPIO_4_INT_MASK_POS))
+#define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O
+#define GLB_REG_GPIO_4_O_POS (24U)
+#define GLB_REG_GPIO_4_O_LEN (1U)
+#define GLB_REG_GPIO_4_O_MSK (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
+#define GLB_REG_GPIO_4_O_UMSK (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
+#define GLB_REG_GPIO_4_SET GLB_REG_GPIO_4_SET
+#define GLB_REG_GPIO_4_SET_POS (25U)
+#define GLB_REG_GPIO_4_SET_LEN (1U)
+#define GLB_REG_GPIO_4_SET_MSK (((1U << GLB_REG_GPIO_4_SET_LEN) - 1) << GLB_REG_GPIO_4_SET_POS)
+#define GLB_REG_GPIO_4_SET_UMSK (~(((1U << GLB_REG_GPIO_4_SET_LEN) - 1) << GLB_REG_GPIO_4_SET_POS))
+#define GLB_REG_GPIO_4_CLR GLB_REG_GPIO_4_CLR
+#define GLB_REG_GPIO_4_CLR_POS (26U)
+#define GLB_REG_GPIO_4_CLR_LEN (1U)
+#define GLB_REG_GPIO_4_CLR_MSK (((1U << GLB_REG_GPIO_4_CLR_LEN) - 1) << GLB_REG_GPIO_4_CLR_POS)
+#define GLB_REG_GPIO_4_CLR_UMSK (~(((1U << GLB_REG_GPIO_4_CLR_LEN) - 1) << GLB_REG_GPIO_4_CLR_POS))
+#define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I
+#define GLB_REG_GPIO_4_I_POS (28U)
+#define GLB_REG_GPIO_4_I_LEN (1U)
+#define GLB_REG_GPIO_4_I_MSK (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
+#define GLB_REG_GPIO_4_I_UMSK (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
+#define GLB_REG_GPIO_4_MODE GLB_REG_GPIO_4_MODE
+#define GLB_REG_GPIO_4_MODE_POS (30U)
+#define GLB_REG_GPIO_4_MODE_LEN (2U)
+#define GLB_REG_GPIO_4_MODE_MSK (((1U << GLB_REG_GPIO_4_MODE_LEN) - 1) << GLB_REG_GPIO_4_MODE_POS)
+#define GLB_REG_GPIO_4_MODE_UMSK (~(((1U << GLB_REG_GPIO_4_MODE_LEN) - 1) << GLB_REG_GPIO_4_MODE_POS))
+
+/* 0x8D8 : gpio_cfg5 */
+#define GLB_GPIO_CFG5_OFFSET (0x8D8)
+#define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE
+#define GLB_REG_GPIO_5_IE_POS (0U)
+#define GLB_REG_GPIO_5_IE_LEN (1U)
+#define GLB_REG_GPIO_5_IE_MSK (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
+#define GLB_REG_GPIO_5_IE_UMSK (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
+#define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT
+#define GLB_REG_GPIO_5_SMT_POS (1U)
+#define GLB_REG_GPIO_5_SMT_LEN (1U)
+#define GLB_REG_GPIO_5_SMT_MSK (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
+#define GLB_REG_GPIO_5_SMT_UMSK (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
+#define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV
+#define GLB_REG_GPIO_5_DRV_POS (2U)
+#define GLB_REG_GPIO_5_DRV_LEN (2U)
+#define GLB_REG_GPIO_5_DRV_MSK (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
+#define GLB_REG_GPIO_5_DRV_UMSK (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
+#define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU
+#define GLB_REG_GPIO_5_PU_POS (4U)
+#define GLB_REG_GPIO_5_PU_LEN (1U)
+#define GLB_REG_GPIO_5_PU_MSK (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
+#define GLB_REG_GPIO_5_PU_UMSK (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
+#define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD
+#define GLB_REG_GPIO_5_PD_POS (5U)
+#define GLB_REG_GPIO_5_PD_LEN (1U)
+#define GLB_REG_GPIO_5_PD_MSK (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
+#define GLB_REG_GPIO_5_PD_UMSK (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
+#define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE
+#define GLB_REG_GPIO_5_OE_POS (6U)
+#define GLB_REG_GPIO_5_OE_LEN (1U)
+#define GLB_REG_GPIO_5_OE_MSK (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
+#define GLB_REG_GPIO_5_OE_UMSK (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
+#define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL
+#define GLB_REG_GPIO_5_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_5_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_5_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
+#define GLB_REG_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))
+#define GLB_REG_GPIO_5_INT_MODE_SET GLB_REG_GPIO_5_INT_MODE_SET
+#define GLB_REG_GPIO_5_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_5_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_5_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_5_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_5_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_5_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_5_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_5_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_5_INT_CLR GLB_REG_GPIO_5_INT_CLR
+#define GLB_REG_GPIO_5_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_5_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_5_INT_CLR_MSK (((1U << GLB_REG_GPIO_5_INT_CLR_LEN) - 1) << GLB_REG_GPIO_5_INT_CLR_POS)
+#define GLB_REG_GPIO_5_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_5_INT_CLR_LEN) - 1) << GLB_REG_GPIO_5_INT_CLR_POS))
+#define GLB_GPIO_5_INT_STAT GLB_GPIO_5_INT_STAT
+#define GLB_GPIO_5_INT_STAT_POS (21U)
+#define GLB_GPIO_5_INT_STAT_LEN (1U)
+#define GLB_GPIO_5_INT_STAT_MSK (((1U << GLB_GPIO_5_INT_STAT_LEN) - 1) << GLB_GPIO_5_INT_STAT_POS)
+#define GLB_GPIO_5_INT_STAT_UMSK (~(((1U << GLB_GPIO_5_INT_STAT_LEN) - 1) << GLB_GPIO_5_INT_STAT_POS))
+#define GLB_REG_GPIO_5_INT_MASK GLB_REG_GPIO_5_INT_MASK
+#define GLB_REG_GPIO_5_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_5_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_5_INT_MASK_MSK (((1U << GLB_REG_GPIO_5_INT_MASK_LEN) - 1) << GLB_REG_GPIO_5_INT_MASK_POS)
+#define GLB_REG_GPIO_5_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_5_INT_MASK_LEN) - 1) << GLB_REG_GPIO_5_INT_MASK_POS))
+#define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O
+#define GLB_REG_GPIO_5_O_POS (24U)
+#define GLB_REG_GPIO_5_O_LEN (1U)
+#define GLB_REG_GPIO_5_O_MSK (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
+#define GLB_REG_GPIO_5_O_UMSK (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
+#define GLB_REG_GPIO_5_SET GLB_REG_GPIO_5_SET
+#define GLB_REG_GPIO_5_SET_POS (25U)
+#define GLB_REG_GPIO_5_SET_LEN (1U)
+#define GLB_REG_GPIO_5_SET_MSK (((1U << GLB_REG_GPIO_5_SET_LEN) - 1) << GLB_REG_GPIO_5_SET_POS)
+#define GLB_REG_GPIO_5_SET_UMSK (~(((1U << GLB_REG_GPIO_5_SET_LEN) - 1) << GLB_REG_GPIO_5_SET_POS))
+#define GLB_REG_GPIO_5_CLR GLB_REG_GPIO_5_CLR
+#define GLB_REG_GPIO_5_CLR_POS (26U)
+#define GLB_REG_GPIO_5_CLR_LEN (1U)
+#define GLB_REG_GPIO_5_CLR_MSK (((1U << GLB_REG_GPIO_5_CLR_LEN) - 1) << GLB_REG_GPIO_5_CLR_POS)
+#define GLB_REG_GPIO_5_CLR_UMSK (~(((1U << GLB_REG_GPIO_5_CLR_LEN) - 1) << GLB_REG_GPIO_5_CLR_POS))
+#define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I
+#define GLB_REG_GPIO_5_I_POS (28U)
+#define GLB_REG_GPIO_5_I_LEN (1U)
+#define GLB_REG_GPIO_5_I_MSK (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
+#define GLB_REG_GPIO_5_I_UMSK (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
+#define GLB_REG_GPIO_5_MODE GLB_REG_GPIO_5_MODE
+#define GLB_REG_GPIO_5_MODE_POS (30U)
+#define GLB_REG_GPIO_5_MODE_LEN (2U)
+#define GLB_REG_GPIO_5_MODE_MSK (((1U << GLB_REG_GPIO_5_MODE_LEN) - 1) << GLB_REG_GPIO_5_MODE_POS)
+#define GLB_REG_GPIO_5_MODE_UMSK (~(((1U << GLB_REG_GPIO_5_MODE_LEN) - 1) << GLB_REG_GPIO_5_MODE_POS))
+
+/* 0x8DC : gpio_cfg6 */
+#define GLB_GPIO_CFG6_OFFSET (0x8DC)
+#define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE
+#define GLB_REG_GPIO_6_IE_POS (0U)
+#define GLB_REG_GPIO_6_IE_LEN (1U)
+#define GLB_REG_GPIO_6_IE_MSK (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
+#define GLB_REG_GPIO_6_IE_UMSK (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
+#define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT
+#define GLB_REG_GPIO_6_SMT_POS (1U)
+#define GLB_REG_GPIO_6_SMT_LEN (1U)
+#define GLB_REG_GPIO_6_SMT_MSK (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
+#define GLB_REG_GPIO_6_SMT_UMSK (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
+#define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV
+#define GLB_REG_GPIO_6_DRV_POS (2U)
+#define GLB_REG_GPIO_6_DRV_LEN (2U)
+#define GLB_REG_GPIO_6_DRV_MSK (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
+#define GLB_REG_GPIO_6_DRV_UMSK (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
+#define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU
+#define GLB_REG_GPIO_6_PU_POS (4U)
+#define GLB_REG_GPIO_6_PU_LEN (1U)
+#define GLB_REG_GPIO_6_PU_MSK (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
+#define GLB_REG_GPIO_6_PU_UMSK (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
+#define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD
+#define GLB_REG_GPIO_6_PD_POS (5U)
+#define GLB_REG_GPIO_6_PD_LEN (1U)
+#define GLB_REG_GPIO_6_PD_MSK (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
+#define GLB_REG_GPIO_6_PD_UMSK (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
+#define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE
+#define GLB_REG_GPIO_6_OE_POS (6U)
+#define GLB_REG_GPIO_6_OE_LEN (1U)
+#define GLB_REG_GPIO_6_OE_MSK (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
+#define GLB_REG_GPIO_6_OE_UMSK (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
+#define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL
+#define GLB_REG_GPIO_6_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_6_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_6_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
+#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
+#define GLB_REG_GPIO_6_INT_MODE_SET GLB_REG_GPIO_6_INT_MODE_SET
+#define GLB_REG_GPIO_6_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_6_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_6_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_6_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_6_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_6_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_6_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_6_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_6_INT_CLR GLB_REG_GPIO_6_INT_CLR
+#define GLB_REG_GPIO_6_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_6_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_6_INT_CLR_MSK (((1U << GLB_REG_GPIO_6_INT_CLR_LEN) - 1) << GLB_REG_GPIO_6_INT_CLR_POS)
+#define GLB_REG_GPIO_6_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_6_INT_CLR_LEN) - 1) << GLB_REG_GPIO_6_INT_CLR_POS))
+#define GLB_GPIO_6_INT_STAT GLB_GPIO_6_INT_STAT
+#define GLB_GPIO_6_INT_STAT_POS (21U)
+#define GLB_GPIO_6_INT_STAT_LEN (1U)
+#define GLB_GPIO_6_INT_STAT_MSK (((1U << GLB_GPIO_6_INT_STAT_LEN) - 1) << GLB_GPIO_6_INT_STAT_POS)
+#define GLB_GPIO_6_INT_STAT_UMSK (~(((1U << GLB_GPIO_6_INT_STAT_LEN) - 1) << GLB_GPIO_6_INT_STAT_POS))
+#define GLB_REG_GPIO_6_INT_MASK GLB_REG_GPIO_6_INT_MASK
+#define GLB_REG_GPIO_6_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_6_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_6_INT_MASK_MSK (((1U << GLB_REG_GPIO_6_INT_MASK_LEN) - 1) << GLB_REG_GPIO_6_INT_MASK_POS)
+#define GLB_REG_GPIO_6_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_6_INT_MASK_LEN) - 1) << GLB_REG_GPIO_6_INT_MASK_POS))
+#define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O
+#define GLB_REG_GPIO_6_O_POS (24U)
+#define GLB_REG_GPIO_6_O_LEN (1U)
+#define GLB_REG_GPIO_6_O_MSK (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
+#define GLB_REG_GPIO_6_O_UMSK (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
+#define GLB_REG_GPIO_6_SET GLB_REG_GPIO_6_SET
+#define GLB_REG_GPIO_6_SET_POS (25U)
+#define GLB_REG_GPIO_6_SET_LEN (1U)
+#define GLB_REG_GPIO_6_SET_MSK (((1U << GLB_REG_GPIO_6_SET_LEN) - 1) << GLB_REG_GPIO_6_SET_POS)
+#define GLB_REG_GPIO_6_SET_UMSK (~(((1U << GLB_REG_GPIO_6_SET_LEN) - 1) << GLB_REG_GPIO_6_SET_POS))
+#define GLB_REG_GPIO_6_CLR GLB_REG_GPIO_6_CLR
+#define GLB_REG_GPIO_6_CLR_POS (26U)
+#define GLB_REG_GPIO_6_CLR_LEN (1U)
+#define GLB_REG_GPIO_6_CLR_MSK (((1U << GLB_REG_GPIO_6_CLR_LEN) - 1) << GLB_REG_GPIO_6_CLR_POS)
+#define GLB_REG_GPIO_6_CLR_UMSK (~(((1U << GLB_REG_GPIO_6_CLR_LEN) - 1) << GLB_REG_GPIO_6_CLR_POS))
+#define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I
+#define GLB_REG_GPIO_6_I_POS (28U)
+#define GLB_REG_GPIO_6_I_LEN (1U)
+#define GLB_REG_GPIO_6_I_MSK (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
+#define GLB_REG_GPIO_6_I_UMSK (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
+#define GLB_REG_GPIO_6_MODE GLB_REG_GPIO_6_MODE
+#define GLB_REG_GPIO_6_MODE_POS (30U)
+#define GLB_REG_GPIO_6_MODE_LEN (2U)
+#define GLB_REG_GPIO_6_MODE_MSK (((1U << GLB_REG_GPIO_6_MODE_LEN) - 1) << GLB_REG_GPIO_6_MODE_POS)
+#define GLB_REG_GPIO_6_MODE_UMSK (~(((1U << GLB_REG_GPIO_6_MODE_LEN) - 1) << GLB_REG_GPIO_6_MODE_POS))
+
+/* 0x8E0 : gpio_cfg7 */
+#define GLB_GPIO_CFG7_OFFSET (0x8E0)
+#define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE
+#define GLB_REG_GPIO_7_IE_POS (0U)
+#define GLB_REG_GPIO_7_IE_LEN (1U)
+#define GLB_REG_GPIO_7_IE_MSK (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
+#define GLB_REG_GPIO_7_IE_UMSK (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
+#define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT
+#define GLB_REG_GPIO_7_SMT_POS (1U)
+#define GLB_REG_GPIO_7_SMT_LEN (1U)
+#define GLB_REG_GPIO_7_SMT_MSK (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
+#define GLB_REG_GPIO_7_SMT_UMSK (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
+#define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV
+#define GLB_REG_GPIO_7_DRV_POS (2U)
+#define GLB_REG_GPIO_7_DRV_LEN (2U)
+#define GLB_REG_GPIO_7_DRV_MSK (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
+#define GLB_REG_GPIO_7_DRV_UMSK (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
+#define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU
+#define GLB_REG_GPIO_7_PU_POS (4U)
+#define GLB_REG_GPIO_7_PU_LEN (1U)
+#define GLB_REG_GPIO_7_PU_MSK (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
+#define GLB_REG_GPIO_7_PU_UMSK (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
+#define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD
+#define GLB_REG_GPIO_7_PD_POS (5U)
+#define GLB_REG_GPIO_7_PD_LEN (1U)
+#define GLB_REG_GPIO_7_PD_MSK (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
+#define GLB_REG_GPIO_7_PD_UMSK (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
+#define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE
+#define GLB_REG_GPIO_7_OE_POS (6U)
+#define GLB_REG_GPIO_7_OE_LEN (1U)
+#define GLB_REG_GPIO_7_OE_MSK (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
+#define GLB_REG_GPIO_7_OE_UMSK (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
+#define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL
+#define GLB_REG_GPIO_7_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_7_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_7_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
+#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))
+#define GLB_REG_GPIO_7_INT_MODE_SET GLB_REG_GPIO_7_INT_MODE_SET
+#define GLB_REG_GPIO_7_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_7_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_7_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_7_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_7_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_7_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_7_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_7_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_7_INT_CLR GLB_REG_GPIO_7_INT_CLR
+#define GLB_REG_GPIO_7_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_7_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_7_INT_CLR_MSK (((1U << GLB_REG_GPIO_7_INT_CLR_LEN) - 1) << GLB_REG_GPIO_7_INT_CLR_POS)
+#define GLB_REG_GPIO_7_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_7_INT_CLR_LEN) - 1) << GLB_REG_GPIO_7_INT_CLR_POS))
+#define GLB_GPIO_7_INT_STAT GLB_GPIO_7_INT_STAT
+#define GLB_GPIO_7_INT_STAT_POS (21U)
+#define GLB_GPIO_7_INT_STAT_LEN (1U)
+#define GLB_GPIO_7_INT_STAT_MSK (((1U << GLB_GPIO_7_INT_STAT_LEN) - 1) << GLB_GPIO_7_INT_STAT_POS)
+#define GLB_GPIO_7_INT_STAT_UMSK (~(((1U << GLB_GPIO_7_INT_STAT_LEN) - 1) << GLB_GPIO_7_INT_STAT_POS))
+#define GLB_REG_GPIO_7_INT_MASK GLB_REG_GPIO_7_INT_MASK
+#define GLB_REG_GPIO_7_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_7_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_7_INT_MASK_MSK (((1U << GLB_REG_GPIO_7_INT_MASK_LEN) - 1) << GLB_REG_GPIO_7_INT_MASK_POS)
+#define GLB_REG_GPIO_7_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_7_INT_MASK_LEN) - 1) << GLB_REG_GPIO_7_INT_MASK_POS))
+#define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O
+#define GLB_REG_GPIO_7_O_POS (24U)
+#define GLB_REG_GPIO_7_O_LEN (1U)
+#define GLB_REG_GPIO_7_O_MSK (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
+#define GLB_REG_GPIO_7_O_UMSK (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
+#define GLB_REG_GPIO_7_SET GLB_REG_GPIO_7_SET
+#define GLB_REG_GPIO_7_SET_POS (25U)
+#define GLB_REG_GPIO_7_SET_LEN (1U)
+#define GLB_REG_GPIO_7_SET_MSK (((1U << GLB_REG_GPIO_7_SET_LEN) - 1) << GLB_REG_GPIO_7_SET_POS)
+#define GLB_REG_GPIO_7_SET_UMSK (~(((1U << GLB_REG_GPIO_7_SET_LEN) - 1) << GLB_REG_GPIO_7_SET_POS))
+#define GLB_REG_GPIO_7_CLR GLB_REG_GPIO_7_CLR
+#define GLB_REG_GPIO_7_CLR_POS (26U)
+#define GLB_REG_GPIO_7_CLR_LEN (1U)
+#define GLB_REG_GPIO_7_CLR_MSK (((1U << GLB_REG_GPIO_7_CLR_LEN) - 1) << GLB_REG_GPIO_7_CLR_POS)
+#define GLB_REG_GPIO_7_CLR_UMSK (~(((1U << GLB_REG_GPIO_7_CLR_LEN) - 1) << GLB_REG_GPIO_7_CLR_POS))
+#define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I
+#define GLB_REG_GPIO_7_I_POS (28U)
+#define GLB_REG_GPIO_7_I_LEN (1U)
+#define GLB_REG_GPIO_7_I_MSK (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
+#define GLB_REG_GPIO_7_I_UMSK (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
+#define GLB_REG_GPIO_7_MODE GLB_REG_GPIO_7_MODE
+#define GLB_REG_GPIO_7_MODE_POS (30U)
+#define GLB_REG_GPIO_7_MODE_LEN (2U)
+#define GLB_REG_GPIO_7_MODE_MSK (((1U << GLB_REG_GPIO_7_MODE_LEN) - 1) << GLB_REG_GPIO_7_MODE_POS)
+#define GLB_REG_GPIO_7_MODE_UMSK (~(((1U << GLB_REG_GPIO_7_MODE_LEN) - 1) << GLB_REG_GPIO_7_MODE_POS))
+
+/* 0x8E4 : gpio_cfg8 */
+#define GLB_GPIO_CFG8_OFFSET (0x8E4)
+#define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE
+#define GLB_REG_GPIO_8_IE_POS (0U)
+#define GLB_REG_GPIO_8_IE_LEN (1U)
+#define GLB_REG_GPIO_8_IE_MSK (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
+#define GLB_REG_GPIO_8_IE_UMSK (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
+#define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT
+#define GLB_REG_GPIO_8_SMT_POS (1U)
+#define GLB_REG_GPIO_8_SMT_LEN (1U)
+#define GLB_REG_GPIO_8_SMT_MSK (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
+#define GLB_REG_GPIO_8_SMT_UMSK (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
+#define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV
+#define GLB_REG_GPIO_8_DRV_POS (2U)
+#define GLB_REG_GPIO_8_DRV_LEN (2U)
+#define GLB_REG_GPIO_8_DRV_MSK (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
+#define GLB_REG_GPIO_8_DRV_UMSK (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
+#define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU
+#define GLB_REG_GPIO_8_PU_POS (4U)
+#define GLB_REG_GPIO_8_PU_LEN (1U)
+#define GLB_REG_GPIO_8_PU_MSK (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
+#define GLB_REG_GPIO_8_PU_UMSK (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
+#define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD
+#define GLB_REG_GPIO_8_PD_POS (5U)
+#define GLB_REG_GPIO_8_PD_LEN (1U)
+#define GLB_REG_GPIO_8_PD_MSK (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
+#define GLB_REG_GPIO_8_PD_UMSK (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
+#define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE
+#define GLB_REG_GPIO_8_OE_POS (6U)
+#define GLB_REG_GPIO_8_OE_LEN (1U)
+#define GLB_REG_GPIO_8_OE_MSK (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
+#define GLB_REG_GPIO_8_OE_UMSK (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
+#define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL
+#define GLB_REG_GPIO_8_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_8_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_8_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
+#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
+#define GLB_REG_GPIO_8_INT_MODE_SET GLB_REG_GPIO_8_INT_MODE_SET
+#define GLB_REG_GPIO_8_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_8_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_8_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_8_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_8_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_8_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_8_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_8_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_8_INT_CLR GLB_REG_GPIO_8_INT_CLR
+#define GLB_REG_GPIO_8_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_8_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_8_INT_CLR_MSK (((1U << GLB_REG_GPIO_8_INT_CLR_LEN) - 1) << GLB_REG_GPIO_8_INT_CLR_POS)
+#define GLB_REG_GPIO_8_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_8_INT_CLR_LEN) - 1) << GLB_REG_GPIO_8_INT_CLR_POS))
+#define GLB_GPIO_8_INT_STAT GLB_GPIO_8_INT_STAT
+#define GLB_GPIO_8_INT_STAT_POS (21U)
+#define GLB_GPIO_8_INT_STAT_LEN (1U)
+#define GLB_GPIO_8_INT_STAT_MSK (((1U << GLB_GPIO_8_INT_STAT_LEN) - 1) << GLB_GPIO_8_INT_STAT_POS)
+#define GLB_GPIO_8_INT_STAT_UMSK (~(((1U << GLB_GPIO_8_INT_STAT_LEN) - 1) << GLB_GPIO_8_INT_STAT_POS))
+#define GLB_REG_GPIO_8_INT_MASK GLB_REG_GPIO_8_INT_MASK
+#define GLB_REG_GPIO_8_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_8_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_8_INT_MASK_MSK (((1U << GLB_REG_GPIO_8_INT_MASK_LEN) - 1) << GLB_REG_GPIO_8_INT_MASK_POS)
+#define GLB_REG_GPIO_8_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_8_INT_MASK_LEN) - 1) << GLB_REG_GPIO_8_INT_MASK_POS))
+#define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O
+#define GLB_REG_GPIO_8_O_POS (24U)
+#define GLB_REG_GPIO_8_O_LEN (1U)
+#define GLB_REG_GPIO_8_O_MSK (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
+#define GLB_REG_GPIO_8_O_UMSK (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
+#define GLB_REG_GPIO_8_SET GLB_REG_GPIO_8_SET
+#define GLB_REG_GPIO_8_SET_POS (25U)
+#define GLB_REG_GPIO_8_SET_LEN (1U)
+#define GLB_REG_GPIO_8_SET_MSK (((1U << GLB_REG_GPIO_8_SET_LEN) - 1) << GLB_REG_GPIO_8_SET_POS)
+#define GLB_REG_GPIO_8_SET_UMSK (~(((1U << GLB_REG_GPIO_8_SET_LEN) - 1) << GLB_REG_GPIO_8_SET_POS))
+#define GLB_REG_GPIO_8_CLR GLB_REG_GPIO_8_CLR
+#define GLB_REG_GPIO_8_CLR_POS (26U)
+#define GLB_REG_GPIO_8_CLR_LEN (1U)
+#define GLB_REG_GPIO_8_CLR_MSK (((1U << GLB_REG_GPIO_8_CLR_LEN) - 1) << GLB_REG_GPIO_8_CLR_POS)
+#define GLB_REG_GPIO_8_CLR_UMSK (~(((1U << GLB_REG_GPIO_8_CLR_LEN) - 1) << GLB_REG_GPIO_8_CLR_POS))
+#define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I
+#define GLB_REG_GPIO_8_I_POS (28U)
+#define GLB_REG_GPIO_8_I_LEN (1U)
+#define GLB_REG_GPIO_8_I_MSK (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
+#define GLB_REG_GPIO_8_I_UMSK (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
+#define GLB_REG_GPIO_8_MODE GLB_REG_GPIO_8_MODE
+#define GLB_REG_GPIO_8_MODE_POS (30U)
+#define GLB_REG_GPIO_8_MODE_LEN (2U)
+#define GLB_REG_GPIO_8_MODE_MSK (((1U << GLB_REG_GPIO_8_MODE_LEN) - 1) << GLB_REG_GPIO_8_MODE_POS)
+#define GLB_REG_GPIO_8_MODE_UMSK (~(((1U << GLB_REG_GPIO_8_MODE_LEN) - 1) << GLB_REG_GPIO_8_MODE_POS))
+
+/* 0x8E8 : gpio_cfg9 */
+#define GLB_GPIO_CFG9_OFFSET (0x8E8)
+#define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE
+#define GLB_REG_GPIO_9_IE_POS (0U)
+#define GLB_REG_GPIO_9_IE_LEN (1U)
+#define GLB_REG_GPIO_9_IE_MSK (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
+#define GLB_REG_GPIO_9_IE_UMSK (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
+#define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT
+#define GLB_REG_GPIO_9_SMT_POS (1U)
+#define GLB_REG_GPIO_9_SMT_LEN (1U)
+#define GLB_REG_GPIO_9_SMT_MSK (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
+#define GLB_REG_GPIO_9_SMT_UMSK (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
+#define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV
+#define GLB_REG_GPIO_9_DRV_POS (2U)
+#define GLB_REG_GPIO_9_DRV_LEN (2U)
+#define GLB_REG_GPIO_9_DRV_MSK (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
+#define GLB_REG_GPIO_9_DRV_UMSK (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
+#define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU
+#define GLB_REG_GPIO_9_PU_POS (4U)
+#define GLB_REG_GPIO_9_PU_LEN (1U)
+#define GLB_REG_GPIO_9_PU_MSK (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
+#define GLB_REG_GPIO_9_PU_UMSK (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
+#define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD
+#define GLB_REG_GPIO_9_PD_POS (5U)
+#define GLB_REG_GPIO_9_PD_LEN (1U)
+#define GLB_REG_GPIO_9_PD_MSK (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
+#define GLB_REG_GPIO_9_PD_UMSK (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
+#define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE
+#define GLB_REG_GPIO_9_OE_POS (6U)
+#define GLB_REG_GPIO_9_OE_LEN (1U)
+#define GLB_REG_GPIO_9_OE_MSK (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
+#define GLB_REG_GPIO_9_OE_UMSK (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
+#define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL
+#define GLB_REG_GPIO_9_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_9_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_9_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
+#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))
+#define GLB_REG_GPIO_9_INT_MODE_SET GLB_REG_GPIO_9_INT_MODE_SET
+#define GLB_REG_GPIO_9_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_9_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_9_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_9_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_9_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_9_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_9_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_9_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_9_INT_CLR GLB_REG_GPIO_9_INT_CLR
+#define GLB_REG_GPIO_9_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_9_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_9_INT_CLR_MSK (((1U << GLB_REG_GPIO_9_INT_CLR_LEN) - 1) << GLB_REG_GPIO_9_INT_CLR_POS)
+#define GLB_REG_GPIO_9_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_9_INT_CLR_LEN) - 1) << GLB_REG_GPIO_9_INT_CLR_POS))
+#define GLB_GPIO_9_INT_STAT GLB_GPIO_9_INT_STAT
+#define GLB_GPIO_9_INT_STAT_POS (21U)
+#define GLB_GPIO_9_INT_STAT_LEN (1U)
+#define GLB_GPIO_9_INT_STAT_MSK (((1U << GLB_GPIO_9_INT_STAT_LEN) - 1) << GLB_GPIO_9_INT_STAT_POS)
+#define GLB_GPIO_9_INT_STAT_UMSK (~(((1U << GLB_GPIO_9_INT_STAT_LEN) - 1) << GLB_GPIO_9_INT_STAT_POS))
+#define GLB_REG_GPIO_9_INT_MASK GLB_REG_GPIO_9_INT_MASK
+#define GLB_REG_GPIO_9_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_9_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_9_INT_MASK_MSK (((1U << GLB_REG_GPIO_9_INT_MASK_LEN) - 1) << GLB_REG_GPIO_9_INT_MASK_POS)
+#define GLB_REG_GPIO_9_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_9_INT_MASK_LEN) - 1) << GLB_REG_GPIO_9_INT_MASK_POS))
+#define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O
+#define GLB_REG_GPIO_9_O_POS (24U)
+#define GLB_REG_GPIO_9_O_LEN (1U)
+#define GLB_REG_GPIO_9_O_MSK (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
+#define GLB_REG_GPIO_9_O_UMSK (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
+#define GLB_REG_GPIO_9_SET GLB_REG_GPIO_9_SET
+#define GLB_REG_GPIO_9_SET_POS (25U)
+#define GLB_REG_GPIO_9_SET_LEN (1U)
+#define GLB_REG_GPIO_9_SET_MSK (((1U << GLB_REG_GPIO_9_SET_LEN) - 1) << GLB_REG_GPIO_9_SET_POS)
+#define GLB_REG_GPIO_9_SET_UMSK (~(((1U << GLB_REG_GPIO_9_SET_LEN) - 1) << GLB_REG_GPIO_9_SET_POS))
+#define GLB_REG_GPIO_9_CLR GLB_REG_GPIO_9_CLR
+#define GLB_REG_GPIO_9_CLR_POS (26U)
+#define GLB_REG_GPIO_9_CLR_LEN (1U)
+#define GLB_REG_GPIO_9_CLR_MSK (((1U << GLB_REG_GPIO_9_CLR_LEN) - 1) << GLB_REG_GPIO_9_CLR_POS)
+#define GLB_REG_GPIO_9_CLR_UMSK (~(((1U << GLB_REG_GPIO_9_CLR_LEN) - 1) << GLB_REG_GPIO_9_CLR_POS))
+#define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I
+#define GLB_REG_GPIO_9_I_POS (28U)
+#define GLB_REG_GPIO_9_I_LEN (1U)
+#define GLB_REG_GPIO_9_I_MSK (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
+#define GLB_REG_GPIO_9_I_UMSK (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
+#define GLB_REG_GPIO_9_MODE GLB_REG_GPIO_9_MODE
+#define GLB_REG_GPIO_9_MODE_POS (30U)
+#define GLB_REG_GPIO_9_MODE_LEN (2U)
+#define GLB_REG_GPIO_9_MODE_MSK (((1U << GLB_REG_GPIO_9_MODE_LEN) - 1) << GLB_REG_GPIO_9_MODE_POS)
+#define GLB_REG_GPIO_9_MODE_UMSK (~(((1U << GLB_REG_GPIO_9_MODE_LEN) - 1) << GLB_REG_GPIO_9_MODE_POS))
+
+/* 0x8EC : gpio_cfg10 */
+#define GLB_GPIO_CFG10_OFFSET (0x8EC)
+#define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE
+#define GLB_REG_GPIO_10_IE_POS (0U)
+#define GLB_REG_GPIO_10_IE_LEN (1U)
+#define GLB_REG_GPIO_10_IE_MSK (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
+#define GLB_REG_GPIO_10_IE_UMSK (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
+#define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT
+#define GLB_REG_GPIO_10_SMT_POS (1U)
+#define GLB_REG_GPIO_10_SMT_LEN (1U)
+#define GLB_REG_GPIO_10_SMT_MSK (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
+#define GLB_REG_GPIO_10_SMT_UMSK (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
+#define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV
+#define GLB_REG_GPIO_10_DRV_POS (2U)
+#define GLB_REG_GPIO_10_DRV_LEN (2U)
+#define GLB_REG_GPIO_10_DRV_MSK (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
+#define GLB_REG_GPIO_10_DRV_UMSK (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
+#define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU
+#define GLB_REG_GPIO_10_PU_POS (4U)
+#define GLB_REG_GPIO_10_PU_LEN (1U)
+#define GLB_REG_GPIO_10_PU_MSK (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
+#define GLB_REG_GPIO_10_PU_UMSK (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
+#define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD
+#define GLB_REG_GPIO_10_PD_POS (5U)
+#define GLB_REG_GPIO_10_PD_LEN (1U)
+#define GLB_REG_GPIO_10_PD_MSK (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
+#define GLB_REG_GPIO_10_PD_UMSK (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
+#define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE
+#define GLB_REG_GPIO_10_OE_POS (6U)
+#define GLB_REG_GPIO_10_OE_LEN (1U)
+#define GLB_REG_GPIO_10_OE_MSK (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
+#define GLB_REG_GPIO_10_OE_UMSK (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
+#define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL
+#define GLB_REG_GPIO_10_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_10_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_10_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
+#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS))
+#define GLB_REG_GPIO_10_INT_MODE_SET GLB_REG_GPIO_10_INT_MODE_SET
+#define GLB_REG_GPIO_10_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_10_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_10_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_10_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_10_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_10_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_10_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_10_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_10_INT_CLR GLB_REG_GPIO_10_INT_CLR
+#define GLB_REG_GPIO_10_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_10_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_10_INT_CLR_MSK (((1U << GLB_REG_GPIO_10_INT_CLR_LEN) - 1) << GLB_REG_GPIO_10_INT_CLR_POS)
+#define GLB_REG_GPIO_10_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_10_INT_CLR_LEN) - 1) << GLB_REG_GPIO_10_INT_CLR_POS))
+#define GLB_GPIO_10_INT_STAT GLB_GPIO_10_INT_STAT
+#define GLB_GPIO_10_INT_STAT_POS (21U)
+#define GLB_GPIO_10_INT_STAT_LEN (1U)
+#define GLB_GPIO_10_INT_STAT_MSK (((1U << GLB_GPIO_10_INT_STAT_LEN) - 1) << GLB_GPIO_10_INT_STAT_POS)
+#define GLB_GPIO_10_INT_STAT_UMSK (~(((1U << GLB_GPIO_10_INT_STAT_LEN) - 1) << GLB_GPIO_10_INT_STAT_POS))
+#define GLB_REG_GPIO_10_INT_MASK GLB_REG_GPIO_10_INT_MASK
+#define GLB_REG_GPIO_10_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_10_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_10_INT_MASK_MSK (((1U << GLB_REG_GPIO_10_INT_MASK_LEN) - 1) << GLB_REG_GPIO_10_INT_MASK_POS)
+#define GLB_REG_GPIO_10_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_10_INT_MASK_LEN) - 1) << GLB_REG_GPIO_10_INT_MASK_POS))
+#define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O
+#define GLB_REG_GPIO_10_O_POS (24U)
+#define GLB_REG_GPIO_10_O_LEN (1U)
+#define GLB_REG_GPIO_10_O_MSK (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
+#define GLB_REG_GPIO_10_O_UMSK (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
+#define GLB_REG_GPIO_10_SET GLB_REG_GPIO_10_SET
+#define GLB_REG_GPIO_10_SET_POS (25U)
+#define GLB_REG_GPIO_10_SET_LEN (1U)
+#define GLB_REG_GPIO_10_SET_MSK (((1U << GLB_REG_GPIO_10_SET_LEN) - 1) << GLB_REG_GPIO_10_SET_POS)
+#define GLB_REG_GPIO_10_SET_UMSK (~(((1U << GLB_REG_GPIO_10_SET_LEN) - 1) << GLB_REG_GPIO_10_SET_POS))
+#define GLB_REG_GPIO_10_CLR GLB_REG_GPIO_10_CLR
+#define GLB_REG_GPIO_10_CLR_POS (26U)
+#define GLB_REG_GPIO_10_CLR_LEN (1U)
+#define GLB_REG_GPIO_10_CLR_MSK (((1U << GLB_REG_GPIO_10_CLR_LEN) - 1) << GLB_REG_GPIO_10_CLR_POS)
+#define GLB_REG_GPIO_10_CLR_UMSK (~(((1U << GLB_REG_GPIO_10_CLR_LEN) - 1) << GLB_REG_GPIO_10_CLR_POS))
+#define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I
+#define GLB_REG_GPIO_10_I_POS (28U)
+#define GLB_REG_GPIO_10_I_LEN (1U)
+#define GLB_REG_GPIO_10_I_MSK (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
+#define GLB_REG_GPIO_10_I_UMSK (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
+#define GLB_REG_GPIO_10_MODE GLB_REG_GPIO_10_MODE
+#define GLB_REG_GPIO_10_MODE_POS (30U)
+#define GLB_REG_GPIO_10_MODE_LEN (2U)
+#define GLB_REG_GPIO_10_MODE_MSK (((1U << GLB_REG_GPIO_10_MODE_LEN) - 1) << GLB_REG_GPIO_10_MODE_POS)
+#define GLB_REG_GPIO_10_MODE_UMSK (~(((1U << GLB_REG_GPIO_10_MODE_LEN) - 1) << GLB_REG_GPIO_10_MODE_POS))
+
+/* 0x8F0 : gpio_cfg11 */
+#define GLB_GPIO_CFG11_OFFSET (0x8F0)
+#define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE
+#define GLB_REG_GPIO_11_IE_POS (0U)
+#define GLB_REG_GPIO_11_IE_LEN (1U)
+#define GLB_REG_GPIO_11_IE_MSK (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
+#define GLB_REG_GPIO_11_IE_UMSK (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
+#define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT
+#define GLB_REG_GPIO_11_SMT_POS (1U)
+#define GLB_REG_GPIO_11_SMT_LEN (1U)
+#define GLB_REG_GPIO_11_SMT_MSK (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
+#define GLB_REG_GPIO_11_SMT_UMSK (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
+#define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV
+#define GLB_REG_GPIO_11_DRV_POS (2U)
+#define GLB_REG_GPIO_11_DRV_LEN (2U)
+#define GLB_REG_GPIO_11_DRV_MSK (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
+#define GLB_REG_GPIO_11_DRV_UMSK (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
+#define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU
+#define GLB_REG_GPIO_11_PU_POS (4U)
+#define GLB_REG_GPIO_11_PU_LEN (1U)
+#define GLB_REG_GPIO_11_PU_MSK (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
+#define GLB_REG_GPIO_11_PU_UMSK (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
+#define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD
+#define GLB_REG_GPIO_11_PD_POS (5U)
+#define GLB_REG_GPIO_11_PD_LEN (1U)
+#define GLB_REG_GPIO_11_PD_MSK (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
+#define GLB_REG_GPIO_11_PD_UMSK (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
+#define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE
+#define GLB_REG_GPIO_11_OE_POS (6U)
+#define GLB_REG_GPIO_11_OE_LEN (1U)
+#define GLB_REG_GPIO_11_OE_MSK (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
+#define GLB_REG_GPIO_11_OE_UMSK (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
+#define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL
+#define GLB_REG_GPIO_11_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_11_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_11_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
+#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS))
+#define GLB_REG_GPIO_11_INT_MODE_SET GLB_REG_GPIO_11_INT_MODE_SET
+#define GLB_REG_GPIO_11_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_11_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_11_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_11_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_11_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_11_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_11_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_11_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_11_INT_CLR GLB_REG_GPIO_11_INT_CLR
+#define GLB_REG_GPIO_11_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_11_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_11_INT_CLR_MSK (((1U << GLB_REG_GPIO_11_INT_CLR_LEN) - 1) << GLB_REG_GPIO_11_INT_CLR_POS)
+#define GLB_REG_GPIO_11_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_11_INT_CLR_LEN) - 1) << GLB_REG_GPIO_11_INT_CLR_POS))
+#define GLB_GPIO_11_INT_STAT GLB_GPIO_11_INT_STAT
+#define GLB_GPIO_11_INT_STAT_POS (21U)
+#define GLB_GPIO_11_INT_STAT_LEN (1U)
+#define GLB_GPIO_11_INT_STAT_MSK (((1U << GLB_GPIO_11_INT_STAT_LEN) - 1) << GLB_GPIO_11_INT_STAT_POS)
+#define GLB_GPIO_11_INT_STAT_UMSK (~(((1U << GLB_GPIO_11_INT_STAT_LEN) - 1) << GLB_GPIO_11_INT_STAT_POS))
+#define GLB_REG_GPIO_11_INT_MASK GLB_REG_GPIO_11_INT_MASK
+#define GLB_REG_GPIO_11_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_11_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_11_INT_MASK_MSK (((1U << GLB_REG_GPIO_11_INT_MASK_LEN) - 1) << GLB_REG_GPIO_11_INT_MASK_POS)
+#define GLB_REG_GPIO_11_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_11_INT_MASK_LEN) - 1) << GLB_REG_GPIO_11_INT_MASK_POS))
+#define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O
+#define GLB_REG_GPIO_11_O_POS (24U)
+#define GLB_REG_GPIO_11_O_LEN (1U)
+#define GLB_REG_GPIO_11_O_MSK (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
+#define GLB_REG_GPIO_11_O_UMSK (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
+#define GLB_REG_GPIO_11_SET GLB_REG_GPIO_11_SET
+#define GLB_REG_GPIO_11_SET_POS (25U)
+#define GLB_REG_GPIO_11_SET_LEN (1U)
+#define GLB_REG_GPIO_11_SET_MSK (((1U << GLB_REG_GPIO_11_SET_LEN) - 1) << GLB_REG_GPIO_11_SET_POS)
+#define GLB_REG_GPIO_11_SET_UMSK (~(((1U << GLB_REG_GPIO_11_SET_LEN) - 1) << GLB_REG_GPIO_11_SET_POS))
+#define GLB_REG_GPIO_11_CLR GLB_REG_GPIO_11_CLR
+#define GLB_REG_GPIO_11_CLR_POS (26U)
+#define GLB_REG_GPIO_11_CLR_LEN (1U)
+#define GLB_REG_GPIO_11_CLR_MSK (((1U << GLB_REG_GPIO_11_CLR_LEN) - 1) << GLB_REG_GPIO_11_CLR_POS)
+#define GLB_REG_GPIO_11_CLR_UMSK (~(((1U << GLB_REG_GPIO_11_CLR_LEN) - 1) << GLB_REG_GPIO_11_CLR_POS))
+#define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I
+#define GLB_REG_GPIO_11_I_POS (28U)
+#define GLB_REG_GPIO_11_I_LEN (1U)
+#define GLB_REG_GPIO_11_I_MSK (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
+#define GLB_REG_GPIO_11_I_UMSK (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
+#define GLB_REG_GPIO_11_MODE GLB_REG_GPIO_11_MODE
+#define GLB_REG_GPIO_11_MODE_POS (30U)
+#define GLB_REG_GPIO_11_MODE_LEN (2U)
+#define GLB_REG_GPIO_11_MODE_MSK (((1U << GLB_REG_GPIO_11_MODE_LEN) - 1) << GLB_REG_GPIO_11_MODE_POS)
+#define GLB_REG_GPIO_11_MODE_UMSK (~(((1U << GLB_REG_GPIO_11_MODE_LEN) - 1) << GLB_REG_GPIO_11_MODE_POS))
+
+/* 0x8F4 : gpio_cfg12 */
+#define GLB_GPIO_CFG12_OFFSET (0x8F4)
+#define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE
+#define GLB_REG_GPIO_12_IE_POS (0U)
+#define GLB_REG_GPIO_12_IE_LEN (1U)
+#define GLB_REG_GPIO_12_IE_MSK (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
+#define GLB_REG_GPIO_12_IE_UMSK (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
+#define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT
+#define GLB_REG_GPIO_12_SMT_POS (1U)
+#define GLB_REG_GPIO_12_SMT_LEN (1U)
+#define GLB_REG_GPIO_12_SMT_MSK (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
+#define GLB_REG_GPIO_12_SMT_UMSK (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
+#define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV
+#define GLB_REG_GPIO_12_DRV_POS (2U)
+#define GLB_REG_GPIO_12_DRV_LEN (2U)
+#define GLB_REG_GPIO_12_DRV_MSK (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
+#define GLB_REG_GPIO_12_DRV_UMSK (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
+#define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU
+#define GLB_REG_GPIO_12_PU_POS (4U)
+#define GLB_REG_GPIO_12_PU_LEN (1U)
+#define GLB_REG_GPIO_12_PU_MSK (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
+#define GLB_REG_GPIO_12_PU_UMSK (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
+#define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD
+#define GLB_REG_GPIO_12_PD_POS (5U)
+#define GLB_REG_GPIO_12_PD_LEN (1U)
+#define GLB_REG_GPIO_12_PD_MSK (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
+#define GLB_REG_GPIO_12_PD_UMSK (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
+#define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE
+#define GLB_REG_GPIO_12_OE_POS (6U)
+#define GLB_REG_GPIO_12_OE_LEN (1U)
+#define GLB_REG_GPIO_12_OE_MSK (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
+#define GLB_REG_GPIO_12_OE_UMSK (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
+#define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL
+#define GLB_REG_GPIO_12_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_12_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_12_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
+#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS))
+#define GLB_REG_GPIO_12_INT_MODE_SET GLB_REG_GPIO_12_INT_MODE_SET
+#define GLB_REG_GPIO_12_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_12_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_12_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_12_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_12_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_12_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_12_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_12_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_12_INT_CLR GLB_REG_GPIO_12_INT_CLR
+#define GLB_REG_GPIO_12_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_12_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_12_INT_CLR_MSK (((1U << GLB_REG_GPIO_12_INT_CLR_LEN) - 1) << GLB_REG_GPIO_12_INT_CLR_POS)
+#define GLB_REG_GPIO_12_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_12_INT_CLR_LEN) - 1) << GLB_REG_GPIO_12_INT_CLR_POS))
+#define GLB_GPIO_12_INT_STAT GLB_GPIO_12_INT_STAT
+#define GLB_GPIO_12_INT_STAT_POS (21U)
+#define GLB_GPIO_12_INT_STAT_LEN (1U)
+#define GLB_GPIO_12_INT_STAT_MSK (((1U << GLB_GPIO_12_INT_STAT_LEN) - 1) << GLB_GPIO_12_INT_STAT_POS)
+#define GLB_GPIO_12_INT_STAT_UMSK (~(((1U << GLB_GPIO_12_INT_STAT_LEN) - 1) << GLB_GPIO_12_INT_STAT_POS))
+#define GLB_REG_GPIO_12_INT_MASK GLB_REG_GPIO_12_INT_MASK
+#define GLB_REG_GPIO_12_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_12_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_12_INT_MASK_MSK (((1U << GLB_REG_GPIO_12_INT_MASK_LEN) - 1) << GLB_REG_GPIO_12_INT_MASK_POS)
+#define GLB_REG_GPIO_12_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_12_INT_MASK_LEN) - 1) << GLB_REG_GPIO_12_INT_MASK_POS))
+#define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O
+#define GLB_REG_GPIO_12_O_POS (24U)
+#define GLB_REG_GPIO_12_O_LEN (1U)
+#define GLB_REG_GPIO_12_O_MSK (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
+#define GLB_REG_GPIO_12_O_UMSK (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
+#define GLB_REG_GPIO_12_SET GLB_REG_GPIO_12_SET
+#define GLB_REG_GPIO_12_SET_POS (25U)
+#define GLB_REG_GPIO_12_SET_LEN (1U)
+#define GLB_REG_GPIO_12_SET_MSK (((1U << GLB_REG_GPIO_12_SET_LEN) - 1) << GLB_REG_GPIO_12_SET_POS)
+#define GLB_REG_GPIO_12_SET_UMSK (~(((1U << GLB_REG_GPIO_12_SET_LEN) - 1) << GLB_REG_GPIO_12_SET_POS))
+#define GLB_REG_GPIO_12_CLR GLB_REG_GPIO_12_CLR
+#define GLB_REG_GPIO_12_CLR_POS (26U)
+#define GLB_REG_GPIO_12_CLR_LEN (1U)
+#define GLB_REG_GPIO_12_CLR_MSK (((1U << GLB_REG_GPIO_12_CLR_LEN) - 1) << GLB_REG_GPIO_12_CLR_POS)
+#define GLB_REG_GPIO_12_CLR_UMSK (~(((1U << GLB_REG_GPIO_12_CLR_LEN) - 1) << GLB_REG_GPIO_12_CLR_POS))
+#define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I
+#define GLB_REG_GPIO_12_I_POS (28U)
+#define GLB_REG_GPIO_12_I_LEN (1U)
+#define GLB_REG_GPIO_12_I_MSK (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
+#define GLB_REG_GPIO_12_I_UMSK (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
+#define GLB_REG_GPIO_12_MODE GLB_REG_GPIO_12_MODE
+#define GLB_REG_GPIO_12_MODE_POS (30U)
+#define GLB_REG_GPIO_12_MODE_LEN (2U)
+#define GLB_REG_GPIO_12_MODE_MSK (((1U << GLB_REG_GPIO_12_MODE_LEN) - 1) << GLB_REG_GPIO_12_MODE_POS)
+#define GLB_REG_GPIO_12_MODE_UMSK (~(((1U << GLB_REG_GPIO_12_MODE_LEN) - 1) << GLB_REG_GPIO_12_MODE_POS))
+
+/* 0x8F8 : gpio_cfg13 */
+#define GLB_GPIO_CFG13_OFFSET (0x8F8)
+#define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE
+#define GLB_REG_GPIO_13_IE_POS (0U)
+#define GLB_REG_GPIO_13_IE_LEN (1U)
+#define GLB_REG_GPIO_13_IE_MSK (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
+#define GLB_REG_GPIO_13_IE_UMSK (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
+#define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT
+#define GLB_REG_GPIO_13_SMT_POS (1U)
+#define GLB_REG_GPIO_13_SMT_LEN (1U)
+#define GLB_REG_GPIO_13_SMT_MSK (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
+#define GLB_REG_GPIO_13_SMT_UMSK (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
+#define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV
+#define GLB_REG_GPIO_13_DRV_POS (2U)
+#define GLB_REG_GPIO_13_DRV_LEN (2U)
+#define GLB_REG_GPIO_13_DRV_MSK (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
+#define GLB_REG_GPIO_13_DRV_UMSK (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
+#define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU
+#define GLB_REG_GPIO_13_PU_POS (4U)
+#define GLB_REG_GPIO_13_PU_LEN (1U)
+#define GLB_REG_GPIO_13_PU_MSK (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
+#define GLB_REG_GPIO_13_PU_UMSK (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
+#define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD
+#define GLB_REG_GPIO_13_PD_POS (5U)
+#define GLB_REG_GPIO_13_PD_LEN (1U)
+#define GLB_REG_GPIO_13_PD_MSK (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
+#define GLB_REG_GPIO_13_PD_UMSK (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
+#define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE
+#define GLB_REG_GPIO_13_OE_POS (6U)
+#define GLB_REG_GPIO_13_OE_LEN (1U)
+#define GLB_REG_GPIO_13_OE_MSK (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
+#define GLB_REG_GPIO_13_OE_UMSK (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
+#define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL
+#define GLB_REG_GPIO_13_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_13_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_13_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
+#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS))
+#define GLB_REG_GPIO_13_INT_MODE_SET GLB_REG_GPIO_13_INT_MODE_SET
+#define GLB_REG_GPIO_13_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_13_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_13_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_13_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_13_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_13_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_13_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_13_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_13_INT_CLR GLB_REG_GPIO_13_INT_CLR
+#define GLB_REG_GPIO_13_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_13_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_13_INT_CLR_MSK (((1U << GLB_REG_GPIO_13_INT_CLR_LEN) - 1) << GLB_REG_GPIO_13_INT_CLR_POS)
+#define GLB_REG_GPIO_13_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_13_INT_CLR_LEN) - 1) << GLB_REG_GPIO_13_INT_CLR_POS))
+#define GLB_GPIO_13_INT_STAT GLB_GPIO_13_INT_STAT
+#define GLB_GPIO_13_INT_STAT_POS (21U)
+#define GLB_GPIO_13_INT_STAT_LEN (1U)
+#define GLB_GPIO_13_INT_STAT_MSK (((1U << GLB_GPIO_13_INT_STAT_LEN) - 1) << GLB_GPIO_13_INT_STAT_POS)
+#define GLB_GPIO_13_INT_STAT_UMSK (~(((1U << GLB_GPIO_13_INT_STAT_LEN) - 1) << GLB_GPIO_13_INT_STAT_POS))
+#define GLB_REG_GPIO_13_INT_MASK GLB_REG_GPIO_13_INT_MASK
+#define GLB_REG_GPIO_13_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_13_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_13_INT_MASK_MSK (((1U << GLB_REG_GPIO_13_INT_MASK_LEN) - 1) << GLB_REG_GPIO_13_INT_MASK_POS)
+#define GLB_REG_GPIO_13_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_13_INT_MASK_LEN) - 1) << GLB_REG_GPIO_13_INT_MASK_POS))
+#define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O
+#define GLB_REG_GPIO_13_O_POS (24U)
+#define GLB_REG_GPIO_13_O_LEN (1U)
+#define GLB_REG_GPIO_13_O_MSK (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
+#define GLB_REG_GPIO_13_O_UMSK (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
+#define GLB_REG_GPIO_13_SET GLB_REG_GPIO_13_SET
+#define GLB_REG_GPIO_13_SET_POS (25U)
+#define GLB_REG_GPIO_13_SET_LEN (1U)
+#define GLB_REG_GPIO_13_SET_MSK (((1U << GLB_REG_GPIO_13_SET_LEN) - 1) << GLB_REG_GPIO_13_SET_POS)
+#define GLB_REG_GPIO_13_SET_UMSK (~(((1U << GLB_REG_GPIO_13_SET_LEN) - 1) << GLB_REG_GPIO_13_SET_POS))
+#define GLB_REG_GPIO_13_CLR GLB_REG_GPIO_13_CLR
+#define GLB_REG_GPIO_13_CLR_POS (26U)
+#define GLB_REG_GPIO_13_CLR_LEN (1U)
+#define GLB_REG_GPIO_13_CLR_MSK (((1U << GLB_REG_GPIO_13_CLR_LEN) - 1) << GLB_REG_GPIO_13_CLR_POS)
+#define GLB_REG_GPIO_13_CLR_UMSK (~(((1U << GLB_REG_GPIO_13_CLR_LEN) - 1) << GLB_REG_GPIO_13_CLR_POS))
+#define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I
+#define GLB_REG_GPIO_13_I_POS (28U)
+#define GLB_REG_GPIO_13_I_LEN (1U)
+#define GLB_REG_GPIO_13_I_MSK (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
+#define GLB_REG_GPIO_13_I_UMSK (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
+#define GLB_REG_GPIO_13_MODE GLB_REG_GPIO_13_MODE
+#define GLB_REG_GPIO_13_MODE_POS (30U)
+#define GLB_REG_GPIO_13_MODE_LEN (2U)
+#define GLB_REG_GPIO_13_MODE_MSK (((1U << GLB_REG_GPIO_13_MODE_LEN) - 1) << GLB_REG_GPIO_13_MODE_POS)
+#define GLB_REG_GPIO_13_MODE_UMSK (~(((1U << GLB_REG_GPIO_13_MODE_LEN) - 1) << GLB_REG_GPIO_13_MODE_POS))
+
+/* 0x8FC : gpio_cfg14 */
+#define GLB_GPIO_CFG14_OFFSET (0x8FC)
+#define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE
+#define GLB_REG_GPIO_14_IE_POS (0U)
+#define GLB_REG_GPIO_14_IE_LEN (1U)
+#define GLB_REG_GPIO_14_IE_MSK (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
+#define GLB_REG_GPIO_14_IE_UMSK (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
+#define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT
+#define GLB_REG_GPIO_14_SMT_POS (1U)
+#define GLB_REG_GPIO_14_SMT_LEN (1U)
+#define GLB_REG_GPIO_14_SMT_MSK (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
+#define GLB_REG_GPIO_14_SMT_UMSK (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
+#define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV
+#define GLB_REG_GPIO_14_DRV_POS (2U)
+#define GLB_REG_GPIO_14_DRV_LEN (2U)
+#define GLB_REG_GPIO_14_DRV_MSK (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
+#define GLB_REG_GPIO_14_DRV_UMSK (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
+#define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU
+#define GLB_REG_GPIO_14_PU_POS (4U)
+#define GLB_REG_GPIO_14_PU_LEN (1U)
+#define GLB_REG_GPIO_14_PU_MSK (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
+#define GLB_REG_GPIO_14_PU_UMSK (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
+#define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD
+#define GLB_REG_GPIO_14_PD_POS (5U)
+#define GLB_REG_GPIO_14_PD_LEN (1U)
+#define GLB_REG_GPIO_14_PD_MSK (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
+#define GLB_REG_GPIO_14_PD_UMSK (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
+#define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE
+#define GLB_REG_GPIO_14_OE_POS (6U)
+#define GLB_REG_GPIO_14_OE_LEN (1U)
+#define GLB_REG_GPIO_14_OE_MSK (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
+#define GLB_REG_GPIO_14_OE_UMSK (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
+#define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL
+#define GLB_REG_GPIO_14_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_14_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_14_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
+#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS))
+#define GLB_REG_GPIO_14_INT_MODE_SET GLB_REG_GPIO_14_INT_MODE_SET
+#define GLB_REG_GPIO_14_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_14_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_14_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_14_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_14_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_14_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_14_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_14_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_14_INT_CLR GLB_REG_GPIO_14_INT_CLR
+#define GLB_REG_GPIO_14_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_14_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_14_INT_CLR_MSK (((1U << GLB_REG_GPIO_14_INT_CLR_LEN) - 1) << GLB_REG_GPIO_14_INT_CLR_POS)
+#define GLB_REG_GPIO_14_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_14_INT_CLR_LEN) - 1) << GLB_REG_GPIO_14_INT_CLR_POS))
+#define GLB_GPIO_14_INT_STAT GLB_GPIO_14_INT_STAT
+#define GLB_GPIO_14_INT_STAT_POS (21U)
+#define GLB_GPIO_14_INT_STAT_LEN (1U)
+#define GLB_GPIO_14_INT_STAT_MSK (((1U << GLB_GPIO_14_INT_STAT_LEN) - 1) << GLB_GPIO_14_INT_STAT_POS)
+#define GLB_GPIO_14_INT_STAT_UMSK (~(((1U << GLB_GPIO_14_INT_STAT_LEN) - 1) << GLB_GPIO_14_INT_STAT_POS))
+#define GLB_REG_GPIO_14_INT_MASK GLB_REG_GPIO_14_INT_MASK
+#define GLB_REG_GPIO_14_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_14_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_14_INT_MASK_MSK (((1U << GLB_REG_GPIO_14_INT_MASK_LEN) - 1) << GLB_REG_GPIO_14_INT_MASK_POS)
+#define GLB_REG_GPIO_14_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_14_INT_MASK_LEN) - 1) << GLB_REG_GPIO_14_INT_MASK_POS))
+#define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O
+#define GLB_REG_GPIO_14_O_POS (24U)
+#define GLB_REG_GPIO_14_O_LEN (1U)
+#define GLB_REG_GPIO_14_O_MSK (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
+#define GLB_REG_GPIO_14_O_UMSK (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
+#define GLB_REG_GPIO_14_SET GLB_REG_GPIO_14_SET
+#define GLB_REG_GPIO_14_SET_POS (25U)
+#define GLB_REG_GPIO_14_SET_LEN (1U)
+#define GLB_REG_GPIO_14_SET_MSK (((1U << GLB_REG_GPIO_14_SET_LEN) - 1) << GLB_REG_GPIO_14_SET_POS)
+#define GLB_REG_GPIO_14_SET_UMSK (~(((1U << GLB_REG_GPIO_14_SET_LEN) - 1) << GLB_REG_GPIO_14_SET_POS))
+#define GLB_REG_GPIO_14_CLR GLB_REG_GPIO_14_CLR
+#define GLB_REG_GPIO_14_CLR_POS (26U)
+#define GLB_REG_GPIO_14_CLR_LEN (1U)
+#define GLB_REG_GPIO_14_CLR_MSK (((1U << GLB_REG_GPIO_14_CLR_LEN) - 1) << GLB_REG_GPIO_14_CLR_POS)
+#define GLB_REG_GPIO_14_CLR_UMSK (~(((1U << GLB_REG_GPIO_14_CLR_LEN) - 1) << GLB_REG_GPIO_14_CLR_POS))
+#define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I
+#define GLB_REG_GPIO_14_I_POS (28U)
+#define GLB_REG_GPIO_14_I_LEN (1U)
+#define GLB_REG_GPIO_14_I_MSK (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
+#define GLB_REG_GPIO_14_I_UMSK (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
+#define GLB_REG_GPIO_14_MODE GLB_REG_GPIO_14_MODE
+#define GLB_REG_GPIO_14_MODE_POS (30U)
+#define GLB_REG_GPIO_14_MODE_LEN (2U)
+#define GLB_REG_GPIO_14_MODE_MSK (((1U << GLB_REG_GPIO_14_MODE_LEN) - 1) << GLB_REG_GPIO_14_MODE_POS)
+#define GLB_REG_GPIO_14_MODE_UMSK (~(((1U << GLB_REG_GPIO_14_MODE_LEN) - 1) << GLB_REG_GPIO_14_MODE_POS))
+
+/* 0x900 : gpio_cfg15 */
+#define GLB_GPIO_CFG15_OFFSET (0x900)
+#define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE
+#define GLB_REG_GPIO_15_IE_POS (0U)
+#define GLB_REG_GPIO_15_IE_LEN (1U)
+#define GLB_REG_GPIO_15_IE_MSK (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
+#define GLB_REG_GPIO_15_IE_UMSK (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
+#define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT
+#define GLB_REG_GPIO_15_SMT_POS (1U)
+#define GLB_REG_GPIO_15_SMT_LEN (1U)
+#define GLB_REG_GPIO_15_SMT_MSK (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
+#define GLB_REG_GPIO_15_SMT_UMSK (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
+#define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV
+#define GLB_REG_GPIO_15_DRV_POS (2U)
+#define GLB_REG_GPIO_15_DRV_LEN (2U)
+#define GLB_REG_GPIO_15_DRV_MSK (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
+#define GLB_REG_GPIO_15_DRV_UMSK (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
+#define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU
+#define GLB_REG_GPIO_15_PU_POS (4U)
+#define GLB_REG_GPIO_15_PU_LEN (1U)
+#define GLB_REG_GPIO_15_PU_MSK (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
+#define GLB_REG_GPIO_15_PU_UMSK (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
+#define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD
+#define GLB_REG_GPIO_15_PD_POS (5U)
+#define GLB_REG_GPIO_15_PD_LEN (1U)
+#define GLB_REG_GPIO_15_PD_MSK (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
+#define GLB_REG_GPIO_15_PD_UMSK (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
+#define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE
+#define GLB_REG_GPIO_15_OE_POS (6U)
+#define GLB_REG_GPIO_15_OE_LEN (1U)
+#define GLB_REG_GPIO_15_OE_MSK (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
+#define GLB_REG_GPIO_15_OE_UMSK (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
+#define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL
+#define GLB_REG_GPIO_15_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_15_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_15_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
+#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS))
+#define GLB_REG_GPIO_15_INT_MODE_SET GLB_REG_GPIO_15_INT_MODE_SET
+#define GLB_REG_GPIO_15_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_15_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_15_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_15_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_15_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_15_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_15_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_15_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_15_INT_CLR GLB_REG_GPIO_15_INT_CLR
+#define GLB_REG_GPIO_15_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_15_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_15_INT_CLR_MSK (((1U << GLB_REG_GPIO_15_INT_CLR_LEN) - 1) << GLB_REG_GPIO_15_INT_CLR_POS)
+#define GLB_REG_GPIO_15_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_15_INT_CLR_LEN) - 1) << GLB_REG_GPIO_15_INT_CLR_POS))
+#define GLB_GPIO_15_INT_STAT GLB_GPIO_15_INT_STAT
+#define GLB_GPIO_15_INT_STAT_POS (21U)
+#define GLB_GPIO_15_INT_STAT_LEN (1U)
+#define GLB_GPIO_15_INT_STAT_MSK (((1U << GLB_GPIO_15_INT_STAT_LEN) - 1) << GLB_GPIO_15_INT_STAT_POS)
+#define GLB_GPIO_15_INT_STAT_UMSK (~(((1U << GLB_GPIO_15_INT_STAT_LEN) - 1) << GLB_GPIO_15_INT_STAT_POS))
+#define GLB_REG_GPIO_15_INT_MASK GLB_REG_GPIO_15_INT_MASK
+#define GLB_REG_GPIO_15_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_15_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_15_INT_MASK_MSK (((1U << GLB_REG_GPIO_15_INT_MASK_LEN) - 1) << GLB_REG_GPIO_15_INT_MASK_POS)
+#define GLB_REG_GPIO_15_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_15_INT_MASK_LEN) - 1) << GLB_REG_GPIO_15_INT_MASK_POS))
+#define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O
+#define GLB_REG_GPIO_15_O_POS (24U)
+#define GLB_REG_GPIO_15_O_LEN (1U)
+#define GLB_REG_GPIO_15_O_MSK (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
+#define GLB_REG_GPIO_15_O_UMSK (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
+#define GLB_REG_GPIO_15_SET GLB_REG_GPIO_15_SET
+#define GLB_REG_GPIO_15_SET_POS (25U)
+#define GLB_REG_GPIO_15_SET_LEN (1U)
+#define GLB_REG_GPIO_15_SET_MSK (((1U << GLB_REG_GPIO_15_SET_LEN) - 1) << GLB_REG_GPIO_15_SET_POS)
+#define GLB_REG_GPIO_15_SET_UMSK (~(((1U << GLB_REG_GPIO_15_SET_LEN) - 1) << GLB_REG_GPIO_15_SET_POS))
+#define GLB_REG_GPIO_15_CLR GLB_REG_GPIO_15_CLR
+#define GLB_REG_GPIO_15_CLR_POS (26U)
+#define GLB_REG_GPIO_15_CLR_LEN (1U)
+#define GLB_REG_GPIO_15_CLR_MSK (((1U << GLB_REG_GPIO_15_CLR_LEN) - 1) << GLB_REG_GPIO_15_CLR_POS)
+#define GLB_REG_GPIO_15_CLR_UMSK (~(((1U << GLB_REG_GPIO_15_CLR_LEN) - 1) << GLB_REG_GPIO_15_CLR_POS))
+#define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I
+#define GLB_REG_GPIO_15_I_POS (28U)
+#define GLB_REG_GPIO_15_I_LEN (1U)
+#define GLB_REG_GPIO_15_I_MSK (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
+#define GLB_REG_GPIO_15_I_UMSK (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
+#define GLB_REG_GPIO_15_MODE GLB_REG_GPIO_15_MODE
+#define GLB_REG_GPIO_15_MODE_POS (30U)
+#define GLB_REG_GPIO_15_MODE_LEN (2U)
+#define GLB_REG_GPIO_15_MODE_MSK (((1U << GLB_REG_GPIO_15_MODE_LEN) - 1) << GLB_REG_GPIO_15_MODE_POS)
+#define GLB_REG_GPIO_15_MODE_UMSK (~(((1U << GLB_REG_GPIO_15_MODE_LEN) - 1) << GLB_REG_GPIO_15_MODE_POS))
+
+/* 0x904 : gpio_cfg16 */
+#define GLB_GPIO_CFG16_OFFSET (0x904)
+#define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE
+#define GLB_REG_GPIO_16_IE_POS (0U)
+#define GLB_REG_GPIO_16_IE_LEN (1U)
+#define GLB_REG_GPIO_16_IE_MSK (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
+#define GLB_REG_GPIO_16_IE_UMSK (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
+#define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT
+#define GLB_REG_GPIO_16_SMT_POS (1U)
+#define GLB_REG_GPIO_16_SMT_LEN (1U)
+#define GLB_REG_GPIO_16_SMT_MSK (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
+#define GLB_REG_GPIO_16_SMT_UMSK (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
+#define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV
+#define GLB_REG_GPIO_16_DRV_POS (2U)
+#define GLB_REG_GPIO_16_DRV_LEN (2U)
+#define GLB_REG_GPIO_16_DRV_MSK (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
+#define GLB_REG_GPIO_16_DRV_UMSK (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
+#define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU
+#define GLB_REG_GPIO_16_PU_POS (4U)
+#define GLB_REG_GPIO_16_PU_LEN (1U)
+#define GLB_REG_GPIO_16_PU_MSK (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
+#define GLB_REG_GPIO_16_PU_UMSK (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
+#define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD
+#define GLB_REG_GPIO_16_PD_POS (5U)
+#define GLB_REG_GPIO_16_PD_LEN (1U)
+#define GLB_REG_GPIO_16_PD_MSK (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
+#define GLB_REG_GPIO_16_PD_UMSK (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
+#define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE
+#define GLB_REG_GPIO_16_OE_POS (6U)
+#define GLB_REG_GPIO_16_OE_LEN (1U)
+#define GLB_REG_GPIO_16_OE_MSK (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
+#define GLB_REG_GPIO_16_OE_UMSK (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
+#define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL
+#define GLB_REG_GPIO_16_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_16_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_16_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
+#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS))
+#define GLB_REG_GPIO_16_INT_MODE_SET GLB_REG_GPIO_16_INT_MODE_SET
+#define GLB_REG_GPIO_16_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_16_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_16_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_16_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_16_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_16_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_16_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_16_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_16_INT_CLR GLB_REG_GPIO_16_INT_CLR
+#define GLB_REG_GPIO_16_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_16_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_16_INT_CLR_MSK (((1U << GLB_REG_GPIO_16_INT_CLR_LEN) - 1) << GLB_REG_GPIO_16_INT_CLR_POS)
+#define GLB_REG_GPIO_16_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_16_INT_CLR_LEN) - 1) << GLB_REG_GPIO_16_INT_CLR_POS))
+#define GLB_GPIO_16_INT_STAT GLB_GPIO_16_INT_STAT
+#define GLB_GPIO_16_INT_STAT_POS (21U)
+#define GLB_GPIO_16_INT_STAT_LEN (1U)
+#define GLB_GPIO_16_INT_STAT_MSK (((1U << GLB_GPIO_16_INT_STAT_LEN) - 1) << GLB_GPIO_16_INT_STAT_POS)
+#define GLB_GPIO_16_INT_STAT_UMSK (~(((1U << GLB_GPIO_16_INT_STAT_LEN) - 1) << GLB_GPIO_16_INT_STAT_POS))
+#define GLB_REG_GPIO_16_INT_MASK GLB_REG_GPIO_16_INT_MASK
+#define GLB_REG_GPIO_16_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_16_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_16_INT_MASK_MSK (((1U << GLB_REG_GPIO_16_INT_MASK_LEN) - 1) << GLB_REG_GPIO_16_INT_MASK_POS)
+#define GLB_REG_GPIO_16_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_16_INT_MASK_LEN) - 1) << GLB_REG_GPIO_16_INT_MASK_POS))
+#define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O
+#define GLB_REG_GPIO_16_O_POS (24U)
+#define GLB_REG_GPIO_16_O_LEN (1U)
+#define GLB_REG_GPIO_16_O_MSK (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
+#define GLB_REG_GPIO_16_O_UMSK (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
+#define GLB_REG_GPIO_16_SET GLB_REG_GPIO_16_SET
+#define GLB_REG_GPIO_16_SET_POS (25U)
+#define GLB_REG_GPIO_16_SET_LEN (1U)
+#define GLB_REG_GPIO_16_SET_MSK (((1U << GLB_REG_GPIO_16_SET_LEN) - 1) << GLB_REG_GPIO_16_SET_POS)
+#define GLB_REG_GPIO_16_SET_UMSK (~(((1U << GLB_REG_GPIO_16_SET_LEN) - 1) << GLB_REG_GPIO_16_SET_POS))
+#define GLB_REG_GPIO_16_CLR GLB_REG_GPIO_16_CLR
+#define GLB_REG_GPIO_16_CLR_POS (26U)
+#define GLB_REG_GPIO_16_CLR_LEN (1U)
+#define GLB_REG_GPIO_16_CLR_MSK (((1U << GLB_REG_GPIO_16_CLR_LEN) - 1) << GLB_REG_GPIO_16_CLR_POS)
+#define GLB_REG_GPIO_16_CLR_UMSK (~(((1U << GLB_REG_GPIO_16_CLR_LEN) - 1) << GLB_REG_GPIO_16_CLR_POS))
+#define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I
+#define GLB_REG_GPIO_16_I_POS (28U)
+#define GLB_REG_GPIO_16_I_LEN (1U)
+#define GLB_REG_GPIO_16_I_MSK (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
+#define GLB_REG_GPIO_16_I_UMSK (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
+#define GLB_REG_GPIO_16_MODE GLB_REG_GPIO_16_MODE
+#define GLB_REG_GPIO_16_MODE_POS (30U)
+#define GLB_REG_GPIO_16_MODE_LEN (2U)
+#define GLB_REG_GPIO_16_MODE_MSK (((1U << GLB_REG_GPIO_16_MODE_LEN) - 1) << GLB_REG_GPIO_16_MODE_POS)
+#define GLB_REG_GPIO_16_MODE_UMSK (~(((1U << GLB_REG_GPIO_16_MODE_LEN) - 1) << GLB_REG_GPIO_16_MODE_POS))
+
+/* 0x908 : gpio_cfg17 */
+#define GLB_GPIO_CFG17_OFFSET (0x908)
+#define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE
+#define GLB_REG_GPIO_17_IE_POS (0U)
+#define GLB_REG_GPIO_17_IE_LEN (1U)
+#define GLB_REG_GPIO_17_IE_MSK (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
+#define GLB_REG_GPIO_17_IE_UMSK (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
+#define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT
+#define GLB_REG_GPIO_17_SMT_POS (1U)
+#define GLB_REG_GPIO_17_SMT_LEN (1U)
+#define GLB_REG_GPIO_17_SMT_MSK (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
+#define GLB_REG_GPIO_17_SMT_UMSK (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
+#define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV
+#define GLB_REG_GPIO_17_DRV_POS (2U)
+#define GLB_REG_GPIO_17_DRV_LEN (2U)
+#define GLB_REG_GPIO_17_DRV_MSK (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
+#define GLB_REG_GPIO_17_DRV_UMSK (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
+#define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU
+#define GLB_REG_GPIO_17_PU_POS (4U)
+#define GLB_REG_GPIO_17_PU_LEN (1U)
+#define GLB_REG_GPIO_17_PU_MSK (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
+#define GLB_REG_GPIO_17_PU_UMSK (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
+#define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD
+#define GLB_REG_GPIO_17_PD_POS (5U)
+#define GLB_REG_GPIO_17_PD_LEN (1U)
+#define GLB_REG_GPIO_17_PD_MSK (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
+#define GLB_REG_GPIO_17_PD_UMSK (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
+#define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE
+#define GLB_REG_GPIO_17_OE_POS (6U)
+#define GLB_REG_GPIO_17_OE_LEN (1U)
+#define GLB_REG_GPIO_17_OE_MSK (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
+#define GLB_REG_GPIO_17_OE_UMSK (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
+#define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL
+#define GLB_REG_GPIO_17_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_17_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_17_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
+#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS))
+#define GLB_REG_GPIO_17_INT_MODE_SET GLB_REG_GPIO_17_INT_MODE_SET
+#define GLB_REG_GPIO_17_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_17_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_17_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_17_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_17_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_17_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_17_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_17_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_17_INT_CLR GLB_REG_GPIO_17_INT_CLR
+#define GLB_REG_GPIO_17_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_17_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_17_INT_CLR_MSK (((1U << GLB_REG_GPIO_17_INT_CLR_LEN) - 1) << GLB_REG_GPIO_17_INT_CLR_POS)
+#define GLB_REG_GPIO_17_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_17_INT_CLR_LEN) - 1) << GLB_REG_GPIO_17_INT_CLR_POS))
+#define GLB_GPIO_17_INT_STAT GLB_GPIO_17_INT_STAT
+#define GLB_GPIO_17_INT_STAT_POS (21U)
+#define GLB_GPIO_17_INT_STAT_LEN (1U)
+#define GLB_GPIO_17_INT_STAT_MSK (((1U << GLB_GPIO_17_INT_STAT_LEN) - 1) << GLB_GPIO_17_INT_STAT_POS)
+#define GLB_GPIO_17_INT_STAT_UMSK (~(((1U << GLB_GPIO_17_INT_STAT_LEN) - 1) << GLB_GPIO_17_INT_STAT_POS))
+#define GLB_REG_GPIO_17_INT_MASK GLB_REG_GPIO_17_INT_MASK
+#define GLB_REG_GPIO_17_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_17_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_17_INT_MASK_MSK (((1U << GLB_REG_GPIO_17_INT_MASK_LEN) - 1) << GLB_REG_GPIO_17_INT_MASK_POS)
+#define GLB_REG_GPIO_17_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_17_INT_MASK_LEN) - 1) << GLB_REG_GPIO_17_INT_MASK_POS))
+#define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O
+#define GLB_REG_GPIO_17_O_POS (24U)
+#define GLB_REG_GPIO_17_O_LEN (1U)
+#define GLB_REG_GPIO_17_O_MSK (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
+#define GLB_REG_GPIO_17_O_UMSK (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
+#define GLB_REG_GPIO_17_SET GLB_REG_GPIO_17_SET
+#define GLB_REG_GPIO_17_SET_POS (25U)
+#define GLB_REG_GPIO_17_SET_LEN (1U)
+#define GLB_REG_GPIO_17_SET_MSK (((1U << GLB_REG_GPIO_17_SET_LEN) - 1) << GLB_REG_GPIO_17_SET_POS)
+#define GLB_REG_GPIO_17_SET_UMSK (~(((1U << GLB_REG_GPIO_17_SET_LEN) - 1) << GLB_REG_GPIO_17_SET_POS))
+#define GLB_REG_GPIO_17_CLR GLB_REG_GPIO_17_CLR
+#define GLB_REG_GPIO_17_CLR_POS (26U)
+#define GLB_REG_GPIO_17_CLR_LEN (1U)
+#define GLB_REG_GPIO_17_CLR_MSK (((1U << GLB_REG_GPIO_17_CLR_LEN) - 1) << GLB_REG_GPIO_17_CLR_POS)
+#define GLB_REG_GPIO_17_CLR_UMSK (~(((1U << GLB_REG_GPIO_17_CLR_LEN) - 1) << GLB_REG_GPIO_17_CLR_POS))
+#define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I
+#define GLB_REG_GPIO_17_I_POS (28U)
+#define GLB_REG_GPIO_17_I_LEN (1U)
+#define GLB_REG_GPIO_17_I_MSK (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
+#define GLB_REG_GPIO_17_I_UMSK (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
+#define GLB_REG_GPIO_17_MODE GLB_REG_GPIO_17_MODE
+#define GLB_REG_GPIO_17_MODE_POS (30U)
+#define GLB_REG_GPIO_17_MODE_LEN (2U)
+#define GLB_REG_GPIO_17_MODE_MSK (((1U << GLB_REG_GPIO_17_MODE_LEN) - 1) << GLB_REG_GPIO_17_MODE_POS)
+#define GLB_REG_GPIO_17_MODE_UMSK (~(((1U << GLB_REG_GPIO_17_MODE_LEN) - 1) << GLB_REG_GPIO_17_MODE_POS))
+
+/* 0x90C : gpio_cfg18 */
+#define GLB_GPIO_CFG18_OFFSET (0x90C)
+#define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE
+#define GLB_REG_GPIO_18_IE_POS (0U)
+#define GLB_REG_GPIO_18_IE_LEN (1U)
+#define GLB_REG_GPIO_18_IE_MSK (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
+#define GLB_REG_GPIO_18_IE_UMSK (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
+#define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT
+#define GLB_REG_GPIO_18_SMT_POS (1U)
+#define GLB_REG_GPIO_18_SMT_LEN (1U)
+#define GLB_REG_GPIO_18_SMT_MSK (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
+#define GLB_REG_GPIO_18_SMT_UMSK (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
+#define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV
+#define GLB_REG_GPIO_18_DRV_POS (2U)
+#define GLB_REG_GPIO_18_DRV_LEN (2U)
+#define GLB_REG_GPIO_18_DRV_MSK (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
+#define GLB_REG_GPIO_18_DRV_UMSK (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
+#define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU
+#define GLB_REG_GPIO_18_PU_POS (4U)
+#define GLB_REG_GPIO_18_PU_LEN (1U)
+#define GLB_REG_GPIO_18_PU_MSK (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
+#define GLB_REG_GPIO_18_PU_UMSK (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
+#define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD
+#define GLB_REG_GPIO_18_PD_POS (5U)
+#define GLB_REG_GPIO_18_PD_LEN (1U)
+#define GLB_REG_GPIO_18_PD_MSK (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
+#define GLB_REG_GPIO_18_PD_UMSK (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
+#define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE
+#define GLB_REG_GPIO_18_OE_POS (6U)
+#define GLB_REG_GPIO_18_OE_LEN (1U)
+#define GLB_REG_GPIO_18_OE_MSK (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
+#define GLB_REG_GPIO_18_OE_UMSK (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
+#define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL
+#define GLB_REG_GPIO_18_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_18_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_18_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
+#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS))
+#define GLB_REG_GPIO_18_INT_MODE_SET GLB_REG_GPIO_18_INT_MODE_SET
+#define GLB_REG_GPIO_18_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_18_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_18_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_18_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_18_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_18_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_18_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_18_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_18_INT_CLR GLB_REG_GPIO_18_INT_CLR
+#define GLB_REG_GPIO_18_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_18_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_18_INT_CLR_MSK (((1U << GLB_REG_GPIO_18_INT_CLR_LEN) - 1) << GLB_REG_GPIO_18_INT_CLR_POS)
+#define GLB_REG_GPIO_18_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_18_INT_CLR_LEN) - 1) << GLB_REG_GPIO_18_INT_CLR_POS))
+#define GLB_GPIO_18_INT_STAT GLB_GPIO_18_INT_STAT
+#define GLB_GPIO_18_INT_STAT_POS (21U)
+#define GLB_GPIO_18_INT_STAT_LEN (1U)
+#define GLB_GPIO_18_INT_STAT_MSK (((1U << GLB_GPIO_18_INT_STAT_LEN) - 1) << GLB_GPIO_18_INT_STAT_POS)
+#define GLB_GPIO_18_INT_STAT_UMSK (~(((1U << GLB_GPIO_18_INT_STAT_LEN) - 1) << GLB_GPIO_18_INT_STAT_POS))
+#define GLB_REG_GPIO_18_INT_MASK GLB_REG_GPIO_18_INT_MASK
+#define GLB_REG_GPIO_18_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_18_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_18_INT_MASK_MSK (((1U << GLB_REG_GPIO_18_INT_MASK_LEN) - 1) << GLB_REG_GPIO_18_INT_MASK_POS)
+#define GLB_REG_GPIO_18_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_18_INT_MASK_LEN) - 1) << GLB_REG_GPIO_18_INT_MASK_POS))
+#define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O
+#define GLB_REG_GPIO_18_O_POS (24U)
+#define GLB_REG_GPIO_18_O_LEN (1U)
+#define GLB_REG_GPIO_18_O_MSK (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
+#define GLB_REG_GPIO_18_O_UMSK (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
+#define GLB_REG_GPIO_18_SET GLB_REG_GPIO_18_SET
+#define GLB_REG_GPIO_18_SET_POS (25U)
+#define GLB_REG_GPIO_18_SET_LEN (1U)
+#define GLB_REG_GPIO_18_SET_MSK (((1U << GLB_REG_GPIO_18_SET_LEN) - 1) << GLB_REG_GPIO_18_SET_POS)
+#define GLB_REG_GPIO_18_SET_UMSK (~(((1U << GLB_REG_GPIO_18_SET_LEN) - 1) << GLB_REG_GPIO_18_SET_POS))
+#define GLB_REG_GPIO_18_CLR GLB_REG_GPIO_18_CLR
+#define GLB_REG_GPIO_18_CLR_POS (26U)
+#define GLB_REG_GPIO_18_CLR_LEN (1U)
+#define GLB_REG_GPIO_18_CLR_MSK (((1U << GLB_REG_GPIO_18_CLR_LEN) - 1) << GLB_REG_GPIO_18_CLR_POS)
+#define GLB_REG_GPIO_18_CLR_UMSK (~(((1U << GLB_REG_GPIO_18_CLR_LEN) - 1) << GLB_REG_GPIO_18_CLR_POS))
+#define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I
+#define GLB_REG_GPIO_18_I_POS (28U)
+#define GLB_REG_GPIO_18_I_LEN (1U)
+#define GLB_REG_GPIO_18_I_MSK (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
+#define GLB_REG_GPIO_18_I_UMSK (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
+#define GLB_REG_GPIO_18_MODE GLB_REG_GPIO_18_MODE
+#define GLB_REG_GPIO_18_MODE_POS (30U)
+#define GLB_REG_GPIO_18_MODE_LEN (2U)
+#define GLB_REG_GPIO_18_MODE_MSK (((1U << GLB_REG_GPIO_18_MODE_LEN) - 1) << GLB_REG_GPIO_18_MODE_POS)
+#define GLB_REG_GPIO_18_MODE_UMSK (~(((1U << GLB_REG_GPIO_18_MODE_LEN) - 1) << GLB_REG_GPIO_18_MODE_POS))
+
+/* 0x910 : gpio_cfg19 */
+#define GLB_GPIO_CFG19_OFFSET (0x910)
+#define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE
+#define GLB_REG_GPIO_19_IE_POS (0U)
+#define GLB_REG_GPIO_19_IE_LEN (1U)
+#define GLB_REG_GPIO_19_IE_MSK (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
+#define GLB_REG_GPIO_19_IE_UMSK (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
+#define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT
+#define GLB_REG_GPIO_19_SMT_POS (1U)
+#define GLB_REG_GPIO_19_SMT_LEN (1U)
+#define GLB_REG_GPIO_19_SMT_MSK (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
+#define GLB_REG_GPIO_19_SMT_UMSK (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
+#define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV
+#define GLB_REG_GPIO_19_DRV_POS (2U)
+#define GLB_REG_GPIO_19_DRV_LEN (2U)
+#define GLB_REG_GPIO_19_DRV_MSK (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
+#define GLB_REG_GPIO_19_DRV_UMSK (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
+#define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU
+#define GLB_REG_GPIO_19_PU_POS (4U)
+#define GLB_REG_GPIO_19_PU_LEN (1U)
+#define GLB_REG_GPIO_19_PU_MSK (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
+#define GLB_REG_GPIO_19_PU_UMSK (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
+#define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD
+#define GLB_REG_GPIO_19_PD_POS (5U)
+#define GLB_REG_GPIO_19_PD_LEN (1U)
+#define GLB_REG_GPIO_19_PD_MSK (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
+#define GLB_REG_GPIO_19_PD_UMSK (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
+#define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE
+#define GLB_REG_GPIO_19_OE_POS (6U)
+#define GLB_REG_GPIO_19_OE_LEN (1U)
+#define GLB_REG_GPIO_19_OE_MSK (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
+#define GLB_REG_GPIO_19_OE_UMSK (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
+#define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL
+#define GLB_REG_GPIO_19_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_19_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_19_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
+#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS))
+#define GLB_REG_GPIO_19_INT_MODE_SET GLB_REG_GPIO_19_INT_MODE_SET
+#define GLB_REG_GPIO_19_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_19_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_19_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_19_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_19_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_19_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_19_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_19_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_19_INT_CLR GLB_REG_GPIO_19_INT_CLR
+#define GLB_REG_GPIO_19_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_19_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_19_INT_CLR_MSK (((1U << GLB_REG_GPIO_19_INT_CLR_LEN) - 1) << GLB_REG_GPIO_19_INT_CLR_POS)
+#define GLB_REG_GPIO_19_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_19_INT_CLR_LEN) - 1) << GLB_REG_GPIO_19_INT_CLR_POS))
+#define GLB_GPIO_19_INT_STAT GLB_GPIO_19_INT_STAT
+#define GLB_GPIO_19_INT_STAT_POS (21U)
+#define GLB_GPIO_19_INT_STAT_LEN (1U)
+#define GLB_GPIO_19_INT_STAT_MSK (((1U << GLB_GPIO_19_INT_STAT_LEN) - 1) << GLB_GPIO_19_INT_STAT_POS)
+#define GLB_GPIO_19_INT_STAT_UMSK (~(((1U << GLB_GPIO_19_INT_STAT_LEN) - 1) << GLB_GPIO_19_INT_STAT_POS))
+#define GLB_REG_GPIO_19_INT_MASK GLB_REG_GPIO_19_INT_MASK
+#define GLB_REG_GPIO_19_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_19_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_19_INT_MASK_MSK (((1U << GLB_REG_GPIO_19_INT_MASK_LEN) - 1) << GLB_REG_GPIO_19_INT_MASK_POS)
+#define GLB_REG_GPIO_19_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_19_INT_MASK_LEN) - 1) << GLB_REG_GPIO_19_INT_MASK_POS))
+#define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O
+#define GLB_REG_GPIO_19_O_POS (24U)
+#define GLB_REG_GPIO_19_O_LEN (1U)
+#define GLB_REG_GPIO_19_O_MSK (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
+#define GLB_REG_GPIO_19_O_UMSK (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
+#define GLB_REG_GPIO_19_SET GLB_REG_GPIO_19_SET
+#define GLB_REG_GPIO_19_SET_POS (25U)
+#define GLB_REG_GPIO_19_SET_LEN (1U)
+#define GLB_REG_GPIO_19_SET_MSK (((1U << GLB_REG_GPIO_19_SET_LEN) - 1) << GLB_REG_GPIO_19_SET_POS)
+#define GLB_REG_GPIO_19_SET_UMSK (~(((1U << GLB_REG_GPIO_19_SET_LEN) - 1) << GLB_REG_GPIO_19_SET_POS))
+#define GLB_REG_GPIO_19_CLR GLB_REG_GPIO_19_CLR
+#define GLB_REG_GPIO_19_CLR_POS (26U)
+#define GLB_REG_GPIO_19_CLR_LEN (1U)
+#define GLB_REG_GPIO_19_CLR_MSK (((1U << GLB_REG_GPIO_19_CLR_LEN) - 1) << GLB_REG_GPIO_19_CLR_POS)
+#define GLB_REG_GPIO_19_CLR_UMSK (~(((1U << GLB_REG_GPIO_19_CLR_LEN) - 1) << GLB_REG_GPIO_19_CLR_POS))
+#define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I
+#define GLB_REG_GPIO_19_I_POS (28U)
+#define GLB_REG_GPIO_19_I_LEN (1U)
+#define GLB_REG_GPIO_19_I_MSK (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
+#define GLB_REG_GPIO_19_I_UMSK (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
+#define GLB_REG_GPIO_19_MODE GLB_REG_GPIO_19_MODE
+#define GLB_REG_GPIO_19_MODE_POS (30U)
+#define GLB_REG_GPIO_19_MODE_LEN (2U)
+#define GLB_REG_GPIO_19_MODE_MSK (((1U << GLB_REG_GPIO_19_MODE_LEN) - 1) << GLB_REG_GPIO_19_MODE_POS)
+#define GLB_REG_GPIO_19_MODE_UMSK (~(((1U << GLB_REG_GPIO_19_MODE_LEN) - 1) << GLB_REG_GPIO_19_MODE_POS))
+
+/* 0x914 : gpio_cfg20 */
+#define GLB_GPIO_CFG20_OFFSET (0x914)
+#define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE
+#define GLB_REG_GPIO_20_IE_POS (0U)
+#define GLB_REG_GPIO_20_IE_LEN (1U)
+#define GLB_REG_GPIO_20_IE_MSK (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
+#define GLB_REG_GPIO_20_IE_UMSK (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
+#define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT
+#define GLB_REG_GPIO_20_SMT_POS (1U)
+#define GLB_REG_GPIO_20_SMT_LEN (1U)
+#define GLB_REG_GPIO_20_SMT_MSK (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
+#define GLB_REG_GPIO_20_SMT_UMSK (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
+#define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV
+#define GLB_REG_GPIO_20_DRV_POS (2U)
+#define GLB_REG_GPIO_20_DRV_LEN (2U)
+#define GLB_REG_GPIO_20_DRV_MSK (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
+#define GLB_REG_GPIO_20_DRV_UMSK (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
+#define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU
+#define GLB_REG_GPIO_20_PU_POS (4U)
+#define GLB_REG_GPIO_20_PU_LEN (1U)
+#define GLB_REG_GPIO_20_PU_MSK (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
+#define GLB_REG_GPIO_20_PU_UMSK (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
+#define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD
+#define GLB_REG_GPIO_20_PD_POS (5U)
+#define GLB_REG_GPIO_20_PD_LEN (1U)
+#define GLB_REG_GPIO_20_PD_MSK (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
+#define GLB_REG_GPIO_20_PD_UMSK (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
+#define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE
+#define GLB_REG_GPIO_20_OE_POS (6U)
+#define GLB_REG_GPIO_20_OE_LEN (1U)
+#define GLB_REG_GPIO_20_OE_MSK (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
+#define GLB_REG_GPIO_20_OE_UMSK (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
+#define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL
+#define GLB_REG_GPIO_20_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_20_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_20_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
+#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS))
+#define GLB_REG_GPIO_20_INT_MODE_SET GLB_REG_GPIO_20_INT_MODE_SET
+#define GLB_REG_GPIO_20_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_20_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_20_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_20_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_20_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_20_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_20_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_20_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_20_INT_CLR GLB_REG_GPIO_20_INT_CLR
+#define GLB_REG_GPIO_20_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_20_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_20_INT_CLR_MSK (((1U << GLB_REG_GPIO_20_INT_CLR_LEN) - 1) << GLB_REG_GPIO_20_INT_CLR_POS)
+#define GLB_REG_GPIO_20_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_20_INT_CLR_LEN) - 1) << GLB_REG_GPIO_20_INT_CLR_POS))
+#define GLB_GPIO_20_INT_STAT GLB_GPIO_20_INT_STAT
+#define GLB_GPIO_20_INT_STAT_POS (21U)
+#define GLB_GPIO_20_INT_STAT_LEN (1U)
+#define GLB_GPIO_20_INT_STAT_MSK (((1U << GLB_GPIO_20_INT_STAT_LEN) - 1) << GLB_GPIO_20_INT_STAT_POS)
+#define GLB_GPIO_20_INT_STAT_UMSK (~(((1U << GLB_GPIO_20_INT_STAT_LEN) - 1) << GLB_GPIO_20_INT_STAT_POS))
+#define GLB_REG_GPIO_20_INT_MASK GLB_REG_GPIO_20_INT_MASK
+#define GLB_REG_GPIO_20_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_20_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_20_INT_MASK_MSK (((1U << GLB_REG_GPIO_20_INT_MASK_LEN) - 1) << GLB_REG_GPIO_20_INT_MASK_POS)
+#define GLB_REG_GPIO_20_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_20_INT_MASK_LEN) - 1) << GLB_REG_GPIO_20_INT_MASK_POS))
+#define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O
+#define GLB_REG_GPIO_20_O_POS (24U)
+#define GLB_REG_GPIO_20_O_LEN (1U)
+#define GLB_REG_GPIO_20_O_MSK (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
+#define GLB_REG_GPIO_20_O_UMSK (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
+#define GLB_REG_GPIO_20_SET GLB_REG_GPIO_20_SET
+#define GLB_REG_GPIO_20_SET_POS (25U)
+#define GLB_REG_GPIO_20_SET_LEN (1U)
+#define GLB_REG_GPIO_20_SET_MSK (((1U << GLB_REG_GPIO_20_SET_LEN) - 1) << GLB_REG_GPIO_20_SET_POS)
+#define GLB_REG_GPIO_20_SET_UMSK (~(((1U << GLB_REG_GPIO_20_SET_LEN) - 1) << GLB_REG_GPIO_20_SET_POS))
+#define GLB_REG_GPIO_20_CLR GLB_REG_GPIO_20_CLR
+#define GLB_REG_GPIO_20_CLR_POS (26U)
+#define GLB_REG_GPIO_20_CLR_LEN (1U)
+#define GLB_REG_GPIO_20_CLR_MSK (((1U << GLB_REG_GPIO_20_CLR_LEN) - 1) << GLB_REG_GPIO_20_CLR_POS)
+#define GLB_REG_GPIO_20_CLR_UMSK (~(((1U << GLB_REG_GPIO_20_CLR_LEN) - 1) << GLB_REG_GPIO_20_CLR_POS))
+#define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I
+#define GLB_REG_GPIO_20_I_POS (28U)
+#define GLB_REG_GPIO_20_I_LEN (1U)
+#define GLB_REG_GPIO_20_I_MSK (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
+#define GLB_REG_GPIO_20_I_UMSK (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
+#define GLB_REG_GPIO_20_MODE GLB_REG_GPIO_20_MODE
+#define GLB_REG_GPIO_20_MODE_POS (30U)
+#define GLB_REG_GPIO_20_MODE_LEN (2U)
+#define GLB_REG_GPIO_20_MODE_MSK (((1U << GLB_REG_GPIO_20_MODE_LEN) - 1) << GLB_REG_GPIO_20_MODE_POS)
+#define GLB_REG_GPIO_20_MODE_UMSK (~(((1U << GLB_REG_GPIO_20_MODE_LEN) - 1) << GLB_REG_GPIO_20_MODE_POS))
+
+/* 0x918 : gpio_cfg21 */
+#define GLB_GPIO_CFG21_OFFSET (0x918)
+#define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE
+#define GLB_REG_GPIO_21_IE_POS (0U)
+#define GLB_REG_GPIO_21_IE_LEN (1U)
+#define GLB_REG_GPIO_21_IE_MSK (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
+#define GLB_REG_GPIO_21_IE_UMSK (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
+#define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT
+#define GLB_REG_GPIO_21_SMT_POS (1U)
+#define GLB_REG_GPIO_21_SMT_LEN (1U)
+#define GLB_REG_GPIO_21_SMT_MSK (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
+#define GLB_REG_GPIO_21_SMT_UMSK (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
+#define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV
+#define GLB_REG_GPIO_21_DRV_POS (2U)
+#define GLB_REG_GPIO_21_DRV_LEN (2U)
+#define GLB_REG_GPIO_21_DRV_MSK (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
+#define GLB_REG_GPIO_21_DRV_UMSK (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
+#define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU
+#define GLB_REG_GPIO_21_PU_POS (4U)
+#define GLB_REG_GPIO_21_PU_LEN (1U)
+#define GLB_REG_GPIO_21_PU_MSK (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
+#define GLB_REG_GPIO_21_PU_UMSK (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
+#define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD
+#define GLB_REG_GPIO_21_PD_POS (5U)
+#define GLB_REG_GPIO_21_PD_LEN (1U)
+#define GLB_REG_GPIO_21_PD_MSK (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
+#define GLB_REG_GPIO_21_PD_UMSK (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
+#define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE
+#define GLB_REG_GPIO_21_OE_POS (6U)
+#define GLB_REG_GPIO_21_OE_LEN (1U)
+#define GLB_REG_GPIO_21_OE_MSK (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
+#define GLB_REG_GPIO_21_OE_UMSK (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
+#define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL
+#define GLB_REG_GPIO_21_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_21_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_21_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
+#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS))
+#define GLB_REG_GPIO_21_INT_MODE_SET GLB_REG_GPIO_21_INT_MODE_SET
+#define GLB_REG_GPIO_21_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_21_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_21_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_21_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_21_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_21_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_21_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_21_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_21_INT_CLR GLB_REG_GPIO_21_INT_CLR
+#define GLB_REG_GPIO_21_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_21_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_21_INT_CLR_MSK (((1U << GLB_REG_GPIO_21_INT_CLR_LEN) - 1) << GLB_REG_GPIO_21_INT_CLR_POS)
+#define GLB_REG_GPIO_21_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_21_INT_CLR_LEN) - 1) << GLB_REG_GPIO_21_INT_CLR_POS))
+#define GLB_GPIO_21_INT_STAT GLB_GPIO_21_INT_STAT
+#define GLB_GPIO_21_INT_STAT_POS (21U)
+#define GLB_GPIO_21_INT_STAT_LEN (1U)
+#define GLB_GPIO_21_INT_STAT_MSK (((1U << GLB_GPIO_21_INT_STAT_LEN) - 1) << GLB_GPIO_21_INT_STAT_POS)
+#define GLB_GPIO_21_INT_STAT_UMSK (~(((1U << GLB_GPIO_21_INT_STAT_LEN) - 1) << GLB_GPIO_21_INT_STAT_POS))
+#define GLB_REG_GPIO_21_INT_MASK GLB_REG_GPIO_21_INT_MASK
+#define GLB_REG_GPIO_21_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_21_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_21_INT_MASK_MSK (((1U << GLB_REG_GPIO_21_INT_MASK_LEN) - 1) << GLB_REG_GPIO_21_INT_MASK_POS)
+#define GLB_REG_GPIO_21_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_21_INT_MASK_LEN) - 1) << GLB_REG_GPIO_21_INT_MASK_POS))
+#define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O
+#define GLB_REG_GPIO_21_O_POS (24U)
+#define GLB_REG_GPIO_21_O_LEN (1U)
+#define GLB_REG_GPIO_21_O_MSK (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
+#define GLB_REG_GPIO_21_O_UMSK (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
+#define GLB_REG_GPIO_21_SET GLB_REG_GPIO_21_SET
+#define GLB_REG_GPIO_21_SET_POS (25U)
+#define GLB_REG_GPIO_21_SET_LEN (1U)
+#define GLB_REG_GPIO_21_SET_MSK (((1U << GLB_REG_GPIO_21_SET_LEN) - 1) << GLB_REG_GPIO_21_SET_POS)
+#define GLB_REG_GPIO_21_SET_UMSK (~(((1U << GLB_REG_GPIO_21_SET_LEN) - 1) << GLB_REG_GPIO_21_SET_POS))
+#define GLB_REG_GPIO_21_CLR GLB_REG_GPIO_21_CLR
+#define GLB_REG_GPIO_21_CLR_POS (26U)
+#define GLB_REG_GPIO_21_CLR_LEN (1U)
+#define GLB_REG_GPIO_21_CLR_MSK (((1U << GLB_REG_GPIO_21_CLR_LEN) - 1) << GLB_REG_GPIO_21_CLR_POS)
+#define GLB_REG_GPIO_21_CLR_UMSK (~(((1U << GLB_REG_GPIO_21_CLR_LEN) - 1) << GLB_REG_GPIO_21_CLR_POS))
+#define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I
+#define GLB_REG_GPIO_21_I_POS (28U)
+#define GLB_REG_GPIO_21_I_LEN (1U)
+#define GLB_REG_GPIO_21_I_MSK (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
+#define GLB_REG_GPIO_21_I_UMSK (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
+#define GLB_REG_GPIO_21_MODE GLB_REG_GPIO_21_MODE
+#define GLB_REG_GPIO_21_MODE_POS (30U)
+#define GLB_REG_GPIO_21_MODE_LEN (2U)
+#define GLB_REG_GPIO_21_MODE_MSK (((1U << GLB_REG_GPIO_21_MODE_LEN) - 1) << GLB_REG_GPIO_21_MODE_POS)
+#define GLB_REG_GPIO_21_MODE_UMSK (~(((1U << GLB_REG_GPIO_21_MODE_LEN) - 1) << GLB_REG_GPIO_21_MODE_POS))
+
+/* 0x91C : gpio_cfg22 */
+#define GLB_GPIO_CFG22_OFFSET (0x91C)
+#define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE
+#define GLB_REG_GPIO_22_IE_POS (0U)
+#define GLB_REG_GPIO_22_IE_LEN (1U)
+#define GLB_REG_GPIO_22_IE_MSK (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
+#define GLB_REG_GPIO_22_IE_UMSK (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
+#define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT
+#define GLB_REG_GPIO_22_SMT_POS (1U)
+#define GLB_REG_GPIO_22_SMT_LEN (1U)
+#define GLB_REG_GPIO_22_SMT_MSK (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
+#define GLB_REG_GPIO_22_SMT_UMSK (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
+#define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV
+#define GLB_REG_GPIO_22_DRV_POS (2U)
+#define GLB_REG_GPIO_22_DRV_LEN (2U)
+#define GLB_REG_GPIO_22_DRV_MSK (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
+#define GLB_REG_GPIO_22_DRV_UMSK (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
+#define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU
+#define GLB_REG_GPIO_22_PU_POS (4U)
+#define GLB_REG_GPIO_22_PU_LEN (1U)
+#define GLB_REG_GPIO_22_PU_MSK (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
+#define GLB_REG_GPIO_22_PU_UMSK (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
+#define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD
+#define GLB_REG_GPIO_22_PD_POS (5U)
+#define GLB_REG_GPIO_22_PD_LEN (1U)
+#define GLB_REG_GPIO_22_PD_MSK (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
+#define GLB_REG_GPIO_22_PD_UMSK (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
+#define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE
+#define GLB_REG_GPIO_22_OE_POS (6U)
+#define GLB_REG_GPIO_22_OE_LEN (1U)
+#define GLB_REG_GPIO_22_OE_MSK (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
+#define GLB_REG_GPIO_22_OE_UMSK (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
+#define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL
+#define GLB_REG_GPIO_22_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_22_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_22_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
+#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS))
+#define GLB_REG_GPIO_22_INT_MODE_SET GLB_REG_GPIO_22_INT_MODE_SET
+#define GLB_REG_GPIO_22_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_22_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_22_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_22_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_22_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_22_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_22_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_22_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_22_INT_CLR GLB_REG_GPIO_22_INT_CLR
+#define GLB_REG_GPIO_22_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_22_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_22_INT_CLR_MSK (((1U << GLB_REG_GPIO_22_INT_CLR_LEN) - 1) << GLB_REG_GPIO_22_INT_CLR_POS)
+#define GLB_REG_GPIO_22_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_22_INT_CLR_LEN) - 1) << GLB_REG_GPIO_22_INT_CLR_POS))
+#define GLB_GPIO_22_INT_STAT GLB_GPIO_22_INT_STAT
+#define GLB_GPIO_22_INT_STAT_POS (21U)
+#define GLB_GPIO_22_INT_STAT_LEN (1U)
+#define GLB_GPIO_22_INT_STAT_MSK (((1U << GLB_GPIO_22_INT_STAT_LEN) - 1) << GLB_GPIO_22_INT_STAT_POS)
+#define GLB_GPIO_22_INT_STAT_UMSK (~(((1U << GLB_GPIO_22_INT_STAT_LEN) - 1) << GLB_GPIO_22_INT_STAT_POS))
+#define GLB_REG_GPIO_22_INT_MASK GLB_REG_GPIO_22_INT_MASK
+#define GLB_REG_GPIO_22_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_22_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_22_INT_MASK_MSK (((1U << GLB_REG_GPIO_22_INT_MASK_LEN) - 1) << GLB_REG_GPIO_22_INT_MASK_POS)
+#define GLB_REG_GPIO_22_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_22_INT_MASK_LEN) - 1) << GLB_REG_GPIO_22_INT_MASK_POS))
+#define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O
+#define GLB_REG_GPIO_22_O_POS (24U)
+#define GLB_REG_GPIO_22_O_LEN (1U)
+#define GLB_REG_GPIO_22_O_MSK (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
+#define GLB_REG_GPIO_22_O_UMSK (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
+#define GLB_REG_GPIO_22_SET GLB_REG_GPIO_22_SET
+#define GLB_REG_GPIO_22_SET_POS (25U)
+#define GLB_REG_GPIO_22_SET_LEN (1U)
+#define GLB_REG_GPIO_22_SET_MSK (((1U << GLB_REG_GPIO_22_SET_LEN) - 1) << GLB_REG_GPIO_22_SET_POS)
+#define GLB_REG_GPIO_22_SET_UMSK (~(((1U << GLB_REG_GPIO_22_SET_LEN) - 1) << GLB_REG_GPIO_22_SET_POS))
+#define GLB_REG_GPIO_22_CLR GLB_REG_GPIO_22_CLR
+#define GLB_REG_GPIO_22_CLR_POS (26U)
+#define GLB_REG_GPIO_22_CLR_LEN (1U)
+#define GLB_REG_GPIO_22_CLR_MSK (((1U << GLB_REG_GPIO_22_CLR_LEN) - 1) << GLB_REG_GPIO_22_CLR_POS)
+#define GLB_REG_GPIO_22_CLR_UMSK (~(((1U << GLB_REG_GPIO_22_CLR_LEN) - 1) << GLB_REG_GPIO_22_CLR_POS))
+#define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I
+#define GLB_REG_GPIO_22_I_POS (28U)
+#define GLB_REG_GPIO_22_I_LEN (1U)
+#define GLB_REG_GPIO_22_I_MSK (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
+#define GLB_REG_GPIO_22_I_UMSK (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
+#define GLB_REG_GPIO_22_MODE GLB_REG_GPIO_22_MODE
+#define GLB_REG_GPIO_22_MODE_POS (30U)
+#define GLB_REG_GPIO_22_MODE_LEN (2U)
+#define GLB_REG_GPIO_22_MODE_MSK (((1U << GLB_REG_GPIO_22_MODE_LEN) - 1) << GLB_REG_GPIO_22_MODE_POS)
+#define GLB_REG_GPIO_22_MODE_UMSK (~(((1U << GLB_REG_GPIO_22_MODE_LEN) - 1) << GLB_REG_GPIO_22_MODE_POS))
+
+/* 0x920 : gpio_cfg23 */
+#define GLB_GPIO_CFG23_OFFSET (0x920)
+#define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE
+#define GLB_REG_GPIO_23_IE_POS (0U)
+#define GLB_REG_GPIO_23_IE_LEN (1U)
+#define GLB_REG_GPIO_23_IE_MSK (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
+#define GLB_REG_GPIO_23_IE_UMSK (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
+#define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT
+#define GLB_REG_GPIO_23_SMT_POS (1U)
+#define GLB_REG_GPIO_23_SMT_LEN (1U)
+#define GLB_REG_GPIO_23_SMT_MSK (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
+#define GLB_REG_GPIO_23_SMT_UMSK (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
+#define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV
+#define GLB_REG_GPIO_23_DRV_POS (2U)
+#define GLB_REG_GPIO_23_DRV_LEN (2U)
+#define GLB_REG_GPIO_23_DRV_MSK (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
+#define GLB_REG_GPIO_23_DRV_UMSK (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
+#define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU
+#define GLB_REG_GPIO_23_PU_POS (4U)
+#define GLB_REG_GPIO_23_PU_LEN (1U)
+#define GLB_REG_GPIO_23_PU_MSK (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
+#define GLB_REG_GPIO_23_PU_UMSK (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
+#define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD
+#define GLB_REG_GPIO_23_PD_POS (5U)
+#define GLB_REG_GPIO_23_PD_LEN (1U)
+#define GLB_REG_GPIO_23_PD_MSK (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
+#define GLB_REG_GPIO_23_PD_UMSK (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
+#define GLB_REG_GPIO_23_OE GLB_REG_GPIO_23_OE
+#define GLB_REG_GPIO_23_OE_POS (6U)
+#define GLB_REG_GPIO_23_OE_LEN (1U)
+#define GLB_REG_GPIO_23_OE_MSK (((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS)
+#define GLB_REG_GPIO_23_OE_UMSK (~(((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS))
+#define GLB_REG_GPIO_23_FUNC_SEL GLB_REG_GPIO_23_FUNC_SEL
+#define GLB_REG_GPIO_23_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_23_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_23_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS)
+#define GLB_REG_GPIO_23_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS))
+#define GLB_REG_GPIO_23_INT_MODE_SET GLB_REG_GPIO_23_INT_MODE_SET
+#define GLB_REG_GPIO_23_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_23_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_23_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_23_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_23_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_23_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_23_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_23_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_23_INT_CLR GLB_REG_GPIO_23_INT_CLR
+#define GLB_REG_GPIO_23_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_23_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_23_INT_CLR_MSK (((1U << GLB_REG_GPIO_23_INT_CLR_LEN) - 1) << GLB_REG_GPIO_23_INT_CLR_POS)
+#define GLB_REG_GPIO_23_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_23_INT_CLR_LEN) - 1) << GLB_REG_GPIO_23_INT_CLR_POS))
+#define GLB_GPIO_23_INT_STAT GLB_GPIO_23_INT_STAT
+#define GLB_GPIO_23_INT_STAT_POS (21U)
+#define GLB_GPIO_23_INT_STAT_LEN (1U)
+#define GLB_GPIO_23_INT_STAT_MSK (((1U << GLB_GPIO_23_INT_STAT_LEN) - 1) << GLB_GPIO_23_INT_STAT_POS)
+#define GLB_GPIO_23_INT_STAT_UMSK (~(((1U << GLB_GPIO_23_INT_STAT_LEN) - 1) << GLB_GPIO_23_INT_STAT_POS))
+#define GLB_REG_GPIO_23_INT_MASK GLB_REG_GPIO_23_INT_MASK
+#define GLB_REG_GPIO_23_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_23_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_23_INT_MASK_MSK (((1U << GLB_REG_GPIO_23_INT_MASK_LEN) - 1) << GLB_REG_GPIO_23_INT_MASK_POS)
+#define GLB_REG_GPIO_23_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_23_INT_MASK_LEN) - 1) << GLB_REG_GPIO_23_INT_MASK_POS))
+#define GLB_REG_GPIO_23_O GLB_REG_GPIO_23_O
+#define GLB_REG_GPIO_23_O_POS (24U)
+#define GLB_REG_GPIO_23_O_LEN (1U)
+#define GLB_REG_GPIO_23_O_MSK (((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS)
+#define GLB_REG_GPIO_23_O_UMSK (~(((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS))
+#define GLB_REG_GPIO_23_SET GLB_REG_GPIO_23_SET
+#define GLB_REG_GPIO_23_SET_POS (25U)
+#define GLB_REG_GPIO_23_SET_LEN (1U)
+#define GLB_REG_GPIO_23_SET_MSK (((1U << GLB_REG_GPIO_23_SET_LEN) - 1) << GLB_REG_GPIO_23_SET_POS)
+#define GLB_REG_GPIO_23_SET_UMSK (~(((1U << GLB_REG_GPIO_23_SET_LEN) - 1) << GLB_REG_GPIO_23_SET_POS))
+#define GLB_REG_GPIO_23_CLR GLB_REG_GPIO_23_CLR
+#define GLB_REG_GPIO_23_CLR_POS (26U)
+#define GLB_REG_GPIO_23_CLR_LEN (1U)
+#define GLB_REG_GPIO_23_CLR_MSK (((1U << GLB_REG_GPIO_23_CLR_LEN) - 1) << GLB_REG_GPIO_23_CLR_POS)
+#define GLB_REG_GPIO_23_CLR_UMSK (~(((1U << GLB_REG_GPIO_23_CLR_LEN) - 1) << GLB_REG_GPIO_23_CLR_POS))
+#define GLB_REG_GPIO_23_I GLB_REG_GPIO_23_I
+#define GLB_REG_GPIO_23_I_POS (28U)
+#define GLB_REG_GPIO_23_I_LEN (1U)
+#define GLB_REG_GPIO_23_I_MSK (((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS)
+#define GLB_REG_GPIO_23_I_UMSK (~(((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS))
+#define GLB_REG_GPIO_23_MODE GLB_REG_GPIO_23_MODE
+#define GLB_REG_GPIO_23_MODE_POS (30U)
+#define GLB_REG_GPIO_23_MODE_LEN (2U)
+#define GLB_REG_GPIO_23_MODE_MSK (((1U << GLB_REG_GPIO_23_MODE_LEN) - 1) << GLB_REG_GPIO_23_MODE_POS)
+#define GLB_REG_GPIO_23_MODE_UMSK (~(((1U << GLB_REG_GPIO_23_MODE_LEN) - 1) << GLB_REG_GPIO_23_MODE_POS))
+
+/* 0x924 : gpio_cfg24 */
+#define GLB_GPIO_CFG24_OFFSET (0x924)
+#define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE
+#define GLB_REG_GPIO_24_IE_POS (0U)
+#define GLB_REG_GPIO_24_IE_LEN (1U)
+#define GLB_REG_GPIO_24_IE_MSK (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
+#define GLB_REG_GPIO_24_IE_UMSK (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
+#define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT
+#define GLB_REG_GPIO_24_SMT_POS (1U)
+#define GLB_REG_GPIO_24_SMT_LEN (1U)
+#define GLB_REG_GPIO_24_SMT_MSK (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
+#define GLB_REG_GPIO_24_SMT_UMSK (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
+#define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV
+#define GLB_REG_GPIO_24_DRV_POS (2U)
+#define GLB_REG_GPIO_24_DRV_LEN (2U)
+#define GLB_REG_GPIO_24_DRV_MSK (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
+#define GLB_REG_GPIO_24_DRV_UMSK (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
+#define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU
+#define GLB_REG_GPIO_24_PU_POS (4U)
+#define GLB_REG_GPIO_24_PU_LEN (1U)
+#define GLB_REG_GPIO_24_PU_MSK (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
+#define GLB_REG_GPIO_24_PU_UMSK (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
+#define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD
+#define GLB_REG_GPIO_24_PD_POS (5U)
+#define GLB_REG_GPIO_24_PD_LEN (1U)
+#define GLB_REG_GPIO_24_PD_MSK (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
+#define GLB_REG_GPIO_24_PD_UMSK (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
+#define GLB_REG_GPIO_24_OE GLB_REG_GPIO_24_OE
+#define GLB_REG_GPIO_24_OE_POS (6U)
+#define GLB_REG_GPIO_24_OE_LEN (1U)
+#define GLB_REG_GPIO_24_OE_MSK (((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS)
+#define GLB_REG_GPIO_24_OE_UMSK (~(((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS))
+#define GLB_REG_GPIO_24_FUNC_SEL GLB_REG_GPIO_24_FUNC_SEL
+#define GLB_REG_GPIO_24_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_24_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_24_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS)
+#define GLB_REG_GPIO_24_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS))
+#define GLB_REG_GPIO_24_INT_MODE_SET GLB_REG_GPIO_24_INT_MODE_SET
+#define GLB_REG_GPIO_24_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_24_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_24_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_24_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_24_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_24_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_24_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_24_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_24_INT_CLR GLB_REG_GPIO_24_INT_CLR
+#define GLB_REG_GPIO_24_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_24_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_24_INT_CLR_MSK (((1U << GLB_REG_GPIO_24_INT_CLR_LEN) - 1) << GLB_REG_GPIO_24_INT_CLR_POS)
+#define GLB_REG_GPIO_24_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_24_INT_CLR_LEN) - 1) << GLB_REG_GPIO_24_INT_CLR_POS))
+#define GLB_GPIO_24_INT_STAT GLB_GPIO_24_INT_STAT
+#define GLB_GPIO_24_INT_STAT_POS (21U)
+#define GLB_GPIO_24_INT_STAT_LEN (1U)
+#define GLB_GPIO_24_INT_STAT_MSK (((1U << GLB_GPIO_24_INT_STAT_LEN) - 1) << GLB_GPIO_24_INT_STAT_POS)
+#define GLB_GPIO_24_INT_STAT_UMSK (~(((1U << GLB_GPIO_24_INT_STAT_LEN) - 1) << GLB_GPIO_24_INT_STAT_POS))
+#define GLB_REG_GPIO_24_INT_MASK GLB_REG_GPIO_24_INT_MASK
+#define GLB_REG_GPIO_24_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_24_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_24_INT_MASK_MSK (((1U << GLB_REG_GPIO_24_INT_MASK_LEN) - 1) << GLB_REG_GPIO_24_INT_MASK_POS)
+#define GLB_REG_GPIO_24_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_24_INT_MASK_LEN) - 1) << GLB_REG_GPIO_24_INT_MASK_POS))
+#define GLB_REG_GPIO_24_O GLB_REG_GPIO_24_O
+#define GLB_REG_GPIO_24_O_POS (24U)
+#define GLB_REG_GPIO_24_O_LEN (1U)
+#define GLB_REG_GPIO_24_O_MSK (((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS)
+#define GLB_REG_GPIO_24_O_UMSK (~(((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS))
+#define GLB_REG_GPIO_24_SET GLB_REG_GPIO_24_SET
+#define GLB_REG_GPIO_24_SET_POS (25U)
+#define GLB_REG_GPIO_24_SET_LEN (1U)
+#define GLB_REG_GPIO_24_SET_MSK (((1U << GLB_REG_GPIO_24_SET_LEN) - 1) << GLB_REG_GPIO_24_SET_POS)
+#define GLB_REG_GPIO_24_SET_UMSK (~(((1U << GLB_REG_GPIO_24_SET_LEN) - 1) << GLB_REG_GPIO_24_SET_POS))
+#define GLB_REG_GPIO_24_CLR GLB_REG_GPIO_24_CLR
+#define GLB_REG_GPIO_24_CLR_POS (26U)
+#define GLB_REG_GPIO_24_CLR_LEN (1U)
+#define GLB_REG_GPIO_24_CLR_MSK (((1U << GLB_REG_GPIO_24_CLR_LEN) - 1) << GLB_REG_GPIO_24_CLR_POS)
+#define GLB_REG_GPIO_24_CLR_UMSK (~(((1U << GLB_REG_GPIO_24_CLR_LEN) - 1) << GLB_REG_GPIO_24_CLR_POS))
+#define GLB_REG_GPIO_24_I GLB_REG_GPIO_24_I
+#define GLB_REG_GPIO_24_I_POS (28U)
+#define GLB_REG_GPIO_24_I_LEN (1U)
+#define GLB_REG_GPIO_24_I_MSK (((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS)
+#define GLB_REG_GPIO_24_I_UMSK (~(((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS))
+#define GLB_REG_GPIO_24_MODE GLB_REG_GPIO_24_MODE
+#define GLB_REG_GPIO_24_MODE_POS (30U)
+#define GLB_REG_GPIO_24_MODE_LEN (2U)
+#define GLB_REG_GPIO_24_MODE_MSK (((1U << GLB_REG_GPIO_24_MODE_LEN) - 1) << GLB_REG_GPIO_24_MODE_POS)
+#define GLB_REG_GPIO_24_MODE_UMSK (~(((1U << GLB_REG_GPIO_24_MODE_LEN) - 1) << GLB_REG_GPIO_24_MODE_POS))
+
+/* 0x928 : gpio_cfg25 */
+#define GLB_GPIO_CFG25_OFFSET (0x928)
+#define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE
+#define GLB_REG_GPIO_25_IE_POS (0U)
+#define GLB_REG_GPIO_25_IE_LEN (1U)
+#define GLB_REG_GPIO_25_IE_MSK (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
+#define GLB_REG_GPIO_25_IE_UMSK (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
+#define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT
+#define GLB_REG_GPIO_25_SMT_POS (1U)
+#define GLB_REG_GPIO_25_SMT_LEN (1U)
+#define GLB_REG_GPIO_25_SMT_MSK (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
+#define GLB_REG_GPIO_25_SMT_UMSK (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
+#define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV
+#define GLB_REG_GPIO_25_DRV_POS (2U)
+#define GLB_REG_GPIO_25_DRV_LEN (2U)
+#define GLB_REG_GPIO_25_DRV_MSK (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
+#define GLB_REG_GPIO_25_DRV_UMSK (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
+#define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU
+#define GLB_REG_GPIO_25_PU_POS (4U)
+#define GLB_REG_GPIO_25_PU_LEN (1U)
+#define GLB_REG_GPIO_25_PU_MSK (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
+#define GLB_REG_GPIO_25_PU_UMSK (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
+#define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD
+#define GLB_REG_GPIO_25_PD_POS (5U)
+#define GLB_REG_GPIO_25_PD_LEN (1U)
+#define GLB_REG_GPIO_25_PD_MSK (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
+#define GLB_REG_GPIO_25_PD_UMSK (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
+#define GLB_REG_GPIO_25_OE GLB_REG_GPIO_25_OE
+#define GLB_REG_GPIO_25_OE_POS (6U)
+#define GLB_REG_GPIO_25_OE_LEN (1U)
+#define GLB_REG_GPIO_25_OE_MSK (((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS)
+#define GLB_REG_GPIO_25_OE_UMSK (~(((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS))
+#define GLB_REG_GPIO_25_FUNC_SEL GLB_REG_GPIO_25_FUNC_SEL
+#define GLB_REG_GPIO_25_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_25_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_25_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS)
+#define GLB_REG_GPIO_25_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS))
+#define GLB_REG_GPIO_25_INT_MODE_SET GLB_REG_GPIO_25_INT_MODE_SET
+#define GLB_REG_GPIO_25_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_25_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_25_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_25_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_25_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_25_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_25_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_25_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_25_INT_CLR GLB_REG_GPIO_25_INT_CLR
+#define GLB_REG_GPIO_25_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_25_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_25_INT_CLR_MSK (((1U << GLB_REG_GPIO_25_INT_CLR_LEN) - 1) << GLB_REG_GPIO_25_INT_CLR_POS)
+#define GLB_REG_GPIO_25_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_25_INT_CLR_LEN) - 1) << GLB_REG_GPIO_25_INT_CLR_POS))
+#define GLB_GPIO_25_INT_STAT GLB_GPIO_25_INT_STAT
+#define GLB_GPIO_25_INT_STAT_POS (21U)
+#define GLB_GPIO_25_INT_STAT_LEN (1U)
+#define GLB_GPIO_25_INT_STAT_MSK (((1U << GLB_GPIO_25_INT_STAT_LEN) - 1) << GLB_GPIO_25_INT_STAT_POS)
+#define GLB_GPIO_25_INT_STAT_UMSK (~(((1U << GLB_GPIO_25_INT_STAT_LEN) - 1) << GLB_GPIO_25_INT_STAT_POS))
+#define GLB_REG_GPIO_25_INT_MASK GLB_REG_GPIO_25_INT_MASK
+#define GLB_REG_GPIO_25_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_25_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_25_INT_MASK_MSK (((1U << GLB_REG_GPIO_25_INT_MASK_LEN) - 1) << GLB_REG_GPIO_25_INT_MASK_POS)
+#define GLB_REG_GPIO_25_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_25_INT_MASK_LEN) - 1) << GLB_REG_GPIO_25_INT_MASK_POS))
+#define GLB_REG_GPIO_25_O GLB_REG_GPIO_25_O
+#define GLB_REG_GPIO_25_O_POS (24U)
+#define GLB_REG_GPIO_25_O_LEN (1U)
+#define GLB_REG_GPIO_25_O_MSK (((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS)
+#define GLB_REG_GPIO_25_O_UMSK (~(((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS))
+#define GLB_REG_GPIO_25_SET GLB_REG_GPIO_25_SET
+#define GLB_REG_GPIO_25_SET_POS (25U)
+#define GLB_REG_GPIO_25_SET_LEN (1U)
+#define GLB_REG_GPIO_25_SET_MSK (((1U << GLB_REG_GPIO_25_SET_LEN) - 1) << GLB_REG_GPIO_25_SET_POS)
+#define GLB_REG_GPIO_25_SET_UMSK (~(((1U << GLB_REG_GPIO_25_SET_LEN) - 1) << GLB_REG_GPIO_25_SET_POS))
+#define GLB_REG_GPIO_25_CLR GLB_REG_GPIO_25_CLR
+#define GLB_REG_GPIO_25_CLR_POS (26U)
+#define GLB_REG_GPIO_25_CLR_LEN (1U)
+#define GLB_REG_GPIO_25_CLR_MSK (((1U << GLB_REG_GPIO_25_CLR_LEN) - 1) << GLB_REG_GPIO_25_CLR_POS)
+#define GLB_REG_GPIO_25_CLR_UMSK (~(((1U << GLB_REG_GPIO_25_CLR_LEN) - 1) << GLB_REG_GPIO_25_CLR_POS))
+#define GLB_REG_GPIO_25_I GLB_REG_GPIO_25_I
+#define GLB_REG_GPIO_25_I_POS (28U)
+#define GLB_REG_GPIO_25_I_LEN (1U)
+#define GLB_REG_GPIO_25_I_MSK (((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS)
+#define GLB_REG_GPIO_25_I_UMSK (~(((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS))
+#define GLB_REG_GPIO_25_MODE GLB_REG_GPIO_25_MODE
+#define GLB_REG_GPIO_25_MODE_POS (30U)
+#define GLB_REG_GPIO_25_MODE_LEN (2U)
+#define GLB_REG_GPIO_25_MODE_MSK (((1U << GLB_REG_GPIO_25_MODE_LEN) - 1) << GLB_REG_GPIO_25_MODE_POS)
+#define GLB_REG_GPIO_25_MODE_UMSK (~(((1U << GLB_REG_GPIO_25_MODE_LEN) - 1) << GLB_REG_GPIO_25_MODE_POS))
+
+/* 0x92C : gpio_cfg26 */
+#define GLB_GPIO_CFG26_OFFSET (0x92C)
+#define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE
+#define GLB_REG_GPIO_26_IE_POS (0U)
+#define GLB_REG_GPIO_26_IE_LEN (1U)
+#define GLB_REG_GPIO_26_IE_MSK (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
+#define GLB_REG_GPIO_26_IE_UMSK (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
+#define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT
+#define GLB_REG_GPIO_26_SMT_POS (1U)
+#define GLB_REG_GPIO_26_SMT_LEN (1U)
+#define GLB_REG_GPIO_26_SMT_MSK (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
+#define GLB_REG_GPIO_26_SMT_UMSK (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
+#define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV
+#define GLB_REG_GPIO_26_DRV_POS (2U)
+#define GLB_REG_GPIO_26_DRV_LEN (2U)
+#define GLB_REG_GPIO_26_DRV_MSK (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
+#define GLB_REG_GPIO_26_DRV_UMSK (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
+#define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU
+#define GLB_REG_GPIO_26_PU_POS (4U)
+#define GLB_REG_GPIO_26_PU_LEN (1U)
+#define GLB_REG_GPIO_26_PU_MSK (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
+#define GLB_REG_GPIO_26_PU_UMSK (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
+#define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD
+#define GLB_REG_GPIO_26_PD_POS (5U)
+#define GLB_REG_GPIO_26_PD_LEN (1U)
+#define GLB_REG_GPIO_26_PD_MSK (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
+#define GLB_REG_GPIO_26_PD_UMSK (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
+#define GLB_REG_GPIO_26_OE GLB_REG_GPIO_26_OE
+#define GLB_REG_GPIO_26_OE_POS (6U)
+#define GLB_REG_GPIO_26_OE_LEN (1U)
+#define GLB_REG_GPIO_26_OE_MSK (((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS)
+#define GLB_REG_GPIO_26_OE_UMSK (~(((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS))
+#define GLB_REG_GPIO_26_FUNC_SEL GLB_REG_GPIO_26_FUNC_SEL
+#define GLB_REG_GPIO_26_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_26_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_26_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS)
+#define GLB_REG_GPIO_26_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS))
+#define GLB_REG_GPIO_26_INT_MODE_SET GLB_REG_GPIO_26_INT_MODE_SET
+#define GLB_REG_GPIO_26_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_26_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_26_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_26_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_26_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_26_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_26_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_26_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_26_INT_CLR GLB_REG_GPIO_26_INT_CLR
+#define GLB_REG_GPIO_26_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_26_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_26_INT_CLR_MSK (((1U << GLB_REG_GPIO_26_INT_CLR_LEN) - 1) << GLB_REG_GPIO_26_INT_CLR_POS)
+#define GLB_REG_GPIO_26_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_26_INT_CLR_LEN) - 1) << GLB_REG_GPIO_26_INT_CLR_POS))
+#define GLB_GPIO_26_INT_STAT GLB_GPIO_26_INT_STAT
+#define GLB_GPIO_26_INT_STAT_POS (21U)
+#define GLB_GPIO_26_INT_STAT_LEN (1U)
+#define GLB_GPIO_26_INT_STAT_MSK (((1U << GLB_GPIO_26_INT_STAT_LEN) - 1) << GLB_GPIO_26_INT_STAT_POS)
+#define GLB_GPIO_26_INT_STAT_UMSK (~(((1U << GLB_GPIO_26_INT_STAT_LEN) - 1) << GLB_GPIO_26_INT_STAT_POS))
+#define GLB_REG_GPIO_26_INT_MASK GLB_REG_GPIO_26_INT_MASK
+#define GLB_REG_GPIO_26_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_26_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_26_INT_MASK_MSK (((1U << GLB_REG_GPIO_26_INT_MASK_LEN) - 1) << GLB_REG_GPIO_26_INT_MASK_POS)
+#define GLB_REG_GPIO_26_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_26_INT_MASK_LEN) - 1) << GLB_REG_GPIO_26_INT_MASK_POS))
+#define GLB_REG_GPIO_26_O GLB_REG_GPIO_26_O
+#define GLB_REG_GPIO_26_O_POS (24U)
+#define GLB_REG_GPIO_26_O_LEN (1U)
+#define GLB_REG_GPIO_26_O_MSK (((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS)
+#define GLB_REG_GPIO_26_O_UMSK (~(((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS))
+#define GLB_REG_GPIO_26_SET GLB_REG_GPIO_26_SET
+#define GLB_REG_GPIO_26_SET_POS (25U)
+#define GLB_REG_GPIO_26_SET_LEN (1U)
+#define GLB_REG_GPIO_26_SET_MSK (((1U << GLB_REG_GPIO_26_SET_LEN) - 1) << GLB_REG_GPIO_26_SET_POS)
+#define GLB_REG_GPIO_26_SET_UMSK (~(((1U << GLB_REG_GPIO_26_SET_LEN) - 1) << GLB_REG_GPIO_26_SET_POS))
+#define GLB_REG_GPIO_26_CLR GLB_REG_GPIO_26_CLR
+#define GLB_REG_GPIO_26_CLR_POS (26U)
+#define GLB_REG_GPIO_26_CLR_LEN (1U)
+#define GLB_REG_GPIO_26_CLR_MSK (((1U << GLB_REG_GPIO_26_CLR_LEN) - 1) << GLB_REG_GPIO_26_CLR_POS)
+#define GLB_REG_GPIO_26_CLR_UMSK (~(((1U << GLB_REG_GPIO_26_CLR_LEN) - 1) << GLB_REG_GPIO_26_CLR_POS))
+#define GLB_REG_GPIO_26_I GLB_REG_GPIO_26_I
+#define GLB_REG_GPIO_26_I_POS (28U)
+#define GLB_REG_GPIO_26_I_LEN (1U)
+#define GLB_REG_GPIO_26_I_MSK (((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS)
+#define GLB_REG_GPIO_26_I_UMSK (~(((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS))
+#define GLB_REG_GPIO_26_MODE GLB_REG_GPIO_26_MODE
+#define GLB_REG_GPIO_26_MODE_POS (30U)
+#define GLB_REG_GPIO_26_MODE_LEN (2U)
+#define GLB_REG_GPIO_26_MODE_MSK (((1U << GLB_REG_GPIO_26_MODE_LEN) - 1) << GLB_REG_GPIO_26_MODE_POS)
+#define GLB_REG_GPIO_26_MODE_UMSK (~(((1U << GLB_REG_GPIO_26_MODE_LEN) - 1) << GLB_REG_GPIO_26_MODE_POS))
+
+/* 0x930 : gpio_cfg27 */
+#define GLB_GPIO_CFG27_OFFSET (0x930)
+#define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE
+#define GLB_REG_GPIO_27_IE_POS (0U)
+#define GLB_REG_GPIO_27_IE_LEN (1U)
+#define GLB_REG_GPIO_27_IE_MSK (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
+#define GLB_REG_GPIO_27_IE_UMSK (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
+#define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT
+#define GLB_REG_GPIO_27_SMT_POS (1U)
+#define GLB_REG_GPIO_27_SMT_LEN (1U)
+#define GLB_REG_GPIO_27_SMT_MSK (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
+#define GLB_REG_GPIO_27_SMT_UMSK (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
+#define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV
+#define GLB_REG_GPIO_27_DRV_POS (2U)
+#define GLB_REG_GPIO_27_DRV_LEN (2U)
+#define GLB_REG_GPIO_27_DRV_MSK (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
+#define GLB_REG_GPIO_27_DRV_UMSK (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
+#define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU
+#define GLB_REG_GPIO_27_PU_POS (4U)
+#define GLB_REG_GPIO_27_PU_LEN (1U)
+#define GLB_REG_GPIO_27_PU_MSK (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
+#define GLB_REG_GPIO_27_PU_UMSK (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
+#define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD
+#define GLB_REG_GPIO_27_PD_POS (5U)
+#define GLB_REG_GPIO_27_PD_LEN (1U)
+#define GLB_REG_GPIO_27_PD_MSK (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
+#define GLB_REG_GPIO_27_PD_UMSK (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
+#define GLB_REG_GPIO_27_OE GLB_REG_GPIO_27_OE
+#define GLB_REG_GPIO_27_OE_POS (6U)
+#define GLB_REG_GPIO_27_OE_LEN (1U)
+#define GLB_REG_GPIO_27_OE_MSK (((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS)
+#define GLB_REG_GPIO_27_OE_UMSK (~(((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS))
+#define GLB_REG_GPIO_27_FUNC_SEL GLB_REG_GPIO_27_FUNC_SEL
+#define GLB_REG_GPIO_27_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_27_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_27_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS)
+#define GLB_REG_GPIO_27_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS))
+#define GLB_REG_GPIO_27_INT_MODE_SET GLB_REG_GPIO_27_INT_MODE_SET
+#define GLB_REG_GPIO_27_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_27_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_27_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_27_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_27_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_27_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_27_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_27_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_27_INT_CLR GLB_REG_GPIO_27_INT_CLR
+#define GLB_REG_GPIO_27_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_27_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_27_INT_CLR_MSK (((1U << GLB_REG_GPIO_27_INT_CLR_LEN) - 1) << GLB_REG_GPIO_27_INT_CLR_POS)
+#define GLB_REG_GPIO_27_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_27_INT_CLR_LEN) - 1) << GLB_REG_GPIO_27_INT_CLR_POS))
+#define GLB_GPIO_27_INT_STAT GLB_GPIO_27_INT_STAT
+#define GLB_GPIO_27_INT_STAT_POS (21U)
+#define GLB_GPIO_27_INT_STAT_LEN (1U)
+#define GLB_GPIO_27_INT_STAT_MSK (((1U << GLB_GPIO_27_INT_STAT_LEN) - 1) << GLB_GPIO_27_INT_STAT_POS)
+#define GLB_GPIO_27_INT_STAT_UMSK (~(((1U << GLB_GPIO_27_INT_STAT_LEN) - 1) << GLB_GPIO_27_INT_STAT_POS))
+#define GLB_REG_GPIO_27_INT_MASK GLB_REG_GPIO_27_INT_MASK
+#define GLB_REG_GPIO_27_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_27_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_27_INT_MASK_MSK (((1U << GLB_REG_GPIO_27_INT_MASK_LEN) - 1) << GLB_REG_GPIO_27_INT_MASK_POS)
+#define GLB_REG_GPIO_27_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_27_INT_MASK_LEN) - 1) << GLB_REG_GPIO_27_INT_MASK_POS))
+#define GLB_REG_GPIO_27_O GLB_REG_GPIO_27_O
+#define GLB_REG_GPIO_27_O_POS (24U)
+#define GLB_REG_GPIO_27_O_LEN (1U)
+#define GLB_REG_GPIO_27_O_MSK (((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS)
+#define GLB_REG_GPIO_27_O_UMSK (~(((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS))
+#define GLB_REG_GPIO_27_SET GLB_REG_GPIO_27_SET
+#define GLB_REG_GPIO_27_SET_POS (25U)
+#define GLB_REG_GPIO_27_SET_LEN (1U)
+#define GLB_REG_GPIO_27_SET_MSK (((1U << GLB_REG_GPIO_27_SET_LEN) - 1) << GLB_REG_GPIO_27_SET_POS)
+#define GLB_REG_GPIO_27_SET_UMSK (~(((1U << GLB_REG_GPIO_27_SET_LEN) - 1) << GLB_REG_GPIO_27_SET_POS))
+#define GLB_REG_GPIO_27_CLR GLB_REG_GPIO_27_CLR
+#define GLB_REG_GPIO_27_CLR_POS (26U)
+#define GLB_REG_GPIO_27_CLR_LEN (1U)
+#define GLB_REG_GPIO_27_CLR_MSK (((1U << GLB_REG_GPIO_27_CLR_LEN) - 1) << GLB_REG_GPIO_27_CLR_POS)
+#define GLB_REG_GPIO_27_CLR_UMSK (~(((1U << GLB_REG_GPIO_27_CLR_LEN) - 1) << GLB_REG_GPIO_27_CLR_POS))
+#define GLB_REG_GPIO_27_I GLB_REG_GPIO_27_I
+#define GLB_REG_GPIO_27_I_POS (28U)
+#define GLB_REG_GPIO_27_I_LEN (1U)
+#define GLB_REG_GPIO_27_I_MSK (((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS)
+#define GLB_REG_GPIO_27_I_UMSK (~(((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS))
+#define GLB_REG_GPIO_27_MODE GLB_REG_GPIO_27_MODE
+#define GLB_REG_GPIO_27_MODE_POS (30U)
+#define GLB_REG_GPIO_27_MODE_LEN (2U)
+#define GLB_REG_GPIO_27_MODE_MSK (((1U << GLB_REG_GPIO_27_MODE_LEN) - 1) << GLB_REG_GPIO_27_MODE_POS)
+#define GLB_REG_GPIO_27_MODE_UMSK (~(((1U << GLB_REG_GPIO_27_MODE_LEN) - 1) << GLB_REG_GPIO_27_MODE_POS))
+
+/* 0x934 : gpio_cfg28 */
+#define GLB_GPIO_CFG28_OFFSET (0x934)
+#define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE
+#define GLB_REG_GPIO_28_IE_POS (0U)
+#define GLB_REG_GPIO_28_IE_LEN (1U)
+#define GLB_REG_GPIO_28_IE_MSK (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
+#define GLB_REG_GPIO_28_IE_UMSK (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
+#define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT
+#define GLB_REG_GPIO_28_SMT_POS (1U)
+#define GLB_REG_GPIO_28_SMT_LEN (1U)
+#define GLB_REG_GPIO_28_SMT_MSK (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
+#define GLB_REG_GPIO_28_SMT_UMSK (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
+#define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV
+#define GLB_REG_GPIO_28_DRV_POS (2U)
+#define GLB_REG_GPIO_28_DRV_LEN (2U)
+#define GLB_REG_GPIO_28_DRV_MSK (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
+#define GLB_REG_GPIO_28_DRV_UMSK (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
+#define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU
+#define GLB_REG_GPIO_28_PU_POS (4U)
+#define GLB_REG_GPIO_28_PU_LEN (1U)
+#define GLB_REG_GPIO_28_PU_MSK (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
+#define GLB_REG_GPIO_28_PU_UMSK (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
+#define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD
+#define GLB_REG_GPIO_28_PD_POS (5U)
+#define GLB_REG_GPIO_28_PD_LEN (1U)
+#define GLB_REG_GPIO_28_PD_MSK (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
+#define GLB_REG_GPIO_28_PD_UMSK (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
+#define GLB_REG_GPIO_28_OE GLB_REG_GPIO_28_OE
+#define GLB_REG_GPIO_28_OE_POS (6U)
+#define GLB_REG_GPIO_28_OE_LEN (1U)
+#define GLB_REG_GPIO_28_OE_MSK (((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS)
+#define GLB_REG_GPIO_28_OE_UMSK (~(((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS))
+#define GLB_REG_GPIO_28_FUNC_SEL GLB_REG_GPIO_28_FUNC_SEL
+#define GLB_REG_GPIO_28_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_28_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_28_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS)
+#define GLB_REG_GPIO_28_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS))
+#define GLB_REG_GPIO_28_INT_MODE_SET GLB_REG_GPIO_28_INT_MODE_SET
+#define GLB_REG_GPIO_28_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_28_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_28_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_28_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_28_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_28_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_28_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_28_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_28_INT_CLR GLB_REG_GPIO_28_INT_CLR
+#define GLB_REG_GPIO_28_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_28_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_28_INT_CLR_MSK (((1U << GLB_REG_GPIO_28_INT_CLR_LEN) - 1) << GLB_REG_GPIO_28_INT_CLR_POS)
+#define GLB_REG_GPIO_28_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_28_INT_CLR_LEN) - 1) << GLB_REG_GPIO_28_INT_CLR_POS))
+#define GLB_GPIO_28_INT_STAT GLB_GPIO_28_INT_STAT
+#define GLB_GPIO_28_INT_STAT_POS (21U)
+#define GLB_GPIO_28_INT_STAT_LEN (1U)
+#define GLB_GPIO_28_INT_STAT_MSK (((1U << GLB_GPIO_28_INT_STAT_LEN) - 1) << GLB_GPIO_28_INT_STAT_POS)
+#define GLB_GPIO_28_INT_STAT_UMSK (~(((1U << GLB_GPIO_28_INT_STAT_LEN) - 1) << GLB_GPIO_28_INT_STAT_POS))
+#define GLB_REG_GPIO_28_INT_MASK GLB_REG_GPIO_28_INT_MASK
+#define GLB_REG_GPIO_28_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_28_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_28_INT_MASK_MSK (((1U << GLB_REG_GPIO_28_INT_MASK_LEN) - 1) << GLB_REG_GPIO_28_INT_MASK_POS)
+#define GLB_REG_GPIO_28_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_28_INT_MASK_LEN) - 1) << GLB_REG_GPIO_28_INT_MASK_POS))
+#define GLB_REG_GPIO_28_O GLB_REG_GPIO_28_O
+#define GLB_REG_GPIO_28_O_POS (24U)
+#define GLB_REG_GPIO_28_O_LEN (1U)
+#define GLB_REG_GPIO_28_O_MSK (((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS)
+#define GLB_REG_GPIO_28_O_UMSK (~(((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS))
+#define GLB_REG_GPIO_28_SET GLB_REG_GPIO_28_SET
+#define GLB_REG_GPIO_28_SET_POS (25U)
+#define GLB_REG_GPIO_28_SET_LEN (1U)
+#define GLB_REG_GPIO_28_SET_MSK (((1U << GLB_REG_GPIO_28_SET_LEN) - 1) << GLB_REG_GPIO_28_SET_POS)
+#define GLB_REG_GPIO_28_SET_UMSK (~(((1U << GLB_REG_GPIO_28_SET_LEN) - 1) << GLB_REG_GPIO_28_SET_POS))
+#define GLB_REG_GPIO_28_CLR GLB_REG_GPIO_28_CLR
+#define GLB_REG_GPIO_28_CLR_POS (26U)
+#define GLB_REG_GPIO_28_CLR_LEN (1U)
+#define GLB_REG_GPIO_28_CLR_MSK (((1U << GLB_REG_GPIO_28_CLR_LEN) - 1) << GLB_REG_GPIO_28_CLR_POS)
+#define GLB_REG_GPIO_28_CLR_UMSK (~(((1U << GLB_REG_GPIO_28_CLR_LEN) - 1) << GLB_REG_GPIO_28_CLR_POS))
+#define GLB_REG_GPIO_28_I GLB_REG_GPIO_28_I
+#define GLB_REG_GPIO_28_I_POS (28U)
+#define GLB_REG_GPIO_28_I_LEN (1U)
+#define GLB_REG_GPIO_28_I_MSK (((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS)
+#define GLB_REG_GPIO_28_I_UMSK (~(((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS))
+#define GLB_REG_GPIO_28_MODE GLB_REG_GPIO_28_MODE
+#define GLB_REG_GPIO_28_MODE_POS (30U)
+#define GLB_REG_GPIO_28_MODE_LEN (2U)
+#define GLB_REG_GPIO_28_MODE_MSK (((1U << GLB_REG_GPIO_28_MODE_LEN) - 1) << GLB_REG_GPIO_28_MODE_POS)
+#define GLB_REG_GPIO_28_MODE_UMSK (~(((1U << GLB_REG_GPIO_28_MODE_LEN) - 1) << GLB_REG_GPIO_28_MODE_POS))
+
+/* 0x938 : gpio_cfg29 */
+#define GLB_GPIO_CFG29_OFFSET (0x938)
+#define GLB_REG_GPIO_29_IE GLB_REG_GPIO_29_IE
+#define GLB_REG_GPIO_29_IE_POS (0U)
+#define GLB_REG_GPIO_29_IE_LEN (1U)
+#define GLB_REG_GPIO_29_IE_MSK (((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS)
+#define GLB_REG_GPIO_29_IE_UMSK (~(((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS))
+#define GLB_REG_GPIO_29_SMT GLB_REG_GPIO_29_SMT
+#define GLB_REG_GPIO_29_SMT_POS (1U)
+#define GLB_REG_GPIO_29_SMT_LEN (1U)
+#define GLB_REG_GPIO_29_SMT_MSK (((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS)
+#define GLB_REG_GPIO_29_SMT_UMSK (~(((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS))
+#define GLB_REG_GPIO_29_DRV GLB_REG_GPIO_29_DRV
+#define GLB_REG_GPIO_29_DRV_POS (2U)
+#define GLB_REG_GPIO_29_DRV_LEN (2U)
+#define GLB_REG_GPIO_29_DRV_MSK (((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS)
+#define GLB_REG_GPIO_29_DRV_UMSK (~(((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS))
+#define GLB_REG_GPIO_29_PU GLB_REG_GPIO_29_PU
+#define GLB_REG_GPIO_29_PU_POS (4U)
+#define GLB_REG_GPIO_29_PU_LEN (1U)
+#define GLB_REG_GPIO_29_PU_MSK (((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS)
+#define GLB_REG_GPIO_29_PU_UMSK (~(((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS))
+#define GLB_REG_GPIO_29_PD GLB_REG_GPIO_29_PD
+#define GLB_REG_GPIO_29_PD_POS (5U)
+#define GLB_REG_GPIO_29_PD_LEN (1U)
+#define GLB_REG_GPIO_29_PD_MSK (((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS)
+#define GLB_REG_GPIO_29_PD_UMSK (~(((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS))
+#define GLB_REG_GPIO_29_OE GLB_REG_GPIO_29_OE
+#define GLB_REG_GPIO_29_OE_POS (6U)
+#define GLB_REG_GPIO_29_OE_LEN (1U)
+#define GLB_REG_GPIO_29_OE_MSK (((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS)
+#define GLB_REG_GPIO_29_OE_UMSK (~(((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS))
+#define GLB_REG_GPIO_29_FUNC_SEL GLB_REG_GPIO_29_FUNC_SEL
+#define GLB_REG_GPIO_29_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_29_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_29_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS)
+#define GLB_REG_GPIO_29_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS))
+#define GLB_REG_GPIO_29_INT_MODE_SET GLB_REG_GPIO_29_INT_MODE_SET
+#define GLB_REG_GPIO_29_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_29_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_29_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_29_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_29_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_29_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_29_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_29_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_29_INT_CLR GLB_REG_GPIO_29_INT_CLR
+#define GLB_REG_GPIO_29_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_29_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_29_INT_CLR_MSK (((1U << GLB_REG_GPIO_29_INT_CLR_LEN) - 1) << GLB_REG_GPIO_29_INT_CLR_POS)
+#define GLB_REG_GPIO_29_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_29_INT_CLR_LEN) - 1) << GLB_REG_GPIO_29_INT_CLR_POS))
+#define GLB_GPIO_29_INT_STAT GLB_GPIO_29_INT_STAT
+#define GLB_GPIO_29_INT_STAT_POS (21U)
+#define GLB_GPIO_29_INT_STAT_LEN (1U)
+#define GLB_GPIO_29_INT_STAT_MSK (((1U << GLB_GPIO_29_INT_STAT_LEN) - 1) << GLB_GPIO_29_INT_STAT_POS)
+#define GLB_GPIO_29_INT_STAT_UMSK (~(((1U << GLB_GPIO_29_INT_STAT_LEN) - 1) << GLB_GPIO_29_INT_STAT_POS))
+#define GLB_REG_GPIO_29_INT_MASK GLB_REG_GPIO_29_INT_MASK
+#define GLB_REG_GPIO_29_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_29_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_29_INT_MASK_MSK (((1U << GLB_REG_GPIO_29_INT_MASK_LEN) - 1) << GLB_REG_GPIO_29_INT_MASK_POS)
+#define GLB_REG_GPIO_29_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_29_INT_MASK_LEN) - 1) << GLB_REG_GPIO_29_INT_MASK_POS))
+#define GLB_REG_GPIO_29_O GLB_REG_GPIO_29_O
+#define GLB_REG_GPIO_29_O_POS (24U)
+#define GLB_REG_GPIO_29_O_LEN (1U)
+#define GLB_REG_GPIO_29_O_MSK (((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS)
+#define GLB_REG_GPIO_29_O_UMSK (~(((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS))
+#define GLB_REG_GPIO_29_SET GLB_REG_GPIO_29_SET
+#define GLB_REG_GPIO_29_SET_POS (25U)
+#define GLB_REG_GPIO_29_SET_LEN (1U)
+#define GLB_REG_GPIO_29_SET_MSK (((1U << GLB_REG_GPIO_29_SET_LEN) - 1) << GLB_REG_GPIO_29_SET_POS)
+#define GLB_REG_GPIO_29_SET_UMSK (~(((1U << GLB_REG_GPIO_29_SET_LEN) - 1) << GLB_REG_GPIO_29_SET_POS))
+#define GLB_REG_GPIO_29_CLR GLB_REG_GPIO_29_CLR
+#define GLB_REG_GPIO_29_CLR_POS (26U)
+#define GLB_REG_GPIO_29_CLR_LEN (1U)
+#define GLB_REG_GPIO_29_CLR_MSK (((1U << GLB_REG_GPIO_29_CLR_LEN) - 1) << GLB_REG_GPIO_29_CLR_POS)
+#define GLB_REG_GPIO_29_CLR_UMSK (~(((1U << GLB_REG_GPIO_29_CLR_LEN) - 1) << GLB_REG_GPIO_29_CLR_POS))
+#define GLB_REG_GPIO_29_I GLB_REG_GPIO_29_I
+#define GLB_REG_GPIO_29_I_POS (28U)
+#define GLB_REG_GPIO_29_I_LEN (1U)
+#define GLB_REG_GPIO_29_I_MSK (((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS)
+#define GLB_REG_GPIO_29_I_UMSK (~(((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS))
+#define GLB_REG_GPIO_29_MODE GLB_REG_GPIO_29_MODE
+#define GLB_REG_GPIO_29_MODE_POS (30U)
+#define GLB_REG_GPIO_29_MODE_LEN (2U)
+#define GLB_REG_GPIO_29_MODE_MSK (((1U << GLB_REG_GPIO_29_MODE_LEN) - 1) << GLB_REG_GPIO_29_MODE_POS)
+#define GLB_REG_GPIO_29_MODE_UMSK (~(((1U << GLB_REG_GPIO_29_MODE_LEN) - 1) << GLB_REG_GPIO_29_MODE_POS))
+
+/* 0x93C : gpio_cfg30 */
+#define GLB_GPIO_CFG30_OFFSET (0x93C)
+#define GLB_REG_GPIO_30_IE GLB_REG_GPIO_30_IE
+#define GLB_REG_GPIO_30_IE_POS (0U)
+#define GLB_REG_GPIO_30_IE_LEN (1U)
+#define GLB_REG_GPIO_30_IE_MSK (((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS)
+#define GLB_REG_GPIO_30_IE_UMSK (~(((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS))
+#define GLB_REG_GPIO_30_SMT GLB_REG_GPIO_30_SMT
+#define GLB_REG_GPIO_30_SMT_POS (1U)
+#define GLB_REG_GPIO_30_SMT_LEN (1U)
+#define GLB_REG_GPIO_30_SMT_MSK (((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS)
+#define GLB_REG_GPIO_30_SMT_UMSK (~(((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS))
+#define GLB_REG_GPIO_30_DRV GLB_REG_GPIO_30_DRV
+#define GLB_REG_GPIO_30_DRV_POS (2U)
+#define GLB_REG_GPIO_30_DRV_LEN (2U)
+#define GLB_REG_GPIO_30_DRV_MSK (((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS)
+#define GLB_REG_GPIO_30_DRV_UMSK (~(((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS))
+#define GLB_REG_GPIO_30_PU GLB_REG_GPIO_30_PU
+#define GLB_REG_GPIO_30_PU_POS (4U)
+#define GLB_REG_GPIO_30_PU_LEN (1U)
+#define GLB_REG_GPIO_30_PU_MSK (((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS)
+#define GLB_REG_GPIO_30_PU_UMSK (~(((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS))
+#define GLB_REG_GPIO_30_PD GLB_REG_GPIO_30_PD
+#define GLB_REG_GPIO_30_PD_POS (5U)
+#define GLB_REG_GPIO_30_PD_LEN (1U)
+#define GLB_REG_GPIO_30_PD_MSK (((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS)
+#define GLB_REG_GPIO_30_PD_UMSK (~(((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS))
+#define GLB_REG_GPIO_30_OE GLB_REG_GPIO_30_OE
+#define GLB_REG_GPIO_30_OE_POS (6U)
+#define GLB_REG_GPIO_30_OE_LEN (1U)
+#define GLB_REG_GPIO_30_OE_MSK (((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS)
+#define GLB_REG_GPIO_30_OE_UMSK (~(((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS))
+#define GLB_REG_GPIO_30_FUNC_SEL GLB_REG_GPIO_30_FUNC_SEL
+#define GLB_REG_GPIO_30_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_30_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_30_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS)
+#define GLB_REG_GPIO_30_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS))
+#define GLB_REG_GPIO_30_INT_MODE_SET GLB_REG_GPIO_30_INT_MODE_SET
+#define GLB_REG_GPIO_30_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_30_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_30_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_30_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_30_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_30_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_30_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_30_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_30_INT_CLR GLB_REG_GPIO_30_INT_CLR
+#define GLB_REG_GPIO_30_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_30_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_30_INT_CLR_MSK (((1U << GLB_REG_GPIO_30_INT_CLR_LEN) - 1) << GLB_REG_GPIO_30_INT_CLR_POS)
+#define GLB_REG_GPIO_30_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_30_INT_CLR_LEN) - 1) << GLB_REG_GPIO_30_INT_CLR_POS))
+#define GLB_GPIO_30_INT_STAT GLB_GPIO_30_INT_STAT
+#define GLB_GPIO_30_INT_STAT_POS (21U)
+#define GLB_GPIO_30_INT_STAT_LEN (1U)
+#define GLB_GPIO_30_INT_STAT_MSK (((1U << GLB_GPIO_30_INT_STAT_LEN) - 1) << GLB_GPIO_30_INT_STAT_POS)
+#define GLB_GPIO_30_INT_STAT_UMSK (~(((1U << GLB_GPIO_30_INT_STAT_LEN) - 1) << GLB_GPIO_30_INT_STAT_POS))
+#define GLB_REG_GPIO_30_INT_MASK GLB_REG_GPIO_30_INT_MASK
+#define GLB_REG_GPIO_30_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_30_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_30_INT_MASK_MSK (((1U << GLB_REG_GPIO_30_INT_MASK_LEN) - 1) << GLB_REG_GPIO_30_INT_MASK_POS)
+#define GLB_REG_GPIO_30_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_30_INT_MASK_LEN) - 1) << GLB_REG_GPIO_30_INT_MASK_POS))
+#define GLB_REG_GPIO_30_O GLB_REG_GPIO_30_O
+#define GLB_REG_GPIO_30_O_POS (24U)
+#define GLB_REG_GPIO_30_O_LEN (1U)
+#define GLB_REG_GPIO_30_O_MSK (((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS)
+#define GLB_REG_GPIO_30_O_UMSK (~(((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS))
+#define GLB_REG_GPIO_30_SET GLB_REG_GPIO_30_SET
+#define GLB_REG_GPIO_30_SET_POS (25U)
+#define GLB_REG_GPIO_30_SET_LEN (1U)
+#define GLB_REG_GPIO_30_SET_MSK (((1U << GLB_REG_GPIO_30_SET_LEN) - 1) << GLB_REG_GPIO_30_SET_POS)
+#define GLB_REG_GPIO_30_SET_UMSK (~(((1U << GLB_REG_GPIO_30_SET_LEN) - 1) << GLB_REG_GPIO_30_SET_POS))
+#define GLB_REG_GPIO_30_CLR GLB_REG_GPIO_30_CLR
+#define GLB_REG_GPIO_30_CLR_POS (26U)
+#define GLB_REG_GPIO_30_CLR_LEN (1U)
+#define GLB_REG_GPIO_30_CLR_MSK (((1U << GLB_REG_GPIO_30_CLR_LEN) - 1) << GLB_REG_GPIO_30_CLR_POS)
+#define GLB_REG_GPIO_30_CLR_UMSK (~(((1U << GLB_REG_GPIO_30_CLR_LEN) - 1) << GLB_REG_GPIO_30_CLR_POS))
+#define GLB_REG_GPIO_30_I GLB_REG_GPIO_30_I
+#define GLB_REG_GPIO_30_I_POS (28U)
+#define GLB_REG_GPIO_30_I_LEN (1U)
+#define GLB_REG_GPIO_30_I_MSK (((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS)
+#define GLB_REG_GPIO_30_I_UMSK (~(((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS))
+#define GLB_REG_GPIO_30_MODE GLB_REG_GPIO_30_MODE
+#define GLB_REG_GPIO_30_MODE_POS (30U)
+#define GLB_REG_GPIO_30_MODE_LEN (2U)
+#define GLB_REG_GPIO_30_MODE_MSK (((1U << GLB_REG_GPIO_30_MODE_LEN) - 1) << GLB_REG_GPIO_30_MODE_POS)
+#define GLB_REG_GPIO_30_MODE_UMSK (~(((1U << GLB_REG_GPIO_30_MODE_LEN) - 1) << GLB_REG_GPIO_30_MODE_POS))
+
+/* 0x940 : gpio_cfg31 */
+#define GLB_GPIO_CFG31_OFFSET (0x940)
+#define GLB_REG_GPIO_31_IE GLB_REG_GPIO_31_IE
+#define GLB_REG_GPIO_31_IE_POS (0U)
+#define GLB_REG_GPIO_31_IE_LEN (1U)
+#define GLB_REG_GPIO_31_IE_MSK (((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS)
+#define GLB_REG_GPIO_31_IE_UMSK (~(((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS))
+#define GLB_REG_GPIO_31_SMT GLB_REG_GPIO_31_SMT
+#define GLB_REG_GPIO_31_SMT_POS (1U)
+#define GLB_REG_GPIO_31_SMT_LEN (1U)
+#define GLB_REG_GPIO_31_SMT_MSK (((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS)
+#define GLB_REG_GPIO_31_SMT_UMSK (~(((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS))
+#define GLB_REG_GPIO_31_DRV GLB_REG_GPIO_31_DRV
+#define GLB_REG_GPIO_31_DRV_POS (2U)
+#define GLB_REG_GPIO_31_DRV_LEN (2U)
+#define GLB_REG_GPIO_31_DRV_MSK (((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS)
+#define GLB_REG_GPIO_31_DRV_UMSK (~(((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS))
+#define GLB_REG_GPIO_31_PU GLB_REG_GPIO_31_PU
+#define GLB_REG_GPIO_31_PU_POS (4U)
+#define GLB_REG_GPIO_31_PU_LEN (1U)
+#define GLB_REG_GPIO_31_PU_MSK (((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS)
+#define GLB_REG_GPIO_31_PU_UMSK (~(((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS))
+#define GLB_REG_GPIO_31_PD GLB_REG_GPIO_31_PD
+#define GLB_REG_GPIO_31_PD_POS (5U)
+#define GLB_REG_GPIO_31_PD_LEN (1U)
+#define GLB_REG_GPIO_31_PD_MSK (((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS)
+#define GLB_REG_GPIO_31_PD_UMSK (~(((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS))
+#define GLB_REG_GPIO_31_OE GLB_REG_GPIO_31_OE
+#define GLB_REG_GPIO_31_OE_POS (6U)
+#define GLB_REG_GPIO_31_OE_LEN (1U)
+#define GLB_REG_GPIO_31_OE_MSK (((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS)
+#define GLB_REG_GPIO_31_OE_UMSK (~(((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS))
+#define GLB_REG_GPIO_31_FUNC_SEL GLB_REG_GPIO_31_FUNC_SEL
+#define GLB_REG_GPIO_31_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_31_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_31_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS)
+#define GLB_REG_GPIO_31_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS))
+#define GLB_REG_GPIO_31_INT_MODE_SET GLB_REG_GPIO_31_INT_MODE_SET
+#define GLB_REG_GPIO_31_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_31_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_31_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_31_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_31_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_31_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_31_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_31_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_31_INT_CLR GLB_REG_GPIO_31_INT_CLR
+#define GLB_REG_GPIO_31_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_31_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_31_INT_CLR_MSK (((1U << GLB_REG_GPIO_31_INT_CLR_LEN) - 1) << GLB_REG_GPIO_31_INT_CLR_POS)
+#define GLB_REG_GPIO_31_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_31_INT_CLR_LEN) - 1) << GLB_REG_GPIO_31_INT_CLR_POS))
+#define GLB_GPIO_31_INT_STAT GLB_GPIO_31_INT_STAT
+#define GLB_GPIO_31_INT_STAT_POS (21U)
+#define GLB_GPIO_31_INT_STAT_LEN (1U)
+#define GLB_GPIO_31_INT_STAT_MSK (((1U << GLB_GPIO_31_INT_STAT_LEN) - 1) << GLB_GPIO_31_INT_STAT_POS)
+#define GLB_GPIO_31_INT_STAT_UMSK (~(((1U << GLB_GPIO_31_INT_STAT_LEN) - 1) << GLB_GPIO_31_INT_STAT_POS))
+#define GLB_REG_GPIO_31_INT_MASK GLB_REG_GPIO_31_INT_MASK
+#define GLB_REG_GPIO_31_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_31_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_31_INT_MASK_MSK (((1U << GLB_REG_GPIO_31_INT_MASK_LEN) - 1) << GLB_REG_GPIO_31_INT_MASK_POS)
+#define GLB_REG_GPIO_31_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_31_INT_MASK_LEN) - 1) << GLB_REG_GPIO_31_INT_MASK_POS))
+#define GLB_REG_GPIO_31_O GLB_REG_GPIO_31_O
+#define GLB_REG_GPIO_31_O_POS (24U)
+#define GLB_REG_GPIO_31_O_LEN (1U)
+#define GLB_REG_GPIO_31_O_MSK (((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS)
+#define GLB_REG_GPIO_31_O_UMSK (~(((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS))
+#define GLB_REG_GPIO_31_SET GLB_REG_GPIO_31_SET
+#define GLB_REG_GPIO_31_SET_POS (25U)
+#define GLB_REG_GPIO_31_SET_LEN (1U)
+#define GLB_REG_GPIO_31_SET_MSK (((1U << GLB_REG_GPIO_31_SET_LEN) - 1) << GLB_REG_GPIO_31_SET_POS)
+#define GLB_REG_GPIO_31_SET_UMSK (~(((1U << GLB_REG_GPIO_31_SET_LEN) - 1) << GLB_REG_GPIO_31_SET_POS))
+#define GLB_REG_GPIO_31_CLR GLB_REG_GPIO_31_CLR
+#define GLB_REG_GPIO_31_CLR_POS (26U)
+#define GLB_REG_GPIO_31_CLR_LEN (1U)
+#define GLB_REG_GPIO_31_CLR_MSK (((1U << GLB_REG_GPIO_31_CLR_LEN) - 1) << GLB_REG_GPIO_31_CLR_POS)
+#define GLB_REG_GPIO_31_CLR_UMSK (~(((1U << GLB_REG_GPIO_31_CLR_LEN) - 1) << GLB_REG_GPIO_31_CLR_POS))
+#define GLB_REG_GPIO_31_I GLB_REG_GPIO_31_I
+#define GLB_REG_GPIO_31_I_POS (28U)
+#define GLB_REG_GPIO_31_I_LEN (1U)
+#define GLB_REG_GPIO_31_I_MSK (((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS)
+#define GLB_REG_GPIO_31_I_UMSK (~(((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS))
+#define GLB_REG_GPIO_31_MODE GLB_REG_GPIO_31_MODE
+#define GLB_REG_GPIO_31_MODE_POS (30U)
+#define GLB_REG_GPIO_31_MODE_LEN (2U)
+#define GLB_REG_GPIO_31_MODE_MSK (((1U << GLB_REG_GPIO_31_MODE_LEN) - 1) << GLB_REG_GPIO_31_MODE_POS)
+#define GLB_REG_GPIO_31_MODE_UMSK (~(((1U << GLB_REG_GPIO_31_MODE_LEN) - 1) << GLB_REG_GPIO_31_MODE_POS))
+
+/* 0x944 : gpio_cfg32 */
+#define GLB_GPIO_CFG32_OFFSET (0x944)
+#define GLB_REG_GPIO_32_IE GLB_REG_GPIO_32_IE
+#define GLB_REG_GPIO_32_IE_POS (0U)
+#define GLB_REG_GPIO_32_IE_LEN (1U)
+#define GLB_REG_GPIO_32_IE_MSK (((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS)
+#define GLB_REG_GPIO_32_IE_UMSK (~(((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS))
+#define GLB_REG_GPIO_32_SMT GLB_REG_GPIO_32_SMT
+#define GLB_REG_GPIO_32_SMT_POS (1U)
+#define GLB_REG_GPIO_32_SMT_LEN (1U)
+#define GLB_REG_GPIO_32_SMT_MSK (((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS)
+#define GLB_REG_GPIO_32_SMT_UMSK (~(((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS))
+#define GLB_REG_GPIO_32_DRV GLB_REG_GPIO_32_DRV
+#define GLB_REG_GPIO_32_DRV_POS (2U)
+#define GLB_REG_GPIO_32_DRV_LEN (2U)
+#define GLB_REG_GPIO_32_DRV_MSK (((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS)
+#define GLB_REG_GPIO_32_DRV_UMSK (~(((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS))
+#define GLB_REG_GPIO_32_PU GLB_REG_GPIO_32_PU
+#define GLB_REG_GPIO_32_PU_POS (4U)
+#define GLB_REG_GPIO_32_PU_LEN (1U)
+#define GLB_REG_GPIO_32_PU_MSK (((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS)
+#define GLB_REG_GPIO_32_PU_UMSK (~(((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS))
+#define GLB_REG_GPIO_32_PD GLB_REG_GPIO_32_PD
+#define GLB_REG_GPIO_32_PD_POS (5U)
+#define GLB_REG_GPIO_32_PD_LEN (1U)
+#define GLB_REG_GPIO_32_PD_MSK (((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS)
+#define GLB_REG_GPIO_32_PD_UMSK (~(((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS))
+#define GLB_REG_GPIO_32_OE GLB_REG_GPIO_32_OE
+#define GLB_REG_GPIO_32_OE_POS (6U)
+#define GLB_REG_GPIO_32_OE_LEN (1U)
+#define GLB_REG_GPIO_32_OE_MSK (((1U << GLB_REG_GPIO_32_OE_LEN) - 1) << GLB_REG_GPIO_32_OE_POS)
+#define GLB_REG_GPIO_32_OE_UMSK (~(((1U << GLB_REG_GPIO_32_OE_LEN) - 1) << GLB_REG_GPIO_32_OE_POS))
+#define GLB_REG_GPIO_32_FUNC_SEL GLB_REG_GPIO_32_FUNC_SEL
+#define GLB_REG_GPIO_32_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_32_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_32_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_32_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_32_FUNC_SEL_POS)
+#define GLB_REG_GPIO_32_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_32_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_32_FUNC_SEL_POS))
+#define GLB_REG_GPIO_32_INT_MODE_SET GLB_REG_GPIO_32_INT_MODE_SET
+#define GLB_REG_GPIO_32_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_32_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_32_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_32_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_32_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_32_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_32_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_32_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_32_INT_CLR GLB_REG_GPIO_32_INT_CLR
+#define GLB_REG_GPIO_32_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_32_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_32_INT_CLR_MSK (((1U << GLB_REG_GPIO_32_INT_CLR_LEN) - 1) << GLB_REG_GPIO_32_INT_CLR_POS)
+#define GLB_REG_GPIO_32_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_32_INT_CLR_LEN) - 1) << GLB_REG_GPIO_32_INT_CLR_POS))
+#define GLB_GPIO_32_INT_STAT GLB_GPIO_32_INT_STAT
+#define GLB_GPIO_32_INT_STAT_POS (21U)
+#define GLB_GPIO_32_INT_STAT_LEN (1U)
+#define GLB_GPIO_32_INT_STAT_MSK (((1U << GLB_GPIO_32_INT_STAT_LEN) - 1) << GLB_GPIO_32_INT_STAT_POS)
+#define GLB_GPIO_32_INT_STAT_UMSK (~(((1U << GLB_GPIO_32_INT_STAT_LEN) - 1) << GLB_GPIO_32_INT_STAT_POS))
+#define GLB_REG_GPIO_32_INT_MASK GLB_REG_GPIO_32_INT_MASK
+#define GLB_REG_GPIO_32_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_32_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_32_INT_MASK_MSK (((1U << GLB_REG_GPIO_32_INT_MASK_LEN) - 1) << GLB_REG_GPIO_32_INT_MASK_POS)
+#define GLB_REG_GPIO_32_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_32_INT_MASK_LEN) - 1) << GLB_REG_GPIO_32_INT_MASK_POS))
+#define GLB_REG_GPIO_32_O GLB_REG_GPIO_32_O
+#define GLB_REG_GPIO_32_O_POS (24U)
+#define GLB_REG_GPIO_32_O_LEN (1U)
+#define GLB_REG_GPIO_32_O_MSK (((1U << GLB_REG_GPIO_32_O_LEN) - 1) << GLB_REG_GPIO_32_O_POS)
+#define GLB_REG_GPIO_32_O_UMSK (~(((1U << GLB_REG_GPIO_32_O_LEN) - 1) << GLB_REG_GPIO_32_O_POS))
+#define GLB_REG_GPIO_32_SET GLB_REG_GPIO_32_SET
+#define GLB_REG_GPIO_32_SET_POS (25U)
+#define GLB_REG_GPIO_32_SET_LEN (1U)
+#define GLB_REG_GPIO_32_SET_MSK (((1U << GLB_REG_GPIO_32_SET_LEN) - 1) << GLB_REG_GPIO_32_SET_POS)
+#define GLB_REG_GPIO_32_SET_UMSK (~(((1U << GLB_REG_GPIO_32_SET_LEN) - 1) << GLB_REG_GPIO_32_SET_POS))
+#define GLB_REG_GPIO_32_CLR GLB_REG_GPIO_32_CLR
+#define GLB_REG_GPIO_32_CLR_POS (26U)
+#define GLB_REG_GPIO_32_CLR_LEN (1U)
+#define GLB_REG_GPIO_32_CLR_MSK (((1U << GLB_REG_GPIO_32_CLR_LEN) - 1) << GLB_REG_GPIO_32_CLR_POS)
+#define GLB_REG_GPIO_32_CLR_UMSK (~(((1U << GLB_REG_GPIO_32_CLR_LEN) - 1) << GLB_REG_GPIO_32_CLR_POS))
+#define GLB_REG_GPIO_32_I GLB_REG_GPIO_32_I
+#define GLB_REG_GPIO_32_I_POS (28U)
+#define GLB_REG_GPIO_32_I_LEN (1U)
+#define GLB_REG_GPIO_32_I_MSK (((1U << GLB_REG_GPIO_32_I_LEN) - 1) << GLB_REG_GPIO_32_I_POS)
+#define GLB_REG_GPIO_32_I_UMSK (~(((1U << GLB_REG_GPIO_32_I_LEN) - 1) << GLB_REG_GPIO_32_I_POS))
+#define GLB_REG_GPIO_32_MODE GLB_REG_GPIO_32_MODE
+#define GLB_REG_GPIO_32_MODE_POS (30U)
+#define GLB_REG_GPIO_32_MODE_LEN (2U)
+#define GLB_REG_GPIO_32_MODE_MSK (((1U << GLB_REG_GPIO_32_MODE_LEN) - 1) << GLB_REG_GPIO_32_MODE_POS)
+#define GLB_REG_GPIO_32_MODE_UMSK (~(((1U << GLB_REG_GPIO_32_MODE_LEN) - 1) << GLB_REG_GPIO_32_MODE_POS))
+
+/* 0x948 : gpio_cfg33 */
+#define GLB_GPIO_CFG33_OFFSET (0x948)
+#define GLB_REG_GPIO_33_IE GLB_REG_GPIO_33_IE
+#define GLB_REG_GPIO_33_IE_POS (0U)
+#define GLB_REG_GPIO_33_IE_LEN (1U)
+#define GLB_REG_GPIO_33_IE_MSK (((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS)
+#define GLB_REG_GPIO_33_IE_UMSK (~(((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS))
+#define GLB_REG_GPIO_33_SMT GLB_REG_GPIO_33_SMT
+#define GLB_REG_GPIO_33_SMT_POS (1U)
+#define GLB_REG_GPIO_33_SMT_LEN (1U)
+#define GLB_REG_GPIO_33_SMT_MSK (((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS)
+#define GLB_REG_GPIO_33_SMT_UMSK (~(((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS))
+#define GLB_REG_GPIO_33_DRV GLB_REG_GPIO_33_DRV
+#define GLB_REG_GPIO_33_DRV_POS (2U)
+#define GLB_REG_GPIO_33_DRV_LEN (2U)
+#define GLB_REG_GPIO_33_DRV_MSK (((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS)
+#define GLB_REG_GPIO_33_DRV_UMSK (~(((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS))
+#define GLB_REG_GPIO_33_PU GLB_REG_GPIO_33_PU
+#define GLB_REG_GPIO_33_PU_POS (4U)
+#define GLB_REG_GPIO_33_PU_LEN (1U)
+#define GLB_REG_GPIO_33_PU_MSK (((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS)
+#define GLB_REG_GPIO_33_PU_UMSK (~(((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS))
+#define GLB_REG_GPIO_33_PD GLB_REG_GPIO_33_PD
+#define GLB_REG_GPIO_33_PD_POS (5U)
+#define GLB_REG_GPIO_33_PD_LEN (1U)
+#define GLB_REG_GPIO_33_PD_MSK (((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS)
+#define GLB_REG_GPIO_33_PD_UMSK (~(((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS))
+#define GLB_REG_GPIO_33_OE GLB_REG_GPIO_33_OE
+#define GLB_REG_GPIO_33_OE_POS (6U)
+#define GLB_REG_GPIO_33_OE_LEN (1U)
+#define GLB_REG_GPIO_33_OE_MSK (((1U << GLB_REG_GPIO_33_OE_LEN) - 1) << GLB_REG_GPIO_33_OE_POS)
+#define GLB_REG_GPIO_33_OE_UMSK (~(((1U << GLB_REG_GPIO_33_OE_LEN) - 1) << GLB_REG_GPIO_33_OE_POS))
+#define GLB_REG_GPIO_33_FUNC_SEL GLB_REG_GPIO_33_FUNC_SEL
+#define GLB_REG_GPIO_33_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_33_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_33_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_33_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_33_FUNC_SEL_POS)
+#define GLB_REG_GPIO_33_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_33_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_33_FUNC_SEL_POS))
+#define GLB_REG_GPIO_33_INT_MODE_SET GLB_REG_GPIO_33_INT_MODE_SET
+#define GLB_REG_GPIO_33_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_33_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_33_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_33_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_33_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_33_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_33_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_33_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_33_INT_CLR GLB_REG_GPIO_33_INT_CLR
+#define GLB_REG_GPIO_33_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_33_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_33_INT_CLR_MSK (((1U << GLB_REG_GPIO_33_INT_CLR_LEN) - 1) << GLB_REG_GPIO_33_INT_CLR_POS)
+#define GLB_REG_GPIO_33_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_33_INT_CLR_LEN) - 1) << GLB_REG_GPIO_33_INT_CLR_POS))
+#define GLB_GPIO_33_INT_STAT GLB_GPIO_33_INT_STAT
+#define GLB_GPIO_33_INT_STAT_POS (21U)
+#define GLB_GPIO_33_INT_STAT_LEN (1U)
+#define GLB_GPIO_33_INT_STAT_MSK (((1U << GLB_GPIO_33_INT_STAT_LEN) - 1) << GLB_GPIO_33_INT_STAT_POS)
+#define GLB_GPIO_33_INT_STAT_UMSK (~(((1U << GLB_GPIO_33_INT_STAT_LEN) - 1) << GLB_GPIO_33_INT_STAT_POS))
+#define GLB_REG_GPIO_33_INT_MASK GLB_REG_GPIO_33_INT_MASK
+#define GLB_REG_GPIO_33_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_33_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_33_INT_MASK_MSK (((1U << GLB_REG_GPIO_33_INT_MASK_LEN) - 1) << GLB_REG_GPIO_33_INT_MASK_POS)
+#define GLB_REG_GPIO_33_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_33_INT_MASK_LEN) - 1) << GLB_REG_GPIO_33_INT_MASK_POS))
+#define GLB_REG_GPIO_33_O GLB_REG_GPIO_33_O
+#define GLB_REG_GPIO_33_O_POS (24U)
+#define GLB_REG_GPIO_33_O_LEN (1U)
+#define GLB_REG_GPIO_33_O_MSK (((1U << GLB_REG_GPIO_33_O_LEN) - 1) << GLB_REG_GPIO_33_O_POS)
+#define GLB_REG_GPIO_33_O_UMSK (~(((1U << GLB_REG_GPIO_33_O_LEN) - 1) << GLB_REG_GPIO_33_O_POS))
+#define GLB_REG_GPIO_33_SET GLB_REG_GPIO_33_SET
+#define GLB_REG_GPIO_33_SET_POS (25U)
+#define GLB_REG_GPIO_33_SET_LEN (1U)
+#define GLB_REG_GPIO_33_SET_MSK (((1U << GLB_REG_GPIO_33_SET_LEN) - 1) << GLB_REG_GPIO_33_SET_POS)
+#define GLB_REG_GPIO_33_SET_UMSK (~(((1U << GLB_REG_GPIO_33_SET_LEN) - 1) << GLB_REG_GPIO_33_SET_POS))
+#define GLB_REG_GPIO_33_CLR GLB_REG_GPIO_33_CLR
+#define GLB_REG_GPIO_33_CLR_POS (26U)
+#define GLB_REG_GPIO_33_CLR_LEN (1U)
+#define GLB_REG_GPIO_33_CLR_MSK (((1U << GLB_REG_GPIO_33_CLR_LEN) - 1) << GLB_REG_GPIO_33_CLR_POS)
+#define GLB_REG_GPIO_33_CLR_UMSK (~(((1U << GLB_REG_GPIO_33_CLR_LEN) - 1) << GLB_REG_GPIO_33_CLR_POS))
+#define GLB_REG_GPIO_33_I GLB_REG_GPIO_33_I
+#define GLB_REG_GPIO_33_I_POS (28U)
+#define GLB_REG_GPIO_33_I_LEN (1U)
+#define GLB_REG_GPIO_33_I_MSK (((1U << GLB_REG_GPIO_33_I_LEN) - 1) << GLB_REG_GPIO_33_I_POS)
+#define GLB_REG_GPIO_33_I_UMSK (~(((1U << GLB_REG_GPIO_33_I_LEN) - 1) << GLB_REG_GPIO_33_I_POS))
+#define GLB_REG_GPIO_33_MODE GLB_REG_GPIO_33_MODE
+#define GLB_REG_GPIO_33_MODE_POS (30U)
+#define GLB_REG_GPIO_33_MODE_LEN (2U)
+#define GLB_REG_GPIO_33_MODE_MSK (((1U << GLB_REG_GPIO_33_MODE_LEN) - 1) << GLB_REG_GPIO_33_MODE_POS)
+#define GLB_REG_GPIO_33_MODE_UMSK (~(((1U << GLB_REG_GPIO_33_MODE_LEN) - 1) << GLB_REG_GPIO_33_MODE_POS))
+
+/* 0x94C : gpio_cfg34 */
+#define GLB_GPIO_CFG34_OFFSET (0x94C)
+#define GLB_REG_GPIO_34_IE GLB_REG_GPIO_34_IE
+#define GLB_REG_GPIO_34_IE_POS (0U)
+#define GLB_REG_GPIO_34_IE_LEN (1U)
+#define GLB_REG_GPIO_34_IE_MSK (((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS)
+#define GLB_REG_GPIO_34_IE_UMSK (~(((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS))
+#define GLB_REG_GPIO_34_SMT GLB_REG_GPIO_34_SMT
+#define GLB_REG_GPIO_34_SMT_POS (1U)
+#define GLB_REG_GPIO_34_SMT_LEN (1U)
+#define GLB_REG_GPIO_34_SMT_MSK (((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS)
+#define GLB_REG_GPIO_34_SMT_UMSK (~(((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS))
+#define GLB_REG_GPIO_34_DRV GLB_REG_GPIO_34_DRV
+#define GLB_REG_GPIO_34_DRV_POS (2U)
+#define GLB_REG_GPIO_34_DRV_LEN (2U)
+#define GLB_REG_GPIO_34_DRV_MSK (((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS)
+#define GLB_REG_GPIO_34_DRV_UMSK (~(((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS))
+#define GLB_REG_GPIO_34_PU GLB_REG_GPIO_34_PU
+#define GLB_REG_GPIO_34_PU_POS (4U)
+#define GLB_REG_GPIO_34_PU_LEN (1U)
+#define GLB_REG_GPIO_34_PU_MSK (((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS)
+#define GLB_REG_GPIO_34_PU_UMSK (~(((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS))
+#define GLB_REG_GPIO_34_PD GLB_REG_GPIO_34_PD
+#define GLB_REG_GPIO_34_PD_POS (5U)
+#define GLB_REG_GPIO_34_PD_LEN (1U)
+#define GLB_REG_GPIO_34_PD_MSK (((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS)
+#define GLB_REG_GPIO_34_PD_UMSK (~(((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS))
+#define GLB_REG_GPIO_34_OE GLB_REG_GPIO_34_OE
+#define GLB_REG_GPIO_34_OE_POS (6U)
+#define GLB_REG_GPIO_34_OE_LEN (1U)
+#define GLB_REG_GPIO_34_OE_MSK (((1U << GLB_REG_GPIO_34_OE_LEN) - 1) << GLB_REG_GPIO_34_OE_POS)
+#define GLB_REG_GPIO_34_OE_UMSK (~(((1U << GLB_REG_GPIO_34_OE_LEN) - 1) << GLB_REG_GPIO_34_OE_POS))
+#define GLB_REG_GPIO_34_FUNC_SEL GLB_REG_GPIO_34_FUNC_SEL
+#define GLB_REG_GPIO_34_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_34_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_34_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_34_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_34_FUNC_SEL_POS)
+#define GLB_REG_GPIO_34_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_34_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_34_FUNC_SEL_POS))
+#define GLB_REG_GPIO_34_INT_MODE_SET GLB_REG_GPIO_34_INT_MODE_SET
+#define GLB_REG_GPIO_34_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_34_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_34_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_34_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_34_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_34_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_34_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_34_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_34_INT_CLR GLB_REG_GPIO_34_INT_CLR
+#define GLB_REG_GPIO_34_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_34_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_34_INT_CLR_MSK (((1U << GLB_REG_GPIO_34_INT_CLR_LEN) - 1) << GLB_REG_GPIO_34_INT_CLR_POS)
+#define GLB_REG_GPIO_34_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_34_INT_CLR_LEN) - 1) << GLB_REG_GPIO_34_INT_CLR_POS))
+#define GLB_GPIO_34_INT_STAT GLB_GPIO_34_INT_STAT
+#define GLB_GPIO_34_INT_STAT_POS (21U)
+#define GLB_GPIO_34_INT_STAT_LEN (1U)
+#define GLB_GPIO_34_INT_STAT_MSK (((1U << GLB_GPIO_34_INT_STAT_LEN) - 1) << GLB_GPIO_34_INT_STAT_POS)
+#define GLB_GPIO_34_INT_STAT_UMSK (~(((1U << GLB_GPIO_34_INT_STAT_LEN) - 1) << GLB_GPIO_34_INT_STAT_POS))
+#define GLB_REG_GPIO_34_INT_MASK GLB_REG_GPIO_34_INT_MASK
+#define GLB_REG_GPIO_34_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_34_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_34_INT_MASK_MSK (((1U << GLB_REG_GPIO_34_INT_MASK_LEN) - 1) << GLB_REG_GPIO_34_INT_MASK_POS)
+#define GLB_REG_GPIO_34_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_34_INT_MASK_LEN) - 1) << GLB_REG_GPIO_34_INT_MASK_POS))
+#define GLB_REG_GPIO_34_O GLB_REG_GPIO_34_O
+#define GLB_REG_GPIO_34_O_POS (24U)
+#define GLB_REG_GPIO_34_O_LEN (1U)
+#define GLB_REG_GPIO_34_O_MSK (((1U << GLB_REG_GPIO_34_O_LEN) - 1) << GLB_REG_GPIO_34_O_POS)
+#define GLB_REG_GPIO_34_O_UMSK (~(((1U << GLB_REG_GPIO_34_O_LEN) - 1) << GLB_REG_GPIO_34_O_POS))
+#define GLB_REG_GPIO_34_SET GLB_REG_GPIO_34_SET
+#define GLB_REG_GPIO_34_SET_POS (25U)
+#define GLB_REG_GPIO_34_SET_LEN (1U)
+#define GLB_REG_GPIO_34_SET_MSK (((1U << GLB_REG_GPIO_34_SET_LEN) - 1) << GLB_REG_GPIO_34_SET_POS)
+#define GLB_REG_GPIO_34_SET_UMSK (~(((1U << GLB_REG_GPIO_34_SET_LEN) - 1) << GLB_REG_GPIO_34_SET_POS))
+#define GLB_REG_GPIO_34_CLR GLB_REG_GPIO_34_CLR
+#define GLB_REG_GPIO_34_CLR_POS (26U)
+#define GLB_REG_GPIO_34_CLR_LEN (1U)
+#define GLB_REG_GPIO_34_CLR_MSK (((1U << GLB_REG_GPIO_34_CLR_LEN) - 1) << GLB_REG_GPIO_34_CLR_POS)
+#define GLB_REG_GPIO_34_CLR_UMSK (~(((1U << GLB_REG_GPIO_34_CLR_LEN) - 1) << GLB_REG_GPIO_34_CLR_POS))
+#define GLB_REG_GPIO_34_I GLB_REG_GPIO_34_I
+#define GLB_REG_GPIO_34_I_POS (28U)
+#define GLB_REG_GPIO_34_I_LEN (1U)
+#define GLB_REG_GPIO_34_I_MSK (((1U << GLB_REG_GPIO_34_I_LEN) - 1) << GLB_REG_GPIO_34_I_POS)
+#define GLB_REG_GPIO_34_I_UMSK (~(((1U << GLB_REG_GPIO_34_I_LEN) - 1) << GLB_REG_GPIO_34_I_POS))
+#define GLB_REG_GPIO_34_MODE GLB_REG_GPIO_34_MODE
+#define GLB_REG_GPIO_34_MODE_POS (30U)
+#define GLB_REG_GPIO_34_MODE_LEN (2U)
+#define GLB_REG_GPIO_34_MODE_MSK (((1U << GLB_REG_GPIO_34_MODE_LEN) - 1) << GLB_REG_GPIO_34_MODE_POS)
+#define GLB_REG_GPIO_34_MODE_UMSK (~(((1U << GLB_REG_GPIO_34_MODE_LEN) - 1) << GLB_REG_GPIO_34_MODE_POS))
+
+/* 0x950 : gpio_cfg35 */
+#define GLB_GPIO_CFG35_OFFSET (0x950)
+#define GLB_REG_GPIO_35_IE GLB_REG_GPIO_35_IE
+#define GLB_REG_GPIO_35_IE_POS (0U)
+#define GLB_REG_GPIO_35_IE_LEN (1U)
+#define GLB_REG_GPIO_35_IE_MSK (((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS)
+#define GLB_REG_GPIO_35_IE_UMSK (~(((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS))
+#define GLB_REG_GPIO_35_SMT GLB_REG_GPIO_35_SMT
+#define GLB_REG_GPIO_35_SMT_POS (1U)
+#define GLB_REG_GPIO_35_SMT_LEN (1U)
+#define GLB_REG_GPIO_35_SMT_MSK (((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS)
+#define GLB_REG_GPIO_35_SMT_UMSK (~(((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS))
+#define GLB_REG_GPIO_35_DRV GLB_REG_GPIO_35_DRV
+#define GLB_REG_GPIO_35_DRV_POS (2U)
+#define GLB_REG_GPIO_35_DRV_LEN (2U)
+#define GLB_REG_GPIO_35_DRV_MSK (((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS)
+#define GLB_REG_GPIO_35_DRV_UMSK (~(((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS))
+#define GLB_REG_GPIO_35_PU GLB_REG_GPIO_35_PU
+#define GLB_REG_GPIO_35_PU_POS (4U)
+#define GLB_REG_GPIO_35_PU_LEN (1U)
+#define GLB_REG_GPIO_35_PU_MSK (((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS)
+#define GLB_REG_GPIO_35_PU_UMSK (~(((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS))
+#define GLB_REG_GPIO_35_PD GLB_REG_GPIO_35_PD
+#define GLB_REG_GPIO_35_PD_POS (5U)
+#define GLB_REG_GPIO_35_PD_LEN (1U)
+#define GLB_REG_GPIO_35_PD_MSK (((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS)
+#define GLB_REG_GPIO_35_PD_UMSK (~(((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS))
+#define GLB_REG_GPIO_35_OE GLB_REG_GPIO_35_OE
+#define GLB_REG_GPIO_35_OE_POS (6U)
+#define GLB_REG_GPIO_35_OE_LEN (1U)
+#define GLB_REG_GPIO_35_OE_MSK (((1U << GLB_REG_GPIO_35_OE_LEN) - 1) << GLB_REG_GPIO_35_OE_POS)
+#define GLB_REG_GPIO_35_OE_UMSK (~(((1U << GLB_REG_GPIO_35_OE_LEN) - 1) << GLB_REG_GPIO_35_OE_POS))
+#define GLB_REG_GPIO_35_FUNC_SEL GLB_REG_GPIO_35_FUNC_SEL
+#define GLB_REG_GPIO_35_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_35_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_35_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_35_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_35_FUNC_SEL_POS)
+#define GLB_REG_GPIO_35_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_35_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_35_FUNC_SEL_POS))
+#define GLB_REG_GPIO_35_INT_MODE_SET GLB_REG_GPIO_35_INT_MODE_SET
+#define GLB_REG_GPIO_35_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_35_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_35_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_35_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_35_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_35_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_35_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_35_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_35_INT_CLR GLB_REG_GPIO_35_INT_CLR
+#define GLB_REG_GPIO_35_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_35_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_35_INT_CLR_MSK (((1U << GLB_REG_GPIO_35_INT_CLR_LEN) - 1) << GLB_REG_GPIO_35_INT_CLR_POS)
+#define GLB_REG_GPIO_35_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_35_INT_CLR_LEN) - 1) << GLB_REG_GPIO_35_INT_CLR_POS))
+#define GLB_GPIO_35_INT_STAT GLB_GPIO_35_INT_STAT
+#define GLB_GPIO_35_INT_STAT_POS (21U)
+#define GLB_GPIO_35_INT_STAT_LEN (1U)
+#define GLB_GPIO_35_INT_STAT_MSK (((1U << GLB_GPIO_35_INT_STAT_LEN) - 1) << GLB_GPIO_35_INT_STAT_POS)
+#define GLB_GPIO_35_INT_STAT_UMSK (~(((1U << GLB_GPIO_35_INT_STAT_LEN) - 1) << GLB_GPIO_35_INT_STAT_POS))
+#define GLB_REG_GPIO_35_INT_MASK GLB_REG_GPIO_35_INT_MASK
+#define GLB_REG_GPIO_35_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_35_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_35_INT_MASK_MSK (((1U << GLB_REG_GPIO_35_INT_MASK_LEN) - 1) << GLB_REG_GPIO_35_INT_MASK_POS)
+#define GLB_REG_GPIO_35_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_35_INT_MASK_LEN) - 1) << GLB_REG_GPIO_35_INT_MASK_POS))
+#define GLB_REG_GPIO_35_O GLB_REG_GPIO_35_O
+#define GLB_REG_GPIO_35_O_POS (24U)
+#define GLB_REG_GPIO_35_O_LEN (1U)
+#define GLB_REG_GPIO_35_O_MSK (((1U << GLB_REG_GPIO_35_O_LEN) - 1) << GLB_REG_GPIO_35_O_POS)
+#define GLB_REG_GPIO_35_O_UMSK (~(((1U << GLB_REG_GPIO_35_O_LEN) - 1) << GLB_REG_GPIO_35_O_POS))
+#define GLB_REG_GPIO_35_SET GLB_REG_GPIO_35_SET
+#define GLB_REG_GPIO_35_SET_POS (25U)
+#define GLB_REG_GPIO_35_SET_LEN (1U)
+#define GLB_REG_GPIO_35_SET_MSK (((1U << GLB_REG_GPIO_35_SET_LEN) - 1) << GLB_REG_GPIO_35_SET_POS)
+#define GLB_REG_GPIO_35_SET_UMSK (~(((1U << GLB_REG_GPIO_35_SET_LEN) - 1) << GLB_REG_GPIO_35_SET_POS))
+#define GLB_REG_GPIO_35_CLR GLB_REG_GPIO_35_CLR
+#define GLB_REG_GPIO_35_CLR_POS (26U)
+#define GLB_REG_GPIO_35_CLR_LEN (1U)
+#define GLB_REG_GPIO_35_CLR_MSK (((1U << GLB_REG_GPIO_35_CLR_LEN) - 1) << GLB_REG_GPIO_35_CLR_POS)
+#define GLB_REG_GPIO_35_CLR_UMSK (~(((1U << GLB_REG_GPIO_35_CLR_LEN) - 1) << GLB_REG_GPIO_35_CLR_POS))
+#define GLB_REG_GPIO_35_I GLB_REG_GPIO_35_I
+#define GLB_REG_GPIO_35_I_POS (28U)
+#define GLB_REG_GPIO_35_I_LEN (1U)
+#define GLB_REG_GPIO_35_I_MSK (((1U << GLB_REG_GPIO_35_I_LEN) - 1) << GLB_REG_GPIO_35_I_POS)
+#define GLB_REG_GPIO_35_I_UMSK (~(((1U << GLB_REG_GPIO_35_I_LEN) - 1) << GLB_REG_GPIO_35_I_POS))
+#define GLB_REG_GPIO_35_MODE GLB_REG_GPIO_35_MODE
+#define GLB_REG_GPIO_35_MODE_POS (30U)
+#define GLB_REG_GPIO_35_MODE_LEN (2U)
+#define GLB_REG_GPIO_35_MODE_MSK (((1U << GLB_REG_GPIO_35_MODE_LEN) - 1) << GLB_REG_GPIO_35_MODE_POS)
+#define GLB_REG_GPIO_35_MODE_UMSK (~(((1U << GLB_REG_GPIO_35_MODE_LEN) - 1) << GLB_REG_GPIO_35_MODE_POS))
+
+/* 0x954 : gpio_cfg36 */
+#define GLB_GPIO_CFG36_OFFSET (0x954)
+#define GLB_REG_GPIO_36_IE GLB_REG_GPIO_36_IE
+#define GLB_REG_GPIO_36_IE_POS (0U)
+#define GLB_REG_GPIO_36_IE_LEN (1U)
+#define GLB_REG_GPIO_36_IE_MSK (((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS)
+#define GLB_REG_GPIO_36_IE_UMSK (~(((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS))
+#define GLB_REG_GPIO_36_SMT GLB_REG_GPIO_36_SMT
+#define GLB_REG_GPIO_36_SMT_POS (1U)
+#define GLB_REG_GPIO_36_SMT_LEN (1U)
+#define GLB_REG_GPIO_36_SMT_MSK (((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS)
+#define GLB_REG_GPIO_36_SMT_UMSK (~(((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS))
+#define GLB_REG_GPIO_36_DRV GLB_REG_GPIO_36_DRV
+#define GLB_REG_GPIO_36_DRV_POS (2U)
+#define GLB_REG_GPIO_36_DRV_LEN (2U)
+#define GLB_REG_GPIO_36_DRV_MSK (((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS)
+#define GLB_REG_GPIO_36_DRV_UMSK (~(((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS))
+#define GLB_REG_GPIO_36_PU GLB_REG_GPIO_36_PU
+#define GLB_REG_GPIO_36_PU_POS (4U)
+#define GLB_REG_GPIO_36_PU_LEN (1U)
+#define GLB_REG_GPIO_36_PU_MSK (((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS)
+#define GLB_REG_GPIO_36_PU_UMSK (~(((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS))
+#define GLB_REG_GPIO_36_PD GLB_REG_GPIO_36_PD
+#define GLB_REG_GPIO_36_PD_POS (5U)
+#define GLB_REG_GPIO_36_PD_LEN (1U)
+#define GLB_REG_GPIO_36_PD_MSK (((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS)
+#define GLB_REG_GPIO_36_PD_UMSK (~(((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS))
+#define GLB_REG_GPIO_36_OE GLB_REG_GPIO_36_OE
+#define GLB_REG_GPIO_36_OE_POS (6U)
+#define GLB_REG_GPIO_36_OE_LEN (1U)
+#define GLB_REG_GPIO_36_OE_MSK (((1U << GLB_REG_GPIO_36_OE_LEN) - 1) << GLB_REG_GPIO_36_OE_POS)
+#define GLB_REG_GPIO_36_OE_UMSK (~(((1U << GLB_REG_GPIO_36_OE_LEN) - 1) << GLB_REG_GPIO_36_OE_POS))
+#define GLB_REG_GPIO_36_FUNC_SEL GLB_REG_GPIO_36_FUNC_SEL
+#define GLB_REG_GPIO_36_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_36_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_36_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_36_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_36_FUNC_SEL_POS)
+#define GLB_REG_GPIO_36_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_36_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_36_FUNC_SEL_POS))
+#define GLB_REG_GPIO_36_INT_MODE_SET GLB_REG_GPIO_36_INT_MODE_SET
+#define GLB_REG_GPIO_36_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_36_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_36_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_36_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_36_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_36_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_36_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_36_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_36_INT_CLR GLB_REG_GPIO_36_INT_CLR
+#define GLB_REG_GPIO_36_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_36_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_36_INT_CLR_MSK (((1U << GLB_REG_GPIO_36_INT_CLR_LEN) - 1) << GLB_REG_GPIO_36_INT_CLR_POS)
+#define GLB_REG_GPIO_36_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_36_INT_CLR_LEN) - 1) << GLB_REG_GPIO_36_INT_CLR_POS))
+#define GLB_GPIO_36_INT_STAT GLB_GPIO_36_INT_STAT
+#define GLB_GPIO_36_INT_STAT_POS (21U)
+#define GLB_GPIO_36_INT_STAT_LEN (1U)
+#define GLB_GPIO_36_INT_STAT_MSK (((1U << GLB_GPIO_36_INT_STAT_LEN) - 1) << GLB_GPIO_36_INT_STAT_POS)
+#define GLB_GPIO_36_INT_STAT_UMSK (~(((1U << GLB_GPIO_36_INT_STAT_LEN) - 1) << GLB_GPIO_36_INT_STAT_POS))
+#define GLB_REG_GPIO_36_INT_MASK GLB_REG_GPIO_36_INT_MASK
+#define GLB_REG_GPIO_36_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_36_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_36_INT_MASK_MSK (((1U << GLB_REG_GPIO_36_INT_MASK_LEN) - 1) << GLB_REG_GPIO_36_INT_MASK_POS)
+#define GLB_REG_GPIO_36_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_36_INT_MASK_LEN) - 1) << GLB_REG_GPIO_36_INT_MASK_POS))
+#define GLB_REG_GPIO_36_O GLB_REG_GPIO_36_O
+#define GLB_REG_GPIO_36_O_POS (24U)
+#define GLB_REG_GPIO_36_O_LEN (1U)
+#define GLB_REG_GPIO_36_O_MSK (((1U << GLB_REG_GPIO_36_O_LEN) - 1) << GLB_REG_GPIO_36_O_POS)
+#define GLB_REG_GPIO_36_O_UMSK (~(((1U << GLB_REG_GPIO_36_O_LEN) - 1) << GLB_REG_GPIO_36_O_POS))
+#define GLB_REG_GPIO_36_SET GLB_REG_GPIO_36_SET
+#define GLB_REG_GPIO_36_SET_POS (25U)
+#define GLB_REG_GPIO_36_SET_LEN (1U)
+#define GLB_REG_GPIO_36_SET_MSK (((1U << GLB_REG_GPIO_36_SET_LEN) - 1) << GLB_REG_GPIO_36_SET_POS)
+#define GLB_REG_GPIO_36_SET_UMSK (~(((1U << GLB_REG_GPIO_36_SET_LEN) - 1) << GLB_REG_GPIO_36_SET_POS))
+#define GLB_REG_GPIO_36_CLR GLB_REG_GPIO_36_CLR
+#define GLB_REG_GPIO_36_CLR_POS (26U)
+#define GLB_REG_GPIO_36_CLR_LEN (1U)
+#define GLB_REG_GPIO_36_CLR_MSK (((1U << GLB_REG_GPIO_36_CLR_LEN) - 1) << GLB_REG_GPIO_36_CLR_POS)
+#define GLB_REG_GPIO_36_CLR_UMSK (~(((1U << GLB_REG_GPIO_36_CLR_LEN) - 1) << GLB_REG_GPIO_36_CLR_POS))
+#define GLB_REG_GPIO_36_I GLB_REG_GPIO_36_I
+#define GLB_REG_GPIO_36_I_POS (28U)
+#define GLB_REG_GPIO_36_I_LEN (1U)
+#define GLB_REG_GPIO_36_I_MSK (((1U << GLB_REG_GPIO_36_I_LEN) - 1) << GLB_REG_GPIO_36_I_POS)
+#define GLB_REG_GPIO_36_I_UMSK (~(((1U << GLB_REG_GPIO_36_I_LEN) - 1) << GLB_REG_GPIO_36_I_POS))
+#define GLB_REG_GPIO_36_MODE GLB_REG_GPIO_36_MODE
+#define GLB_REG_GPIO_36_MODE_POS (30U)
+#define GLB_REG_GPIO_36_MODE_LEN (2U)
+#define GLB_REG_GPIO_36_MODE_MSK (((1U << GLB_REG_GPIO_36_MODE_LEN) - 1) << GLB_REG_GPIO_36_MODE_POS)
+#define GLB_REG_GPIO_36_MODE_UMSK (~(((1U << GLB_REG_GPIO_36_MODE_LEN) - 1) << GLB_REG_GPIO_36_MODE_POS))
+
+/* 0x958 : gpio_cfg37 */
+#define GLB_GPIO_CFG37_OFFSET (0x958)
+#define GLB_REG_GPIO_37_IE GLB_REG_GPIO_37_IE
+#define GLB_REG_GPIO_37_IE_POS (0U)
+#define GLB_REG_GPIO_37_IE_LEN (1U)
+#define GLB_REG_GPIO_37_IE_MSK (((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS)
+#define GLB_REG_GPIO_37_IE_UMSK (~(((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS))
+#define GLB_REG_GPIO_37_SMT GLB_REG_GPIO_37_SMT
+#define GLB_REG_GPIO_37_SMT_POS (1U)
+#define GLB_REG_GPIO_37_SMT_LEN (1U)
+#define GLB_REG_GPIO_37_SMT_MSK (((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS)
+#define GLB_REG_GPIO_37_SMT_UMSK (~(((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS))
+#define GLB_REG_GPIO_37_DRV GLB_REG_GPIO_37_DRV
+#define GLB_REG_GPIO_37_DRV_POS (2U)
+#define GLB_REG_GPIO_37_DRV_LEN (2U)
+#define GLB_REG_GPIO_37_DRV_MSK (((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS)
+#define GLB_REG_GPIO_37_DRV_UMSK (~(((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS))
+#define GLB_REG_GPIO_37_PU GLB_REG_GPIO_37_PU
+#define GLB_REG_GPIO_37_PU_POS (4U)
+#define GLB_REG_GPIO_37_PU_LEN (1U)
+#define GLB_REG_GPIO_37_PU_MSK (((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS)
+#define GLB_REG_GPIO_37_PU_UMSK (~(((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS))
+#define GLB_REG_GPIO_37_PD GLB_REG_GPIO_37_PD
+#define GLB_REG_GPIO_37_PD_POS (5U)
+#define GLB_REG_GPIO_37_PD_LEN (1U)
+#define GLB_REG_GPIO_37_PD_MSK (((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS)
+#define GLB_REG_GPIO_37_PD_UMSK (~(((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS))
+#define GLB_REG_GPIO_37_OE GLB_REG_GPIO_37_OE
+#define GLB_REG_GPIO_37_OE_POS (6U)
+#define GLB_REG_GPIO_37_OE_LEN (1U)
+#define GLB_REG_GPIO_37_OE_MSK (((1U << GLB_REG_GPIO_37_OE_LEN) - 1) << GLB_REG_GPIO_37_OE_POS)
+#define GLB_REG_GPIO_37_OE_UMSK (~(((1U << GLB_REG_GPIO_37_OE_LEN) - 1) << GLB_REG_GPIO_37_OE_POS))
+#define GLB_REG_GPIO_37_FUNC_SEL GLB_REG_GPIO_37_FUNC_SEL
+#define GLB_REG_GPIO_37_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_37_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_37_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_37_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_37_FUNC_SEL_POS)
+#define GLB_REG_GPIO_37_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_37_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_37_FUNC_SEL_POS))
+#define GLB_REG_GPIO_37_INT_MODE_SET GLB_REG_GPIO_37_INT_MODE_SET
+#define GLB_REG_GPIO_37_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_37_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_37_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_37_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_37_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_37_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_37_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_37_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_37_INT_CLR GLB_REG_GPIO_37_INT_CLR
+#define GLB_REG_GPIO_37_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_37_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_37_INT_CLR_MSK (((1U << GLB_REG_GPIO_37_INT_CLR_LEN) - 1) << GLB_REG_GPIO_37_INT_CLR_POS)
+#define GLB_REG_GPIO_37_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_37_INT_CLR_LEN) - 1) << GLB_REG_GPIO_37_INT_CLR_POS))
+#define GLB_GPIO_37_INT_STAT GLB_GPIO_37_INT_STAT
+#define GLB_GPIO_37_INT_STAT_POS (21U)
+#define GLB_GPIO_37_INT_STAT_LEN (1U)
+#define GLB_GPIO_37_INT_STAT_MSK (((1U << GLB_GPIO_37_INT_STAT_LEN) - 1) << GLB_GPIO_37_INT_STAT_POS)
+#define GLB_GPIO_37_INT_STAT_UMSK (~(((1U << GLB_GPIO_37_INT_STAT_LEN) - 1) << GLB_GPIO_37_INT_STAT_POS))
+#define GLB_REG_GPIO_37_INT_MASK GLB_REG_GPIO_37_INT_MASK
+#define GLB_REG_GPIO_37_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_37_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_37_INT_MASK_MSK (((1U << GLB_REG_GPIO_37_INT_MASK_LEN) - 1) << GLB_REG_GPIO_37_INT_MASK_POS)
+#define GLB_REG_GPIO_37_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_37_INT_MASK_LEN) - 1) << GLB_REG_GPIO_37_INT_MASK_POS))
+#define GLB_REG_GPIO_37_O GLB_REG_GPIO_37_O
+#define GLB_REG_GPIO_37_O_POS (24U)
+#define GLB_REG_GPIO_37_O_LEN (1U)
+#define GLB_REG_GPIO_37_O_MSK (((1U << GLB_REG_GPIO_37_O_LEN) - 1) << GLB_REG_GPIO_37_O_POS)
+#define GLB_REG_GPIO_37_O_UMSK (~(((1U << GLB_REG_GPIO_37_O_LEN) - 1) << GLB_REG_GPIO_37_O_POS))
+#define GLB_REG_GPIO_37_SET GLB_REG_GPIO_37_SET
+#define GLB_REG_GPIO_37_SET_POS (25U)
+#define GLB_REG_GPIO_37_SET_LEN (1U)
+#define GLB_REG_GPIO_37_SET_MSK (((1U << GLB_REG_GPIO_37_SET_LEN) - 1) << GLB_REG_GPIO_37_SET_POS)
+#define GLB_REG_GPIO_37_SET_UMSK (~(((1U << GLB_REG_GPIO_37_SET_LEN) - 1) << GLB_REG_GPIO_37_SET_POS))
+#define GLB_REG_GPIO_37_CLR GLB_REG_GPIO_37_CLR
+#define GLB_REG_GPIO_37_CLR_POS (26U)
+#define GLB_REG_GPIO_37_CLR_LEN (1U)
+#define GLB_REG_GPIO_37_CLR_MSK (((1U << GLB_REG_GPIO_37_CLR_LEN) - 1) << GLB_REG_GPIO_37_CLR_POS)
+#define GLB_REG_GPIO_37_CLR_UMSK (~(((1U << GLB_REG_GPIO_37_CLR_LEN) - 1) << GLB_REG_GPIO_37_CLR_POS))
+#define GLB_REG_GPIO_37_I GLB_REG_GPIO_37_I
+#define GLB_REG_GPIO_37_I_POS (28U)
+#define GLB_REG_GPIO_37_I_LEN (1U)
+#define GLB_REG_GPIO_37_I_MSK (((1U << GLB_REG_GPIO_37_I_LEN) - 1) << GLB_REG_GPIO_37_I_POS)
+#define GLB_REG_GPIO_37_I_UMSK (~(((1U << GLB_REG_GPIO_37_I_LEN) - 1) << GLB_REG_GPIO_37_I_POS))
+#define GLB_REG_GPIO_37_MODE GLB_REG_GPIO_37_MODE
+#define GLB_REG_GPIO_37_MODE_POS (30U)
+#define GLB_REG_GPIO_37_MODE_LEN (2U)
+#define GLB_REG_GPIO_37_MODE_MSK (((1U << GLB_REG_GPIO_37_MODE_LEN) - 1) << GLB_REG_GPIO_37_MODE_POS)
+#define GLB_REG_GPIO_37_MODE_UMSK (~(((1U << GLB_REG_GPIO_37_MODE_LEN) - 1) << GLB_REG_GPIO_37_MODE_POS))
+
+/* 0x95C : gpio_cfg38 */
+#define GLB_GPIO_CFG38_OFFSET (0x95C)
+#define GLB_REG_GPIO_38_IE GLB_REG_GPIO_38_IE
+#define GLB_REG_GPIO_38_IE_POS (0U)
+#define GLB_REG_GPIO_38_IE_LEN (1U)
+#define GLB_REG_GPIO_38_IE_MSK (((1U << GLB_REG_GPIO_38_IE_LEN) - 1) << GLB_REG_GPIO_38_IE_POS)
+#define GLB_REG_GPIO_38_IE_UMSK (~(((1U << GLB_REG_GPIO_38_IE_LEN) - 1) << GLB_REG_GPIO_38_IE_POS))
+#define GLB_REG_GPIO_38_SMT GLB_REG_GPIO_38_SMT
+#define GLB_REG_GPIO_38_SMT_POS (1U)
+#define GLB_REG_GPIO_38_SMT_LEN (1U)
+#define GLB_REG_GPIO_38_SMT_MSK (((1U << GLB_REG_GPIO_38_SMT_LEN) - 1) << GLB_REG_GPIO_38_SMT_POS)
+#define GLB_REG_GPIO_38_SMT_UMSK (~(((1U << GLB_REG_GPIO_38_SMT_LEN) - 1) << GLB_REG_GPIO_38_SMT_POS))
+#define GLB_REG_GPIO_38_DRV GLB_REG_GPIO_38_DRV
+#define GLB_REG_GPIO_38_DRV_POS (2U)
+#define GLB_REG_GPIO_38_DRV_LEN (2U)
+#define GLB_REG_GPIO_38_DRV_MSK (((1U << GLB_REG_GPIO_38_DRV_LEN) - 1) << GLB_REG_GPIO_38_DRV_POS)
+#define GLB_REG_GPIO_38_DRV_UMSK (~(((1U << GLB_REG_GPIO_38_DRV_LEN) - 1) << GLB_REG_GPIO_38_DRV_POS))
+#define GLB_REG_GPIO_38_PU GLB_REG_GPIO_38_PU
+#define GLB_REG_GPIO_38_PU_POS (4U)
+#define GLB_REG_GPIO_38_PU_LEN (1U)
+#define GLB_REG_GPIO_38_PU_MSK (((1U << GLB_REG_GPIO_38_PU_LEN) - 1) << GLB_REG_GPIO_38_PU_POS)
+#define GLB_REG_GPIO_38_PU_UMSK (~(((1U << GLB_REG_GPIO_38_PU_LEN) - 1) << GLB_REG_GPIO_38_PU_POS))
+#define GLB_REG_GPIO_38_PD GLB_REG_GPIO_38_PD
+#define GLB_REG_GPIO_38_PD_POS (5U)
+#define GLB_REG_GPIO_38_PD_LEN (1U)
+#define GLB_REG_GPIO_38_PD_MSK (((1U << GLB_REG_GPIO_38_PD_LEN) - 1) << GLB_REG_GPIO_38_PD_POS)
+#define GLB_REG_GPIO_38_PD_UMSK (~(((1U << GLB_REG_GPIO_38_PD_LEN) - 1) << GLB_REG_GPIO_38_PD_POS))
+#define GLB_REG_GPIO_38_OE GLB_REG_GPIO_38_OE
+#define GLB_REG_GPIO_38_OE_POS (6U)
+#define GLB_REG_GPIO_38_OE_LEN (1U)
+#define GLB_REG_GPIO_38_OE_MSK (((1U << GLB_REG_GPIO_38_OE_LEN) - 1) << GLB_REG_GPIO_38_OE_POS)
+#define GLB_REG_GPIO_38_OE_UMSK (~(((1U << GLB_REG_GPIO_38_OE_LEN) - 1) << GLB_REG_GPIO_38_OE_POS))
+#define GLB_REG_GPIO_38_FUNC_SEL GLB_REG_GPIO_38_FUNC_SEL
+#define GLB_REG_GPIO_38_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_38_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_38_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_38_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_38_FUNC_SEL_POS)
+#define GLB_REG_GPIO_38_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_38_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_38_FUNC_SEL_POS))
+#define GLB_REG_GPIO_38_INT_MODE_SET GLB_REG_GPIO_38_INT_MODE_SET
+#define GLB_REG_GPIO_38_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_38_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_38_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_38_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_38_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_38_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_38_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_38_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_38_INT_CLR GLB_REG_GPIO_38_INT_CLR
+#define GLB_REG_GPIO_38_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_38_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_38_INT_CLR_MSK (((1U << GLB_REG_GPIO_38_INT_CLR_LEN) - 1) << GLB_REG_GPIO_38_INT_CLR_POS)
+#define GLB_REG_GPIO_38_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_38_INT_CLR_LEN) - 1) << GLB_REG_GPIO_38_INT_CLR_POS))
+#define GLB_GPIO_38_INT_STAT GLB_GPIO_38_INT_STAT
+#define GLB_GPIO_38_INT_STAT_POS (21U)
+#define GLB_GPIO_38_INT_STAT_LEN (1U)
+#define GLB_GPIO_38_INT_STAT_MSK (((1U << GLB_GPIO_38_INT_STAT_LEN) - 1) << GLB_GPIO_38_INT_STAT_POS)
+#define GLB_GPIO_38_INT_STAT_UMSK (~(((1U << GLB_GPIO_38_INT_STAT_LEN) - 1) << GLB_GPIO_38_INT_STAT_POS))
+#define GLB_REG_GPIO_38_INT_MASK GLB_REG_GPIO_38_INT_MASK
+#define GLB_REG_GPIO_38_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_38_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_38_INT_MASK_MSK (((1U << GLB_REG_GPIO_38_INT_MASK_LEN) - 1) << GLB_REG_GPIO_38_INT_MASK_POS)
+#define GLB_REG_GPIO_38_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_38_INT_MASK_LEN) - 1) << GLB_REG_GPIO_38_INT_MASK_POS))
+#define GLB_REG_GPIO_38_O GLB_REG_GPIO_38_O
+#define GLB_REG_GPIO_38_O_POS (24U)
+#define GLB_REG_GPIO_38_O_LEN (1U)
+#define GLB_REG_GPIO_38_O_MSK (((1U << GLB_REG_GPIO_38_O_LEN) - 1) << GLB_REG_GPIO_38_O_POS)
+#define GLB_REG_GPIO_38_O_UMSK (~(((1U << GLB_REG_GPIO_38_O_LEN) - 1) << GLB_REG_GPIO_38_O_POS))
+#define GLB_REG_GPIO_38_SET GLB_REG_GPIO_38_SET
+#define GLB_REG_GPIO_38_SET_POS (25U)
+#define GLB_REG_GPIO_38_SET_LEN (1U)
+#define GLB_REG_GPIO_38_SET_MSK (((1U << GLB_REG_GPIO_38_SET_LEN) - 1) << GLB_REG_GPIO_38_SET_POS)
+#define GLB_REG_GPIO_38_SET_UMSK (~(((1U << GLB_REG_GPIO_38_SET_LEN) - 1) << GLB_REG_GPIO_38_SET_POS))
+#define GLB_REG_GPIO_38_CLR GLB_REG_GPIO_38_CLR
+#define GLB_REG_GPIO_38_CLR_POS (26U)
+#define GLB_REG_GPIO_38_CLR_LEN (1U)
+#define GLB_REG_GPIO_38_CLR_MSK (((1U << GLB_REG_GPIO_38_CLR_LEN) - 1) << GLB_REG_GPIO_38_CLR_POS)
+#define GLB_REG_GPIO_38_CLR_UMSK (~(((1U << GLB_REG_GPIO_38_CLR_LEN) - 1) << GLB_REG_GPIO_38_CLR_POS))
+#define GLB_REG_GPIO_38_I GLB_REG_GPIO_38_I
+#define GLB_REG_GPIO_38_I_POS (28U)
+#define GLB_REG_GPIO_38_I_LEN (1U)
+#define GLB_REG_GPIO_38_I_MSK (((1U << GLB_REG_GPIO_38_I_LEN) - 1) << GLB_REG_GPIO_38_I_POS)
+#define GLB_REG_GPIO_38_I_UMSK (~(((1U << GLB_REG_GPIO_38_I_LEN) - 1) << GLB_REG_GPIO_38_I_POS))
+#define GLB_REG_GPIO_38_MODE GLB_REG_GPIO_38_MODE
+#define GLB_REG_GPIO_38_MODE_POS (30U)
+#define GLB_REG_GPIO_38_MODE_LEN (2U)
+#define GLB_REG_GPIO_38_MODE_MSK (((1U << GLB_REG_GPIO_38_MODE_LEN) - 1) << GLB_REG_GPIO_38_MODE_POS)
+#define GLB_REG_GPIO_38_MODE_UMSK (~(((1U << GLB_REG_GPIO_38_MODE_LEN) - 1) << GLB_REG_GPIO_38_MODE_POS))
+
+/* 0x960 : gpio_cfg39 */
+#define GLB_GPIO_CFG39_OFFSET (0x960)
+#define GLB_REG_GPIO_39_IE GLB_REG_GPIO_39_IE
+#define GLB_REG_GPIO_39_IE_POS (0U)
+#define GLB_REG_GPIO_39_IE_LEN (1U)
+#define GLB_REG_GPIO_39_IE_MSK (((1U << GLB_REG_GPIO_39_IE_LEN) - 1) << GLB_REG_GPIO_39_IE_POS)
+#define GLB_REG_GPIO_39_IE_UMSK (~(((1U << GLB_REG_GPIO_39_IE_LEN) - 1) << GLB_REG_GPIO_39_IE_POS))
+#define GLB_REG_GPIO_39_SMT GLB_REG_GPIO_39_SMT
+#define GLB_REG_GPIO_39_SMT_POS (1U)
+#define GLB_REG_GPIO_39_SMT_LEN (1U)
+#define GLB_REG_GPIO_39_SMT_MSK (((1U << GLB_REG_GPIO_39_SMT_LEN) - 1) << GLB_REG_GPIO_39_SMT_POS)
+#define GLB_REG_GPIO_39_SMT_UMSK (~(((1U << GLB_REG_GPIO_39_SMT_LEN) - 1) << GLB_REG_GPIO_39_SMT_POS))
+#define GLB_REG_GPIO_39_DRV GLB_REG_GPIO_39_DRV
+#define GLB_REG_GPIO_39_DRV_POS (2U)
+#define GLB_REG_GPIO_39_DRV_LEN (2U)
+#define GLB_REG_GPIO_39_DRV_MSK (((1U << GLB_REG_GPIO_39_DRV_LEN) - 1) << GLB_REG_GPIO_39_DRV_POS)
+#define GLB_REG_GPIO_39_DRV_UMSK (~(((1U << GLB_REG_GPIO_39_DRV_LEN) - 1) << GLB_REG_GPIO_39_DRV_POS))
+#define GLB_REG_GPIO_39_PU GLB_REG_GPIO_39_PU
+#define GLB_REG_GPIO_39_PU_POS (4U)
+#define GLB_REG_GPIO_39_PU_LEN (1U)
+#define GLB_REG_GPIO_39_PU_MSK (((1U << GLB_REG_GPIO_39_PU_LEN) - 1) << GLB_REG_GPIO_39_PU_POS)
+#define GLB_REG_GPIO_39_PU_UMSK (~(((1U << GLB_REG_GPIO_39_PU_LEN) - 1) << GLB_REG_GPIO_39_PU_POS))
+#define GLB_REG_GPIO_39_PD GLB_REG_GPIO_39_PD
+#define GLB_REG_GPIO_39_PD_POS (5U)
+#define GLB_REG_GPIO_39_PD_LEN (1U)
+#define GLB_REG_GPIO_39_PD_MSK (((1U << GLB_REG_GPIO_39_PD_LEN) - 1) << GLB_REG_GPIO_39_PD_POS)
+#define GLB_REG_GPIO_39_PD_UMSK (~(((1U << GLB_REG_GPIO_39_PD_LEN) - 1) << GLB_REG_GPIO_39_PD_POS))
+#define GLB_REG_GPIO_39_OE GLB_REG_GPIO_39_OE
+#define GLB_REG_GPIO_39_OE_POS (6U)
+#define GLB_REG_GPIO_39_OE_LEN (1U)
+#define GLB_REG_GPIO_39_OE_MSK (((1U << GLB_REG_GPIO_39_OE_LEN) - 1) << GLB_REG_GPIO_39_OE_POS)
+#define GLB_REG_GPIO_39_OE_UMSK (~(((1U << GLB_REG_GPIO_39_OE_LEN) - 1) << GLB_REG_GPIO_39_OE_POS))
+#define GLB_REG_GPIO_39_FUNC_SEL GLB_REG_GPIO_39_FUNC_SEL
+#define GLB_REG_GPIO_39_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_39_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_39_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_39_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_39_FUNC_SEL_POS)
+#define GLB_REG_GPIO_39_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_39_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_39_FUNC_SEL_POS))
+#define GLB_REG_GPIO_39_INT_MODE_SET GLB_REG_GPIO_39_INT_MODE_SET
+#define GLB_REG_GPIO_39_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_39_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_39_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_39_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_39_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_39_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_39_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_39_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_39_INT_CLR GLB_REG_GPIO_39_INT_CLR
+#define GLB_REG_GPIO_39_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_39_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_39_INT_CLR_MSK (((1U << GLB_REG_GPIO_39_INT_CLR_LEN) - 1) << GLB_REG_GPIO_39_INT_CLR_POS)
+#define GLB_REG_GPIO_39_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_39_INT_CLR_LEN) - 1) << GLB_REG_GPIO_39_INT_CLR_POS))
+#define GLB_GPIO_39_INT_STAT GLB_GPIO_39_INT_STAT
+#define GLB_GPIO_39_INT_STAT_POS (21U)
+#define GLB_GPIO_39_INT_STAT_LEN (1U)
+#define GLB_GPIO_39_INT_STAT_MSK (((1U << GLB_GPIO_39_INT_STAT_LEN) - 1) << GLB_GPIO_39_INT_STAT_POS)
+#define GLB_GPIO_39_INT_STAT_UMSK (~(((1U << GLB_GPIO_39_INT_STAT_LEN) - 1) << GLB_GPIO_39_INT_STAT_POS))
+#define GLB_REG_GPIO_39_INT_MASK GLB_REG_GPIO_39_INT_MASK
+#define GLB_REG_GPIO_39_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_39_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_39_INT_MASK_MSK (((1U << GLB_REG_GPIO_39_INT_MASK_LEN) - 1) << GLB_REG_GPIO_39_INT_MASK_POS)
+#define GLB_REG_GPIO_39_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_39_INT_MASK_LEN) - 1) << GLB_REG_GPIO_39_INT_MASK_POS))
+#define GLB_REG_GPIO_39_O GLB_REG_GPIO_39_O
+#define GLB_REG_GPIO_39_O_POS (24U)
+#define GLB_REG_GPIO_39_O_LEN (1U)
+#define GLB_REG_GPIO_39_O_MSK (((1U << GLB_REG_GPIO_39_O_LEN) - 1) << GLB_REG_GPIO_39_O_POS)
+#define GLB_REG_GPIO_39_O_UMSK (~(((1U << GLB_REG_GPIO_39_O_LEN) - 1) << GLB_REG_GPIO_39_O_POS))
+#define GLB_REG_GPIO_39_SET GLB_REG_GPIO_39_SET
+#define GLB_REG_GPIO_39_SET_POS (25U)
+#define GLB_REG_GPIO_39_SET_LEN (1U)
+#define GLB_REG_GPIO_39_SET_MSK (((1U << GLB_REG_GPIO_39_SET_LEN) - 1) << GLB_REG_GPIO_39_SET_POS)
+#define GLB_REG_GPIO_39_SET_UMSK (~(((1U << GLB_REG_GPIO_39_SET_LEN) - 1) << GLB_REG_GPIO_39_SET_POS))
+#define GLB_REG_GPIO_39_CLR GLB_REG_GPIO_39_CLR
+#define GLB_REG_GPIO_39_CLR_POS (26U)
+#define GLB_REG_GPIO_39_CLR_LEN (1U)
+#define GLB_REG_GPIO_39_CLR_MSK (((1U << GLB_REG_GPIO_39_CLR_LEN) - 1) << GLB_REG_GPIO_39_CLR_POS)
+#define GLB_REG_GPIO_39_CLR_UMSK (~(((1U << GLB_REG_GPIO_39_CLR_LEN) - 1) << GLB_REG_GPIO_39_CLR_POS))
+#define GLB_REG_GPIO_39_I GLB_REG_GPIO_39_I
+#define GLB_REG_GPIO_39_I_POS (28U)
+#define GLB_REG_GPIO_39_I_LEN (1U)
+#define GLB_REG_GPIO_39_I_MSK (((1U << GLB_REG_GPIO_39_I_LEN) - 1) << GLB_REG_GPIO_39_I_POS)
+#define GLB_REG_GPIO_39_I_UMSK (~(((1U << GLB_REG_GPIO_39_I_LEN) - 1) << GLB_REG_GPIO_39_I_POS))
+#define GLB_REG_GPIO_39_MODE GLB_REG_GPIO_39_MODE
+#define GLB_REG_GPIO_39_MODE_POS (30U)
+#define GLB_REG_GPIO_39_MODE_LEN (2U)
+#define GLB_REG_GPIO_39_MODE_MSK (((1U << GLB_REG_GPIO_39_MODE_LEN) - 1) << GLB_REG_GPIO_39_MODE_POS)
+#define GLB_REG_GPIO_39_MODE_UMSK (~(((1U << GLB_REG_GPIO_39_MODE_LEN) - 1) << GLB_REG_GPIO_39_MODE_POS))
+
+/* 0x964 : gpio_cfg40 */
+#define GLB_GPIO_CFG40_OFFSET (0x964)
+#define GLB_REG_GPIO_40_IE GLB_REG_GPIO_40_IE
+#define GLB_REG_GPIO_40_IE_POS (0U)
+#define GLB_REG_GPIO_40_IE_LEN (1U)
+#define GLB_REG_GPIO_40_IE_MSK (((1U << GLB_REG_GPIO_40_IE_LEN) - 1) << GLB_REG_GPIO_40_IE_POS)
+#define GLB_REG_GPIO_40_IE_UMSK (~(((1U << GLB_REG_GPIO_40_IE_LEN) - 1) << GLB_REG_GPIO_40_IE_POS))
+#define GLB_REG_GPIO_40_SMT GLB_REG_GPIO_40_SMT
+#define GLB_REG_GPIO_40_SMT_POS (1U)
+#define GLB_REG_GPIO_40_SMT_LEN (1U)
+#define GLB_REG_GPIO_40_SMT_MSK (((1U << GLB_REG_GPIO_40_SMT_LEN) - 1) << GLB_REG_GPIO_40_SMT_POS)
+#define GLB_REG_GPIO_40_SMT_UMSK (~(((1U << GLB_REG_GPIO_40_SMT_LEN) - 1) << GLB_REG_GPIO_40_SMT_POS))
+#define GLB_REG_GPIO_40_DRV GLB_REG_GPIO_40_DRV
+#define GLB_REG_GPIO_40_DRV_POS (2U)
+#define GLB_REG_GPIO_40_DRV_LEN (2U)
+#define GLB_REG_GPIO_40_DRV_MSK (((1U << GLB_REG_GPIO_40_DRV_LEN) - 1) << GLB_REG_GPIO_40_DRV_POS)
+#define GLB_REG_GPIO_40_DRV_UMSK (~(((1U << GLB_REG_GPIO_40_DRV_LEN) - 1) << GLB_REG_GPIO_40_DRV_POS))
+#define GLB_REG_GPIO_40_PU GLB_REG_GPIO_40_PU
+#define GLB_REG_GPIO_40_PU_POS (4U)
+#define GLB_REG_GPIO_40_PU_LEN (1U)
+#define GLB_REG_GPIO_40_PU_MSK (((1U << GLB_REG_GPIO_40_PU_LEN) - 1) << GLB_REG_GPIO_40_PU_POS)
+#define GLB_REG_GPIO_40_PU_UMSK (~(((1U << GLB_REG_GPIO_40_PU_LEN) - 1) << GLB_REG_GPIO_40_PU_POS))
+#define GLB_REG_GPIO_40_PD GLB_REG_GPIO_40_PD
+#define GLB_REG_GPIO_40_PD_POS (5U)
+#define GLB_REG_GPIO_40_PD_LEN (1U)
+#define GLB_REG_GPIO_40_PD_MSK (((1U << GLB_REG_GPIO_40_PD_LEN) - 1) << GLB_REG_GPIO_40_PD_POS)
+#define GLB_REG_GPIO_40_PD_UMSK (~(((1U << GLB_REG_GPIO_40_PD_LEN) - 1) << GLB_REG_GPIO_40_PD_POS))
+#define GLB_REG_GPIO_40_OE GLB_REG_GPIO_40_OE
+#define GLB_REG_GPIO_40_OE_POS (6U)
+#define GLB_REG_GPIO_40_OE_LEN (1U)
+#define GLB_REG_GPIO_40_OE_MSK (((1U << GLB_REG_GPIO_40_OE_LEN) - 1) << GLB_REG_GPIO_40_OE_POS)
+#define GLB_REG_GPIO_40_OE_UMSK (~(((1U << GLB_REG_GPIO_40_OE_LEN) - 1) << GLB_REG_GPIO_40_OE_POS))
+#define GLB_REG_GPIO_40_FUNC_SEL GLB_REG_GPIO_40_FUNC_SEL
+#define GLB_REG_GPIO_40_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_40_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_40_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_40_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_40_FUNC_SEL_POS)
+#define GLB_REG_GPIO_40_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_40_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_40_FUNC_SEL_POS))
+#define GLB_REG_GPIO_40_INT_MODE_SET GLB_REG_GPIO_40_INT_MODE_SET
+#define GLB_REG_GPIO_40_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_40_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_40_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_40_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_40_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_40_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_40_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_40_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_40_INT_CLR GLB_REG_GPIO_40_INT_CLR
+#define GLB_REG_GPIO_40_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_40_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_40_INT_CLR_MSK (((1U << GLB_REG_GPIO_40_INT_CLR_LEN) - 1) << GLB_REG_GPIO_40_INT_CLR_POS)
+#define GLB_REG_GPIO_40_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_40_INT_CLR_LEN) - 1) << GLB_REG_GPIO_40_INT_CLR_POS))
+#define GLB_GPIO_40_INT_STAT GLB_GPIO_40_INT_STAT
+#define GLB_GPIO_40_INT_STAT_POS (21U)
+#define GLB_GPIO_40_INT_STAT_LEN (1U)
+#define GLB_GPIO_40_INT_STAT_MSK (((1U << GLB_GPIO_40_INT_STAT_LEN) - 1) << GLB_GPIO_40_INT_STAT_POS)
+#define GLB_GPIO_40_INT_STAT_UMSK (~(((1U << GLB_GPIO_40_INT_STAT_LEN) - 1) << GLB_GPIO_40_INT_STAT_POS))
+#define GLB_REG_GPIO_40_INT_MASK GLB_REG_GPIO_40_INT_MASK
+#define GLB_REG_GPIO_40_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_40_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_40_INT_MASK_MSK (((1U << GLB_REG_GPIO_40_INT_MASK_LEN) - 1) << GLB_REG_GPIO_40_INT_MASK_POS)
+#define GLB_REG_GPIO_40_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_40_INT_MASK_LEN) - 1) << GLB_REG_GPIO_40_INT_MASK_POS))
+#define GLB_REG_GPIO_40_O GLB_REG_GPIO_40_O
+#define GLB_REG_GPIO_40_O_POS (24U)
+#define GLB_REG_GPIO_40_O_LEN (1U)
+#define GLB_REG_GPIO_40_O_MSK (((1U << GLB_REG_GPIO_40_O_LEN) - 1) << GLB_REG_GPIO_40_O_POS)
+#define GLB_REG_GPIO_40_O_UMSK (~(((1U << GLB_REG_GPIO_40_O_LEN) - 1) << GLB_REG_GPIO_40_O_POS))
+#define GLB_REG_GPIO_40_SET GLB_REG_GPIO_40_SET
+#define GLB_REG_GPIO_40_SET_POS (25U)
+#define GLB_REG_GPIO_40_SET_LEN (1U)
+#define GLB_REG_GPIO_40_SET_MSK (((1U << GLB_REG_GPIO_40_SET_LEN) - 1) << GLB_REG_GPIO_40_SET_POS)
+#define GLB_REG_GPIO_40_SET_UMSK (~(((1U << GLB_REG_GPIO_40_SET_LEN) - 1) << GLB_REG_GPIO_40_SET_POS))
+#define GLB_REG_GPIO_40_CLR GLB_REG_GPIO_40_CLR
+#define GLB_REG_GPIO_40_CLR_POS (26U)
+#define GLB_REG_GPIO_40_CLR_LEN (1U)
+#define GLB_REG_GPIO_40_CLR_MSK (((1U << GLB_REG_GPIO_40_CLR_LEN) - 1) << GLB_REG_GPIO_40_CLR_POS)
+#define GLB_REG_GPIO_40_CLR_UMSK (~(((1U << GLB_REG_GPIO_40_CLR_LEN) - 1) << GLB_REG_GPIO_40_CLR_POS))
+#define GLB_REG_GPIO_40_I GLB_REG_GPIO_40_I
+#define GLB_REG_GPIO_40_I_POS (28U)
+#define GLB_REG_GPIO_40_I_LEN (1U)
+#define GLB_REG_GPIO_40_I_MSK (((1U << GLB_REG_GPIO_40_I_LEN) - 1) << GLB_REG_GPIO_40_I_POS)
+#define GLB_REG_GPIO_40_I_UMSK (~(((1U << GLB_REG_GPIO_40_I_LEN) - 1) << GLB_REG_GPIO_40_I_POS))
+#define GLB_REG_GPIO_40_MODE GLB_REG_GPIO_40_MODE
+#define GLB_REG_GPIO_40_MODE_POS (30U)
+#define GLB_REG_GPIO_40_MODE_LEN (2U)
+#define GLB_REG_GPIO_40_MODE_MSK (((1U << GLB_REG_GPIO_40_MODE_LEN) - 1) << GLB_REG_GPIO_40_MODE_POS)
+#define GLB_REG_GPIO_40_MODE_UMSK (~(((1U << GLB_REG_GPIO_40_MODE_LEN) - 1) << GLB_REG_GPIO_40_MODE_POS))
+
+/* 0x968 : gpio_cfg41 */
+#define GLB_GPIO_CFG41_OFFSET (0x968)
+#define GLB_REG_GPIO_41_IE GLB_REG_GPIO_41_IE
+#define GLB_REG_GPIO_41_IE_POS (0U)
+#define GLB_REG_GPIO_41_IE_LEN (1U)
+#define GLB_REG_GPIO_41_IE_MSK (((1U << GLB_REG_GPIO_41_IE_LEN) - 1) << GLB_REG_GPIO_41_IE_POS)
+#define GLB_REG_GPIO_41_IE_UMSK (~(((1U << GLB_REG_GPIO_41_IE_LEN) - 1) << GLB_REG_GPIO_41_IE_POS))
+#define GLB_REG_GPIO_41_SMT GLB_REG_GPIO_41_SMT
+#define GLB_REG_GPIO_41_SMT_POS (1U)
+#define GLB_REG_GPIO_41_SMT_LEN (1U)
+#define GLB_REG_GPIO_41_SMT_MSK (((1U << GLB_REG_GPIO_41_SMT_LEN) - 1) << GLB_REG_GPIO_41_SMT_POS)
+#define GLB_REG_GPIO_41_SMT_UMSK (~(((1U << GLB_REG_GPIO_41_SMT_LEN) - 1) << GLB_REG_GPIO_41_SMT_POS))
+#define GLB_REG_GPIO_41_DRV GLB_REG_GPIO_41_DRV
+#define GLB_REG_GPIO_41_DRV_POS (2U)
+#define GLB_REG_GPIO_41_DRV_LEN (2U)
+#define GLB_REG_GPIO_41_DRV_MSK (((1U << GLB_REG_GPIO_41_DRV_LEN) - 1) << GLB_REG_GPIO_41_DRV_POS)
+#define GLB_REG_GPIO_41_DRV_UMSK (~(((1U << GLB_REG_GPIO_41_DRV_LEN) - 1) << GLB_REG_GPIO_41_DRV_POS))
+#define GLB_REG_GPIO_41_PU GLB_REG_GPIO_41_PU
+#define GLB_REG_GPIO_41_PU_POS (4U)
+#define GLB_REG_GPIO_41_PU_LEN (1U)
+#define GLB_REG_GPIO_41_PU_MSK (((1U << GLB_REG_GPIO_41_PU_LEN) - 1) << GLB_REG_GPIO_41_PU_POS)
+#define GLB_REG_GPIO_41_PU_UMSK (~(((1U << GLB_REG_GPIO_41_PU_LEN) - 1) << GLB_REG_GPIO_41_PU_POS))
+#define GLB_REG_GPIO_41_PD GLB_REG_GPIO_41_PD
+#define GLB_REG_GPIO_41_PD_POS (5U)
+#define GLB_REG_GPIO_41_PD_LEN (1U)
+#define GLB_REG_GPIO_41_PD_MSK (((1U << GLB_REG_GPIO_41_PD_LEN) - 1) << GLB_REG_GPIO_41_PD_POS)
+#define GLB_REG_GPIO_41_PD_UMSK (~(((1U << GLB_REG_GPIO_41_PD_LEN) - 1) << GLB_REG_GPIO_41_PD_POS))
+#define GLB_REG_GPIO_41_OE GLB_REG_GPIO_41_OE
+#define GLB_REG_GPIO_41_OE_POS (6U)
+#define GLB_REG_GPIO_41_OE_LEN (1U)
+#define GLB_REG_GPIO_41_OE_MSK (((1U << GLB_REG_GPIO_41_OE_LEN) - 1) << GLB_REG_GPIO_41_OE_POS)
+#define GLB_REG_GPIO_41_OE_UMSK (~(((1U << GLB_REG_GPIO_41_OE_LEN) - 1) << GLB_REG_GPIO_41_OE_POS))
+#define GLB_REG_GPIO_41_FUNC_SEL GLB_REG_GPIO_41_FUNC_SEL
+#define GLB_REG_GPIO_41_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_41_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_41_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_41_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_41_FUNC_SEL_POS)
+#define GLB_REG_GPIO_41_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_41_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_41_FUNC_SEL_POS))
+#define GLB_REG_GPIO_41_INT_MODE_SET GLB_REG_GPIO_41_INT_MODE_SET
+#define GLB_REG_GPIO_41_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_41_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_41_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_41_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_41_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_41_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_41_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_41_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_41_INT_CLR GLB_REG_GPIO_41_INT_CLR
+#define GLB_REG_GPIO_41_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_41_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_41_INT_CLR_MSK (((1U << GLB_REG_GPIO_41_INT_CLR_LEN) - 1) << GLB_REG_GPIO_41_INT_CLR_POS)
+#define GLB_REG_GPIO_41_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_41_INT_CLR_LEN) - 1) << GLB_REG_GPIO_41_INT_CLR_POS))
+#define GLB_GPIO_41_INT_STAT GLB_GPIO_41_INT_STAT
+#define GLB_GPIO_41_INT_STAT_POS (21U)
+#define GLB_GPIO_41_INT_STAT_LEN (1U)
+#define GLB_GPIO_41_INT_STAT_MSK (((1U << GLB_GPIO_41_INT_STAT_LEN) - 1) << GLB_GPIO_41_INT_STAT_POS)
+#define GLB_GPIO_41_INT_STAT_UMSK (~(((1U << GLB_GPIO_41_INT_STAT_LEN) - 1) << GLB_GPIO_41_INT_STAT_POS))
+#define GLB_REG_GPIO_41_INT_MASK GLB_REG_GPIO_41_INT_MASK
+#define GLB_REG_GPIO_41_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_41_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_41_INT_MASK_MSK (((1U << GLB_REG_GPIO_41_INT_MASK_LEN) - 1) << GLB_REG_GPIO_41_INT_MASK_POS)
+#define GLB_REG_GPIO_41_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_41_INT_MASK_LEN) - 1) << GLB_REG_GPIO_41_INT_MASK_POS))
+#define GLB_REG_GPIO_41_O GLB_REG_GPIO_41_O
+#define GLB_REG_GPIO_41_O_POS (24U)
+#define GLB_REG_GPIO_41_O_LEN (1U)
+#define GLB_REG_GPIO_41_O_MSK (((1U << GLB_REG_GPIO_41_O_LEN) - 1) << GLB_REG_GPIO_41_O_POS)
+#define GLB_REG_GPIO_41_O_UMSK (~(((1U << GLB_REG_GPIO_41_O_LEN) - 1) << GLB_REG_GPIO_41_O_POS))
+#define GLB_REG_GPIO_41_SET GLB_REG_GPIO_41_SET
+#define GLB_REG_GPIO_41_SET_POS (25U)
+#define GLB_REG_GPIO_41_SET_LEN (1U)
+#define GLB_REG_GPIO_41_SET_MSK (((1U << GLB_REG_GPIO_41_SET_LEN) - 1) << GLB_REG_GPIO_41_SET_POS)
+#define GLB_REG_GPIO_41_SET_UMSK (~(((1U << GLB_REG_GPIO_41_SET_LEN) - 1) << GLB_REG_GPIO_41_SET_POS))
+#define GLB_REG_GPIO_41_CLR GLB_REG_GPIO_41_CLR
+#define GLB_REG_GPIO_41_CLR_POS (26U)
+#define GLB_REG_GPIO_41_CLR_LEN (1U)
+#define GLB_REG_GPIO_41_CLR_MSK (((1U << GLB_REG_GPIO_41_CLR_LEN) - 1) << GLB_REG_GPIO_41_CLR_POS)
+#define GLB_REG_GPIO_41_CLR_UMSK (~(((1U << GLB_REG_GPIO_41_CLR_LEN) - 1) << GLB_REG_GPIO_41_CLR_POS))
+#define GLB_REG_GPIO_41_I GLB_REG_GPIO_41_I
+#define GLB_REG_GPIO_41_I_POS (28U)
+#define GLB_REG_GPIO_41_I_LEN (1U)
+#define GLB_REG_GPIO_41_I_MSK (((1U << GLB_REG_GPIO_41_I_LEN) - 1) << GLB_REG_GPIO_41_I_POS)
+#define GLB_REG_GPIO_41_I_UMSK (~(((1U << GLB_REG_GPIO_41_I_LEN) - 1) << GLB_REG_GPIO_41_I_POS))
+#define GLB_REG_GPIO_41_MODE GLB_REG_GPIO_41_MODE
+#define GLB_REG_GPIO_41_MODE_POS (30U)
+#define GLB_REG_GPIO_41_MODE_LEN (2U)
+#define GLB_REG_GPIO_41_MODE_MSK (((1U << GLB_REG_GPIO_41_MODE_LEN) - 1) << GLB_REG_GPIO_41_MODE_POS)
+#define GLB_REG_GPIO_41_MODE_UMSK (~(((1U << GLB_REG_GPIO_41_MODE_LEN) - 1) << GLB_REG_GPIO_41_MODE_POS))
+
+/* 0x96C : gpio_cfg42 */
+#define GLB_GPIO_CFG42_OFFSET (0x96C)
+#define GLB_REG_GPIO_42_IE GLB_REG_GPIO_42_IE
+#define GLB_REG_GPIO_42_IE_POS (0U)
+#define GLB_REG_GPIO_42_IE_LEN (1U)
+#define GLB_REG_GPIO_42_IE_MSK (((1U << GLB_REG_GPIO_42_IE_LEN) - 1) << GLB_REG_GPIO_42_IE_POS)
+#define GLB_REG_GPIO_42_IE_UMSK (~(((1U << GLB_REG_GPIO_42_IE_LEN) - 1) << GLB_REG_GPIO_42_IE_POS))
+#define GLB_REG_GPIO_42_SMT GLB_REG_GPIO_42_SMT
+#define GLB_REG_GPIO_42_SMT_POS (1U)
+#define GLB_REG_GPIO_42_SMT_LEN (1U)
+#define GLB_REG_GPIO_42_SMT_MSK (((1U << GLB_REG_GPIO_42_SMT_LEN) - 1) << GLB_REG_GPIO_42_SMT_POS)
+#define GLB_REG_GPIO_42_SMT_UMSK (~(((1U << GLB_REG_GPIO_42_SMT_LEN) - 1) << GLB_REG_GPIO_42_SMT_POS))
+#define GLB_REG_GPIO_42_DRV GLB_REG_GPIO_42_DRV
+#define GLB_REG_GPIO_42_DRV_POS (2U)
+#define GLB_REG_GPIO_42_DRV_LEN (2U)
+#define GLB_REG_GPIO_42_DRV_MSK (((1U << GLB_REG_GPIO_42_DRV_LEN) - 1) << GLB_REG_GPIO_42_DRV_POS)
+#define GLB_REG_GPIO_42_DRV_UMSK (~(((1U << GLB_REG_GPIO_42_DRV_LEN) - 1) << GLB_REG_GPIO_42_DRV_POS))
+#define GLB_REG_GPIO_42_PU GLB_REG_GPIO_42_PU
+#define GLB_REG_GPIO_42_PU_POS (4U)
+#define GLB_REG_GPIO_42_PU_LEN (1U)
+#define GLB_REG_GPIO_42_PU_MSK (((1U << GLB_REG_GPIO_42_PU_LEN) - 1) << GLB_REG_GPIO_42_PU_POS)
+#define GLB_REG_GPIO_42_PU_UMSK (~(((1U << GLB_REG_GPIO_42_PU_LEN) - 1) << GLB_REG_GPIO_42_PU_POS))
+#define GLB_REG_GPIO_42_PD GLB_REG_GPIO_42_PD
+#define GLB_REG_GPIO_42_PD_POS (5U)
+#define GLB_REG_GPIO_42_PD_LEN (1U)
+#define GLB_REG_GPIO_42_PD_MSK (((1U << GLB_REG_GPIO_42_PD_LEN) - 1) << GLB_REG_GPIO_42_PD_POS)
+#define GLB_REG_GPIO_42_PD_UMSK (~(((1U << GLB_REG_GPIO_42_PD_LEN) - 1) << GLB_REG_GPIO_42_PD_POS))
+#define GLB_REG_GPIO_42_OE GLB_REG_GPIO_42_OE
+#define GLB_REG_GPIO_42_OE_POS (6U)
+#define GLB_REG_GPIO_42_OE_LEN (1U)
+#define GLB_REG_GPIO_42_OE_MSK (((1U << GLB_REG_GPIO_42_OE_LEN) - 1) << GLB_REG_GPIO_42_OE_POS)
+#define GLB_REG_GPIO_42_OE_UMSK (~(((1U << GLB_REG_GPIO_42_OE_LEN) - 1) << GLB_REG_GPIO_42_OE_POS))
+#define GLB_REG_GPIO_42_FUNC_SEL GLB_REG_GPIO_42_FUNC_SEL
+#define GLB_REG_GPIO_42_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_42_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_42_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_42_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_42_FUNC_SEL_POS)
+#define GLB_REG_GPIO_42_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_42_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_42_FUNC_SEL_POS))
+#define GLB_REG_GPIO_42_INT_MODE_SET GLB_REG_GPIO_42_INT_MODE_SET
+#define GLB_REG_GPIO_42_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_42_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_42_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_42_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_42_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_42_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_42_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_42_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_42_INT_CLR GLB_REG_GPIO_42_INT_CLR
+#define GLB_REG_GPIO_42_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_42_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_42_INT_CLR_MSK (((1U << GLB_REG_GPIO_42_INT_CLR_LEN) - 1) << GLB_REG_GPIO_42_INT_CLR_POS)
+#define GLB_REG_GPIO_42_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_42_INT_CLR_LEN) - 1) << GLB_REG_GPIO_42_INT_CLR_POS))
+#define GLB_GPIO_42_INT_STAT GLB_GPIO_42_INT_STAT
+#define GLB_GPIO_42_INT_STAT_POS (21U)
+#define GLB_GPIO_42_INT_STAT_LEN (1U)
+#define GLB_GPIO_42_INT_STAT_MSK (((1U << GLB_GPIO_42_INT_STAT_LEN) - 1) << GLB_GPIO_42_INT_STAT_POS)
+#define GLB_GPIO_42_INT_STAT_UMSK (~(((1U << GLB_GPIO_42_INT_STAT_LEN) - 1) << GLB_GPIO_42_INT_STAT_POS))
+#define GLB_REG_GPIO_42_INT_MASK GLB_REG_GPIO_42_INT_MASK
+#define GLB_REG_GPIO_42_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_42_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_42_INT_MASK_MSK (((1U << GLB_REG_GPIO_42_INT_MASK_LEN) - 1) << GLB_REG_GPIO_42_INT_MASK_POS)
+#define GLB_REG_GPIO_42_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_42_INT_MASK_LEN) - 1) << GLB_REG_GPIO_42_INT_MASK_POS))
+#define GLB_REG_GPIO_42_O GLB_REG_GPIO_42_O
+#define GLB_REG_GPIO_42_O_POS (24U)
+#define GLB_REG_GPIO_42_O_LEN (1U)
+#define GLB_REG_GPIO_42_O_MSK (((1U << GLB_REG_GPIO_42_O_LEN) - 1) << GLB_REG_GPIO_42_O_POS)
+#define GLB_REG_GPIO_42_O_UMSK (~(((1U << GLB_REG_GPIO_42_O_LEN) - 1) << GLB_REG_GPIO_42_O_POS))
+#define GLB_REG_GPIO_42_SET GLB_REG_GPIO_42_SET
+#define GLB_REG_GPIO_42_SET_POS (25U)
+#define GLB_REG_GPIO_42_SET_LEN (1U)
+#define GLB_REG_GPIO_42_SET_MSK (((1U << GLB_REG_GPIO_42_SET_LEN) - 1) << GLB_REG_GPIO_42_SET_POS)
+#define GLB_REG_GPIO_42_SET_UMSK (~(((1U << GLB_REG_GPIO_42_SET_LEN) - 1) << GLB_REG_GPIO_42_SET_POS))
+#define GLB_REG_GPIO_42_CLR GLB_REG_GPIO_42_CLR
+#define GLB_REG_GPIO_42_CLR_POS (26U)
+#define GLB_REG_GPIO_42_CLR_LEN (1U)
+#define GLB_REG_GPIO_42_CLR_MSK (((1U << GLB_REG_GPIO_42_CLR_LEN) - 1) << GLB_REG_GPIO_42_CLR_POS)
+#define GLB_REG_GPIO_42_CLR_UMSK (~(((1U << GLB_REG_GPIO_42_CLR_LEN) - 1) << GLB_REG_GPIO_42_CLR_POS))
+#define GLB_REG_GPIO_42_I GLB_REG_GPIO_42_I
+#define GLB_REG_GPIO_42_I_POS (28U)
+#define GLB_REG_GPIO_42_I_LEN (1U)
+#define GLB_REG_GPIO_42_I_MSK (((1U << GLB_REG_GPIO_42_I_LEN) - 1) << GLB_REG_GPIO_42_I_POS)
+#define GLB_REG_GPIO_42_I_UMSK (~(((1U << GLB_REG_GPIO_42_I_LEN) - 1) << GLB_REG_GPIO_42_I_POS))
+#define GLB_REG_GPIO_42_MODE GLB_REG_GPIO_42_MODE
+#define GLB_REG_GPIO_42_MODE_POS (30U)
+#define GLB_REG_GPIO_42_MODE_LEN (2U)
+#define GLB_REG_GPIO_42_MODE_MSK (((1U << GLB_REG_GPIO_42_MODE_LEN) - 1) << GLB_REG_GPIO_42_MODE_POS)
+#define GLB_REG_GPIO_42_MODE_UMSK (~(((1U << GLB_REG_GPIO_42_MODE_LEN) - 1) << GLB_REG_GPIO_42_MODE_POS))
+
+/* 0x970 : gpio_cfg43 */
+#define GLB_GPIO_CFG43_OFFSET (0x970)
+#define GLB_REG_GPIO_43_IE GLB_REG_GPIO_43_IE
+#define GLB_REG_GPIO_43_IE_POS (0U)
+#define GLB_REG_GPIO_43_IE_LEN (1U)
+#define GLB_REG_GPIO_43_IE_MSK (((1U << GLB_REG_GPIO_43_IE_LEN) - 1) << GLB_REG_GPIO_43_IE_POS)
+#define GLB_REG_GPIO_43_IE_UMSK (~(((1U << GLB_REG_GPIO_43_IE_LEN) - 1) << GLB_REG_GPIO_43_IE_POS))
+#define GLB_REG_GPIO_43_SMT GLB_REG_GPIO_43_SMT
+#define GLB_REG_GPIO_43_SMT_POS (1U)
+#define GLB_REG_GPIO_43_SMT_LEN (1U)
+#define GLB_REG_GPIO_43_SMT_MSK (((1U << GLB_REG_GPIO_43_SMT_LEN) - 1) << GLB_REG_GPIO_43_SMT_POS)
+#define GLB_REG_GPIO_43_SMT_UMSK (~(((1U << GLB_REG_GPIO_43_SMT_LEN) - 1) << GLB_REG_GPIO_43_SMT_POS))
+#define GLB_REG_GPIO_43_DRV GLB_REG_GPIO_43_DRV
+#define GLB_REG_GPIO_43_DRV_POS (2U)
+#define GLB_REG_GPIO_43_DRV_LEN (2U)
+#define GLB_REG_GPIO_43_DRV_MSK (((1U << GLB_REG_GPIO_43_DRV_LEN) - 1) << GLB_REG_GPIO_43_DRV_POS)
+#define GLB_REG_GPIO_43_DRV_UMSK (~(((1U << GLB_REG_GPIO_43_DRV_LEN) - 1) << GLB_REG_GPIO_43_DRV_POS))
+#define GLB_REG_GPIO_43_PU GLB_REG_GPIO_43_PU
+#define GLB_REG_GPIO_43_PU_POS (4U)
+#define GLB_REG_GPIO_43_PU_LEN (1U)
+#define GLB_REG_GPIO_43_PU_MSK (((1U << GLB_REG_GPIO_43_PU_LEN) - 1) << GLB_REG_GPIO_43_PU_POS)
+#define GLB_REG_GPIO_43_PU_UMSK (~(((1U << GLB_REG_GPIO_43_PU_LEN) - 1) << GLB_REG_GPIO_43_PU_POS))
+#define GLB_REG_GPIO_43_PD GLB_REG_GPIO_43_PD
+#define GLB_REG_GPIO_43_PD_POS (5U)
+#define GLB_REG_GPIO_43_PD_LEN (1U)
+#define GLB_REG_GPIO_43_PD_MSK (((1U << GLB_REG_GPIO_43_PD_LEN) - 1) << GLB_REG_GPIO_43_PD_POS)
+#define GLB_REG_GPIO_43_PD_UMSK (~(((1U << GLB_REG_GPIO_43_PD_LEN) - 1) << GLB_REG_GPIO_43_PD_POS))
+#define GLB_REG_GPIO_43_OE GLB_REG_GPIO_43_OE
+#define GLB_REG_GPIO_43_OE_POS (6U)
+#define GLB_REG_GPIO_43_OE_LEN (1U)
+#define GLB_REG_GPIO_43_OE_MSK (((1U << GLB_REG_GPIO_43_OE_LEN) - 1) << GLB_REG_GPIO_43_OE_POS)
+#define GLB_REG_GPIO_43_OE_UMSK (~(((1U << GLB_REG_GPIO_43_OE_LEN) - 1) << GLB_REG_GPIO_43_OE_POS))
+#define GLB_REG_GPIO_43_FUNC_SEL GLB_REG_GPIO_43_FUNC_SEL
+#define GLB_REG_GPIO_43_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_43_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_43_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_43_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_43_FUNC_SEL_POS)
+#define GLB_REG_GPIO_43_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_43_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_43_FUNC_SEL_POS))
+#define GLB_REG_GPIO_43_INT_MODE_SET GLB_REG_GPIO_43_INT_MODE_SET
+#define GLB_REG_GPIO_43_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_43_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_43_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_43_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_43_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_43_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_43_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_43_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_43_INT_CLR GLB_REG_GPIO_43_INT_CLR
+#define GLB_REG_GPIO_43_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_43_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_43_INT_CLR_MSK (((1U << GLB_REG_GPIO_43_INT_CLR_LEN) - 1) << GLB_REG_GPIO_43_INT_CLR_POS)
+#define GLB_REG_GPIO_43_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_43_INT_CLR_LEN) - 1) << GLB_REG_GPIO_43_INT_CLR_POS))
+#define GLB_GPIO_43_INT_STAT GLB_GPIO_43_INT_STAT
+#define GLB_GPIO_43_INT_STAT_POS (21U)
+#define GLB_GPIO_43_INT_STAT_LEN (1U)
+#define GLB_GPIO_43_INT_STAT_MSK (((1U << GLB_GPIO_43_INT_STAT_LEN) - 1) << GLB_GPIO_43_INT_STAT_POS)
+#define GLB_GPIO_43_INT_STAT_UMSK (~(((1U << GLB_GPIO_43_INT_STAT_LEN) - 1) << GLB_GPIO_43_INT_STAT_POS))
+#define GLB_REG_GPIO_43_INT_MASK GLB_REG_GPIO_43_INT_MASK
+#define GLB_REG_GPIO_43_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_43_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_43_INT_MASK_MSK (((1U << GLB_REG_GPIO_43_INT_MASK_LEN) - 1) << GLB_REG_GPIO_43_INT_MASK_POS)
+#define GLB_REG_GPIO_43_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_43_INT_MASK_LEN) - 1) << GLB_REG_GPIO_43_INT_MASK_POS))
+#define GLB_REG_GPIO_43_O GLB_REG_GPIO_43_O
+#define GLB_REG_GPIO_43_O_POS (24U)
+#define GLB_REG_GPIO_43_O_LEN (1U)
+#define GLB_REG_GPIO_43_O_MSK (((1U << GLB_REG_GPIO_43_O_LEN) - 1) << GLB_REG_GPIO_43_O_POS)
+#define GLB_REG_GPIO_43_O_UMSK (~(((1U << GLB_REG_GPIO_43_O_LEN) - 1) << GLB_REG_GPIO_43_O_POS))
+#define GLB_REG_GPIO_43_SET GLB_REG_GPIO_43_SET
+#define GLB_REG_GPIO_43_SET_POS (25U)
+#define GLB_REG_GPIO_43_SET_LEN (1U)
+#define GLB_REG_GPIO_43_SET_MSK (((1U << GLB_REG_GPIO_43_SET_LEN) - 1) << GLB_REG_GPIO_43_SET_POS)
+#define GLB_REG_GPIO_43_SET_UMSK (~(((1U << GLB_REG_GPIO_43_SET_LEN) - 1) << GLB_REG_GPIO_43_SET_POS))
+#define GLB_REG_GPIO_43_CLR GLB_REG_GPIO_43_CLR
+#define GLB_REG_GPIO_43_CLR_POS (26U)
+#define GLB_REG_GPIO_43_CLR_LEN (1U)
+#define GLB_REG_GPIO_43_CLR_MSK (((1U << GLB_REG_GPIO_43_CLR_LEN) - 1) << GLB_REG_GPIO_43_CLR_POS)
+#define GLB_REG_GPIO_43_CLR_UMSK (~(((1U << GLB_REG_GPIO_43_CLR_LEN) - 1) << GLB_REG_GPIO_43_CLR_POS))
+#define GLB_REG_GPIO_43_I GLB_REG_GPIO_43_I
+#define GLB_REG_GPIO_43_I_POS (28U)
+#define GLB_REG_GPIO_43_I_LEN (1U)
+#define GLB_REG_GPIO_43_I_MSK (((1U << GLB_REG_GPIO_43_I_LEN) - 1) << GLB_REG_GPIO_43_I_POS)
+#define GLB_REG_GPIO_43_I_UMSK (~(((1U << GLB_REG_GPIO_43_I_LEN) - 1) << GLB_REG_GPIO_43_I_POS))
+#define GLB_REG_GPIO_43_MODE GLB_REG_GPIO_43_MODE
+#define GLB_REG_GPIO_43_MODE_POS (30U)
+#define GLB_REG_GPIO_43_MODE_LEN (2U)
+#define GLB_REG_GPIO_43_MODE_MSK (((1U << GLB_REG_GPIO_43_MODE_LEN) - 1) << GLB_REG_GPIO_43_MODE_POS)
+#define GLB_REG_GPIO_43_MODE_UMSK (~(((1U << GLB_REG_GPIO_43_MODE_LEN) - 1) << GLB_REG_GPIO_43_MODE_POS))
+
+/* 0x974 : gpio_cfg44 */
+#define GLB_GPIO_CFG44_OFFSET (0x974)
+#define GLB_REG_GPIO_44_IE GLB_REG_GPIO_44_IE
+#define GLB_REG_GPIO_44_IE_POS (0U)
+#define GLB_REG_GPIO_44_IE_LEN (1U)
+#define GLB_REG_GPIO_44_IE_MSK (((1U << GLB_REG_GPIO_44_IE_LEN) - 1) << GLB_REG_GPIO_44_IE_POS)
+#define GLB_REG_GPIO_44_IE_UMSK (~(((1U << GLB_REG_GPIO_44_IE_LEN) - 1) << GLB_REG_GPIO_44_IE_POS))
+#define GLB_REG_GPIO_44_SMT GLB_REG_GPIO_44_SMT
+#define GLB_REG_GPIO_44_SMT_POS (1U)
+#define GLB_REG_GPIO_44_SMT_LEN (1U)
+#define GLB_REG_GPIO_44_SMT_MSK (((1U << GLB_REG_GPIO_44_SMT_LEN) - 1) << GLB_REG_GPIO_44_SMT_POS)
+#define GLB_REG_GPIO_44_SMT_UMSK (~(((1U << GLB_REG_GPIO_44_SMT_LEN) - 1) << GLB_REG_GPIO_44_SMT_POS))
+#define GLB_REG_GPIO_44_DRV GLB_REG_GPIO_44_DRV
+#define GLB_REG_GPIO_44_DRV_POS (2U)
+#define GLB_REG_GPIO_44_DRV_LEN (2U)
+#define GLB_REG_GPIO_44_DRV_MSK (((1U << GLB_REG_GPIO_44_DRV_LEN) - 1) << GLB_REG_GPIO_44_DRV_POS)
+#define GLB_REG_GPIO_44_DRV_UMSK (~(((1U << GLB_REG_GPIO_44_DRV_LEN) - 1) << GLB_REG_GPIO_44_DRV_POS))
+#define GLB_REG_GPIO_44_PU GLB_REG_GPIO_44_PU
+#define GLB_REG_GPIO_44_PU_POS (4U)
+#define GLB_REG_GPIO_44_PU_LEN (1U)
+#define GLB_REG_GPIO_44_PU_MSK (((1U << GLB_REG_GPIO_44_PU_LEN) - 1) << GLB_REG_GPIO_44_PU_POS)
+#define GLB_REG_GPIO_44_PU_UMSK (~(((1U << GLB_REG_GPIO_44_PU_LEN) - 1) << GLB_REG_GPIO_44_PU_POS))
+#define GLB_REG_GPIO_44_PD GLB_REG_GPIO_44_PD
+#define GLB_REG_GPIO_44_PD_POS (5U)
+#define GLB_REG_GPIO_44_PD_LEN (1U)
+#define GLB_REG_GPIO_44_PD_MSK (((1U << GLB_REG_GPIO_44_PD_LEN) - 1) << GLB_REG_GPIO_44_PD_POS)
+#define GLB_REG_GPIO_44_PD_UMSK (~(((1U << GLB_REG_GPIO_44_PD_LEN) - 1) << GLB_REG_GPIO_44_PD_POS))
+#define GLB_REG_GPIO_44_OE GLB_REG_GPIO_44_OE
+#define GLB_REG_GPIO_44_OE_POS (6U)
+#define GLB_REG_GPIO_44_OE_LEN (1U)
+#define GLB_REG_GPIO_44_OE_MSK (((1U << GLB_REG_GPIO_44_OE_LEN) - 1) << GLB_REG_GPIO_44_OE_POS)
+#define GLB_REG_GPIO_44_OE_UMSK (~(((1U << GLB_REG_GPIO_44_OE_LEN) - 1) << GLB_REG_GPIO_44_OE_POS))
+#define GLB_REG_GPIO_44_FUNC_SEL GLB_REG_GPIO_44_FUNC_SEL
+#define GLB_REG_GPIO_44_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_44_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_44_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_44_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_44_FUNC_SEL_POS)
+#define GLB_REG_GPIO_44_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_44_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_44_FUNC_SEL_POS))
+#define GLB_REG_GPIO_44_INT_MODE_SET GLB_REG_GPIO_44_INT_MODE_SET
+#define GLB_REG_GPIO_44_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_44_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_44_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_44_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_44_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_44_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_44_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_44_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_44_INT_CLR GLB_REG_GPIO_44_INT_CLR
+#define GLB_REG_GPIO_44_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_44_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_44_INT_CLR_MSK (((1U << GLB_REG_GPIO_44_INT_CLR_LEN) - 1) << GLB_REG_GPIO_44_INT_CLR_POS)
+#define GLB_REG_GPIO_44_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_44_INT_CLR_LEN) - 1) << GLB_REG_GPIO_44_INT_CLR_POS))
+#define GLB_GPIO_44_INT_STAT GLB_GPIO_44_INT_STAT
+#define GLB_GPIO_44_INT_STAT_POS (21U)
+#define GLB_GPIO_44_INT_STAT_LEN (1U)
+#define GLB_GPIO_44_INT_STAT_MSK (((1U << GLB_GPIO_44_INT_STAT_LEN) - 1) << GLB_GPIO_44_INT_STAT_POS)
+#define GLB_GPIO_44_INT_STAT_UMSK (~(((1U << GLB_GPIO_44_INT_STAT_LEN) - 1) << GLB_GPIO_44_INT_STAT_POS))
+#define GLB_REG_GPIO_44_INT_MASK GLB_REG_GPIO_44_INT_MASK
+#define GLB_REG_GPIO_44_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_44_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_44_INT_MASK_MSK (((1U << GLB_REG_GPIO_44_INT_MASK_LEN) - 1) << GLB_REG_GPIO_44_INT_MASK_POS)
+#define GLB_REG_GPIO_44_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_44_INT_MASK_LEN) - 1) << GLB_REG_GPIO_44_INT_MASK_POS))
+#define GLB_REG_GPIO_44_O GLB_REG_GPIO_44_O
+#define GLB_REG_GPIO_44_O_POS (24U)
+#define GLB_REG_GPIO_44_O_LEN (1U)
+#define GLB_REG_GPIO_44_O_MSK (((1U << GLB_REG_GPIO_44_O_LEN) - 1) << GLB_REG_GPIO_44_O_POS)
+#define GLB_REG_GPIO_44_O_UMSK (~(((1U << GLB_REG_GPIO_44_O_LEN) - 1) << GLB_REG_GPIO_44_O_POS))
+#define GLB_REG_GPIO_44_SET GLB_REG_GPIO_44_SET
+#define GLB_REG_GPIO_44_SET_POS (25U)
+#define GLB_REG_GPIO_44_SET_LEN (1U)
+#define GLB_REG_GPIO_44_SET_MSK (((1U << GLB_REG_GPIO_44_SET_LEN) - 1) << GLB_REG_GPIO_44_SET_POS)
+#define GLB_REG_GPIO_44_SET_UMSK (~(((1U << GLB_REG_GPIO_44_SET_LEN) - 1) << GLB_REG_GPIO_44_SET_POS))
+#define GLB_REG_GPIO_44_CLR GLB_REG_GPIO_44_CLR
+#define GLB_REG_GPIO_44_CLR_POS (26U)
+#define GLB_REG_GPIO_44_CLR_LEN (1U)
+#define GLB_REG_GPIO_44_CLR_MSK (((1U << GLB_REG_GPIO_44_CLR_LEN) - 1) << GLB_REG_GPIO_44_CLR_POS)
+#define GLB_REG_GPIO_44_CLR_UMSK (~(((1U << GLB_REG_GPIO_44_CLR_LEN) - 1) << GLB_REG_GPIO_44_CLR_POS))
+#define GLB_REG_GPIO_44_I GLB_REG_GPIO_44_I
+#define GLB_REG_GPIO_44_I_POS (28U)
+#define GLB_REG_GPIO_44_I_LEN (1U)
+#define GLB_REG_GPIO_44_I_MSK (((1U << GLB_REG_GPIO_44_I_LEN) - 1) << GLB_REG_GPIO_44_I_POS)
+#define GLB_REG_GPIO_44_I_UMSK (~(((1U << GLB_REG_GPIO_44_I_LEN) - 1) << GLB_REG_GPIO_44_I_POS))
+#define GLB_REG_GPIO_44_MODE GLB_REG_GPIO_44_MODE
+#define GLB_REG_GPIO_44_MODE_POS (30U)
+#define GLB_REG_GPIO_44_MODE_LEN (2U)
+#define GLB_REG_GPIO_44_MODE_MSK (((1U << GLB_REG_GPIO_44_MODE_LEN) - 1) << GLB_REG_GPIO_44_MODE_POS)
+#define GLB_REG_GPIO_44_MODE_UMSK (~(((1U << GLB_REG_GPIO_44_MODE_LEN) - 1) << GLB_REG_GPIO_44_MODE_POS))
+
+/* 0x978 : gpio_cfg45 */
+#define GLB_GPIO_CFG45_OFFSET (0x978)
+#define GLB_REG_GPIO_45_IE GLB_REG_GPIO_45_IE
+#define GLB_REG_GPIO_45_IE_POS (0U)
+#define GLB_REG_GPIO_45_IE_LEN (1U)
+#define GLB_REG_GPIO_45_IE_MSK (((1U << GLB_REG_GPIO_45_IE_LEN) - 1) << GLB_REG_GPIO_45_IE_POS)
+#define GLB_REG_GPIO_45_IE_UMSK (~(((1U << GLB_REG_GPIO_45_IE_LEN) - 1) << GLB_REG_GPIO_45_IE_POS))
+#define GLB_REG_GPIO_45_SMT GLB_REG_GPIO_45_SMT
+#define GLB_REG_GPIO_45_SMT_POS (1U)
+#define GLB_REG_GPIO_45_SMT_LEN (1U)
+#define GLB_REG_GPIO_45_SMT_MSK (((1U << GLB_REG_GPIO_45_SMT_LEN) - 1) << GLB_REG_GPIO_45_SMT_POS)
+#define GLB_REG_GPIO_45_SMT_UMSK (~(((1U << GLB_REG_GPIO_45_SMT_LEN) - 1) << GLB_REG_GPIO_45_SMT_POS))
+#define GLB_REG_GPIO_45_DRV GLB_REG_GPIO_45_DRV
+#define GLB_REG_GPIO_45_DRV_POS (2U)
+#define GLB_REG_GPIO_45_DRV_LEN (2U)
+#define GLB_REG_GPIO_45_DRV_MSK (((1U << GLB_REG_GPIO_45_DRV_LEN) - 1) << GLB_REG_GPIO_45_DRV_POS)
+#define GLB_REG_GPIO_45_DRV_UMSK (~(((1U << GLB_REG_GPIO_45_DRV_LEN) - 1) << GLB_REG_GPIO_45_DRV_POS))
+#define GLB_REG_GPIO_45_PU GLB_REG_GPIO_45_PU
+#define GLB_REG_GPIO_45_PU_POS (4U)
+#define GLB_REG_GPIO_45_PU_LEN (1U)
+#define GLB_REG_GPIO_45_PU_MSK (((1U << GLB_REG_GPIO_45_PU_LEN) - 1) << GLB_REG_GPIO_45_PU_POS)
+#define GLB_REG_GPIO_45_PU_UMSK (~(((1U << GLB_REG_GPIO_45_PU_LEN) - 1) << GLB_REG_GPIO_45_PU_POS))
+#define GLB_REG_GPIO_45_PD GLB_REG_GPIO_45_PD
+#define GLB_REG_GPIO_45_PD_POS (5U)
+#define GLB_REG_GPIO_45_PD_LEN (1U)
+#define GLB_REG_GPIO_45_PD_MSK (((1U << GLB_REG_GPIO_45_PD_LEN) - 1) << GLB_REG_GPIO_45_PD_POS)
+#define GLB_REG_GPIO_45_PD_UMSK (~(((1U << GLB_REG_GPIO_45_PD_LEN) - 1) << GLB_REG_GPIO_45_PD_POS))
+#define GLB_REG_GPIO_45_OE GLB_REG_GPIO_45_OE
+#define GLB_REG_GPIO_45_OE_POS (6U)
+#define GLB_REG_GPIO_45_OE_LEN (1U)
+#define GLB_REG_GPIO_45_OE_MSK (((1U << GLB_REG_GPIO_45_OE_LEN) - 1) << GLB_REG_GPIO_45_OE_POS)
+#define GLB_REG_GPIO_45_OE_UMSK (~(((1U << GLB_REG_GPIO_45_OE_LEN) - 1) << GLB_REG_GPIO_45_OE_POS))
+#define GLB_REG_GPIO_45_FUNC_SEL GLB_REG_GPIO_45_FUNC_SEL
+#define GLB_REG_GPIO_45_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_45_FUNC_SEL_LEN (5U)
+#define GLB_REG_GPIO_45_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_45_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_45_FUNC_SEL_POS)
+#define GLB_REG_GPIO_45_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_45_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_45_FUNC_SEL_POS))
+#define GLB_REG_GPIO_45_INT_MODE_SET GLB_REG_GPIO_45_INT_MODE_SET
+#define GLB_REG_GPIO_45_INT_MODE_SET_POS (16U)
+#define GLB_REG_GPIO_45_INT_MODE_SET_LEN (4U)
+#define GLB_REG_GPIO_45_INT_MODE_SET_MSK (((1U << GLB_REG_GPIO_45_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_45_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_45_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_45_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_45_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_45_INT_CLR GLB_REG_GPIO_45_INT_CLR
+#define GLB_REG_GPIO_45_INT_CLR_POS (20U)
+#define GLB_REG_GPIO_45_INT_CLR_LEN (1U)
+#define GLB_REG_GPIO_45_INT_CLR_MSK (((1U << GLB_REG_GPIO_45_INT_CLR_LEN) - 1) << GLB_REG_GPIO_45_INT_CLR_POS)
+#define GLB_REG_GPIO_45_INT_CLR_UMSK (~(((1U << GLB_REG_GPIO_45_INT_CLR_LEN) - 1) << GLB_REG_GPIO_45_INT_CLR_POS))
+#define GLB_GPIO_45_INT_STAT GLB_GPIO_45_INT_STAT
+#define GLB_GPIO_45_INT_STAT_POS (21U)
+#define GLB_GPIO_45_INT_STAT_LEN (1U)
+#define GLB_GPIO_45_INT_STAT_MSK (((1U << GLB_GPIO_45_INT_STAT_LEN) - 1) << GLB_GPIO_45_INT_STAT_POS)
+#define GLB_GPIO_45_INT_STAT_UMSK (~(((1U << GLB_GPIO_45_INT_STAT_LEN) - 1) << GLB_GPIO_45_INT_STAT_POS))
+#define GLB_REG_GPIO_45_INT_MASK GLB_REG_GPIO_45_INT_MASK
+#define GLB_REG_GPIO_45_INT_MASK_POS (22U)
+#define GLB_REG_GPIO_45_INT_MASK_LEN (1U)
+#define GLB_REG_GPIO_45_INT_MASK_MSK (((1U << GLB_REG_GPIO_45_INT_MASK_LEN) - 1) << GLB_REG_GPIO_45_INT_MASK_POS)
+#define GLB_REG_GPIO_45_INT_MASK_UMSK (~(((1U << GLB_REG_GPIO_45_INT_MASK_LEN) - 1) << GLB_REG_GPIO_45_INT_MASK_POS))
+#define GLB_REG_GPIO_45_O GLB_REG_GPIO_45_O
+#define GLB_REG_GPIO_45_O_POS (24U)
+#define GLB_REG_GPIO_45_O_LEN (1U)
+#define GLB_REG_GPIO_45_O_MSK (((1U << GLB_REG_GPIO_45_O_LEN) - 1) << GLB_REG_GPIO_45_O_POS)
+#define GLB_REG_GPIO_45_O_UMSK (~(((1U << GLB_REG_GPIO_45_O_LEN) - 1) << GLB_REG_GPIO_45_O_POS))
+#define GLB_REG_GPIO_45_SET GLB_REG_GPIO_45_SET
+#define GLB_REG_GPIO_45_SET_POS (25U)
+#define GLB_REG_GPIO_45_SET_LEN (1U)
+#define GLB_REG_GPIO_45_SET_MSK (((1U << GLB_REG_GPIO_45_SET_LEN) - 1) << GLB_REG_GPIO_45_SET_POS)
+#define GLB_REG_GPIO_45_SET_UMSK (~(((1U << GLB_REG_GPIO_45_SET_LEN) - 1) << GLB_REG_GPIO_45_SET_POS))
+#define GLB_REG_GPIO_45_CLR GLB_REG_GPIO_45_CLR
+#define GLB_REG_GPIO_45_CLR_POS (26U)
+#define GLB_REG_GPIO_45_CLR_LEN (1U)
+#define GLB_REG_GPIO_45_CLR_MSK (((1U << GLB_REG_GPIO_45_CLR_LEN) - 1) << GLB_REG_GPIO_45_CLR_POS)
+#define GLB_REG_GPIO_45_CLR_UMSK (~(((1U << GLB_REG_GPIO_45_CLR_LEN) - 1) << GLB_REG_GPIO_45_CLR_POS))
+#define GLB_REG_GPIO_45_I GLB_REG_GPIO_45_I
+#define GLB_REG_GPIO_45_I_POS (28U)
+#define GLB_REG_GPIO_45_I_LEN (1U)
+#define GLB_REG_GPIO_45_I_MSK (((1U << GLB_REG_GPIO_45_I_LEN) - 1) << GLB_REG_GPIO_45_I_POS)
+#define GLB_REG_GPIO_45_I_UMSK (~(((1U << GLB_REG_GPIO_45_I_LEN) - 1) << GLB_REG_GPIO_45_I_POS))
+#define GLB_REG_GPIO_45_MODE GLB_REG_GPIO_45_MODE
+#define GLB_REG_GPIO_45_MODE_POS (30U)
+#define GLB_REG_GPIO_45_MODE_LEN (2U)
+#define GLB_REG_GPIO_45_MODE_MSK (((1U << GLB_REG_GPIO_45_MODE_LEN) - 1) << GLB_REG_GPIO_45_MODE_POS)
+#define GLB_REG_GPIO_45_MODE_UMSK (~(((1U << GLB_REG_GPIO_45_MODE_LEN) - 1) << GLB_REG_GPIO_45_MODE_POS))
+
+/* 0x97C : gpio_cfg46 */
+#define GLB_GPIO_CFG46_OFFSET (0x97C)
+#define GLB_REG_GPIO_46_IE GLB_REG_GPIO_46_IE
+#define GLB_REG_GPIO_46_IE_POS (0U)
+#define GLB_REG_GPIO_46_IE_LEN (1U)
+#define GLB_REG_GPIO_46_IE_MSK (((1U << GLB_REG_GPIO_46_IE_LEN) - 1) << GLB_REG_GPIO_46_IE_POS)
+#define GLB_REG_GPIO_46_IE_UMSK (~(((1U << GLB_REG_GPIO_46_IE_LEN) - 1) << GLB_REG_GPIO_46_IE_POS))
+#define GLB_REG_GPIO_46_SMT GLB_REG_GPIO_46_SMT
+#define GLB_REG_GPIO_46_SMT_POS (1U)
+#define GLB_REG_GPIO_46_SMT_LEN (1U)
+#define GLB_REG_GPIO_46_SMT_MSK (((1U << GLB_REG_GPIO_46_SMT_LEN) - 1) << GLB_REG_GPIO_46_SMT_POS)
+#define GLB_REG_GPIO_46_SMT_UMSK (~(((1U << GLB_REG_GPIO_46_SMT_LEN) - 1) << GLB_REG_GPIO_46_SMT_POS))
+#define GLB_REG_GPIO_46_DRV GLB_REG_GPIO_46_DRV
+#define GLB_REG_GPIO_46_DRV_POS (2U)
+#define GLB_REG_GPIO_46_DRV_LEN (2U)
+#define GLB_REG_GPIO_46_DRV_MSK (((1U << GLB_REG_GPIO_46_DRV_LEN) - 1) << GLB_REG_GPIO_46_DRV_POS)
+#define GLB_REG_GPIO_46_DRV_UMSK (~(((1U << GLB_REG_GPIO_46_DRV_LEN) - 1) << GLB_REG_GPIO_46_DRV_POS))
+#define GLB_REG_GPIO_46_PU GLB_REG_GPIO_46_PU
+#define GLB_REG_GPIO_46_PU_POS (4U)
+#define GLB_REG_GPIO_46_PU_LEN (1U)
+#define GLB_REG_GPIO_46_PU_MSK (((1U << GLB_REG_GPIO_46_PU_LEN) - 1) << GLB_REG_GPIO_46_PU_POS)
+#define GLB_REG_GPIO_46_PU_UMSK (~(((1U << GLB_REG_GPIO_46_PU_LEN) - 1) << GLB_REG_GPIO_46_PU_POS))
+#define GLB_REG_GPIO_46_PD GLB_REG_GPIO_46_PD
+#define GLB_REG_GPIO_46_PD_POS (5U)
+#define GLB_REG_GPIO_46_PD_LEN (1U)
+#define GLB_REG_GPIO_46_PD_MSK (((1U << GLB_REG_GPIO_46_PD_LEN) - 1) << GLB_REG_GPIO_46_PD_POS)
+#define GLB_REG_GPIO_46_PD_UMSK (~(((1U << GLB_REG_GPIO_46_PD_LEN) - 1) << GLB_REG_GPIO_46_PD_POS))
+
+/* 0x980 : gpio_cfg47 */
+#define GLB_GPIO_CFG47_OFFSET (0x980)
+#define GLB_REG_GPIO_47_IE GLB_REG_GPIO_47_IE
+#define GLB_REG_GPIO_47_IE_POS (0U)
+#define GLB_REG_GPIO_47_IE_LEN (1U)
+#define GLB_REG_GPIO_47_IE_MSK (((1U << GLB_REG_GPIO_47_IE_LEN) - 1) << GLB_REG_GPIO_47_IE_POS)
+#define GLB_REG_GPIO_47_IE_UMSK (~(((1U << GLB_REG_GPIO_47_IE_LEN) - 1) << GLB_REG_GPIO_47_IE_POS))
+#define GLB_REG_GPIO_47_SMT GLB_REG_GPIO_47_SMT
+#define GLB_REG_GPIO_47_SMT_POS (1U)
+#define GLB_REG_GPIO_47_SMT_LEN (1U)
+#define GLB_REG_GPIO_47_SMT_MSK (((1U << GLB_REG_GPIO_47_SMT_LEN) - 1) << GLB_REG_GPIO_47_SMT_POS)
+#define GLB_REG_GPIO_47_SMT_UMSK (~(((1U << GLB_REG_GPIO_47_SMT_LEN) - 1) << GLB_REG_GPIO_47_SMT_POS))
+#define GLB_REG_GPIO_47_DRV GLB_REG_GPIO_47_DRV
+#define GLB_REG_GPIO_47_DRV_POS (2U)
+#define GLB_REG_GPIO_47_DRV_LEN (2U)
+#define GLB_REG_GPIO_47_DRV_MSK (((1U << GLB_REG_GPIO_47_DRV_LEN) - 1) << GLB_REG_GPIO_47_DRV_POS)
+#define GLB_REG_GPIO_47_DRV_UMSK (~(((1U << GLB_REG_GPIO_47_DRV_LEN) - 1) << GLB_REG_GPIO_47_DRV_POS))
+#define GLB_REG_GPIO_47_PU GLB_REG_GPIO_47_PU
+#define GLB_REG_GPIO_47_PU_POS (4U)
+#define GLB_REG_GPIO_47_PU_LEN (1U)
+#define GLB_REG_GPIO_47_PU_MSK (((1U << GLB_REG_GPIO_47_PU_LEN) - 1) << GLB_REG_GPIO_47_PU_POS)
+#define GLB_REG_GPIO_47_PU_UMSK (~(((1U << GLB_REG_GPIO_47_PU_LEN) - 1) << GLB_REG_GPIO_47_PU_POS))
+#define GLB_REG_GPIO_47_PD GLB_REG_GPIO_47_PD
+#define GLB_REG_GPIO_47_PD_POS (5U)
+#define GLB_REG_GPIO_47_PD_LEN (1U)
+#define GLB_REG_GPIO_47_PD_MSK (((1U << GLB_REG_GPIO_47_PD_LEN) - 1) << GLB_REG_GPIO_47_PD_POS)
+#define GLB_REG_GPIO_47_PD_UMSK (~(((1U << GLB_REG_GPIO_47_PD_LEN) - 1) << GLB_REG_GPIO_47_PD_POS))
+
+/* 0x984 : gpio_cfg48 */
+#define GLB_GPIO_CFG48_OFFSET (0x984)
+#define GLB_REG_GPIO_48_IE GLB_REG_GPIO_48_IE
+#define GLB_REG_GPIO_48_IE_POS (0U)
+#define GLB_REG_GPIO_48_IE_LEN (1U)
+#define GLB_REG_GPIO_48_IE_MSK (((1U << GLB_REG_GPIO_48_IE_LEN) - 1) << GLB_REG_GPIO_48_IE_POS)
+#define GLB_REG_GPIO_48_IE_UMSK (~(((1U << GLB_REG_GPIO_48_IE_LEN) - 1) << GLB_REG_GPIO_48_IE_POS))
+#define GLB_REG_GPIO_48_SMT GLB_REG_GPIO_48_SMT
+#define GLB_REG_GPIO_48_SMT_POS (1U)
+#define GLB_REG_GPIO_48_SMT_LEN (1U)
+#define GLB_REG_GPIO_48_SMT_MSK (((1U << GLB_REG_GPIO_48_SMT_LEN) - 1) << GLB_REG_GPIO_48_SMT_POS)
+#define GLB_REG_GPIO_48_SMT_UMSK (~(((1U << GLB_REG_GPIO_48_SMT_LEN) - 1) << GLB_REG_GPIO_48_SMT_POS))
+#define GLB_REG_GPIO_48_DRV GLB_REG_GPIO_48_DRV
+#define GLB_REG_GPIO_48_DRV_POS (2U)
+#define GLB_REG_GPIO_48_DRV_LEN (2U)
+#define GLB_REG_GPIO_48_DRV_MSK (((1U << GLB_REG_GPIO_48_DRV_LEN) - 1) << GLB_REG_GPIO_48_DRV_POS)
+#define GLB_REG_GPIO_48_DRV_UMSK (~(((1U << GLB_REG_GPIO_48_DRV_LEN) - 1) << GLB_REG_GPIO_48_DRV_POS))
+#define GLB_REG_GPIO_48_PU GLB_REG_GPIO_48_PU
+#define GLB_REG_GPIO_48_PU_POS (4U)
+#define GLB_REG_GPIO_48_PU_LEN (1U)
+#define GLB_REG_GPIO_48_PU_MSK (((1U << GLB_REG_GPIO_48_PU_LEN) - 1) << GLB_REG_GPIO_48_PU_POS)
+#define GLB_REG_GPIO_48_PU_UMSK (~(((1U << GLB_REG_GPIO_48_PU_LEN) - 1) << GLB_REG_GPIO_48_PU_POS))
+#define GLB_REG_GPIO_48_PD GLB_REG_GPIO_48_PD
+#define GLB_REG_GPIO_48_PD_POS (5U)
+#define GLB_REG_GPIO_48_PD_LEN (1U)
+#define GLB_REG_GPIO_48_PD_MSK (((1U << GLB_REG_GPIO_48_PD_LEN) - 1) << GLB_REG_GPIO_48_PD_POS)
+#define GLB_REG_GPIO_48_PD_UMSK (~(((1U << GLB_REG_GPIO_48_PD_LEN) - 1) << GLB_REG_GPIO_48_PD_POS))
+
+/* 0x988 : gpio_cfg49 */
+#define GLB_GPIO_CFG49_OFFSET (0x988)
+#define GLB_REG_GPIO_49_IE GLB_REG_GPIO_49_IE
+#define GLB_REG_GPIO_49_IE_POS (0U)
+#define GLB_REG_GPIO_49_IE_LEN (1U)
+#define GLB_REG_GPIO_49_IE_MSK (((1U << GLB_REG_GPIO_49_IE_LEN) - 1) << GLB_REG_GPIO_49_IE_POS)
+#define GLB_REG_GPIO_49_IE_UMSK (~(((1U << GLB_REG_GPIO_49_IE_LEN) - 1) << GLB_REG_GPIO_49_IE_POS))
+#define GLB_REG_GPIO_49_SMT GLB_REG_GPIO_49_SMT
+#define GLB_REG_GPIO_49_SMT_POS (1U)
+#define GLB_REG_GPIO_49_SMT_LEN (1U)
+#define GLB_REG_GPIO_49_SMT_MSK (((1U << GLB_REG_GPIO_49_SMT_LEN) - 1) << GLB_REG_GPIO_49_SMT_POS)
+#define GLB_REG_GPIO_49_SMT_UMSK (~(((1U << GLB_REG_GPIO_49_SMT_LEN) - 1) << GLB_REG_GPIO_49_SMT_POS))
+#define GLB_REG_GPIO_49_DRV GLB_REG_GPIO_49_DRV
+#define GLB_REG_GPIO_49_DRV_POS (2U)
+#define GLB_REG_GPIO_49_DRV_LEN (2U)
+#define GLB_REG_GPIO_49_DRV_MSK (((1U << GLB_REG_GPIO_49_DRV_LEN) - 1) << GLB_REG_GPIO_49_DRV_POS)
+#define GLB_REG_GPIO_49_DRV_UMSK (~(((1U << GLB_REG_GPIO_49_DRV_LEN) - 1) << GLB_REG_GPIO_49_DRV_POS))
+#define GLB_REG_GPIO_49_PU GLB_REG_GPIO_49_PU
+#define GLB_REG_GPIO_49_PU_POS (4U)
+#define GLB_REG_GPIO_49_PU_LEN (1U)
+#define GLB_REG_GPIO_49_PU_MSK (((1U << GLB_REG_GPIO_49_PU_LEN) - 1) << GLB_REG_GPIO_49_PU_POS)
+#define GLB_REG_GPIO_49_PU_UMSK (~(((1U << GLB_REG_GPIO_49_PU_LEN) - 1) << GLB_REG_GPIO_49_PU_POS))
+#define GLB_REG_GPIO_49_PD GLB_REG_GPIO_49_PD
+#define GLB_REG_GPIO_49_PD_POS (5U)
+#define GLB_REG_GPIO_49_PD_LEN (1U)
+#define GLB_REG_GPIO_49_PD_MSK (((1U << GLB_REG_GPIO_49_PD_LEN) - 1) << GLB_REG_GPIO_49_PD_POS)
+#define GLB_REG_GPIO_49_PD_UMSK (~(((1U << GLB_REG_GPIO_49_PD_LEN) - 1) << GLB_REG_GPIO_49_PD_POS))
+
+/* 0x98C : gpio_cfg50 */
+#define GLB_GPIO_CFG50_OFFSET (0x98C)
+#define GLB_REG_GPIO_50_IE GLB_REG_GPIO_50_IE
+#define GLB_REG_GPIO_50_IE_POS (0U)
+#define GLB_REG_GPIO_50_IE_LEN (1U)
+#define GLB_REG_GPIO_50_IE_MSK (((1U << GLB_REG_GPIO_50_IE_LEN) - 1) << GLB_REG_GPIO_50_IE_POS)
+#define GLB_REG_GPIO_50_IE_UMSK (~(((1U << GLB_REG_GPIO_50_IE_LEN) - 1) << GLB_REG_GPIO_50_IE_POS))
+#define GLB_REG_GPIO_50_SMT GLB_REG_GPIO_50_SMT
+#define GLB_REG_GPIO_50_SMT_POS (1U)
+#define GLB_REG_GPIO_50_SMT_LEN (1U)
+#define GLB_REG_GPIO_50_SMT_MSK (((1U << GLB_REG_GPIO_50_SMT_LEN) - 1) << GLB_REG_GPIO_50_SMT_POS)
+#define GLB_REG_GPIO_50_SMT_UMSK (~(((1U << GLB_REG_GPIO_50_SMT_LEN) - 1) << GLB_REG_GPIO_50_SMT_POS))
+#define GLB_REG_GPIO_50_DRV GLB_REG_GPIO_50_DRV
+#define GLB_REG_GPIO_50_DRV_POS (2U)
+#define GLB_REG_GPIO_50_DRV_LEN (2U)
+#define GLB_REG_GPIO_50_DRV_MSK (((1U << GLB_REG_GPIO_50_DRV_LEN) - 1) << GLB_REG_GPIO_50_DRV_POS)
+#define GLB_REG_GPIO_50_DRV_UMSK (~(((1U << GLB_REG_GPIO_50_DRV_LEN) - 1) << GLB_REG_GPIO_50_DRV_POS))
+#define GLB_REG_GPIO_50_PU GLB_REG_GPIO_50_PU
+#define GLB_REG_GPIO_50_PU_POS (4U)
+#define GLB_REG_GPIO_50_PU_LEN (1U)
+#define GLB_REG_GPIO_50_PU_MSK (((1U << GLB_REG_GPIO_50_PU_LEN) - 1) << GLB_REG_GPIO_50_PU_POS)
+#define GLB_REG_GPIO_50_PU_UMSK (~(((1U << GLB_REG_GPIO_50_PU_LEN) - 1) << GLB_REG_GPIO_50_PU_POS))
+#define GLB_REG_GPIO_50_PD GLB_REG_GPIO_50_PD
+#define GLB_REG_GPIO_50_PD_POS (5U)
+#define GLB_REG_GPIO_50_PD_LEN (1U)
+#define GLB_REG_GPIO_50_PD_MSK (((1U << GLB_REG_GPIO_50_PD_LEN) - 1) << GLB_REG_GPIO_50_PD_POS)
+#define GLB_REG_GPIO_50_PD_UMSK (~(((1U << GLB_REG_GPIO_50_PD_LEN) - 1) << GLB_REG_GPIO_50_PD_POS))
+
+/* 0x990 : gpio_cfg51 */
+#define GLB_GPIO_CFG51_OFFSET (0x990)
+#define GLB_REG_GPIO_51_IE GLB_REG_GPIO_51_IE
+#define GLB_REG_GPIO_51_IE_POS (0U)
+#define GLB_REG_GPIO_51_IE_LEN (1U)
+#define GLB_REG_GPIO_51_IE_MSK (((1U << GLB_REG_GPIO_51_IE_LEN) - 1) << GLB_REG_GPIO_51_IE_POS)
+#define GLB_REG_GPIO_51_IE_UMSK (~(((1U << GLB_REG_GPIO_51_IE_LEN) - 1) << GLB_REG_GPIO_51_IE_POS))
+#define GLB_REG_GPIO_51_SMT GLB_REG_GPIO_51_SMT
+#define GLB_REG_GPIO_51_SMT_POS (1U)
+#define GLB_REG_GPIO_51_SMT_LEN (1U)
+#define GLB_REG_GPIO_51_SMT_MSK (((1U << GLB_REG_GPIO_51_SMT_LEN) - 1) << GLB_REG_GPIO_51_SMT_POS)
+#define GLB_REG_GPIO_51_SMT_UMSK (~(((1U << GLB_REG_GPIO_51_SMT_LEN) - 1) << GLB_REG_GPIO_51_SMT_POS))
+#define GLB_REG_GPIO_51_DRV GLB_REG_GPIO_51_DRV
+#define GLB_REG_GPIO_51_DRV_POS (2U)
+#define GLB_REG_GPIO_51_DRV_LEN (2U)
+#define GLB_REG_GPIO_51_DRV_MSK (((1U << GLB_REG_GPIO_51_DRV_LEN) - 1) << GLB_REG_GPIO_51_DRV_POS)
+#define GLB_REG_GPIO_51_DRV_UMSK (~(((1U << GLB_REG_GPIO_51_DRV_LEN) - 1) << GLB_REG_GPIO_51_DRV_POS))
+#define GLB_REG_GPIO_51_PU GLB_REG_GPIO_51_PU
+#define GLB_REG_GPIO_51_PU_POS (4U)
+#define GLB_REG_GPIO_51_PU_LEN (1U)
+#define GLB_REG_GPIO_51_PU_MSK (((1U << GLB_REG_GPIO_51_PU_LEN) - 1) << GLB_REG_GPIO_51_PU_POS)
+#define GLB_REG_GPIO_51_PU_UMSK (~(((1U << GLB_REG_GPIO_51_PU_LEN) - 1) << GLB_REG_GPIO_51_PU_POS))
+#define GLB_REG_GPIO_51_PD GLB_REG_GPIO_51_PD
+#define GLB_REG_GPIO_51_PD_POS (5U)
+#define GLB_REG_GPIO_51_PD_LEN (1U)
+#define GLB_REG_GPIO_51_PD_MSK (((1U << GLB_REG_GPIO_51_PD_LEN) - 1) << GLB_REG_GPIO_51_PD_POS)
+#define GLB_REG_GPIO_51_PD_UMSK (~(((1U << GLB_REG_GPIO_51_PD_LEN) - 1) << GLB_REG_GPIO_51_PD_POS))
+
+/* 0x994 : gpio_cfg52 */
+#define GLB_GPIO_CFG52_OFFSET (0x994)
+#define GLB_REG_GPIO_52_IE GLB_REG_GPIO_52_IE
+#define GLB_REG_GPIO_52_IE_POS (0U)
+#define GLB_REG_GPIO_52_IE_LEN (1U)
+#define GLB_REG_GPIO_52_IE_MSK (((1U << GLB_REG_GPIO_52_IE_LEN) - 1) << GLB_REG_GPIO_52_IE_POS)
+#define GLB_REG_GPIO_52_IE_UMSK (~(((1U << GLB_REG_GPIO_52_IE_LEN) - 1) << GLB_REG_GPIO_52_IE_POS))
+#define GLB_REG_GPIO_52_SMT GLB_REG_GPIO_52_SMT
+#define GLB_REG_GPIO_52_SMT_POS (1U)
+#define GLB_REG_GPIO_52_SMT_LEN (1U)
+#define GLB_REG_GPIO_52_SMT_MSK (((1U << GLB_REG_GPIO_52_SMT_LEN) - 1) << GLB_REG_GPIO_52_SMT_POS)
+#define GLB_REG_GPIO_52_SMT_UMSK (~(((1U << GLB_REG_GPIO_52_SMT_LEN) - 1) << GLB_REG_GPIO_52_SMT_POS))
+#define GLB_REG_GPIO_52_DRV GLB_REG_GPIO_52_DRV
+#define GLB_REG_GPIO_52_DRV_POS (2U)
+#define GLB_REG_GPIO_52_DRV_LEN (2U)
+#define GLB_REG_GPIO_52_DRV_MSK (((1U << GLB_REG_GPIO_52_DRV_LEN) - 1) << GLB_REG_GPIO_52_DRV_POS)
+#define GLB_REG_GPIO_52_DRV_UMSK (~(((1U << GLB_REG_GPIO_52_DRV_LEN) - 1) << GLB_REG_GPIO_52_DRV_POS))
+#define GLB_REG_GPIO_52_PU GLB_REG_GPIO_52_PU
+#define GLB_REG_GPIO_52_PU_POS (4U)
+#define GLB_REG_GPIO_52_PU_LEN (1U)
+#define GLB_REG_GPIO_52_PU_MSK (((1U << GLB_REG_GPIO_52_PU_LEN) - 1) << GLB_REG_GPIO_52_PU_POS)
+#define GLB_REG_GPIO_52_PU_UMSK (~(((1U << GLB_REG_GPIO_52_PU_LEN) - 1) << GLB_REG_GPIO_52_PU_POS))
+#define GLB_REG_GPIO_52_PD GLB_REG_GPIO_52_PD
+#define GLB_REG_GPIO_52_PD_POS (5U)
+#define GLB_REG_GPIO_52_PD_LEN (1U)
+#define GLB_REG_GPIO_52_PD_MSK (((1U << GLB_REG_GPIO_52_PD_LEN) - 1) << GLB_REG_GPIO_52_PD_POS)
+#define GLB_REG_GPIO_52_PD_UMSK (~(((1U << GLB_REG_GPIO_52_PD_LEN) - 1) << GLB_REG_GPIO_52_PD_POS))
+
+/* 0x998 : gpio_cfg53 */
+#define GLB_GPIO_CFG53_OFFSET (0x998)
+#define GLB_REG_GPIO_53_IE GLB_REG_GPIO_53_IE
+#define GLB_REG_GPIO_53_IE_POS (0U)
+#define GLB_REG_GPIO_53_IE_LEN (1U)
+#define GLB_REG_GPIO_53_IE_MSK (((1U << GLB_REG_GPIO_53_IE_LEN) - 1) << GLB_REG_GPIO_53_IE_POS)
+#define GLB_REG_GPIO_53_IE_UMSK (~(((1U << GLB_REG_GPIO_53_IE_LEN) - 1) << GLB_REG_GPIO_53_IE_POS))
+#define GLB_REG_GPIO_53_SMT GLB_REG_GPIO_53_SMT
+#define GLB_REG_GPIO_53_SMT_POS (1U)
+#define GLB_REG_GPIO_53_SMT_LEN (1U)
+#define GLB_REG_GPIO_53_SMT_MSK (((1U << GLB_REG_GPIO_53_SMT_LEN) - 1) << GLB_REG_GPIO_53_SMT_POS)
+#define GLB_REG_GPIO_53_SMT_UMSK (~(((1U << GLB_REG_GPIO_53_SMT_LEN) - 1) << GLB_REG_GPIO_53_SMT_POS))
+#define GLB_REG_GPIO_53_DRV GLB_REG_GPIO_53_DRV
+#define GLB_REG_GPIO_53_DRV_POS (2U)
+#define GLB_REG_GPIO_53_DRV_LEN (2U)
+#define GLB_REG_GPIO_53_DRV_MSK (((1U << GLB_REG_GPIO_53_DRV_LEN) - 1) << GLB_REG_GPIO_53_DRV_POS)
+#define GLB_REG_GPIO_53_DRV_UMSK (~(((1U << GLB_REG_GPIO_53_DRV_LEN) - 1) << GLB_REG_GPIO_53_DRV_POS))
+#define GLB_REG_GPIO_53_PU GLB_REG_GPIO_53_PU
+#define GLB_REG_GPIO_53_PU_POS (4U)
+#define GLB_REG_GPIO_53_PU_LEN (1U)
+#define GLB_REG_GPIO_53_PU_MSK (((1U << GLB_REG_GPIO_53_PU_LEN) - 1) << GLB_REG_GPIO_53_PU_POS)
+#define GLB_REG_GPIO_53_PU_UMSK (~(((1U << GLB_REG_GPIO_53_PU_LEN) - 1) << GLB_REG_GPIO_53_PU_POS))
+#define GLB_REG_GPIO_53_PD GLB_REG_GPIO_53_PD
+#define GLB_REG_GPIO_53_PD_POS (5U)
+#define GLB_REG_GPIO_53_PD_LEN (1U)
+#define GLB_REG_GPIO_53_PD_MSK (((1U << GLB_REG_GPIO_53_PD_LEN) - 1) << GLB_REG_GPIO_53_PD_POS)
+#define GLB_REG_GPIO_53_PD_UMSK (~(((1U << GLB_REG_GPIO_53_PD_LEN) - 1) << GLB_REG_GPIO_53_PD_POS))
+
+/* 0x99C : gpio_cfg54 */
+#define GLB_GPIO_CFG54_OFFSET (0x99C)
+#define GLB_REG_GPIO_54_IE GLB_REG_GPIO_54_IE
+#define GLB_REG_GPIO_54_IE_POS (0U)
+#define GLB_REG_GPIO_54_IE_LEN (1U)
+#define GLB_REG_GPIO_54_IE_MSK (((1U << GLB_REG_GPIO_54_IE_LEN) - 1) << GLB_REG_GPIO_54_IE_POS)
+#define GLB_REG_GPIO_54_IE_UMSK (~(((1U << GLB_REG_GPIO_54_IE_LEN) - 1) << GLB_REG_GPIO_54_IE_POS))
+#define GLB_REG_GPIO_54_SMT GLB_REG_GPIO_54_SMT
+#define GLB_REG_GPIO_54_SMT_POS (1U)
+#define GLB_REG_GPIO_54_SMT_LEN (1U)
+#define GLB_REG_GPIO_54_SMT_MSK (((1U << GLB_REG_GPIO_54_SMT_LEN) - 1) << GLB_REG_GPIO_54_SMT_POS)
+#define GLB_REG_GPIO_54_SMT_UMSK (~(((1U << GLB_REG_GPIO_54_SMT_LEN) - 1) << GLB_REG_GPIO_54_SMT_POS))
+#define GLB_REG_GPIO_54_DRV GLB_REG_GPIO_54_DRV
+#define GLB_REG_GPIO_54_DRV_POS (2U)
+#define GLB_REG_GPIO_54_DRV_LEN (2U)
+#define GLB_REG_GPIO_54_DRV_MSK (((1U << GLB_REG_GPIO_54_DRV_LEN) - 1) << GLB_REG_GPIO_54_DRV_POS)
+#define GLB_REG_GPIO_54_DRV_UMSK (~(((1U << GLB_REG_GPIO_54_DRV_LEN) - 1) << GLB_REG_GPIO_54_DRV_POS))
+#define GLB_REG_GPIO_54_PU GLB_REG_GPIO_54_PU
+#define GLB_REG_GPIO_54_PU_POS (4U)
+#define GLB_REG_GPIO_54_PU_LEN (1U)
+#define GLB_REG_GPIO_54_PU_MSK (((1U << GLB_REG_GPIO_54_PU_LEN) - 1) << GLB_REG_GPIO_54_PU_POS)
+#define GLB_REG_GPIO_54_PU_UMSK (~(((1U << GLB_REG_GPIO_54_PU_LEN) - 1) << GLB_REG_GPIO_54_PU_POS))
+#define GLB_REG_GPIO_54_PD GLB_REG_GPIO_54_PD
+#define GLB_REG_GPIO_54_PD_POS (5U)
+#define GLB_REG_GPIO_54_PD_LEN (1U)
+#define GLB_REG_GPIO_54_PD_MSK (((1U << GLB_REG_GPIO_54_PD_LEN) - 1) << GLB_REG_GPIO_54_PD_POS)
+#define GLB_REG_GPIO_54_PD_UMSK (~(((1U << GLB_REG_GPIO_54_PD_LEN) - 1) << GLB_REG_GPIO_54_PD_POS))
+
+/* 0x9A0 : gpio_cfg55 */
+#define GLB_GPIO_CFG55_OFFSET (0x9A0)
+#define GLB_REG_GPIO_55_IE GLB_REG_GPIO_55_IE
+#define GLB_REG_GPIO_55_IE_POS (0U)
+#define GLB_REG_GPIO_55_IE_LEN (1U)
+#define GLB_REG_GPIO_55_IE_MSK (((1U << GLB_REG_GPIO_55_IE_LEN) - 1) << GLB_REG_GPIO_55_IE_POS)
+#define GLB_REG_GPIO_55_IE_UMSK (~(((1U << GLB_REG_GPIO_55_IE_LEN) - 1) << GLB_REG_GPIO_55_IE_POS))
+#define GLB_REG_GPIO_55_SMT GLB_REG_GPIO_55_SMT
+#define GLB_REG_GPIO_55_SMT_POS (1U)
+#define GLB_REG_GPIO_55_SMT_LEN (1U)
+#define GLB_REG_GPIO_55_SMT_MSK (((1U << GLB_REG_GPIO_55_SMT_LEN) - 1) << GLB_REG_GPIO_55_SMT_POS)
+#define GLB_REG_GPIO_55_SMT_UMSK (~(((1U << GLB_REG_GPIO_55_SMT_LEN) - 1) << GLB_REG_GPIO_55_SMT_POS))
+#define GLB_REG_GPIO_55_DRV GLB_REG_GPIO_55_DRV
+#define GLB_REG_GPIO_55_DRV_POS (2U)
+#define GLB_REG_GPIO_55_DRV_LEN (2U)
+#define GLB_REG_GPIO_55_DRV_MSK (((1U << GLB_REG_GPIO_55_DRV_LEN) - 1) << GLB_REG_GPIO_55_DRV_POS)
+#define GLB_REG_GPIO_55_DRV_UMSK (~(((1U << GLB_REG_GPIO_55_DRV_LEN) - 1) << GLB_REG_GPIO_55_DRV_POS))
+#define GLB_REG_GPIO_55_PU GLB_REG_GPIO_55_PU
+#define GLB_REG_GPIO_55_PU_POS (4U)
+#define GLB_REG_GPIO_55_PU_LEN (1U)
+#define GLB_REG_GPIO_55_PU_MSK (((1U << GLB_REG_GPIO_55_PU_LEN) - 1) << GLB_REG_GPIO_55_PU_POS)
+#define GLB_REG_GPIO_55_PU_UMSK (~(((1U << GLB_REG_GPIO_55_PU_LEN) - 1) << GLB_REG_GPIO_55_PU_POS))
+#define GLB_REG_GPIO_55_PD GLB_REG_GPIO_55_PD
+#define GLB_REG_GPIO_55_PD_POS (5U)
+#define GLB_REG_GPIO_55_PD_LEN (1U)
+#define GLB_REG_GPIO_55_PD_MSK (((1U << GLB_REG_GPIO_55_PD_LEN) - 1) << GLB_REG_GPIO_55_PD_POS)
+#define GLB_REG_GPIO_55_PD_UMSK (~(((1U << GLB_REG_GPIO_55_PD_LEN) - 1) << GLB_REG_GPIO_55_PD_POS))
+
+/* 0x9A4 : gpio_cfg56 */
+#define GLB_GPIO_CFG56_OFFSET (0x9A4)
+#define GLB_REG_GPIO_56_IE GLB_REG_GPIO_56_IE
+#define GLB_REG_GPIO_56_IE_POS (0U)
+#define GLB_REG_GPIO_56_IE_LEN (1U)
+#define GLB_REG_GPIO_56_IE_MSK (((1U << GLB_REG_GPIO_56_IE_LEN) - 1) << GLB_REG_GPIO_56_IE_POS)
+#define GLB_REG_GPIO_56_IE_UMSK (~(((1U << GLB_REG_GPIO_56_IE_LEN) - 1) << GLB_REG_GPIO_56_IE_POS))
+#define GLB_REG_GPIO_56_SMT GLB_REG_GPIO_56_SMT
+#define GLB_REG_GPIO_56_SMT_POS (1U)
+#define GLB_REG_GPIO_56_SMT_LEN (1U)
+#define GLB_REG_GPIO_56_SMT_MSK (((1U << GLB_REG_GPIO_56_SMT_LEN) - 1) << GLB_REG_GPIO_56_SMT_POS)
+#define GLB_REG_GPIO_56_SMT_UMSK (~(((1U << GLB_REG_GPIO_56_SMT_LEN) - 1) << GLB_REG_GPIO_56_SMT_POS))
+#define GLB_REG_GPIO_56_DRV GLB_REG_GPIO_56_DRV
+#define GLB_REG_GPIO_56_DRV_POS (2U)
+#define GLB_REG_GPIO_56_DRV_LEN (2U)
+#define GLB_REG_GPIO_56_DRV_MSK (((1U << GLB_REG_GPIO_56_DRV_LEN) - 1) << GLB_REG_GPIO_56_DRV_POS)
+#define GLB_REG_GPIO_56_DRV_UMSK (~(((1U << GLB_REG_GPIO_56_DRV_LEN) - 1) << GLB_REG_GPIO_56_DRV_POS))
+#define GLB_REG_GPIO_56_PU GLB_REG_GPIO_56_PU
+#define GLB_REG_GPIO_56_PU_POS (4U)
+#define GLB_REG_GPIO_56_PU_LEN (1U)
+#define GLB_REG_GPIO_56_PU_MSK (((1U << GLB_REG_GPIO_56_PU_LEN) - 1) << GLB_REG_GPIO_56_PU_POS)
+#define GLB_REG_GPIO_56_PU_UMSK (~(((1U << GLB_REG_GPIO_56_PU_LEN) - 1) << GLB_REG_GPIO_56_PU_POS))
+#define GLB_REG_GPIO_56_PD GLB_REG_GPIO_56_PD
+#define GLB_REG_GPIO_56_PD_POS (5U)
+#define GLB_REG_GPIO_56_PD_LEN (1U)
+#define GLB_REG_GPIO_56_PD_MSK (((1U << GLB_REG_GPIO_56_PD_LEN) - 1) << GLB_REG_GPIO_56_PD_POS)
+#define GLB_REG_GPIO_56_PD_UMSK (~(((1U << GLB_REG_GPIO_56_PD_LEN) - 1) << GLB_REG_GPIO_56_PD_POS))
+
+/* 0x9A8 : gpio_cfg57 */
+#define GLB_GPIO_CFG57_OFFSET (0x9A8)
+#define GLB_REG_GPIO_57_IE GLB_REG_GPIO_57_IE
+#define GLB_REG_GPIO_57_IE_POS (0U)
+#define GLB_REG_GPIO_57_IE_LEN (1U)
+#define GLB_REG_GPIO_57_IE_MSK (((1U << GLB_REG_GPIO_57_IE_LEN) - 1) << GLB_REG_GPIO_57_IE_POS)
+#define GLB_REG_GPIO_57_IE_UMSK (~(((1U << GLB_REG_GPIO_57_IE_LEN) - 1) << GLB_REG_GPIO_57_IE_POS))
+#define GLB_REG_GPIO_57_SMT GLB_REG_GPIO_57_SMT
+#define GLB_REG_GPIO_57_SMT_POS (1U)
+#define GLB_REG_GPIO_57_SMT_LEN (1U)
+#define GLB_REG_GPIO_57_SMT_MSK (((1U << GLB_REG_GPIO_57_SMT_LEN) - 1) << GLB_REG_GPIO_57_SMT_POS)
+#define GLB_REG_GPIO_57_SMT_UMSK (~(((1U << GLB_REG_GPIO_57_SMT_LEN) - 1) << GLB_REG_GPIO_57_SMT_POS))
+#define GLB_REG_GPIO_57_DRV GLB_REG_GPIO_57_DRV
+#define GLB_REG_GPIO_57_DRV_POS (2U)
+#define GLB_REG_GPIO_57_DRV_LEN (2U)
+#define GLB_REG_GPIO_57_DRV_MSK (((1U << GLB_REG_GPIO_57_DRV_LEN) - 1) << GLB_REG_GPIO_57_DRV_POS)
+#define GLB_REG_GPIO_57_DRV_UMSK (~(((1U << GLB_REG_GPIO_57_DRV_LEN) - 1) << GLB_REG_GPIO_57_DRV_POS))
+#define GLB_REG_GPIO_57_PU GLB_REG_GPIO_57_PU
+#define GLB_REG_GPIO_57_PU_POS (4U)
+#define GLB_REG_GPIO_57_PU_LEN (1U)
+#define GLB_REG_GPIO_57_PU_MSK (((1U << GLB_REG_GPIO_57_PU_LEN) - 1) << GLB_REG_GPIO_57_PU_POS)
+#define GLB_REG_GPIO_57_PU_UMSK (~(((1U << GLB_REG_GPIO_57_PU_LEN) - 1) << GLB_REG_GPIO_57_PU_POS))
+#define GLB_REG_GPIO_57_PD GLB_REG_GPIO_57_PD
+#define GLB_REG_GPIO_57_PD_POS (5U)
+#define GLB_REG_GPIO_57_PD_LEN (1U)
+#define GLB_REG_GPIO_57_PD_MSK (((1U << GLB_REG_GPIO_57_PD_LEN) - 1) << GLB_REG_GPIO_57_PD_POS)
+#define GLB_REG_GPIO_57_PD_UMSK (~(((1U << GLB_REG_GPIO_57_PD_LEN) - 1) << GLB_REG_GPIO_57_PD_POS))
+
+/* 0x9AC : gpio_cfg58 */
+#define GLB_GPIO_CFG58_OFFSET (0x9AC)
+#define GLB_REG_GPIO_58_IE GLB_REG_GPIO_58_IE
+#define GLB_REG_GPIO_58_IE_POS (0U)
+#define GLB_REG_GPIO_58_IE_LEN (1U)
+#define GLB_REG_GPIO_58_IE_MSK (((1U << GLB_REG_GPIO_58_IE_LEN) - 1) << GLB_REG_GPIO_58_IE_POS)
+#define GLB_REG_GPIO_58_IE_UMSK (~(((1U << GLB_REG_GPIO_58_IE_LEN) - 1) << GLB_REG_GPIO_58_IE_POS))
+#define GLB_REG_GPIO_58_SMT GLB_REG_GPIO_58_SMT
+#define GLB_REG_GPIO_58_SMT_POS (1U)
+#define GLB_REG_GPIO_58_SMT_LEN (1U)
+#define GLB_REG_GPIO_58_SMT_MSK (((1U << GLB_REG_GPIO_58_SMT_LEN) - 1) << GLB_REG_GPIO_58_SMT_POS)
+#define GLB_REG_GPIO_58_SMT_UMSK (~(((1U << GLB_REG_GPIO_58_SMT_LEN) - 1) << GLB_REG_GPIO_58_SMT_POS))
+#define GLB_REG_GPIO_58_DRV GLB_REG_GPIO_58_DRV
+#define GLB_REG_GPIO_58_DRV_POS (2U)
+#define GLB_REG_GPIO_58_DRV_LEN (2U)
+#define GLB_REG_GPIO_58_DRV_MSK (((1U << GLB_REG_GPIO_58_DRV_LEN) - 1) << GLB_REG_GPIO_58_DRV_POS)
+#define GLB_REG_GPIO_58_DRV_UMSK (~(((1U << GLB_REG_GPIO_58_DRV_LEN) - 1) << GLB_REG_GPIO_58_DRV_POS))
+#define GLB_REG_GPIO_58_PU GLB_REG_GPIO_58_PU
+#define GLB_REG_GPIO_58_PU_POS (4U)
+#define GLB_REG_GPIO_58_PU_LEN (1U)
+#define GLB_REG_GPIO_58_PU_MSK (((1U << GLB_REG_GPIO_58_PU_LEN) - 1) << GLB_REG_GPIO_58_PU_POS)
+#define GLB_REG_GPIO_58_PU_UMSK (~(((1U << GLB_REG_GPIO_58_PU_LEN) - 1) << GLB_REG_GPIO_58_PU_POS))
+#define GLB_REG_GPIO_58_PD GLB_REG_GPIO_58_PD
+#define GLB_REG_GPIO_58_PD_POS (5U)
+#define GLB_REG_GPIO_58_PD_LEN (1U)
+#define GLB_REG_GPIO_58_PD_MSK (((1U << GLB_REG_GPIO_58_PD_LEN) - 1) << GLB_REG_GPIO_58_PD_POS)
+#define GLB_REG_GPIO_58_PD_UMSK (~(((1U << GLB_REG_GPIO_58_PD_LEN) - 1) << GLB_REG_GPIO_58_PD_POS))
+
+/* 0x9B0 : gpio_cfg59 */
+#define GLB_GPIO_CFG59_OFFSET (0x9B0)
+#define GLB_REG_GPIO_59_IE GLB_REG_GPIO_59_IE
+#define GLB_REG_GPIO_59_IE_POS (0U)
+#define GLB_REG_GPIO_59_IE_LEN (1U)
+#define GLB_REG_GPIO_59_IE_MSK (((1U << GLB_REG_GPIO_59_IE_LEN) - 1) << GLB_REG_GPIO_59_IE_POS)
+#define GLB_REG_GPIO_59_IE_UMSK (~(((1U << GLB_REG_GPIO_59_IE_LEN) - 1) << GLB_REG_GPIO_59_IE_POS))
+#define GLB_REG_GPIO_59_SMT GLB_REG_GPIO_59_SMT
+#define GLB_REG_GPIO_59_SMT_POS (1U)
+#define GLB_REG_GPIO_59_SMT_LEN (1U)
+#define GLB_REG_GPIO_59_SMT_MSK (((1U << GLB_REG_GPIO_59_SMT_LEN) - 1) << GLB_REG_GPIO_59_SMT_POS)
+#define GLB_REG_GPIO_59_SMT_UMSK (~(((1U << GLB_REG_GPIO_59_SMT_LEN) - 1) << GLB_REG_GPIO_59_SMT_POS))
+#define GLB_REG_GPIO_59_DRV GLB_REG_GPIO_59_DRV
+#define GLB_REG_GPIO_59_DRV_POS (2U)
+#define GLB_REG_GPIO_59_DRV_LEN (2U)
+#define GLB_REG_GPIO_59_DRV_MSK (((1U << GLB_REG_GPIO_59_DRV_LEN) - 1) << GLB_REG_GPIO_59_DRV_POS)
+#define GLB_REG_GPIO_59_DRV_UMSK (~(((1U << GLB_REG_GPIO_59_DRV_LEN) - 1) << GLB_REG_GPIO_59_DRV_POS))
+#define GLB_REG_GPIO_59_PU GLB_REG_GPIO_59_PU
+#define GLB_REG_GPIO_59_PU_POS (4U)
+#define GLB_REG_GPIO_59_PU_LEN (1U)
+#define GLB_REG_GPIO_59_PU_MSK (((1U << GLB_REG_GPIO_59_PU_LEN) - 1) << GLB_REG_GPIO_59_PU_POS)
+#define GLB_REG_GPIO_59_PU_UMSK (~(((1U << GLB_REG_GPIO_59_PU_LEN) - 1) << GLB_REG_GPIO_59_PU_POS))
+#define GLB_REG_GPIO_59_PD GLB_REG_GPIO_59_PD
+#define GLB_REG_GPIO_59_PD_POS (5U)
+#define GLB_REG_GPIO_59_PD_LEN (1U)
+#define GLB_REG_GPIO_59_PD_MSK (((1U << GLB_REG_GPIO_59_PD_LEN) - 1) << GLB_REG_GPIO_59_PD_POS)
+#define GLB_REG_GPIO_59_PD_UMSK (~(((1U << GLB_REG_GPIO_59_PD_LEN) - 1) << GLB_REG_GPIO_59_PD_POS))
+
+/* 0x9B4 : gpio_cfg60 */
+#define GLB_GPIO_CFG60_OFFSET (0x9B4)
+#define GLB_REG_GPIO_60_IE GLB_REG_GPIO_60_IE
+#define GLB_REG_GPIO_60_IE_POS (0U)
+#define GLB_REG_GPIO_60_IE_LEN (1U)
+#define GLB_REG_GPIO_60_IE_MSK (((1U << GLB_REG_GPIO_60_IE_LEN) - 1) << GLB_REG_GPIO_60_IE_POS)
+#define GLB_REG_GPIO_60_IE_UMSK (~(((1U << GLB_REG_GPIO_60_IE_LEN) - 1) << GLB_REG_GPIO_60_IE_POS))
+#define GLB_REG_GPIO_60_SMT GLB_REG_GPIO_60_SMT
+#define GLB_REG_GPIO_60_SMT_POS (1U)
+#define GLB_REG_GPIO_60_SMT_LEN (1U)
+#define GLB_REG_GPIO_60_SMT_MSK (((1U << GLB_REG_GPIO_60_SMT_LEN) - 1) << GLB_REG_GPIO_60_SMT_POS)
+#define GLB_REG_GPIO_60_SMT_UMSK (~(((1U << GLB_REG_GPIO_60_SMT_LEN) - 1) << GLB_REG_GPIO_60_SMT_POS))
+#define GLB_REG_GPIO_60_DRV GLB_REG_GPIO_60_DRV
+#define GLB_REG_GPIO_60_DRV_POS (2U)
+#define GLB_REG_GPIO_60_DRV_LEN (2U)
+#define GLB_REG_GPIO_60_DRV_MSK (((1U << GLB_REG_GPIO_60_DRV_LEN) - 1) << GLB_REG_GPIO_60_DRV_POS)
+#define GLB_REG_GPIO_60_DRV_UMSK (~(((1U << GLB_REG_GPIO_60_DRV_LEN) - 1) << GLB_REG_GPIO_60_DRV_POS))
+#define GLB_REG_GPIO_60_PU GLB_REG_GPIO_60_PU
+#define GLB_REG_GPIO_60_PU_POS (4U)
+#define GLB_REG_GPIO_60_PU_LEN (1U)
+#define GLB_REG_GPIO_60_PU_MSK (((1U << GLB_REG_GPIO_60_PU_LEN) - 1) << GLB_REG_GPIO_60_PU_POS)
+#define GLB_REG_GPIO_60_PU_UMSK (~(((1U << GLB_REG_GPIO_60_PU_LEN) - 1) << GLB_REG_GPIO_60_PU_POS))
+#define GLB_REG_GPIO_60_PD GLB_REG_GPIO_60_PD
+#define GLB_REG_GPIO_60_PD_POS (5U)
+#define GLB_REG_GPIO_60_PD_LEN (1U)
+#define GLB_REG_GPIO_60_PD_MSK (((1U << GLB_REG_GPIO_60_PD_LEN) - 1) << GLB_REG_GPIO_60_PD_POS)
+#define GLB_REG_GPIO_60_PD_UMSK (~(((1U << GLB_REG_GPIO_60_PD_LEN) - 1) << GLB_REG_GPIO_60_PD_POS))
+
+/* 0x9B8 : gpio_cfg61 */
+#define GLB_GPIO_CFG61_OFFSET (0x9B8)
+#define GLB_REG_GPIO_61_IE GLB_REG_GPIO_61_IE
+#define GLB_REG_GPIO_61_IE_POS (0U)
+#define GLB_REG_GPIO_61_IE_LEN (1U)
+#define GLB_REG_GPIO_61_IE_MSK (((1U << GLB_REG_GPIO_61_IE_LEN) - 1) << GLB_REG_GPIO_61_IE_POS)
+#define GLB_REG_GPIO_61_IE_UMSK (~(((1U << GLB_REG_GPIO_61_IE_LEN) - 1) << GLB_REG_GPIO_61_IE_POS))
+#define GLB_REG_GPIO_61_SMT GLB_REG_GPIO_61_SMT
+#define GLB_REG_GPIO_61_SMT_POS (1U)
+#define GLB_REG_GPIO_61_SMT_LEN (1U)
+#define GLB_REG_GPIO_61_SMT_MSK (((1U << GLB_REG_GPIO_61_SMT_LEN) - 1) << GLB_REG_GPIO_61_SMT_POS)
+#define GLB_REG_GPIO_61_SMT_UMSK (~(((1U << GLB_REG_GPIO_61_SMT_LEN) - 1) << GLB_REG_GPIO_61_SMT_POS))
+#define GLB_REG_GPIO_61_DRV GLB_REG_GPIO_61_DRV
+#define GLB_REG_GPIO_61_DRV_POS (2U)
+#define GLB_REG_GPIO_61_DRV_LEN (2U)
+#define GLB_REG_GPIO_61_DRV_MSK (((1U << GLB_REG_GPIO_61_DRV_LEN) - 1) << GLB_REG_GPIO_61_DRV_POS)
+#define GLB_REG_GPIO_61_DRV_UMSK (~(((1U << GLB_REG_GPIO_61_DRV_LEN) - 1) << GLB_REG_GPIO_61_DRV_POS))
+#define GLB_REG_GPIO_61_PU GLB_REG_GPIO_61_PU
+#define GLB_REG_GPIO_61_PU_POS (4U)
+#define GLB_REG_GPIO_61_PU_LEN (1U)
+#define GLB_REG_GPIO_61_PU_MSK (((1U << GLB_REG_GPIO_61_PU_LEN) - 1) << GLB_REG_GPIO_61_PU_POS)
+#define GLB_REG_GPIO_61_PU_UMSK (~(((1U << GLB_REG_GPIO_61_PU_LEN) - 1) << GLB_REG_GPIO_61_PU_POS))
+#define GLB_REG_GPIO_61_PD GLB_REG_GPIO_61_PD
+#define GLB_REG_GPIO_61_PD_POS (5U)
+#define GLB_REG_GPIO_61_PD_LEN (1U)
+#define GLB_REG_GPIO_61_PD_MSK (((1U << GLB_REG_GPIO_61_PD_LEN) - 1) << GLB_REG_GPIO_61_PD_POS)
+#define GLB_REG_GPIO_61_PD_UMSK (~(((1U << GLB_REG_GPIO_61_PD_LEN) - 1) << GLB_REG_GPIO_61_PD_POS))
+
+/* 0x9BC : gpio_cfg62 */
+#define GLB_GPIO_CFG62_OFFSET (0x9BC)
+#define GLB_REG_GPIO_62_IE GLB_REG_GPIO_62_IE
+#define GLB_REG_GPIO_62_IE_POS (0U)
+#define GLB_REG_GPIO_62_IE_LEN (1U)
+#define GLB_REG_GPIO_62_IE_MSK (((1U << GLB_REG_GPIO_62_IE_LEN) - 1) << GLB_REG_GPIO_62_IE_POS)
+#define GLB_REG_GPIO_62_IE_UMSK (~(((1U << GLB_REG_GPIO_62_IE_LEN) - 1) << GLB_REG_GPIO_62_IE_POS))
+#define GLB_REG_GPIO_62_SMT GLB_REG_GPIO_62_SMT
+#define GLB_REG_GPIO_62_SMT_POS (1U)
+#define GLB_REG_GPIO_62_SMT_LEN (1U)
+#define GLB_REG_GPIO_62_SMT_MSK (((1U << GLB_REG_GPIO_62_SMT_LEN) - 1) << GLB_REG_GPIO_62_SMT_POS)
+#define GLB_REG_GPIO_62_SMT_UMSK (~(((1U << GLB_REG_GPIO_62_SMT_LEN) - 1) << GLB_REG_GPIO_62_SMT_POS))
+#define GLB_REG_GPIO_62_DRV GLB_REG_GPIO_62_DRV
+#define GLB_REG_GPIO_62_DRV_POS (2U)
+#define GLB_REG_GPIO_62_DRV_LEN (2U)
+#define GLB_REG_GPIO_62_DRV_MSK (((1U << GLB_REG_GPIO_62_DRV_LEN) - 1) << GLB_REG_GPIO_62_DRV_POS)
+#define GLB_REG_GPIO_62_DRV_UMSK (~(((1U << GLB_REG_GPIO_62_DRV_LEN) - 1) << GLB_REG_GPIO_62_DRV_POS))
+#define GLB_REG_GPIO_62_PU GLB_REG_GPIO_62_PU
+#define GLB_REG_GPIO_62_PU_POS (4U)
+#define GLB_REG_GPIO_62_PU_LEN (1U)
+#define GLB_REG_GPIO_62_PU_MSK (((1U << GLB_REG_GPIO_62_PU_LEN) - 1) << GLB_REG_GPIO_62_PU_POS)
+#define GLB_REG_GPIO_62_PU_UMSK (~(((1U << GLB_REG_GPIO_62_PU_LEN) - 1) << GLB_REG_GPIO_62_PU_POS))
+#define GLB_REG_GPIO_62_PD GLB_REG_GPIO_62_PD
+#define GLB_REG_GPIO_62_PD_POS (5U)
+#define GLB_REG_GPIO_62_PD_LEN (1U)
+#define GLB_REG_GPIO_62_PD_MSK (((1U << GLB_REG_GPIO_62_PD_LEN) - 1) << GLB_REG_GPIO_62_PD_POS)
+#define GLB_REG_GPIO_62_PD_UMSK (~(((1U << GLB_REG_GPIO_62_PD_LEN) - 1) << GLB_REG_GPIO_62_PD_POS))
+
+/* 0x9C0 : gpio_cfg63 */
+#define GLB_GPIO_CFG63_OFFSET (0x9C0)
+#define GLB_REG_GPIO_63_IE GLB_REG_GPIO_63_IE
+#define GLB_REG_GPIO_63_IE_POS (0U)
+#define GLB_REG_GPIO_63_IE_LEN (1U)
+#define GLB_REG_GPIO_63_IE_MSK (((1U << GLB_REG_GPIO_63_IE_LEN) - 1) << GLB_REG_GPIO_63_IE_POS)
+#define GLB_REG_GPIO_63_IE_UMSK (~(((1U << GLB_REG_GPIO_63_IE_LEN) - 1) << GLB_REG_GPIO_63_IE_POS))
+#define GLB_REG_GPIO_63_SMT GLB_REG_GPIO_63_SMT
+#define GLB_REG_GPIO_63_SMT_POS (1U)
+#define GLB_REG_GPIO_63_SMT_LEN (1U)
+#define GLB_REG_GPIO_63_SMT_MSK (((1U << GLB_REG_GPIO_63_SMT_LEN) - 1) << GLB_REG_GPIO_63_SMT_POS)
+#define GLB_REG_GPIO_63_SMT_UMSK (~(((1U << GLB_REG_GPIO_63_SMT_LEN) - 1) << GLB_REG_GPIO_63_SMT_POS))
+#define GLB_REG_GPIO_63_DRV GLB_REG_GPIO_63_DRV
+#define GLB_REG_GPIO_63_DRV_POS (2U)
+#define GLB_REG_GPIO_63_DRV_LEN (2U)
+#define GLB_REG_GPIO_63_DRV_MSK (((1U << GLB_REG_GPIO_63_DRV_LEN) - 1) << GLB_REG_GPIO_63_DRV_POS)
+#define GLB_REG_GPIO_63_DRV_UMSK (~(((1U << GLB_REG_GPIO_63_DRV_LEN) - 1) << GLB_REG_GPIO_63_DRV_POS))
+#define GLB_REG_GPIO_63_PU GLB_REG_GPIO_63_PU
+#define GLB_REG_GPIO_63_PU_POS (4U)
+#define GLB_REG_GPIO_63_PU_LEN (1U)
+#define GLB_REG_GPIO_63_PU_MSK (((1U << GLB_REG_GPIO_63_PU_LEN) - 1) << GLB_REG_GPIO_63_PU_POS)
+#define GLB_REG_GPIO_63_PU_UMSK (~(((1U << GLB_REG_GPIO_63_PU_LEN) - 1) << GLB_REG_GPIO_63_PU_POS))
+#define GLB_REG_GPIO_63_PD GLB_REG_GPIO_63_PD
+#define GLB_REG_GPIO_63_PD_POS (5U)
+#define GLB_REG_GPIO_63_PD_LEN (1U)
+#define GLB_REG_GPIO_63_PD_MSK (((1U << GLB_REG_GPIO_63_PD_LEN) - 1) << GLB_REG_GPIO_63_PD_POS)
+#define GLB_REG_GPIO_63_PD_UMSK (~(((1U << GLB_REG_GPIO_63_PD_LEN) - 1) << GLB_REG_GPIO_63_PD_POS))
+
+/* 0xAC4 : gpio_cfg128 */
+#define GLB_GPIO_CFG128_OFFSET (0xAC4)
+#define GLB_REG2_GPIO_0_I GLB_REG2_GPIO_0_I
+#define GLB_REG2_GPIO_0_I_POS (0U)
+#define GLB_REG2_GPIO_0_I_LEN (1U)
+#define GLB_REG2_GPIO_0_I_MSK (((1U << GLB_REG2_GPIO_0_I_LEN) - 1) << GLB_REG2_GPIO_0_I_POS)
+#define GLB_REG2_GPIO_0_I_UMSK (~(((1U << GLB_REG2_GPIO_0_I_LEN) - 1) << GLB_REG2_GPIO_0_I_POS))
+#define GLB_REG2_GPIO_1_I GLB_REG2_GPIO_1_I
+#define GLB_REG2_GPIO_1_I_POS (1U)
+#define GLB_REG2_GPIO_1_I_LEN (1U)
+#define GLB_REG2_GPIO_1_I_MSK (((1U << GLB_REG2_GPIO_1_I_LEN) - 1) << GLB_REG2_GPIO_1_I_POS)
+#define GLB_REG2_GPIO_1_I_UMSK (~(((1U << GLB_REG2_GPIO_1_I_LEN) - 1) << GLB_REG2_GPIO_1_I_POS))
+#define GLB_REG2_GPIO_2_I GLB_REG2_GPIO_2_I
+#define GLB_REG2_GPIO_2_I_POS (2U)
+#define GLB_REG2_GPIO_2_I_LEN (1U)
+#define GLB_REG2_GPIO_2_I_MSK (((1U << GLB_REG2_GPIO_2_I_LEN) - 1) << GLB_REG2_GPIO_2_I_POS)
+#define GLB_REG2_GPIO_2_I_UMSK (~(((1U << GLB_REG2_GPIO_2_I_LEN) - 1) << GLB_REG2_GPIO_2_I_POS))
+#define GLB_REG2_GPIO_3_I GLB_REG2_GPIO_3_I
+#define GLB_REG2_GPIO_3_I_POS (3U)
+#define GLB_REG2_GPIO_3_I_LEN (1U)
+#define GLB_REG2_GPIO_3_I_MSK (((1U << GLB_REG2_GPIO_3_I_LEN) - 1) << GLB_REG2_GPIO_3_I_POS)
+#define GLB_REG2_GPIO_3_I_UMSK (~(((1U << GLB_REG2_GPIO_3_I_LEN) - 1) << GLB_REG2_GPIO_3_I_POS))
+#define GLB_REG2_GPIO_4_I GLB_REG2_GPIO_4_I
+#define GLB_REG2_GPIO_4_I_POS (4U)
+#define GLB_REG2_GPIO_4_I_LEN (1U)
+#define GLB_REG2_GPIO_4_I_MSK (((1U << GLB_REG2_GPIO_4_I_LEN) - 1) << GLB_REG2_GPIO_4_I_POS)
+#define GLB_REG2_GPIO_4_I_UMSK (~(((1U << GLB_REG2_GPIO_4_I_LEN) - 1) << GLB_REG2_GPIO_4_I_POS))
+#define GLB_REG2_GPIO_5_I GLB_REG2_GPIO_5_I
+#define GLB_REG2_GPIO_5_I_POS (5U)
+#define GLB_REG2_GPIO_5_I_LEN (1U)
+#define GLB_REG2_GPIO_5_I_MSK (((1U << GLB_REG2_GPIO_5_I_LEN) - 1) << GLB_REG2_GPIO_5_I_POS)
+#define GLB_REG2_GPIO_5_I_UMSK (~(((1U << GLB_REG2_GPIO_5_I_LEN) - 1) << GLB_REG2_GPIO_5_I_POS))
+#define GLB_REG2_GPIO_6_I GLB_REG2_GPIO_6_I
+#define GLB_REG2_GPIO_6_I_POS (6U)
+#define GLB_REG2_GPIO_6_I_LEN (1U)
+#define GLB_REG2_GPIO_6_I_MSK (((1U << GLB_REG2_GPIO_6_I_LEN) - 1) << GLB_REG2_GPIO_6_I_POS)
+#define GLB_REG2_GPIO_6_I_UMSK (~(((1U << GLB_REG2_GPIO_6_I_LEN) - 1) << GLB_REG2_GPIO_6_I_POS))
+#define GLB_REG2_GPIO_7_I GLB_REG2_GPIO_7_I
+#define GLB_REG2_GPIO_7_I_POS (7U)
+#define GLB_REG2_GPIO_7_I_LEN (1U)
+#define GLB_REG2_GPIO_7_I_MSK (((1U << GLB_REG2_GPIO_7_I_LEN) - 1) << GLB_REG2_GPIO_7_I_POS)
+#define GLB_REG2_GPIO_7_I_UMSK (~(((1U << GLB_REG2_GPIO_7_I_LEN) - 1) << GLB_REG2_GPIO_7_I_POS))
+#define GLB_REG2_GPIO_8_I GLB_REG2_GPIO_8_I
+#define GLB_REG2_GPIO_8_I_POS (8U)
+#define GLB_REG2_GPIO_8_I_LEN (1U)
+#define GLB_REG2_GPIO_8_I_MSK (((1U << GLB_REG2_GPIO_8_I_LEN) - 1) << GLB_REG2_GPIO_8_I_POS)
+#define GLB_REG2_GPIO_8_I_UMSK (~(((1U << GLB_REG2_GPIO_8_I_LEN) - 1) << GLB_REG2_GPIO_8_I_POS))
+#define GLB_REG2_GPIO_9_I GLB_REG2_GPIO_9_I
+#define GLB_REG2_GPIO_9_I_POS (9U)
+#define GLB_REG2_GPIO_9_I_LEN (1U)
+#define GLB_REG2_GPIO_9_I_MSK (((1U << GLB_REG2_GPIO_9_I_LEN) - 1) << GLB_REG2_GPIO_9_I_POS)
+#define GLB_REG2_GPIO_9_I_UMSK (~(((1U << GLB_REG2_GPIO_9_I_LEN) - 1) << GLB_REG2_GPIO_9_I_POS))
+#define GLB_REG2_GPIO_10_I GLB_REG2_GPIO_10_I
+#define GLB_REG2_GPIO_10_I_POS (10U)
+#define GLB_REG2_GPIO_10_I_LEN (1U)
+#define GLB_REG2_GPIO_10_I_MSK (((1U << GLB_REG2_GPIO_10_I_LEN) - 1) << GLB_REG2_GPIO_10_I_POS)
+#define GLB_REG2_GPIO_10_I_UMSK (~(((1U << GLB_REG2_GPIO_10_I_LEN) - 1) << GLB_REG2_GPIO_10_I_POS))
+#define GLB_REG2_GPIO_11_I GLB_REG2_GPIO_11_I
+#define GLB_REG2_GPIO_11_I_POS (11U)
+#define GLB_REG2_GPIO_11_I_LEN (1U)
+#define GLB_REG2_GPIO_11_I_MSK (((1U << GLB_REG2_GPIO_11_I_LEN) - 1) << GLB_REG2_GPIO_11_I_POS)
+#define GLB_REG2_GPIO_11_I_UMSK (~(((1U << GLB_REG2_GPIO_11_I_LEN) - 1) << GLB_REG2_GPIO_11_I_POS))
+#define GLB_REG2_GPIO_12_I GLB_REG2_GPIO_12_I
+#define GLB_REG2_GPIO_12_I_POS (12U)
+#define GLB_REG2_GPIO_12_I_LEN (1U)
+#define GLB_REG2_GPIO_12_I_MSK (((1U << GLB_REG2_GPIO_12_I_LEN) - 1) << GLB_REG2_GPIO_12_I_POS)
+#define GLB_REG2_GPIO_12_I_UMSK (~(((1U << GLB_REG2_GPIO_12_I_LEN) - 1) << GLB_REG2_GPIO_12_I_POS))
+#define GLB_REG2_GPIO_13_I GLB_REG2_GPIO_13_I
+#define GLB_REG2_GPIO_13_I_POS (13U)
+#define GLB_REG2_GPIO_13_I_LEN (1U)
+#define GLB_REG2_GPIO_13_I_MSK (((1U << GLB_REG2_GPIO_13_I_LEN) - 1) << GLB_REG2_GPIO_13_I_POS)
+#define GLB_REG2_GPIO_13_I_UMSK (~(((1U << GLB_REG2_GPIO_13_I_LEN) - 1) << GLB_REG2_GPIO_13_I_POS))
+#define GLB_REG2_GPIO_14_I GLB_REG2_GPIO_14_I
+#define GLB_REG2_GPIO_14_I_POS (14U)
+#define GLB_REG2_GPIO_14_I_LEN (1U)
+#define GLB_REG2_GPIO_14_I_MSK (((1U << GLB_REG2_GPIO_14_I_LEN) - 1) << GLB_REG2_GPIO_14_I_POS)
+#define GLB_REG2_GPIO_14_I_UMSK (~(((1U << GLB_REG2_GPIO_14_I_LEN) - 1) << GLB_REG2_GPIO_14_I_POS))
+#define GLB_REG2_GPIO_15_I GLB_REG2_GPIO_15_I
+#define GLB_REG2_GPIO_15_I_POS (15U)
+#define GLB_REG2_GPIO_15_I_LEN (1U)
+#define GLB_REG2_GPIO_15_I_MSK (((1U << GLB_REG2_GPIO_15_I_LEN) - 1) << GLB_REG2_GPIO_15_I_POS)
+#define GLB_REG2_GPIO_15_I_UMSK (~(((1U << GLB_REG2_GPIO_15_I_LEN) - 1) << GLB_REG2_GPIO_15_I_POS))
+#define GLB_REG2_GPIO_16_I GLB_REG2_GPIO_16_I
+#define GLB_REG2_GPIO_16_I_POS (16U)
+#define GLB_REG2_GPIO_16_I_LEN (1U)
+#define GLB_REG2_GPIO_16_I_MSK (((1U << GLB_REG2_GPIO_16_I_LEN) - 1) << GLB_REG2_GPIO_16_I_POS)
+#define GLB_REG2_GPIO_16_I_UMSK (~(((1U << GLB_REG2_GPIO_16_I_LEN) - 1) << GLB_REG2_GPIO_16_I_POS))
+#define GLB_REG2_GPIO_17_I GLB_REG2_GPIO_17_I
+#define GLB_REG2_GPIO_17_I_POS (17U)
+#define GLB_REG2_GPIO_17_I_LEN (1U)
+#define GLB_REG2_GPIO_17_I_MSK (((1U << GLB_REG2_GPIO_17_I_LEN) - 1) << GLB_REG2_GPIO_17_I_POS)
+#define GLB_REG2_GPIO_17_I_UMSK (~(((1U << GLB_REG2_GPIO_17_I_LEN) - 1) << GLB_REG2_GPIO_17_I_POS))
+#define GLB_REG2_GPIO_18_I GLB_REG2_GPIO_18_I
+#define GLB_REG2_GPIO_18_I_POS (18U)
+#define GLB_REG2_GPIO_18_I_LEN (1U)
+#define GLB_REG2_GPIO_18_I_MSK (((1U << GLB_REG2_GPIO_18_I_LEN) - 1) << GLB_REG2_GPIO_18_I_POS)
+#define GLB_REG2_GPIO_18_I_UMSK (~(((1U << GLB_REG2_GPIO_18_I_LEN) - 1) << GLB_REG2_GPIO_18_I_POS))
+#define GLB_REG2_GPIO_19_I GLB_REG2_GPIO_19_I
+#define GLB_REG2_GPIO_19_I_POS (19U)
+#define GLB_REG2_GPIO_19_I_LEN (1U)
+#define GLB_REG2_GPIO_19_I_MSK (((1U << GLB_REG2_GPIO_19_I_LEN) - 1) << GLB_REG2_GPIO_19_I_POS)
+#define GLB_REG2_GPIO_19_I_UMSK (~(((1U << GLB_REG2_GPIO_19_I_LEN) - 1) << GLB_REG2_GPIO_19_I_POS))
+#define GLB_REG2_GPIO_20_I GLB_REG2_GPIO_20_I
+#define GLB_REG2_GPIO_20_I_POS (20U)
+#define GLB_REG2_GPIO_20_I_LEN (1U)
+#define GLB_REG2_GPIO_20_I_MSK (((1U << GLB_REG2_GPIO_20_I_LEN) - 1) << GLB_REG2_GPIO_20_I_POS)
+#define GLB_REG2_GPIO_20_I_UMSK (~(((1U << GLB_REG2_GPIO_20_I_LEN) - 1) << GLB_REG2_GPIO_20_I_POS))
+#define GLB_REG2_GPIO_21_I GLB_REG2_GPIO_21_I
+#define GLB_REG2_GPIO_21_I_POS (21U)
+#define GLB_REG2_GPIO_21_I_LEN (1U)
+#define GLB_REG2_GPIO_21_I_MSK (((1U << GLB_REG2_GPIO_21_I_LEN) - 1) << GLB_REG2_GPIO_21_I_POS)
+#define GLB_REG2_GPIO_21_I_UMSK (~(((1U << GLB_REG2_GPIO_21_I_LEN) - 1) << GLB_REG2_GPIO_21_I_POS))
+#define GLB_REG2_GPIO_22_I GLB_REG2_GPIO_22_I
+#define GLB_REG2_GPIO_22_I_POS (22U)
+#define GLB_REG2_GPIO_22_I_LEN (1U)
+#define GLB_REG2_GPIO_22_I_MSK (((1U << GLB_REG2_GPIO_22_I_LEN) - 1) << GLB_REG2_GPIO_22_I_POS)
+#define GLB_REG2_GPIO_22_I_UMSK (~(((1U << GLB_REG2_GPIO_22_I_LEN) - 1) << GLB_REG2_GPIO_22_I_POS))
+#define GLB_REG2_GPIO_23_I GLB_REG2_GPIO_23_I
+#define GLB_REG2_GPIO_23_I_POS (23U)
+#define GLB_REG2_GPIO_23_I_LEN (1U)
+#define GLB_REG2_GPIO_23_I_MSK (((1U << GLB_REG2_GPIO_23_I_LEN) - 1) << GLB_REG2_GPIO_23_I_POS)
+#define GLB_REG2_GPIO_23_I_UMSK (~(((1U << GLB_REG2_GPIO_23_I_LEN) - 1) << GLB_REG2_GPIO_23_I_POS))
+#define GLB_REG2_GPIO_24_I GLB_REG2_GPIO_24_I
+#define GLB_REG2_GPIO_24_I_POS (24U)
+#define GLB_REG2_GPIO_24_I_LEN (1U)
+#define GLB_REG2_GPIO_24_I_MSK (((1U << GLB_REG2_GPIO_24_I_LEN) - 1) << GLB_REG2_GPIO_24_I_POS)
+#define GLB_REG2_GPIO_24_I_UMSK (~(((1U << GLB_REG2_GPIO_24_I_LEN) - 1) << GLB_REG2_GPIO_24_I_POS))
+#define GLB_REG2_GPIO_25_I GLB_REG2_GPIO_25_I
+#define GLB_REG2_GPIO_25_I_POS (25U)
+#define GLB_REG2_GPIO_25_I_LEN (1U)
+#define GLB_REG2_GPIO_25_I_MSK (((1U << GLB_REG2_GPIO_25_I_LEN) - 1) << GLB_REG2_GPIO_25_I_POS)
+#define GLB_REG2_GPIO_25_I_UMSK (~(((1U << GLB_REG2_GPIO_25_I_LEN) - 1) << GLB_REG2_GPIO_25_I_POS))
+#define GLB_REG2_GPIO_26_I GLB_REG2_GPIO_26_I
+#define GLB_REG2_GPIO_26_I_POS (26U)
+#define GLB_REG2_GPIO_26_I_LEN (1U)
+#define GLB_REG2_GPIO_26_I_MSK (((1U << GLB_REG2_GPIO_26_I_LEN) - 1) << GLB_REG2_GPIO_26_I_POS)
+#define GLB_REG2_GPIO_26_I_UMSK (~(((1U << GLB_REG2_GPIO_26_I_LEN) - 1) << GLB_REG2_GPIO_26_I_POS))
+#define GLB_REG2_GPIO_27_I GLB_REG2_GPIO_27_I
+#define GLB_REG2_GPIO_27_I_POS (27U)
+#define GLB_REG2_GPIO_27_I_LEN (1U)
+#define GLB_REG2_GPIO_27_I_MSK (((1U << GLB_REG2_GPIO_27_I_LEN) - 1) << GLB_REG2_GPIO_27_I_POS)
+#define GLB_REG2_GPIO_27_I_UMSK (~(((1U << GLB_REG2_GPIO_27_I_LEN) - 1) << GLB_REG2_GPIO_27_I_POS))
+#define GLB_REG2_GPIO_28_I GLB_REG2_GPIO_28_I
+#define GLB_REG2_GPIO_28_I_POS (28U)
+#define GLB_REG2_GPIO_28_I_LEN (1U)
+#define GLB_REG2_GPIO_28_I_MSK (((1U << GLB_REG2_GPIO_28_I_LEN) - 1) << GLB_REG2_GPIO_28_I_POS)
+#define GLB_REG2_GPIO_28_I_UMSK (~(((1U << GLB_REG2_GPIO_28_I_LEN) - 1) << GLB_REG2_GPIO_28_I_POS))
+#define GLB_REG2_GPIO_29_I GLB_REG2_GPIO_29_I
+#define GLB_REG2_GPIO_29_I_POS (29U)
+#define GLB_REG2_GPIO_29_I_LEN (1U)
+#define GLB_REG2_GPIO_29_I_MSK (((1U << GLB_REG2_GPIO_29_I_LEN) - 1) << GLB_REG2_GPIO_29_I_POS)
+#define GLB_REG2_GPIO_29_I_UMSK (~(((1U << GLB_REG2_GPIO_29_I_LEN) - 1) << GLB_REG2_GPIO_29_I_POS))
+#define GLB_REG2_GPIO_30_I GLB_REG2_GPIO_30_I
+#define GLB_REG2_GPIO_30_I_POS (30U)
+#define GLB_REG2_GPIO_30_I_LEN (1U)
+#define GLB_REG2_GPIO_30_I_MSK (((1U << GLB_REG2_GPIO_30_I_LEN) - 1) << GLB_REG2_GPIO_30_I_POS)
+#define GLB_REG2_GPIO_30_I_UMSK (~(((1U << GLB_REG2_GPIO_30_I_LEN) - 1) << GLB_REG2_GPIO_30_I_POS))
+#define GLB_REG2_GPIO_31_I GLB_REG2_GPIO_31_I
+#define GLB_REG2_GPIO_31_I_POS (31U)
+#define GLB_REG2_GPIO_31_I_LEN (1U)
+#define GLB_REG2_GPIO_31_I_MSK (((1U << GLB_REG2_GPIO_31_I_LEN) - 1) << GLB_REG2_GPIO_31_I_POS)
+#define GLB_REG2_GPIO_31_I_UMSK (~(((1U << GLB_REG2_GPIO_31_I_LEN) - 1) << GLB_REG2_GPIO_31_I_POS))
+
+/* 0xAC8 : gpio_cfg129 */
+#define GLB_GPIO_CFG129_OFFSET (0xAC8)
+#define GLB_REG2_GPIO_32_I GLB_REG2_GPIO_32_I
+#define GLB_REG2_GPIO_32_I_POS (0U)
+#define GLB_REG2_GPIO_32_I_LEN (1U)
+#define GLB_REG2_GPIO_32_I_MSK (((1U << GLB_REG2_GPIO_32_I_LEN) - 1) << GLB_REG2_GPIO_32_I_POS)
+#define GLB_REG2_GPIO_32_I_UMSK (~(((1U << GLB_REG2_GPIO_32_I_LEN) - 1) << GLB_REG2_GPIO_32_I_POS))
+#define GLB_REG2_GPIO_33_I GLB_REG2_GPIO_33_I
+#define GLB_REG2_GPIO_33_I_POS (1U)
+#define GLB_REG2_GPIO_33_I_LEN (1U)
+#define GLB_REG2_GPIO_33_I_MSK (((1U << GLB_REG2_GPIO_33_I_LEN) - 1) << GLB_REG2_GPIO_33_I_POS)
+#define GLB_REG2_GPIO_33_I_UMSK (~(((1U << GLB_REG2_GPIO_33_I_LEN) - 1) << GLB_REG2_GPIO_33_I_POS))
+#define GLB_REG2_GPIO_34_I GLB_REG2_GPIO_34_I
+#define GLB_REG2_GPIO_34_I_POS (2U)
+#define GLB_REG2_GPIO_34_I_LEN (1U)
+#define GLB_REG2_GPIO_34_I_MSK (((1U << GLB_REG2_GPIO_34_I_LEN) - 1) << GLB_REG2_GPIO_34_I_POS)
+#define GLB_REG2_GPIO_34_I_UMSK (~(((1U << GLB_REG2_GPIO_34_I_LEN) - 1) << GLB_REG2_GPIO_34_I_POS))
+#define GLB_REG2_GPIO_35_I GLB_REG2_GPIO_35_I
+#define GLB_REG2_GPIO_35_I_POS (3U)
+#define GLB_REG2_GPIO_35_I_LEN (1U)
+#define GLB_REG2_GPIO_35_I_MSK (((1U << GLB_REG2_GPIO_35_I_LEN) - 1) << GLB_REG2_GPIO_35_I_POS)
+#define GLB_REG2_GPIO_35_I_UMSK (~(((1U << GLB_REG2_GPIO_35_I_LEN) - 1) << GLB_REG2_GPIO_35_I_POS))
+#define GLB_REG2_GPIO_36_I GLB_REG2_GPIO_36_I
+#define GLB_REG2_GPIO_36_I_POS (4U)
+#define GLB_REG2_GPIO_36_I_LEN (1U)
+#define GLB_REG2_GPIO_36_I_MSK (((1U << GLB_REG2_GPIO_36_I_LEN) - 1) << GLB_REG2_GPIO_36_I_POS)
+#define GLB_REG2_GPIO_36_I_UMSK (~(((1U << GLB_REG2_GPIO_36_I_LEN) - 1) << GLB_REG2_GPIO_36_I_POS))
+#define GLB_REG2_GPIO_37_I GLB_REG2_GPIO_37_I
+#define GLB_REG2_GPIO_37_I_POS (5U)
+#define GLB_REG2_GPIO_37_I_LEN (1U)
+#define GLB_REG2_GPIO_37_I_MSK (((1U << GLB_REG2_GPIO_37_I_LEN) - 1) << GLB_REG2_GPIO_37_I_POS)
+#define GLB_REG2_GPIO_37_I_UMSK (~(((1U << GLB_REG2_GPIO_37_I_LEN) - 1) << GLB_REG2_GPIO_37_I_POS))
+#define GLB_REG2_GPIO_38_I GLB_REG2_GPIO_38_I
+#define GLB_REG2_GPIO_38_I_POS (6U)
+#define GLB_REG2_GPIO_38_I_LEN (1U)
+#define GLB_REG2_GPIO_38_I_MSK (((1U << GLB_REG2_GPIO_38_I_LEN) - 1) << GLB_REG2_GPIO_38_I_POS)
+#define GLB_REG2_GPIO_38_I_UMSK (~(((1U << GLB_REG2_GPIO_38_I_LEN) - 1) << GLB_REG2_GPIO_38_I_POS))
+#define GLB_REG2_GPIO_39_I GLB_REG2_GPIO_39_I
+#define GLB_REG2_GPIO_39_I_POS (7U)
+#define GLB_REG2_GPIO_39_I_LEN (1U)
+#define GLB_REG2_GPIO_39_I_MSK (((1U << GLB_REG2_GPIO_39_I_LEN) - 1) << GLB_REG2_GPIO_39_I_POS)
+#define GLB_REG2_GPIO_39_I_UMSK (~(((1U << GLB_REG2_GPIO_39_I_LEN) - 1) << GLB_REG2_GPIO_39_I_POS))
+#define GLB_REG2_GPIO_40_I GLB_REG2_GPIO_40_I
+#define GLB_REG2_GPIO_40_I_POS (8U)
+#define GLB_REG2_GPIO_40_I_LEN (1U)
+#define GLB_REG2_GPIO_40_I_MSK (((1U << GLB_REG2_GPIO_40_I_LEN) - 1) << GLB_REG2_GPIO_40_I_POS)
+#define GLB_REG2_GPIO_40_I_UMSK (~(((1U << GLB_REG2_GPIO_40_I_LEN) - 1) << GLB_REG2_GPIO_40_I_POS))
+#define GLB_REG2_GPIO_41_I GLB_REG2_GPIO_41_I
+#define GLB_REG2_GPIO_41_I_POS (9U)
+#define GLB_REG2_GPIO_41_I_LEN (1U)
+#define GLB_REG2_GPIO_41_I_MSK (((1U << GLB_REG2_GPIO_41_I_LEN) - 1) << GLB_REG2_GPIO_41_I_POS)
+#define GLB_REG2_GPIO_41_I_UMSK (~(((1U << GLB_REG2_GPIO_41_I_LEN) - 1) << GLB_REG2_GPIO_41_I_POS))
+#define GLB_REG2_GPIO_42_I GLB_REG2_GPIO_42_I
+#define GLB_REG2_GPIO_42_I_POS (10U)
+#define GLB_REG2_GPIO_42_I_LEN (1U)
+#define GLB_REG2_GPIO_42_I_MSK (((1U << GLB_REG2_GPIO_42_I_LEN) - 1) << GLB_REG2_GPIO_42_I_POS)
+#define GLB_REG2_GPIO_42_I_UMSK (~(((1U << GLB_REG2_GPIO_42_I_LEN) - 1) << GLB_REG2_GPIO_42_I_POS))
+#define GLB_REG2_GPIO_43_I GLB_REG2_GPIO_43_I
+#define GLB_REG2_GPIO_43_I_POS (11U)
+#define GLB_REG2_GPIO_43_I_LEN (1U)
+#define GLB_REG2_GPIO_43_I_MSK (((1U << GLB_REG2_GPIO_43_I_LEN) - 1) << GLB_REG2_GPIO_43_I_POS)
+#define GLB_REG2_GPIO_43_I_UMSK (~(((1U << GLB_REG2_GPIO_43_I_LEN) - 1) << GLB_REG2_GPIO_43_I_POS))
+#define GLB_REG2_GPIO_44_I GLB_REG2_GPIO_44_I
+#define GLB_REG2_GPIO_44_I_POS (12U)
+#define GLB_REG2_GPIO_44_I_LEN (1U)
+#define GLB_REG2_GPIO_44_I_MSK (((1U << GLB_REG2_GPIO_44_I_LEN) - 1) << GLB_REG2_GPIO_44_I_POS)
+#define GLB_REG2_GPIO_44_I_UMSK (~(((1U << GLB_REG2_GPIO_44_I_LEN) - 1) << GLB_REG2_GPIO_44_I_POS))
+#define GLB_REG2_GPIO_45_I GLB_REG2_GPIO_45_I
+#define GLB_REG2_GPIO_45_I_POS (13U)
+#define GLB_REG2_GPIO_45_I_LEN (1U)
+#define GLB_REG2_GPIO_45_I_MSK (((1U << GLB_REG2_GPIO_45_I_LEN) - 1) << GLB_REG2_GPIO_45_I_POS)
+#define GLB_REG2_GPIO_45_I_UMSK (~(((1U << GLB_REG2_GPIO_45_I_LEN) - 1) << GLB_REG2_GPIO_45_I_POS))
+
+/* 0xAE4 : gpio_cfg136 */
+#define GLB_GPIO_CFG136_OFFSET (0xAE4)
+#define GLB_REG2_GPIO_0_O GLB_REG2_GPIO_0_O
+#define GLB_REG2_GPIO_0_O_POS (0U)
+#define GLB_REG2_GPIO_0_O_LEN (1U)
+#define GLB_REG2_GPIO_0_O_MSK (((1U << GLB_REG2_GPIO_0_O_LEN) - 1) << GLB_REG2_GPIO_0_O_POS)
+#define GLB_REG2_GPIO_0_O_UMSK (~(((1U << GLB_REG2_GPIO_0_O_LEN) - 1) << GLB_REG2_GPIO_0_O_POS))
+#define GLB_REG2_GPIO_1_O GLB_REG2_GPIO_1_O
+#define GLB_REG2_GPIO_1_O_POS (1U)
+#define GLB_REG2_GPIO_1_O_LEN (1U)
+#define GLB_REG2_GPIO_1_O_MSK (((1U << GLB_REG2_GPIO_1_O_LEN) - 1) << GLB_REG2_GPIO_1_O_POS)
+#define GLB_REG2_GPIO_1_O_UMSK (~(((1U << GLB_REG2_GPIO_1_O_LEN) - 1) << GLB_REG2_GPIO_1_O_POS))
+#define GLB_REG2_GPIO_2_O GLB_REG2_GPIO_2_O
+#define GLB_REG2_GPIO_2_O_POS (2U)
+#define GLB_REG2_GPIO_2_O_LEN (1U)
+#define GLB_REG2_GPIO_2_O_MSK (((1U << GLB_REG2_GPIO_2_O_LEN) - 1) << GLB_REG2_GPIO_2_O_POS)
+#define GLB_REG2_GPIO_2_O_UMSK (~(((1U << GLB_REG2_GPIO_2_O_LEN) - 1) << GLB_REG2_GPIO_2_O_POS))
+#define GLB_REG2_GPIO_3_O GLB_REG2_GPIO_3_O
+#define GLB_REG2_GPIO_3_O_POS (3U)
+#define GLB_REG2_GPIO_3_O_LEN (1U)
+#define GLB_REG2_GPIO_3_O_MSK (((1U << GLB_REG2_GPIO_3_O_LEN) - 1) << GLB_REG2_GPIO_3_O_POS)
+#define GLB_REG2_GPIO_3_O_UMSK (~(((1U << GLB_REG2_GPIO_3_O_LEN) - 1) << GLB_REG2_GPIO_3_O_POS))
+#define GLB_REG2_GPIO_4_O GLB_REG2_GPIO_4_O
+#define GLB_REG2_GPIO_4_O_POS (4U)
+#define GLB_REG2_GPIO_4_O_LEN (1U)
+#define GLB_REG2_GPIO_4_O_MSK (((1U << GLB_REG2_GPIO_4_O_LEN) - 1) << GLB_REG2_GPIO_4_O_POS)
+#define GLB_REG2_GPIO_4_O_UMSK (~(((1U << GLB_REG2_GPIO_4_O_LEN) - 1) << GLB_REG2_GPIO_4_O_POS))
+#define GLB_REG2_GPIO_5_O GLB_REG2_GPIO_5_O
+#define GLB_REG2_GPIO_5_O_POS (5U)
+#define GLB_REG2_GPIO_5_O_LEN (1U)
+#define GLB_REG2_GPIO_5_O_MSK (((1U << GLB_REG2_GPIO_5_O_LEN) - 1) << GLB_REG2_GPIO_5_O_POS)
+#define GLB_REG2_GPIO_5_O_UMSK (~(((1U << GLB_REG2_GPIO_5_O_LEN) - 1) << GLB_REG2_GPIO_5_O_POS))
+#define GLB_REG2_GPIO_6_O GLB_REG2_GPIO_6_O
+#define GLB_REG2_GPIO_6_O_POS (6U)
+#define GLB_REG2_GPIO_6_O_LEN (1U)
+#define GLB_REG2_GPIO_6_O_MSK (((1U << GLB_REG2_GPIO_6_O_LEN) - 1) << GLB_REG2_GPIO_6_O_POS)
+#define GLB_REG2_GPIO_6_O_UMSK (~(((1U << GLB_REG2_GPIO_6_O_LEN) - 1) << GLB_REG2_GPIO_6_O_POS))
+#define GLB_REG2_GPIO_7_O GLB_REG2_GPIO_7_O
+#define GLB_REG2_GPIO_7_O_POS (7U)
+#define GLB_REG2_GPIO_7_O_LEN (1U)
+#define GLB_REG2_GPIO_7_O_MSK (((1U << GLB_REG2_GPIO_7_O_LEN) - 1) << GLB_REG2_GPIO_7_O_POS)
+#define GLB_REG2_GPIO_7_O_UMSK (~(((1U << GLB_REG2_GPIO_7_O_LEN) - 1) << GLB_REG2_GPIO_7_O_POS))
+#define GLB_REG2_GPIO_8_O GLB_REG2_GPIO_8_O
+#define GLB_REG2_GPIO_8_O_POS (8U)
+#define GLB_REG2_GPIO_8_O_LEN (1U)
+#define GLB_REG2_GPIO_8_O_MSK (((1U << GLB_REG2_GPIO_8_O_LEN) - 1) << GLB_REG2_GPIO_8_O_POS)
+#define GLB_REG2_GPIO_8_O_UMSK (~(((1U << GLB_REG2_GPIO_8_O_LEN) - 1) << GLB_REG2_GPIO_8_O_POS))
+#define GLB_REG2_GPIO_9_O GLB_REG2_GPIO_9_O
+#define GLB_REG2_GPIO_9_O_POS (9U)
+#define GLB_REG2_GPIO_9_O_LEN (1U)
+#define GLB_REG2_GPIO_9_O_MSK (((1U << GLB_REG2_GPIO_9_O_LEN) - 1) << GLB_REG2_GPIO_9_O_POS)
+#define GLB_REG2_GPIO_9_O_UMSK (~(((1U << GLB_REG2_GPIO_9_O_LEN) - 1) << GLB_REG2_GPIO_9_O_POS))
+#define GLB_REG2_GPIO_10_O GLB_REG2_GPIO_10_O
+#define GLB_REG2_GPIO_10_O_POS (10U)
+#define GLB_REG2_GPIO_10_O_LEN (1U)
+#define GLB_REG2_GPIO_10_O_MSK (((1U << GLB_REG2_GPIO_10_O_LEN) - 1) << GLB_REG2_GPIO_10_O_POS)
+#define GLB_REG2_GPIO_10_O_UMSK (~(((1U << GLB_REG2_GPIO_10_O_LEN) - 1) << GLB_REG2_GPIO_10_O_POS))
+#define GLB_REG2_GPIO_11_O GLB_REG2_GPIO_11_O
+#define GLB_REG2_GPIO_11_O_POS (11U)
+#define GLB_REG2_GPIO_11_O_LEN (1U)
+#define GLB_REG2_GPIO_11_O_MSK (((1U << GLB_REG2_GPIO_11_O_LEN) - 1) << GLB_REG2_GPIO_11_O_POS)
+#define GLB_REG2_GPIO_11_O_UMSK (~(((1U << GLB_REG2_GPIO_11_O_LEN) - 1) << GLB_REG2_GPIO_11_O_POS))
+#define GLB_REG2_GPIO_12_O GLB_REG2_GPIO_12_O
+#define GLB_REG2_GPIO_12_O_POS (12U)
+#define GLB_REG2_GPIO_12_O_LEN (1U)
+#define GLB_REG2_GPIO_12_O_MSK (((1U << GLB_REG2_GPIO_12_O_LEN) - 1) << GLB_REG2_GPIO_12_O_POS)
+#define GLB_REG2_GPIO_12_O_UMSK (~(((1U << GLB_REG2_GPIO_12_O_LEN) - 1) << GLB_REG2_GPIO_12_O_POS))
+#define GLB_REG2_GPIO_13_O GLB_REG2_GPIO_13_O
+#define GLB_REG2_GPIO_13_O_POS (13U)
+#define GLB_REG2_GPIO_13_O_LEN (1U)
+#define GLB_REG2_GPIO_13_O_MSK (((1U << GLB_REG2_GPIO_13_O_LEN) - 1) << GLB_REG2_GPIO_13_O_POS)
+#define GLB_REG2_GPIO_13_O_UMSK (~(((1U << GLB_REG2_GPIO_13_O_LEN) - 1) << GLB_REG2_GPIO_13_O_POS))
+#define GLB_REG2_GPIO_14_O GLB_REG2_GPIO_14_O
+#define GLB_REG2_GPIO_14_O_POS (14U)
+#define GLB_REG2_GPIO_14_O_LEN (1U)
+#define GLB_REG2_GPIO_14_O_MSK (((1U << GLB_REG2_GPIO_14_O_LEN) - 1) << GLB_REG2_GPIO_14_O_POS)
+#define GLB_REG2_GPIO_14_O_UMSK (~(((1U << GLB_REG2_GPIO_14_O_LEN) - 1) << GLB_REG2_GPIO_14_O_POS))
+#define GLB_REG2_GPIO_15_O GLB_REG2_GPIO_15_O
+#define GLB_REG2_GPIO_15_O_POS (15U)
+#define GLB_REG2_GPIO_15_O_LEN (1U)
+#define GLB_REG2_GPIO_15_O_MSK (((1U << GLB_REG2_GPIO_15_O_LEN) - 1) << GLB_REG2_GPIO_15_O_POS)
+#define GLB_REG2_GPIO_15_O_UMSK (~(((1U << GLB_REG2_GPIO_15_O_LEN) - 1) << GLB_REG2_GPIO_15_O_POS))
+#define GLB_REG2_GPIO_16_O GLB_REG2_GPIO_16_O
+#define GLB_REG2_GPIO_16_O_POS (16U)
+#define GLB_REG2_GPIO_16_O_LEN (1U)
+#define GLB_REG2_GPIO_16_O_MSK (((1U << GLB_REG2_GPIO_16_O_LEN) - 1) << GLB_REG2_GPIO_16_O_POS)
+#define GLB_REG2_GPIO_16_O_UMSK (~(((1U << GLB_REG2_GPIO_16_O_LEN) - 1) << GLB_REG2_GPIO_16_O_POS))
+#define GLB_REG2_GPIO_17_O GLB_REG2_GPIO_17_O
+#define GLB_REG2_GPIO_17_O_POS (17U)
+#define GLB_REG2_GPIO_17_O_LEN (1U)
+#define GLB_REG2_GPIO_17_O_MSK (((1U << GLB_REG2_GPIO_17_O_LEN) - 1) << GLB_REG2_GPIO_17_O_POS)
+#define GLB_REG2_GPIO_17_O_UMSK (~(((1U << GLB_REG2_GPIO_17_O_LEN) - 1) << GLB_REG2_GPIO_17_O_POS))
+#define GLB_REG2_GPIO_18_O GLB_REG2_GPIO_18_O
+#define GLB_REG2_GPIO_18_O_POS (18U)
+#define GLB_REG2_GPIO_18_O_LEN (1U)
+#define GLB_REG2_GPIO_18_O_MSK (((1U << GLB_REG2_GPIO_18_O_LEN) - 1) << GLB_REG2_GPIO_18_O_POS)
+#define GLB_REG2_GPIO_18_O_UMSK (~(((1U << GLB_REG2_GPIO_18_O_LEN) - 1) << GLB_REG2_GPIO_18_O_POS))
+#define GLB_REG2_GPIO_19_O GLB_REG2_GPIO_19_O
+#define GLB_REG2_GPIO_19_O_POS (19U)
+#define GLB_REG2_GPIO_19_O_LEN (1U)
+#define GLB_REG2_GPIO_19_O_MSK (((1U << GLB_REG2_GPIO_19_O_LEN) - 1) << GLB_REG2_GPIO_19_O_POS)
+#define GLB_REG2_GPIO_19_O_UMSK (~(((1U << GLB_REG2_GPIO_19_O_LEN) - 1) << GLB_REG2_GPIO_19_O_POS))
+#define GLB_REG2_GPIO_20_O GLB_REG2_GPIO_20_O
+#define GLB_REG2_GPIO_20_O_POS (20U)
+#define GLB_REG2_GPIO_20_O_LEN (1U)
+#define GLB_REG2_GPIO_20_O_MSK (((1U << GLB_REG2_GPIO_20_O_LEN) - 1) << GLB_REG2_GPIO_20_O_POS)
+#define GLB_REG2_GPIO_20_O_UMSK (~(((1U << GLB_REG2_GPIO_20_O_LEN) - 1) << GLB_REG2_GPIO_20_O_POS))
+#define GLB_REG2_GPIO_21_O GLB_REG2_GPIO_21_O
+#define GLB_REG2_GPIO_21_O_POS (21U)
+#define GLB_REG2_GPIO_21_O_LEN (1U)
+#define GLB_REG2_GPIO_21_O_MSK (((1U << GLB_REG2_GPIO_21_O_LEN) - 1) << GLB_REG2_GPIO_21_O_POS)
+#define GLB_REG2_GPIO_21_O_UMSK (~(((1U << GLB_REG2_GPIO_21_O_LEN) - 1) << GLB_REG2_GPIO_21_O_POS))
+#define GLB_REG2_GPIO_22_O GLB_REG2_GPIO_22_O
+#define GLB_REG2_GPIO_22_O_POS (22U)
+#define GLB_REG2_GPIO_22_O_LEN (1U)
+#define GLB_REG2_GPIO_22_O_MSK (((1U << GLB_REG2_GPIO_22_O_LEN) - 1) << GLB_REG2_GPIO_22_O_POS)
+#define GLB_REG2_GPIO_22_O_UMSK (~(((1U << GLB_REG2_GPIO_22_O_LEN) - 1) << GLB_REG2_GPIO_22_O_POS))
+#define GLB_REG2_GPIO_23_O GLB_REG2_GPIO_23_O
+#define GLB_REG2_GPIO_23_O_POS (23U)
+#define GLB_REG2_GPIO_23_O_LEN (1U)
+#define GLB_REG2_GPIO_23_O_MSK (((1U << GLB_REG2_GPIO_23_O_LEN) - 1) << GLB_REG2_GPIO_23_O_POS)
+#define GLB_REG2_GPIO_23_O_UMSK (~(((1U << GLB_REG2_GPIO_23_O_LEN) - 1) << GLB_REG2_GPIO_23_O_POS))
+#define GLB_REG2_GPIO_24_O GLB_REG2_GPIO_24_O
+#define GLB_REG2_GPIO_24_O_POS (24U)
+#define GLB_REG2_GPIO_24_O_LEN (1U)
+#define GLB_REG2_GPIO_24_O_MSK (((1U << GLB_REG2_GPIO_24_O_LEN) - 1) << GLB_REG2_GPIO_24_O_POS)
+#define GLB_REG2_GPIO_24_O_UMSK (~(((1U << GLB_REG2_GPIO_24_O_LEN) - 1) << GLB_REG2_GPIO_24_O_POS))
+#define GLB_REG2_GPIO_25_O GLB_REG2_GPIO_25_O
+#define GLB_REG2_GPIO_25_O_POS (25U)
+#define GLB_REG2_GPIO_25_O_LEN (1U)
+#define GLB_REG2_GPIO_25_O_MSK (((1U << GLB_REG2_GPIO_25_O_LEN) - 1) << GLB_REG2_GPIO_25_O_POS)
+#define GLB_REG2_GPIO_25_O_UMSK (~(((1U << GLB_REG2_GPIO_25_O_LEN) - 1) << GLB_REG2_GPIO_25_O_POS))
+#define GLB_REG2_GPIO_26_O GLB_REG2_GPIO_26_O
+#define GLB_REG2_GPIO_26_O_POS (26U)
+#define GLB_REG2_GPIO_26_O_LEN (1U)
+#define GLB_REG2_GPIO_26_O_MSK (((1U << GLB_REG2_GPIO_26_O_LEN) - 1) << GLB_REG2_GPIO_26_O_POS)
+#define GLB_REG2_GPIO_26_O_UMSK (~(((1U << GLB_REG2_GPIO_26_O_LEN) - 1) << GLB_REG2_GPIO_26_O_POS))
+#define GLB_REG2_GPIO_27_O GLB_REG2_GPIO_27_O
+#define GLB_REG2_GPIO_27_O_POS (27U)
+#define GLB_REG2_GPIO_27_O_LEN (1U)
+#define GLB_REG2_GPIO_27_O_MSK (((1U << GLB_REG2_GPIO_27_O_LEN) - 1) << GLB_REG2_GPIO_27_O_POS)
+#define GLB_REG2_GPIO_27_O_UMSK (~(((1U << GLB_REG2_GPIO_27_O_LEN) - 1) << GLB_REG2_GPIO_27_O_POS))
+#define GLB_REG2_GPIO_28_O GLB_REG2_GPIO_28_O
+#define GLB_REG2_GPIO_28_O_POS (28U)
+#define GLB_REG2_GPIO_28_O_LEN (1U)
+#define GLB_REG2_GPIO_28_O_MSK (((1U << GLB_REG2_GPIO_28_O_LEN) - 1) << GLB_REG2_GPIO_28_O_POS)
+#define GLB_REG2_GPIO_28_O_UMSK (~(((1U << GLB_REG2_GPIO_28_O_LEN) - 1) << GLB_REG2_GPIO_28_O_POS))
+#define GLB_REG2_GPIO_29_O GLB_REG2_GPIO_29_O
+#define GLB_REG2_GPIO_29_O_POS (29U)
+#define GLB_REG2_GPIO_29_O_LEN (1U)
+#define GLB_REG2_GPIO_29_O_MSK (((1U << GLB_REG2_GPIO_29_O_LEN) - 1) << GLB_REG2_GPIO_29_O_POS)
+#define GLB_REG2_GPIO_29_O_UMSK (~(((1U << GLB_REG2_GPIO_29_O_LEN) - 1) << GLB_REG2_GPIO_29_O_POS))
+#define GLB_REG2_GPIO_30_O GLB_REG2_GPIO_30_O
+#define GLB_REG2_GPIO_30_O_POS (30U)
+#define GLB_REG2_GPIO_30_O_LEN (1U)
+#define GLB_REG2_GPIO_30_O_MSK (((1U << GLB_REG2_GPIO_30_O_LEN) - 1) << GLB_REG2_GPIO_30_O_POS)
+#define GLB_REG2_GPIO_30_O_UMSK (~(((1U << GLB_REG2_GPIO_30_O_LEN) - 1) << GLB_REG2_GPIO_30_O_POS))
+#define GLB_REG2_GPIO_31_O GLB_REG2_GPIO_31_O
+#define GLB_REG2_GPIO_31_O_POS (31U)
+#define GLB_REG2_GPIO_31_O_LEN (1U)
+#define GLB_REG2_GPIO_31_O_MSK (((1U << GLB_REG2_GPIO_31_O_LEN) - 1) << GLB_REG2_GPIO_31_O_POS)
+#define GLB_REG2_GPIO_31_O_UMSK (~(((1U << GLB_REG2_GPIO_31_O_LEN) - 1) << GLB_REG2_GPIO_31_O_POS))
+
+/* 0xAE8 : gpio_cfg137 */
+#define GLB_GPIO_CFG137_OFFSET (0xAE8)
+#define GLB_REG2_GPIO_32_O GLB_REG2_GPIO_32_O
+#define GLB_REG2_GPIO_32_O_POS (0U)
+#define GLB_REG2_GPIO_32_O_LEN (1U)
+#define GLB_REG2_GPIO_32_O_MSK (((1U << GLB_REG2_GPIO_32_O_LEN) - 1) << GLB_REG2_GPIO_32_O_POS)
+#define GLB_REG2_GPIO_32_O_UMSK (~(((1U << GLB_REG2_GPIO_32_O_LEN) - 1) << GLB_REG2_GPIO_32_O_POS))
+#define GLB_REG2_GPIO_33_O GLB_REG2_GPIO_33_O
+#define GLB_REG2_GPIO_33_O_POS (1U)
+#define GLB_REG2_GPIO_33_O_LEN (1U)
+#define GLB_REG2_GPIO_33_O_MSK (((1U << GLB_REG2_GPIO_33_O_LEN) - 1) << GLB_REG2_GPIO_33_O_POS)
+#define GLB_REG2_GPIO_33_O_UMSK (~(((1U << GLB_REG2_GPIO_33_O_LEN) - 1) << GLB_REG2_GPIO_33_O_POS))
+#define GLB_REG2_GPIO_34_O GLB_REG2_GPIO_34_O
+#define GLB_REG2_GPIO_34_O_POS (2U)
+#define GLB_REG2_GPIO_34_O_LEN (1U)
+#define GLB_REG2_GPIO_34_O_MSK (((1U << GLB_REG2_GPIO_34_O_LEN) - 1) << GLB_REG2_GPIO_34_O_POS)
+#define GLB_REG2_GPIO_34_O_UMSK (~(((1U << GLB_REG2_GPIO_34_O_LEN) - 1) << GLB_REG2_GPIO_34_O_POS))
+#define GLB_REG2_GPIO_35_O GLB_REG2_GPIO_35_O
+#define GLB_REG2_GPIO_35_O_POS (3U)
+#define GLB_REG2_GPIO_35_O_LEN (1U)
+#define GLB_REG2_GPIO_35_O_MSK (((1U << GLB_REG2_GPIO_35_O_LEN) - 1) << GLB_REG2_GPIO_35_O_POS)
+#define GLB_REG2_GPIO_35_O_UMSK (~(((1U << GLB_REG2_GPIO_35_O_LEN) - 1) << GLB_REG2_GPIO_35_O_POS))
+#define GLB_REG2_GPIO_36_O GLB_REG2_GPIO_36_O
+#define GLB_REG2_GPIO_36_O_POS (4U)
+#define GLB_REG2_GPIO_36_O_LEN (1U)
+#define GLB_REG2_GPIO_36_O_MSK (((1U << GLB_REG2_GPIO_36_O_LEN) - 1) << GLB_REG2_GPIO_36_O_POS)
+#define GLB_REG2_GPIO_36_O_UMSK (~(((1U << GLB_REG2_GPIO_36_O_LEN) - 1) << GLB_REG2_GPIO_36_O_POS))
+#define GLB_REG2_GPIO_37_O GLB_REG2_GPIO_37_O
+#define GLB_REG2_GPIO_37_O_POS (5U)
+#define GLB_REG2_GPIO_37_O_LEN (1U)
+#define GLB_REG2_GPIO_37_O_MSK (((1U << GLB_REG2_GPIO_37_O_LEN) - 1) << GLB_REG2_GPIO_37_O_POS)
+#define GLB_REG2_GPIO_37_O_UMSK (~(((1U << GLB_REG2_GPIO_37_O_LEN) - 1) << GLB_REG2_GPIO_37_O_POS))
+#define GLB_REG2_GPIO_38_O GLB_REG2_GPIO_38_O
+#define GLB_REG2_GPIO_38_O_POS (6U)
+#define GLB_REG2_GPIO_38_O_LEN (1U)
+#define GLB_REG2_GPIO_38_O_MSK (((1U << GLB_REG2_GPIO_38_O_LEN) - 1) << GLB_REG2_GPIO_38_O_POS)
+#define GLB_REG2_GPIO_38_O_UMSK (~(((1U << GLB_REG2_GPIO_38_O_LEN) - 1) << GLB_REG2_GPIO_38_O_POS))
+#define GLB_REG2_GPIO_39_O GLB_REG2_GPIO_39_O
+#define GLB_REG2_GPIO_39_O_POS (7U)
+#define GLB_REG2_GPIO_39_O_LEN (1U)
+#define GLB_REG2_GPIO_39_O_MSK (((1U << GLB_REG2_GPIO_39_O_LEN) - 1) << GLB_REG2_GPIO_39_O_POS)
+#define GLB_REG2_GPIO_39_O_UMSK (~(((1U << GLB_REG2_GPIO_39_O_LEN) - 1) << GLB_REG2_GPIO_39_O_POS))
+#define GLB_REG2_GPIO_40_O GLB_REG2_GPIO_40_O
+#define GLB_REG2_GPIO_40_O_POS (8U)
+#define GLB_REG2_GPIO_40_O_LEN (1U)
+#define GLB_REG2_GPIO_40_O_MSK (((1U << GLB_REG2_GPIO_40_O_LEN) - 1) << GLB_REG2_GPIO_40_O_POS)
+#define GLB_REG2_GPIO_40_O_UMSK (~(((1U << GLB_REG2_GPIO_40_O_LEN) - 1) << GLB_REG2_GPIO_40_O_POS))
+#define GLB_REG2_GPIO_41_O GLB_REG2_GPIO_41_O
+#define GLB_REG2_GPIO_41_O_POS (9U)
+#define GLB_REG2_GPIO_41_O_LEN (1U)
+#define GLB_REG2_GPIO_41_O_MSK (((1U << GLB_REG2_GPIO_41_O_LEN) - 1) << GLB_REG2_GPIO_41_O_POS)
+#define GLB_REG2_GPIO_41_O_UMSK (~(((1U << GLB_REG2_GPIO_41_O_LEN) - 1) << GLB_REG2_GPIO_41_O_POS))
+#define GLB_REG2_GPIO_42_O GLB_REG2_GPIO_42_O
+#define GLB_REG2_GPIO_42_O_POS (10U)
+#define GLB_REG2_GPIO_42_O_LEN (1U)
+#define GLB_REG2_GPIO_42_O_MSK (((1U << GLB_REG2_GPIO_42_O_LEN) - 1) << GLB_REG2_GPIO_42_O_POS)
+#define GLB_REG2_GPIO_42_O_UMSK (~(((1U << GLB_REG2_GPIO_42_O_LEN) - 1) << GLB_REG2_GPIO_42_O_POS))
+#define GLB_REG2_GPIO_43_O GLB_REG2_GPIO_43_O
+#define GLB_REG2_GPIO_43_O_POS (11U)
+#define GLB_REG2_GPIO_43_O_LEN (1U)
+#define GLB_REG2_GPIO_43_O_MSK (((1U << GLB_REG2_GPIO_43_O_LEN) - 1) << GLB_REG2_GPIO_43_O_POS)
+#define GLB_REG2_GPIO_43_O_UMSK (~(((1U << GLB_REG2_GPIO_43_O_LEN) - 1) << GLB_REG2_GPIO_43_O_POS))
+#define GLB_REG2_GPIO_44_O GLB_REG2_GPIO_44_O
+#define GLB_REG2_GPIO_44_O_POS (12U)
+#define GLB_REG2_GPIO_44_O_LEN (1U)
+#define GLB_REG2_GPIO_44_O_MSK (((1U << GLB_REG2_GPIO_44_O_LEN) - 1) << GLB_REG2_GPIO_44_O_POS)
+#define GLB_REG2_GPIO_44_O_UMSK (~(((1U << GLB_REG2_GPIO_44_O_LEN) - 1) << GLB_REG2_GPIO_44_O_POS))
+#define GLB_REG2_GPIO_45_O GLB_REG2_GPIO_45_O
+#define GLB_REG2_GPIO_45_O_POS (13U)
+#define GLB_REG2_GPIO_45_O_LEN (1U)
+#define GLB_REG2_GPIO_45_O_MSK (((1U << GLB_REG2_GPIO_45_O_LEN) - 1) << GLB_REG2_GPIO_45_O_POS)
+#define GLB_REG2_GPIO_45_O_UMSK (~(((1U << GLB_REG2_GPIO_45_O_LEN) - 1) << GLB_REG2_GPIO_45_O_POS))
+
+/* 0xAEC : gpio_cfg138 */
+#define GLB_GPIO_CFG138_OFFSET (0xAEC)
+#define GLB_REG2_GPIO_0_SET GLB_REG2_GPIO_0_SET
+#define GLB_REG2_GPIO_0_SET_POS (0U)
+#define GLB_REG2_GPIO_0_SET_LEN (1U)
+#define GLB_REG2_GPIO_0_SET_MSK (((1U << GLB_REG2_GPIO_0_SET_LEN) - 1) << GLB_REG2_GPIO_0_SET_POS)
+#define GLB_REG2_GPIO_0_SET_UMSK (~(((1U << GLB_REG2_GPIO_0_SET_LEN) - 1) << GLB_REG2_GPIO_0_SET_POS))
+#define GLB_REG2_GPIO_1_SET GLB_REG2_GPIO_1_SET
+#define GLB_REG2_GPIO_1_SET_POS (1U)
+#define GLB_REG2_GPIO_1_SET_LEN (1U)
+#define GLB_REG2_GPIO_1_SET_MSK (((1U << GLB_REG2_GPIO_1_SET_LEN) - 1) << GLB_REG2_GPIO_1_SET_POS)
+#define GLB_REG2_GPIO_1_SET_UMSK (~(((1U << GLB_REG2_GPIO_1_SET_LEN) - 1) << GLB_REG2_GPIO_1_SET_POS))
+#define GLB_REG2_GPIO_2_SET GLB_REG2_GPIO_2_SET
+#define GLB_REG2_GPIO_2_SET_POS (2U)
+#define GLB_REG2_GPIO_2_SET_LEN (1U)
+#define GLB_REG2_GPIO_2_SET_MSK (((1U << GLB_REG2_GPIO_2_SET_LEN) - 1) << GLB_REG2_GPIO_2_SET_POS)
+#define GLB_REG2_GPIO_2_SET_UMSK (~(((1U << GLB_REG2_GPIO_2_SET_LEN) - 1) << GLB_REG2_GPIO_2_SET_POS))
+#define GLB_REG2_GPIO_3_SET GLB_REG2_GPIO_3_SET
+#define GLB_REG2_GPIO_3_SET_POS (3U)
+#define GLB_REG2_GPIO_3_SET_LEN (1U)
+#define GLB_REG2_GPIO_3_SET_MSK (((1U << GLB_REG2_GPIO_3_SET_LEN) - 1) << GLB_REG2_GPIO_3_SET_POS)
+#define GLB_REG2_GPIO_3_SET_UMSK (~(((1U << GLB_REG2_GPIO_3_SET_LEN) - 1) << GLB_REG2_GPIO_3_SET_POS))
+#define GLB_REG2_GPIO_4_SET GLB_REG2_GPIO_4_SET
+#define GLB_REG2_GPIO_4_SET_POS (4U)
+#define GLB_REG2_GPIO_4_SET_LEN (1U)
+#define GLB_REG2_GPIO_4_SET_MSK (((1U << GLB_REG2_GPIO_4_SET_LEN) - 1) << GLB_REG2_GPIO_4_SET_POS)
+#define GLB_REG2_GPIO_4_SET_UMSK (~(((1U << GLB_REG2_GPIO_4_SET_LEN) - 1) << GLB_REG2_GPIO_4_SET_POS))
+#define GLB_REG2_GPIO_5_SET GLB_REG2_GPIO_5_SET
+#define GLB_REG2_GPIO_5_SET_POS (5U)
+#define GLB_REG2_GPIO_5_SET_LEN (1U)
+#define GLB_REG2_GPIO_5_SET_MSK (((1U << GLB_REG2_GPIO_5_SET_LEN) - 1) << GLB_REG2_GPIO_5_SET_POS)
+#define GLB_REG2_GPIO_5_SET_UMSK (~(((1U << GLB_REG2_GPIO_5_SET_LEN) - 1) << GLB_REG2_GPIO_5_SET_POS))
+#define GLB_REG2_GPIO_6_SET GLB_REG2_GPIO_6_SET
+#define GLB_REG2_GPIO_6_SET_POS (6U)
+#define GLB_REG2_GPIO_6_SET_LEN (1U)
+#define GLB_REG2_GPIO_6_SET_MSK (((1U << GLB_REG2_GPIO_6_SET_LEN) - 1) << GLB_REG2_GPIO_6_SET_POS)
+#define GLB_REG2_GPIO_6_SET_UMSK (~(((1U << GLB_REG2_GPIO_6_SET_LEN) - 1) << GLB_REG2_GPIO_6_SET_POS))
+#define GLB_REG2_GPIO_7_SET GLB_REG2_GPIO_7_SET
+#define GLB_REG2_GPIO_7_SET_POS (7U)
+#define GLB_REG2_GPIO_7_SET_LEN (1U)
+#define GLB_REG2_GPIO_7_SET_MSK (((1U << GLB_REG2_GPIO_7_SET_LEN) - 1) << GLB_REG2_GPIO_7_SET_POS)
+#define GLB_REG2_GPIO_7_SET_UMSK (~(((1U << GLB_REG2_GPIO_7_SET_LEN) - 1) << GLB_REG2_GPIO_7_SET_POS))
+#define GLB_REG2_GPIO_8_SET GLB_REG2_GPIO_8_SET
+#define GLB_REG2_GPIO_8_SET_POS (8U)
+#define GLB_REG2_GPIO_8_SET_LEN (1U)
+#define GLB_REG2_GPIO_8_SET_MSK (((1U << GLB_REG2_GPIO_8_SET_LEN) - 1) << GLB_REG2_GPIO_8_SET_POS)
+#define GLB_REG2_GPIO_8_SET_UMSK (~(((1U << GLB_REG2_GPIO_8_SET_LEN) - 1) << GLB_REG2_GPIO_8_SET_POS))
+#define GLB_REG2_GPIO_9_SET GLB_REG2_GPIO_9_SET
+#define GLB_REG2_GPIO_9_SET_POS (9U)
+#define GLB_REG2_GPIO_9_SET_LEN (1U)
+#define GLB_REG2_GPIO_9_SET_MSK (((1U << GLB_REG2_GPIO_9_SET_LEN) - 1) << GLB_REG2_GPIO_9_SET_POS)
+#define GLB_REG2_GPIO_9_SET_UMSK (~(((1U << GLB_REG2_GPIO_9_SET_LEN) - 1) << GLB_REG2_GPIO_9_SET_POS))
+#define GLB_REG2_GPIO_10_SET GLB_REG2_GPIO_10_SET
+#define GLB_REG2_GPIO_10_SET_POS (10U)
+#define GLB_REG2_GPIO_10_SET_LEN (1U)
+#define GLB_REG2_GPIO_10_SET_MSK (((1U << GLB_REG2_GPIO_10_SET_LEN) - 1) << GLB_REG2_GPIO_10_SET_POS)
+#define GLB_REG2_GPIO_10_SET_UMSK (~(((1U << GLB_REG2_GPIO_10_SET_LEN) - 1) << GLB_REG2_GPIO_10_SET_POS))
+#define GLB_REG2_GPIO_11_SET GLB_REG2_GPIO_11_SET
+#define GLB_REG2_GPIO_11_SET_POS (11U)
+#define GLB_REG2_GPIO_11_SET_LEN (1U)
+#define GLB_REG2_GPIO_11_SET_MSK (((1U << GLB_REG2_GPIO_11_SET_LEN) - 1) << GLB_REG2_GPIO_11_SET_POS)
+#define GLB_REG2_GPIO_11_SET_UMSK (~(((1U << GLB_REG2_GPIO_11_SET_LEN) - 1) << GLB_REG2_GPIO_11_SET_POS))
+#define GLB_REG2_GPIO_12_SET GLB_REG2_GPIO_12_SET
+#define GLB_REG2_GPIO_12_SET_POS (12U)
+#define GLB_REG2_GPIO_12_SET_LEN (1U)
+#define GLB_REG2_GPIO_12_SET_MSK (((1U << GLB_REG2_GPIO_12_SET_LEN) - 1) << GLB_REG2_GPIO_12_SET_POS)
+#define GLB_REG2_GPIO_12_SET_UMSK (~(((1U << GLB_REG2_GPIO_12_SET_LEN) - 1) << GLB_REG2_GPIO_12_SET_POS))
+#define GLB_REG2_GPIO_13_SET GLB_REG2_GPIO_13_SET
+#define GLB_REG2_GPIO_13_SET_POS (13U)
+#define GLB_REG2_GPIO_13_SET_LEN (1U)
+#define GLB_REG2_GPIO_13_SET_MSK (((1U << GLB_REG2_GPIO_13_SET_LEN) - 1) << GLB_REG2_GPIO_13_SET_POS)
+#define GLB_REG2_GPIO_13_SET_UMSK (~(((1U << GLB_REG2_GPIO_13_SET_LEN) - 1) << GLB_REG2_GPIO_13_SET_POS))
+#define GLB_REG2_GPIO_14_SET GLB_REG2_GPIO_14_SET
+#define GLB_REG2_GPIO_14_SET_POS (14U)
+#define GLB_REG2_GPIO_14_SET_LEN (1U)
+#define GLB_REG2_GPIO_14_SET_MSK (((1U << GLB_REG2_GPIO_14_SET_LEN) - 1) << GLB_REG2_GPIO_14_SET_POS)
+#define GLB_REG2_GPIO_14_SET_UMSK (~(((1U << GLB_REG2_GPIO_14_SET_LEN) - 1) << GLB_REG2_GPIO_14_SET_POS))
+#define GLB_REG2_GPIO_15_SET GLB_REG2_GPIO_15_SET
+#define GLB_REG2_GPIO_15_SET_POS (15U)
+#define GLB_REG2_GPIO_15_SET_LEN (1U)
+#define GLB_REG2_GPIO_15_SET_MSK (((1U << GLB_REG2_GPIO_15_SET_LEN) - 1) << GLB_REG2_GPIO_15_SET_POS)
+#define GLB_REG2_GPIO_15_SET_UMSK (~(((1U << GLB_REG2_GPIO_15_SET_LEN) - 1) << GLB_REG2_GPIO_15_SET_POS))
+#define GLB_REG2_GPIO_16_SET GLB_REG2_GPIO_16_SET
+#define GLB_REG2_GPIO_16_SET_POS (16U)
+#define GLB_REG2_GPIO_16_SET_LEN (1U)
+#define GLB_REG2_GPIO_16_SET_MSK (((1U << GLB_REG2_GPIO_16_SET_LEN) - 1) << GLB_REG2_GPIO_16_SET_POS)
+#define GLB_REG2_GPIO_16_SET_UMSK (~(((1U << GLB_REG2_GPIO_16_SET_LEN) - 1) << GLB_REG2_GPIO_16_SET_POS))
+#define GLB_REG2_GPIO_17_SET GLB_REG2_GPIO_17_SET
+#define GLB_REG2_GPIO_17_SET_POS (17U)
+#define GLB_REG2_GPIO_17_SET_LEN (1U)
+#define GLB_REG2_GPIO_17_SET_MSK (((1U << GLB_REG2_GPIO_17_SET_LEN) - 1) << GLB_REG2_GPIO_17_SET_POS)
+#define GLB_REG2_GPIO_17_SET_UMSK (~(((1U << GLB_REG2_GPIO_17_SET_LEN) - 1) << GLB_REG2_GPIO_17_SET_POS))
+#define GLB_REG2_GPIO_18_SET GLB_REG2_GPIO_18_SET
+#define GLB_REG2_GPIO_18_SET_POS (18U)
+#define GLB_REG2_GPIO_18_SET_LEN (1U)
+#define GLB_REG2_GPIO_18_SET_MSK (((1U << GLB_REG2_GPIO_18_SET_LEN) - 1) << GLB_REG2_GPIO_18_SET_POS)
+#define GLB_REG2_GPIO_18_SET_UMSK (~(((1U << GLB_REG2_GPIO_18_SET_LEN) - 1) << GLB_REG2_GPIO_18_SET_POS))
+#define GLB_REG2_GPIO_19_SET GLB_REG2_GPIO_19_SET
+#define GLB_REG2_GPIO_19_SET_POS (19U)
+#define GLB_REG2_GPIO_19_SET_LEN (1U)
+#define GLB_REG2_GPIO_19_SET_MSK (((1U << GLB_REG2_GPIO_19_SET_LEN) - 1) << GLB_REG2_GPIO_19_SET_POS)
+#define GLB_REG2_GPIO_19_SET_UMSK (~(((1U << GLB_REG2_GPIO_19_SET_LEN) - 1) << GLB_REG2_GPIO_19_SET_POS))
+#define GLB_REG2_GPIO_20_SET GLB_REG2_GPIO_20_SET
+#define GLB_REG2_GPIO_20_SET_POS (20U)
+#define GLB_REG2_GPIO_20_SET_LEN (1U)
+#define GLB_REG2_GPIO_20_SET_MSK (((1U << GLB_REG2_GPIO_20_SET_LEN) - 1) << GLB_REG2_GPIO_20_SET_POS)
+#define GLB_REG2_GPIO_20_SET_UMSK (~(((1U << GLB_REG2_GPIO_20_SET_LEN) - 1) << GLB_REG2_GPIO_20_SET_POS))
+#define GLB_REG2_GPIO_21_SET GLB_REG2_GPIO_21_SET
+#define GLB_REG2_GPIO_21_SET_POS (21U)
+#define GLB_REG2_GPIO_21_SET_LEN (1U)
+#define GLB_REG2_GPIO_21_SET_MSK (((1U << GLB_REG2_GPIO_21_SET_LEN) - 1) << GLB_REG2_GPIO_21_SET_POS)
+#define GLB_REG2_GPIO_21_SET_UMSK (~(((1U << GLB_REG2_GPIO_21_SET_LEN) - 1) << GLB_REG2_GPIO_21_SET_POS))
+#define GLB_REG2_GPIO_22_SET GLB_REG2_GPIO_22_SET
+#define GLB_REG2_GPIO_22_SET_POS (22U)
+#define GLB_REG2_GPIO_22_SET_LEN (1U)
+#define GLB_REG2_GPIO_22_SET_MSK (((1U << GLB_REG2_GPIO_22_SET_LEN) - 1) << GLB_REG2_GPIO_22_SET_POS)
+#define GLB_REG2_GPIO_22_SET_UMSK (~(((1U << GLB_REG2_GPIO_22_SET_LEN) - 1) << GLB_REG2_GPIO_22_SET_POS))
+#define GLB_REG2_GPIO_23_SET GLB_REG2_GPIO_23_SET
+#define GLB_REG2_GPIO_23_SET_POS (23U)
+#define GLB_REG2_GPIO_23_SET_LEN (1U)
+#define GLB_REG2_GPIO_23_SET_MSK (((1U << GLB_REG2_GPIO_23_SET_LEN) - 1) << GLB_REG2_GPIO_23_SET_POS)
+#define GLB_REG2_GPIO_23_SET_UMSK (~(((1U << GLB_REG2_GPIO_23_SET_LEN) - 1) << GLB_REG2_GPIO_23_SET_POS))
+#define GLB_REG2_GPIO_24_SET GLB_REG2_GPIO_24_SET
+#define GLB_REG2_GPIO_24_SET_POS (24U)
+#define GLB_REG2_GPIO_24_SET_LEN (1U)
+#define GLB_REG2_GPIO_24_SET_MSK (((1U << GLB_REG2_GPIO_24_SET_LEN) - 1) << GLB_REG2_GPIO_24_SET_POS)
+#define GLB_REG2_GPIO_24_SET_UMSK (~(((1U << GLB_REG2_GPIO_24_SET_LEN) - 1) << GLB_REG2_GPIO_24_SET_POS))
+#define GLB_REG2_GPIO_25_SET GLB_REG2_GPIO_25_SET
+#define GLB_REG2_GPIO_25_SET_POS (25U)
+#define GLB_REG2_GPIO_25_SET_LEN (1U)
+#define GLB_REG2_GPIO_25_SET_MSK (((1U << GLB_REG2_GPIO_25_SET_LEN) - 1) << GLB_REG2_GPIO_25_SET_POS)
+#define GLB_REG2_GPIO_25_SET_UMSK (~(((1U << GLB_REG2_GPIO_25_SET_LEN) - 1) << GLB_REG2_GPIO_25_SET_POS))
+#define GLB_REG2_GPIO_26_SET GLB_REG2_GPIO_26_SET
+#define GLB_REG2_GPIO_26_SET_POS (26U)
+#define GLB_REG2_GPIO_26_SET_LEN (1U)
+#define GLB_REG2_GPIO_26_SET_MSK (((1U << GLB_REG2_GPIO_26_SET_LEN) - 1) << GLB_REG2_GPIO_26_SET_POS)
+#define GLB_REG2_GPIO_26_SET_UMSK (~(((1U << GLB_REG2_GPIO_26_SET_LEN) - 1) << GLB_REG2_GPIO_26_SET_POS))
+#define GLB_REG2_GPIO_27_SET GLB_REG2_GPIO_27_SET
+#define GLB_REG2_GPIO_27_SET_POS (27U)
+#define GLB_REG2_GPIO_27_SET_LEN (1U)
+#define GLB_REG2_GPIO_27_SET_MSK (((1U << GLB_REG2_GPIO_27_SET_LEN) - 1) << GLB_REG2_GPIO_27_SET_POS)
+#define GLB_REG2_GPIO_27_SET_UMSK (~(((1U << GLB_REG2_GPIO_27_SET_LEN) - 1) << GLB_REG2_GPIO_27_SET_POS))
+#define GLB_REG2_GPIO_28_SET GLB_REG2_GPIO_28_SET
+#define GLB_REG2_GPIO_28_SET_POS (28U)
+#define GLB_REG2_GPIO_28_SET_LEN (1U)
+#define GLB_REG2_GPIO_28_SET_MSK (((1U << GLB_REG2_GPIO_28_SET_LEN) - 1) << GLB_REG2_GPIO_28_SET_POS)
+#define GLB_REG2_GPIO_28_SET_UMSK (~(((1U << GLB_REG2_GPIO_28_SET_LEN) - 1) << GLB_REG2_GPIO_28_SET_POS))
+#define GLB_REG2_GPIO_29_SET GLB_REG2_GPIO_29_SET
+#define GLB_REG2_GPIO_29_SET_POS (29U)
+#define GLB_REG2_GPIO_29_SET_LEN (1U)
+#define GLB_REG2_GPIO_29_SET_MSK (((1U << GLB_REG2_GPIO_29_SET_LEN) - 1) << GLB_REG2_GPIO_29_SET_POS)
+#define GLB_REG2_GPIO_29_SET_UMSK (~(((1U << GLB_REG2_GPIO_29_SET_LEN) - 1) << GLB_REG2_GPIO_29_SET_POS))
+#define GLB_REG2_GPIO_30_SET GLB_REG2_GPIO_30_SET
+#define GLB_REG2_GPIO_30_SET_POS (30U)
+#define GLB_REG2_GPIO_30_SET_LEN (1U)
+#define GLB_REG2_GPIO_30_SET_MSK (((1U << GLB_REG2_GPIO_30_SET_LEN) - 1) << GLB_REG2_GPIO_30_SET_POS)
+#define GLB_REG2_GPIO_30_SET_UMSK (~(((1U << GLB_REG2_GPIO_30_SET_LEN) - 1) << GLB_REG2_GPIO_30_SET_POS))
+#define GLB_REG2_GPIO_31_SET GLB_REG2_GPIO_31_SET
+#define GLB_REG2_GPIO_31_SET_POS (31U)
+#define GLB_REG2_GPIO_31_SET_LEN (1U)
+#define GLB_REG2_GPIO_31_SET_MSK (((1U << GLB_REG2_GPIO_31_SET_LEN) - 1) << GLB_REG2_GPIO_31_SET_POS)
+#define GLB_REG2_GPIO_31_SET_UMSK (~(((1U << GLB_REG2_GPIO_31_SET_LEN) - 1) << GLB_REG2_GPIO_31_SET_POS))
+
+/* 0xAF0 : gpio_cfg139 */
+#define GLB_GPIO_CFG139_OFFSET (0xAF0)
+#define GLB_REG2_GPIO_32_SET GLB_REG2_GPIO_32_SET
+#define GLB_REG2_GPIO_32_SET_POS (0U)
+#define GLB_REG2_GPIO_32_SET_LEN (1U)
+#define GLB_REG2_GPIO_32_SET_MSK (((1U << GLB_REG2_GPIO_32_SET_LEN) - 1) << GLB_REG2_GPIO_32_SET_POS)
+#define GLB_REG2_GPIO_32_SET_UMSK (~(((1U << GLB_REG2_GPIO_32_SET_LEN) - 1) << GLB_REG2_GPIO_32_SET_POS))
+#define GLB_REG2_GPIO_33_SET GLB_REG2_GPIO_33_SET
+#define GLB_REG2_GPIO_33_SET_POS (1U)
+#define GLB_REG2_GPIO_33_SET_LEN (1U)
+#define GLB_REG2_GPIO_33_SET_MSK (((1U << GLB_REG2_GPIO_33_SET_LEN) - 1) << GLB_REG2_GPIO_33_SET_POS)
+#define GLB_REG2_GPIO_33_SET_UMSK (~(((1U << GLB_REG2_GPIO_33_SET_LEN) - 1) << GLB_REG2_GPIO_33_SET_POS))
+#define GLB_REG2_GPIO_34_SET GLB_REG2_GPIO_34_SET
+#define GLB_REG2_GPIO_34_SET_POS (2U)
+#define GLB_REG2_GPIO_34_SET_LEN (1U)
+#define GLB_REG2_GPIO_34_SET_MSK (((1U << GLB_REG2_GPIO_34_SET_LEN) - 1) << GLB_REG2_GPIO_34_SET_POS)
+#define GLB_REG2_GPIO_34_SET_UMSK (~(((1U << GLB_REG2_GPIO_34_SET_LEN) - 1) << GLB_REG2_GPIO_34_SET_POS))
+#define GLB_REG2_GPIO_35_SET GLB_REG2_GPIO_35_SET
+#define GLB_REG2_GPIO_35_SET_POS (3U)
+#define GLB_REG2_GPIO_35_SET_LEN (1U)
+#define GLB_REG2_GPIO_35_SET_MSK (((1U << GLB_REG2_GPIO_35_SET_LEN) - 1) << GLB_REG2_GPIO_35_SET_POS)
+#define GLB_REG2_GPIO_35_SET_UMSK (~(((1U << GLB_REG2_GPIO_35_SET_LEN) - 1) << GLB_REG2_GPIO_35_SET_POS))
+#define GLB_REG2_GPIO_36_SET GLB_REG2_GPIO_36_SET
+#define GLB_REG2_GPIO_36_SET_POS (4U)
+#define GLB_REG2_GPIO_36_SET_LEN (1U)
+#define GLB_REG2_GPIO_36_SET_MSK (((1U << GLB_REG2_GPIO_36_SET_LEN) - 1) << GLB_REG2_GPIO_36_SET_POS)
+#define GLB_REG2_GPIO_36_SET_UMSK (~(((1U << GLB_REG2_GPIO_36_SET_LEN) - 1) << GLB_REG2_GPIO_36_SET_POS))
+#define GLB_REG2_GPIO_37_SET GLB_REG2_GPIO_37_SET
+#define GLB_REG2_GPIO_37_SET_POS (5U)
+#define GLB_REG2_GPIO_37_SET_LEN (1U)
+#define GLB_REG2_GPIO_37_SET_MSK (((1U << GLB_REG2_GPIO_37_SET_LEN) - 1) << GLB_REG2_GPIO_37_SET_POS)
+#define GLB_REG2_GPIO_37_SET_UMSK (~(((1U << GLB_REG2_GPIO_37_SET_LEN) - 1) << GLB_REG2_GPIO_37_SET_POS))
+#define GLB_REG2_GPIO_38_SET GLB_REG2_GPIO_38_SET
+#define GLB_REG2_GPIO_38_SET_POS (6U)
+#define GLB_REG2_GPIO_38_SET_LEN (1U)
+#define GLB_REG2_GPIO_38_SET_MSK (((1U << GLB_REG2_GPIO_38_SET_LEN) - 1) << GLB_REG2_GPIO_38_SET_POS)
+#define GLB_REG2_GPIO_38_SET_UMSK (~(((1U << GLB_REG2_GPIO_38_SET_LEN) - 1) << GLB_REG2_GPIO_38_SET_POS))
+#define GLB_REG2_GPIO_39_SET GLB_REG2_GPIO_39_SET
+#define GLB_REG2_GPIO_39_SET_POS (7U)
+#define GLB_REG2_GPIO_39_SET_LEN (1U)
+#define GLB_REG2_GPIO_39_SET_MSK (((1U << GLB_REG2_GPIO_39_SET_LEN) - 1) << GLB_REG2_GPIO_39_SET_POS)
+#define GLB_REG2_GPIO_39_SET_UMSK (~(((1U << GLB_REG2_GPIO_39_SET_LEN) - 1) << GLB_REG2_GPIO_39_SET_POS))
+#define GLB_REG2_GPIO_40_SET GLB_REG2_GPIO_40_SET
+#define GLB_REG2_GPIO_40_SET_POS (8U)
+#define GLB_REG2_GPIO_40_SET_LEN (1U)
+#define GLB_REG2_GPIO_40_SET_MSK (((1U << GLB_REG2_GPIO_40_SET_LEN) - 1) << GLB_REG2_GPIO_40_SET_POS)
+#define GLB_REG2_GPIO_40_SET_UMSK (~(((1U << GLB_REG2_GPIO_40_SET_LEN) - 1) << GLB_REG2_GPIO_40_SET_POS))
+#define GLB_REG2_GPIO_41_SET GLB_REG2_GPIO_41_SET
+#define GLB_REG2_GPIO_41_SET_POS (9U)
+#define GLB_REG2_GPIO_41_SET_LEN (1U)
+#define GLB_REG2_GPIO_41_SET_MSK (((1U << GLB_REG2_GPIO_41_SET_LEN) - 1) << GLB_REG2_GPIO_41_SET_POS)
+#define GLB_REG2_GPIO_41_SET_UMSK (~(((1U << GLB_REG2_GPIO_41_SET_LEN) - 1) << GLB_REG2_GPIO_41_SET_POS))
+#define GLB_REG2_GPIO_42_SET GLB_REG2_GPIO_42_SET
+#define GLB_REG2_GPIO_42_SET_POS (10U)
+#define GLB_REG2_GPIO_42_SET_LEN (1U)
+#define GLB_REG2_GPIO_42_SET_MSK (((1U << GLB_REG2_GPIO_42_SET_LEN) - 1) << GLB_REG2_GPIO_42_SET_POS)
+#define GLB_REG2_GPIO_42_SET_UMSK (~(((1U << GLB_REG2_GPIO_42_SET_LEN) - 1) << GLB_REG2_GPIO_42_SET_POS))
+#define GLB_REG2_GPIO_43_SET GLB_REG2_GPIO_43_SET
+#define GLB_REG2_GPIO_43_SET_POS (11U)
+#define GLB_REG2_GPIO_43_SET_LEN (1U)
+#define GLB_REG2_GPIO_43_SET_MSK (((1U << GLB_REG2_GPIO_43_SET_LEN) - 1) << GLB_REG2_GPIO_43_SET_POS)
+#define GLB_REG2_GPIO_43_SET_UMSK (~(((1U << GLB_REG2_GPIO_43_SET_LEN) - 1) << GLB_REG2_GPIO_43_SET_POS))
+#define GLB_REG2_GPIO_44_SET GLB_REG2_GPIO_44_SET
+#define GLB_REG2_GPIO_44_SET_POS (12U)
+#define GLB_REG2_GPIO_44_SET_LEN (1U)
+#define GLB_REG2_GPIO_44_SET_MSK (((1U << GLB_REG2_GPIO_44_SET_LEN) - 1) << GLB_REG2_GPIO_44_SET_POS)
+#define GLB_REG2_GPIO_44_SET_UMSK (~(((1U << GLB_REG2_GPIO_44_SET_LEN) - 1) << GLB_REG2_GPIO_44_SET_POS))
+#define GLB_REG2_GPIO_45_SET GLB_REG2_GPIO_45_SET
+#define GLB_REG2_GPIO_45_SET_POS (13U)
+#define GLB_REG2_GPIO_45_SET_LEN (1U)
+#define GLB_REG2_GPIO_45_SET_MSK (((1U << GLB_REG2_GPIO_45_SET_LEN) - 1) << GLB_REG2_GPIO_45_SET_POS)
+#define GLB_REG2_GPIO_45_SET_UMSK (~(((1U << GLB_REG2_GPIO_45_SET_LEN) - 1) << GLB_REG2_GPIO_45_SET_POS))
+
+/* 0xAF4 : gpio_cfg140 */
+#define GLB_GPIO_CFG140_OFFSET (0xAF4)
+#define GLB_REG2_GPIO_0_CLR GLB_REG2_GPIO_0_CLR
+#define GLB_REG2_GPIO_0_CLR_POS (0U)
+#define GLB_REG2_GPIO_0_CLR_LEN (1U)
+#define GLB_REG2_GPIO_0_CLR_MSK (((1U << GLB_REG2_GPIO_0_CLR_LEN) - 1) << GLB_REG2_GPIO_0_CLR_POS)
+#define GLB_REG2_GPIO_0_CLR_UMSK (~(((1U << GLB_REG2_GPIO_0_CLR_LEN) - 1) << GLB_REG2_GPIO_0_CLR_POS))
+#define GLB_REG2_GPIO_1_CLR GLB_REG2_GPIO_1_CLR
+#define GLB_REG2_GPIO_1_CLR_POS (1U)
+#define GLB_REG2_GPIO_1_CLR_LEN (1U)
+#define GLB_REG2_GPIO_1_CLR_MSK (((1U << GLB_REG2_GPIO_1_CLR_LEN) - 1) << GLB_REG2_GPIO_1_CLR_POS)
+#define GLB_REG2_GPIO_1_CLR_UMSK (~(((1U << GLB_REG2_GPIO_1_CLR_LEN) - 1) << GLB_REG2_GPIO_1_CLR_POS))
+#define GLB_REG2_GPIO_2_CLR GLB_REG2_GPIO_2_CLR
+#define GLB_REG2_GPIO_2_CLR_POS (2U)
+#define GLB_REG2_GPIO_2_CLR_LEN (1U)
+#define GLB_REG2_GPIO_2_CLR_MSK (((1U << GLB_REG2_GPIO_2_CLR_LEN) - 1) << GLB_REG2_GPIO_2_CLR_POS)
+#define GLB_REG2_GPIO_2_CLR_UMSK (~(((1U << GLB_REG2_GPIO_2_CLR_LEN) - 1) << GLB_REG2_GPIO_2_CLR_POS))
+#define GLB_REG2_GPIO_3_CLR GLB_REG2_GPIO_3_CLR
+#define GLB_REG2_GPIO_3_CLR_POS (3U)
+#define GLB_REG2_GPIO_3_CLR_LEN (1U)
+#define GLB_REG2_GPIO_3_CLR_MSK (((1U << GLB_REG2_GPIO_3_CLR_LEN) - 1) << GLB_REG2_GPIO_3_CLR_POS)
+#define GLB_REG2_GPIO_3_CLR_UMSK (~(((1U << GLB_REG2_GPIO_3_CLR_LEN) - 1) << GLB_REG2_GPIO_3_CLR_POS))
+#define GLB_REG2_GPIO_4_CLR GLB_REG2_GPIO_4_CLR
+#define GLB_REG2_GPIO_4_CLR_POS (4U)
+#define GLB_REG2_GPIO_4_CLR_LEN (1U)
+#define GLB_REG2_GPIO_4_CLR_MSK (((1U << GLB_REG2_GPIO_4_CLR_LEN) - 1) << GLB_REG2_GPIO_4_CLR_POS)
+#define GLB_REG2_GPIO_4_CLR_UMSK (~(((1U << GLB_REG2_GPIO_4_CLR_LEN) - 1) << GLB_REG2_GPIO_4_CLR_POS))
+#define GLB_REG2_GPIO_5_CLR GLB_REG2_GPIO_5_CLR
+#define GLB_REG2_GPIO_5_CLR_POS (5U)
+#define GLB_REG2_GPIO_5_CLR_LEN (1U)
+#define GLB_REG2_GPIO_5_CLR_MSK (((1U << GLB_REG2_GPIO_5_CLR_LEN) - 1) << GLB_REG2_GPIO_5_CLR_POS)
+#define GLB_REG2_GPIO_5_CLR_UMSK (~(((1U << GLB_REG2_GPIO_5_CLR_LEN) - 1) << GLB_REG2_GPIO_5_CLR_POS))
+#define GLB_REG2_GPIO_6_CLR GLB_REG2_GPIO_6_CLR
+#define GLB_REG2_GPIO_6_CLR_POS (6U)
+#define GLB_REG2_GPIO_6_CLR_LEN (1U)
+#define GLB_REG2_GPIO_6_CLR_MSK (((1U << GLB_REG2_GPIO_6_CLR_LEN) - 1) << GLB_REG2_GPIO_6_CLR_POS)
+#define GLB_REG2_GPIO_6_CLR_UMSK (~(((1U << GLB_REG2_GPIO_6_CLR_LEN) - 1) << GLB_REG2_GPIO_6_CLR_POS))
+#define GLB_REG2_GPIO_7_CLR GLB_REG2_GPIO_7_CLR
+#define GLB_REG2_GPIO_7_CLR_POS (7U)
+#define GLB_REG2_GPIO_7_CLR_LEN (1U)
+#define GLB_REG2_GPIO_7_CLR_MSK (((1U << GLB_REG2_GPIO_7_CLR_LEN) - 1) << GLB_REG2_GPIO_7_CLR_POS)
+#define GLB_REG2_GPIO_7_CLR_UMSK (~(((1U << GLB_REG2_GPIO_7_CLR_LEN) - 1) << GLB_REG2_GPIO_7_CLR_POS))
+#define GLB_REG2_GPIO_8_CLR GLB_REG2_GPIO_8_CLR
+#define GLB_REG2_GPIO_8_CLR_POS (8U)
+#define GLB_REG2_GPIO_8_CLR_LEN (1U)
+#define GLB_REG2_GPIO_8_CLR_MSK (((1U << GLB_REG2_GPIO_8_CLR_LEN) - 1) << GLB_REG2_GPIO_8_CLR_POS)
+#define GLB_REG2_GPIO_8_CLR_UMSK (~(((1U << GLB_REG2_GPIO_8_CLR_LEN) - 1) << GLB_REG2_GPIO_8_CLR_POS))
+#define GLB_REG2_GPIO_9_CLR GLB_REG2_GPIO_9_CLR
+#define GLB_REG2_GPIO_9_CLR_POS (9U)
+#define GLB_REG2_GPIO_9_CLR_LEN (1U)
+#define GLB_REG2_GPIO_9_CLR_MSK (((1U << GLB_REG2_GPIO_9_CLR_LEN) - 1) << GLB_REG2_GPIO_9_CLR_POS)
+#define GLB_REG2_GPIO_9_CLR_UMSK (~(((1U << GLB_REG2_GPIO_9_CLR_LEN) - 1) << GLB_REG2_GPIO_9_CLR_POS))
+#define GLB_REG2_GPIO_10_CLR GLB_REG2_GPIO_10_CLR
+#define GLB_REG2_GPIO_10_CLR_POS (10U)
+#define GLB_REG2_GPIO_10_CLR_LEN (1U)
+#define GLB_REG2_GPIO_10_CLR_MSK (((1U << GLB_REG2_GPIO_10_CLR_LEN) - 1) << GLB_REG2_GPIO_10_CLR_POS)
+#define GLB_REG2_GPIO_10_CLR_UMSK (~(((1U << GLB_REG2_GPIO_10_CLR_LEN) - 1) << GLB_REG2_GPIO_10_CLR_POS))
+#define GLB_REG2_GPIO_11_CLR GLB_REG2_GPIO_11_CLR
+#define GLB_REG2_GPIO_11_CLR_POS (11U)
+#define GLB_REG2_GPIO_11_CLR_LEN (1U)
+#define GLB_REG2_GPIO_11_CLR_MSK (((1U << GLB_REG2_GPIO_11_CLR_LEN) - 1) << GLB_REG2_GPIO_11_CLR_POS)
+#define GLB_REG2_GPIO_11_CLR_UMSK (~(((1U << GLB_REG2_GPIO_11_CLR_LEN) - 1) << GLB_REG2_GPIO_11_CLR_POS))
+#define GLB_REG2_GPIO_12_CLR GLB_REG2_GPIO_12_CLR
+#define GLB_REG2_GPIO_12_CLR_POS (12U)
+#define GLB_REG2_GPIO_12_CLR_LEN (1U)
+#define GLB_REG2_GPIO_12_CLR_MSK (((1U << GLB_REG2_GPIO_12_CLR_LEN) - 1) << GLB_REG2_GPIO_12_CLR_POS)
+#define GLB_REG2_GPIO_12_CLR_UMSK (~(((1U << GLB_REG2_GPIO_12_CLR_LEN) - 1) << GLB_REG2_GPIO_12_CLR_POS))
+#define GLB_REG2_GPIO_13_CLR GLB_REG2_GPIO_13_CLR
+#define GLB_REG2_GPIO_13_CLR_POS (13U)
+#define GLB_REG2_GPIO_13_CLR_LEN (1U)
+#define GLB_REG2_GPIO_13_CLR_MSK (((1U << GLB_REG2_GPIO_13_CLR_LEN) - 1) << GLB_REG2_GPIO_13_CLR_POS)
+#define GLB_REG2_GPIO_13_CLR_UMSK (~(((1U << GLB_REG2_GPIO_13_CLR_LEN) - 1) << GLB_REG2_GPIO_13_CLR_POS))
+#define GLB_REG2_GPIO_14_CLR GLB_REG2_GPIO_14_CLR
+#define GLB_REG2_GPIO_14_CLR_POS (14U)
+#define GLB_REG2_GPIO_14_CLR_LEN (1U)
+#define GLB_REG2_GPIO_14_CLR_MSK (((1U << GLB_REG2_GPIO_14_CLR_LEN) - 1) << GLB_REG2_GPIO_14_CLR_POS)
+#define GLB_REG2_GPIO_14_CLR_UMSK (~(((1U << GLB_REG2_GPIO_14_CLR_LEN) - 1) << GLB_REG2_GPIO_14_CLR_POS))
+#define GLB_REG2_GPIO_15_CLR GLB_REG2_GPIO_15_CLR
+#define GLB_REG2_GPIO_15_CLR_POS (15U)
+#define GLB_REG2_GPIO_15_CLR_LEN (1U)
+#define GLB_REG2_GPIO_15_CLR_MSK (((1U << GLB_REG2_GPIO_15_CLR_LEN) - 1) << GLB_REG2_GPIO_15_CLR_POS)
+#define GLB_REG2_GPIO_15_CLR_UMSK (~(((1U << GLB_REG2_GPIO_15_CLR_LEN) - 1) << GLB_REG2_GPIO_15_CLR_POS))
+#define GLB_REG2_GPIO_16_CLR GLB_REG2_GPIO_16_CLR
+#define GLB_REG2_GPIO_16_CLR_POS (16U)
+#define GLB_REG2_GPIO_16_CLR_LEN (1U)
+#define GLB_REG2_GPIO_16_CLR_MSK (((1U << GLB_REG2_GPIO_16_CLR_LEN) - 1) << GLB_REG2_GPIO_16_CLR_POS)
+#define GLB_REG2_GPIO_16_CLR_UMSK (~(((1U << GLB_REG2_GPIO_16_CLR_LEN) - 1) << GLB_REG2_GPIO_16_CLR_POS))
+#define GLB_REG2_GPIO_17_CLR GLB_REG2_GPIO_17_CLR
+#define GLB_REG2_GPIO_17_CLR_POS (17U)
+#define GLB_REG2_GPIO_17_CLR_LEN (1U)
+#define GLB_REG2_GPIO_17_CLR_MSK (((1U << GLB_REG2_GPIO_17_CLR_LEN) - 1) << GLB_REG2_GPIO_17_CLR_POS)
+#define GLB_REG2_GPIO_17_CLR_UMSK (~(((1U << GLB_REG2_GPIO_17_CLR_LEN) - 1) << GLB_REG2_GPIO_17_CLR_POS))
+#define GLB_REG2_GPIO_18_CLR GLB_REG2_GPIO_18_CLR
+#define GLB_REG2_GPIO_18_CLR_POS (18U)
+#define GLB_REG2_GPIO_18_CLR_LEN (1U)
+#define GLB_REG2_GPIO_18_CLR_MSK (((1U << GLB_REG2_GPIO_18_CLR_LEN) - 1) << GLB_REG2_GPIO_18_CLR_POS)
+#define GLB_REG2_GPIO_18_CLR_UMSK (~(((1U << GLB_REG2_GPIO_18_CLR_LEN) - 1) << GLB_REG2_GPIO_18_CLR_POS))
+#define GLB_REG2_GPIO_19_CLR GLB_REG2_GPIO_19_CLR
+#define GLB_REG2_GPIO_19_CLR_POS (19U)
+#define GLB_REG2_GPIO_19_CLR_LEN (1U)
+#define GLB_REG2_GPIO_19_CLR_MSK (((1U << GLB_REG2_GPIO_19_CLR_LEN) - 1) << GLB_REG2_GPIO_19_CLR_POS)
+#define GLB_REG2_GPIO_19_CLR_UMSK (~(((1U << GLB_REG2_GPIO_19_CLR_LEN) - 1) << GLB_REG2_GPIO_19_CLR_POS))
+#define GLB_REG2_GPIO_20_CLR GLB_REG2_GPIO_20_CLR
+#define GLB_REG2_GPIO_20_CLR_POS (20U)
+#define GLB_REG2_GPIO_20_CLR_LEN (1U)
+#define GLB_REG2_GPIO_20_CLR_MSK (((1U << GLB_REG2_GPIO_20_CLR_LEN) - 1) << GLB_REG2_GPIO_20_CLR_POS)
+#define GLB_REG2_GPIO_20_CLR_UMSK (~(((1U << GLB_REG2_GPIO_20_CLR_LEN) - 1) << GLB_REG2_GPIO_20_CLR_POS))
+#define GLB_REG2_GPIO_21_CLR GLB_REG2_GPIO_21_CLR
+#define GLB_REG2_GPIO_21_CLR_POS (21U)
+#define GLB_REG2_GPIO_21_CLR_LEN (1U)
+#define GLB_REG2_GPIO_21_CLR_MSK (((1U << GLB_REG2_GPIO_21_CLR_LEN) - 1) << GLB_REG2_GPIO_21_CLR_POS)
+#define GLB_REG2_GPIO_21_CLR_UMSK (~(((1U << GLB_REG2_GPIO_21_CLR_LEN) - 1) << GLB_REG2_GPIO_21_CLR_POS))
+#define GLB_REG2_GPIO_22_CLR GLB_REG2_GPIO_22_CLR
+#define GLB_REG2_GPIO_22_CLR_POS (22U)
+#define GLB_REG2_GPIO_22_CLR_LEN (1U)
+#define GLB_REG2_GPIO_22_CLR_MSK (((1U << GLB_REG2_GPIO_22_CLR_LEN) - 1) << GLB_REG2_GPIO_22_CLR_POS)
+#define GLB_REG2_GPIO_22_CLR_UMSK (~(((1U << GLB_REG2_GPIO_22_CLR_LEN) - 1) << GLB_REG2_GPIO_22_CLR_POS))
+#define GLB_REG2_GPIO_23_CLR GLB_REG2_GPIO_23_CLR
+#define GLB_REG2_GPIO_23_CLR_POS (23U)
+#define GLB_REG2_GPIO_23_CLR_LEN (1U)
+#define GLB_REG2_GPIO_23_CLR_MSK (((1U << GLB_REG2_GPIO_23_CLR_LEN) - 1) << GLB_REG2_GPIO_23_CLR_POS)
+#define GLB_REG2_GPIO_23_CLR_UMSK (~(((1U << GLB_REG2_GPIO_23_CLR_LEN) - 1) << GLB_REG2_GPIO_23_CLR_POS))
+#define GLB_REG2_GPIO_24_CLR GLB_REG2_GPIO_24_CLR
+#define GLB_REG2_GPIO_24_CLR_POS (24U)
+#define GLB_REG2_GPIO_24_CLR_LEN (1U)
+#define GLB_REG2_GPIO_24_CLR_MSK (((1U << GLB_REG2_GPIO_24_CLR_LEN) - 1) << GLB_REG2_GPIO_24_CLR_POS)
+#define GLB_REG2_GPIO_24_CLR_UMSK (~(((1U << GLB_REG2_GPIO_24_CLR_LEN) - 1) << GLB_REG2_GPIO_24_CLR_POS))
+#define GLB_REG2_GPIO_25_CLR GLB_REG2_GPIO_25_CLR
+#define GLB_REG2_GPIO_25_CLR_POS (25U)
+#define GLB_REG2_GPIO_25_CLR_LEN (1U)
+#define GLB_REG2_GPIO_25_CLR_MSK (((1U << GLB_REG2_GPIO_25_CLR_LEN) - 1) << GLB_REG2_GPIO_25_CLR_POS)
+#define GLB_REG2_GPIO_25_CLR_UMSK (~(((1U << GLB_REG2_GPIO_25_CLR_LEN) - 1) << GLB_REG2_GPIO_25_CLR_POS))
+#define GLB_REG2_GPIO_26_CLR GLB_REG2_GPIO_26_CLR
+#define GLB_REG2_GPIO_26_CLR_POS (26U)
+#define GLB_REG2_GPIO_26_CLR_LEN (1U)
+#define GLB_REG2_GPIO_26_CLR_MSK (((1U << GLB_REG2_GPIO_26_CLR_LEN) - 1) << GLB_REG2_GPIO_26_CLR_POS)
+#define GLB_REG2_GPIO_26_CLR_UMSK (~(((1U << GLB_REG2_GPIO_26_CLR_LEN) - 1) << GLB_REG2_GPIO_26_CLR_POS))
+#define GLB_REG2_GPIO_27_CLR GLB_REG2_GPIO_27_CLR
+#define GLB_REG2_GPIO_27_CLR_POS (27U)
+#define GLB_REG2_GPIO_27_CLR_LEN (1U)
+#define GLB_REG2_GPIO_27_CLR_MSK (((1U << GLB_REG2_GPIO_27_CLR_LEN) - 1) << GLB_REG2_GPIO_27_CLR_POS)
+#define GLB_REG2_GPIO_27_CLR_UMSK (~(((1U << GLB_REG2_GPIO_27_CLR_LEN) - 1) << GLB_REG2_GPIO_27_CLR_POS))
+#define GLB_REG2_GPIO_28_CLR GLB_REG2_GPIO_28_CLR
+#define GLB_REG2_GPIO_28_CLR_POS (28U)
+#define GLB_REG2_GPIO_28_CLR_LEN (1U)
+#define GLB_REG2_GPIO_28_CLR_MSK (((1U << GLB_REG2_GPIO_28_CLR_LEN) - 1) << GLB_REG2_GPIO_28_CLR_POS)
+#define GLB_REG2_GPIO_28_CLR_UMSK (~(((1U << GLB_REG2_GPIO_28_CLR_LEN) - 1) << GLB_REG2_GPIO_28_CLR_POS))
+#define GLB_REG2_GPIO_29_CLR GLB_REG2_GPIO_29_CLR
+#define GLB_REG2_GPIO_29_CLR_POS (29U)
+#define GLB_REG2_GPIO_29_CLR_LEN (1U)
+#define GLB_REG2_GPIO_29_CLR_MSK (((1U << GLB_REG2_GPIO_29_CLR_LEN) - 1) << GLB_REG2_GPIO_29_CLR_POS)
+#define GLB_REG2_GPIO_29_CLR_UMSK (~(((1U << GLB_REG2_GPIO_29_CLR_LEN) - 1) << GLB_REG2_GPIO_29_CLR_POS))
+#define GLB_REG2_GPIO_30_CLR GLB_REG2_GPIO_30_CLR
+#define GLB_REG2_GPIO_30_CLR_POS (30U)
+#define GLB_REG2_GPIO_30_CLR_LEN (1U)
+#define GLB_REG2_GPIO_30_CLR_MSK (((1U << GLB_REG2_GPIO_30_CLR_LEN) - 1) << GLB_REG2_GPIO_30_CLR_POS)
+#define GLB_REG2_GPIO_30_CLR_UMSK (~(((1U << GLB_REG2_GPIO_30_CLR_LEN) - 1) << GLB_REG2_GPIO_30_CLR_POS))
+#define GLB_REG2_GPIO_31_CLR GLB_REG2_GPIO_31_CLR
+#define GLB_REG2_GPIO_31_CLR_POS (31U)
+#define GLB_REG2_GPIO_31_CLR_LEN (1U)
+#define GLB_REG2_GPIO_31_CLR_MSK (((1U << GLB_REG2_GPIO_31_CLR_LEN) - 1) << GLB_REG2_GPIO_31_CLR_POS)
+#define GLB_REG2_GPIO_31_CLR_UMSK (~(((1U << GLB_REG2_GPIO_31_CLR_LEN) - 1) << GLB_REG2_GPIO_31_CLR_POS))
+
+/* 0xAF8 : gpio_cfg141 */
+#define GLB_GPIO_CFG141_OFFSET (0xAF8)
+#define GLB_REG2_GPIO_32_CLR GLB_REG2_GPIO_32_CLR
+#define GLB_REG2_GPIO_32_CLR_POS (0U)
+#define GLB_REG2_GPIO_32_CLR_LEN (1U)
+#define GLB_REG2_GPIO_32_CLR_MSK (((1U << GLB_REG2_GPIO_32_CLR_LEN) - 1) << GLB_REG2_GPIO_32_CLR_POS)
+#define GLB_REG2_GPIO_32_CLR_UMSK (~(((1U << GLB_REG2_GPIO_32_CLR_LEN) - 1) << GLB_REG2_GPIO_32_CLR_POS))
+#define GLB_REG2_GPIO_33_CLR GLB_REG2_GPIO_33_CLR
+#define GLB_REG2_GPIO_33_CLR_POS (1U)
+#define GLB_REG2_GPIO_33_CLR_LEN (1U)
+#define GLB_REG2_GPIO_33_CLR_MSK (((1U << GLB_REG2_GPIO_33_CLR_LEN) - 1) << GLB_REG2_GPIO_33_CLR_POS)
+#define GLB_REG2_GPIO_33_CLR_UMSK (~(((1U << GLB_REG2_GPIO_33_CLR_LEN) - 1) << GLB_REG2_GPIO_33_CLR_POS))
+#define GLB_REG2_GPIO_34_CLR GLB_REG2_GPIO_34_CLR
+#define GLB_REG2_GPIO_34_CLR_POS (2U)
+#define GLB_REG2_GPIO_34_CLR_LEN (1U)
+#define GLB_REG2_GPIO_34_CLR_MSK (((1U << GLB_REG2_GPIO_34_CLR_LEN) - 1) << GLB_REG2_GPIO_34_CLR_POS)
+#define GLB_REG2_GPIO_34_CLR_UMSK (~(((1U << GLB_REG2_GPIO_34_CLR_LEN) - 1) << GLB_REG2_GPIO_34_CLR_POS))
+#define GLB_REG2_GPIO_35_CLR GLB_REG2_GPIO_35_CLR
+#define GLB_REG2_GPIO_35_CLR_POS (3U)
+#define GLB_REG2_GPIO_35_CLR_LEN (1U)
+#define GLB_REG2_GPIO_35_CLR_MSK (((1U << GLB_REG2_GPIO_35_CLR_LEN) - 1) << GLB_REG2_GPIO_35_CLR_POS)
+#define GLB_REG2_GPIO_35_CLR_UMSK (~(((1U << GLB_REG2_GPIO_35_CLR_LEN) - 1) << GLB_REG2_GPIO_35_CLR_POS))
+#define GLB_REG2_GPIO_36_CLR GLB_REG2_GPIO_36_CLR
+#define GLB_REG2_GPIO_36_CLR_POS (4U)
+#define GLB_REG2_GPIO_36_CLR_LEN (1U)
+#define GLB_REG2_GPIO_36_CLR_MSK (((1U << GLB_REG2_GPIO_36_CLR_LEN) - 1) << GLB_REG2_GPIO_36_CLR_POS)
+#define GLB_REG2_GPIO_36_CLR_UMSK (~(((1U << GLB_REG2_GPIO_36_CLR_LEN) - 1) << GLB_REG2_GPIO_36_CLR_POS))
+#define GLB_REG2_GPIO_37_CLR GLB_REG2_GPIO_37_CLR
+#define GLB_REG2_GPIO_37_CLR_POS (5U)
+#define GLB_REG2_GPIO_37_CLR_LEN (1U)
+#define GLB_REG2_GPIO_37_CLR_MSK (((1U << GLB_REG2_GPIO_37_CLR_LEN) - 1) << GLB_REG2_GPIO_37_CLR_POS)
+#define GLB_REG2_GPIO_37_CLR_UMSK (~(((1U << GLB_REG2_GPIO_37_CLR_LEN) - 1) << GLB_REG2_GPIO_37_CLR_POS))
+#define GLB_REG2_GPIO_38_CLR GLB_REG2_GPIO_38_CLR
+#define GLB_REG2_GPIO_38_CLR_POS (6U)
+#define GLB_REG2_GPIO_38_CLR_LEN (1U)
+#define GLB_REG2_GPIO_38_CLR_MSK (((1U << GLB_REG2_GPIO_38_CLR_LEN) - 1) << GLB_REG2_GPIO_38_CLR_POS)
+#define GLB_REG2_GPIO_38_CLR_UMSK (~(((1U << GLB_REG2_GPIO_38_CLR_LEN) - 1) << GLB_REG2_GPIO_38_CLR_POS))
+#define GLB_REG2_GPIO_39_CLR GLB_REG2_GPIO_39_CLR
+#define GLB_REG2_GPIO_39_CLR_POS (7U)
+#define GLB_REG2_GPIO_39_CLR_LEN (1U)
+#define GLB_REG2_GPIO_39_CLR_MSK (((1U << GLB_REG2_GPIO_39_CLR_LEN) - 1) << GLB_REG2_GPIO_39_CLR_POS)
+#define GLB_REG2_GPIO_39_CLR_UMSK (~(((1U << GLB_REG2_GPIO_39_CLR_LEN) - 1) << GLB_REG2_GPIO_39_CLR_POS))
+#define GLB_REG2_GPIO_40_CLR GLB_REG2_GPIO_40_CLR
+#define GLB_REG2_GPIO_40_CLR_POS (8U)
+#define GLB_REG2_GPIO_40_CLR_LEN (1U)
+#define GLB_REG2_GPIO_40_CLR_MSK (((1U << GLB_REG2_GPIO_40_CLR_LEN) - 1) << GLB_REG2_GPIO_40_CLR_POS)
+#define GLB_REG2_GPIO_40_CLR_UMSK (~(((1U << GLB_REG2_GPIO_40_CLR_LEN) - 1) << GLB_REG2_GPIO_40_CLR_POS))
+#define GLB_REG2_GPIO_41_CLR GLB_REG2_GPIO_41_CLR
+#define GLB_REG2_GPIO_41_CLR_POS (9U)
+#define GLB_REG2_GPIO_41_CLR_LEN (1U)
+#define GLB_REG2_GPIO_41_CLR_MSK (((1U << GLB_REG2_GPIO_41_CLR_LEN) - 1) << GLB_REG2_GPIO_41_CLR_POS)
+#define GLB_REG2_GPIO_41_CLR_UMSK (~(((1U << GLB_REG2_GPIO_41_CLR_LEN) - 1) << GLB_REG2_GPIO_41_CLR_POS))
+#define GLB_REG2_GPIO_42_CLR GLB_REG2_GPIO_42_CLR
+#define GLB_REG2_GPIO_42_CLR_POS (10U)
+#define GLB_REG2_GPIO_42_CLR_LEN (1U)
+#define GLB_REG2_GPIO_42_CLR_MSK (((1U << GLB_REG2_GPIO_42_CLR_LEN) - 1) << GLB_REG2_GPIO_42_CLR_POS)
+#define GLB_REG2_GPIO_42_CLR_UMSK (~(((1U << GLB_REG2_GPIO_42_CLR_LEN) - 1) << GLB_REG2_GPIO_42_CLR_POS))
+#define GLB_REG2_GPIO_43_CLR GLB_REG2_GPIO_43_CLR
+#define GLB_REG2_GPIO_43_CLR_POS (11U)
+#define GLB_REG2_GPIO_43_CLR_LEN (1U)
+#define GLB_REG2_GPIO_43_CLR_MSK (((1U << GLB_REG2_GPIO_43_CLR_LEN) - 1) << GLB_REG2_GPIO_43_CLR_POS)
+#define GLB_REG2_GPIO_43_CLR_UMSK (~(((1U << GLB_REG2_GPIO_43_CLR_LEN) - 1) << GLB_REG2_GPIO_43_CLR_POS))
+#define GLB_REG2_GPIO_44_CLR GLB_REG2_GPIO_44_CLR
+#define GLB_REG2_GPIO_44_CLR_POS (12U)
+#define GLB_REG2_GPIO_44_CLR_LEN (1U)
+#define GLB_REG2_GPIO_44_CLR_MSK (((1U << GLB_REG2_GPIO_44_CLR_LEN) - 1) << GLB_REG2_GPIO_44_CLR_POS)
+#define GLB_REG2_GPIO_44_CLR_UMSK (~(((1U << GLB_REG2_GPIO_44_CLR_LEN) - 1) << GLB_REG2_GPIO_44_CLR_POS))
+#define GLB_REG2_GPIO_45_CLR GLB_REG2_GPIO_45_CLR
+#define GLB_REG2_GPIO_45_CLR_POS (13U)
+#define GLB_REG2_GPIO_45_CLR_LEN (1U)
+#define GLB_REG2_GPIO_45_CLR_MSK (((1U << GLB_REG2_GPIO_45_CLR_LEN) - 1) << GLB_REG2_GPIO_45_CLR_POS)
+#define GLB_REG2_GPIO_45_CLR_UMSK (~(((1U << GLB_REG2_GPIO_45_CLR_LEN) - 1) << GLB_REG2_GPIO_45_CLR_POS))
+
+/* 0xAFC : gpio_cfg142 */
+#define GLB_GPIO_CFG142_OFFSET (0xAFC)
+#define GLB_CR_GPIO_TX_EN GLB_CR_GPIO_TX_EN
+#define GLB_CR_GPIO_TX_EN_POS (0U)
+#define GLB_CR_GPIO_TX_EN_LEN (1U)
+#define GLB_CR_GPIO_TX_EN_MSK (((1U << GLB_CR_GPIO_TX_EN_LEN) - 1) << GLB_CR_GPIO_TX_EN_POS)
+#define GLB_CR_GPIO_TX_EN_UMSK (~(((1U << GLB_CR_GPIO_TX_EN_LEN) - 1) << GLB_CR_GPIO_TX_EN_POS))
+#define GLB_CR_INVERT_CODE0_HIGH GLB_CR_INVERT_CODE0_HIGH
+#define GLB_CR_INVERT_CODE0_HIGH_POS (1U)
+#define GLB_CR_INVERT_CODE0_HIGH_LEN (1U)
+#define GLB_CR_INVERT_CODE0_HIGH_MSK (((1U << GLB_CR_INVERT_CODE0_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE0_HIGH_POS)
+#define GLB_CR_INVERT_CODE0_HIGH_UMSK (~(((1U << GLB_CR_INVERT_CODE0_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE0_HIGH_POS))
+#define GLB_CR_INVERT_CODE1_HIGH GLB_CR_INVERT_CODE1_HIGH
+#define GLB_CR_INVERT_CODE1_HIGH_POS (2U)
+#define GLB_CR_INVERT_CODE1_HIGH_LEN (1U)
+#define GLB_CR_INVERT_CODE1_HIGH_MSK (((1U << GLB_CR_INVERT_CODE1_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE1_HIGH_POS)
+#define GLB_CR_INVERT_CODE1_HIGH_UMSK (~(((1U << GLB_CR_INVERT_CODE1_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE1_HIGH_POS))
+#define GLB_CR_CODE_TOTAL_TIME GLB_CR_CODE_TOTAL_TIME
+#define GLB_CR_CODE_TOTAL_TIME_POS (7U)
+#define GLB_CR_CODE_TOTAL_TIME_LEN (9U)
+#define GLB_CR_CODE_TOTAL_TIME_MSK (((1U << GLB_CR_CODE_TOTAL_TIME_LEN) - 1) << GLB_CR_CODE_TOTAL_TIME_POS)
+#define GLB_CR_CODE_TOTAL_TIME_UMSK (~(((1U << GLB_CR_CODE_TOTAL_TIME_LEN) - 1) << GLB_CR_CODE_TOTAL_TIME_POS))
+#define GLB_CR_CODE0_HIGH_TIME GLB_CR_CODE0_HIGH_TIME
+#define GLB_CR_CODE0_HIGH_TIME_POS (16U)
+#define GLB_CR_CODE0_HIGH_TIME_LEN (8U)
+#define GLB_CR_CODE0_HIGH_TIME_MSK (((1U << GLB_CR_CODE0_HIGH_TIME_LEN) - 1) << GLB_CR_CODE0_HIGH_TIME_POS)
+#define GLB_CR_CODE0_HIGH_TIME_UMSK (~(((1U << GLB_CR_CODE0_HIGH_TIME_LEN) - 1) << GLB_CR_CODE0_HIGH_TIME_POS))
+#define GLB_CR_CODE1_HIGH_TIME GLB_CR_CODE1_HIGH_TIME
+#define GLB_CR_CODE1_HIGH_TIME_POS (24U)
+#define GLB_CR_CODE1_HIGH_TIME_LEN (8U)
+#define GLB_CR_CODE1_HIGH_TIME_MSK (((1U << GLB_CR_CODE1_HIGH_TIME_LEN) - 1) << GLB_CR_CODE1_HIGH_TIME_POS)
+#define GLB_CR_CODE1_HIGH_TIME_UMSK (~(((1U << GLB_CR_CODE1_HIGH_TIME_LEN) - 1) << GLB_CR_CODE1_HIGH_TIME_POS))
+
+/* 0xB00 : gpio_cfg143 */
+#define GLB_GPIO_CFG143_OFFSET (0xB00)
+#define GLB_CR_GPIO_DMA_TX_EN GLB_CR_GPIO_DMA_TX_EN
+#define GLB_CR_GPIO_DMA_TX_EN_POS (0U)
+#define GLB_CR_GPIO_DMA_TX_EN_LEN (1U)
+#define GLB_CR_GPIO_DMA_TX_EN_MSK (((1U << GLB_CR_GPIO_DMA_TX_EN_LEN) - 1) << GLB_CR_GPIO_DMA_TX_EN_POS)
+#define GLB_CR_GPIO_DMA_TX_EN_UMSK (~(((1U << GLB_CR_GPIO_DMA_TX_EN_LEN) - 1) << GLB_CR_GPIO_DMA_TX_EN_POS))
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH GLB_CR_GPIO_DMA_OUT_SEL_LATCH
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_POS (1U)
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_LEN (1U)
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_MSK (((1U << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_LEN) - 1) << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_POS)
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_UMSK (~(((1U << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_LEN) - 1) << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_POS))
+#define GLB_GPIO_TX_FIFO_CLR GLB_GPIO_TX_FIFO_CLR
+#define GLB_GPIO_TX_FIFO_CLR_POS (2U)
+#define GLB_GPIO_TX_FIFO_CLR_LEN (1U)
+#define GLB_GPIO_TX_FIFO_CLR_MSK (((1U << GLB_GPIO_TX_FIFO_CLR_LEN) - 1) << GLB_GPIO_TX_FIFO_CLR_POS)
+#define GLB_GPIO_TX_FIFO_CLR_UMSK (~(((1U << GLB_GPIO_TX_FIFO_CLR_LEN) - 1) << GLB_GPIO_TX_FIFO_CLR_POS))
+#define GLB_GPIO_TX_END_CLR GLB_GPIO_TX_END_CLR
+#define GLB_GPIO_TX_END_CLR_POS (3U)
+#define GLB_GPIO_TX_END_CLR_LEN (1U)
+#define GLB_GPIO_TX_END_CLR_MSK (((1U << GLB_GPIO_TX_END_CLR_LEN) - 1) << GLB_GPIO_TX_END_CLR_POS)
+#define GLB_GPIO_TX_END_CLR_UMSK (~(((1U << GLB_GPIO_TX_END_CLR_LEN) - 1) << GLB_GPIO_TX_END_CLR_POS))
+#define GLB_GPIO_TX_FIFO_OVERFLOW GLB_GPIO_TX_FIFO_OVERFLOW
+#define GLB_GPIO_TX_FIFO_OVERFLOW_POS (4U)
+#define GLB_GPIO_TX_FIFO_OVERFLOW_LEN (1U)
+#define GLB_GPIO_TX_FIFO_OVERFLOW_MSK (((1U << GLB_GPIO_TX_FIFO_OVERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_OVERFLOW_POS)
+#define GLB_GPIO_TX_FIFO_OVERFLOW_UMSK (~(((1U << GLB_GPIO_TX_FIFO_OVERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_OVERFLOW_POS))
+#define GLB_GPIO_TX_FIFO_UNDERFLOW GLB_GPIO_TX_FIFO_UNDERFLOW
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_POS (5U)
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_LEN (1U)
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_MSK (((1U << GLB_GPIO_TX_FIFO_UNDERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_UNDERFLOW_POS)
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_UMSK (~(((1U << GLB_GPIO_TX_FIFO_UNDERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_UNDERFLOW_POS))
+#define GLB_CR_GPIO_DMA_PARK_VALUE GLB_CR_GPIO_DMA_PARK_VALUE
+#define GLB_CR_GPIO_DMA_PARK_VALUE_POS (7U)
+#define GLB_CR_GPIO_DMA_PARK_VALUE_LEN (1U)
+#define GLB_CR_GPIO_DMA_PARK_VALUE_MSK (((1U << GLB_CR_GPIO_DMA_PARK_VALUE_LEN) - 1) << GLB_CR_GPIO_DMA_PARK_VALUE_POS)
+#define GLB_CR_GPIO_DMA_PARK_VALUE_UMSK (~(((1U << GLB_CR_GPIO_DMA_PARK_VALUE_LEN) - 1) << GLB_CR_GPIO_DMA_PARK_VALUE_POS))
+#define GLB_GPIO_TX_FIFO_CNT GLB_GPIO_TX_FIFO_CNT
+#define GLB_GPIO_TX_FIFO_CNT_POS (8U)
+#define GLB_GPIO_TX_FIFO_CNT_LEN (8U)
+#define GLB_GPIO_TX_FIFO_CNT_MSK (((1U << GLB_GPIO_TX_FIFO_CNT_LEN) - 1) << GLB_GPIO_TX_FIFO_CNT_POS)
+#define GLB_GPIO_TX_FIFO_CNT_UMSK (~(((1U << GLB_GPIO_TX_FIFO_CNT_LEN) - 1) << GLB_GPIO_TX_FIFO_CNT_POS))
+#define GLB_CR_GPIO_TX_FIFO_TH GLB_CR_GPIO_TX_FIFO_TH
+#define GLB_CR_GPIO_TX_FIFO_TH_POS (16U)
+#define GLB_CR_GPIO_TX_FIFO_TH_LEN (7U)
+#define GLB_CR_GPIO_TX_FIFO_TH_MSK (((1U << GLB_CR_GPIO_TX_FIFO_TH_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_TH_POS)
+#define GLB_CR_GPIO_TX_FIFO_TH_UMSK (~(((1U << GLB_CR_GPIO_TX_FIFO_TH_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_TH_POS))
+#define GLB_CR_GPIO_TX_END_MASK GLB_CR_GPIO_TX_END_MASK
+#define GLB_CR_GPIO_TX_END_MASK_POS (23U)
+#define GLB_CR_GPIO_TX_END_MASK_LEN (1U)
+#define GLB_CR_GPIO_TX_END_MASK_MSK (((1U << GLB_CR_GPIO_TX_END_MASK_LEN) - 1) << GLB_CR_GPIO_TX_END_MASK_POS)
+#define GLB_CR_GPIO_TX_END_MASK_UMSK (~(((1U << GLB_CR_GPIO_TX_END_MASK_LEN) - 1) << GLB_CR_GPIO_TX_END_MASK_POS))
+#define GLB_CR_GPIO_TX_FIFO_MASK GLB_CR_GPIO_TX_FIFO_MASK
+#define GLB_CR_GPIO_TX_FIFO_MASK_POS (24U)
+#define GLB_CR_GPIO_TX_FIFO_MASK_LEN (1U)
+#define GLB_CR_GPIO_TX_FIFO_MASK_MSK (((1U << GLB_CR_GPIO_TX_FIFO_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_MASK_POS)
+#define GLB_CR_GPIO_TX_FIFO_MASK_UMSK (~(((1U << GLB_CR_GPIO_TX_FIFO_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_MASK_POS))
+#define GLB_CR_GPIO_TX_FER_MASK GLB_CR_GPIO_TX_FER_MASK
+#define GLB_CR_GPIO_TX_FER_MASK_POS (25U)
+#define GLB_CR_GPIO_TX_FER_MASK_LEN (1U)
+#define GLB_CR_GPIO_TX_FER_MASK_MSK (((1U << GLB_CR_GPIO_TX_FER_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FER_MASK_POS)
+#define GLB_CR_GPIO_TX_FER_MASK_UMSK (~(((1U << GLB_CR_GPIO_TX_FER_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FER_MASK_POS))
+#define GLB_R_GPIO_TX_END_INT GLB_R_GPIO_TX_END_INT
+#define GLB_R_GPIO_TX_END_INT_POS (26U)
+#define GLB_R_GPIO_TX_END_INT_LEN (1U)
+#define GLB_R_GPIO_TX_END_INT_MSK (((1U << GLB_R_GPIO_TX_END_INT_LEN) - 1) << GLB_R_GPIO_TX_END_INT_POS)
+#define GLB_R_GPIO_TX_END_INT_UMSK (~(((1U << GLB_R_GPIO_TX_END_INT_LEN) - 1) << GLB_R_GPIO_TX_END_INT_POS))
+#define GLB_R_GPIO_TX_FIFO_INT GLB_R_GPIO_TX_FIFO_INT
+#define GLB_R_GPIO_TX_FIFO_INT_POS (27U)
+#define GLB_R_GPIO_TX_FIFO_INT_LEN (1U)
+#define GLB_R_GPIO_TX_FIFO_INT_MSK (((1U << GLB_R_GPIO_TX_FIFO_INT_LEN) - 1) << GLB_R_GPIO_TX_FIFO_INT_POS)
+#define GLB_R_GPIO_TX_FIFO_INT_UMSK (~(((1U << GLB_R_GPIO_TX_FIFO_INT_LEN) - 1) << GLB_R_GPIO_TX_FIFO_INT_POS))
+#define GLB_R_GPIO_TX_FER_INT GLB_R_GPIO_TX_FER_INT
+#define GLB_R_GPIO_TX_FER_INT_POS (28U)
+#define GLB_R_GPIO_TX_FER_INT_LEN (1U)
+#define GLB_R_GPIO_TX_FER_INT_MSK (((1U << GLB_R_GPIO_TX_FER_INT_LEN) - 1) << GLB_R_GPIO_TX_FER_INT_POS)
+#define GLB_R_GPIO_TX_FER_INT_UMSK (~(((1U << GLB_R_GPIO_TX_FER_INT_LEN) - 1) << GLB_R_GPIO_TX_FER_INT_POS))
+#define GLB_CR_GPIO_TX_END_EN GLB_CR_GPIO_TX_END_EN
+#define GLB_CR_GPIO_TX_END_EN_POS (29U)
+#define GLB_CR_GPIO_TX_END_EN_LEN (1U)
+#define GLB_CR_GPIO_TX_END_EN_MSK (((1U << GLB_CR_GPIO_TX_END_EN_LEN) - 1) << GLB_CR_GPIO_TX_END_EN_POS)
+#define GLB_CR_GPIO_TX_END_EN_UMSK (~(((1U << GLB_CR_GPIO_TX_END_EN_LEN) - 1) << GLB_CR_GPIO_TX_END_EN_POS))
+#define GLB_CR_GPIO_TX_FIFO_EN GLB_CR_GPIO_TX_FIFO_EN
+#define GLB_CR_GPIO_TX_FIFO_EN_POS (30U)
+#define GLB_CR_GPIO_TX_FIFO_EN_LEN (1U)
+#define GLB_CR_GPIO_TX_FIFO_EN_MSK (((1U << GLB_CR_GPIO_TX_FIFO_EN_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_EN_POS)
+#define GLB_CR_GPIO_TX_FIFO_EN_UMSK (~(((1U << GLB_CR_GPIO_TX_FIFO_EN_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_EN_POS))
+#define GLB_CR_GPIO_TX_FER_EN GLB_CR_GPIO_TX_FER_EN
+#define GLB_CR_GPIO_TX_FER_EN_POS (31U)
+#define GLB_CR_GPIO_TX_FER_EN_LEN (1U)
+#define GLB_CR_GPIO_TX_FER_EN_MSK (((1U << GLB_CR_GPIO_TX_FER_EN_LEN) - 1) << GLB_CR_GPIO_TX_FER_EN_POS)
+#define GLB_CR_GPIO_TX_FER_EN_UMSK (~(((1U << GLB_CR_GPIO_TX_FER_EN_LEN) - 1) << GLB_CR_GPIO_TX_FER_EN_POS))
+
+/* 0xB04 : gpio_cfg144 */
+#define GLB_GPIO_CFG144_OFFSET (0xB04)
+#define GLB_GPIO_TX_DATA_TO_FIFO GLB_GPIO_TX_DATA_TO_FIFO
+#define GLB_GPIO_TX_DATA_TO_FIFO_POS (0U)
+#define GLB_GPIO_TX_DATA_TO_FIFO_LEN (16U)
+#define GLB_GPIO_TX_DATA_TO_FIFO_MSK (((1U << GLB_GPIO_TX_DATA_TO_FIFO_LEN) - 1) << GLB_GPIO_TX_DATA_TO_FIFO_POS)
+#define GLB_GPIO_TX_DATA_TO_FIFO_UMSK (~(((1U << GLB_GPIO_TX_DATA_TO_FIFO_LEN) - 1) << GLB_GPIO_TX_DATA_TO_FIFO_POS))
+
+struct glb_reg {
+ /* 0x0 : soc_info0 */
+ union {
+ struct {
+ uint32_t reserved_0_26 : 27; /* [26: 0], rsvd, 0x0 */
+ uint32_t chip_rdy : 1; /* [ 27], r, 0x0 */
+ uint32_t glb_id : 4; /* [31:28], r, 0x6 */
+ } BF;
+ uint32_t WORD;
+ } soc_info0;
+
+ /* 0x4 reserved */
+ uint8_t RESERVED0x4[76];
+
+ /* 0x50 : core_cfg16 */
+ union {
+ struct {
+ uint32_t np_int_sta0 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg16;
+
+ /* 0x54 : core_cfg17 */
+ union {
+ struct {
+ uint32_t np_int_sta1 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg17;
+
+ /* 0x58 : core_cfg18 */
+ union {
+ struct {
+ uint32_t np_int_mask0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg18;
+
+ /* 0x5C : core_cfg19 */
+ union {
+ struct {
+ uint32_t np_int_mask1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg19;
+
+ /* 0x60 : core_cfg20 */
+ union {
+ struct {
+ uint32_t np_int_clr0 : 32; /* [31: 0], w1c, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg20;
+
+ /* 0x64 : core_cfg21 */
+ union {
+ struct {
+ uint32_t np_int_clr1 : 32; /* [31: 0], w1c, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg21;
+
+ /* 0x68 : core_cfg22 */
+ union {
+ struct {
+ uint32_t reg_e902_int_en0 : 32; /* [31: 0], r/w, 0xffffffff */
+ } BF;
+ uint32_t WORD;
+ } core_cfg22;
+
+ /* 0x6C : core_cfg23 */
+ union {
+ struct {
+ uint32_t reg_e902_int_en1 : 32; /* [31: 0], r/w, 0xffffffff */
+ } BF;
+ uint32_t WORD;
+ } core_cfg23;
+
+ /* 0x70 : core_cfg24 */
+ union {
+ struct {
+ uint32_t sts_e902_int_bus_0 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg24;
+
+ /* 0x74 : core_cfg25 */
+ union {
+ struct {
+ uint32_t sts_e902_int_bus_1 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } core_cfg25;
+
+ /* 0x78 reserved */
+ uint8_t RESERVED0x78[24];
+
+ /* 0x90 : sys_cfg0 */
+ union {
+ struct {
+ uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_fclk_en : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_hclk_en : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reg_bclk_en : 1; /* [ 3], r/w, 0x1 */
+ uint32_t reserved_4_5 : 2; /* [ 5: 4], rsvd, 0x0 */
+ uint32_t hbn_root_clk_sel : 2; /* [ 7: 6], r, 0x0 */
+ uint32_t reg_hclk_div : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_bclk_div : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sys_cfg0;
+
+ /* 0x94 : sys_cfg1 */
+ union {
+ struct {
+ uint32_t reg_bclk_div_act_pulse : 1; /* [ 0], w1p, 0x0 */
+ uint32_t reg_bclk_div_bypass : 1; /* [ 1], r/w, 0x0 */
+ uint32_t sts_bclk_prot_done : 1; /* [ 2], r, 0x1 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t reg_bclk_sw_done_cnt : 4; /* [ 7: 4], r/w, 0x5 */
+ uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */
+ uint32_t reg_pico_clk_div_act_pulse : 1; /* [ 16], w1p, 0x0 */
+ uint32_t reg_pico_clk_div_bypass : 1; /* [ 17], r/w, 0x0 */
+ uint32_t sts_pico_clk_prot_done : 1; /* [ 18], r, 0x1 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t reg_pico_clk_sw_done_cnt : 4; /* [23:20], r/w, 0x5 */
+ uint32_t fclk_sw_state : 3; /* [26:24], r, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sys_cfg1;
+
+ /* 0x98 reserved */
+ uint8_t RESERVED0x98[8];
+
+ /* 0xA0 : bus_cfg0 */
+ union {
+ struct {
+ uint32_t rg_apb2_pck_force : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bus_cfg0;
+
+ /* 0xa4 reserved */
+ uint8_t RESERVED0xa4[60];
+
+ /* 0xE0 : emi_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_8 : 9; /* [ 8: 0], rsvd, 0x0 */
+ uint32_t reg_emi_clk_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t reserved_10_13 : 4; /* [13:10], rsvd, 0x0 */
+ uint32_t reg_emi_clk_sel : 3; /* [16:14], r/w, 0x0 */
+ uint32_t reserved_17_21 : 5; /* [21:17], rsvd, 0x0 */
+ uint32_t reg_emi_clk_div : 2; /* [23:22], r/w, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } emi_cfg0;
+
+ /* 0xe4 reserved */
+ uint8_t RESERVED0xe4[12];
+
+ /* 0xF0 : rtc_cfg0 */
+ union {
+ struct {
+ uint32_t cpu_rtc_div : 17; /* [16: 0], r/w, 0x10 */
+ uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
+ uint32_t cpu_rtc_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t cpu_rtc_sel : 1; /* [ 19], r/w, 0x1 */
+ uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } rtc_cfg0;
+
+ /* 0xf4 reserved */
+ uint8_t RESERVED0xf4[28];
+
+ /* 0x110 : adc_cfg0 */
+ union {
+ struct {
+ uint32_t gpadc_32m_clk_div : 6; /* [ 5: 0], r/w, 0x2 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t gpadc_32m_clk_sel : 1; /* [ 7], r/w, 0x0 */
+ uint32_t gpadc_32m_div_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } adc_cfg0;
+
+ /* 0x114 reserved */
+ uint8_t RESERVED0x114[12];
+
+ /* 0x120 : dac_cfg0 */
+ union {
+ struct {
+ uint32_t gpdaca_rstn_ana : 1; /* [ 0], r/w, 0x1 */
+ uint32_t gpdacb_rstn_ana : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reserved_2_6 : 5; /* [ 6: 2], rsvd, 0x0 */
+ uint32_t gpdac_test_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t gpdac_ref_sel : 1; /* [ 8], r/w, 0x0 */
+ uint32_t gpdac_test_sel : 3; /* [11: 9], r/w, 0x0 */
+ uint32_t reserved_12_23 : 12; /* [23:12], rsvd, 0x0 */
+ uint32_t gpdac_reserved : 8; /* [31:24], r/w, 0xf */
+ } BF;
+ uint32_t WORD;
+ } dac_cfg0;
+
+ /* 0x124 : dac_cfg1 */
+ union {
+ struct {
+ uint32_t gpdac_a_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t gpdac_ioa_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */
+ uint32_t gpdac_a_rng : 2; /* [19:18], r/w, 0x3 */
+ uint32_t gpdac_a_outmux : 3; /* [22:20], r/w, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dac_cfg1;
+
+ /* 0x128 : dac_cfg2 */
+ union {
+ struct {
+ uint32_t gpdac_b_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t gpdac_iob_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */
+ uint32_t gpdac_b_rng : 2; /* [19:18], r/w, 0x3 */
+ uint32_t gpdac_b_outmux : 3; /* [22:20], r/w, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dac_cfg2;
+
+ /* 0x12C : dac_cfg3 */
+ union {
+ struct {
+ uint32_t gpdac_b_data : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t gpdac_a_data : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dac_cfg3;
+
+ /* 0x130 : dma_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_23 : 24; /* [23: 0], rsvd, 0x0 */
+ uint32_t dma_clk_en : 8; /* [31:24], r/w, 0xff */
+ } BF;
+ uint32_t WORD;
+ } dma_cfg0;
+
+ /* 0x134 : dma_cfg1 */
+ union {
+ struct {
+ uint32_t reserved_0_23 : 24; /* [23: 0], rsvd, 0x0 */
+ uint32_t dma2_clk_en : 8; /* [31:24], r/w, 0xff */
+ } BF;
+ uint32_t WORD;
+ } dma_cfg1;
+
+ /* 0x138 : dma_cfg2 */
+ union {
+ struct {
+ uint32_t reg_dma_cn_sel : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dma_cfg2;
+
+ /* 0x13c reserved */
+ uint8_t RESERVED0x13c[4];
+
+ /* 0x140 : ir_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */
+ uint32_t ir_clk_div : 6; /* [21:16], r/w, 0xf */
+ uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */
+ uint32_t ir_clk_en : 1; /* [ 23], r/w, 0x1 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ir_cfg0;
+
+ /* 0x144 : ir_cfg1 */
+ union {
+ struct {
+ uint32_t led_din_reg : 1; /* [ 0], r/w, 0x0 */
+ uint32_t led_din_sel : 1; /* [ 1], r/w, 0x0 */
+ uint32_t led_din_polarity_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t leddrv_ibias : 4; /* [ 7: 4], r/w, 0x8 */
+ uint32_t ir_rx_gpio_sel : 4; /* [11: 8], r/w, 0x0 */
+ uint32_t reserved_12_30 : 19; /* [30:12], rsvd, 0x0 */
+ uint32_t pu_leddrv : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ir_cfg1;
+
+ /* 0x148 reserved */
+ uint8_t RESERVED0x148[8];
+
+ /* 0x150 : uart_cfg0 */
+ union {
+ struct {
+ uint32_t uart_clk_div : 3; /* [ 2: 0], r/w, 0x7 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t uart_clk_en : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */
+ uint32_t hbn_uart_clk_sel : 1; /* [ 7], r, 0x0 */
+ uint32_t reserved_8_21 : 14; /* [21: 8], rsvd, 0x0 */
+ uint32_t hbn_uart_clk_sel2 : 1; /* [ 22], r, 0x0 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t uart2_io_sel : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uart_cfg0;
+
+ /* 0x154 : uart_cfg1 */
+ union {
+ struct {
+ uint32_t uart_sig_0_sel : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t uart_sig_1_sel : 4; /* [ 7: 4], r/w, 0x1 */
+ uint32_t uart_sig_2_sel : 4; /* [11: 8], r/w, 0x2 */
+ uint32_t uart_sig_3_sel : 4; /* [15:12], r/w, 0x3 */
+ uint32_t uart_sig_4_sel : 4; /* [19:16], r/w, 0x4 */
+ uint32_t uart_sig_5_sel : 4; /* [23:20], r/w, 0x5 */
+ uint32_t uart_sig_6_sel : 4; /* [27:24], r/w, 0x6 */
+ uint32_t uart_sig_7_sel : 4; /* [31:28], r/w, 0x7 */
+ } BF;
+ uint32_t WORD;
+ } uart_cfg1;
+
+ /* 0x158 : uart_cfg2 */
+ union {
+ struct {
+ uint32_t uart_sig_8_sel : 4; /* [ 3: 0], r/w, 0x8 */
+ uint32_t uart_sig_9_sel : 4; /* [ 7: 4], r/w, 0x9 */
+ uint32_t uart_sig_10_sel : 4; /* [11: 8], r/w, 0xa */
+ uint32_t uart_sig_11_sel : 4; /* [15:12], r/w, 0xb */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uart_cfg2;
+
+ /* 0x15c reserved */
+ uint8_t RESERVED0x15c[20];
+
+ /* 0x170 : sf_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */
+ uint32_t sf_clk_div : 3; /* [10: 8], r/w, 0x3 */
+ uint32_t sf_clk_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t sf_clk_sel : 2; /* [13:12], r/w, 0x2 */
+ uint32_t sf_clk_sel2 : 2; /* [15:14], r/w, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_cfg0;
+
+ /* 0x174 reserved */
+ uint8_t RESERVED0x174[12];
+
+ /* 0x180 : i2c_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */
+ uint32_t i2c_clk_div : 8; /* [23:16], r/w, 0xff */
+ uint32_t i2c_clk_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t i2c_clk_sel : 1; /* [ 25], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } i2c_cfg0;
+
+ /* 0x184 reserved */
+ uint8_t RESERVED0x184[12];
+
+ /* 0x190 : i2s_cfg0 */
+ union {
+ struct {
+ uint32_t reg_i2s_ref_clk_div : 6; /* [ 5: 0], r/w, 0x1 */
+ uint32_t reg_i2s_di_ref_clk_sel : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_i2s_ref_clk_en : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reg_i2s_do_ref_clk_sel : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } i2s_cfg0;
+
+ /* 0x194 reserved */
+ uint8_t RESERVED0x194[28];
+
+ /* 0x1B0 : spi_cfg0 */
+ union {
+ struct {
+ uint32_t spi_clk_div : 5; /* [ 4: 0], r/w, 0x3 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t spi_clk_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t spi_clk_sel : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t spi_swap_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } spi_cfg0;
+
+ /* 0x1b4 reserved */
+ uint8_t RESERVED0x1b4[12];
+
+ /* 0x1C0 : qdec_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } qdec_cfg0;
+
+ /* 0x1c4 reserved */
+ uint8_t RESERVED0x1c4[12];
+
+ /* 0x1D0 : pwm_cfg0 */
+ union {
+ struct {
+ uint32_t reg_pwm1_io_sel : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_pwm2_io_sel : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pwm_cfg0;
+
+ /* 0x1d4 reserved */
+ uint8_t RESERVED0x1d4[12];
+
+ /* 0x1E0 : pdm_cfg0 */
+ union {
+ struct {
+ uint32_t reg_pdm_io_sel : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pdm_cfg0;
+
+ /* 0x1e4 reserved */
+ uint8_t RESERVED0x1e4[108];
+
+ /* 0x250 : dig_clk_cfg0 */
+ union {
+ struct {
+ uint32_t dig_32k_div : 11; /* [10: 0], r/w, 0x3e8 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t dig_32k_en : 1; /* [ 12], r/w, 0x1 */
+ uint32_t dig_32k_comp : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t dig_512k_div : 7; /* [22:16], r/w, 0x3e */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t dig_512k_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t dig_512k_comp : 1; /* [ 25], r/w, 0x1 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t dig_clk_src_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */
+ uint32_t reg_en_platform_wakeup : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dig_clk_cfg0;
+
+ /* 0x254 : dig_clk_cfg1 */
+ union {
+ struct {
+ uint32_t reg_mm_muxpll_160m_sel : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_mm_muxpll_240m_sel : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_mm_muxpll_320m_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
+ uint32_t reg_top_muxpll_80m_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reg_top_muxpll_160m_sel : 2; /* [11:10], r/w, 0x0 */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dig_clk_cfg1;
+
+ /* 0x258 : dig_clk_cfg2 */
+ union {
+ struct {
+ uint32_t chip_clk_out_0_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t chip_clk_out_1_sel : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t chip_clk_out_2_sel : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t chip_clk_out_3_sel : 2; /* [ 7: 6], r/w, 0x0 */
+ uint32_t chip_clk_out_0_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t chip_clk_out_1_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t chip_clk_out_2_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t chip_clk_out_3_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t gpio_tmr_clk_sel : 2; /* [13:12], r/w, 0x0 */
+ uint32_t gpio_mm_tmr_clk_sel : 2; /* [15:14], r/w, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dig_clk_cfg2;
+
+ /* 0x25C : dig_clk_cfg3 */
+ union {
+ struct {
+ uint32_t dsi_txclkesc_sel : 1; /* [ 0], r/w, 0x0 */
+ uint32_t csi_txclkesc_sel : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dig_clk_cfg3;
+
+ /* 0x260 : rf_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_8 : 9; /* [ 8: 0], rsvd, 0x0 */
+ uint32_t cfg_inv_rf2_test_clk_o : 1; /* [ 9], r/w, 0x1 */
+ uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } rf_cfg0;
+
+ /* 0x264 reserved */
+ uint8_t RESERVED0x264[124];
+
+ /* 0x2E0 : dbg_cfg0 */
+ union {
+ struct {
+ uint32_t reg_dbg_ll_ctrl : 30; /* [29: 0], r/w, 0x0 */
+ uint32_t reg_dbg_ll_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dbg_cfg0;
+
+ /* 0x2E4 : dbg_cfg1 */
+ union {
+ struct {
+ uint32_t reg_dbg_lh_ctrl : 30; /* [29: 0], r/w, 0x0 */
+ uint32_t reg_dbg_lh_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dbg_cfg1;
+
+ /* 0x2E8 : dbg_cfg2 */
+ union {
+ struct {
+ uint32_t reg_dbg_hl_ctrl : 30; /* [29: 0], r/w, 0x0 */
+ uint32_t reg_dbg_hl_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dbg_cfg2;
+
+ /* 0x2EC : dbg_cfg3 */
+ union {
+ struct {
+ uint32_t reg_dbg_hh_ctrl : 30; /* [29: 0], r/w, 0x0 */
+ uint32_t reg_dbg_hh_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dbg_cfg3;
+
+ /* 0x2F0 : dbg_cfg4 */
+ union {
+ struct {
+ uint32_t debug_oe : 1; /* [ 0], r/w, 0x0 */
+ uint32_t debug_i : 31; /* [31: 1], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dbg_cfg4;
+
+ /* 0x2f4 reserved */
+ uint8_t RESERVED0x2f4[12];
+
+ /* 0x300 : mbist_cfg0 */
+ union {
+ struct {
+ uint32_t mbist_mode : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mbist_cfg0;
+
+ /* 0x304 reserved */
+ uint8_t RESERVED0x304[28];
+
+ /* 0x320 : bmx_cfg0 */
+ union {
+ struct {
+ uint32_t reg_bmx_timeout_en : 5; /* [ 4: 0], r/w, 0x0 */
+ uint32_t reg_bmx_arb_mode : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_bmx_timeout_clr : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_h_wthre_hw2ext : 2; /* [ 8: 7], r/w, 0x0 */
+ uint32_t bmx_busy_option_dis : 1; /* [ 9], r/w, 0x0 */
+ uint32_t bmx_gating_dis : 1; /* [ 10], r/w, 0x0 */
+ uint32_t sts_bmx_timeout_sts : 5; /* [15:11], r, 0x0 */
+ uint32_t pds_apb_cfg : 8; /* [23:16], r/w, 0x0 */
+ uint32_t hbn_apb_cfg : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bmx_cfg0;
+
+ /* 0x324 : bmx_cfg1 */
+ union {
+ struct {
+ uint32_t reg_bmx_berr_int_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_mcu_berr_int_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */
+ uint32_t reg_bmx_qos_cpu : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reg_bmx_qos_sdu : 1; /* [ 17], r/w, 0x0 */
+ uint32_t reg_bmx_qos_sec0 : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reg_bmx_qos_sec1 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t reg_bmx_qos_sec2 : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_bmx_qos_dma : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reg_bmx_qos_cci : 1; /* [ 22], r/w, 0x0 */
+ uint32_t reg_bmx_qos_pldma : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reg_bmx_qos_blem : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_bmx_qos_emacA : 1; /* [ 25], r/w, 0x0 */
+ uint32_t reg_bmx_qos_dma2 : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reg_bmx_qos_sdhm : 1; /* [ 27], r/w, 0x0 */
+ uint32_t bmx_dbg_sel : 4; /* [31:28], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bmx_cfg1;
+
+ /* 0x328 : bmx_cfg2 */
+ union {
+ struct {
+ uint32_t reg_bmx_berr_en : 14; /* [13: 0], r/w, 0x3fff */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t reg_mcu_berr_en : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bmx_cfg2;
+
+ /* 0x32C : bmx_cfg3 */
+ union {
+ struct {
+ uint32_t reg_bmx_berr_clr : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_bmx_berr_last : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t reg_mcu_berr_clr : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_mcu_berr_last : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sts_bmx_berr : 1; /* [ 16], r, 0x0 */
+ uint32_t sts_mcu_berr : 1; /* [ 17], r, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t sts_bmx_berr_write : 1; /* [ 24], r, 0x0 */
+ uint32_t sts_mcu_berr_write : 1; /* [ 25], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bmx_cfg3;
+
+ /* 0x330 : bmx_cfg4 */
+ union {
+ struct {
+ uint32_t sts_bmx_berr_src : 14; /* [13: 0], r, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t sts_mcu_berr_src : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
+ uint32_t sts_mcu_berr_id : 8; /* [31:24], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bmx_cfg4;
+
+ /* 0x334 : bmx_cfg5 */
+ union {
+ struct {
+ uint32_t sts_bmx_berr_addr : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bmx_cfg5;
+
+ /* 0x338 : bmx_cfg6 */
+ union {
+ struct {
+ uint32_t sts_mcu_berr_addr : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } bmx_cfg6;
+
+ /* 0x33c reserved */
+ uint8_t RESERVED0x33c[4];
+
+ /* 0x340 : audio_cfg0 */
+ union {
+ struct {
+ uint32_t reg_audio_pdm_clk_div : 6; /* [ 5: 0], r/w, 0x3 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t reg_audio_pdm_clk_en : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reg_audio_adc_clk_div : 6; /* [13: 8], r/w, 0x3 */
+ uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */
+ uint32_t reg_audio_adc_clk_en : 1; /* [ 15], r/w, 0x1 */
+ uint32_t reg_audio_dac_clk_div : 6; /* [21:16], r/w, 0x3 */
+ uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */
+ uint32_t reg_audio_dac_clk_en : 1; /* [ 23], r/w, 0x1 */
+ uint32_t reserved_24_30 : 7; /* [30:24], rsvd, 0x0 */
+ uint32_t reg_audio_auto_div_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } audio_cfg0;
+
+ /* 0x344 : audio_cfg1 */
+ union {
+ struct {
+ uint32_t reg_padc_clk_div : 10; /* [ 9: 0], r/w, 0x60 */
+ uint32_t reg_padc_clk_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } audio_cfg1;
+
+ /* 0x348 reserved */
+ uint8_t RESERVED0x348[72];
+
+ /* 0x390 : eth_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_4 : 5; /* [ 4: 0], rsvd, 0x0 */
+ uint32_t cfg_sel_eth_ref_clk_o : 1; /* [ 5], r/w, 0x0 */
+ uint32_t cfg_inv_eth_ref_clk_o : 1; /* [ 6], r/w, 0x1 */
+ uint32_t cfg_inv_eth_tx_clk : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */
+ uint32_t cfg_inv_eth_rx_clk : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } eth_cfg0;
+
+ /* 0x394 reserved */
+ uint8_t RESERVED0x394[140];
+
+ /* 0x420 : cam_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_26 : 27; /* [26: 0], rsvd, 0x0 */
+ uint32_t reg_cam_ref_clk_en : 1; /* [ 27], r/w, 0x0 */
+ uint32_t reg_cam_ref_clk_src_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t reg_cam_ref_clk_div : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cam_cfg0;
+
+ /* 0x424 reserved */
+ uint8_t RESERVED0x424[12];
+
+ /* 0x430 : sdh_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_8 : 9; /* [ 8: 0], rsvd, 0x0 */
+ uint32_t reg_sdh_clk_div : 3; /* [11: 9], r/w, 0x0 */
+ uint32_t reg_sdh_clk_sel : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_sdh_clk_en : 1; /* [ 13], r/w, 0x1 */
+ uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sdh_cfg0;
+
+ /* 0x434 reserved */
+ uint8_t RESERVED0x434[92];
+
+ /* 0x490 : tzc_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
+ uint32_t tzc_glb_pwron_rst_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t tzc_glb_cpu_reset_lock : 1; /* [ 13], r, 0x0 */
+ uint32_t tzc_glb_sys_reset_lock : 1; /* [ 14], r, 0x0 */
+ uint32_t tzc_glb_cpu2_reset_lock : 1; /* [ 15], r, 0x0 */
+ uint32_t reserved_16_20 : 5; /* [20:16], rsvd, 0x0 */
+ uint32_t tzc_glb_pwr_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_glb_int_lock : 1; /* [ 22], r, 0x0 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t tzc_glb_cpupll_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_glb_misc_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_glb_sram_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t tzc_glb_swrst_lock : 1; /* [ 27], r, 0x0 */
+ uint32_t tzc_glb_bmx_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t tzc_glb_dbg_lock : 1; /* [ 29], r, 0x0 */
+ uint32_t tzc_glb_mbist_lock : 1; /* [ 30], r, 0x0 */
+ uint32_t tzc_glb_clk_lock : 1; /* [ 31], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_cfg0;
+
+ /* 0x494 reserved */
+ uint8_t RESERVED0x494[124];
+
+ /* 0x510 : glb_parm_cfg0 */
+ union {
+ struct {
+ uint32_t reg_bd_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t uart_swap_set : 4; /* [ 5: 2], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t swap_sflash_io_3_io_0 : 1; /* [ 8], r/w, 0x1 */
+ uint32_t sel_embedded_sflash : 1; /* [ 9], r/w, 0x1 */
+ uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
+ uint32_t reg_sel_psram0_x16 : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reg_spi_0_master_mode : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_spi_0_swap : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reg_sel_dbi_type_c : 1; /* [ 14], r/w, 0x0 */
+ uint32_t ant_switch_sel : 1; /* [ 15], r/w, 0x0 */
+ uint32_t reserved_16 : 1; /* [ 16], rsvd, 0x0 */
+ uint32_t p1_adc_test_with_cci : 1; /* [ 17], r/w, 0x0 */
+ uint32_t p2_dac_test_with_cci : 1; /* [ 18], r/w, 0x0 */
+ uint32_t p3_cci_use_io_2_5 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t p4_adc_test_with_jtag : 1; /* [ 20], r/w, 0x0 */
+ uint32_t p5_dac_test_with_jtag : 1; /* [ 21], r/w, 0x0 */
+ uint32_t p6_sdh_use_io_0_5 : 1; /* [ 22], r/w, 0x0 */
+ uint32_t p7_jtag_use_io_2_5 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reserved_24 : 1; /* [ 24], rsvd, 0x0 */
+ uint32_t rf1_test_mode : 2; /* [26:25], r/w, 0x0 */
+ uint32_t reg_mm_spi_master_mode : 1; /* [ 27], r/w, 0x0 */
+ uint32_t reg_mm_spi_swap : 1; /* [ 28], r/w, 0x0 */
+ uint32_t audio_test_mode : 1; /* [ 29], r/w, 0x0 */
+ uint32_t sel_rf_audio_test : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } glb_parm_cfg0;
+
+ /* 0x514 reserved */
+ uint8_t RESERVED0x514[12];
+
+ /* 0x520 : debug_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } debug_cfg0;
+
+ /* 0x524 : debug_cfg1 */
+ union {
+ struct {
+ uint32_t reserved_0_19 : 20; /* [19: 0], rsvd, 0x0 */
+ uint32_t debug_ndreset_gate : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } debug_cfg1;
+
+ /* 0x528 reserved */
+ uint8_t RESERVED0x528[8];
+
+ /* 0x530 : reset_sts0 */
+ union {
+ struct {
+ uint32_t top_reset_recorder : 7; /* [ 6: 0], r, 0x0 */
+ uint32_t clr_top_reset_recorder : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } reset_sts0;
+
+ /* 0x534 reserved */
+ uint8_t RESERVED0x534[12];
+
+ /* 0x540 : swrst_s1_ext + swrst_s3 + swrst_s2 */
+ union {
+ struct {
+ uint32_t swrst_s00 : 1; /* [ 0], r/w, 0x0 */
+ uint32_t swrst_s01 : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t swrst_s20 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t swrst_s30 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t swrst_s31 : 1; /* [ 9], r/w, 0x0 */
+ uint32_t swrst_s32 : 1; /* [ 10], r/w, 0x0 */
+ uint32_t swrst_s33 : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t swrst_s1_ext_emi_misc : 1; /* [ 16], r/w, 0x0 */
+ uint32_t swrst_s1_ext_psram0_ctrl : 1; /* [ 17], r/w, 0x0 */
+ uint32_t swrst_s1_ext_psram1_ctrl : 1; /* [ 18], r/w, 0x0 */
+ uint32_t swrst_s1_ext_usb : 1; /* [ 19], r/w, 0x0 */
+ uint32_t swrst_s1_ext_mix2 : 1; /* [ 20], r/w, 0x0 */
+ uint32_t swrst_s1_ext_audio : 1; /* [ 21], r/w, 0x0 */
+ uint32_t swrst_s1_ext_sdh : 1; /* [ 22], r/w, 0x0 */
+ uint32_t swrst_s1_ext_emac : 1; /* [ 23], r/w, 0x0 */
+ uint32_t swrst_s1_ext_dma2 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } swrst_cfg0;
+
+ /* 0x544 : swrst_s1 */
+ union {
+ struct {
+ uint32_t swrst_s10 : 1; /* [ 0], r/w, 0x0 */
+ uint32_t swrst_s11 : 1; /* [ 1], r/w, 0x0 */
+ uint32_t swrst_s12 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t swrst_s13 : 1; /* [ 3], r/w, 0x0 */
+ uint32_t swrst_s14 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t swrst_s15 : 1; /* [ 5], r/w, 0x0 */
+ uint32_t swrst_s16 : 1; /* [ 6], r/w, 0x0 */
+ uint32_t swrst_s17 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t swrst_s18 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t swrst_s19 : 1; /* [ 9], r/w, 0x0 */
+ uint32_t swrst_s1a : 1; /* [ 10], r/w, 0x0 */
+ uint32_t swrst_s1b : 1; /* [ 11], r/w, 0x0 */
+ uint32_t swrst_s1c : 1; /* [ 12], r/w, 0x0 */
+ uint32_t swrst_s1d : 1; /* [ 13], r/w, 0x0 */
+ uint32_t swrst_s1e : 1; /* [ 14], r/w, 0x0 */
+ uint32_t swrst_s1f : 1; /* [ 15], r/w, 0x0 */
+ uint32_t swrst_s1a0 : 1; /* [ 16], r/w, 0x0 */
+ uint32_t swrst_s1a1 : 1; /* [ 17], r/w, 0x0 */
+ uint32_t swrst_s1a2 : 1; /* [ 18], r/w, 0x0 */
+ uint32_t swrst_s1a3 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t swrst_s1a4 : 1; /* [ 20], r/w, 0x0 */
+ uint32_t swrst_s1a5 : 1; /* [ 21], r/w, 0x0 */
+ uint32_t swrst_s1a6 : 1; /* [ 22], r/w, 0x0 */
+ uint32_t swrst_s1a7 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t swrst_s1a8 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t swrst_s1a9 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t swrst_s1aa : 1; /* [ 26], r/w, 0x0 */
+ uint32_t swrst_s1ab : 1; /* [ 27], r/w, 0x0 */
+ uint32_t swrst_s1ac : 1; /* [ 28], r/w, 0x0 */
+ uint32_t swrst_s1ad : 1; /* [ 29], r/w, 0x0 */
+ uint32_t swrst_s1ae : 1; /* [ 30], r/w, 0x0 */
+ uint32_t swrst_s1af : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } swrst_cfg1;
+
+ /* 0x548 : swrst_cfg2 */
+ union {
+ struct {
+ uint32_t reg_ctrl_pwron_rst : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_ctrl_cpu_reset : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_ctrl_sys_reset : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_ctrl_pico_reset : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg_ctrl_cpu2_reset : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reg_ctrl_chip_reset : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_wl_wdt_reset_mm_en : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_mmwdt2wl_rst_msk : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reserved_8_23 : 16; /* [23: 8], rsvd, 0x0 */
+ uint32_t pka_clk_sel : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_27 : 3; /* [27:25], rsvd, 0x0 */
+ uint32_t reg_ctrl_reset_dummy : 4; /* [31:28], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } swrst_cfg2;
+
+ /* 0x54C : Disable hreset */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t disrst_s12 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t disrst_s14 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t disrst_s18 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_10 : 2; /* [10: 9], rsvd, 0x0 */
+ uint32_t disrst_s1b : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t disrst_s1a0 : 1; /* [ 16], r/w, 0x0 */
+ uint32_t disrst_s1a1 : 1; /* [ 17], r/w, 0x0 */
+ uint32_t disrst_s1a2 : 1; /* [ 18], r/w, 0x0 */
+ uint32_t disrst_s1a3 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t disrst_s1a4 : 1; /* [ 20], r/w, 0x0 */
+ uint32_t disrst_s1a5 : 1; /* [ 21], r/w, 0x0 */
+ uint32_t disrst_s1a6 : 1; /* [ 22], r/w, 0x0 */
+ uint32_t disrst_s1a7 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t disrst_s1a8 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t disrst_s1a9 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t disrst_s1aa : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } swrst_cfg3;
+
+ /* 0x550 reserved */
+ uint8_t RESERVED0x550[48];
+
+ /* 0x580 : cgen_m */
+ union {
+ struct {
+ uint32_t cgen_m_cpu : 1; /* [ 0], r/w, 0x1 */
+ uint32_t cgen_m_sdu : 1; /* [ 1], r/w, 0x1 */
+ uint32_t cgen_m_sec : 1; /* [ 2], r/w, 0x1 */
+ uint32_t cgen_m_dma : 1; /* [ 3], r/w, 0x1 */
+ uint32_t cgen_m_cci : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cgen_cfg0;
+
+ /* 0x584 : cgen_s1a + cgen_s1 */
+ union {
+ struct {
+ uint32_t cgen_s1_rsvd0 : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t cgen_s1_gpip : 1; /* [ 2], r/w, 0x1 */
+ uint32_t cgen_s1_sec_dbg : 1; /* [ 3], r/w, 0x1 */
+ uint32_t cgen_s1_sec_eng : 1; /* [ 4], r/w, 0x1 */
+ uint32_t cgen_s1_tz : 1; /* [ 5], r/w, 0x1 */
+ uint32_t cgen_s1_rsvd6 : 1; /* [ 6], r/w, 0x1 */
+ uint32_t cgen_s1_ef_ctrl : 1; /* [ 7], r/w, 0x1 */
+ uint32_t cgen_s1_rsvd8 : 1; /* [ 8], r/w, 0x1 */
+ uint32_t cgen_s1_rsvd9 : 1; /* [ 9], r/w, 0x1 */
+ uint32_t cgen_s1_rsvd10 : 1; /* [ 10], r/w, 0x1 */
+ uint32_t cgen_s1_sf_ctrl : 1; /* [ 11], r/w, 0x1 */
+ uint32_t cgen_s1_dma : 1; /* [ 12], r/w, 0x0 */
+ uint32_t cgen_s1_rsvd13 : 1; /* [ 13], r/w, 0x0 */
+ uint32_t cgen_s1_rsvd14 : 1; /* [ 14], r/w, 0x1 */
+ uint32_t cgen_s1_rsvd15 : 1; /* [ 15], r/w, 0x1 */
+ uint32_t cgen_s1a_uart0 : 1; /* [ 16], r/w, 0x1 */
+ uint32_t cgen_s1a_uart1 : 1; /* [ 17], r/w, 0x1 */
+ uint32_t cgen_s1a_spi : 1; /* [ 18], r/w, 0x0 */
+ uint32_t cgen_s1a_i2c : 1; /* [ 19], r/w, 0x0 */
+ uint32_t cgen_s1a_pwm : 1; /* [ 20], r/w, 0x0 */
+ uint32_t cgen_s1a_timer : 1; /* [ 21], r/w, 0x1 */
+ uint32_t cgen_s1a_ir : 1; /* [ 22], r/w, 0x0 */
+ uint32_t cgen_s1a_cks : 1; /* [ 23], r/w, 0x0 */
+ uint32_t cgen_s1a_rsvd8 : 1; /* [ 24], r/w, 0x1 */
+ uint32_t cgen_s1a_i2c1 : 1; /* [ 25], r/w, 0x1 */
+ uint32_t cgen_s1a_uart2 : 1; /* [ 26], r/w, 0x0 */
+ uint32_t cgen_s1a_rsvd11 : 1; /* [ 27], r/w, 0x1 */
+ uint32_t cgen_s1a_rsvd12 : 1; /* [ 28], r/w, 0x1 */
+ uint32_t cgen_s1a_rsvd13 : 1; /* [ 29], r/w, 0x0 */
+ uint32_t cgen_s1a_rsvd14 : 1; /* [ 30], r/w, 0x0 */
+ uint32_t cgen_s1a_rsvd15 : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } cgen_cfg1;
+
+ /* 0x588 : cgen_s1_ext + cgen_s3 */
+ union {
+ struct {
+ uint32_t cgen_s0 : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t cgen_s2_wifi : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reserved_5_9 : 5; /* [ 9: 5], rsvd, 0x0 */
+ uint32_t cgen_s3_bt_ble2 : 1; /* [ 10], r/w, 0x1 */
+ uint32_t cgen_s3_m1542 : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t cgen_s1_ext_emi_misc : 1; /* [ 16], r/w, 0x1 */
+ uint32_t cgen_s1_ext_psram0_ctrl : 1; /* [ 17], r/w, 0x1 */
+ uint32_t cgen_s1_ext_psram_ctrl : 1; /* [ 18], r/w, 0x1 */
+ uint32_t cgen_s1_ext_usb : 1; /* [ 19], r/w, 0x1 */
+ uint32_t cgen_s1_ext_mix2 : 1; /* [ 20], r/w, 0x1 */
+ uint32_t cgen_s1_ext_audio : 1; /* [ 21], r/w, 0x1 */
+ uint32_t cgen_s1_ext_sdh : 1; /* [ 22], r/w, 0x1 */
+ uint32_t cgen_s1_ext_emac : 1; /* [ 23], r/w, 0x1 */
+ uint32_t cgen_s1_ext_dma2 : 1; /* [ 24], r/w, 0x1 */
+ uint32_t cgen_s1_ext_rsvd9 : 1; /* [ 25], r/w, 0x1 */
+ uint32_t cgen_s1_ext_rsvd10 : 1; /* [ 26], r/w, 0x1 */
+ uint32_t cgen_s1_ext_rsvd11 : 1; /* [ 27], r/w, 0x1 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cgen_cfg2;
+
+ /* 0x58C : cgen_cfg3 */
+ union {
+ struct {
+ uint32_t cgen_mm_wifipll_160m : 1; /* [ 0], r/w, 0x1 */
+ uint32_t cgen_mm_wifipll_240m : 1; /* [ 1], r/w, 0x1 */
+ uint32_t cgen_mm_wifipll_320m : 1; /* [ 2], r/w, 0x1 */
+ uint32_t cgen_mm_aupll_div1 : 1; /* [ 3], r/w, 0x1 */
+ uint32_t cgen_mm_aupll_div2 : 1; /* [ 4], r/w, 0x1 */
+ uint32_t cgen_emi_cpupll_400m : 1; /* [ 5], r/w, 0x1 */
+ uint32_t cgen_emi_cpupll_200m : 1; /* [ 6], r/w, 0x1 */
+ uint32_t cgen_emi_wifipll_320m : 1; /* [ 7], r/w, 0x1 */
+ uint32_t cgen_emi_aupll_div1 : 1; /* [ 8], r/w, 0x1 */
+ uint32_t cgen_top_cpupll_80m : 1; /* [ 9], r/w, 0x1 */
+ uint32_t cgen_top_cpupll_100m : 1; /* [ 10], r/w, 0x1 */
+ uint32_t cgen_top_cpupll_160m : 1; /* [ 11], r/w, 0x1 */
+ uint32_t cgen_top_cpupll_400m : 1; /* [ 12], r/w, 0x1 */
+ uint32_t cgen_top_wifipll_240m : 1; /* [ 13], r/w, 0x1 */
+ uint32_t cgen_top_wifipll_320m : 1; /* [ 14], r/w, 0x1 */
+ uint32_t cgen_top_aupll_div2 : 1; /* [ 15], r/w, 0x1 */
+ uint32_t cgen_top_aupll_div1 : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cgen_cfg3;
+
+ /* 0x590 reserved */
+ uint8_t RESERVED0x590[48];
+
+ /* 0x5C0 : hw_rsv0 */
+ union {
+ struct {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } hw_rsv0;
+
+ /* 0x5C4 : hw_rsv1 */
+ union {
+ struct {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } hw_rsv1;
+
+ /* 0x5C8 : hw_rsv2 */
+ union {
+ struct {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } hw_rsv2;
+
+ /* 0x5CC : hw_rsv3 */
+ union {
+ struct {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0xffffffff */
+ } BF;
+ uint32_t WORD;
+ } hw_rsv3;
+
+ /* 0x5d0 reserved */
+ uint8_t RESERVED0x5d0[48];
+
+ /* 0x600 : reg_sram_ret */
+ union {
+ struct {
+ uint32_t cr_mcu_cache_ret : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t cr_mcu_hsram_ret : 4; /* [ 5: 2], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t cr_wb_ram_ret : 1; /* [ 8], r/w, 0x0 */
+ uint32_t cr_misc_ram_ret : 2; /* [10: 9], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sram_cfg0;
+
+ /* 0x604 : reg_sram_slp */
+ union {
+ struct {
+ uint32_t cr_mcu_cache_slp : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t cr_mcu_hsram_slp : 4; /* [ 5: 2], r/w, 0x0 */
+ uint32_t cr_mcu_rom_slp : 2; /* [ 7: 6], r/w, 0x0 */
+ uint32_t cr_wb_ram_slp : 1; /* [ 8], r/w, 0x0 */
+ uint32_t cr_misc_ram_slp : 2; /* [10: 9], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sram_cfg1;
+
+ /* 0x608 : reg_sram_parm */
+ union {
+ struct {
+ uint32_t cr_mcu_cache_dvse : 1; /* [ 0], r/w, 0x0 */
+ uint32_t cr_mcu_hsram_dvse : 1; /* [ 1], r/w, 0x0 */
+ uint32_t cr_mcu_rom_dvse : 1; /* [ 2], r/w, 0x0 */
+ uint32_t cr_wb_ram_dvse : 1; /* [ 3], r/w, 0x0 */
+ uint32_t cr_misc_ram_dvse : 1; /* [ 4], r/w, 0x0 */
+ uint32_t cr_ocram_dvse : 1; /* [ 5], r/w, 0x0 */
+ uint32_t cr_wram_dvse : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t cr_mcu_cache_nap : 1; /* [ 8], r/w, 0x0 */
+ uint32_t cr_mcu_hsram_nap : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
+ uint32_t cr_wb_ram_nap : 1; /* [ 11], r/w, 0x0 */
+ uint32_t cr_misc_ram_nap : 1; /* [ 12], r/w, 0x0 */
+ uint32_t cr_ocram_nap : 1; /* [ 13], r/w, 0x0 */
+ uint32_t cr_wram_nap : 1; /* [ 14], r/w, 0x0 */
+ uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sram_cfg2;
+
+ /* 0x60C : sram_cfg3 */
+ union {
+ struct {
+ uint32_t em_sel : 8; /* [ 7: 0], r/w, 0x3 */
+ uint32_t reserved_8_27 : 20; /* [27: 8], rsvd, 0x0 */
+ uint32_t reg_vram_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sram_cfg3;
+
+ /* 0x610 : reg_sram_parm2 */
+ union {
+ struct {
+ uint32_t cr_mcu_cache_dvs : 4; /* [ 3: 0], r/w, 0xc */
+ uint32_t cr_mcu_hsram_dvs : 4; /* [ 7: 4], r/w, 0xc */
+ uint32_t cr_mcu_rom_dvs : 4; /* [11: 8], r/w, 0xc */
+ uint32_t cr_wb_ram_dvs : 4; /* [15:12], r/w, 0xc */
+ uint32_t cr_misc_ram_dvs : 4; /* [19:16], r/w, 0xc */
+ uint32_t cr_ocram_dvs : 4; /* [23:20], r/w, 0xc */
+ uint32_t cr_wram_dvs : 4; /* [27:24], r/w, 0xc */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sram_cfg4;
+
+ /* 0x614 reserved */
+ uint8_t RESERVED0x614[12];
+
+ /* 0x620 : psram_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_26 : 27; /* [26: 0], rsvd, 0x0 */
+ uint32_t reg_psramB_clk_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t reg_psramB_clk_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t reg_psramB_clk_div : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_cfg0;
+
+ /* 0x624 reserved */
+ uint8_t RESERVED0x624[156];
+
+ /* 0x6C0 : ldo28cis */
+ union {
+ struct {
+ uint32_t pu_ldo28cis : 1; /* [ 0], r/w, 0x1 */
+ uint32_t ldo28cis_bypass : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ldo28cis_pulldown : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ldo28cis_pulldown_sel : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ldo28cis_bm : 3; /* [ 6: 4], r/w, 0x5 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t ldo28cis_cc : 3; /* [10: 8], r/w, 0x3 */
+ uint32_t ldo28cis_ocp_out : 1; /* [ 11], r, 0x0 */
+ uint32_t ldo28cis_ocp_th : 3; /* [14:12], r/w, 0x3 */
+ uint32_t ldo28cis_ocp_en : 1; /* [ 15], r/w, 0x1 */
+ uint32_t ldo28cis_sstart_delay : 3; /* [18:16], r/w, 0x2 */
+ uint32_t ldo28cis_sstart_en : 1; /* [ 19], r/w, 0x1 */
+ uint32_t ldo28cis_vout_sel : 4; /* [23:20], r/w, 0x3 */
+ uint32_t ldo28cis_vout_trim : 4; /* [27:24], r/w, 0x8 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ldo28cis;
+
+ /* 0x6C4 : ldo18io */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ldo18io;
+
+ /* 0x6C8 : ldo15cis */
+ union {
+ struct {
+ uint32_t pu_ldo15cis : 1; /* [ 0], r/w, 0x1 */
+ uint32_t ldo15cis_bypass : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ldo15cis_pulldown : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ldo15cis_pulldown_sel : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ldo15cis_bm : 3; /* [ 6: 4], r/w, 0x2 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t ldo15cis_cc : 3; /* [10: 8], r/w, 0x3 */
+ uint32_t ldo15cis_ocp_out : 1; /* [ 11], r, 0x0 */
+ uint32_t ldo15cis_ocp_th : 3; /* [14:12], r/w, 0x3 */
+ uint32_t ldo15cis_ocp_en : 1; /* [ 15], r/w, 0x1 */
+ uint32_t ldo15cis_sstart_delay : 3; /* [18:16], r/w, 0x2 */
+ uint32_t ldo15cis_sstart_en : 1; /* [ 19], r/w, 0x1 */
+ uint32_t ldo15cis_vout_sel : 4; /* [23:20], r/w, 0x8 */
+ uint32_t ldo15cis_vout_trim : 4; /* [27:24], r/w, 0x8 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ldo15cis;
+
+ /* 0x6CC : ldo18flash */
+ union {
+ struct {
+ uint32_t pu_ldo18flash : 1; /* [ 0], r/w, 0x0 */
+ uint32_t ldo18flash_bypass : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ldo18flash_pulldown : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ldo18flash_pulldown_sel : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ldo18flash_bm : 3; /* [ 6: 4], r/w, 0x3 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t ldo18flash_cc : 3; /* [10: 8], r/w, 0x3 */
+ uint32_t ldo18flash_ocp_out : 1; /* [ 11], r, 0x0 */
+ uint32_t ldo18flash_ocp_th : 3; /* [14:12], r/w, 0x3 */
+ uint32_t ldo18flash_ocp_en : 1; /* [ 15], r/w, 0x1 */
+ uint32_t ldo18flash_sstart_delay : 3; /* [18:16], r/w, 0x3 */
+ uint32_t ldo18flash_sstart_en : 1; /* [ 19], r/w, 0x1 */
+ uint32_t ldo18flash_vout_sel : 4; /* [23:20], r/w, 0x3 */
+ uint32_t ldo18flash_vout_trim : 4; /* [27:24], r/w, 0x7 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ldo18flash;
+
+ /* 0x6D0 : ldo12uhs */
+ union {
+ struct {
+ uint32_t pu_ldo12uhs : 1; /* [ 0], r/w, 0x0 */
+ uint32_t ldo12uhs_bypass : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ldo12uhs_pulldown : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ldo12uhs_pulldown_sel : 1; /* [ 3], r/w, 0x0 */
+ uint32_t ldo12uhs_bm : 3; /* [ 6: 4], r/w, 0x2 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t ldo12uhs_cc : 3; /* [10: 8], r/w, 0x3 */
+ uint32_t ldo12uhs_ocp_out : 1; /* [ 11], r, 0x0 */
+ uint32_t ldo12uhs_ocp_th : 3; /* [14:12], r/w, 0x3 */
+ uint32_t ldo12uhs_ocp_en : 1; /* [ 15], r/w, 0x1 */
+ uint32_t ldo12uhs_sstart_delay : 3; /* [18:16], r/w, 0x2 */
+ uint32_t ldo12uhs_sstart_en : 1; /* [ 19], r/w, 0x1 */
+ uint32_t ldo12uhs_vout_sel : 4; /* [23:20], r/w, 0x3 */
+ uint32_t ldo12uhs_vout_trim : 4; /* [27:24], r/w, 0x8 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } ldo12uhs;
+
+ /* 0x6d4 reserved */
+ uint8_t RESERVED0x6d4[28];
+
+ /* 0x6F0 : proc_mon */
+ union {
+ struct {
+ uint32_t pu_proc_mon : 1; /* [ 0], r/w, 0x0 */
+ uint32_t osc_en_rvt : 1; /* [ 1], r/w, 0x0 */
+ uint32_t osc_en_lvt : 1; /* [ 2], r/w, 0x0 */
+ uint32_t osc_sel : 1; /* [ 3], r/w, 0x0 */
+ uint32_t rstn_ringcount : 1; /* [ 4], r/w, 0x0 */
+ uint32_t rstn_refcount : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t refcount_div_onehot : 4; /* [11: 8], r/w, 0x4 */
+ uint32_t ring_freq : 16; /* [27:12], r, 0x0 */
+ uint32_t ring_freq_rdy : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } proc_mon;
+
+ /* 0x6f4 reserved */
+ uint8_t RESERVED0x6f4[12];
+
+ /* 0x700 : dll_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dll_cfg0;
+
+ /* 0x704 reserved */
+ uint8_t RESERVED0x704[140];
+
+ /* 0x790 : mipi_pll_cfg0 */
+ union {
+ struct {
+ uint32_t mipipll_sdm_rstb : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t mipipll_fbdv_rstb : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */
+ uint32_t pu_mipipll_fbdv : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t pu_mipipll_cp : 1; /* [ 8], r/w, 0x1 */
+ uint32_t pu_mipipll_sfreg : 1; /* [ 9], r/w, 0x0 */
+ uint32_t pu_mipipll : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg0;
+
+ /* 0x794 : mipi_pll_cfg1 */
+ union {
+ struct {
+ uint32_t mipipll_even_div_ratio : 7; /* [ 6: 0], r/w, 0x32 */
+ uint32_t mipipll_even_div_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t mipipll_refdiv_ratio : 4; /* [11: 8], r/w, 0x2 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t mipipll_refclk_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
+ uint32_t mipipll_vg11_sel : 2; /* [21:20], r/w, 0x1 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t mipipll_vg13_sel : 2; /* [25:24], r/w, 0x1 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg1;
+
+ /* 0x798 : mipi_pll_cfg2 */
+ union {
+ struct {
+ uint32_t mipipll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t mipipll_icp_5u : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t mipipll_icp_1u : 2; /* [ 7: 6], r/w, 0x0 */
+ uint32_t mipipll_int_frac_sw : 1; /* [ 8], r/w, 0x0 */
+ uint32_t mipipll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t mipipll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t mipipll_cp_ota_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t mipipll_pfd_en : 1; /* [ 12], r/w, 0x1 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg2;
+
+ /* 0x79C : mipi_pll_cfg3 */
+ union {
+ struct {
+ uint32_t mipipll_c4_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t mipipll_r4 : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t mipipll_r4_short : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t mipipll_c3 : 2; /* [13:12], r/w, 0x2 */
+ uint32_t mipipll_cz : 2; /* [15:14], r/w, 0x2 */
+ uint32_t mipipll_rz : 3; /* [18:16], r/w, 0x1 */
+ uint32_t mipipll_lf_test_en : 1; /* [ 19], r/w, 0x0 */
+ uint32_t mipipll_fast_lock_en : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg3;
+
+ /* 0x7A0 : mipi_pll_cfg4 */
+ union {
+ struct {
+ uint32_t mipipll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t mipipll_sel_fb_clk : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t mipipll_lock_det_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t mipipll_lock_clk_sel : 2; /* [10: 9], r/w, 0x1 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t mipipll_lock_clk_inv_en : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_14 : 2; /* [14:13], rsvd, 0x0 */
+ uint32_t mipipll_lock_win_sel : 2; /* [16:15], r/w, 0x1 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg4;
+
+ /* 0x7A4 : mipi_pll_cfg5 */
+ union {
+ struct {
+ uint32_t mipipll_vco_speed : 3; /* [ 2: 0], r/w, 0x5 */
+ uint32_t mipipll_vco_vdd_ctrl : 2; /* [ 4: 3], r/w, 0x2 */
+ uint32_t mipipll_vco_vdd_ctrl_extra : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t mipipll_vco_postdiv_sel : 3; /* [ 9: 7], r/w, 0x0 */
+ uint32_t mipipll_vco_postdiv_clk_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg5;
+
+ /* 0x7A8 : mipi_pll_cfg6 */
+ union {
+ struct {
+ uint32_t mipipll_sdmin : 19; /* [18: 0], r/w, 0x25800 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t mipipll_sdm_bypass : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg6;
+
+ /* 0x7AC : mipi_pll_cfg7 */
+ union {
+ struct {
+ uint32_t mipipll_sdm_order_sel : 1; /* [ 0], r/w, 0x1 */
+ uint32_t mipipll_sdm_dith_sel : 2; /* [ 2: 1], r/w, 0x0 */
+ uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg7;
+
+ /* 0x7B0 : mipi_pll_cfg8 */
+ union {
+ struct {
+ uint32_t mipipll_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t mipipll_ten : 1; /* [ 1], r/w, 0x0 */
+ uint32_t mipipll_ten_sfreg : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t mipipll_dten_ckin : 1; /* [ 4], r/w, 0x0 */
+ uint32_t mipipll_dten_fref : 1; /* [ 5], r/w, 0x0 */
+ uint32_t mipipll_dten_fsdm : 1; /* [ 6], r/w, 0x0 */
+ uint32_t mipipll_dten_pupll : 1; /* [ 7], r/w, 0x0 */
+ uint32_t mipipll_dten_pll_locked : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
+ uint32_t mipipll_dtest_pull_down : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg8;
+
+ /* 0x7B4 : mipi_pll_cfg9 */
+ union {
+ struct {
+ uint32_t mipipll_ssc_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t mipipll_ssc_cnt : 8; /* [11: 4], r/w, 0x64 */
+ uint32_t mipipll_ssc_gain : 3; /* [14:12], r/w, 0x5 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t mipipll_ssc_start_gate_en : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mipi_pll_cfg9;
+
+ /* 0x7b8 reserved */
+ uint8_t RESERVED0x7b8[24];
+
+ /* 0x7D0 : uhs_pll_cfg0 */
+ union {
+ struct {
+ uint32_t uhspll_sdm_rstb : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t uhspll_fbdv_rstb : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */
+ uint32_t pu_uhspll_fbdv : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t pu_uhspll_cp : 1; /* [ 8], r/w, 0x1 */
+ uint32_t pu_uhspll_sfreg : 1; /* [ 9], r/w, 0x0 */
+ uint32_t pu_uhspll : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg0;
+
+ /* 0x7D4 : uhs_pll_cfg1 */
+ union {
+ struct {
+ uint32_t uhspll_even_div_ratio : 7; /* [ 6: 0], r/w, 0x54 */
+ uint32_t uhspll_even_div_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t uhspll_refdiv_ratio : 4; /* [11: 8], r/w, 0x2 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t uhspll_refclk_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
+ uint32_t uhspll_vg11_sel : 2; /* [21:20], r/w, 0x1 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t uhspll_vg13_sel : 2; /* [25:24], r/w, 0x1 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg1;
+
+ /* 0x7D8 : uhs_pll_cfg2 */
+ union {
+ struct {
+ uint32_t uhspll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t uhspll_icp_5u : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t uhspll_icp_1u : 2; /* [ 7: 6], r/w, 0x0 */
+ uint32_t uhspll_int_frac_sw : 1; /* [ 8], r/w, 0x0 */
+ uint32_t uhspll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t uhspll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t uhspll_cp_ota_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t uhspll_pfd_en : 1; /* [ 12], r/w, 0x1 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg2;
+
+ /* 0x7DC : uhs_pll_cfg3 */
+ union {
+ struct {
+ uint32_t uhspll_c4_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t uhspll_r4 : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t uhspll_r4_short : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t uhspll_c3 : 2; /* [13:12], r/w, 0x2 */
+ uint32_t uhspll_cz : 2; /* [15:14], r/w, 0x2 */
+ uint32_t uhspll_rz : 3; /* [18:16], r/w, 0x1 */
+ uint32_t uhspll_lf_test_en : 1; /* [ 19], r/w, 0x0 */
+ uint32_t uhspll_fast_lock_en : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg3;
+
+ /* 0x7E0 : uhs_pll_cfg4 */
+ union {
+ struct {
+ uint32_t uhspll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t uhspll_sel_fb_clk : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t uhspll_lock_det_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t uhspll_lock_clk_sel : 2; /* [10: 9], r/w, 0x1 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t uhspll_lock_clk_inv_en : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_14 : 2; /* [14:13], rsvd, 0x0 */
+ uint32_t uhspll_lock_win_sel : 2; /* [16:15], r/w, 0x1 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg4;
+
+ /* 0x7E4 : uhs_pll_cfg5 */
+ union {
+ struct {
+ uint32_t uhspll_vco_speed : 3; /* [ 2: 0], r/w, 0x7 */
+ uint32_t uhspll_vco_vdd_ctrl : 2; /* [ 4: 3], r/w, 0x3 */
+ uint32_t uhspll_vco_vdd_ctrl_extra : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t uhspll_vco_postdiv_sel : 3; /* [ 9: 7], r/w, 0x0 */
+ uint32_t uhspll_vco_postdiv_clk_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg5;
+
+ /* 0x7E8 : uhs_pll_cfg6 */
+ union {
+ struct {
+ uint32_t uhspll_sdmin : 19; /* [18: 0], r/w, 0x34800 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t uhspll_sdm_bypass : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg6;
+
+ /* 0x7EC : uhs_pll_cfg7 */
+ union {
+ struct {
+ uint32_t uhspll_sdm_order_sel : 1; /* [ 0], r/w, 0x1 */
+ uint32_t uhspll_sdm_dith_sel : 2; /* [ 2: 1], r/w, 0x0 */
+ uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg7;
+
+ /* 0x7F0 : uhs_pll_cfg8 */
+ union {
+ struct {
+ uint32_t uhspll_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t uhspll_ten : 1; /* [ 1], r/w, 0x0 */
+ uint32_t uhspll_ten_sfreg : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t uhspll_dten_ckin : 1; /* [ 4], r/w, 0x0 */
+ uint32_t uhspll_dten_fref : 1; /* [ 5], r/w, 0x0 */
+ uint32_t uhspll_dten_fsdm : 1; /* [ 6], r/w, 0x0 */
+ uint32_t uhspll_dten_pupll : 1; /* [ 7], r/w, 0x0 */
+ uint32_t uhspll_dten_pll_locked : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
+ uint32_t uhspll_dtest_pull_down : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg8;
+
+ /* 0x7F4 : uhs_pll_cfg9 */
+ union {
+ struct {
+ uint32_t uhspll_ssc_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t uhspll_ssc_cnt : 8; /* [11: 4], r/w, 0x64 */
+ uint32_t uhspll_ssc_gain : 3; /* [14:12], r/w, 0x5 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t uhspll_ssc_start_gate_en : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } uhs_pll_cfg9;
+
+ /* 0x7f8 reserved */
+ uint8_t RESERVED0x7f8[24];
+
+ /* 0x810 : wifi_pll_cfg0 */
+ union {
+ struct {
+ uint32_t wifipll_sdm_rstb : 1; /* [ 0], r/w, 0x1 */
+ uint32_t wifipll_postdiv_rstb : 1; /* [ 1], r/w, 0x1 */
+ uint32_t wifipll_fbdv_rstb : 1; /* [ 2], r/w, 0x1 */
+ uint32_t wifipll_refdiv_rstb : 1; /* [ 3], r/w, 0x1 */
+ uint32_t pu_wifipll_postdiv : 1; /* [ 4], r/w, 0x0 */
+ uint32_t pu_wifipll_fbdv : 1; /* [ 5], r/w, 0x1 */
+ uint32_t pu_wifipll_clamp_op : 1; /* [ 6], r/w, 0x1 */
+ uint32_t pu_wifipll_pfd : 1; /* [ 7], r/w, 0x1 */
+ uint32_t pu_wifipll_cp : 1; /* [ 8], r/w, 0x1 */
+ uint32_t pu_wifipll_sfreg : 1; /* [ 9], r/w, 0x0 */
+ uint32_t pu_wifipll : 1; /* [ 10], r/w, 0x0 */
+ uint32_t pu_wifipll_clktree : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg0;
+
+ /* 0x814 : wifi_pll_cfg1 */
+ union {
+ struct {
+ uint32_t wifipll_postdiv : 7; /* [ 6: 0], r/w, 0x16 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t wifipll_refdiv_ratio : 4; /* [11: 8], r/w, 0x2 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t wifipll_refclk_sel : 2; /* [17:16], r/w, 0x1 */
+ uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
+ uint32_t wifipll_vg11_sel : 2; /* [21:20], r/w, 0x1 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t wifipll_vg13_sel : 2; /* [25:24], r/w, 0x1 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg1;
+
+ /* 0x818 : wifi_pll_cfg2 */
+ union {
+ struct {
+ uint32_t wifipll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t wifipll_icp_5u : 2; /* [ 5: 4], r/w, 0x2 */
+ uint32_t wifipll_icp_1u : 2; /* [ 7: 6], r/w, 0x0 */
+ uint32_t wifipll_int_frac_sw : 1; /* [ 8], r/w, 0x0 */
+ uint32_t wifipll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t wifipll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg2;
+
+ /* 0x81C : wifi_pll_cfg3 */
+ union {
+ struct {
+ uint32_t wifipll_c4_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t wifipll_r4 : 2; /* [ 5: 4], r/w, 0x2 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t wifipll_r4_short : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t wifipll_c3 : 2; /* [13:12], r/w, 0x2 */
+ uint32_t wifipll_cz : 2; /* [15:14], r/w, 0x1 */
+ uint32_t wifipll_rz : 3; /* [18:16], r/w, 0x3 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg3;
+
+ /* 0x820 : wifi_pll_cfg4 */
+ union {
+ struct {
+ uint32_t wifipll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t wifipll_sel_fb_clk : 2; /* [ 5: 4], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t wifipll_sdmclk_sel : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg4;
+
+ /* 0x824 : wifi_pll_cfg5 */
+ union {
+ struct {
+ uint32_t wifipll_vco_speed : 3; /* [ 2: 0], r/w, 0x5 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t wifipll_vco_div1_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t wifipll_vco_div2_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t wifipll_vco_div3_en : 1; /* [ 12], r/w, 0x1 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg5;
+
+ /* 0x828 : wifi_pll_cfg6 */
+ union {
+ struct {
+ uint32_t wifipll_sdmin : 26; /* [25: 0], r/w, 0x1800000 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t wifipll_sdm_bypass : 1; /* [ 28], r/w, 0x0 */
+ uint32_t wifipll_sdm_bypass_hw : 1; /* [ 29], r, 0x0 */
+ uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */
+ uint32_t wifipll_sdm_ctrl_hw : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg6;
+
+ /* 0x82C : wifi_pll_cfg7 */
+ union {
+ struct {
+ uint32_t wifipll_sdm_order_sel : 2; /* [ 1: 0], r/w, 0x2 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t wifipll_sdm_noi_prbs_sel : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t wifipll_sdm_noi_prbs_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t wifipll_sdm_sig_prbs_sel : 2; /* [13:12], r/w, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t wifipll_sdm_sig_dith_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg7;
+
+ /* 0x830 : wifi_pll_cfg8 */
+ union {
+ struct {
+ uint32_t wifipll_en_div2 : 1; /* [ 0], r/w, 0x1 */
+ uint32_t wifipll_en_div4 : 1; /* [ 1], r/w, 0x1 */
+ uint32_t wifipll_en_div5 : 1; /* [ 2], r/w, 0x1 */
+ uint32_t wifipll_en_div6 : 1; /* [ 3], r/w, 0x1 */
+ uint32_t wifipll_en_div8 : 1; /* [ 4], r/w, 0x1 */
+ uint32_t wifipll_en_div10 : 1; /* [ 5], r/w, 0x1 */
+ uint32_t wifipll_en_div12 : 1; /* [ 6], r/w, 0x1 */
+ uint32_t wifipll_en_div20 : 1; /* [ 7], r/w, 0x1 */
+ uint32_t wifipll_en_div30 : 1; /* [ 8], r/w, 0x1 */
+ uint32_t wifipll_sel_div2_div4 : 1; /* [ 9], r/w, 0x0 */
+ uint32_t en_wifipll_div30_bz_adc : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t wifipll_en_div2_hw : 1; /* [ 12], r, 0x1 */
+ uint32_t reserved_13_30 : 18; /* [30:13], rsvd, 0x0 */
+ uint32_t wifipll_en_ctrl_hw : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg8;
+
+ /* 0x834 : wifi_pll_cfg9 */
+ union {
+ struct {
+ uint32_t wifipll_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t ten_wifipll : 1; /* [ 1], r/w, 0x0 */
+ uint32_t ten_wifipll_sfreg : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t dten_wifipll_fin : 1; /* [ 4], r/w, 0x0 */
+ uint32_t dten_wifipll_fref : 1; /* [ 5], r/w, 0x0 */
+ uint32_t dten_wifipll_fsdm : 1; /* [ 6], r/w, 0x0 */
+ uint32_t dten_wifipll_div30 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t dten_wifipll_div10 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t dten_wifipll_postdiv_clk : 1; /* [ 9], r/w, 0x0 */
+ uint32_t usbpll_dtest_pclk_en : 1; /* [ 10], r/w, 0x0 */
+ uint32_t usbpll_dtest_clkout_en : 1; /* [ 11], r/w, 0x0 */
+ uint32_t dtest_wifipll_pulldown : 1; /* [ 12], r/w, 0x1 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg9;
+
+ /* 0x838 : wifi_pll_cfg10 */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t usbpll_ssc_start : 1; /* [ 2], r/w, 0x1 */
+ uint32_t usbpll_ssc_start_gate_en : 1; /* [ 3], r/w, 0x0 */
+ uint32_t usbpll_ssc_gain : 3; /* [ 6: 4], r/w, 0x3 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t usbpll_ssc_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t usbpll_sdm_bypass : 1; /* [ 9], r/w, 0x0 */
+ uint32_t usbpll_sdm_order_sel : 1; /* [ 10], r/w, 0x1 */
+ uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
+ uint32_t usbpll_sdm_sig_dith_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
+ uint32_t usbpll_div2_en : 1; /* [ 20], r/w, 0x1 */
+ uint32_t usbpll_clkout_en : 1; /* [ 21], r/w, 0x1 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t usbpll_sel_sample_clk : 2; /* [25:24], r/w, 0x1 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t usbpll_rstb : 1; /* [ 28], r/w, 0x1 */
+ uint32_t pu_usbpll_mmdiv : 1; /* [ 29], r/w, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg10;
+
+ /* 0x83C : wifi_pll_cfg11 */
+ union {
+ struct {
+ uint32_t usbpll_sdmin : 19; /* [18: 0], r/w, 0x28000 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg11;
+
+ /* 0x840 : wifi_pll_cfg12 */
+ union {
+ struct {
+ uint32_t usbpll_ssc_cnt : 9; /* [ 8: 0], r/w, 0xf0 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg12;
+
+ /* 0x844 : wifi_pll_cfg13 */
+ union {
+ struct {
+ uint32_t wifipll_resv : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reserved_16_20 : 5; /* [20:16], rsvd, 0x0 */
+ uint32_t usbpll_dl_ctrl : 1; /* [ 21], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_30_bz_adc : 1; /* [ 22], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_30 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_20 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_12 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_10 : 1; /* [ 26], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_8 : 1; /* [ 27], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_6 : 1; /* [ 28], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_5 : 1; /* [ 29], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_4 : 1; /* [ 30], r/w, 0x0 */
+ uint32_t wifipll_dl_ctrl_2 : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } wifi_pll_cfg13;
+
+ /* 0x848 reserved */
+ uint8_t RESERVED0x848[92];
+
+ /* 0x8A4 : gauge */
+ union {
+ struct {
+ uint32_t gauge_reserve : 3; /* [ 2: 0], r/w, 0x0 */
+ uint32_t gauge_ictrl_adc : 2; /* [ 4: 3], r/w, 0x1 */
+ uint32_t gauge_dem_en : 1; /* [ 5], r/w, 0x1 */
+ uint32_t gauge_ckb_en : 1; /* [ 6], r/w, 0x0 */
+ uint32_t gauge_chop_phas : 1; /* [ 7], r/w, 0x1 */
+ uint32_t gauge_chop_freq : 3; /* [10: 8], r/w, 0x1 */
+ uint32_t gauge_chop_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t gauge_sel_edge : 1; /* [ 12], r/w, 0x0 */
+ uint32_t gauge_quan_gain : 2; /* [14:13], r/w, 0x1 */
+ uint32_t gauge_sdm_pu : 1; /* [ 15], r/w, 0x0 */
+ uint32_t gauge_channel_sel : 1; /* [ 16], r/w, 0x0 */
+ uint32_t gauge_channel_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t gauge_lp_mode : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t tmux_gauge_power : 3; /* [22:20], r/w, 0x0 */
+ uint32_t ten_gauge_power : 1; /* [ 23], r/w, 0x0 */
+ uint32_t ntc_bias_sel : 4; /* [27:24], r/w, 0x8 */
+ uint32_t ntc_bias_en : 1; /* [ 28], r/w, 0x0 */
+ uint32_t gauge_ldo_pu : 1; /* [ 29], r/w, 0x0 */
+ uint32_t gauge_vcm_pu : 1; /* [ 30], r/w, 0x0 */
+ uint32_t gauge_bg_pu : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gauge;
+
+ /* 0x8a8 reserved */
+ uint8_t RESERVED0x8a8[16];
+
+ /* 0x8B8 : gauge_rx_fifo_ctrl */
+ union {
+ struct {
+ uint32_t gauge_rx_fifo_flush : 1; /* [ 0], w1p, 0x0 */
+ uint32_t gauge_rxo_int_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t gauge_rxu_int_en : 1; /* [ 2], r/w, 0x0 */
+ uint32_t gauge_rxa_int_en : 1; /* [ 3], r/w, 0x0 */
+ uint32_t gauge_rx_drq_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t gauge_rx_data_res : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t gauge_rx_ch_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_13 : 5; /* [13: 9], rsvd, 0x0 */
+ uint32_t gauge_rx_drq_cnt : 2; /* [15:14], r/w, 0x0 */
+ uint32_t gauge_rx_trg_level : 3; /* [18:16], r/w, 0x1 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t gauge_rx_data_mode : 2; /* [25:24], r/w, 0x3 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gauge_rx_fifo_ctrl;
+
+ /* 0x8BC : gauge_rx_fifo_status */
+ union {
+ struct {
+ uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
+ uint32_t gauge_rxo_int : 1; /* [ 1], r, 0x0 */
+ uint32_t gauge_rxu_int : 1; /* [ 2], r, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t gauge_rxa_int : 1; /* [ 4], r, 0x0 */
+ uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
+ uint32_t gauge_rxa_cnt : 3; /* [18:16], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t gauge_rxa : 1; /* [ 24], r, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gauge_rx_fifo_status;
+
+ /* 0x8C0 : gauge_rx_fifo_data */
+ union {
+ struct {
+ uint32_t gauge_rx_data : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gauge_rx_fifo_data;
+
+ /* 0x8C4 : gpio_cfg0 */
+ union {
+ struct {
+ uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_0_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_0_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_0_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_0_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_0_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_0_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_0_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_0_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_0_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_0_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_0_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg0;
+
+ /* 0x8C8 : gpio_cfg1 */
+ union {
+ struct {
+ uint32_t reg_gpio_1_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_1_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_1_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_1_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_1_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_1_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_1_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_1_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_1_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_1_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_1_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_1_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_1_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_1_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_1_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_1_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg1;
+
+ /* 0x8CC : gpio_cfg2 */
+ union {
+ struct {
+ uint32_t reg_gpio_2_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_2_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_2_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_2_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_2_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_2_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_2_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_2_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_2_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_2_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_2_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_2_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_2_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_2_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_2_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_2_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg2;
+
+ /* 0x8D0 : gpio_cfg3 */
+ union {
+ struct {
+ uint32_t reg_gpio_3_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_3_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_3_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_3_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_3_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_3_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_3_func_sel : 5; /* [12: 8], r/w, 0xf */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_3_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_3_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_3_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_3_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_3_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_3_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_3_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_3_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_3_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg3;
+
+ /* 0x8D4 : gpio_cfg4 */
+ union {
+ struct {
+ uint32_t reg_gpio_4_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_4_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_4_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_4_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_4_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_4_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_4_func_sel : 5; /* [12: 8], r/w, 0xf */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_4_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_4_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_4_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_4_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_4_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_4_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_4_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_4_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_4_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg4;
+
+ /* 0x8D8 : gpio_cfg5 */
+ union {
+ struct {
+ uint32_t reg_gpio_5_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_5_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_5_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_5_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_5_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_5_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_5_func_sel : 5; /* [12: 8], r/w, 0xf */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_5_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_5_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_5_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_5_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_5_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_5_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_5_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_5_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_5_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg5;
+
+ /* 0x8DC : gpio_cfg6 */
+ union {
+ struct {
+ uint32_t reg_gpio_6_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_6_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_6_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_6_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_6_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_6_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_6_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_6_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_6_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_6_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_6_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_6_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_6_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_6_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_6_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_6_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg6;
+
+ /* 0x8E0 : gpio_cfg7 */
+ union {
+ struct {
+ uint32_t reg_gpio_7_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_7_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_7_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_7_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_7_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_7_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_7_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_7_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_7_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_7_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_7_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_7_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_7_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_7_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_7_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_7_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg7;
+
+ /* 0x8E4 : gpio_cfg8 */
+ union {
+ struct {
+ uint32_t reg_gpio_8_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_8_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_8_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_8_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_8_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_8_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_8_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_8_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_8_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_8_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_8_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_8_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_8_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_8_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_8_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_8_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg8;
+
+ /* 0x8E8 : gpio_cfg9 */
+ union {
+ struct {
+ uint32_t reg_gpio_9_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_9_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_9_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_9_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_9_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_9_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_9_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_9_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_9_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_9_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_9_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_9_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_9_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_9_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_9_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_9_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg9;
+
+ /* 0x8EC : gpio_cfg10 */
+ union {
+ struct {
+ uint32_t reg_gpio_10_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_10_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_10_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_10_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_10_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_10_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_10_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_10_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_10_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_10_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_10_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_10_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_10_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_10_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_10_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_10_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg10;
+
+ /* 0x8F0 : gpio_cfg11 */
+ union {
+ struct {
+ uint32_t reg_gpio_11_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_11_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_11_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_11_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_11_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_11_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_11_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_11_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_11_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_11_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_11_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_11_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_11_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_11_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_11_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_11_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg11;
+
+ /* 0x8F4 : gpio_cfg12 */
+ union {
+ struct {
+ uint32_t reg_gpio_12_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_12_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_12_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_12_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_12_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_12_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_12_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_12_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_12_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_12_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_12_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_12_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_12_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_12_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_12_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_12_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg12;
+
+ /* 0x8F8 : gpio_cfg13 */
+ union {
+ struct {
+ uint32_t reg_gpio_13_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_13_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_13_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_13_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_13_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_13_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_13_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_13_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_13_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_13_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_13_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_13_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_13_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_13_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_13_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_13_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg13;
+
+ /* 0x8FC : gpio_cfg14 */
+ union {
+ struct {
+ uint32_t reg_gpio_14_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_14_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_14_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_14_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_14_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_14_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_14_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_14_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_14_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_14_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_14_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_14_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_14_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_14_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_14_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_14_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg14;
+
+ /* 0x900 : gpio_cfg15 */
+ union {
+ struct {
+ uint32_t reg_gpio_15_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_15_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_15_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_15_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_15_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_15_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_15_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_15_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_15_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_15_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_15_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_15_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_15_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_15_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_15_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_15_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg15;
+
+ /* 0x904 : gpio_cfg16 */
+ union {
+ struct {
+ uint32_t reg_gpio_16_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_16_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_16_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_16_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_16_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_16_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_16_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_16_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_16_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_16_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_16_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_16_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_16_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_16_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_16_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_16_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg16;
+
+ /* 0x908 : gpio_cfg17 */
+ union {
+ struct {
+ uint32_t reg_gpio_17_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_17_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_17_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_17_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_17_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_17_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_17_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_17_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_17_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_17_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_17_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_17_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_17_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_17_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_17_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_17_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg17;
+
+ /* 0x90C : gpio_cfg18 */
+ union {
+ struct {
+ uint32_t reg_gpio_18_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_18_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_18_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_18_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_18_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_18_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_18_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_18_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_18_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_18_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_18_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_18_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_18_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_18_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_18_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_18_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg18;
+
+ /* 0x910 : gpio_cfg19 */
+ union {
+ struct {
+ uint32_t reg_gpio_19_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_19_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_19_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_19_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_19_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_19_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_19_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_19_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_19_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_19_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_19_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_19_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_19_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_19_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_19_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_19_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg19;
+
+ /* 0x914 : gpio_cfg20 */
+ union {
+ struct {
+ uint32_t reg_gpio_20_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_20_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_20_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_20_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_20_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_20_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_20_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_20_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_20_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_20_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_20_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_20_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_20_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_20_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_20_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_20_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg20;
+
+ /* 0x918 : gpio_cfg21 */
+ union {
+ struct {
+ uint32_t reg_gpio_21_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_21_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_21_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_21_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_21_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_21_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_21_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_21_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_21_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_21_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_21_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_21_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_21_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_21_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_21_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_21_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg21;
+
+ /* 0x91C : gpio_cfg22 */
+ union {
+ struct {
+ uint32_t reg_gpio_22_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_22_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_22_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_22_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_22_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_22_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_22_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_22_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_22_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_22_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_22_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_22_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_22_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_22_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_22_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_22_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg22;
+
+ /* 0x920 : gpio_cfg23 */
+ union {
+ struct {
+ uint32_t reg_gpio_23_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_23_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_23_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_23_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_23_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_23_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_23_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_23_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_23_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_23_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_23_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_23_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_23_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_23_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_23_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_23_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg23;
+
+ /* 0x924 : gpio_cfg24 */
+ union {
+ struct {
+ uint32_t reg_gpio_24_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_24_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_24_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_24_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_24_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_24_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_24_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_24_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_24_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_24_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_24_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_24_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_24_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_24_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_24_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_24_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg24;
+
+ /* 0x928 : gpio_cfg25 */
+ union {
+ struct {
+ uint32_t reg_gpio_25_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_25_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_25_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_25_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_25_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_25_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_25_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_25_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_25_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_25_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_25_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_25_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_25_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_25_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_25_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_25_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg25;
+
+ /* 0x92C : gpio_cfg26 */
+ union {
+ struct {
+ uint32_t reg_gpio_26_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_26_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_26_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_26_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_26_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_26_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_26_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_26_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_26_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_26_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_26_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_26_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_26_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_26_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_26_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_26_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg26;
+
+ /* 0x930 : gpio_cfg27 */
+ union {
+ struct {
+ uint32_t reg_gpio_27_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_27_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_27_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_27_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_27_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_27_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_27_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_27_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_27_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_27_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_27_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_27_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_27_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_27_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_27_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_27_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg27;
+
+ /* 0x934 : gpio_cfg28 */
+ union {
+ struct {
+ uint32_t reg_gpio_28_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_28_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_28_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_28_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_28_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_28_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_28_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_28_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_28_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_28_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_28_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_28_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_28_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_28_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_28_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_28_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg28;
+
+ /* 0x938 : gpio_cfg29 */
+ union {
+ struct {
+ uint32_t reg_gpio_29_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_29_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_29_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_29_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_29_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_29_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_29_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_29_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_29_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_29_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_29_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_29_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_29_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_29_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_29_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_29_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg29;
+
+ /* 0x93C : gpio_cfg30 */
+ union {
+ struct {
+ uint32_t reg_gpio_30_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_30_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_30_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_30_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_30_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_30_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_30_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_30_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_30_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_30_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_30_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_30_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_30_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_30_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_30_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_30_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg30;
+
+ /* 0x940 : gpio_cfg31 */
+ union {
+ struct {
+ uint32_t reg_gpio_31_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_31_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_31_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_31_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_31_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_31_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_31_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_31_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_31_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_31_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_31_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_31_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_31_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_31_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_31_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_31_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg31;
+
+ /* 0x944 : gpio_cfg32 */
+ union {
+ struct {
+ uint32_t reg_gpio_32_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_32_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_32_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_32_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_32_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_32_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_32_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_32_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_32_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_32_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_32_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_32_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_32_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_32_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_32_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_32_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg32;
+
+ /* 0x948 : gpio_cfg33 */
+ union {
+ struct {
+ uint32_t reg_gpio_33_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_33_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_33_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_33_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_33_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_33_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_33_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_33_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_33_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_33_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_33_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_33_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_33_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_33_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_33_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_33_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg33;
+
+ /* 0x94C : gpio_cfg34 */
+ union {
+ struct {
+ uint32_t reg_gpio_34_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_34_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_34_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_34_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_34_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_34_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_34_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_34_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_34_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_34_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_34_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_34_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_34_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_34_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_34_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_34_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg34;
+
+ /* 0x950 : gpio_cfg35 */
+ union {
+ struct {
+ uint32_t reg_gpio_35_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_35_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_35_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_35_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_35_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_35_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_35_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_35_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_35_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_35_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_35_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_35_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_35_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_35_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_35_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_35_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg35;
+
+ /* 0x954 : gpio_cfg36 */
+ union {
+ struct {
+ uint32_t reg_gpio_36_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_36_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_36_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_36_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_36_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_36_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_36_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_36_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_36_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_36_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_36_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_36_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_36_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_36_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_36_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_36_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg36;
+
+ /* 0x958 : gpio_cfg37 */
+ union {
+ struct {
+ uint32_t reg_gpio_37_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_37_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_37_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_37_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_37_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_37_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_37_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_37_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_37_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_37_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_37_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_37_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_37_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_37_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_37_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_37_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg37;
+
+ /* 0x95C : gpio_cfg38 */
+ union {
+ struct {
+ uint32_t reg_gpio_38_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_38_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_38_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_38_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_38_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_38_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_38_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_38_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_38_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_38_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_38_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_38_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_38_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_38_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_38_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_38_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg38;
+
+ /* 0x960 : gpio_cfg39 */
+ union {
+ struct {
+ uint32_t reg_gpio_39_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_39_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_39_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_39_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_39_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_39_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_39_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_39_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_39_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_39_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_39_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_39_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_39_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_39_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_39_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_39_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg39;
+
+ /* 0x964 : gpio_cfg40 */
+ union {
+ struct {
+ uint32_t reg_gpio_40_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_40_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_40_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_40_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_40_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_40_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_40_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_40_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_40_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_40_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_40_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_40_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_40_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_40_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_40_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_40_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg40;
+
+ /* 0x968 : gpio_cfg41 */
+ union {
+ struct {
+ uint32_t reg_gpio_41_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_41_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_41_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_41_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_41_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_41_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_41_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_41_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_41_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_41_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_41_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_41_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_41_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_41_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_41_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_41_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg41;
+
+ /* 0x96C : gpio_cfg42 */
+ union {
+ struct {
+ uint32_t reg_gpio_42_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_42_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_42_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_42_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_42_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_42_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_42_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_42_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_42_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_42_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_42_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_42_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_42_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_42_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_42_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_42_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg42;
+
+ /* 0x970 : gpio_cfg43 */
+ union {
+ struct {
+ uint32_t reg_gpio_43_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_43_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_43_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_43_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_43_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_43_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_43_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_43_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_43_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_43_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_43_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_43_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_43_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_43_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_43_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_43_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg43;
+
+ /* 0x974 : gpio_cfg44 */
+ union {
+ struct {
+ uint32_t reg_gpio_44_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_44_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_44_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_44_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_44_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_44_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_44_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_44_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_44_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_44_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_44_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_44_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_44_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_44_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_44_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_44_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg44;
+
+ /* 0x978 : gpio_cfg45 */
+ union {
+ struct {
+ uint32_t reg_gpio_45_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_45_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_45_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_45_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_45_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_45_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_gpio_45_func_sel : 5; /* [12: 8], r/w, 0xb */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_gpio_45_int_mode_set : 4; /* [19:16], r/w, 0x0 */
+ uint32_t reg_gpio_45_int_clr : 1; /* [ 20], r/w, 0x0 */
+ uint32_t gpio_45_int_stat : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_45_int_mask : 1; /* [ 22], r/w, 0x1 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_gpio_45_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_gpio_45_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg_gpio_45_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t reg_gpio_45_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t reg_gpio_45_mode : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg45;
+
+ /* 0x97C : gpio_cfg46 */
+ union {
+ struct {
+ uint32_t reg_gpio_46_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_46_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_46_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_46_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_46_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg46;
+
+ /* 0x980 : gpio_cfg47 */
+ union {
+ struct {
+ uint32_t reg_gpio_47_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_47_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_47_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_47_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_47_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg47;
+
+ /* 0x984 : gpio_cfg48 */
+ union {
+ struct {
+ uint32_t reg_gpio_48_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_48_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_48_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_48_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_48_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg48;
+
+ /* 0x988 : gpio_cfg49 */
+ union {
+ struct {
+ uint32_t reg_gpio_49_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_49_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_49_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_49_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_49_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg49;
+
+ /* 0x98C : gpio_cfg50 */
+ union {
+ struct {
+ uint32_t reg_gpio_50_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_50_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_50_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_50_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_50_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg50;
+
+ /* 0x990 : gpio_cfg51 */
+ union {
+ struct {
+ uint32_t reg_gpio_51_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_51_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_51_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_51_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_51_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg51;
+
+ /* 0x994 : gpio_cfg52 */
+ union {
+ struct {
+ uint32_t reg_gpio_52_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_52_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_52_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_52_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_52_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg52;
+
+ /* 0x998 : gpio_cfg53 */
+ union {
+ struct {
+ uint32_t reg_gpio_53_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_53_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_53_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_53_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_53_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg53;
+
+ /* 0x99C : gpio_cfg54 */
+ union {
+ struct {
+ uint32_t reg_gpio_54_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_54_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_54_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_54_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_54_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg54;
+
+ /* 0x9A0 : gpio_cfg55 */
+ union {
+ struct {
+ uint32_t reg_gpio_55_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_55_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_55_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_55_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_55_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg55;
+
+ /* 0x9A4 : gpio_cfg56 */
+ union {
+ struct {
+ uint32_t reg_gpio_56_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_56_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_56_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_56_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_56_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg56;
+
+ /* 0x9A8 : gpio_cfg57 */
+ union {
+ struct {
+ uint32_t reg_gpio_57_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_57_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_57_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_57_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_57_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg57;
+
+ /* 0x9AC : gpio_cfg58 */
+ union {
+ struct {
+ uint32_t reg_gpio_58_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_58_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_58_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_58_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_58_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg58;
+
+ /* 0x9B0 : gpio_cfg59 */
+ union {
+ struct {
+ uint32_t reg_gpio_59_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_59_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_59_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_59_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_59_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg59;
+
+ /* 0x9B4 : gpio_cfg60 */
+ union {
+ struct {
+ uint32_t reg_gpio_60_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_60_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_60_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_60_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_60_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg60;
+
+ /* 0x9B8 : gpio_cfg61 */
+ union {
+ struct {
+ uint32_t reg_gpio_61_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_61_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_61_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_61_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_61_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg61;
+
+ /* 0x9BC : gpio_cfg62 */
+ union {
+ struct {
+ uint32_t reg_gpio_62_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_62_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_62_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_62_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_62_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg62;
+
+ /* 0x9C0 : gpio_cfg63 */
+ union {
+ struct {
+ uint32_t reg_gpio_63_ie : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_63_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_63_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_63_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_63_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg63;
+
+ /* 0x9c4 reserved */
+ uint8_t RESERVED0x9c4[256];
+
+ /* 0xAC4 : gpio_cfg128 */
+ union {
+ struct {
+ uint32_t reg2_gpio_0_i : 1; /* [ 0], r, 0x0 */
+ uint32_t reg2_gpio_1_i : 1; /* [ 1], r, 0x0 */
+ uint32_t reg2_gpio_2_i : 1; /* [ 2], r, 0x0 */
+ uint32_t reg2_gpio_3_i : 1; /* [ 3], r, 0x0 */
+ uint32_t reg2_gpio_4_i : 1; /* [ 4], r, 0x0 */
+ uint32_t reg2_gpio_5_i : 1; /* [ 5], r, 0x0 */
+ uint32_t reg2_gpio_6_i : 1; /* [ 6], r, 0x0 */
+ uint32_t reg2_gpio_7_i : 1; /* [ 7], r, 0x0 */
+ uint32_t reg2_gpio_8_i : 1; /* [ 8], r, 0x0 */
+ uint32_t reg2_gpio_9_i : 1; /* [ 9], r, 0x0 */
+ uint32_t reg2_gpio_10_i : 1; /* [ 10], r, 0x0 */
+ uint32_t reg2_gpio_11_i : 1; /* [ 11], r, 0x0 */
+ uint32_t reg2_gpio_12_i : 1; /* [ 12], r, 0x0 */
+ uint32_t reg2_gpio_13_i : 1; /* [ 13], r, 0x0 */
+ uint32_t reg2_gpio_14_i : 1; /* [ 14], r, 0x0 */
+ uint32_t reg2_gpio_15_i : 1; /* [ 15], r, 0x0 */
+ uint32_t reg2_gpio_16_i : 1; /* [ 16], r, 0x0 */
+ uint32_t reg2_gpio_17_i : 1; /* [ 17], r, 0x0 */
+ uint32_t reg2_gpio_18_i : 1; /* [ 18], r, 0x0 */
+ uint32_t reg2_gpio_19_i : 1; /* [ 19], r, 0x0 */
+ uint32_t reg2_gpio_20_i : 1; /* [ 20], r, 0x0 */
+ uint32_t reg2_gpio_21_i : 1; /* [ 21], r, 0x0 */
+ uint32_t reg2_gpio_22_i : 1; /* [ 22], r, 0x0 */
+ uint32_t reg2_gpio_23_i : 1; /* [ 23], r, 0x0 */
+ uint32_t reg2_gpio_24_i : 1; /* [ 24], r, 0x0 */
+ uint32_t reg2_gpio_25_i : 1; /* [ 25], r, 0x0 */
+ uint32_t reg2_gpio_26_i : 1; /* [ 26], r, 0x0 */
+ uint32_t reg2_gpio_27_i : 1; /* [ 27], r, 0x0 */
+ uint32_t reg2_gpio_28_i : 1; /* [ 28], r, 0x0 */
+ uint32_t reg2_gpio_29_i : 1; /* [ 29], r, 0x0 */
+ uint32_t reg2_gpio_30_i : 1; /* [ 30], r, 0x0 */
+ uint32_t reg2_gpio_31_i : 1; /* [ 31], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg128;
+
+ /* 0xAC8 : gpio_cfg129 */
+ union {
+ struct {
+ uint32_t reg2_gpio_32_i : 1; /* [ 0], r, 0x0 */
+ uint32_t reg2_gpio_33_i : 1; /* [ 1], r, 0x0 */
+ uint32_t reg2_gpio_34_i : 1; /* [ 2], r, 0x0 */
+ uint32_t reg2_gpio_35_i : 1; /* [ 3], r, 0x0 */
+ uint32_t reg2_gpio_36_i : 1; /* [ 4], r, 0x0 */
+ uint32_t reg2_gpio_37_i : 1; /* [ 5], r, 0x0 */
+ uint32_t reg2_gpio_38_i : 1; /* [ 6], r, 0x0 */
+ uint32_t reg2_gpio_39_i : 1; /* [ 7], r, 0x0 */
+ uint32_t reg2_gpio_40_i : 1; /* [ 8], r, 0x0 */
+ uint32_t reg2_gpio_41_i : 1; /* [ 9], r, 0x0 */
+ uint32_t reg2_gpio_42_i : 1; /* [ 10], r, 0x0 */
+ uint32_t reg2_gpio_43_i : 1; /* [ 11], r, 0x0 */
+ uint32_t reg2_gpio_44_i : 1; /* [ 12], r, 0x0 */
+ uint32_t reg2_gpio_45_i : 1; /* [ 13], r, 0x0 */
+ uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg129;
+
+ /* 0xacc reserved */
+ uint8_t RESERVED0xacc[24];
+
+ /* 0xAE4 : gpio_cfg136 */
+ union {
+ struct {
+ uint32_t reg2_gpio_0_o : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg2_gpio_1_o : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg2_gpio_2_o : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg2_gpio_3_o : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg2_gpio_4_o : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg2_gpio_5_o : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg2_gpio_6_o : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg2_gpio_7_o : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg2_gpio_8_o : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg2_gpio_9_o : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg2_gpio_10_o : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg2_gpio_11_o : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reg2_gpio_12_o : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg2_gpio_13_o : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reg2_gpio_14_o : 1; /* [ 14], r/w, 0x0 */
+ uint32_t reg2_gpio_15_o : 1; /* [ 15], r/w, 0x0 */
+ uint32_t reg2_gpio_16_o : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reg2_gpio_17_o : 1; /* [ 17], r/w, 0x0 */
+ uint32_t reg2_gpio_18_o : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reg2_gpio_19_o : 1; /* [ 19], r/w, 0x0 */
+ uint32_t reg2_gpio_20_o : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg2_gpio_21_o : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reg2_gpio_22_o : 1; /* [ 22], r/w, 0x0 */
+ uint32_t reg2_gpio_23_o : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reg2_gpio_24_o : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg2_gpio_25_o : 1; /* [ 25], r/w, 0x0 */
+ uint32_t reg2_gpio_26_o : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reg2_gpio_27_o : 1; /* [ 27], r/w, 0x0 */
+ uint32_t reg2_gpio_28_o : 1; /* [ 28], r/w, 0x0 */
+ uint32_t reg2_gpio_29_o : 1; /* [ 29], r/w, 0x0 */
+ uint32_t reg2_gpio_30_o : 1; /* [ 30], r/w, 0x0 */
+ uint32_t reg2_gpio_31_o : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg136;
+
+ /* 0xAE8 : gpio_cfg137 */
+ union {
+ struct {
+ uint32_t reg2_gpio_32_o : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg2_gpio_33_o : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg2_gpio_34_o : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg2_gpio_35_o : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg2_gpio_36_o : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg2_gpio_37_o : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg2_gpio_38_o : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg2_gpio_39_o : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg2_gpio_40_o : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg2_gpio_41_o : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg2_gpio_42_o : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg2_gpio_43_o : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reg2_gpio_44_o : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg2_gpio_45_o : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg137;
+
+ /* 0xAEC : gpio_cfg138 */
+ union {
+ struct {
+ uint32_t reg2_gpio_0_set : 1; /* [ 0], w1p, 0x0 */
+ uint32_t reg2_gpio_1_set : 1; /* [ 1], w1p, 0x0 */
+ uint32_t reg2_gpio_2_set : 1; /* [ 2], w1p, 0x0 */
+ uint32_t reg2_gpio_3_set : 1; /* [ 3], w1p, 0x0 */
+ uint32_t reg2_gpio_4_set : 1; /* [ 4], w1p, 0x0 */
+ uint32_t reg2_gpio_5_set : 1; /* [ 5], w1p, 0x0 */
+ uint32_t reg2_gpio_6_set : 1; /* [ 6], w1p, 0x0 */
+ uint32_t reg2_gpio_7_set : 1; /* [ 7], w1p, 0x0 */
+ uint32_t reg2_gpio_8_set : 1; /* [ 8], w1p, 0x0 */
+ uint32_t reg2_gpio_9_set : 1; /* [ 9], w1p, 0x0 */
+ uint32_t reg2_gpio_10_set : 1; /* [ 10], w1p, 0x0 */
+ uint32_t reg2_gpio_11_set : 1; /* [ 11], w1p, 0x0 */
+ uint32_t reg2_gpio_12_set : 1; /* [ 12], w1p, 0x0 */
+ uint32_t reg2_gpio_13_set : 1; /* [ 13], w1p, 0x0 */
+ uint32_t reg2_gpio_14_set : 1; /* [ 14], w1p, 0x0 */
+ uint32_t reg2_gpio_15_set : 1; /* [ 15], w1p, 0x0 */
+ uint32_t reg2_gpio_16_set : 1; /* [ 16], w1p, 0x0 */
+ uint32_t reg2_gpio_17_set : 1; /* [ 17], w1p, 0x0 */
+ uint32_t reg2_gpio_18_set : 1; /* [ 18], w1p, 0x0 */
+ uint32_t reg2_gpio_19_set : 1; /* [ 19], w1p, 0x0 */
+ uint32_t reg2_gpio_20_set : 1; /* [ 20], w1p, 0x0 */
+ uint32_t reg2_gpio_21_set : 1; /* [ 21], w1p, 0x0 */
+ uint32_t reg2_gpio_22_set : 1; /* [ 22], w1p, 0x0 */
+ uint32_t reg2_gpio_23_set : 1; /* [ 23], w1p, 0x0 */
+ uint32_t reg2_gpio_24_set : 1; /* [ 24], w1p, 0x0 */
+ uint32_t reg2_gpio_25_set : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg2_gpio_26_set : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reg2_gpio_27_set : 1; /* [ 27], w1p, 0x0 */
+ uint32_t reg2_gpio_28_set : 1; /* [ 28], w1p, 0x0 */
+ uint32_t reg2_gpio_29_set : 1; /* [ 29], w1p, 0x0 */
+ uint32_t reg2_gpio_30_set : 1; /* [ 30], w1p, 0x0 */
+ uint32_t reg2_gpio_31_set : 1; /* [ 31], w1p, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg138;
+
+ /* 0xAF0 : gpio_cfg139 */
+ union {
+ struct {
+ uint32_t reg2_gpio_32_set : 1; /* [ 0], w1p, 0x0 */
+ uint32_t reg2_gpio_33_set : 1; /* [ 1], w1p, 0x0 */
+ uint32_t reg2_gpio_34_set : 1; /* [ 2], w1p, 0x0 */
+ uint32_t reg2_gpio_35_set : 1; /* [ 3], w1p, 0x0 */
+ uint32_t reg2_gpio_36_set : 1; /* [ 4], w1p, 0x0 */
+ uint32_t reg2_gpio_37_set : 1; /* [ 5], w1p, 0x0 */
+ uint32_t reg2_gpio_38_set : 1; /* [ 6], w1p, 0x0 */
+ uint32_t reg2_gpio_39_set : 1; /* [ 7], w1p, 0x0 */
+ uint32_t reg2_gpio_40_set : 1; /* [ 8], w1p, 0x0 */
+ uint32_t reg2_gpio_41_set : 1; /* [ 9], w1p, 0x0 */
+ uint32_t reg2_gpio_42_set : 1; /* [ 10], w1p, 0x0 */
+ uint32_t reg2_gpio_43_set : 1; /* [ 11], w1p, 0x0 */
+ uint32_t reg2_gpio_44_set : 1; /* [ 12], w1p, 0x0 */
+ uint32_t reg2_gpio_45_set : 1; /* [ 13], w1p, 0x0 */
+ uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg139;
+
+ /* 0xAF4 : gpio_cfg140 */
+ union {
+ struct {
+ uint32_t reg2_gpio_0_clr : 1; /* [ 0], w1p, 0x0 */
+ uint32_t reg2_gpio_1_clr : 1; /* [ 1], w1p, 0x0 */
+ uint32_t reg2_gpio_2_clr : 1; /* [ 2], w1p, 0x0 */
+ uint32_t reg2_gpio_3_clr : 1; /* [ 3], w1p, 0x0 */
+ uint32_t reg2_gpio_4_clr : 1; /* [ 4], w1p, 0x0 */
+ uint32_t reg2_gpio_5_clr : 1; /* [ 5], w1p, 0x0 */
+ uint32_t reg2_gpio_6_clr : 1; /* [ 6], w1p, 0x0 */
+ uint32_t reg2_gpio_7_clr : 1; /* [ 7], w1p, 0x0 */
+ uint32_t reg2_gpio_8_clr : 1; /* [ 8], w1p, 0x0 */
+ uint32_t reg2_gpio_9_clr : 1; /* [ 9], w1p, 0x0 */
+ uint32_t reg2_gpio_10_clr : 1; /* [ 10], w1p, 0x0 */
+ uint32_t reg2_gpio_11_clr : 1; /* [ 11], w1p, 0x0 */
+ uint32_t reg2_gpio_12_clr : 1; /* [ 12], w1p, 0x0 */
+ uint32_t reg2_gpio_13_clr : 1; /* [ 13], w1p, 0x0 */
+ uint32_t reg2_gpio_14_clr : 1; /* [ 14], w1p, 0x0 */
+ uint32_t reg2_gpio_15_clr : 1; /* [ 15], w1p, 0x0 */
+ uint32_t reg2_gpio_16_clr : 1; /* [ 16], w1p, 0x0 */
+ uint32_t reg2_gpio_17_clr : 1; /* [ 17], w1p, 0x0 */
+ uint32_t reg2_gpio_18_clr : 1; /* [ 18], w1p, 0x0 */
+ uint32_t reg2_gpio_19_clr : 1; /* [ 19], w1p, 0x0 */
+ uint32_t reg2_gpio_20_clr : 1; /* [ 20], w1p, 0x0 */
+ uint32_t reg2_gpio_21_clr : 1; /* [ 21], w1p, 0x0 */
+ uint32_t reg2_gpio_22_clr : 1; /* [ 22], w1p, 0x0 */
+ uint32_t reg2_gpio_23_clr : 1; /* [ 23], w1p, 0x0 */
+ uint32_t reg2_gpio_24_clr : 1; /* [ 24], w1p, 0x0 */
+ uint32_t reg2_gpio_25_clr : 1; /* [ 25], w1p, 0x0 */
+ uint32_t reg2_gpio_26_clr : 1; /* [ 26], w1p, 0x0 */
+ uint32_t reg2_gpio_27_clr : 1; /* [ 27], w1p, 0x0 */
+ uint32_t reg2_gpio_28_clr : 1; /* [ 28], w1p, 0x0 */
+ uint32_t reg2_gpio_29_clr : 1; /* [ 29], w1p, 0x0 */
+ uint32_t reg2_gpio_30_clr : 1; /* [ 30], w1p, 0x0 */
+ uint32_t reg2_gpio_31_clr : 1; /* [ 31], w1p, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg140;
+
+ /* 0xAF8 : gpio_cfg141 */
+ union {
+ struct {
+ uint32_t reg2_gpio_32_clr : 1; /* [ 0], w1p, 0x0 */
+ uint32_t reg2_gpio_33_clr : 1; /* [ 1], w1p, 0x0 */
+ uint32_t reg2_gpio_34_clr : 1; /* [ 2], w1p, 0x0 */
+ uint32_t reg2_gpio_35_clr : 1; /* [ 3], w1p, 0x0 */
+ uint32_t reg2_gpio_36_clr : 1; /* [ 4], w1p, 0x0 */
+ uint32_t reg2_gpio_37_clr : 1; /* [ 5], w1p, 0x0 */
+ uint32_t reg2_gpio_38_clr : 1; /* [ 6], w1p, 0x0 */
+ uint32_t reg2_gpio_39_clr : 1; /* [ 7], w1p, 0x0 */
+ uint32_t reg2_gpio_40_clr : 1; /* [ 8], w1p, 0x0 */
+ uint32_t reg2_gpio_41_clr : 1; /* [ 9], w1p, 0x0 */
+ uint32_t reg2_gpio_42_clr : 1; /* [ 10], w1p, 0x0 */
+ uint32_t reg2_gpio_43_clr : 1; /* [ 11], w1p, 0x0 */
+ uint32_t reg2_gpio_44_clr : 1; /* [ 12], w1p, 0x0 */
+ uint32_t reg2_gpio_45_clr : 1; /* [ 13], w1p, 0x0 */
+ uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg141;
+
+ /* 0xAFC : gpio_cfg142 */
+ union {
+ struct {
+ uint32_t cr_gpio_tx_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t cr_invert_code0_high : 1; /* [ 1], r/w, 0x0 */
+ uint32_t cr_invert_code1_high : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3_6 : 4; /* [ 6: 3], rsvd, 0x0 */
+ uint32_t cr_code_total_time : 9; /* [15: 7], r/w, 0x190 */
+ uint32_t cr_code0_high_time : 8; /* [23:16], r/w, 0xc8 */
+ uint32_t cr_code1_high_time : 8; /* [31:24], r/w, 0xc8 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg142;
+
+ /* 0xB00 : gpio_cfg143 */
+ union {
+ struct {
+ uint32_t cr_gpio_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t cr_gpio_dma_out_sel_latch : 1; /* [ 1], r/w, 0x0 */
+ uint32_t gpio_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
+ uint32_t gpio_tx_end_clr : 1; /* [ 3], w1c, 0x0 */
+ uint32_t gpio_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
+ uint32_t gpio_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t cr_gpio_dma_park_value : 1; /* [ 7], r/w, 0x0 */
+ uint32_t gpio_tx_fifo_cnt : 8; /* [15: 8], r, 0x80 */
+ uint32_t cr_gpio_tx_fifo_th : 7; /* [22:16], r/w, 0x0 */
+ uint32_t cr_gpio_tx_end_mask : 1; /* [ 23], r/w, 0x1 */
+ uint32_t cr_gpio_tx_fifo_mask : 1; /* [ 24], r/w, 0x1 */
+ uint32_t cr_gpio_tx_fer_mask : 1; /* [ 25], r/w, 0x1 */
+ uint32_t r_gpio_tx_end_int : 1; /* [ 26], r, 0x0 */
+ uint32_t r_gpio_tx_fifo_int : 1; /* [ 27], r, 0x0 */
+ uint32_t r_gpio_tx_fer_int : 1; /* [ 28], r, 0x0 */
+ uint32_t cr_gpio_tx_end_en : 1; /* [ 29], r/w, 0x1 */
+ uint32_t cr_gpio_tx_fifo_en : 1; /* [ 30], r/w, 0x1 */
+ uint32_t cr_gpio_tx_fer_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg143;
+
+ /* 0xB04 : gpio_cfg144 */
+ union {
+ struct {
+ uint32_t gpio_tx_data_to_fifo : 16; /* [15: 0], w, x */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } gpio_cfg144;
+};
+
+typedef volatile struct glb_reg glb_reg_t;
+
+#endif /* __GLB_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/gpip_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/gpip_reg.h
new file mode 100644
index 00000000..ab425880
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/gpip_reg.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file gpip_reg.h
+ * @version V1.2
+ * @date 2022-03-7
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2022 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __GPIP_REG_H__
+#define __GPIP_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : gpadc_config */
+#define GPIP_GPADC_CONFIG_OFFSET (0x0)
+#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN
+#define GPIP_GPADC_DMA_EN_POS (0U)
+#define GPIP_GPADC_DMA_EN_LEN (1U)
+#define GPIP_GPADC_DMA_EN_MSK (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)
+#define GPIP_GPADC_DMA_EN_UMSK (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS))
+#define GPIP_GPADC_FIFO_CLR GPIP_GPADC_FIFO_CLR
+#define GPIP_GPADC_FIFO_CLR_POS (1U)
+#define GPIP_GPADC_FIFO_CLR_LEN (1U)
+#define GPIP_GPADC_FIFO_CLR_MSK (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)
+#define GPIP_GPADC_FIFO_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS))
+#define GPIP_GPADC_FIFO_NE GPIP_GPADC_FIFO_NE
+#define GPIP_GPADC_FIFO_NE_POS (2U)
+#define GPIP_GPADC_FIFO_NE_LEN (1U)
+#define GPIP_GPADC_FIFO_NE_MSK (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)
+#define GPIP_GPADC_FIFO_NE_UMSK (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS))
+#define GPIP_GPADC_FIFO_FULL GPIP_GPADC_FIFO_FULL
+#define GPIP_GPADC_FIFO_FULL_POS (3U)
+#define GPIP_GPADC_FIFO_FULL_LEN (1U)
+#define GPIP_GPADC_FIFO_FULL_MSK (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)
+#define GPIP_GPADC_FIFO_FULL_UMSK (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS))
+#define GPIP_GPADC_RDY GPIP_GPADC_RDY
+#define GPIP_GPADC_RDY_POS (4U)
+#define GPIP_GPADC_RDY_LEN (1U)
+#define GPIP_GPADC_RDY_MSK (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)
+#define GPIP_GPADC_RDY_UMSK (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS))
+#define GPIP_GPADC_FIFO_OVERRUN GPIP_GPADC_FIFO_OVERRUN
+#define GPIP_GPADC_FIFO_OVERRUN_POS (5U)
+#define GPIP_GPADC_FIFO_OVERRUN_LEN (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN GPIP_GPADC_FIFO_UNDERRUN
+#define GPIP_GPADC_FIFO_UNDERRUN_POS (6U)
+#define GPIP_GPADC_FIFO_UNDERRUN_LEN (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS))
+#define GPIP_GPADC_RDY_CLR GPIP_GPADC_RDY_CLR
+#define GPIP_GPADC_RDY_CLR_POS (8U)
+#define GPIP_GPADC_RDY_CLR_LEN (1U)
+#define GPIP_GPADC_RDY_CLR_MSK (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)
+#define GPIP_GPADC_RDY_CLR_UMSK (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS))
+#define GPIP_GPADC_FIFO_OVERRUN_CLR GPIP_GPADC_FIFO_OVERRUN_CLR
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS (9U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR GPIP_GPADC_FIFO_UNDERRUN_CLR
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS (10U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
+#define GPIP_GPADC_RDY_MASK GPIP_GPADC_RDY_MASK
+#define GPIP_GPADC_RDY_MASK_POS (12U)
+#define GPIP_GPADC_RDY_MASK_LEN (1U)
+#define GPIP_GPADC_RDY_MASK_MSK (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)
+#define GPIP_GPADC_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS))
+#define GPIP_GPADC_FIFO_OVERRUN_MASK GPIP_GPADC_FIFO_OVERRUN_MASK
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS (13U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK GPIP_GPADC_FIFO_UNDERRUN_MASK
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS (14U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
+#define GPIP_GPADC_FIFO_DATA_COUNT GPIP_GPADC_FIFO_DATA_COUNT
+#define GPIP_GPADC_FIFO_DATA_COUNT_POS (16U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_LEN (6U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_MSK (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)
+#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS))
+#define GPIP_GPADC_FIFO_THL GPIP_GPADC_FIFO_THL
+#define GPIP_GPADC_FIFO_THL_POS (22U)
+#define GPIP_GPADC_FIFO_THL_LEN (2U)
+#define GPIP_GPADC_FIFO_THL_MSK (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)
+#define GPIP_GPADC_FIFO_THL_UMSK (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS))
+
+/* 0x4 : gpadc_dma_rdata */
+#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
+#define GPIP_GPADC_DMA_RDATA GPIP_GPADC_DMA_RDATA
+#define GPIP_GPADC_DMA_RDATA_POS (0U)
+#define GPIP_GPADC_DMA_RDATA_LEN (26U)
+#define GPIP_GPADC_DMA_RDATA_MSK (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)
+#define GPIP_GPADC_DMA_RDATA_UMSK (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS))
+
+/* 0x20 : gpadc_pir_train */
+#define GPIP_GPADC_PIR_TRAIN_OFFSET (0x20)
+#define GPIP_PIR_EXTEND GPIP_PIR_EXTEND
+#define GPIP_PIR_EXTEND_POS (0U)
+#define GPIP_PIR_EXTEND_LEN (5U)
+#define GPIP_PIR_EXTEND_MSK (((1U<© COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HBN_REG_H__
+#define __HBN_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : HBN_CTL */
+#define HBN_CTL_OFFSET (0x0)
+#define HBN_RTC_CTL HBN_RTC_CTL
+#define HBN_RTC_CTL_POS (0U)
+#define HBN_RTC_CTL_LEN (4U)
+#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
+#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
+#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION
+#define HBN_RTC_DLY_OPTION_POS (4U)
+#define HBN_RTC_DLY_OPTION_LEN (1U)
+#define HBN_RTC_DLY_OPTION_MSK (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
+#define HBN_RTC_DLY_OPTION_UMSK (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
+#define HBN_PU_LDO18IO_AON HBN_PU_LDO18IO_AON
+#define HBN_PU_LDO18IO_AON_POS (5U)
+#define HBN_PU_LDO18IO_AON_LEN (1U)
+#define HBN_PU_LDO18IO_AON_MSK (((1U << HBN_PU_LDO18IO_AON_LEN) - 1) << HBN_PU_LDO18IO_AON_POS)
+#define HBN_PU_LDO18IO_AON_UMSK (~(((1U << HBN_PU_LDO18IO_AON_LEN) - 1) << HBN_PU_LDO18IO_AON_POS))
+#define HBN_MODE HBN_MODE
+#define HBN_MODE_POS (7U)
+#define HBN_MODE_LEN (1U)
+#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
+#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
+#define HBN_TRAP_MODE HBN_TRAP_MODE
+#define HBN_TRAP_MODE_POS (8U)
+#define HBN_TRAP_MODE_LEN (1U)
+#define HBN_TRAP_MODE_MSK (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
+#define HBN_TRAP_MODE_UMSK (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
+#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE
+#define HBN_PWRDN_HBN_CORE_POS (9U)
+#define HBN_PWRDN_HBN_CORE_LEN (1U)
+#define HBN_PWRDN_HBN_CORE_MSK (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
+#define HBN_PWRDN_HBN_CORE_UMSK (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
+#define HBN_SW_RST HBN_SW_RST
+#define HBN_SW_RST_POS (12U)
+#define HBN_SW_RST_LEN (1U)
+#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
+#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
+#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11
+#define HBN_DIS_PWR_OFF_LDO11_POS (13U)
+#define HBN_DIS_PWR_OFF_LDO11_LEN (1U)
+#define HBN_DIS_PWR_OFF_LDO11_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
+#define HBN_DIS_PWR_OFF_LDO11_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
+#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT
+#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
+#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
+#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL
+#define HBN_LDO11_RT_VOUT_SEL_POS (15U)
+#define HBN_LDO11_RT_VOUT_SEL_LEN (4U)
+#define HBN_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
+#define HBN_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
+#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL
+#define HBN_LDO11_AON_VOUT_SEL_POS (19U)
+#define HBN_LDO11_AON_VOUT_SEL_LEN (4U)
+#define HBN_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
+#define HBN_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
+#define HBN_PU_DCDC_AON HBN_PU_DCDC_AON
+#define HBN_PU_DCDC_AON_POS (23U)
+#define HBN_PU_DCDC_AON_LEN (1U)
+#define HBN_PU_DCDC_AON_MSK (((1U << HBN_PU_DCDC_AON_LEN) - 1) << HBN_PU_DCDC_AON_POS)
+#define HBN_PU_DCDC_AON_UMSK (~(((1U << HBN_PU_DCDC_AON_LEN) - 1) << HBN_PU_DCDC_AON_POS))
+#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON
+#define HBN_PU_DCDC18_AON_POS (24U)
+#define HBN_PU_DCDC18_AON_LEN (1U)
+#define HBN_PU_DCDC18_AON_MSK (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
+#define HBN_PU_DCDC18_AON_UMSK (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
+#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION
+#define HBN_PWR_ON_OPTION_POS (25U)
+#define HBN_PWR_ON_OPTION_LEN (1U)
+#define HBN_PWR_ON_OPTION_MSK (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
+#define HBN_PWR_ON_OPTION_UMSK (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
+#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION
+#define HBN_SRAM_SLP_OPTION_POS (26U)
+#define HBN_SRAM_SLP_OPTION_LEN (1U)
+#define HBN_SRAM_SLP_OPTION_MSK (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
+#define HBN_SRAM_SLP_OPTION_UMSK (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
+#define HBN_SRAM_SLP HBN_SRAM_SLP
+#define HBN_SRAM_SLP_POS (27U)
+#define HBN_SRAM_SLP_LEN (1U)
+#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
+#define HBN_SRAM_SLP_UMSK (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
+#define HBN_STATE HBN_STATE
+#define HBN_STATE_POS (28U)
+#define HBN_STATE_LEN (4U)
+#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
+#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
+
+/* 0x4 : HBN_TIME_L */
+#define HBN_TIME_L_OFFSET (0x4)
+#define HBN_TIME_L HBN_TIME_L
+#define HBN_TIME_L_POS (0U)
+#define HBN_TIME_L_LEN (32U)
+#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
+#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
+
+/* 0x8 : HBN_TIME_H */
+#define HBN_TIME_H_OFFSET (0x8)
+#define HBN_TIME_H HBN_TIME_H
+#define HBN_TIME_H_POS (0U)
+#define HBN_TIME_H_LEN (8U)
+#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
+#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
+
+/* 0xC : RTC_TIME_L */
+#define HBN_RTC_TIME_L_OFFSET (0xC)
+#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L
+#define HBN_RTC_TIME_LATCH_L_POS (0U)
+#define HBN_RTC_TIME_LATCH_L_LEN (32U)
+#define HBN_RTC_TIME_LATCH_L_MSK (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
+#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
+
+/* 0x10 : RTC_TIME_H */
+#define HBN_RTC_TIME_H_OFFSET (0x10)
+#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H
+#define HBN_RTC_TIME_LATCH_H_POS (0U)
+#define HBN_RTC_TIME_LATCH_H_LEN (8U)
+#define HBN_RTC_TIME_LATCH_H_MSK (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
+#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
+#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH
+#define HBN_RTC_TIME_LATCH_POS (31U)
+#define HBN_RTC_TIME_LATCH_LEN (1U)
+#define HBN_RTC_TIME_LATCH_MSK (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
+#define HBN_RTC_TIME_LATCH_UMSK (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
+
+/* 0x14 : HBN_IRQ_MODE */
+#define HBN_IRQ_MODE_OFFSET (0x14)
+#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE
+#define HBN_PIN_WAKEUP_MODE_POS (0U)
+#define HBN_PIN_WAKEUP_MODE_LEN (4U)
+#define HBN_PIN_WAKEUP_MODE_MSK (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
+#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
+#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK
+#define HBN_PIN_WAKEUP_MASK_POS (4U)
+#define HBN_PIN_WAKEUP_MASK_LEN (9U)
+#define HBN_PIN_WAKEUP_MASK_MSK (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
+#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
+#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD
+#define HBN_REG_EN_HW_PU_PD_POS (16U)
+#define HBN_REG_EN_HW_PU_PD_LEN (1U)
+#define HBN_REG_EN_HW_PU_PD_MSK (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
+#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
+#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN
+#define HBN_IRQ_BOR_EN_POS (18U)
+#define HBN_IRQ_BOR_EN_LEN (1U)
+#define HBN_IRQ_BOR_EN_MSK (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
+#define HBN_IRQ_BOR_EN_UMSK (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
+#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN
+#define HBN_IRQ_ACOMP0_EN_POS (20U)
+#define HBN_IRQ_ACOMP0_EN_LEN (2U)
+#define HBN_IRQ_ACOMP0_EN_MSK (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
+#define HBN_IRQ_ACOMP0_EN_UMSK (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
+#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN
+#define HBN_IRQ_ACOMP1_EN_POS (22U)
+#define HBN_IRQ_ACOMP1_EN_LEN (2U)
+#define HBN_IRQ_ACOMP1_EN_MSK (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
+#define HBN_IRQ_ACOMP1_EN_UMSK (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
+#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL
+#define HBN_PIN_WAKEUP_SEL_POS (24U)
+#define HBN_PIN_WAKEUP_SEL_LEN (3U)
+#define HBN_PIN_WAKEUP_SEL_MSK (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
+#define HBN_PIN_WAKEUP_SEL_UMSK (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
+#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN
+#define HBN_PIN_WAKEUP_EN_POS (27U)
+#define HBN_PIN_WAKEUP_EN_LEN (1U)
+#define HBN_PIN_WAKEUP_EN_MSK (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
+#define HBN_PIN_WAKEUP_EN_UMSK (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
+
+/* 0x18 : HBN_IRQ_STAT */
+#define HBN_IRQ_STAT_OFFSET (0x18)
+#define HBN_IRQ_STAT HBN_IRQ_STAT
+#define HBN_IRQ_STAT_POS (0U)
+#define HBN_IRQ_STAT_LEN (32U)
+#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
+#define HBN_IRQ_STAT_UMSK (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
+
+/* 0x1C : HBN_IRQ_CLR */
+#define HBN_IRQ_CLR_OFFSET (0x1C)
+#define HBN_IRQ_CLR HBN_IRQ_CLR
+#define HBN_IRQ_CLR_POS (0U)
+#define HBN_IRQ_CLR_LEN (32U)
+#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
+#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
+
+/* 0x20 : HBN_PIR_CFG */
+#define HBN_PIR_CFG_OFFSET (0x20)
+#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL
+#define HBN_PIR_HPF_SEL_POS (0U)
+#define HBN_PIR_HPF_SEL_LEN (2U)
+#define HBN_PIR_HPF_SEL_MSK (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
+#define HBN_PIR_HPF_SEL_UMSK (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
+#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL
+#define HBN_PIR_LPF_SEL_POS (2U)
+#define HBN_PIR_LPF_SEL_LEN (1U)
+#define HBN_PIR_LPF_SEL_MSK (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
+#define HBN_PIR_LPF_SEL_UMSK (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
+#define HBN_PIR_DIS HBN_PIR_DIS
+#define HBN_PIR_DIS_POS (4U)
+#define HBN_PIR_DIS_LEN (2U)
+#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
+#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
+#define HBN_PIR_EN HBN_PIR_EN
+#define HBN_PIR_EN_POS (7U)
+#define HBN_PIR_EN_LEN (1U)
+#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
+#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
+#define HBN_GPADC_CS HBN_GPADC_CS
+#define HBN_GPADC_CS_POS (8U)
+#define HBN_GPADC_CS_LEN (1U)
+#define HBN_GPADC_CS_MSK (((1U << HBN_GPADC_CS_LEN) - 1) << HBN_GPADC_CS_POS)
+#define HBN_GPADC_CS_UMSK (~(((1U << HBN_GPADC_CS_LEN) - 1) << HBN_GPADC_CS_POS))
+
+/* 0x24 : HBN_PIR_VTH */
+#define HBN_PIR_VTH_OFFSET (0x24)
+#define HBN_PIR_VTH HBN_PIR_VTH
+#define HBN_PIR_VTH_POS (0U)
+#define HBN_PIR_VTH_LEN (14U)
+#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
+#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
+
+/* 0x28 : HBN_PIR_INTERVAL */
+#define HBN_PIR_INTERVAL_OFFSET (0x28)
+#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL
+#define HBN_PIR_INTERVAL_POS (0U)
+#define HBN_PIR_INTERVAL_LEN (12U)
+#define HBN_PIR_INTERVAL_MSK (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
+#define HBN_PIR_INTERVAL_UMSK (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
+
+/* 0x2C : HBN_BOR_CFG */
+#define HBN_BOR_CFG_OFFSET (0x2C)
+#define HBN_BOD_SEL HBN_BOD_SEL
+#define HBN_BOD_SEL_POS (0U)
+#define HBN_BOD_SEL_LEN (1U)
+#define HBN_BOD_SEL_MSK (((1U << HBN_BOD_SEL_LEN) - 1) << HBN_BOD_SEL_POS)
+#define HBN_BOD_SEL_UMSK (~(((1U << HBN_BOD_SEL_LEN) - 1) << HBN_BOD_SEL_POS))
+#define HBN_BOD_VTH HBN_BOD_VTH
+#define HBN_BOD_VTH_POS (1U)
+#define HBN_BOD_VTH_LEN (3U)
+#define HBN_BOD_VTH_MSK (((1U << HBN_BOD_VTH_LEN) - 1) << HBN_BOD_VTH_POS)
+#define HBN_BOD_VTH_UMSK (~(((1U << HBN_BOD_VTH_LEN) - 1) << HBN_BOD_VTH_POS))
+#define HBN_PU_BOD HBN_PU_BOD
+#define HBN_PU_BOD_POS (4U)
+#define HBN_PU_BOD_LEN (1U)
+#define HBN_PU_BOD_MSK (((1U << HBN_PU_BOD_LEN) - 1) << HBN_PU_BOD_POS)
+#define HBN_PU_BOD_UMSK (~(((1U << HBN_PU_BOD_LEN) - 1) << HBN_PU_BOD_POS))
+#define HBN_R_BOD_OUT HBN_R_BOD_OUT
+#define HBN_R_BOD_OUT_POS (5U)
+#define HBN_R_BOD_OUT_LEN (1U)
+#define HBN_R_BOD_OUT_MSK (((1U << HBN_R_BOD_OUT_LEN) - 1) << HBN_R_BOD_OUT_POS)
+#define HBN_R_BOD_OUT_UMSK (~(((1U << HBN_R_BOD_OUT_LEN) - 1) << HBN_R_BOD_OUT_POS))
+
+/* 0x30 : HBN_GLB */
+#define HBN_GLB_OFFSET (0x30)
+#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL
+#define HBN_ROOT_CLK_SEL_POS (0U)
+#define HBN_ROOT_CLK_SEL_LEN (2U)
+#define HBN_ROOT_CLK_SEL_MSK (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
+#define HBN_ROOT_CLK_SEL_UMSK (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
+#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL
+#define HBN_UART_CLK_SEL_POS (2U)
+#define HBN_UART_CLK_SEL_LEN (1U)
+#define HBN_UART_CLK_SEL_MSK (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
+#define HBN_UART_CLK_SEL_UMSK (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
+#define HBN_F32K_SEL HBN_F32K_SEL
+#define HBN_F32K_SEL_POS (3U)
+#define HBN_F32K_SEL_LEN (2U)
+#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
+#define HBN_F32K_SEL_UMSK (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
+#define HBN_RESET_EVENT HBN_RESET_EVENT
+#define HBN_RESET_EVENT_POS (7U)
+#define HBN_RESET_EVENT_LEN (6U)
+#define HBN_RESET_EVENT_MSK (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)
+#define HBN_RESET_EVENT_UMSK (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS))
+#define HBN_CLR_RESET_EVENT HBN_CLR_RESET_EVENT
+#define HBN_CLR_RESET_EVENT_POS (13U)
+#define HBN_CLR_RESET_EVENT_LEN (1U)
+#define HBN_CLR_RESET_EVENT_MSK (((1U << HBN_CLR_RESET_EVENT_LEN) - 1) << HBN_CLR_RESET_EVENT_POS)
+#define HBN_CLR_RESET_EVENT_UMSK (~(((1U << HBN_CLR_RESET_EVENT_LEN) - 1) << HBN_CLR_RESET_EVENT_POS))
+#define HBN_UART_CLK_SEL2 HBN_UART_CLK_SEL2
+#define HBN_UART_CLK_SEL2_POS (15U)
+#define HBN_UART_CLK_SEL2_LEN (1U)
+#define HBN_UART_CLK_SEL2_MSK (((1U << HBN_UART_CLK_SEL2_LEN) - 1) << HBN_UART_CLK_SEL2_POS)
+#define HBN_UART_CLK_SEL2_UMSK (~(((1U << HBN_UART_CLK_SEL2_LEN) - 1) << HBN_UART_CLK_SEL2_POS))
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
+#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL
+#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
+#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
+#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL
+#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
+#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))
+
+/* 0x34 : HBN_SRAM */
+#define HBN_SRAM_OFFSET (0x34)
+#define HBN_RETRAM_RET HBN_RETRAM_RET
+#define HBN_RETRAM_RET_POS (6U)
+#define HBN_RETRAM_RET_LEN (1U)
+#define HBN_RETRAM_RET_MSK (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
+#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
+#define HBN_RETRAM_SLP HBN_RETRAM_SLP
+#define HBN_RETRAM_SLP_POS (7U)
+#define HBN_RETRAM_SLP_LEN (1U)
+#define HBN_RETRAM_SLP_MSK (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
+#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
+
+/* 0x38 : HBN_PAD_CTRL_0 */
+#define HBN_PAD_CTRL_0_OFFSET (0x38)
+#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT
+#define HBN_REG_AON_PAD_IE_SMT_POS (0U)
+#define HBN_REG_AON_PAD_IE_SMT_LEN (9U)
+#define HBN_REG_AON_PAD_IE_SMT_MSK (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
+#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
+#define HBN_REG_AON_LED_SEL HBN_REG_AON_LED_SEL
+#define HBN_REG_AON_LED_SEL_POS (10U)
+#define HBN_REG_AON_LED_SEL_LEN (9U)
+#define HBN_REG_AON_LED_SEL_MSK (((1U << HBN_REG_AON_LED_SEL_LEN) - 1) << HBN_REG_AON_LED_SEL_POS)
+#define HBN_REG_AON_LED_SEL_UMSK (~(((1U << HBN_REG_AON_LED_SEL_LEN) - 1) << HBN_REG_AON_LED_SEL_POS))
+#define HBN_REG_EN_AON_CTRL_GPIO HBN_REG_EN_AON_CTRL_GPIO
+#define HBN_REG_EN_AON_CTRL_GPIO_POS (20U)
+#define HBN_REG_EN_AON_CTRL_GPIO_LEN (9U)
+#define HBN_REG_EN_AON_CTRL_GPIO_MSK (((1U << HBN_REG_EN_AON_CTRL_GPIO_LEN) - 1) << HBN_REG_EN_AON_CTRL_GPIO_POS)
+#define HBN_REG_EN_AON_CTRL_GPIO_UMSK (~(((1U << HBN_REG_EN_AON_CTRL_GPIO_LEN) - 1) << HBN_REG_EN_AON_CTRL_GPIO_POS))
+#define HBN_REG_AON_GPIO_ISO_MODE HBN_REG_AON_GPIO_ISO_MODE
+#define HBN_REG_AON_GPIO_ISO_MODE_POS (31U)
+#define HBN_REG_AON_GPIO_ISO_MODE_LEN (1U)
+#define HBN_REG_AON_GPIO_ISO_MODE_MSK (((1U << HBN_REG_AON_GPIO_ISO_MODE_LEN) - 1) << HBN_REG_AON_GPIO_ISO_MODE_POS)
+#define HBN_REG_AON_GPIO_ISO_MODE_UMSK (~(((1U << HBN_REG_AON_GPIO_ISO_MODE_LEN) - 1) << HBN_REG_AON_GPIO_ISO_MODE_POS))
+
+/* 0x3C : HBN_PAD_CTRL_1 */
+#define HBN_PAD_CTRL_1_OFFSET (0x3C)
+#define HBN_REG_AON_PAD_OE HBN_REG_AON_PAD_OE
+#define HBN_REG_AON_PAD_OE_POS (0U)
+#define HBN_REG_AON_PAD_OE_LEN (9U)
+#define HBN_REG_AON_PAD_OE_MSK (((1U << HBN_REG_AON_PAD_OE_LEN) - 1) << HBN_REG_AON_PAD_OE_POS)
+#define HBN_REG_AON_PAD_OE_UMSK (~(((1U << HBN_REG_AON_PAD_OE_LEN) - 1) << HBN_REG_AON_PAD_OE_POS))
+#define HBN_REG_AON_PAD_PD HBN_REG_AON_PAD_PD
+#define HBN_REG_AON_PAD_PD_POS (10U)
+#define HBN_REG_AON_PAD_PD_LEN (9U)
+#define HBN_REG_AON_PAD_PD_MSK (((1U << HBN_REG_AON_PAD_PD_LEN) - 1) << HBN_REG_AON_PAD_PD_POS)
+#define HBN_REG_AON_PAD_PD_UMSK (~(((1U << HBN_REG_AON_PAD_PD_LEN) - 1) << HBN_REG_AON_PAD_PD_POS))
+#define HBN_REG_AON_PAD_PU HBN_REG_AON_PAD_PU
+#define HBN_REG_AON_PAD_PU_POS (20U)
+#define HBN_REG_AON_PAD_PU_LEN (9U)
+#define HBN_REG_AON_PAD_PU_MSK (((1U << HBN_REG_AON_PAD_PU_LEN) - 1) << HBN_REG_AON_PAD_PU_POS)
+#define HBN_REG_AON_PAD_PU_UMSK (~(((1U << HBN_REG_AON_PAD_PU_LEN) - 1) << HBN_REG_AON_PAD_PU_POS))
+
+/* 0x100 : HBN_RSV0 */
+#define HBN_RSV0_OFFSET (0x100)
+#define HBN_RSV0 HBN_RSV0
+#define HBN_RSV0_POS (0U)
+#define HBN_RSV0_LEN (32U)
+#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
+#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
+
+/* 0x104 : HBN_RSV1 */
+#define HBN_RSV1_OFFSET (0x104)
+#define HBN_RSV1 HBN_RSV1
+#define HBN_RSV1_POS (0U)
+#define HBN_RSV1_LEN (32U)
+#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
+#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
+
+/* 0x108 : HBN_RSV2 */
+#define HBN_RSV2_OFFSET (0x108)
+#define HBN_RSV2 HBN_RSV2
+#define HBN_RSV2_POS (0U)
+#define HBN_RSV2_LEN (32U)
+#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
+#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
+
+/* 0x10C : HBN_RSV3 */
+#define HBN_RSV3_OFFSET (0x10C)
+#define HBN_RSV3 HBN_RSV3
+#define HBN_RSV3_POS (0U)
+#define HBN_RSV3_LEN (32U)
+#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
+#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
+
+/* 0x200 : rc32k_ctrl0 */
+#define HBN_RC32K_CTRL0_OFFSET (0x200)
+#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE
+#define HBN_RC32K_CAL_DONE_POS (0U)
+#define HBN_RC32K_CAL_DONE_LEN (1U)
+#define HBN_RC32K_CAL_DONE_MSK (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
+#define HBN_RC32K_CAL_DONE_UMSK (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
+#define HBN_RC32K_RDY HBN_RC32K_RDY
+#define HBN_RC32K_RDY_POS (1U)
+#define HBN_RC32K_RDY_LEN (1U)
+#define HBN_RC32K_RDY_MSK (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
+#define HBN_RC32K_RDY_UMSK (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
+#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS
+#define HBN_RC32K_CAL_INPROGRESS_POS (2U)
+#define HBN_RC32K_CAL_INPROGRESS_LEN (1U)
+#define HBN_RC32K_CAL_INPROGRESS_MSK (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
+#define HBN_RC32K_CAL_INPROGRESS_UMSK (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
+#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV
+#define HBN_RC32K_CAL_DIV_POS (3U)
+#define HBN_RC32K_CAL_DIV_LEN (2U)
+#define HBN_RC32K_CAL_DIV_MSK (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
+#define HBN_RC32K_CAL_DIV_UMSK (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
+#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE
+#define HBN_RC32K_CAL_PRECHARGE_POS (5U)
+#define HBN_RC32K_CAL_PRECHARGE_LEN (1U)
+#define HBN_RC32K_CAL_PRECHARGE_MSK (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
+#define HBN_RC32K_CAL_PRECHARGE_UMSK (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
+#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL
+#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_MSK (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
+#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
+#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY
+#define HBN_RC32K_VREF_DLY_POS (16U)
+#define HBN_RC32K_VREF_DLY_LEN (2U)
+#define HBN_RC32K_VREF_DLY_MSK (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
+#define HBN_RC32K_VREF_DLY_UMSK (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
+#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL
+#define HBN_RC32K_ALLOW_CAL_POS (18U)
+#define HBN_RC32K_ALLOW_CAL_LEN (1U)
+#define HBN_RC32K_ALLOW_CAL_MSK (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
+#define HBN_RC32K_ALLOW_CAL_UMSK (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
+#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN
+#define HBN_RC32K_EXT_CODE_EN_POS (19U)
+#define HBN_RC32K_EXT_CODE_EN_LEN (1U)
+#define HBN_RC32K_EXT_CODE_EN_MSK (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
+#define HBN_RC32K_EXT_CODE_EN_UMSK (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
+#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN
+#define HBN_RC32K_CAL_EN_POS (20U)
+#define HBN_RC32K_CAL_EN_LEN (1U)
+#define HBN_RC32K_CAL_EN_MSK (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
+#define HBN_RC32K_CAL_EN_UMSK (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
+#define HBN_PU_RC32K HBN_PU_RC32K
+#define HBN_PU_RC32K_POS (21U)
+#define HBN_PU_RC32K_LEN (1U)
+#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
+#define HBN_PU_RC32K_UMSK (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
+#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT
+#define HBN_RC32K_CODE_FR_EXT_POS (22U)
+#define HBN_RC32K_CODE_FR_EXT_LEN (10U)
+#define HBN_RC32K_CODE_FR_EXT_MSK (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
+#define HBN_RC32K_CODE_FR_EXT_UMSK (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
+
+/* 0x204 : xtal32k */
+#define HBN_XTAL32K_OFFSET (0x204)
+#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL
+#define HBN_XTAL32K_EXT_SEL_POS (2U)
+#define HBN_XTAL32K_EXT_SEL_LEN (1U)
+#define HBN_XTAL32K_EXT_SEL_MSK (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
+#define HBN_XTAL32K_EXT_SEL_UMSK (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
+#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL
+#define HBN_XTAL32K_AMP_CTRL_POS (3U)
+#define HBN_XTAL32K_AMP_CTRL_LEN (2U)
+#define HBN_XTAL32K_AMP_CTRL_MSK (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
+#define HBN_XTAL32K_AMP_CTRL_UMSK (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
+#define HBN_XTAL32K_REG HBN_XTAL32K_REG
+#define HBN_XTAL32K_REG_POS (5U)
+#define HBN_XTAL32K_REG_LEN (2U)
+#define HBN_XTAL32K_REG_MSK (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
+#define HBN_XTAL32K_REG_UMSK (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
+#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE
+#define HBN_XTAL32K_OUTBUF_STRE_POS (7U)
+#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U)
+#define HBN_XTAL32K_OUTBUF_STRE_MSK (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
+#define HBN_XTAL32K_OUTBUF_STRE_UMSK (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
+#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT
+#define HBN_XTAL32K_OTF_SHORT_POS (8U)
+#define HBN_XTAL32K_OTF_SHORT_LEN (1U)
+#define HBN_XTAL32K_OTF_SHORT_MSK (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
+#define HBN_XTAL32K_OTF_SHORT_UMSK (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
+#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE
+#define HBN_XTAL32K_INV_STRE_POS (9U)
+#define HBN_XTAL32K_INV_STRE_LEN (2U)
+#define HBN_XTAL32K_INV_STRE_MSK (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
+#define HBN_XTAL32K_INV_STRE_UMSK (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
+#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK
+#define HBN_XTAL32K_CAPBANK_POS (11U)
+#define HBN_XTAL32K_CAPBANK_LEN (6U)
+#define HBN_XTAL32K_CAPBANK_MSK (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
+#define HBN_XTAL32K_CAPBANK_UMSK (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
+#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT
+#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U)
+#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U)
+#define HBN_XTAL32K_AC_CAP_SHORT_MSK (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
+#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
+#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF
+#define HBN_PU_XTAL32K_BUF_POS (18U)
+#define HBN_PU_XTAL32K_BUF_LEN (1U)
+#define HBN_PU_XTAL32K_BUF_MSK (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
+#define HBN_PU_XTAL32K_BUF_UMSK (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
+#define HBN_PU_XTAL32K HBN_PU_XTAL32K
+#define HBN_PU_XTAL32K_POS (19U)
+#define HBN_PU_XTAL32K_LEN (1U)
+#define HBN_PU_XTAL32K_MSK (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
+#define HBN_PU_XTAL32K_UMSK (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
+#define HBN_XTAL32K_HIZ_EN HBN_XTAL32K_HIZ_EN
+#define HBN_XTAL32K_HIZ_EN_POS (20U)
+#define HBN_XTAL32K_HIZ_EN_LEN (1U)
+#define HBN_XTAL32K_HIZ_EN_MSK (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)
+#define HBN_XTAL32K_HIZ_EN_UMSK (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS))
+#define HBN_DTEN_XTAL32K HBN_DTEN_XTAL32K
+#define HBN_DTEN_XTAL32K_POS (22U)
+#define HBN_DTEN_XTAL32K_LEN (1U)
+#define HBN_DTEN_XTAL32K_MSK (((1U << HBN_DTEN_XTAL32K_LEN) - 1) << HBN_DTEN_XTAL32K_POS)
+#define HBN_DTEN_XTAL32K_UMSK (~(((1U << HBN_DTEN_XTAL32K_LEN) - 1) << HBN_DTEN_XTAL32K_POS))
+#define HBN_TEN_XTAL32K HBN_TEN_XTAL32K
+#define HBN_TEN_XTAL32K_POS (23U)
+#define HBN_TEN_XTAL32K_LEN (1U)
+#define HBN_TEN_XTAL32K_MSK (((1U << HBN_TEN_XTAL32K_LEN) - 1) << HBN_TEN_XTAL32K_POS)
+#define HBN_TEN_XTAL32K_UMSK (~(((1U << HBN_TEN_XTAL32K_LEN) - 1) << HBN_TEN_XTAL32K_POS))
+#define HBN_F32K_SEL_RTC HBN_F32K_SEL_RTC
+#define HBN_F32K_SEL_RTC_POS (24U)
+#define HBN_F32K_SEL_RTC_LEN (1U)
+#define HBN_F32K_SEL_RTC_MSK (((1U << HBN_F32K_SEL_RTC_LEN) - 1) << HBN_F32K_SEL_RTC_POS)
+#define HBN_F32K_SEL_RTC_UMSK (~(((1U << HBN_F32K_SEL_RTC_LEN) - 1) << HBN_F32K_SEL_RTC_POS))
+
+/* 0x208 : rtc_rst_ctrl */
+#define HBN_RTC_RST_CTRL_OFFSET (0x208)
+#define HBN_RTC_RST_WAIT_CNT_RTC HBN_RTC_RST_WAIT_CNT_RTC
+#define HBN_RTC_RST_WAIT_CNT_RTC_POS (0U)
+#define HBN_RTC_RST_WAIT_CNT_RTC_LEN (16U)
+#define HBN_RTC_RST_WAIT_CNT_RTC_MSK (((1U << HBN_RTC_RST_WAIT_CNT_RTC_LEN) - 1) << HBN_RTC_RST_WAIT_CNT_RTC_POS)
+#define HBN_RTC_RST_WAIT_CNT_RTC_UMSK (~(((1U << HBN_RTC_RST_WAIT_CNT_RTC_LEN) - 1) << HBN_RTC_RST_WAIT_CNT_RTC_POS))
+#define HBN_RTC_RST_REFDIV_RTC HBN_RTC_RST_REFDIV_RTC
+#define HBN_RTC_RST_REFDIV_RTC_POS (16U)
+#define HBN_RTC_RST_REFDIV_RTC_LEN (3U)
+#define HBN_RTC_RST_REFDIV_RTC_MSK (((1U << HBN_RTC_RST_REFDIV_RTC_LEN) - 1) << HBN_RTC_RST_REFDIV_RTC_POS)
+#define HBN_RTC_RST_REFDIV_RTC_UMSK (~(((1U << HBN_RTC_RST_REFDIV_RTC_LEN) - 1) << HBN_RTC_RST_REFDIV_RTC_POS))
+#define HBN_RTC_RST_CTRL_MISC HBN_RTC_RST_CTRL_MISC
+#define HBN_RTC_RST_CTRL_MISC_POS (19U)
+#define HBN_RTC_RST_CTRL_MISC_LEN (13U)
+#define HBN_RTC_RST_CTRL_MISC_MSK (((1U << HBN_RTC_RST_CTRL_MISC_LEN) - 1) << HBN_RTC_RST_CTRL_MISC_POS)
+#define HBN_RTC_RST_CTRL_MISC_UMSK (~(((1U << HBN_RTC_RST_CTRL_MISC_LEN) - 1) << HBN_RTC_RST_CTRL_MISC_POS))
+
+/* 0x20C : rtc_rst_ctrl2 */
+#define HBN_RTC_RST_CTRL2_OFFSET (0x20C)
+#define HBN_RTC_RESV HBN_RTC_RESV
+#define HBN_RTC_RESV_POS (0U)
+#define HBN_RTC_RESV_LEN (8U)
+#define HBN_RTC_RESV_MSK (((1U << HBN_RTC_RESV_LEN) - 1) << HBN_RTC_RESV_POS)
+#define HBN_RTC_RESV_UMSK (~(((1U << HBN_RTC_RESV_LEN) - 1) << HBN_RTC_RESV_POS))
+#define HBN_REG_EN_HW_PU_RC32K HBN_REG_EN_HW_PU_RC32K
+#define HBN_REG_EN_HW_PU_RC32K_POS (8U)
+#define HBN_REG_EN_HW_PU_RC32K_LEN (1U)
+#define HBN_REG_EN_HW_PU_RC32K_MSK (((1U << HBN_REG_EN_HW_PU_RC32K_LEN) - 1) << HBN_REG_EN_HW_PU_RC32K_POS)
+#define HBN_REG_EN_HW_PU_RC32K_UMSK (~(((1U << HBN_REG_EN_HW_PU_RC32K_LEN) - 1) << HBN_REG_EN_HW_PU_RC32K_POS))
+
+struct hbn_reg {
+ /* 0x0 : HBN_CTL */
+ union {
+ struct {
+ uint32_t rtc_ctl : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t rtc_dly_option : 1; /* [ 4], r/w, 0x0 */
+ uint32_t pu_ldo18io_aon : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */
+ uint32_t trap_mode : 1; /* [ 8], r, 0x0 */
+ uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */
+ uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */
+ uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */
+ uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */
+ uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */
+ uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */
+ uint32_t pu_dcdc_aon : 1; /* [ 23], r/w, 0x1 */
+ uint32_t pu_dcdc18_aon : 1; /* [ 24], r/w, 0x1 */
+ uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */
+ uint32_t sram_slp : 1; /* [ 27], r, 0x0 */
+ uint32_t hbn_state : 4; /* [31:28], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_CTL;
+
+ /* 0x4 : HBN_TIME_L */
+ union {
+ struct {
+ uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_TIME_L;
+
+ /* 0x8 : HBN_TIME_H */
+ union {
+ struct {
+ uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_TIME_H;
+
+ /* 0xC : RTC_TIME_L */
+ union {
+ struct {
+ uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } RTC_TIME_L;
+
+ /* 0x10 : RTC_TIME_H */
+ union {
+ struct {
+ uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */
+ uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */
+ uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } RTC_TIME_H;
+
+ /* 0x14 : HBN_IRQ_MODE */
+ union {
+ struct {
+ uint32_t hbn_pin_wakeup_mode : 4; /* [ 3: 0], r/w, 0x5 */
+ uint32_t hbn_pin_wakeup_mask : 9; /* [12: 4], r/w, 0x0 */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
+ uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */
+ uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */
+ uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */
+ uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_IRQ_MODE;
+
+ /* 0x18 : HBN_IRQ_STAT */
+ union {
+ struct {
+ uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_IRQ_STAT;
+
+ /* 0x1C : HBN_IRQ_CLR */
+ union {
+ struct {
+ uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_IRQ_CLR;
+
+ /* 0x20 : HBN_PIR_CFG */
+ union {
+ struct {
+ uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t gpadc_cs : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_PIR_CFG;
+
+ /* 0x24 : HBN_PIR_VTH */
+ union {
+ struct {
+ uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */
+ uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_PIR_VTH;
+
+ /* 0x28 : HBN_PIR_INTERVAL */
+ union {
+ struct {
+ uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_PIR_INTERVAL;
+
+ /* 0x2C : HBN_BOR_CFG */
+ union {
+ struct {
+ uint32_t bod_sel : 1; /* [ 0], r/w, 0x0 */
+ uint32_t bod_vth : 3; /* [ 3: 1], r/w, 0x5 */
+ uint32_t pu_bod : 1; /* [ 4], r/w, 0x0 */
+ uint32_t r_bod_out : 1; /* [ 5], r, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_BOR_CFG;
+
+ /* 0x30 : HBN_GLB */
+ union {
+ struct {
+ uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */
+ uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */
+ uint32_t hbn_reset_event : 6; /* [12: 7], r, 0x0 */
+ uint32_t hbn_clr_reset_event : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */
+ uint32_t hbn_uart_clk_sel2 : 1; /* [ 15], r/w, 0x0 */
+ uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */
+ uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
+ uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */
+ uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */
+ } BF;
+ uint32_t WORD;
+ } HBN_GLB;
+
+ /* 0x34 : HBN_SRAM */
+ union {
+ struct {
+ uint32_t reserved_0_5 : 6; /* [ 5: 0], rsvd, 0x0 */
+ uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */
+ uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_SRAM;
+
+ /* 0x38 : HBN_PAD_CTRL_0 */
+ union {
+ struct {
+ uint32_t reg_aon_pad_ie_smt : 9; /* [ 8: 0], r/w, 0x0 */
+ uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
+ uint32_t reg_aon_led_sel : 9; /* [18:10], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t reg_en_aon_ctrl_gpio : 9; /* [28:20], r/w, 0x180 */
+ uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */
+ uint32_t reg_aon_gpio_iso_mode : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_PAD_CTRL_0;
+
+ /* 0x3C : HBN_PAD_CTRL_1 */
+ union {
+ struct {
+ uint32_t reg_aon_pad_oe : 9; /* [ 8: 0], r/w, 0x0 */
+ uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
+ uint32_t reg_aon_pad_pd : 9; /* [18:10], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t reg_aon_pad_pu : 9; /* [28:20], r/w, 0x0 */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_PAD_CTRL_1;
+
+ /* 0x40 reserved */
+ uint8_t RESERVED0x40[192];
+
+ /* 0x100 : HBN_RSV0 */
+ union {
+ struct {
+ uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_RSV0;
+
+ /* 0x104 : HBN_RSV1 */
+ union {
+ struct {
+ uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffff */
+ } BF;
+ uint32_t WORD;
+ } HBN_RSV1;
+
+ /* 0x108 : HBN_RSV2 */
+ union {
+ struct {
+ uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } HBN_RSV2;
+
+ /* 0x10C : HBN_RSV3 */
+ union {
+ struct {
+ uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffff */
+ } BF;
+ uint32_t WORD;
+ } HBN_RSV3;
+
+ /* 0x110 reserved */
+ uint8_t RESERVED0x110[240];
+
+ /* 0x200 : rc32k_ctrl0 */
+ union {
+ struct {
+ uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */
+ uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */
+ uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */
+ uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */
+ uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */
+ uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */
+ uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */
+ uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */
+ uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */
+ uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */
+ uint32_t pu_rc32k : 1; /* [ 21], r/w, 0x1 */
+ uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x12c */
+ } BF;
+ uint32_t WORD;
+ } rc32k_ctrl0;
+
+ /* 0x204 : xtal32k */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */
+ uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */
+ uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */
+ uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */
+ uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */
+ uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */
+ uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x0 */
+ uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */
+ uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x0 */
+ uint32_t xtal32k_hiz_en : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */
+ uint32_t dten_xtal32k : 1; /* [ 22], r/w, 0x0 */
+ uint32_t ten_xtal32k : 1; /* [ 23], r/w, 0x0 */
+ uint32_t f32k_sel_rtc : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } xtal32k;
+
+ /* 0x208 : rtc_rst_ctrl */
+ union {
+ struct {
+ uint32_t rtc_rst_wait_cnt_rtc : 16; /* [15: 0], r/w, 0x3c00 */
+ uint32_t rtc_rst_refdiv_rtc : 3; /* [18:16], r/w, 0x4 */
+ uint32_t rtc_rst_ctrl_misc : 13; /* [31:19], r/w, 0xa12 */
+ } BF;
+ uint32_t WORD;
+ } rtc_rst_ctrl;
+
+ /* 0x20C : rtc_rst_ctrl2 */
+ union {
+ struct {
+ uint32_t rtc_resv : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_en_hw_pu_rc32k : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } rtc_rst_ctrl2;
+};
+
+typedef volatile struct hbn_reg hbn_reg_t;
+
+#endif /* __HBN_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ipc_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ipc_reg.h
new file mode 100644
index 00000000..266b5cbc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/ipc_reg.h
@@ -0,0 +1,313 @@
+/**
+ ******************************************************************************
+ * @file ipc_reg.h
+ * @version V1.2
+ * @date 2020-09-21
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __IPC_REG_H__
+#define __IPC_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : Interrupt Set Write Register */
+#define IPC_CPU1_IPC_ISWR_OFFSET (0x0)
+#define IPC_CPU1_IPC_ISWR IPC_CPU1_IPC_ISWR
+#define IPC_CPU1_IPC_ISWR_POS (0U)
+#define IPC_CPU1_IPC_ISWR_LEN (16U)
+#define IPC_CPU1_IPC_ISWR_MSK (((1U << IPC_CPU1_IPC_ISWR_LEN) - 1) << IPC_CPU1_IPC_ISWR_POS)
+#define IPC_CPU1_IPC_ISWR_UMSK (~(((1U << IPC_CPU1_IPC_ISWR_LEN) - 1) << IPC_CPU1_IPC_ISWR_POS))
+
+/* 0x4 : Interrupt raw status Register */
+#define IPC_CPU1_IPC_IRSRR_OFFSET (0x4)
+#define IPC_CPU1_IPC_IRSRR IPC_CPU1_IPC_IRSRR
+#define IPC_CPU1_IPC_IRSRR_POS (0U)
+#define IPC_CPU1_IPC_IRSRR_LEN (16U)
+#define IPC_CPU1_IPC_IRSRR_MSK (((1U << IPC_CPU1_IPC_IRSRR_LEN) - 1) << IPC_CPU1_IPC_IRSRR_POS)
+#define IPC_CPU1_IPC_IRSRR_UMSK (~(((1U << IPC_CPU1_IPC_IRSRR_LEN) - 1) << IPC_CPU1_IPC_IRSRR_POS))
+
+/* 0x8 : Interrupt Clear Register */
+#define IPC_CPU1_IPC_ICR_OFFSET (0x8)
+#define IPC_CPU1_IPC_ICR IPC_CPU1_IPC_ICR
+#define IPC_CPU1_IPC_ICR_POS (0U)
+#define IPC_CPU1_IPC_ICR_LEN (16U)
+#define IPC_CPU1_IPC_ICR_MSK (((1U << IPC_CPU1_IPC_ICR_LEN) - 1) << IPC_CPU1_IPC_ICR_POS)
+#define IPC_CPU1_IPC_ICR_UMSK (~(((1U << IPC_CPU1_IPC_ICR_LEN) - 1) << IPC_CPU1_IPC_ICR_POS))
+
+/* 0xc : Interrupt Unmask Set Register */
+#define IPC_CPU1_IPC_IUSR_OFFSET (0xc)
+#define IPC_CPU1_IPC_IUSR IPC_AP_IPC_IUSR
+#define IPC_CPU1_IPC_IUSR_POS (0U)
+#define IPC_CPU1_IPC_IUSR_LEN (16U)
+#define IPC_CPU1_IPC_IUSR_MSK (((1U << IPC_CPU1_IPC_IUSR_LEN) - 1) << IPC_CPU1_IPC_IUSR_POS)
+#define IPC_CPU1_IPC_IUSR_UMSK (~(((1U << IPC_CPU1_IPC_IUSR_LEN) - 1) << IPC_CPU1_IPC_IUSR_POS))
+
+/* 0x10 : Interrupt Unmask Clear Register */
+#define IPC_CPU1_IPC_IUCR_OFFSET (0x10)
+#define IPC_CPU1_IPC_IUCR IPC_CPU1_IPC_IUCR
+#define IPC_CPU1_IPC_IUCR_POS (0U)
+#define IPC_CPU1_IPC_IUCR_LEN (16U)
+#define IPC_CPU1_IPC_IUCR_MSK (((1U << IPC_CPU1_IPC_IUCR_LEN) - 1) << IPC_CPU1_IPC_IUCR_POS)
+#define IPC_CPU1_IPC_IUCR_UMSK (~(((1U << IPC_CPU1_IPC_IUCR_LEN) - 1) << IPC_CPU1_IPC_IUCR_POS))
+
+/* 0x14 : Interrupt Line Sel Low Register */
+#define IPC_CPU1_IPC_ILSLR_OFFSET (0x14)
+#define IPC_CPU1_IPC_ILSLR IPC_CPU1_IPC_ILSLR
+#define IPC_CPU1_IPC_ILSLR_POS (0U)
+#define IPC_CPU1_IPC_ILSLR_LEN (32U)
+#define IPC_CPU1_IPC_ILSLR_MSK (((1U << IPC_CPU1_IPC_ILSLR_LEN) - 1) << IPC_CPU1_IPC_ILSLR_POS)
+#define IPC_CPU1_IPC_ILSLR_UMSK (~(((1U << IPC_CPU1_IPC_ILSLR_LEN) - 1) << IPC_CPU1_IPC_ILSLR_POS))
+
+/* 0x18 : Interrupt Line Sel High Register */
+#define IPC_CPU1_IPC_ILSHR_OFFSET (0x18)
+#define IPC_CPU1_IPC_ILSHR IPC_CPU1_IPC_ILSHR
+#define IPC_CPU1_IPC_ILSHR_POS (0U)
+#define IPC_CPU1_IPC_ILSHR_LEN (32U)
+#define IPC_CPU1_IPC_ILSHR_MSK (((1U << IPC_CPU1_IPC_ILSHR_LEN) - 1) << IPC_CPU1_IPC_ILSHR_POS)
+#define IPC_CPU1_IPC_ILSHR_UMSK (~(((1U << IPC_CPU1_IPC_ILSHR_LEN) - 1) << IPC_CPU1_IPC_ILSHR_POS))
+
+/* 0x1C : Interrupt status Register */
+#define IPC_CPU1_IPC_ISR_OFFSET (0x1C)
+#define IPC_CPU1_IPC_ISR IPC_CPU1_IPC_ISR
+#define IPC_CPU1_IPC_ISR_POS (0U)
+#define IPC_CPU1_IPC_ISR_LEN (16U)
+#define IPC_CPU1_IPC_ISR_MSK (((1U << IPC_CPU1_IPC_ISR_LEN) - 1) << IPC_CPU1_IPC_ISR_POS)
+#define IPC_CPU1_IPC_ISR_UMSK (~(((1U << IPC_CPU1_IPC_ISR_LEN) - 1) << IPC_CPU1_IPC_ISR_POS))
+
+/* 0x20 : Interrupt Set Write Register */
+#define IPC_CPU0_IPC_ISWR_OFFSET (0x20)
+#define IPC_CPU0_IPC_ISWR IPC_CPU0_IPC_ISWR
+#define IPC_CPU0_IPC_ISWR_POS (0U)
+#define IPC_CPU0_IPC_ISWR_LEN (16U)
+#define IPC_CPU0_IPC_ISWR_MSK (((1U << IPC_CPU0_IPC_ISWR_LEN) - 1) << IPC_CPU0_IPC_ISWR_POS)
+#define IPC_CPU0_IPC_ISWR_UMSK (~(((1U << IPC_CPU0_IPC_ISWR_LEN) - 1) << IPC_CPU0_IPC_ISWR_POS))
+
+/* 0x24 : Interrupt raw status Register */
+#define IPC_CPU0_IPC_IRSRR_OFFSET (0x24)
+#define IPC_CPU0_IPC_IRSRR IPC_CPU0_IPC_IRSRR
+#define IPC_CPU0_IPC_IRSRR_POS (0U)
+#define IPC_CPU0_IPC_IRSRR_LEN (16U)
+#define IPC_CPU0_IPC_IRSRR_MSK (((1U << IPC_CPU0_IPC_IRSRR_LEN) - 1) << IPC_CPU0_IPC_IRSRR_POS)
+#define IPC_CPU0_IPC_IRSRR_UMSK (~(((1U << IPC_CPU0_IPC_IRSRR_LEN) - 1) << IPC_CPU0_IPC_IRSRR_POS))
+
+/* 0x28 : Interrupt Clear Register */
+#define IPC_CPU0_IPC_ICR_OFFSET (0x28)
+#define IPC_CPU0_IPC_ICR IPC_CPU0_IPC_ICR
+#define IPC_CPU0_IPC_ICR_POS (0U)
+#define IPC_CPU0_IPC_ICR_LEN (16U)
+#define IPC_CPU0_IPC_ICR_MSK (((1U << IPC_CPU0_IPC_ICR_LEN) - 1) << IPC_CPU0_IPC_ICR_POS)
+#define IPC_CPU0_IPC_ICR_UMSK (~(((1U << IPC_CPU0_IPC_ICR_LEN) - 1) << IPC_CPU0_IPC_ICR_POS))
+
+/* 0x2c : Interrupt Unmask Set Register */
+#define IPC_CPU0_IPC_IUSR_OFFSET (0x2c)
+#define IPC_CPU0_IPC_IUSR IPC_CPU0_IPC_IUSR
+#define IPC_CPU0_IPC_IUSR_POS (0U)
+#define IPC_NP_IPC_IUSR_LEN (16U)
+#define IPC_CPU0_IPC_IUSR_MSK (((1U << IPC_CPU0_IPC_IUSR_LEN) - 1) << IPC_CPU0_IPC_IUSR_POS)
+#define IPC_CPU0_IPC_IUSR_UMSK (~(((1U << IPC_CPU0_IPC_IUSR_LEN) - 1) << IPC_CPU0_IPC_IUSR_POS))
+
+/* 0x30 : Interrupt Unmask Clear Register */
+#define IPC_CPU0_IPC_IUCR_OFFSET (0x30)
+#define IPC_CPU0_IPC_IUCR IPC_CPU0_IPC_IUCR
+#define IPC_CPU0_IPC_IUCR_POS (0U)
+#define IPC_CPU0_IPC_IUCR_LEN (16U)
+#define IPC_CPU0_IPC_IUCR_MSK (((1U << IPC_CPU0_IPC_IUCR_LEN) - 1) << IPC_CPU0_IPC_IUCR_POS)
+#define IPC_CPU0_IPC_IUCR_UMSK (~(((1U << IPC_CPU0_IPC_IUCR_LEN) - 1) << IPC_CPU0_IPC_IUCR_POS))
+
+/* 0x34 : Interrupt Line Sel Low Register */
+#define IPC_CPU0_IPC_ILSLR_OFFSET (0x34)
+#define IPC_CPU0_IPC_ILSLR IPC_CPU0_IPC_ILSLR
+#define IPC_CPU0_IPC_ILSLR_POS (0U)
+#define IPC_CPU0_IPC_ILSLR_LEN (32U)
+#define IPC_CPU0_IPC_ILSLR_MSK (((1U << IPC_CPU0_IPC_ILSLR_LEN) - 1) << IPC_CPU0_IPC_ILSLR_POS)
+#define IPC_CPU0_IPC_ILSLR_UMSK (~(((1U << IPC_CPU0_IPC_ILSLR_LEN) - 1) << IPC_CPU0_IPC_ILSLR_POS))
+
+/* 0x38 : Interrupt Line Sel High Register */
+#define IPC_CPU0_IPC_ILSHR_OFFSET (0x38)
+#define IPC_CPU0_IPC_ILSHR IPC_CPU0_IPC_ILSHR
+#define IPC_CPU0_IPC_ILSHR_POS (0U)
+#define IPC_CPU0_IPC_ILSHR_LEN (32U)
+#define IPC_CPU0_IPC_ILSHR_MSK (((1U << IPC_CPU0_IPC_ILSHR_LEN) - 1) << IPC_CPU0_IPC_ILSHR_POS)
+#define IPC_CPU0_IPC_ILSHR_UMSK (~(((1U << IPC_CPU0_IPC_ILSHR_LEN) - 1) << IPC_CPU0_IPC_ILSHR_POS))
+
+/* 0x3C : Interrupt status Register */
+#define IPC_CPU0_IPC_ISR_OFFSET (0x3C)
+#define IPC_CPU0_IPC_ISR IPC_CPU0_IPC_ISR
+#define IPC_CPU0_IPC_ISR_POS (0U)
+#define IPC_CPU0_IPC_ISR_LEN (16U)
+#define IPC_CPU0_IPC_ISR_MSK (((1U << IPC_CPU0_IPC_ISR_LEN) - 1) << IPC_CPU0_IPC_ISR_POS)
+#define IPC_CPU0_IPC_ISR_UMSK (~(((1U << IPC_CPU0_IPC_ISR_LEN) - 1) << IPC_CPU0_IPC_ISR_POS))
+
+struct ipc_reg {
+ /* 0x0 : Interrupt Set Write Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_ISWR : 16; /* [15: 0], WO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_ISWR;
+
+ /* 0x4 : Interrupt raw status Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_IRSRR : 16; /* [15: 0], RO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_IRSRR;
+
+ /* 0x8 : Interrupt Clear Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_ICR : 16; /* [15: 0], WO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_ICR;
+
+ /* 0xc : Interrupt Unmask Set Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_IUSR : 16; /* [15: 0], RO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_IUSR;
+
+ /* 0x10 : Interrupt Unmask Clear Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_IUCR : 16; /* [15: 0], WO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_IUCR;
+
+ /* 0x14 : Interrupt Line Sel Low Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_ILSLR : 32; /* [31: 0], RW, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_ILSLR;
+
+ /* 0x18 : Interrupt Line Sel High Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_ILSHR : 32; /* [31: 0], RW, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_ILSHR;
+
+ /* 0x1C : Interrupt status Register */
+ union {
+ struct {
+ uint32_t CPU1_IPC_ISR : 16; /* [15: 0], RO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU1_IPC_ISR;
+
+ /* 0x20 : Interrupt Set Write Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_ISWR : 16; /* [15: 0], WO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_ISWR;
+
+ /* 0x24 : Interrupt raw status Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_IRSRR : 16; /* [15: 0], RO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_IRSRR;
+
+ /* 0x28 : Interrupt Clear Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_ICR : 16; /* [15: 0], WO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_ICR;
+
+ /* 0x2c : Interrupt Unmask Set Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_IUSR : 16; /* [15: 0], RO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_IUSR;
+
+ /* 0x30 : Interrupt Unmask Clear Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_IUCR : 16; /* [15: 0], RO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_IUCR;
+
+ /* 0x34 : Interrupt Line Sel Low Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_ILSLR : 32; /* [31: 0], RW, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_ILSLR;
+
+ /* 0x38 : Interrupt Line Sel High Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_ILSHR : 32; /* [31: 0], RW, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_ILSHR;
+
+ /* 0x3C : Interrupt status Register */
+ union {
+ struct {
+ uint32_t CPU0_IPC_ISR : 16; /* [15: 0], RO, 0x0 */
+ uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_IPC_ISR;
+};
+
+typedef volatile struct ipc_reg ipc_reg_t;
+
+#endif /* __IPC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mcu_misc_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mcu_misc_reg.h
new file mode 100644
index 00000000..bb835d4e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mcu_misc_reg.h
@@ -0,0 +1,352 @@
+/**
+ ******************************************************************************
+ * @file mcu_misc_reg.h
+ * @version V1.0
+ * @date 2021-07-12
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __MCU_MISC_REG_H__
+#define __MCU_MISC_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : mcu_bus_cfg0 */
+#define MCU_MISC_MCU_BUS_CFG0_OFFSET (0x0)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS (0U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN (1U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_MSK (((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS))
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS (1U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN (1U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_MSK (((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS))
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT MCU_MISC_STS_MCU_INFRA_TIMEOUT
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS (16U)
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN (1U)
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_MSK (((1U << MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN) - 1) << MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS)
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_UMSK (~(((1U << MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN) - 1) << MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS))
+
+/* 0x4 : mcu_bus_cfg1 */
+#define MCU_MISC_MCU_BUS_CFG1_OFFSET (0x4)
+#define MCU_MISC_REG_MCU1_HQOS MCU_MISC_REG_MCU1_HQOS
+#define MCU_MISC_REG_MCU1_HQOS_POS (0U)
+#define MCU_MISC_REG_MCU1_HQOS_LEN (1U)
+#define MCU_MISC_REG_MCU1_HQOS_MSK (((1U << MCU_MISC_REG_MCU1_HQOS_LEN) - 1) << MCU_MISC_REG_MCU1_HQOS_POS)
+#define MCU_MISC_REG_MCU1_HQOS_UMSK (~(((1U << MCU_MISC_REG_MCU1_HQOS_LEN) - 1) << MCU_MISC_REG_MCU1_HQOS_POS))
+#define MCU_MISC_REG_MCU1_AWQOS MCU_MISC_REG_MCU1_AWQOS
+#define MCU_MISC_REG_MCU1_AWQOS_POS (1U)
+#define MCU_MISC_REG_MCU1_AWQOS_LEN (1U)
+#define MCU_MISC_REG_MCU1_AWQOS_MSK (((1U << MCU_MISC_REG_MCU1_AWQOS_LEN) - 1) << MCU_MISC_REG_MCU1_AWQOS_POS)
+#define MCU_MISC_REG_MCU1_AWQOS_UMSK (~(((1U << MCU_MISC_REG_MCU1_AWQOS_LEN) - 1) << MCU_MISC_REG_MCU1_AWQOS_POS))
+#define MCU_MISC_REG_MCU1_ARQOS MCU_MISC_REG_MCU1_ARQOS
+#define MCU_MISC_REG_MCU1_ARQOS_POS (2U)
+#define MCU_MISC_REG_MCU1_ARQOS_LEN (1U)
+#define MCU_MISC_REG_MCU1_ARQOS_MSK (((1U << MCU_MISC_REG_MCU1_ARQOS_LEN) - 1) << MCU_MISC_REG_MCU1_ARQOS_POS)
+#define MCU_MISC_REG_MCU1_ARQOS_UMSK (~(((1U << MCU_MISC_REG_MCU1_ARQOS_LEN) - 1) << MCU_MISC_REG_MCU1_ARQOS_POS))
+#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS MCU_MISC_REG_MCU_X2HS_SP_BYPASS
+#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_POS (3U)
+#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_LEN (1U)
+#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_MSK (((1U << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_LEN) - 1) << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_POS)
+#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_UMSK (~(((1U << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_LEN) - 1) << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_POS))
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT MCU_MISC_REG_X_WTHRE_MCU2EXT
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_POS (7U)
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN (2U)
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_MSK (((1U << MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN) - 1) << MCU_MISC_REG_X_WTHRE_MCU2EXT_POS)
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_UMSK (~(((1U << MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN) - 1) << MCU_MISC_REG_X_WTHRE_MCU2EXT_POS))
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE MCU_MISC_REG_MCU_INFRA_ARB_MODE
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS (16U)
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN (1U)
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_MSK (((1U << MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS)
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS))
+
+/* 0x14 : mcu_e907_rtc */
+#define MCU_MISC_MCU_E907_RTC_OFFSET (0x14)
+#define MCU_MISC_REG_MCU_RTC_DIV MCU_MISC_REG_MCU_RTC_DIV
+#define MCU_MISC_REG_MCU_RTC_DIV_POS (0U)
+#define MCU_MISC_REG_MCU_RTC_DIV_LEN (10U)
+#define MCU_MISC_REG_MCU_RTC_DIV_MSK (((1U << MCU_MISC_REG_MCU_RTC_DIV_LEN) - 1) << MCU_MISC_REG_MCU_RTC_DIV_POS)
+#define MCU_MISC_REG_MCU_RTC_DIV_UMSK (~(((1U << MCU_MISC_REG_MCU_RTC_DIV_LEN) - 1) << MCU_MISC_REG_MCU_RTC_DIV_POS))
+#define MCU_MISC_REG_MCU_RTC_RST MCU_MISC_REG_MCU_RTC_RST
+#define MCU_MISC_REG_MCU_RTC_RST_POS (30U)
+#define MCU_MISC_REG_MCU_RTC_RST_LEN (1U)
+#define MCU_MISC_REG_MCU_RTC_RST_MSK (((1U << MCU_MISC_REG_MCU_RTC_RST_LEN) - 1) << MCU_MISC_REG_MCU_RTC_RST_POS)
+#define MCU_MISC_REG_MCU_RTC_RST_UMSK (~(((1U << MCU_MISC_REG_MCU_RTC_RST_LEN) - 1) << MCU_MISC_REG_MCU_RTC_RST_POS))
+#define MCU_MISC_REG_MCU_RTC_EN MCU_MISC_REG_MCU_RTC_EN
+#define MCU_MISC_REG_MCU_RTC_EN_POS (31U)
+#define MCU_MISC_REG_MCU_RTC_EN_LEN (1U)
+#define MCU_MISC_REG_MCU_RTC_EN_MSK (((1U << MCU_MISC_REG_MCU_RTC_EN_LEN) - 1) << MCU_MISC_REG_MCU_RTC_EN_POS)
+#define MCU_MISC_REG_MCU_RTC_EN_UMSK (~(((1U << MCU_MISC_REG_MCU_RTC_EN_LEN) - 1) << MCU_MISC_REG_MCU_RTC_EN_POS))
+
+/* 0x100 : mcu_cfg1 */
+#define MCU_MISC_MCU_CFG1_OFFSET (0x100)
+#define MCU_MISC_REG_MCU1_DFS_REQ MCU_MISC_REG_MCU1_DFS_REQ
+#define MCU_MISC_REG_MCU1_DFS_REQ_POS (0U)
+#define MCU_MISC_REG_MCU1_DFS_REQ_LEN (1U)
+#define MCU_MISC_REG_MCU1_DFS_REQ_MSK (((1U << MCU_MISC_REG_MCU1_DFS_REQ_LEN) - 1) << MCU_MISC_REG_MCU1_DFS_REQ_POS)
+#define MCU_MISC_REG_MCU1_DFS_REQ_UMSK (~(((1U << MCU_MISC_REG_MCU1_DFS_REQ_LEN) - 1) << MCU_MISC_REG_MCU1_DFS_REQ_POS))
+#define MCU_MISC_STS_MCU1_DFS_ACK MCU_MISC_STS_MCU1_DFS_ACK
+#define MCU_MISC_STS_MCU1_DFS_ACK_POS (2U)
+#define MCU_MISC_STS_MCU1_DFS_ACK_LEN (1U)
+#define MCU_MISC_STS_MCU1_DFS_ACK_MSK (((1U << MCU_MISC_STS_MCU1_DFS_ACK_LEN) - 1) << MCU_MISC_STS_MCU1_DFS_ACK_POS)
+#define MCU_MISC_STS_MCU1_DFS_ACK_UMSK (~(((1U << MCU_MISC_STS_MCU1_DFS_ACK_LEN) - 1) << MCU_MISC_STS_MCU1_DFS_ACK_POS))
+#define MCU_MISC_REG_MCU1_SRST_EN MCU_MISC_REG_MCU1_SRST_EN
+#define MCU_MISC_REG_MCU1_SRST_EN_POS (4U)
+#define MCU_MISC_REG_MCU1_SRST_EN_LEN (2U)
+#define MCU_MISC_REG_MCU1_SRST_EN_MSK (((1U << MCU_MISC_REG_MCU1_SRST_EN_LEN) - 1) << MCU_MISC_REG_MCU1_SRST_EN_POS)
+#define MCU_MISC_REG_MCU1_SRST_EN_UMSK (~(((1U << MCU_MISC_REG_MCU1_SRST_EN_LEN) - 1) << MCU_MISC_REG_MCU1_SRST_EN_POS))
+#define MCU_MISC_STS_MCU1_LPMD_B MCU_MISC_STS_MCU1_LPMD_B
+#define MCU_MISC_STS_MCU1_LPMD_B_POS (10U)
+#define MCU_MISC_STS_MCU1_LPMD_B_LEN (2U)
+#define MCU_MISC_STS_MCU1_LPMD_B_MSK (((1U << MCU_MISC_STS_MCU1_LPMD_B_LEN) - 1) << MCU_MISC_STS_MCU1_LPMD_B_POS)
+#define MCU_MISC_STS_MCU1_LPMD_B_UMSK (~(((1U << MCU_MISC_STS_MCU1_LPMD_B_LEN) - 1) << MCU_MISC_STS_MCU1_LPMD_B_POS))
+#define MCU_MISC_MCU1_WFI_FORCE MCU_MISC_MCU1_WFI_FORCE
+#define MCU_MISC_MCU1_WFI_FORCE_POS (16U)
+#define MCU_MISC_MCU1_WFI_FORCE_LEN (1U)
+#define MCU_MISC_MCU1_WFI_FORCE_MSK (((1U << MCU_MISC_MCU1_WFI_FORCE_LEN) - 1) << MCU_MISC_MCU1_WFI_FORCE_POS)
+#define MCU_MISC_MCU1_WFI_FORCE_UMSK (~(((1U << MCU_MISC_MCU1_WFI_FORCE_LEN) - 1) << MCU_MISC_MCU1_WFI_FORCE_POS))
+#define MCU_MISC_MCU1_NDM_RSTN_EN MCU_MISC_MCU1_NDM_RSTN_EN
+#define MCU_MISC_MCU1_NDM_RSTN_EN_POS (28U)
+#define MCU_MISC_MCU1_NDM_RSTN_EN_LEN (1U)
+#define MCU_MISC_MCU1_NDM_RSTN_EN_MSK (((1U << MCU_MISC_MCU1_NDM_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_EN_POS)
+#define MCU_MISC_MCU1_NDM_RSTN_EN_UMSK (~(((1U << MCU_MISC_MCU1_NDM_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_EN_POS))
+#define MCU_MISC_MCU1_HART_RSTN_EN MCU_MISC_MCU1_HART_RSTN_EN
+#define MCU_MISC_MCU1_HART_RSTN_EN_POS (29U)
+#define MCU_MISC_MCU1_HART_RSTN_EN_LEN (1U)
+#define MCU_MISC_MCU1_HART_RSTN_EN_MSK (((1U << MCU_MISC_MCU1_HART_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_EN_POS)
+#define MCU_MISC_MCU1_HART_RSTN_EN_UMSK (~(((1U << MCU_MISC_MCU1_HART_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_EN_POS))
+
+/* 0x110 : mcu1_log1 */
+#define MCU_MISC_MCU1_LOG1_OFFSET (0x110)
+#define MCU_MISC_STS_MCU1_MCAUSE MCU_MISC_STS_MCU1_MCAUSE
+#define MCU_MISC_STS_MCU1_MCAUSE_POS (0U)
+#define MCU_MISC_STS_MCU1_MCAUSE_LEN (32U)
+#define MCU_MISC_STS_MCU1_MCAUSE_MSK (((1U << MCU_MISC_STS_MCU1_MCAUSE_LEN) - 1) << MCU_MISC_STS_MCU1_MCAUSE_POS)
+#define MCU_MISC_STS_MCU1_MCAUSE_UMSK (~(((1U << MCU_MISC_STS_MCU1_MCAUSE_LEN) - 1) << MCU_MISC_STS_MCU1_MCAUSE_POS))
+
+/* 0x114 : mcu1_log2 */
+#define MCU_MISC_MCU1_LOG2_OFFSET (0x114)
+#define MCU_MISC_STS_MCU1_MINTSTATUS MCU_MISC_STS_MCU1_MINTSTATUS
+#define MCU_MISC_STS_MCU1_MINTSTATUS_POS (0U)
+#define MCU_MISC_STS_MCU1_MINTSTATUS_LEN (32U)
+#define MCU_MISC_STS_MCU1_MINTSTATUS_MSK (((1U << MCU_MISC_STS_MCU1_MINTSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MINTSTATUS_POS)
+#define MCU_MISC_STS_MCU1_MINTSTATUS_UMSK (~(((1U << MCU_MISC_STS_MCU1_MINTSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MINTSTATUS_POS))
+
+/* 0x118 : mcu1_log3 */
+#define MCU_MISC_MCU1_LOG3_OFFSET (0x118)
+#define MCU_MISC_STS_MCU1_MSTATUS MCU_MISC_STS_MCU1_MSTATUS
+#define MCU_MISC_STS_MCU1_MSTATUS_POS (0U)
+#define MCU_MISC_STS_MCU1_MSTATUS_LEN (32U)
+#define MCU_MISC_STS_MCU1_MSTATUS_MSK (((1U << MCU_MISC_STS_MCU1_MSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MSTATUS_POS)
+#define MCU_MISC_STS_MCU1_MSTATUS_UMSK (~(((1U << MCU_MISC_STS_MCU1_MSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MSTATUS_POS))
+
+/* 0x11C : mcu1_log4 */
+#define MCU_MISC_MCU1_LOG4_OFFSET (0x11C)
+#define MCU_MISC_STS_MCU1_SP MCU_MISC_STS_MCU1_SP
+#define MCU_MISC_STS_MCU1_SP_POS (0U)
+#define MCU_MISC_STS_MCU1_SP_LEN (1U)
+#define MCU_MISC_STS_MCU1_SP_MSK (((1U << MCU_MISC_STS_MCU1_SP_LEN) - 1) << MCU_MISC_STS_MCU1_SP_POS)
+#define MCU_MISC_STS_MCU1_SP_UMSK (~(((1U << MCU_MISC_STS_MCU1_SP_LEN) - 1) << MCU_MISC_STS_MCU1_SP_POS))
+#define MCU_MISC_STS_MCU1_PC MCU_MISC_STS_MCU1_PC
+#define MCU_MISC_STS_MCU1_PC_POS (1U)
+#define MCU_MISC_STS_MCU1_PC_LEN (31U)
+#define MCU_MISC_STS_MCU1_PC_MSK (((1U << MCU_MISC_STS_MCU1_PC_LEN) - 1) << MCU_MISC_STS_MCU1_PC_POS)
+#define MCU_MISC_STS_MCU1_PC_UMSK (~(((1U << MCU_MISC_STS_MCU1_PC_LEN) - 1) << MCU_MISC_STS_MCU1_PC_POS))
+
+/* 0x120 : mcu1_log5 */
+#define MCU_MISC_MCU1_LOG5_OFFSET (0x120)
+#define MCU_MISC_STS_MCU1_LOCKUP MCU_MISC_STS_MCU1_LOCKUP
+#define MCU_MISC_STS_MCU1_LOCKUP_POS (24U)
+#define MCU_MISC_STS_MCU1_LOCKUP_LEN (1U)
+#define MCU_MISC_STS_MCU1_LOCKUP_MSK (((1U << MCU_MISC_STS_MCU1_LOCKUP_LEN) - 1) << MCU_MISC_STS_MCU1_LOCKUP_POS)
+#define MCU_MISC_STS_MCU1_LOCKUP_UMSK (~(((1U << MCU_MISC_STS_MCU1_LOCKUP_LEN) - 1) << MCU_MISC_STS_MCU1_LOCKUP_POS))
+#define MCU_MISC_STS_MCU1_HALTED MCU_MISC_STS_MCU1_HALTED
+#define MCU_MISC_STS_MCU1_HALTED_POS (25U)
+#define MCU_MISC_STS_MCU1_HALTED_LEN (1U)
+#define MCU_MISC_STS_MCU1_HALTED_MSK (((1U << MCU_MISC_STS_MCU1_HALTED_LEN) - 1) << MCU_MISC_STS_MCU1_HALTED_POS)
+#define MCU_MISC_STS_MCU1_HALTED_UMSK (~(((1U << MCU_MISC_STS_MCU1_HALTED_LEN) - 1) << MCU_MISC_STS_MCU1_HALTED_POS))
+#define MCU_MISC_MCU1_NDM_RSTN_REQ MCU_MISC_MCU1_NDM_RSTN_REQ
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_POS (28U)
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_LEN (1U)
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_MSK (((1U << MCU_MISC_MCU1_NDM_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_REQ_POS)
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_UMSK (~(((1U << MCU_MISC_MCU1_NDM_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_REQ_POS))
+#define MCU_MISC_MCU1_HART_RSTN_REQ MCU_MISC_MCU1_HART_RSTN_REQ
+#define MCU_MISC_MCU1_HART_RSTN_REQ_POS (29U)
+#define MCU_MISC_MCU1_HART_RSTN_REQ_LEN (1U)
+#define MCU_MISC_MCU1_HART_RSTN_REQ_MSK (((1U << MCU_MISC_MCU1_HART_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_REQ_POS)
+#define MCU_MISC_MCU1_HART_RSTN_REQ_UMSK (~(((1U << MCU_MISC_MCU1_HART_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_REQ_POS))
+
+/* 0x208 : irom1_misr_dataout_0 */
+#define MCU_MISC_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
+
+/* 0x20C : irom1_misr_dataout_1 */
+#define MCU_MISC_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
+
+struct mcu_misc_reg {
+ /* 0x0 : mcu_bus_cfg0 */
+ union {
+ struct {
+ uint32_t reg_mcu_infra_timeout_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_mcu_infra_timeout_clr : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */
+ uint32_t sts_mcu_infra_timeout : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu_bus_cfg0;
+
+ /* 0x4 : mcu_bus_cfg1 */
+ union {
+ struct {
+ uint32_t reg_mcu1_hqos : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_mcu1_awqos : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_mcu1_arqos : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_mcu_x2hs_sp_bypass : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reserved_4_6 : 3; /* [ 6: 4], rsvd, 0x0 */
+ uint32_t reg_x_wthre_mcu2ext : 2; /* [ 8: 7], r/w, 0x0 */
+ uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
+ uint32_t reg_mcu_infra_arb_mode : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu_bus_cfg1;
+
+ /* 0x8 reserved */
+ uint8_t RESERVED0x8[12];
+
+ /* 0x14 : mcu_e907_rtc */
+ union {
+ struct {
+ uint32_t reg_mcu_rtc_div : 10; /* [ 9: 0], r/w, 0xa */
+ uint32_t reserved_10_29 : 20; /* [29:10], rsvd, 0x0 */
+ uint32_t reg_mcu_rtc_rst : 1; /* [ 30], r/w, 0x0 */
+ uint32_t reg_mcu_rtc_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } mcu_e907_rtc;
+
+ /* 0x18 reserved */
+ uint8_t RESERVED0x18[232];
+
+ /* 0x100 : mcu_cfg1 */
+ union {
+ struct {
+ uint32_t reg_mcu1_dfs_req : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t sts_mcu1_dfs_ack : 1; /* [ 2], r, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t reg_mcu1_srst_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_9 : 4; /* [ 9: 6], rsvd, 0x0 */
+ uint32_t sts_mcu1_lpmd_b : 2; /* [11:10], r, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t MCU1_WFI_FORCE : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_27 : 11; /* [27:17], rsvd, 0x0 */
+ uint32_t mcu1_ndm_rstn_en : 1; /* [ 28], r/w, 0x0 */
+ uint32_t mcu1_hart_rstn_en : 1; /* [ 29], r/w, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu_cfg1;
+
+ /* 0x104 reserved */
+ uint8_t RESERVED0x104[12];
+
+ /* 0x110 : mcu1_log1 */
+ union {
+ struct {
+ uint32_t sts_mcu1_mcause : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu1_log1;
+
+ /* 0x114 : mcu1_log2 */
+ union {
+ struct {
+ uint32_t sts_mcu1_mintstatus : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu1_log2;
+
+ /* 0x118 : mcu1_log3 */
+ union {
+ struct {
+ uint32_t sts_mcu1_mstatus : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu1_log3;
+
+ /* 0x11C : mcu1_log4 */
+ union {
+ struct {
+ uint32_t sts_mcu1_sp : 1; /* [ 0], r, 0x0 */
+ uint32_t sts_mcu1_pc : 31; /* [31: 1], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu1_log4;
+
+ /* 0x120 : mcu1_log5 */
+ union {
+ struct {
+ uint32_t reserved_0_23 : 24; /* [23: 0], rsvd, 0x0 */
+ uint32_t sts_mcu1_lockup : 1; /* [ 24], r, 0x0 */
+ uint32_t sts_mcu1_halted : 1; /* [ 25], r, 0x0 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t mcu1_ndm_rstn_req : 1; /* [ 28], r, 0x0 */
+ uint32_t mcu1_hart_rstn_req : 1; /* [ 29], r, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mcu1_log5;
+
+ /* 0x124 reserved */
+ uint8_t RESERVED0x124[228];
+
+ /* 0x208 : irom1_misr_dataout_0 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } irom1_misr_dataout_0;
+
+ /* 0x20C : irom1_misr_dataout_1 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } irom1_misr_dataout_1;
+};
+
+typedef volatile struct mcu_misc_reg mcu_misc_reg_t;
+
+#endif /* __MCU_MISC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mm_glb_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mm_glb_reg.h
new file mode 100644
index 00000000..6e9f0e26
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mm_glb_reg.h
@@ -0,0 +1,726 @@
+/**
+ ******************************************************************************
+ * @file mm_glb_reg.h
+ * @version V1.0
+ * @date 2021-07-12
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __MM_GLB_REG_H__
+#define __MM_GLB_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : mm_clk_ctrl_cpu */
+#define MM_GLB_MM_CLK_CTRL_CPU_OFFSET (0x0)
+#define MM_GLB_REG_PLL_EN MM_GLB_REG_PLL_EN
+#define MM_GLB_REG_PLL_EN_POS (0U)
+#define MM_GLB_REG_PLL_EN_LEN (1U)
+#define MM_GLB_REG_PLL_EN_MSK (((1U << MM_GLB_REG_PLL_EN_LEN) - 1) << MM_GLB_REG_PLL_EN_POS)
+#define MM_GLB_REG_PLL_EN_UMSK (~(((1U << MM_GLB_REG_PLL_EN_LEN) - 1) << MM_GLB_REG_PLL_EN_POS))
+#define MM_GLB_REG_CPU_CLK_EN MM_GLB_REG_CPU_CLK_EN
+#define MM_GLB_REG_CPU_CLK_EN_POS (1U)
+#define MM_GLB_REG_CPU_CLK_EN_LEN (1U)
+#define MM_GLB_REG_CPU_CLK_EN_MSK (((1U << MM_GLB_REG_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_CPU_CLK_EN_POS)
+#define MM_GLB_REG_CPU_CLK_EN_UMSK (~(((1U << MM_GLB_REG_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_CPU_CLK_EN_POS))
+#define MM_GLB_REG_BCLK_EN MM_GLB_REG_BCLK_EN
+#define MM_GLB_REG_BCLK_EN_POS (2U)
+#define MM_GLB_REG_BCLK_EN_LEN (1U)
+#define MM_GLB_REG_BCLK_EN_MSK (((1U << MM_GLB_REG_BCLK_EN_LEN) - 1) << MM_GLB_REG_BCLK_EN_POS)
+#define MM_GLB_REG_BCLK_EN_UMSK (~(((1U << MM_GLB_REG_BCLK_EN_LEN) - 1) << MM_GLB_REG_BCLK_EN_POS))
+#define MM_GLB_REG_MM_CPU_CLK_EN MM_GLB_REG_MM_CPU_CLK_EN
+#define MM_GLB_REG_MM_CPU_CLK_EN_POS (3U)
+#define MM_GLB_REG_MM_CPU_CLK_EN_LEN (1U)
+#define MM_GLB_REG_MM_CPU_CLK_EN_MSK (((1U << MM_GLB_REG_MM_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_MM_CPU_CLK_EN_POS)
+#define MM_GLB_REG_MM_CPU_CLK_EN_UMSK (~(((1U << MM_GLB_REG_MM_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_MM_CPU_CLK_EN_POS))
+#define MM_GLB_REG_UART_CLK_SEL MM_GLB_REG_UART_CLK_SEL
+#define MM_GLB_REG_UART_CLK_SEL_POS (4U)
+#define MM_GLB_REG_UART_CLK_SEL_LEN (2U)
+#define MM_GLB_REG_UART_CLK_SEL_MSK (((1U << MM_GLB_REG_UART_CLK_SEL_LEN) - 1) << MM_GLB_REG_UART_CLK_SEL_POS)
+#define MM_GLB_REG_UART_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_UART_CLK_SEL_LEN) - 1) << MM_GLB_REG_UART_CLK_SEL_POS))
+#define MM_GLB_REG_I2C_CLK_SEL MM_GLB_REG_I2C_CLK_SEL
+#define MM_GLB_REG_I2C_CLK_SEL_POS (6U)
+#define MM_GLB_REG_I2C_CLK_SEL_LEN (1U)
+#define MM_GLB_REG_I2C_CLK_SEL_MSK (((1U << MM_GLB_REG_I2C_CLK_SEL_LEN) - 1) << MM_GLB_REG_I2C_CLK_SEL_POS)
+#define MM_GLB_REG_I2C_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_I2C_CLK_SEL_LEN) - 1) << MM_GLB_REG_I2C_CLK_SEL_POS))
+#define MM_GLB_REG_SPI_CLK_SEL MM_GLB_REG_SPI_CLK_SEL
+#define MM_GLB_REG_SPI_CLK_SEL_POS (7U)
+#define MM_GLB_REG_SPI_CLK_SEL_LEN (1U)
+#define MM_GLB_REG_SPI_CLK_SEL_MSK (((1U << MM_GLB_REG_SPI_CLK_SEL_LEN) - 1) << MM_GLB_REG_SPI_CLK_SEL_POS)
+#define MM_GLB_REG_SPI_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_SPI_CLK_SEL_LEN) - 1) << MM_GLB_REG_SPI_CLK_SEL_POS))
+#define MM_GLB_REG_CPU_CLK_SEL MM_GLB_REG_CPU_CLK_SEL
+#define MM_GLB_REG_CPU_CLK_SEL_POS (8U)
+#define MM_GLB_REG_CPU_CLK_SEL_LEN (2U)
+#define MM_GLB_REG_CPU_CLK_SEL_MSK (((1U << MM_GLB_REG_CPU_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_CLK_SEL_POS)
+#define MM_GLB_REG_CPU_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CPU_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_CLK_SEL_POS))
+#define MM_GLB_REG_XCLK_CLK_SEL MM_GLB_REG_XCLK_CLK_SEL
+#define MM_GLB_REG_XCLK_CLK_SEL_POS (10U)
+#define MM_GLB_REG_XCLK_CLK_SEL_LEN (1U)
+#define MM_GLB_REG_XCLK_CLK_SEL_MSK (((1U << MM_GLB_REG_XCLK_CLK_SEL_LEN) - 1) << MM_GLB_REG_XCLK_CLK_SEL_POS)
+#define MM_GLB_REG_XCLK_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_XCLK_CLK_SEL_LEN) - 1) << MM_GLB_REG_XCLK_CLK_SEL_POS))
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL MM_GLB_REG_CPU_ROOT_CLK_SEL
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_POS (11U)
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN (1U)
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_MSK (((1U << MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_ROOT_CLK_SEL_POS)
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_ROOT_CLK_SEL_POS))
+#define MM_GLB_REG_MMCPU0_CLK_EN MM_GLB_REG_MMCPU0_CLK_EN
+#define MM_GLB_REG_MMCPU0_CLK_EN_POS (12U)
+#define MM_GLB_REG_MMCPU0_CLK_EN_LEN (1U)
+#define MM_GLB_REG_MMCPU0_CLK_EN_MSK (((1U << MM_GLB_REG_MMCPU0_CLK_EN_LEN) - 1) << MM_GLB_REG_MMCPU0_CLK_EN_POS)
+#define MM_GLB_REG_MMCPU0_CLK_EN_UMSK (~(((1U << MM_GLB_REG_MMCPU0_CLK_EN_LEN) - 1) << MM_GLB_REG_MMCPU0_CLK_EN_POS))
+#define MM_GLB_REG_BCLK1X_SEL MM_GLB_REG_BCLK1X_SEL
+#define MM_GLB_REG_BCLK1X_SEL_POS (13U)
+#define MM_GLB_REG_BCLK1X_SEL_LEN (2U)
+#define MM_GLB_REG_BCLK1X_SEL_MSK (((1U << MM_GLB_REG_BCLK1X_SEL_LEN) - 1) << MM_GLB_REG_BCLK1X_SEL_POS)
+#define MM_GLB_REG_BCLK1X_SEL_UMSK (~(((1U << MM_GLB_REG_BCLK1X_SEL_LEN) - 1) << MM_GLB_REG_BCLK1X_SEL_POS))
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE MM_GLB_REG_BCLK2X_DIV_ACT_PULSE
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS (18U)
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN (1U)
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_MSK (((1U << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS)
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_UMSK (~(((1U << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS))
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS MM_GLB_REG_BCLK2X_DIV_BYPASS
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_POS (19U)
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN (1U)
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_MSK (((1U << MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_BYPASS_POS)
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_UMSK (~(((1U << MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_BYPASS_POS))
+#define MM_GLB_STS_BCLK2X_PROT_DONE MM_GLB_STS_BCLK2X_PROT_DONE
+#define MM_GLB_STS_BCLK2X_PROT_DONE_POS (20U)
+#define MM_GLB_STS_BCLK2X_PROT_DONE_LEN (1U)
+#define MM_GLB_STS_BCLK2X_PROT_DONE_MSK (((1U << MM_GLB_STS_BCLK2X_PROT_DONE_LEN) - 1) << MM_GLB_STS_BCLK2X_PROT_DONE_POS)
+#define MM_GLB_STS_BCLK2X_PROT_DONE_UMSK (~(((1U << MM_GLB_STS_BCLK2X_PROT_DONE_LEN) - 1) << MM_GLB_STS_BCLK2X_PROT_DONE_POS))
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT MM_GLB_REG_BCLK2X_SW_DONE_CNT
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS (24U)
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN (4U)
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_MSK (((1U << MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN) - 1) << MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS)
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_UMSK (~(((1U << MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN) - 1) << MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS))
+#define MM_GLB_CPU_CLK_SW_STATE MM_GLB_CPU_CLK_SW_STATE
+#define MM_GLB_CPU_CLK_SW_STATE_POS (28U)
+#define MM_GLB_CPU_CLK_SW_STATE_LEN (3U)
+#define MM_GLB_CPU_CLK_SW_STATE_MSK (((1U << MM_GLB_CPU_CLK_SW_STATE_LEN) - 1) << MM_GLB_CPU_CLK_SW_STATE_POS)
+#define MM_GLB_CPU_CLK_SW_STATE_UMSK (~(((1U << MM_GLB_CPU_CLK_SW_STATE_LEN) - 1) << MM_GLB_CPU_CLK_SW_STATE_POS))
+
+/* 0x4 : mm_clk_cpu */
+#define MM_GLB_MM_CLK_CPU_OFFSET (0x4)
+#define MM_GLB_REG_CPU_CLK_DIV MM_GLB_REG_CPU_CLK_DIV
+#define MM_GLB_REG_CPU_CLK_DIV_POS (0U)
+#define MM_GLB_REG_CPU_CLK_DIV_LEN (8U)
+#define MM_GLB_REG_CPU_CLK_DIV_MSK (((1U << MM_GLB_REG_CPU_CLK_DIV_LEN) - 1) << MM_GLB_REG_CPU_CLK_DIV_POS)
+#define MM_GLB_REG_CPU_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_CPU_CLK_DIV_LEN) - 1) << MM_GLB_REG_CPU_CLK_DIV_POS))
+#define MM_GLB_REG_CNN_CLK_DIV_EN MM_GLB_REG_CNN_CLK_DIV_EN
+#define MM_GLB_REG_CNN_CLK_DIV_EN_POS (8U)
+#define MM_GLB_REG_CNN_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_CNN_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_CNN_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_EN_POS)
+#define MM_GLB_REG_CNN_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_CNN_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_EN_POS))
+#define MM_GLB_REG_CNN_CLK_SEL MM_GLB_REG_CNN_CLK_SEL
+#define MM_GLB_REG_CNN_CLK_SEL_POS (9U)
+#define MM_GLB_REG_CNN_CLK_SEL_LEN (2U)
+#define MM_GLB_REG_CNN_CLK_SEL_MSK (((1U << MM_GLB_REG_CNN_CLK_SEL_LEN) - 1) << MM_GLB_REG_CNN_CLK_SEL_POS)
+#define MM_GLB_REG_CNN_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CNN_CLK_SEL_LEN) - 1) << MM_GLB_REG_CNN_CLK_SEL_POS))
+#define MM_GLB_REG_CNN_CLK_DIV MM_GLB_REG_CNN_CLK_DIV
+#define MM_GLB_REG_CNN_CLK_DIV_POS (12U)
+#define MM_GLB_REG_CNN_CLK_DIV_LEN (3U)
+#define MM_GLB_REG_CNN_CLK_DIV_MSK (((1U << MM_GLB_REG_CNN_CLK_DIV_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_POS)
+#define MM_GLB_REG_CNN_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_CNN_CLK_DIV_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_POS))
+#define MM_GLB_REG_BCLK2X_DIV MM_GLB_REG_BCLK2X_DIV
+#define MM_GLB_REG_BCLK2X_DIV_POS (16U)
+#define MM_GLB_REG_BCLK2X_DIV_LEN (8U)
+#define MM_GLB_REG_BCLK2X_DIV_MSK (((1U << MM_GLB_REG_BCLK2X_DIV_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_POS)
+#define MM_GLB_REG_BCLK2X_DIV_UMSK (~(((1U << MM_GLB_REG_BCLK2X_DIV_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_POS))
+#define MM_GLB_REG_BCLK1X_DIV MM_GLB_REG_BCLK1X_DIV
+#define MM_GLB_REG_BCLK1X_DIV_POS (24U)
+#define MM_GLB_REG_BCLK1X_DIV_LEN (8U)
+#define MM_GLB_REG_BCLK1X_DIV_MSK (((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS)
+#define MM_GLB_REG_BCLK1X_DIV_UMSK (~(((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS))
+
+/* 0x8 : dp_clk */
+#define MM_GLB_DP_CLK_OFFSET (0x8)
+#define MM_GLB_REG_CLK_DIV_EN MM_GLB_REG_CLK_DIV_EN
+#define MM_GLB_REG_CLK_DIV_EN_POS (0U)
+#define MM_GLB_REG_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CLK_DIV_EN_POS)
+#define MM_GLB_REG_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CLK_DIV_EN_POS))
+#define MM_GLB_REG_CLK_SEL MM_GLB_REG_CLK_SEL
+#define MM_GLB_REG_CLK_SEL_POS (1U)
+#define MM_GLB_REG_CLK_SEL_LEN (2U)
+#define MM_GLB_REG_CLK_SEL_MSK (((1U << MM_GLB_REG_CLK_SEL_LEN) - 1) << MM_GLB_REG_CLK_SEL_POS)
+#define MM_GLB_REG_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CLK_SEL_LEN) - 1) << MM_GLB_REG_CLK_SEL_POS))
+#define MM_GLB_REG_CLK_DIV MM_GLB_REG_CLK_DIV
+#define MM_GLB_REG_CLK_DIV_POS (8U)
+#define MM_GLB_REG_CLK_DIV_LEN (8U)
+#define MM_GLB_REG_CLK_DIV_MSK (((1U << MM_GLB_REG_CLK_DIV_LEN) - 1) << MM_GLB_REG_CLK_DIV_POS)
+#define MM_GLB_REG_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_CLK_DIV_LEN) - 1) << MM_GLB_REG_CLK_DIV_POS))
+#define MM_GLB_REG_DP_CLK_DIV_EN MM_GLB_REG_DP_CLK_DIV_EN
+#define MM_GLB_REG_DP_CLK_DIV_EN_POS (16U)
+#define MM_GLB_REG_DP_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_DP_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_DP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_EN_POS)
+#define MM_GLB_REG_DP_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_DP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_EN_POS))
+#define MM_GLB_REG_DP_CLK_SEL MM_GLB_REG_DP_CLK_SEL
+#define MM_GLB_REG_DP_CLK_SEL_POS (17U)
+#define MM_GLB_REG_DP_CLK_SEL_LEN (1U)
+#define MM_GLB_REG_DP_CLK_SEL_MSK (((1U << MM_GLB_REG_DP_CLK_SEL_LEN) - 1) << MM_GLB_REG_DP_CLK_SEL_POS)
+#define MM_GLB_REG_DP_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_DP_CLK_SEL_LEN) - 1) << MM_GLB_REG_DP_CLK_SEL_POS))
+#define MM_GLB_REG_DP_CLK_DIV MM_GLB_REG_DP_CLK_DIV
+#define MM_GLB_REG_DP_CLK_DIV_POS (20U)
+#define MM_GLB_REG_DP_CLK_DIV_LEN (4U)
+#define MM_GLB_REG_DP_CLK_DIV_MSK (((1U << MM_GLB_REG_DP_CLK_DIV_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_POS)
+#define MM_GLB_REG_DP_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_DP_CLK_DIV_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_POS))
+
+/* 0xC : codec_clk */
+#define MM_GLB_CODEC_CLK_OFFSET (0xC)
+#define MM_GLB_REG_H264_CLK_DIV_EN MM_GLB_REG_H264_CLK_DIV_EN
+#define MM_GLB_REG_H264_CLK_DIV_EN_POS (8U)
+#define MM_GLB_REG_H264_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_H264_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_H264_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_EN_POS)
+#define MM_GLB_REG_H264_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_H264_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_EN_POS))
+#define MM_GLB_REG_H264_CLK_SEL MM_GLB_REG_H264_CLK_SEL
+#define MM_GLB_REG_H264_CLK_SEL_POS (9U)
+#define MM_GLB_REG_H264_CLK_SEL_LEN (2U)
+#define MM_GLB_REG_H264_CLK_SEL_MSK (((1U << MM_GLB_REG_H264_CLK_SEL_LEN) - 1) << MM_GLB_REG_H264_CLK_SEL_POS)
+#define MM_GLB_REG_H264_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_H264_CLK_SEL_LEN) - 1) << MM_GLB_REG_H264_CLK_SEL_POS))
+#define MM_GLB_REG_H264_CLK_DIV MM_GLB_REG_H264_CLK_DIV
+#define MM_GLB_REG_H264_CLK_DIV_POS (12U)
+#define MM_GLB_REG_H264_CLK_DIV_LEN (3U)
+#define MM_GLB_REG_H264_CLK_DIV_MSK (((1U << MM_GLB_REG_H264_CLK_DIV_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_POS)
+#define MM_GLB_REG_H264_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_H264_CLK_DIV_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_POS))
+
+/* 0x10 : mm_clk_ctrl_peri */
+#define MM_GLB_MM_CLK_CTRL_PERI_OFFSET (0x10)
+#define MM_GLB_REG_I2C0_CLK_DIV MM_GLB_REG_I2C0_CLK_DIV
+#define MM_GLB_REG_I2C0_CLK_DIV_POS (0U)
+#define MM_GLB_REG_I2C0_CLK_DIV_LEN (8U)
+#define MM_GLB_REG_I2C0_CLK_DIV_MSK (((1U << MM_GLB_REG_I2C0_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_POS)
+#define MM_GLB_REG_I2C0_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_I2C0_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_POS))
+#define MM_GLB_REG_I2C0_CLK_DIV_EN MM_GLB_REG_I2C0_CLK_DIV_EN
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_POS (8U)
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_I2C0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_EN_POS)
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_I2C0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_EN_POS))
+#define MM_GLB_REG_I2C0_CLK_EN MM_GLB_REG_I2C0_CLK_EN
+#define MM_GLB_REG_I2C0_CLK_EN_POS (9U)
+#define MM_GLB_REG_I2C0_CLK_EN_LEN (1U)
+#define MM_GLB_REG_I2C0_CLK_EN_MSK (((1U << MM_GLB_REG_I2C0_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_EN_POS)
+#define MM_GLB_REG_I2C0_CLK_EN_UMSK (~(((1U << MM_GLB_REG_I2C0_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_EN_POS))
+#define MM_GLB_REG_UART0_CLK_DIV_EN MM_GLB_REG_UART0_CLK_DIV_EN
+#define MM_GLB_REG_UART0_CLK_DIV_EN_POS (16U)
+#define MM_GLB_REG_UART0_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_UART0_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_UART0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_EN_POS)
+#define MM_GLB_REG_UART0_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_UART0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_EN_POS))
+#define MM_GLB_REG_UART0_CLK_DIV MM_GLB_REG_UART0_CLK_DIV
+#define MM_GLB_REG_UART0_CLK_DIV_POS (17U)
+#define MM_GLB_REG_UART0_CLK_DIV_LEN (3U)
+#define MM_GLB_REG_UART0_CLK_DIV_MSK (((1U << MM_GLB_REG_UART0_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_POS)
+#define MM_GLB_REG_UART0_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_UART0_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_POS))
+#define MM_GLB_REG_SPI_CLK_DIV_EN MM_GLB_REG_SPI_CLK_DIV_EN
+#define MM_GLB_REG_SPI_CLK_DIV_EN_POS (23U)
+#define MM_GLB_REG_SPI_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_SPI_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_SPI_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_EN_POS)
+#define MM_GLB_REG_SPI_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_SPI_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_EN_POS))
+#define MM_GLB_REG_SPI_CLK_DIV MM_GLB_REG_SPI_CLK_DIV
+#define MM_GLB_REG_SPI_CLK_DIV_POS (24U)
+#define MM_GLB_REG_SPI_CLK_DIV_LEN (8U)
+#define MM_GLB_REG_SPI_CLK_DIV_MSK (((1U << MM_GLB_REG_SPI_CLK_DIV_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_POS)
+#define MM_GLB_REG_SPI_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_SPI_CLK_DIV_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_POS))
+
+/* 0x18 : mm_clk_ctrl_peri3 */
+#define MM_GLB_MM_CLK_CTRL_PERI3_OFFSET (0x18)
+#define MM_GLB_REG_I2C1_CLK_DIV MM_GLB_REG_I2C1_CLK_DIV
+#define MM_GLB_REG_I2C1_CLK_DIV_POS (0U)
+#define MM_GLB_REG_I2C1_CLK_DIV_LEN (8U)
+#define MM_GLB_REG_I2C1_CLK_DIV_MSK (((1U << MM_GLB_REG_I2C1_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_POS)
+#define MM_GLB_REG_I2C1_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_I2C1_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_POS))
+#define MM_GLB_REG_I2C1_CLK_DIV_EN MM_GLB_REG_I2C1_CLK_DIV_EN
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_POS (8U)
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_I2C1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_EN_POS)
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_I2C1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_EN_POS))
+#define MM_GLB_REG_I2C1_CLK_EN MM_GLB_REG_I2C1_CLK_EN
+#define MM_GLB_REG_I2C1_CLK_EN_POS (9U)
+#define MM_GLB_REG_I2C1_CLK_EN_LEN (1U)
+#define MM_GLB_REG_I2C1_CLK_EN_MSK (((1U << MM_GLB_REG_I2C1_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_EN_POS)
+#define MM_GLB_REG_I2C1_CLK_EN_UMSK (~(((1U << MM_GLB_REG_I2C1_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_EN_POS))
+#define MM_GLB_REG_UART1_CLK_DIV_EN MM_GLB_REG_UART1_CLK_DIV_EN
+#define MM_GLB_REG_UART1_CLK_DIV_EN_POS (16U)
+#define MM_GLB_REG_UART1_CLK_DIV_EN_LEN (1U)
+#define MM_GLB_REG_UART1_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_UART1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_EN_POS)
+#define MM_GLB_REG_UART1_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_UART1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_EN_POS))
+#define MM_GLB_REG_UART1_CLK_DIV MM_GLB_REG_UART1_CLK_DIV
+#define MM_GLB_REG_UART1_CLK_DIV_POS (17U)
+#define MM_GLB_REG_UART1_CLK_DIV_LEN (3U)
+#define MM_GLB_REG_UART1_CLK_DIV_MSK (((1U << MM_GLB_REG_UART1_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_POS)
+#define MM_GLB_REG_UART1_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_UART1_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_POS))
+
+/* 0x40 : mm_sw_sys_reset */
+#define MM_GLB_MM_SW_SYS_RESET_OFFSET (0x40)
+#define MM_GLB_REG_CTRL_SYS_RESET MM_GLB_REG_CTRL_SYS_RESET
+#define MM_GLB_REG_CTRL_SYS_RESET_POS (0U)
+#define MM_GLB_REG_CTRL_SYS_RESET_LEN (1U)
+#define MM_GLB_REG_CTRL_SYS_RESET_MSK (((1U << MM_GLB_REG_CTRL_SYS_RESET_LEN) - 1) << MM_GLB_REG_CTRL_SYS_RESET_POS)
+#define MM_GLB_REG_CTRL_SYS_RESET_UMSK (~(((1U << MM_GLB_REG_CTRL_SYS_RESET_LEN) - 1) << MM_GLB_REG_CTRL_SYS_RESET_POS))
+#define MM_GLB_REG_CTRL_PWRON_RST MM_GLB_REG_CTRL_PWRON_RST
+#define MM_GLB_REG_CTRL_PWRON_RST_POS (2U)
+#define MM_GLB_REG_CTRL_PWRON_RST_LEN (1U)
+#define MM_GLB_REG_CTRL_PWRON_RST_MSK (((1U << MM_GLB_REG_CTRL_PWRON_RST_LEN) - 1) << MM_GLB_REG_CTRL_PWRON_RST_POS)
+#define MM_GLB_REG_CTRL_PWRON_RST_UMSK (~(((1U << MM_GLB_REG_CTRL_PWRON_RST_LEN) - 1) << MM_GLB_REG_CTRL_PWRON_RST_POS))
+#define MM_GLB_REG_CTRL_MMCPU0_RESET MM_GLB_REG_CTRL_MMCPU0_RESET
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_POS (8U)
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_LEN (1U)
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_MSK (((1U << MM_GLB_REG_CTRL_MMCPU0_RESET_LEN) - 1) << MM_GLB_REG_CTRL_MMCPU0_RESET_POS)
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_UMSK (~(((1U << MM_GLB_REG_CTRL_MMCPU0_RESET_LEN) - 1) << MM_GLB_REG_CTRL_MMCPU0_RESET_POS))
+
+/* 0x44 : sw_reset_mm_peri */
+#define MM_GLB_SW_RESET_MM_PERI_OFFSET (0x44)
+#define MM_GLB_SWRST_MM_MISC MM_GLB_SWRST_MM_MISC
+#define MM_GLB_SWRST_MM_MISC_POS (0U)
+#define MM_GLB_SWRST_MM_MISC_LEN (1U)
+#define MM_GLB_SWRST_MM_MISC_MSK (((1U << MM_GLB_SWRST_MM_MISC_LEN) - 1) << MM_GLB_SWRST_MM_MISC_POS)
+#define MM_GLB_SWRST_MM_MISC_UMSK (~(((1U << MM_GLB_SWRST_MM_MISC_LEN) - 1) << MM_GLB_SWRST_MM_MISC_POS))
+#define MM_GLB_SWRST_DMA MM_GLB_SWRST_DMA
+#define MM_GLB_SWRST_DMA_POS (1U)
+#define MM_GLB_SWRST_DMA_LEN (1U)
+#define MM_GLB_SWRST_DMA_MSK (((1U << MM_GLB_SWRST_DMA_LEN) - 1) << MM_GLB_SWRST_DMA_POS)
+#define MM_GLB_SWRST_DMA_UMSK (~(((1U << MM_GLB_SWRST_DMA_LEN) - 1) << MM_GLB_SWRST_DMA_POS))
+#define MM_GLB_SWRST_UART0 MM_GLB_SWRST_UART0
+#define MM_GLB_SWRST_UART0_POS (2U)
+#define MM_GLB_SWRST_UART0_LEN (1U)
+#define MM_GLB_SWRST_UART0_MSK (((1U << MM_GLB_SWRST_UART0_LEN) - 1) << MM_GLB_SWRST_UART0_POS)
+#define MM_GLB_SWRST_UART0_UMSK (~(((1U << MM_GLB_SWRST_UART0_LEN) - 1) << MM_GLB_SWRST_UART0_POS))
+#define MM_GLB_SWRST_I2C0 MM_GLB_SWRST_I2C0
+#define MM_GLB_SWRST_I2C0_POS (3U)
+#define MM_GLB_SWRST_I2C0_LEN (1U)
+#define MM_GLB_SWRST_I2C0_MSK (((1U << MM_GLB_SWRST_I2C0_LEN) - 1) << MM_GLB_SWRST_I2C0_POS)
+#define MM_GLB_SWRST_I2C0_UMSK (~(((1U << MM_GLB_SWRST_I2C0_LEN) - 1) << MM_GLB_SWRST_I2C0_POS))
+#define MM_GLB_SWRST_I2C1 MM_GLB_SWRST_I2C1
+#define MM_GLB_SWRST_I2C1_POS (4U)
+#define MM_GLB_SWRST_I2C1_LEN (1U)
+#define MM_GLB_SWRST_I2C1_MSK (((1U << MM_GLB_SWRST_I2C1_LEN) - 1) << MM_GLB_SWRST_I2C1_POS)
+#define MM_GLB_SWRST_I2C1_UMSK (~(((1U << MM_GLB_SWRST_I2C1_LEN) - 1) << MM_GLB_SWRST_I2C1_POS))
+#define MM_GLB_SWRST_IPC MM_GLB_SWRST_IPC
+#define MM_GLB_SWRST_IPC_POS (5U)
+#define MM_GLB_SWRST_IPC_LEN (1U)
+#define MM_GLB_SWRST_IPC_MSK (((1U << MM_GLB_SWRST_IPC_LEN) - 1) << MM_GLB_SWRST_IPC_POS)
+#define MM_GLB_SWRST_IPC_UMSK (~(((1U << MM_GLB_SWRST_IPC_LEN) - 1) << MM_GLB_SWRST_IPC_POS))
+#define MM_GLB_SWRST_DMA2D MM_GLB_SWRST_DMA2D
+#define MM_GLB_SWRST_DMA2D_POS (6U)
+#define MM_GLB_SWRST_DMA2D_LEN (1U)
+#define MM_GLB_SWRST_DMA2D_MSK (((1U << MM_GLB_SWRST_DMA2D_LEN) - 1) << MM_GLB_SWRST_DMA2D_POS)
+#define MM_GLB_SWRST_DMA2D_UMSK (~(((1U << MM_GLB_SWRST_DMA2D_LEN) - 1) << MM_GLB_SWRST_DMA2D_POS))
+#define MM_GLB_SWRST_SPI MM_GLB_SWRST_SPI
+#define MM_GLB_SWRST_SPI_POS (8U)
+#define MM_GLB_SWRST_SPI_LEN (1U)
+#define MM_GLB_SWRST_SPI_MSK (((1U << MM_GLB_SWRST_SPI_LEN) - 1) << MM_GLB_SWRST_SPI_POS)
+#define MM_GLB_SWRST_SPI_UMSK (~(((1U << MM_GLB_SWRST_SPI_LEN) - 1) << MM_GLB_SWRST_SPI_POS))
+#define MM_GLB_SWRST_TIMER MM_GLB_SWRST_TIMER
+#define MM_GLB_SWRST_TIMER_POS (9U)
+#define MM_GLB_SWRST_TIMER_LEN (1U)
+#define MM_GLB_SWRST_TIMER_MSK (((1U << MM_GLB_SWRST_TIMER_LEN) - 1) << MM_GLB_SWRST_TIMER_POS)
+#define MM_GLB_SWRST_TIMER_UMSK (~(((1U << MM_GLB_SWRST_TIMER_LEN) - 1) << MM_GLB_SWRST_TIMER_POS))
+#define MM_GLB_SWRST_I2S0 MM_GLB_SWRST_I2S0
+#define MM_GLB_SWRST_I2S0_POS (10U)
+#define MM_GLB_SWRST_I2S0_LEN (1U)
+#define MM_GLB_SWRST_I2S0_MSK (((1U << MM_GLB_SWRST_I2S0_LEN) - 1) << MM_GLB_SWRST_I2S0_POS)
+#define MM_GLB_SWRST_I2S0_UMSK (~(((1U << MM_GLB_SWRST_I2S0_LEN) - 1) << MM_GLB_SWRST_I2S0_POS))
+#define MM_GLB_SWRST_I2S1 MM_GLB_SWRST_I2S1
+#define MM_GLB_SWRST_I2S1_POS (11U)
+#define MM_GLB_SWRST_I2S1_LEN (1U)
+#define MM_GLB_SWRST_I2S1_MSK (((1U << MM_GLB_SWRST_I2S1_LEN) - 1) << MM_GLB_SWRST_I2S1_POS)
+#define MM_GLB_SWRST_I2S1_UMSK (~(((1U << MM_GLB_SWRST_I2S1_LEN) - 1) << MM_GLB_SWRST_I2S1_POS))
+#define MM_GLB_SWRST_PDM0 MM_GLB_SWRST_PDM0
+#define MM_GLB_SWRST_PDM0_POS (12U)
+#define MM_GLB_SWRST_PDM0_LEN (1U)
+#define MM_GLB_SWRST_PDM0_MSK (((1U << MM_GLB_SWRST_PDM0_LEN) - 1) << MM_GLB_SWRST_PDM0_POS)
+#define MM_GLB_SWRST_PDM0_UMSK (~(((1U << MM_GLB_SWRST_PDM0_LEN) - 1) << MM_GLB_SWRST_PDM0_POS))
+#define MM_GLB_SWRST_PDM1 MM_GLB_SWRST_PDM1
+#define MM_GLB_SWRST_PDM1_POS (13U)
+#define MM_GLB_SWRST_PDM1_LEN (1U)
+#define MM_GLB_SWRST_PDM1_MSK (((1U << MM_GLB_SWRST_PDM1_LEN) - 1) << MM_GLB_SWRST_PDM1_POS)
+#define MM_GLB_SWRST_PDM1_UMSK (~(((1U << MM_GLB_SWRST_PDM1_LEN) - 1) << MM_GLB_SWRST_PDM1_POS))
+#define MM_GLB_SWRST_UART1 MM_GLB_SWRST_UART1
+#define MM_GLB_SWRST_UART1_POS (14U)
+#define MM_GLB_SWRST_UART1_LEN (1U)
+#define MM_GLB_SWRST_UART1_MSK (((1U << MM_GLB_SWRST_UART1_LEN) - 1) << MM_GLB_SWRST_UART1_POS)
+#define MM_GLB_SWRST_UART1_UMSK (~(((1U << MM_GLB_SWRST_UART1_LEN) - 1) << MM_GLB_SWRST_UART1_POS))
+#define MM_GLB_SWRST_PUHS MM_GLB_SWRST_PUHS
+#define MM_GLB_SWRST_PUHS_POS (15U)
+#define MM_GLB_SWRST_PUHS_LEN (1U)
+#define MM_GLB_SWRST_PUHS_MSK (((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS)
+#define MM_GLB_SWRST_PUHS_UMSK (~(((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS))
+
+/* 0x48 : sw_reset_sub */
+#define MM_GLB_SW_RESET_SUB_OFFSET (0x48)
+#define MM_GLB_SWRST_MISC MM_GLB_SWRST_MISC
+#define MM_GLB_SWRST_MISC_POS (0U)
+#define MM_GLB_SWRST_MISC_LEN (1U)
+#define MM_GLB_SWRST_MISC_MSK (((1U << MM_GLB_SWRST_MISC_LEN) - 1) << MM_GLB_SWRST_MISC_POS)
+#define MM_GLB_SWRST_MISC_UMSK (~(((1U << MM_GLB_SWRST_MISC_LEN) - 1) << MM_GLB_SWRST_MISC_POS))
+#define MM_GLB_SWRST_MAIN MM_GLB_SWRST_MAIN
+#define MM_GLB_SWRST_MAIN_POS (1U)
+#define MM_GLB_SWRST_MAIN_LEN (1U)
+#define MM_GLB_SWRST_MAIN_MSK (((1U << MM_GLB_SWRST_MAIN_LEN) - 1) << MM_GLB_SWRST_MAIN_POS)
+#define MM_GLB_SWRST_MAIN_UMSK (~(((1U << MM_GLB_SWRST_MAIN_LEN) - 1) << MM_GLB_SWRST_MAIN_POS))
+#define MM_GLB_SWRST_TSRC MM_GLB_SWRST_TSRC
+#define MM_GLB_SWRST_TSRC_POS (2U)
+#define MM_GLB_SWRST_TSRC_LEN (1U)
+#define MM_GLB_SWRST_TSRC_MSK (((1U << MM_GLB_SWRST_TSRC_LEN) - 1) << MM_GLB_SWRST_TSRC_POS)
+#define MM_GLB_SWRST_TSRC_UMSK (~(((1U << MM_GLB_SWRST_TSRC_LEN) - 1) << MM_GLB_SWRST_TSRC_POS))
+#define MM_GLB_SWRST_DP_TSRC MM_GLB_SWRST_DP_TSRC
+#define MM_GLB_SWRST_DP_TSRC_POS (3U)
+#define MM_GLB_SWRST_DP_TSRC_LEN (1U)
+#define MM_GLB_SWRST_DP_TSRC_MSK (((1U << MM_GLB_SWRST_DP_TSRC_LEN) - 1) << MM_GLB_SWRST_DP_TSRC_POS)
+#define MM_GLB_SWRST_DP_TSRC_UMSK (~(((1U << MM_GLB_SWRST_DP_TSRC_LEN) - 1) << MM_GLB_SWRST_DP_TSRC_POS))
+#define MM_GLB_SWRST_NR3D_CTRL MM_GLB_SWRST_NR3D_CTRL
+#define MM_GLB_SWRST_NR3D_CTRL_POS (4U)
+#define MM_GLB_SWRST_NR3D_CTRL_LEN (1U)
+#define MM_GLB_SWRST_NR3D_CTRL_MSK (((1U << MM_GLB_SWRST_NR3D_CTRL_LEN) - 1) << MM_GLB_SWRST_NR3D_CTRL_POS)
+#define MM_GLB_SWRST_NR3D_CTRL_UMSK (~(((1U << MM_GLB_SWRST_NR3D_CTRL_LEN) - 1) << MM_GLB_SWRST_NR3D_CTRL_POS))
+#define MM_GLB_SWRST_DVP2BUSA MM_GLB_SWRST_DVP2BUSA
+#define MM_GLB_SWRST_DVP2BUSA_POS (5U)
+#define MM_GLB_SWRST_DVP2BUSA_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSA_MSK (((1U << MM_GLB_SWRST_DVP2BUSA_LEN) - 1) << MM_GLB_SWRST_DVP2BUSA_POS)
+#define MM_GLB_SWRST_DVP2BUSA_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSA_LEN) - 1) << MM_GLB_SWRST_DVP2BUSA_POS))
+#define MM_GLB_SWRST_DVP2BUSB MM_GLB_SWRST_DVP2BUSB
+#define MM_GLB_SWRST_DVP2BUSB_POS (6U)
+#define MM_GLB_SWRST_DVP2BUSB_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSB_MSK (((1U << MM_GLB_SWRST_DVP2BUSB_LEN) - 1) << MM_GLB_SWRST_DVP2BUSB_POS)
+#define MM_GLB_SWRST_DVP2BUSB_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSB_LEN) - 1) << MM_GLB_SWRST_DVP2BUSB_POS))
+#define MM_GLB_SWRST_DVP2BUSC MM_GLB_SWRST_DVP2BUSC
+#define MM_GLB_SWRST_DVP2BUSC_POS (7U)
+#define MM_GLB_SWRST_DVP2BUSC_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSC_MSK (((1U << MM_GLB_SWRST_DVP2BUSC_LEN) - 1) << MM_GLB_SWRST_DVP2BUSC_POS)
+#define MM_GLB_SWRST_DVP2BUSC_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSC_LEN) - 1) << MM_GLB_SWRST_DVP2BUSC_POS))
+#define MM_GLB_SWRST_DVP2BUSD MM_GLB_SWRST_DVP2BUSD
+#define MM_GLB_SWRST_DVP2BUSD_POS (8U)
+#define MM_GLB_SWRST_DVP2BUSD_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSD_MSK (((1U << MM_GLB_SWRST_DVP2BUSD_LEN) - 1) << MM_GLB_SWRST_DVP2BUSD_POS)
+#define MM_GLB_SWRST_DVP2BUSD_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSD_LEN) - 1) << MM_GLB_SWRST_DVP2BUSD_POS))
+#define MM_GLB_SWRST_MIPI MM_GLB_SWRST_MIPI
+#define MM_GLB_SWRST_MIPI_POS (9U)
+#define MM_GLB_SWRST_MIPI_LEN (1U)
+#define MM_GLB_SWRST_MIPI_MSK (((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS)
+#define MM_GLB_SWRST_MIPI_UMSK (~(((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS))
+#define MM_GLB_SWRST_DVP2BUSE MM_GLB_SWRST_DVP2BUSE
+#define MM_GLB_SWRST_DVP2BUSE_POS (17U)
+#define MM_GLB_SWRST_DVP2BUSE_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSE_MSK (((1U << MM_GLB_SWRST_DVP2BUSE_LEN) - 1) << MM_GLB_SWRST_DVP2BUSE_POS)
+#define MM_GLB_SWRST_DVP2BUSE_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSE_LEN) - 1) << MM_GLB_SWRST_DVP2BUSE_POS))
+#define MM_GLB_SWRST_DVP2BUSF MM_GLB_SWRST_DVP2BUSF
+#define MM_GLB_SWRST_DVP2BUSF_POS (18U)
+#define MM_GLB_SWRST_DVP2BUSF_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSF_MSK (((1U << MM_GLB_SWRST_DVP2BUSF_LEN) - 1) << MM_GLB_SWRST_DVP2BUSF_POS)
+#define MM_GLB_SWRST_DVP2BUSF_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSF_LEN) - 1) << MM_GLB_SWRST_DVP2BUSF_POS))
+#define MM_GLB_SWRST_DVP2BUSG MM_GLB_SWRST_DVP2BUSG
+#define MM_GLB_SWRST_DVP2BUSG_POS (19U)
+#define MM_GLB_SWRST_DVP2BUSG_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSG_MSK (((1U << MM_GLB_SWRST_DVP2BUSG_LEN) - 1) << MM_GLB_SWRST_DVP2BUSG_POS)
+#define MM_GLB_SWRST_DVP2BUSG_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSG_LEN) - 1) << MM_GLB_SWRST_DVP2BUSG_POS))
+#define MM_GLB_SWRST_DVP2BUSH MM_GLB_SWRST_DVP2BUSH
+#define MM_GLB_SWRST_DVP2BUSH_POS (20U)
+#define MM_GLB_SWRST_DVP2BUSH_LEN (1U)
+#define MM_GLB_SWRST_DVP2BUSH_MSK (((1U << MM_GLB_SWRST_DVP2BUSH_LEN) - 1) << MM_GLB_SWRST_DVP2BUSH_POS)
+#define MM_GLB_SWRST_DVP2BUSH_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSH_LEN) - 1) << MM_GLB_SWRST_DVP2BUSH_POS))
+
+/* 0x4C : sw_reset_codec_sub */
+#define MM_GLB_SW_RESET_CODEC_SUB_OFFSET (0x4C)
+#define MM_GLB_SWRST_CODEC_MISC MM_GLB_SWRST_CODEC_MISC
+#define MM_GLB_SWRST_CODEC_MISC_POS (0U)
+#define MM_GLB_SWRST_CODEC_MISC_LEN (1U)
+#define MM_GLB_SWRST_CODEC_MISC_MSK (((1U << MM_GLB_SWRST_CODEC_MISC_LEN) - 1) << MM_GLB_SWRST_CODEC_MISC_POS)
+#define MM_GLB_SWRST_CODEC_MISC_UMSK (~(((1U << MM_GLB_SWRST_CODEC_MISC_LEN) - 1) << MM_GLB_SWRST_CODEC_MISC_POS))
+#define MM_GLB_SWRST_MJPEG MM_GLB_SWRST_MJPEG
+#define MM_GLB_SWRST_MJPEG_POS (1U)
+#define MM_GLB_SWRST_MJPEG_LEN (1U)
+#define MM_GLB_SWRST_MJPEG_MSK (((1U << MM_GLB_SWRST_MJPEG_LEN) - 1) << MM_GLB_SWRST_MJPEG_POS)
+#define MM_GLB_SWRST_MJPEG_UMSK (~(((1U << MM_GLB_SWRST_MJPEG_LEN) - 1) << MM_GLB_SWRST_MJPEG_POS))
+#define MM_GLB_SWRST_H264 MM_GLB_SWRST_H264
+#define MM_GLB_SWRST_H264_POS (2U)
+#define MM_GLB_SWRST_H264_LEN (1U)
+#define MM_GLB_SWRST_H264_MSK (((1U << MM_GLB_SWRST_H264_LEN) - 1) << MM_GLB_SWRST_H264_POS)
+#define MM_GLB_SWRST_H264_UMSK (~(((1U << MM_GLB_SWRST_H264_LEN) - 1) << MM_GLB_SWRST_H264_POS))
+#define MM_GLB_SWRST_MJPEG_DEC MM_GLB_SWRST_MJPEG_DEC
+#define MM_GLB_SWRST_MJPEG_DEC_POS (3U)
+#define MM_GLB_SWRST_MJPEG_DEC_LEN (1U)
+#define MM_GLB_SWRST_MJPEG_DEC_MSK (((1U << MM_GLB_SWRST_MJPEG_DEC_LEN) - 1) << MM_GLB_SWRST_MJPEG_DEC_POS)
+#define MM_GLB_SWRST_MJPEG_DEC_UMSK (~(((1U << MM_GLB_SWRST_MJPEG_DEC_LEN) - 1) << MM_GLB_SWRST_MJPEG_DEC_POS))
+#define MM_GLB_SWRST_CNN MM_GLB_SWRST_CNN
+#define MM_GLB_SWRST_CNN_POS (4U)
+#define MM_GLB_SWRST_CNN_LEN (1U)
+#define MM_GLB_SWRST_CNN_MSK (((1U << MM_GLB_SWRST_CNN_LEN) - 1) << MM_GLB_SWRST_CNN_POS)
+#define MM_GLB_SWRST_CNN_UMSK (~(((1U << MM_GLB_SWRST_CNN_LEN) - 1) << MM_GLB_SWRST_CNN_POS))
+#define MM_GLB_SWRST_VRAM MM_GLB_SWRST_VRAM
+#define MM_GLB_SWRST_VRAM_POS (16U)
+#define MM_GLB_SWRST_VRAM_LEN (1U)
+#define MM_GLB_SWRST_VRAM_MSK (((1U << MM_GLB_SWRST_VRAM_LEN) - 1) << MM_GLB_SWRST_VRAM_POS)
+#define MM_GLB_SWRST_VRAM_UMSK (~(((1U << MM_GLB_SWRST_VRAM_LEN) - 1) << MM_GLB_SWRST_VRAM_POS))
+
+/* 0x50 : image_sensor_ctrl */
+#define MM_GLB_IMAGE_SENSOR_CTRL_OFFSET (0x50)
+#define MM_GLB_RG_IS_RST_N MM_GLB_RG_IS_RST_N
+#define MM_GLB_RG_IS_RST_N_POS (0U)
+#define MM_GLB_RG_IS_RST_N_LEN (1U)
+#define MM_GLB_RG_IS_RST_N_MSK (((1U << MM_GLB_RG_IS_RST_N_LEN) - 1) << MM_GLB_RG_IS_RST_N_POS)
+#define MM_GLB_RG_IS_RST_N_UMSK (~(((1U << MM_GLB_RG_IS_RST_N_LEN) - 1) << MM_GLB_RG_IS_RST_N_POS))
+
+/* 0x60 : tz_mm_clkrst */
+#define MM_GLB_TZ_MM_CLKRST_OFFSET (0x60)
+#define MM_GLB_TZC_MM_SWRST_LOCK MM_GLB_TZC_MM_SWRST_LOCK
+#define MM_GLB_TZC_MM_SWRST_LOCK_POS (0U)
+#define MM_GLB_TZC_MM_SWRST_LOCK_LEN (1U)
+#define MM_GLB_TZC_MM_SWRST_LOCK_MSK (((1U << MM_GLB_TZC_MM_SWRST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SWRST_LOCK_POS)
+#define MM_GLB_TZC_MM_SWRST_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_SWRST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SWRST_LOCK_POS))
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK MM_GLB_TZC_MM_SYS_RESET_LOCK
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_POS (1U)
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN (1U)
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_MSK (((1U << MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SYS_RESET_LOCK_POS)
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SYS_RESET_LOCK_POS))
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK MM_GLB_TZC_MM_PWRON_RST_LOCK
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_POS (2U)
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN (1U)
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_MSK (((1U << MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_PWRON_RST_LOCK_POS)
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_PWRON_RST_LOCK_POS))
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK MM_GLB_TZC_MM_CPU0_RESET_LOCK
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS (3U)
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN (1U)
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_MSK (((1U << MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS)
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS))
+#define MM_GLB_TZC_MM_CLK_LOCK MM_GLB_TZC_MM_CLK_LOCK
+#define MM_GLB_TZC_MM_CLK_LOCK_POS (4U)
+#define MM_GLB_TZC_MM_CLK_LOCK_LEN (1U)
+#define MM_GLB_TZC_MM_CLK_LOCK_MSK (((1U << MM_GLB_TZC_MM_CLK_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CLK_LOCK_POS)
+#define MM_GLB_TZC_MM_CLK_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_CLK_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CLK_LOCK_POS))
+
+struct mm_glb_reg {
+ /* 0x0 : mm_clk_ctrl_cpu */
+ union {
+ struct {
+ uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_cpu_clk_en : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_bclk_en : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reg_mm_cpu_clk_en : 1; /* [ 3], r/w, 0x1 */
+ uint32_t reg_uart_clk_sel : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t reg_i2c_clk_sel : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_spi_clk_sel : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_cpu_clk_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reg_xclk_clk_sel : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg_cpu_root_clk_sel : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reg_mmcpu0_clk_en : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_bclk1x_sel : 2; /* [14:13], r/w, 0x0 */
+ uint32_t reserved_15_17 : 3; /* [17:15], rsvd, 0x0 */
+ uint32_t reg_bclk2x_div_act_pulse : 1; /* [ 18], w1p, 0x0 */
+ uint32_t reg_bclk2x_div_bypass : 1; /* [ 19], r/w, 0x0 */
+ uint32_t sts_bclk2x_prot_done : 1; /* [ 20], r, 0x1 */
+ uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
+ uint32_t reg_bclk2x_sw_done_cnt : 4; /* [27:24], r/w, 0x5 */
+ uint32_t cpu_clk_sw_state : 3; /* [30:28], r, 0x0 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_clk_ctrl_cpu;
+
+ /* 0x4 : mm_clk_cpu */
+ union {
+ struct {
+ uint32_t reg_cpu_clk_div : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_cnn_clk_div_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reg_cnn_clk_sel : 2; /* [10: 9], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t reg_cnn_clk_div : 3; /* [14:12], r/w, 0x0 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t reg_bclk2x_div : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_bclk1x_div : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_clk_cpu;
+
+ /* 0x8 : dp_clk */
+ union {
+ struct {
+ uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */
+ uint32_t reg_dp_clk_div_en : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_dp_clk_sel : 1; /* [ 17], r/w, 0x0 */
+ uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
+ uint32_t reg_dp_clk_div : 4; /* [23:20], r/w, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dp_clk;
+
+ /* 0xC : codec_clk */
+ union {
+ struct {
+ uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */
+ uint32_t reg_h264_clk_div_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reg_h264_clk_sel : 2; /* [10: 9], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t reg_h264_clk_div : 3; /* [14:12], r/w, 0x0 */
+ uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } codec_clk;
+
+ /* 0x10 : mm_clk_ctrl_peri */
+ union {
+ struct {
+ uint32_t reg_i2c0_clk_div : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_i2c0_clk_div_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reg_i2c0_clk_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t reg_uart0_clk_div_en : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_uart0_clk_div : 3; /* [19:17], r/w, 0x0 */
+ uint32_t reserved_20_22 : 3; /* [22:20], rsvd, 0x0 */
+ uint32_t reg_spi_clk_div_en : 1; /* [ 23], r/w, 0x1 */
+ uint32_t reg_spi_clk_div : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_clk_ctrl_peri;
+
+ /* 0x14 reserved */
+ uint8_t RESERVED0x14[4];
+
+ /* 0x18 : mm_clk_ctrl_peri3 */
+ union {
+ struct {
+ uint32_t reg_i2c1_clk_div : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_i2c1_clk_div_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reg_i2c1_clk_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t reg_uart1_clk_div_en : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_uart1_clk_div : 3; /* [19:17], r/w, 0x0 */
+ uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_clk_ctrl_peri3;
+
+ /* 0x1c reserved */
+ uint8_t RESERVED0x1c[36];
+
+ /* 0x40 : mm_sw_sys_reset */
+ union {
+ struct {
+ uint32_t reg_ctrl_sys_reset : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t reg_ctrl_pwron_rst : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
+ uint32_t reg_ctrl_mmcpu0_reset : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_sw_sys_reset;
+
+ /* 0x44 : sw_reset_mm_peri */
+ union {
+ struct {
+ uint32_t swrst_mm_misc : 1; /* [ 0], r/w, 0x0 */
+ uint32_t swrst_dma : 1; /* [ 1], r/w, 0x0 */
+ uint32_t swrst_uart0 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t swrst_i2c0 : 1; /* [ 3], r/w, 0x0 */
+ uint32_t swrst_i2c1 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t swrst_ipc : 1; /* [ 5], r/w, 0x0 */
+ uint32_t swrst_dma2d : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t swrst_spi : 1; /* [ 8], r/w, 0x0 */
+ uint32_t swrst_timer : 1; /* [ 9], r/w, 0x0 */
+ uint32_t swrst_i2s0 : 1; /* [ 10], r/w, 0x0 */
+ uint32_t swrst_i2s1 : 1; /* [ 11], r/w, 0x0 */
+ uint32_t swrst_pdm0 : 1; /* [ 12], r/w, 0x0 */
+ uint32_t swrst_pdm1 : 1; /* [ 13], r/w, 0x0 */
+ uint32_t swrst_uart1 : 1; /* [ 14], r/w, 0x0 */
+ uint32_t swrst_pUHS : 1; /* [ 15], r/w, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sw_reset_mm_peri;
+
+ /* 0x48 : sw_reset_sub */
+ union {
+ struct {
+ uint32_t swrst_misc : 1; /* [ 0], r/w, 0x0 */
+ uint32_t swrst_main : 1; /* [ 1], r/w, 0x0 */
+ uint32_t swrst_tsrc : 1; /* [ 2], r/w, 0x0 */
+ uint32_t swrst_dp_tsrc : 1; /* [ 3], r/w, 0x0 */
+ uint32_t swrst_nr3d_ctrl : 1; /* [ 4], r/w, 0x0 */
+ uint32_t swrst_dvp2busA : 1; /* [ 5], r/w, 0x0 */
+ uint32_t swrst_dvp2busB : 1; /* [ 6], r/w, 0x0 */
+ uint32_t swrst_dvp2busC : 1; /* [ 7], r/w, 0x0 */
+ uint32_t swrst_dvp2busD : 1; /* [ 8], r/w, 0x0 */
+ uint32_t swrst_mipi : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t swrst_reg : 1; /* [ 16], r/w, 0x0 */
+ uint32_t swrst_dvp2busE : 1; /* [ 17], r/w, 0x0 */
+ uint32_t swrst_dvp2busF : 1; /* [ 18], r/w, 0x0 */
+ uint32_t swrst_dvp2busG : 1; /* [ 19], r/w, 0x0 */
+ uint32_t swrst_dvp2busH : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sw_reset_sub;
+
+ /* 0x4C : sw_reset_codec_sub */
+ union {
+ struct {
+ uint32_t swrst_codec_misc : 1; /* [ 0], r/w, 0x0 */
+ uint32_t swrst_mjpeg : 1; /* [ 1], r/w, 0x0 */
+ uint32_t swrst_h264 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t swrst_mjpeg_dec : 1; /* [ 3], r/w, 0x0 */
+ uint32_t swrst_cnn : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
+ uint32_t swrst_vram : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sw_reset_codec_sub;
+
+ /* 0x50 : image_sensor_ctrl */
+ union {
+ struct {
+ uint32_t rg_is_rst_n : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } image_sensor_ctrl;
+
+ /* 0x54 reserved */
+ uint8_t RESERVED0x54[12];
+
+ /* 0x60 : tz_mm_clkrst */
+ union {
+ struct {
+ uint32_t tzc_mm_swrst_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_mm_sys_reset_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_mm_pwron_rst_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_mm_cpu0_reset_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_mm_clk_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tz_mm_clkrst;
+};
+
+typedef volatile struct mm_glb_reg mm_glb_reg_t;
+
+#endif /* __MM_GLB_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mm_misc_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mm_misc_reg.h
new file mode 100644
index 00000000..fc07a350
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/mm_misc_reg.h
@@ -0,0 +1,973 @@
+/**
+ ******************************************************************************
+ * @file mm_misc_reg.h
+ * @version V1.0
+ * @date 2021-07-12
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __MM_MISC_REG_H__
+#define __MM_MISC_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : CPU0_Boot */
+#define MM_MISC_CPU0_BOOT_OFFSET (0x0)
+#define MM_MISC_REG_CPU0_RVBA MM_MISC_REG_CPU0_RVBA
+#define MM_MISC_REG_CPU0_RVBA_POS (0U)
+#define MM_MISC_REG_CPU0_RVBA_LEN (32U)
+#define MM_MISC_REG_CPU0_RVBA_MSK (((1U << MM_MISC_REG_CPU0_RVBA_LEN) - 1) << MM_MISC_REG_CPU0_RVBA_POS)
+#define MM_MISC_REG_CPU0_RVBA_UMSK (~(((1U << MM_MISC_REG_CPU0_RVBA_LEN) - 1) << MM_MISC_REG_CPU0_RVBA_POS))
+
+/* 0x8 : CPU_cfg */
+#define MM_MISC_CPU_CFG_OFFSET (0x8)
+#define MM_MISC_REG_CPU0_APB_BASE MM_MISC_REG_CPU0_APB_BASE
+#define MM_MISC_REG_CPU0_APB_BASE_POS (0U)
+#define MM_MISC_REG_CPU0_APB_BASE_LEN (13U)
+#define MM_MISC_REG_CPU0_APB_BASE_MSK (((1U << MM_MISC_REG_CPU0_APB_BASE_LEN) - 1) << MM_MISC_REG_CPU0_APB_BASE_POS)
+#define MM_MISC_REG_CPU0_APB_BASE_UMSK (~(((1U << MM_MISC_REG_CPU0_APB_BASE_LEN) - 1) << MM_MISC_REG_CPU0_APB_BASE_POS))
+#define MM_MISC_CPU0_NDM_RSTN_EN MM_MISC_CPU0_NDM_RSTN_EN
+#define MM_MISC_CPU0_NDM_RSTN_EN_POS (28U)
+#define MM_MISC_CPU0_NDM_RSTN_EN_LEN (1U)
+#define MM_MISC_CPU0_NDM_RSTN_EN_MSK (((1U << MM_MISC_CPU0_NDM_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_EN_POS)
+#define MM_MISC_CPU0_NDM_RSTN_EN_UMSK (~(((1U << MM_MISC_CPU0_NDM_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_EN_POS))
+#define MM_MISC_CPU0_HART_RSTN_EN MM_MISC_CPU0_HART_RSTN_EN
+#define MM_MISC_CPU0_HART_RSTN_EN_POS (29U)
+#define MM_MISC_CPU0_HART_RSTN_EN_LEN (1U)
+#define MM_MISC_CPU0_HART_RSTN_EN_MSK (((1U << MM_MISC_CPU0_HART_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_EN_POS)
+#define MM_MISC_CPU0_HART_RSTN_EN_UMSK (~(((1U << MM_MISC_CPU0_HART_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_EN_POS))
+
+/* 0xC : CPU_sts1 */
+#define MM_MISC_CPU_STS1_OFFSET (0xC)
+#define MM_MISC_CPU0_LPMD_B MM_MISC_CPU0_LPMD_B
+#define MM_MISC_CPU0_LPMD_B_POS (4U)
+#define MM_MISC_CPU0_LPMD_B_LEN (2U)
+#define MM_MISC_CPU0_LPMD_B_MSK (((1U << MM_MISC_CPU0_LPMD_B_LEN) - 1) << MM_MISC_CPU0_LPMD_B_POS)
+#define MM_MISC_CPU0_LPMD_B_UMSK (~(((1U << MM_MISC_CPU0_LPMD_B_LEN) - 1) << MM_MISC_CPU0_LPMD_B_POS))
+#define MM_MISC_CPU0_RETIRE_PC_39_32 MM_MISC_CPU0_RETIRE_PC_39_32
+#define MM_MISC_CPU0_RETIRE_PC_39_32_POS (16U)
+#define MM_MISC_CPU0_RETIRE_PC_39_32_LEN (8U)
+#define MM_MISC_CPU0_RETIRE_PC_39_32_MSK (((1U << MM_MISC_CPU0_RETIRE_PC_39_32_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_39_32_POS)
+#define MM_MISC_CPU0_RETIRE_PC_39_32_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_PC_39_32_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_39_32_POS))
+#define MM_MISC_CPU0_RETIRE MM_MISC_CPU0_RETIRE
+#define MM_MISC_CPU0_RETIRE_POS (24U)
+#define MM_MISC_CPU0_RETIRE_LEN (1U)
+#define MM_MISC_CPU0_RETIRE_MSK (((1U << MM_MISC_CPU0_RETIRE_LEN) - 1) << MM_MISC_CPU0_RETIRE_POS)
+#define MM_MISC_CPU0_RETIRE_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_LEN) - 1) << MM_MISC_CPU0_RETIRE_POS))
+#define MM_MISC_CPU0_PAD_HALTED MM_MISC_CPU0_PAD_HALTED
+#define MM_MISC_CPU0_PAD_HALTED_POS (25U)
+#define MM_MISC_CPU0_PAD_HALTED_LEN (1U)
+#define MM_MISC_CPU0_PAD_HALTED_MSK (((1U << MM_MISC_CPU0_PAD_HALTED_LEN) - 1) << MM_MISC_CPU0_PAD_HALTED_POS)
+#define MM_MISC_CPU0_PAD_HALTED_UMSK (~(((1U << MM_MISC_CPU0_PAD_HALTED_LEN) - 1) << MM_MISC_CPU0_PAD_HALTED_POS))
+#define MM_MISC_CPU0_NDM_RSTN_REQ MM_MISC_CPU0_NDM_RSTN_REQ
+#define MM_MISC_CPU0_NDM_RSTN_REQ_POS (28U)
+#define MM_MISC_CPU0_NDM_RSTN_REQ_LEN (1U)
+#define MM_MISC_CPU0_NDM_RSTN_REQ_MSK (((1U << MM_MISC_CPU0_NDM_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_REQ_POS)
+#define MM_MISC_CPU0_NDM_RSTN_REQ_UMSK (~(((1U << MM_MISC_CPU0_NDM_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_REQ_POS))
+#define MM_MISC_CPU0_HART_RSTN_REQ MM_MISC_CPU0_HART_RSTN_REQ
+#define MM_MISC_CPU0_HART_RSTN_REQ_POS (29U)
+#define MM_MISC_CPU0_HART_RSTN_REQ_LEN (1U)
+#define MM_MISC_CPU0_HART_RSTN_REQ_MSK (((1U << MM_MISC_CPU0_HART_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_REQ_POS)
+#define MM_MISC_CPU0_HART_RSTN_REQ_UMSK (~(((1U << MM_MISC_CPU0_HART_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_REQ_POS))
+
+/* 0x10 : CPU_sts2 */
+#define MM_MISC_CPU_STS2_OFFSET (0x10)
+#define MM_MISC_CPU0_RETIRE_PC_31_0 MM_MISC_CPU0_RETIRE_PC_31_0
+#define MM_MISC_CPU0_RETIRE_PC_31_0_POS (0U)
+#define MM_MISC_CPU0_RETIRE_PC_31_0_LEN (32U)
+#define MM_MISC_CPU0_RETIRE_PC_31_0_MSK (((1U << MM_MISC_CPU0_RETIRE_PC_31_0_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_31_0_POS)
+#define MM_MISC_CPU0_RETIRE_PC_31_0_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_PC_31_0_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_31_0_POS))
+
+/* 0x18 : CPU_RTC */
+#define MM_MISC_CPU_RTC_OFFSET (0x18)
+#define MM_MISC_C906_RTC_DIV MM_MISC_C906_RTC_DIV
+#define MM_MISC_C906_RTC_DIV_POS (0U)
+#define MM_MISC_C906_RTC_DIV_LEN (10U)
+#define MM_MISC_C906_RTC_DIV_MSK (((1U << MM_MISC_C906_RTC_DIV_LEN) - 1) << MM_MISC_C906_RTC_DIV_POS)
+#define MM_MISC_C906_RTC_DIV_UMSK (~(((1U << MM_MISC_C906_RTC_DIV_LEN) - 1) << MM_MISC_C906_RTC_DIV_POS))
+#define MM_MISC_C906_RTC_RST MM_MISC_C906_RTC_RST
+#define MM_MISC_C906_RTC_RST_POS (30U)
+#define MM_MISC_C906_RTC_RST_LEN (1U)
+#define MM_MISC_C906_RTC_RST_MSK (((1U << MM_MISC_C906_RTC_RST_LEN) - 1) << MM_MISC_C906_RTC_RST_POS)
+#define MM_MISC_C906_RTC_RST_UMSK (~(((1U << MM_MISC_C906_RTC_RST_LEN) - 1) << MM_MISC_C906_RTC_RST_POS))
+#define MM_MISC_C906_RTC_EN MM_MISC_C906_RTC_EN
+#define MM_MISC_C906_RTC_EN_POS (31U)
+#define MM_MISC_C906_RTC_EN_LEN (1U)
+#define MM_MISC_C906_RTC_EN_MSK (((1U << MM_MISC_C906_RTC_EN_LEN) - 1) << MM_MISC_C906_RTC_EN_POS)
+#define MM_MISC_C906_RTC_EN_UMSK (~(((1U << MM_MISC_C906_RTC_EN_LEN) - 1) << MM_MISC_C906_RTC_EN_POS))
+
+/* 0x1C : tzc_mmsys_misc */
+#define MM_MISC_TZC_MMSYS_MISC_OFFSET (0x1C)
+#define MM_MISC_TZC_MM_CPU0_LOCK MM_MISC_TZC_MM_CPU0_LOCK
+#define MM_MISC_TZC_MM_CPU0_LOCK_POS (0U)
+#define MM_MISC_TZC_MM_CPU0_LOCK_LEN (1U)
+#define MM_MISC_TZC_MM_CPU0_LOCK_MSK (((1U << MM_MISC_TZC_MM_CPU0_LOCK_LEN) - 1) << MM_MISC_TZC_MM_CPU0_LOCK_POS)
+#define MM_MISC_TZC_MM_CPU0_LOCK_UMSK (~(((1U << MM_MISC_TZC_MM_CPU0_LOCK_LEN) - 1) << MM_MISC_TZC_MM_CPU0_LOCK_POS))
+#define MM_MISC_TZC_MM_SRAM_LOCK MM_MISC_TZC_MM_SRAM_LOCK
+#define MM_MISC_TZC_MM_SRAM_LOCK_POS (2U)
+#define MM_MISC_TZC_MM_SRAM_LOCK_LEN (1U)
+#define MM_MISC_TZC_MM_SRAM_LOCK_MSK (((1U << MM_MISC_TZC_MM_SRAM_LOCK_LEN) - 1) << MM_MISC_TZC_MM_SRAM_LOCK_POS)
+#define MM_MISC_TZC_MM_SRAM_LOCK_UMSK (~(((1U << MM_MISC_TZC_MM_SRAM_LOCK_LEN) - 1) << MM_MISC_TZC_MM_SRAM_LOCK_POS))
+
+/* 0x20 : peri_apb_ctrl */
+#define MM_MISC_PERI_APB_CTRL_OFFSET (0x20)
+#define MM_MISC_REG_MMINFRA_BERR_INT_EN MM_MISC_REG_MMINFRA_BERR_INT_EN
+#define MM_MISC_REG_MMINFRA_BERR_INT_EN_POS (0U)
+#define MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN (1U)
+#define MM_MISC_REG_MMINFRA_BERR_INT_EN_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS)
+#define MM_MISC_REG_MMINFRA_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS))
+#define MM_MISC_REG_BERR_INT_EN MM_MISC_REG_BERR_INT_EN
+#define MM_MISC_REG_BERR_INT_EN_POS (1U)
+#define MM_MISC_REG_BERR_INT_EN_LEN (1U)
+#define MM_MISC_REG_BERR_INT_EN_MSK (((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS)
+#define MM_MISC_REG_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS))
+#define MM_MISC_REG_CODEC_BERR_INT_EN MM_MISC_REG_CODEC_BERR_INT_EN
+#define MM_MISC_REG_CODEC_BERR_INT_EN_POS (2U)
+#define MM_MISC_REG_CODEC_BERR_INT_EN_LEN (1U)
+#define MM_MISC_REG_CODEC_BERR_INT_EN_MSK (((1U << MM_MISC_REG_CODEC_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_INT_EN_POS)
+#define MM_MISC_REG_CODEC_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_INT_EN_POS))
+#define MM_MISC_REG_MMCPU_BERR_INT_EN MM_MISC_REG_MMCPU_BERR_INT_EN
+#define MM_MISC_REG_MMCPU_BERR_INT_EN_POS (3U)
+#define MM_MISC_REG_MMCPU_BERR_INT_EN_LEN (1U)
+#define MM_MISC_REG_MMCPU_BERR_INT_EN_MSK (((1U << MM_MISC_REG_MMCPU_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_INT_EN_POS)
+#define MM_MISC_REG_MMCPU_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_INT_EN_POS))
+#define MM_MISC_REG_MM_X2HS_SP_BYPASS MM_MISC_REG_MM_X2HS_SP_BYPASS
+#define MM_MISC_REG_MM_X2HS_SP_BYPASS_POS (8U)
+#define MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN (1U)
+#define MM_MISC_REG_MM_X2HS_SP_BYPASS_MSK (((1U << MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN) - 1) << MM_MISC_REG_MM_X2HS_SP_BYPASS_POS)
+#define MM_MISC_REG_MM_X2HS_SP_BYPASS_UMSK (~(((1U << MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN) - 1) << MM_MISC_REG_MM_X2HS_SP_BYPASS_POS))
+#define MM_MISC_RG_PCLK_FORCE_ON MM_MISC_RG_PCLK_FORCE_ON
+#define MM_MISC_RG_PCLK_FORCE_ON_POS (16U)
+#define MM_MISC_RG_PCLK_FORCE_ON_LEN (16U)
+#define MM_MISC_RG_PCLK_FORCE_ON_MSK (((1U << MM_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << MM_MISC_RG_PCLK_FORCE_ON_POS)
+#define MM_MISC_RG_PCLK_FORCE_ON_UMSK (~(((1U << MM_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << MM_MISC_RG_PCLK_FORCE_ON_POS))
+
+/* 0x2C : mm_infra_qos_ctrl */
+#define MM_MISC_MM_INFRA_QOS_CTRL_OFFSET (0x2C)
+#define MM_MISC_REG_MMCPU0_AWQOS MM_MISC_REG_MMCPU0_AWQOS
+#define MM_MISC_REG_MMCPU0_AWQOS_POS (2U)
+#define MM_MISC_REG_MMCPU0_AWQOS_LEN (1U)
+#define MM_MISC_REG_MMCPU0_AWQOS_MSK (((1U << MM_MISC_REG_MMCPU0_AWQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_AWQOS_POS)
+#define MM_MISC_REG_MMCPU0_AWQOS_UMSK (~(((1U << MM_MISC_REG_MMCPU0_AWQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_AWQOS_POS))
+#define MM_MISC_REG_MMCPU0_ARQOS MM_MISC_REG_MMCPU0_ARQOS
+#define MM_MISC_REG_MMCPU0_ARQOS_POS (3U)
+#define MM_MISC_REG_MMCPU0_ARQOS_LEN (1U)
+#define MM_MISC_REG_MMCPU0_ARQOS_MSK (((1U << MM_MISC_REG_MMCPU0_ARQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_ARQOS_POS)
+#define MM_MISC_REG_MMCPU0_ARQOS_UMSK (~(((1U << MM_MISC_REG_MMCPU0_ARQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_ARQOS_POS))
+#define MM_MISC_REG_H_WTHRE_MM2CONN MM_MISC_REG_H_WTHRE_MM2CONN
+#define MM_MISC_REG_H_WTHRE_MM2CONN_POS (16U)
+#define MM_MISC_REG_H_WTHRE_MM2CONN_LEN (2U)
+#define MM_MISC_REG_H_WTHRE_MM2CONN_MSK (((1U << MM_MISC_REG_H_WTHRE_MM2CONN_LEN) - 1) << MM_MISC_REG_H_WTHRE_MM2CONN_POS)
+#define MM_MISC_REG_H_WTHRE_MM2CONN_UMSK (~(((1U << MM_MISC_REG_H_WTHRE_MM2CONN_LEN) - 1) << MM_MISC_REG_H_WTHRE_MM2CONN_POS))
+#define MM_MISC_REG_H_WTHRE_CONN2MM MM_MISC_REG_H_WTHRE_CONN2MM
+#define MM_MISC_REG_H_WTHRE_CONN2MM_POS (18U)
+#define MM_MISC_REG_H_WTHRE_CONN2MM_LEN (2U)
+#define MM_MISC_REG_H_WTHRE_CONN2MM_MSK (((1U << MM_MISC_REG_H_WTHRE_CONN2MM_LEN) - 1) << MM_MISC_REG_H_WTHRE_CONN2MM_POS)
+#define MM_MISC_REG_H_WTHRE_CONN2MM_UMSK (~(((1U << MM_MISC_REG_H_WTHRE_CONN2MM_LEN) - 1) << MM_MISC_REG_H_WTHRE_CONN2MM_POS))
+#define MM_MISC_REG_X_WTHRE_MMHW2PA MM_MISC_REG_X_WTHRE_MMHW2PA
+#define MM_MISC_REG_X_WTHRE_MMHW2PA_POS (20U)
+#define MM_MISC_REG_X_WTHRE_MMHW2PA_LEN (2U)
+#define MM_MISC_REG_X_WTHRE_MMHW2PA_MSK (((1U << MM_MISC_REG_X_WTHRE_MMHW2PA_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2PA_POS)
+#define MM_MISC_REG_X_WTHRE_MMHW2PA_UMSK (~(((1U << MM_MISC_REG_X_WTHRE_MMHW2PA_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2PA_POS))
+#define MM_MISC_REG_X_WTHRE_MMHW2EXT MM_MISC_REG_X_WTHRE_MMHW2EXT
+#define MM_MISC_REG_X_WTHRE_MMHW2EXT_POS (22U)
+#define MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN (2U)
+#define MM_MISC_REG_X_WTHRE_MMHW2EXT_MSK (((1U << MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2EXT_POS)
+#define MM_MISC_REG_X_WTHRE_MMHW2EXT_UMSK (~(((1U << MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2EXT_POS))
+#define MM_MISC_REG_X_WTHRE_PUHS MM_MISC_REG_X_WTHRE_PUHS
+#define MM_MISC_REG_X_WTHRE_PUHS_POS (24U)
+#define MM_MISC_REG_X_WTHRE_PUHS_LEN (2U)
+#define MM_MISC_REG_X_WTHRE_PUHS_MSK (((1U << MM_MISC_REG_X_WTHRE_PUHS_LEN) - 1) << MM_MISC_REG_X_WTHRE_PUHS_POS)
+#define MM_MISC_REG_X_WTHRE_PUHS_UMSK (~(((1U << MM_MISC_REG_X_WTHRE_PUHS_LEN) - 1) << MM_MISC_REG_X_WTHRE_PUHS_POS))
+
+/* 0x40 : dma_clk_ctrl */
+#define MM_MISC_DMA_CLK_CTRL_OFFSET (0x40)
+#define MM_MISC_DMA_CLK_EN MM_MISC_DMA_CLK_EN
+#define MM_MISC_DMA_CLK_EN_POS (0U)
+#define MM_MISC_DMA_CLK_EN_LEN (8U)
+#define MM_MISC_DMA_CLK_EN_MSK (((1U << MM_MISC_DMA_CLK_EN_LEN) - 1) << MM_MISC_DMA_CLK_EN_POS)
+#define MM_MISC_DMA_CLK_EN_UMSK (~(((1U << MM_MISC_DMA_CLK_EN_LEN) - 1) << MM_MISC_DMA_CLK_EN_POS))
+
+/* 0x50 : vram_ctrl */
+#define MM_MISC_VRAM_CTRL_OFFSET (0x50)
+#define MM_MISC_REG_SYSRAM_SET MM_MISC_REG_SYSRAM_SET
+#define MM_MISC_REG_SYSRAM_SET_POS (0U)
+#define MM_MISC_REG_SYSRAM_SET_LEN (1U)
+#define MM_MISC_REG_SYSRAM_SET_MSK (((1U << MM_MISC_REG_SYSRAM_SET_LEN) - 1) << MM_MISC_REG_SYSRAM_SET_POS)
+#define MM_MISC_REG_SYSRAM_SET_UMSK (~(((1U << MM_MISC_REG_SYSRAM_SET_LEN) - 1) << MM_MISC_REG_SYSRAM_SET_POS))
+#define MM_MISC_REG_H2PF_SRAM_REL MM_MISC_REG_H2PF_SRAM_REL
+#define MM_MISC_REG_H2PF_SRAM_REL_POS (1U)
+#define MM_MISC_REG_H2PF_SRAM_REL_LEN (2U)
+#define MM_MISC_REG_H2PF_SRAM_REL_MSK (((1U << MM_MISC_REG_H2PF_SRAM_REL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_REL_POS)
+#define MM_MISC_REG_H2PF_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_H2PF_SRAM_REL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_REL_POS))
+#define MM_MISC_REG_VRAM_SRAM_REL MM_MISC_REG_VRAM_SRAM_REL
+#define MM_MISC_REG_VRAM_SRAM_REL_POS (4U)
+#define MM_MISC_REG_VRAM_SRAM_REL_LEN (1U)
+#define MM_MISC_REG_VRAM_SRAM_REL_MSK (((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS)
+#define MM_MISC_REG_VRAM_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS))
+#define MM_MISC_REG_SUB_SRAM_REL MM_MISC_REG_SUB_SRAM_REL
+#define MM_MISC_REG_SUB_SRAM_REL_POS (6U)
+#define MM_MISC_REG_SUB_SRAM_REL_LEN (1U)
+#define MM_MISC_REG_SUB_SRAM_REL_MSK (((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS)
+#define MM_MISC_REG_SUB_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS))
+#define MM_MISC_REG_BLAI_SRAM_REL MM_MISC_REG_BLAI_SRAM_REL
+#define MM_MISC_REG_BLAI_SRAM_REL_POS (7U)
+#define MM_MISC_REG_BLAI_SRAM_REL_LEN (1U)
+#define MM_MISC_REG_BLAI_SRAM_REL_MSK (((1U << MM_MISC_REG_BLAI_SRAM_REL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_REL_POS)
+#define MM_MISC_REG_BLAI_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_BLAI_SRAM_REL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_REL_POS))
+#define MM_MISC_REG_H2PF_SRAM_SEL MM_MISC_REG_H2PF_SRAM_SEL
+#define MM_MISC_REG_H2PF_SRAM_SEL_POS (8U)
+#define MM_MISC_REG_H2PF_SRAM_SEL_LEN (3U)
+#define MM_MISC_REG_H2PF_SRAM_SEL_MSK (((1U << MM_MISC_REG_H2PF_SRAM_SEL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_SEL_POS)
+#define MM_MISC_REG_H2PF_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_H2PF_SRAM_SEL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_SEL_POS))
+#define MM_MISC_REG_VRAM_SRAM_SEL MM_MISC_REG_VRAM_SRAM_SEL
+#define MM_MISC_REG_VRAM_SRAM_SEL_POS (12U)
+#define MM_MISC_REG_VRAM_SRAM_SEL_LEN (1U)
+#define MM_MISC_REG_VRAM_SRAM_SEL_MSK (((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS)
+#define MM_MISC_REG_VRAM_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS))
+#define MM_MISC_REG_SUB_SRAM_SEL MM_MISC_REG_SUB_SRAM_SEL
+#define MM_MISC_REG_SUB_SRAM_SEL_POS (14U)
+#define MM_MISC_REG_SUB_SRAM_SEL_LEN (1U)
+#define MM_MISC_REG_SUB_SRAM_SEL_MSK (((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS)
+#define MM_MISC_REG_SUB_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS))
+#define MM_MISC_REG_BLAI_SRAM_SEL MM_MISC_REG_BLAI_SRAM_SEL
+#define MM_MISC_REG_BLAI_SRAM_SEL_POS (15U)
+#define MM_MISC_REG_BLAI_SRAM_SEL_LEN (1U)
+#define MM_MISC_REG_BLAI_SRAM_SEL_MSK (((1U << MM_MISC_REG_BLAI_SRAM_SEL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_SEL_POS)
+#define MM_MISC_REG_BLAI_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_BLAI_SRAM_SEL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_SEL_POS))
+
+/* 0x60 : sram_parm */
+#define MM_MISC_SRAM_PARM_OFFSET (0x60)
+#define MM_MISC_REG_SRAM_CPU_RAM_DVS MM_MISC_REG_SRAM_CPU_RAM_DVS
+#define MM_MISC_REG_SRAM_CPU_RAM_DVS_POS (0U)
+#define MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN (4U)
+#define MM_MISC_REG_SRAM_CPU_RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVS_POS)
+#define MM_MISC_REG_SRAM_CPU_RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVS_POS))
+#define MM_MISC_REG_SRAM_CPU_RAM_DVSE MM_MISC_REG_SRAM_CPU_RAM_DVSE
+#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS (4U)
+#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN (1U)
+#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS)
+#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS))
+#define MM_MISC_REG_SRAM_CPU_RAM_NAP MM_MISC_REG_SRAM_CPU_RAM_NAP
+#define MM_MISC_REG_SRAM_CPU_RAM_NAP_POS (5U)
+#define MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN (1U)
+#define MM_MISC_REG_SRAM_CPU_RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_NAP_POS)
+#define MM_MISC_REG_SRAM_CPU_RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_NAP_POS))
+#define MM_MISC_REG_SRAM_L2RAM_DVS MM_MISC_REG_SRAM_L2RAM_DVS
+#define MM_MISC_REG_SRAM_L2RAM_DVS_POS (8U)
+#define MM_MISC_REG_SRAM_L2RAM_DVS_LEN (4U)
+#define MM_MISC_REG_SRAM_L2RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_L2RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVS_POS)
+#define MM_MISC_REG_SRAM_L2RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_L2RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVS_POS))
+#define MM_MISC_REG_SRAM_L2RAM_DVSE MM_MISC_REG_SRAM_L2RAM_DVSE
+#define MM_MISC_REG_SRAM_L2RAM_DVSE_POS (12U)
+#define MM_MISC_REG_SRAM_L2RAM_DVSE_LEN (1U)
+#define MM_MISC_REG_SRAM_L2RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_L2RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVSE_POS)
+#define MM_MISC_REG_SRAM_L2RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_L2RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVSE_POS))
+#define MM_MISC_REG_SRAM_L2RAM_NAP MM_MISC_REG_SRAM_L2RAM_NAP
+#define MM_MISC_REG_SRAM_L2RAM_NAP_POS (13U)
+#define MM_MISC_REG_SRAM_L2RAM_NAP_LEN (1U)
+#define MM_MISC_REG_SRAM_L2RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_L2RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_NAP_POS)
+#define MM_MISC_REG_SRAM_L2RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_L2RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_NAP_POS))
+#define MM_MISC_REG_SRAM_CDC_RAM_DVS MM_MISC_REG_SRAM_CDC_RAM_DVS
+#define MM_MISC_REG_SRAM_CDC_RAM_DVS_POS (16U)
+#define MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN (4U)
+#define MM_MISC_REG_SRAM_CDC_RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVS_POS)
+#define MM_MISC_REG_SRAM_CDC_RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVS_POS))
+#define MM_MISC_REG_SRAM_CDC_RAM_DVSE MM_MISC_REG_SRAM_CDC_RAM_DVSE
+#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS (20U)
+#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN (1U)
+#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS)
+#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS))
+#define MM_MISC_REG_SRAM_CDC_RAM_NAP MM_MISC_REG_SRAM_CDC_RAM_NAP
+#define MM_MISC_REG_SRAM_CDC_RAM_NAP_POS (21U)
+#define MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN (1U)
+#define MM_MISC_REG_SRAM_CDC_RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS)
+#define MM_MISC_REG_SRAM_CDC_RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS))
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS MM_MISC_REG_SRAM_SUB_RAM_DVS
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_POS (24U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN (4U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS))
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE MM_MISC_REG_SRAM_SUB_RAM_DVSE
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS (28U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN (1U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS))
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP MM_MISC_REG_SRAM_SUB_RAM_NAP
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_POS (29U)
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN (1U)
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS)
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS))
+
+/* 0xA0 : MM_INT_STA0 */
+#define MM_MISC_MM_INT_STA0_OFFSET (0xA0)
+#define MM_MISC_MM_INT_STA0 MM_MISC_MM_INT_STA0
+#define MM_MISC_MM_INT_STA0_POS (0U)
+#define MM_MISC_MM_INT_STA0_LEN (32U)
+#define MM_MISC_MM_INT_STA0_MSK (((1U << MM_MISC_MM_INT_STA0_LEN) - 1) << MM_MISC_MM_INT_STA0_POS)
+#define MM_MISC_MM_INT_STA0_UMSK (~(((1U << MM_MISC_MM_INT_STA0_LEN) - 1) << MM_MISC_MM_INT_STA0_POS))
+
+/* 0xA4 : MM_INT_MASK0 */
+#define MM_MISC_MM_INT_MASK0_OFFSET (0xA4)
+#define MM_MISC_MM_INT_MASK0 MM_MISC_MM_INT_MASK0
+#define MM_MISC_MM_INT_MASK0_POS (0U)
+#define MM_MISC_MM_INT_MASK0_LEN (32U)
+#define MM_MISC_MM_INT_MASK0_MSK (((1U << MM_MISC_MM_INT_MASK0_LEN) - 1) << MM_MISC_MM_INT_MASK0_POS)
+#define MM_MISC_MM_INT_MASK0_UMSK (~(((1U << MM_MISC_MM_INT_MASK0_LEN) - 1) << MM_MISC_MM_INT_MASK0_POS))
+
+/* 0xA8 : MM_INT_CLR_0 */
+#define MM_MISC_MM_INT_CLR_0_OFFSET (0xA8)
+#define MM_MISC_MM_INT_CLR0 MM_MISC_MM_INT_CLR0
+#define MM_MISC_MM_INT_CLR0_POS (0U)
+#define MM_MISC_MM_INT_CLR0_LEN (32U)
+#define MM_MISC_MM_INT_CLR0_MSK (((1U << MM_MISC_MM_INT_CLR0_LEN) - 1) << MM_MISC_MM_INT_CLR0_POS)
+#define MM_MISC_MM_INT_CLR0_UMSK (~(((1U << MM_MISC_MM_INT_CLR0_LEN) - 1) << MM_MISC_MM_INT_CLR0_POS))
+
+/* 0xAC : MM_INT_STA1 */
+#define MM_MISC_MM_INT_STA1_OFFSET (0xAC)
+#define MM_MISC_MM_INT_STA1 MM_MISC_MM_INT_STA1
+#define MM_MISC_MM_INT_STA1_POS (0U)
+#define MM_MISC_MM_INT_STA1_LEN (32U)
+#define MM_MISC_MM_INT_STA1_MSK (((1U << MM_MISC_MM_INT_STA1_LEN) - 1) << MM_MISC_MM_INT_STA1_POS)
+#define MM_MISC_MM_INT_STA1_UMSK (~(((1U << MM_MISC_MM_INT_STA1_LEN) - 1) << MM_MISC_MM_INT_STA1_POS))
+
+/* 0xB0 : MM_INT_MASK1 */
+#define MM_MISC_MM_INT_MASK1_OFFSET (0xB0)
+#define MM_MISC_MM_INT_MASK1 MM_MISC_MM_INT_MASK1
+#define MM_MISC_MM_INT_MASK1_POS (0U)
+#define MM_MISC_MM_INT_MASK1_LEN (32U)
+#define MM_MISC_MM_INT_MASK1_MSK (((1U << MM_MISC_MM_INT_MASK1_LEN) - 1) << MM_MISC_MM_INT_MASK1_POS)
+#define MM_MISC_MM_INT_MASK1_UMSK (~(((1U << MM_MISC_MM_INT_MASK1_LEN) - 1) << MM_MISC_MM_INT_MASK1_POS))
+
+/* 0xB4 : MM_INT_CLR_1 */
+#define MM_MISC_MM_INT_CLR_1_OFFSET (0xB4)
+#define MM_MISC_MM_INT_CLR1 MM_MISC_MM_INT_CLR1
+#define MM_MISC_MM_INT_CLR1_POS (0U)
+#define MM_MISC_MM_INT_CLR1_LEN (32U)
+#define MM_MISC_MM_INT_CLR1_MSK (((1U << MM_MISC_MM_INT_CLR1_LEN) - 1) << MM_MISC_MM_INT_CLR1_POS)
+#define MM_MISC_MM_INT_CLR1_UMSK (~(((1U << MM_MISC_MM_INT_CLR1_LEN) - 1) << MM_MISC_MM_INT_CLR1_POS))
+
+/* 0xF0 : mmsys_debug_sel */
+#define MM_MISC_MMSYS_DEBUG_SEL_OFFSET (0xF0)
+#define MM_MISC_MMSYS_DEBUG_SEL MM_MISC_MMSYS_DEBUG_SEL
+#define MM_MISC_MMSYS_DEBUG_SEL_POS (0U)
+#define MM_MISC_MMSYS_DEBUG_SEL_LEN (4U)
+#define MM_MISC_MMSYS_DEBUG_SEL_MSK (((1U << MM_MISC_MMSYS_DEBUG_SEL_LEN) - 1) << MM_MISC_MMSYS_DEBUG_SEL_POS)
+#define MM_MISC_MMSYS_DEBUG_SEL_UMSK (~(((1U << MM_MISC_MMSYS_DEBUG_SEL_LEN) - 1) << MM_MISC_MMSYS_DEBUG_SEL_POS))
+
+/* 0xFC : mmsys_misc_dummy */
+#define MM_MISC_MMSYS_MISC_DUMMY_OFFSET (0xFC)
+#define MM_MISC_PIR_CTRL_O MM_MISC_PIR_CTRL_O
+#define MM_MISC_PIR_CTRL_O_POS (0U)
+#define MM_MISC_PIR_CTRL_O_LEN (1U)
+#define MM_MISC_PIR_CTRL_O_MSK (((1U << MM_MISC_PIR_CTRL_O_LEN) - 1) << MM_MISC_PIR_CTRL_O_POS)
+#define MM_MISC_PIR_CTRL_O_UMSK (~(((1U << MM_MISC_PIR_CTRL_O_LEN) - 1) << MM_MISC_PIR_CTRL_O_POS))
+#define MM_MISC_LIGHT_SENSOR_CTRL_O MM_MISC_LIGHT_SENSOR_CTRL_O
+#define MM_MISC_LIGHT_SENSOR_CTRL_O_POS (1U)
+#define MM_MISC_LIGHT_SENSOR_CTRL_O_LEN (1U)
+#define MM_MISC_LIGHT_SENSOR_CTRL_O_MSK (((1U << MM_MISC_LIGHT_SENSOR_CTRL_O_LEN) - 1) << MM_MISC_LIGHT_SENSOR_CTRL_O_POS)
+#define MM_MISC_LIGHT_SENSOR_CTRL_O_UMSK (~(((1U << MM_MISC_LIGHT_SENSOR_CTRL_O_LEN) - 1) << MM_MISC_LIGHT_SENSOR_CTRL_O_POS))
+#define MM_MISC_IR_CUT_CTRL_O MM_MISC_IR_CUT_CTRL_O
+#define MM_MISC_IR_CUT_CTRL_O_POS (2U)
+#define MM_MISC_IR_CUT_CTRL_O_LEN (1U)
+#define MM_MISC_IR_CUT_CTRL_O_MSK (((1U << MM_MISC_IR_CUT_CTRL_O_LEN) - 1) << MM_MISC_IR_CUT_CTRL_O_POS)
+#define MM_MISC_IR_CUT_CTRL_O_UMSK (~(((1U << MM_MISC_IR_CUT_CTRL_O_LEN) - 1) << MM_MISC_IR_CUT_CTRL_O_POS))
+#define MM_MISC_DVP_SENSOR_PWDN MM_MISC_DVP_SENSOR_PWDN
+#define MM_MISC_DVP_SENSOR_PWDN_POS (3U)
+#define MM_MISC_DVP_SENSOR_PWDN_LEN (1U)
+#define MM_MISC_DVP_SENSOR_PWDN_MSK (((1U << MM_MISC_DVP_SENSOR_PWDN_LEN) - 1) << MM_MISC_DVP_SENSOR_PWDN_POS)
+#define MM_MISC_DVP_SENSOR_PWDN_UMSK (~(((1U << MM_MISC_DVP_SENSOR_PWDN_LEN) - 1) << MM_MISC_DVP_SENSOR_PWDN_POS))
+#define MM_MISC_DUMMY_REG MM_MISC_DUMMY_REG
+#define MM_MISC_DUMMY_REG_POS (4U)
+#define MM_MISC_DUMMY_REG_LEN (28U)
+#define MM_MISC_DUMMY_REG_MSK (((1U << MM_MISC_DUMMY_REG_LEN) - 1) << MM_MISC_DUMMY_REG_POS)
+#define MM_MISC_DUMMY_REG_UMSK (~(((1U << MM_MISC_DUMMY_REG_LEN) - 1) << MM_MISC_DUMMY_REG_POS))
+
+/* 0x100 : DDR_debug */
+#define MM_MISC_DDR_DEBUG_OFFSET (0x100)
+#define MM_MISC_DDR_CALIB_DONE MM_MISC_DDR_CALIB_DONE
+#define MM_MISC_DDR_CALIB_DONE_POS (0U)
+#define MM_MISC_DDR_CALIB_DONE_LEN (1U)
+#define MM_MISC_DDR_CALIB_DONE_MSK (((1U << MM_MISC_DDR_CALIB_DONE_LEN) - 1) << MM_MISC_DDR_CALIB_DONE_POS)
+#define MM_MISC_DDR_CALIB_DONE_UMSK (~(((1U << MM_MISC_DDR_CALIB_DONE_LEN) - 1) << MM_MISC_DDR_CALIB_DONE_POS))
+
+/* 0x140 : mm_berr_cfg0 */
+#define MM_MISC_MM_BERR_CFG0_OFFSET (0x140)
+#define MM_MISC_REG_BERR_EN MM_MISC_REG_BERR_EN
+#define MM_MISC_REG_BERR_EN_POS (0U)
+#define MM_MISC_REG_BERR_EN_LEN (3U)
+#define MM_MISC_REG_BERR_EN_MSK (((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS)
+#define MM_MISC_REG_BERR_EN_UMSK (~(((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS))
+#define MM_MISC_REG_CODEC_BERR_EN MM_MISC_REG_CODEC_BERR_EN
+#define MM_MISC_REG_CODEC_BERR_EN_POS (8U)
+#define MM_MISC_REG_CODEC_BERR_EN_LEN (3U)
+#define MM_MISC_REG_CODEC_BERR_EN_MSK (((1U << MM_MISC_REG_CODEC_BERR_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_EN_POS)
+#define MM_MISC_REG_CODEC_BERR_EN_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_EN_POS))
+#define MM_MISC_REG_MMCPU_BERR_EN MM_MISC_REG_MMCPU_BERR_EN
+#define MM_MISC_REG_MMCPU_BERR_EN_POS (16U)
+#define MM_MISC_REG_MMCPU_BERR_EN_LEN (1U)
+#define MM_MISC_REG_MMCPU_BERR_EN_MSK (((1U << MM_MISC_REG_MMCPU_BERR_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_EN_POS)
+#define MM_MISC_REG_MMCPU_BERR_EN_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_EN_POS))
+#define MM_MISC_REG_MMINFRA_BERR_EN MM_MISC_REG_MMINFRA_BERR_EN
+#define MM_MISC_REG_MMINFRA_BERR_EN_POS (24U)
+#define MM_MISC_REG_MMINFRA_BERR_EN_LEN (5U)
+#define MM_MISC_REG_MMINFRA_BERR_EN_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_EN_POS)
+#define MM_MISC_REG_MMINFRA_BERR_EN_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_EN_POS))
+
+/* 0x144 : mm_berr_cfg1 */
+#define MM_MISC_MM_BERR_CFG1_OFFSET (0x144)
+#define MM_MISC_REG_BERR_CLR MM_MISC_REG_BERR_CLR
+#define MM_MISC_REG_BERR_CLR_POS (0U)
+#define MM_MISC_REG_BERR_CLR_LEN (1U)
+#define MM_MISC_REG_BERR_CLR_MSK (((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS)
+#define MM_MISC_REG_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS))
+#define MM_MISC_REG_CODEC_BERR_CLR MM_MISC_REG_CODEC_BERR_CLR
+#define MM_MISC_REG_CODEC_BERR_CLR_POS (1U)
+#define MM_MISC_REG_CODEC_BERR_CLR_LEN (1U)
+#define MM_MISC_REG_CODEC_BERR_CLR_MSK (((1U << MM_MISC_REG_CODEC_BERR_CLR_LEN) - 1) << MM_MISC_REG_CODEC_BERR_CLR_POS)
+#define MM_MISC_REG_CODEC_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_CLR_LEN) - 1) << MM_MISC_REG_CODEC_BERR_CLR_POS))
+#define MM_MISC_REG_MMCPU_BERR_CLR MM_MISC_REG_MMCPU_BERR_CLR
+#define MM_MISC_REG_MMCPU_BERR_CLR_POS (2U)
+#define MM_MISC_REG_MMCPU_BERR_CLR_LEN (1U)
+#define MM_MISC_REG_MMCPU_BERR_CLR_MSK (((1U << MM_MISC_REG_MMCPU_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_CLR_POS)
+#define MM_MISC_REG_MMCPU_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_CLR_POS))
+#define MM_MISC_REG_MMINFRA_BERR_CLR MM_MISC_REG_MMINFRA_BERR_CLR
+#define MM_MISC_REG_MMINFRA_BERR_CLR_POS (3U)
+#define MM_MISC_REG_MMINFRA_BERR_CLR_LEN (1U)
+#define MM_MISC_REG_MMINFRA_BERR_CLR_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS)
+#define MM_MISC_REG_MMINFRA_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS))
+#define MM_MISC_REG_BERR_LAST MM_MISC_REG_BERR_LAST
+#define MM_MISC_REG_BERR_LAST_POS (8U)
+#define MM_MISC_REG_BERR_LAST_LEN (1U)
+#define MM_MISC_REG_BERR_LAST_MSK (((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS)
+#define MM_MISC_REG_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS))
+#define MM_MISC_REG_CODEC_BERR_LAST MM_MISC_REG_CODEC_BERR_LAST
+#define MM_MISC_REG_CODEC_BERR_LAST_POS (9U)
+#define MM_MISC_REG_CODEC_BERR_LAST_LEN (1U)
+#define MM_MISC_REG_CODEC_BERR_LAST_MSK (((1U << MM_MISC_REG_CODEC_BERR_LAST_LEN) - 1) << MM_MISC_REG_CODEC_BERR_LAST_POS)
+#define MM_MISC_REG_CODEC_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_LAST_LEN) - 1) << MM_MISC_REG_CODEC_BERR_LAST_POS))
+#define MM_MISC_REG_MMCPU_BERR_LAST MM_MISC_REG_MMCPU_BERR_LAST
+#define MM_MISC_REG_MMCPU_BERR_LAST_POS (10U)
+#define MM_MISC_REG_MMCPU_BERR_LAST_LEN (1U)
+#define MM_MISC_REG_MMCPU_BERR_LAST_MSK (((1U << MM_MISC_REG_MMCPU_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_LAST_POS)
+#define MM_MISC_REG_MMCPU_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_LAST_POS))
+#define MM_MISC_REG_MMINFRA_BERR_LAST MM_MISC_REG_MMINFRA_BERR_LAST
+#define MM_MISC_REG_MMINFRA_BERR_LAST_POS (11U)
+#define MM_MISC_REG_MMINFRA_BERR_LAST_LEN (1U)
+#define MM_MISC_REG_MMINFRA_BERR_LAST_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS)
+#define MM_MISC_REG_MMINFRA_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS))
+#define MM_MISC_STS_BERR MM_MISC_STS_BERR
+#define MM_MISC_STS_BERR_POS (16U)
+#define MM_MISC_STS_BERR_LEN (1U)
+#define MM_MISC_STS_BERR_MSK (((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS)
+#define MM_MISC_STS_BERR_UMSK (~(((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS))
+#define MM_MISC_STS_CODEC_BERR MM_MISC_STS_CODEC_BERR
+#define MM_MISC_STS_CODEC_BERR_POS (17U)
+#define MM_MISC_STS_CODEC_BERR_LEN (1U)
+#define MM_MISC_STS_CODEC_BERR_MSK (((1U << MM_MISC_STS_CODEC_BERR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_POS)
+#define MM_MISC_STS_CODEC_BERR_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_POS))
+#define MM_MISC_STS_MMCPU_BERR MM_MISC_STS_MMCPU_BERR
+#define MM_MISC_STS_MMCPU_BERR_POS (18U)
+#define MM_MISC_STS_MMCPU_BERR_LEN (1U)
+#define MM_MISC_STS_MMCPU_BERR_MSK (((1U << MM_MISC_STS_MMCPU_BERR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_POS)
+#define MM_MISC_STS_MMCPU_BERR_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_POS))
+#define MM_MISC_STS_MMINFRA_BERR MM_MISC_STS_MMINFRA_BERR
+#define MM_MISC_STS_MMINFRA_BERR_POS (19U)
+#define MM_MISC_STS_MMINFRA_BERR_LEN (1U)
+#define MM_MISC_STS_MMINFRA_BERR_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS)
+#define MM_MISC_STS_MMINFRA_BERR_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS))
+#define MM_MISC_STS_BERR_WRITE MM_MISC_STS_BERR_WRITE
+#define MM_MISC_STS_BERR_WRITE_POS (24U)
+#define MM_MISC_STS_BERR_WRITE_LEN (1U)
+#define MM_MISC_STS_BERR_WRITE_MSK (((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS)
+#define MM_MISC_STS_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS))
+#define MM_MISC_STS_CODEC_BERR_WRITE MM_MISC_STS_CODEC_BERR_WRITE
+#define MM_MISC_STS_CODEC_BERR_WRITE_POS (25U)
+#define MM_MISC_STS_CODEC_BERR_WRITE_LEN (1U)
+#define MM_MISC_STS_CODEC_BERR_WRITE_MSK (((1U << MM_MISC_STS_CODEC_BERR_WRITE_LEN) - 1) << MM_MISC_STS_CODEC_BERR_WRITE_POS)
+#define MM_MISC_STS_CODEC_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_WRITE_LEN) - 1) << MM_MISC_STS_CODEC_BERR_WRITE_POS))
+#define MM_MISC_STS_MMCPU_BERR_WRITE MM_MISC_STS_MMCPU_BERR_WRITE
+#define MM_MISC_STS_MMCPU_BERR_WRITE_POS (26U)
+#define MM_MISC_STS_MMCPU_BERR_WRITE_LEN (1U)
+#define MM_MISC_STS_MMCPU_BERR_WRITE_MSK (((1U << MM_MISC_STS_MMCPU_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_WRITE_POS)
+#define MM_MISC_STS_MMCPU_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_WRITE_POS))
+#define MM_MISC_STS_MMINFRA_BERR_WRITE MM_MISC_STS_MMINFRA_BERR_WRITE
+#define MM_MISC_STS_MMINFRA_BERR_WRITE_POS (27U)
+#define MM_MISC_STS_MMINFRA_BERR_WRITE_LEN (1U)
+#define MM_MISC_STS_MMINFRA_BERR_WRITE_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_WRITE_POS)
+#define MM_MISC_STS_MMINFRA_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_WRITE_POS))
+
+/* 0x148 : mm_berr_cfg2 */
+#define MM_MISC_MM_BERR_CFG2_OFFSET (0x148)
+#define MM_MISC_STS_BERR_SRC MM_MISC_STS_BERR_SRC
+#define MM_MISC_STS_BERR_SRC_POS (0U)
+#define MM_MISC_STS_BERR_SRC_LEN (3U)
+#define MM_MISC_STS_BERR_SRC_MSK (((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS)
+#define MM_MISC_STS_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS))
+#define MM_MISC_STS_BERR_ID MM_MISC_STS_BERR_ID
+#define MM_MISC_STS_BERR_ID_POS (8U)
+#define MM_MISC_STS_BERR_ID_LEN (4U)
+#define MM_MISC_STS_BERR_ID_MSK (((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS)
+#define MM_MISC_STS_BERR_ID_UMSK (~(((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS))
+#define MM_MISC_STS_CODEC_BERR_SRC MM_MISC_STS_CODEC_BERR_SRC
+#define MM_MISC_STS_CODEC_BERR_SRC_POS (16U)
+#define MM_MISC_STS_CODEC_BERR_SRC_LEN (3U)
+#define MM_MISC_STS_CODEC_BERR_SRC_MSK (((1U << MM_MISC_STS_CODEC_BERR_SRC_LEN) - 1) << MM_MISC_STS_CODEC_BERR_SRC_POS)
+#define MM_MISC_STS_CODEC_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_SRC_LEN) - 1) << MM_MISC_STS_CODEC_BERR_SRC_POS))
+#define MM_MISC_STS_CODEC_BERR_ID MM_MISC_STS_CODEC_BERR_ID
+#define MM_MISC_STS_CODEC_BERR_ID_POS (24U)
+#define MM_MISC_STS_CODEC_BERR_ID_LEN (1U)
+#define MM_MISC_STS_CODEC_BERR_ID_MSK (((1U << MM_MISC_STS_CODEC_BERR_ID_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ID_POS)
+#define MM_MISC_STS_CODEC_BERR_ID_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_ID_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ID_POS))
+
+/* 0x14C : mm_berr_cfg3 */
+#define MM_MISC_MM_BERR_CFG3_OFFSET (0x14C)
+#define MM_MISC_STS_MMCPU_BERR_SRC MM_MISC_STS_MMCPU_BERR_SRC
+#define MM_MISC_STS_MMCPU_BERR_SRC_POS (0U)
+#define MM_MISC_STS_MMCPU_BERR_SRC_LEN (1U)
+#define MM_MISC_STS_MMCPU_BERR_SRC_MSK (((1U << MM_MISC_STS_MMCPU_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_SRC_POS)
+#define MM_MISC_STS_MMCPU_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_SRC_POS))
+#define MM_MISC_STS_MMCPU_BERR_ID MM_MISC_STS_MMCPU_BERR_ID
+#define MM_MISC_STS_MMCPU_BERR_ID_POS (8U)
+#define MM_MISC_STS_MMCPU_BERR_ID_LEN (4U)
+#define MM_MISC_STS_MMCPU_BERR_ID_MSK (((1U << MM_MISC_STS_MMCPU_BERR_ID_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ID_POS)
+#define MM_MISC_STS_MMCPU_BERR_ID_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_ID_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ID_POS))
+#define MM_MISC_STS_MMINFRA_BERR_SRC MM_MISC_STS_MMINFRA_BERR_SRC
+#define MM_MISC_STS_MMINFRA_BERR_SRC_POS (16U)
+#define MM_MISC_STS_MMINFRA_BERR_SRC_LEN (5U)
+#define MM_MISC_STS_MMINFRA_BERR_SRC_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_SRC_POS)
+#define MM_MISC_STS_MMINFRA_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_SRC_POS))
+#define MM_MISC_STS_MMINFRA_BERR_ID MM_MISC_STS_MMINFRA_BERR_ID
+#define MM_MISC_STS_MMINFRA_BERR_ID_POS (24U)
+#define MM_MISC_STS_MMINFRA_BERR_ID_LEN (6U)
+#define MM_MISC_STS_MMINFRA_BERR_ID_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_ID_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ID_POS)
+#define MM_MISC_STS_MMINFRA_BERR_ID_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_ID_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ID_POS))
+
+/* 0x150 : mm_berr_cfg4 */
+#define MM_MISC_MM_BERR_CFG4_OFFSET (0x150)
+#define MM_MISC_STS_BERR_ADDR MM_MISC_STS_BERR_ADDR
+#define MM_MISC_STS_BERR_ADDR_POS (0U)
+#define MM_MISC_STS_BERR_ADDR_LEN (32U)
+#define MM_MISC_STS_BERR_ADDR_MSK (((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS)
+#define MM_MISC_STS_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS))
+
+/* 0x154 : mm_berr_cfg5 */
+#define MM_MISC_MM_BERR_CFG5_OFFSET (0x154)
+#define MM_MISC_STS_CODEC_BERR_ADDR MM_MISC_STS_CODEC_BERR_ADDR
+#define MM_MISC_STS_CODEC_BERR_ADDR_POS (0U)
+#define MM_MISC_STS_CODEC_BERR_ADDR_LEN (32U)
+#define MM_MISC_STS_CODEC_BERR_ADDR_MSK (((1U << MM_MISC_STS_CODEC_BERR_ADDR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ADDR_POS)
+#define MM_MISC_STS_CODEC_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_ADDR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ADDR_POS))
+
+/* 0x158 : mm_berr_cfg6 */
+#define MM_MISC_MM_BERR_CFG6_OFFSET (0x158)
+#define MM_MISC_STS_MMCPU_BERR_ADDR MM_MISC_STS_MMCPU_BERR_ADDR
+#define MM_MISC_STS_MMCPU_BERR_ADDR_POS (0U)
+#define MM_MISC_STS_MMCPU_BERR_ADDR_LEN (32U)
+#define MM_MISC_STS_MMCPU_BERR_ADDR_MSK (((1U << MM_MISC_STS_MMCPU_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ADDR_POS)
+#define MM_MISC_STS_MMCPU_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ADDR_POS))
+
+/* 0x15C : mm_berr_cfg7 */
+#define MM_MISC_MM_BERR_CFG7_OFFSET (0x15C)
+#define MM_MISC_STS_MMINFRA_BERR_ADDR MM_MISC_STS_MMINFRA_BERR_ADDR
+#define MM_MISC_STS_MMINFRA_BERR_ADDR_POS (0U)
+#define MM_MISC_STS_MMINFRA_BERR_ADDR_LEN (32U)
+#define MM_MISC_STS_MMINFRA_BERR_ADDR_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ADDR_POS)
+#define MM_MISC_STS_MMINFRA_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ADDR_POS))
+
+struct mm_misc_reg {
+ /* 0x0 : CPU0_Boot */
+ union {
+ struct {
+ uint32_t reg_cpu0_rvba : 32; /* [31: 0], r/w, 0x3eff0000 */
+ } BF;
+ uint32_t WORD;
+ } CPU0_Boot;
+
+ /* 0x4 reserved */
+ uint8_t RESERVED0x4[4];
+
+ /* 0x8 : CPU_cfg */
+ union {
+ struct {
+ uint32_t reg_cpu0_apb_base : 13; /* [12: 0], r/w, 0x1c */
+ uint32_t reserved_13_27 : 15; /* [27:13], rsvd, 0x0 */
+ uint32_t cpu0_ndm_rstn_en : 1; /* [ 28], r/w, 0x0 */
+ uint32_t cpu0_hart_rstn_en : 1; /* [ 29], r/w, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU_cfg;
+
+ /* 0xC : CPU_sts1 */
+ union {
+ struct {
+ uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */
+ uint32_t cpu0_lpmd_b : 2; /* [ 5: 4], r, 0x0 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t cpu0_retire_pc_39_32 : 8; /* [23:16], r, 0x0 */
+ uint32_t cpu0_retire : 1; /* [ 24], r, 0x0 */
+ uint32_t cpu0_pad_halted : 1; /* [ 25], r, 0x0 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t cpu0_ndm_rstn_req : 1; /* [ 28], r, 0x0 */
+ uint32_t cpu0_hart_rstn_req : 1; /* [ 29], r, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU_sts1;
+
+ /* 0x10 : CPU_sts2 */
+ union {
+ struct {
+ uint32_t cpu0_retire_pc_31_0 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU_sts2;
+
+ /* 0x14 reserved */
+ uint8_t RESERVED0x14[4];
+
+ /* 0x18 : CPU_RTC */
+ union {
+ struct {
+ uint32_t c906_rtc_div : 10; /* [ 9: 0], r/w, 0xa */
+ uint32_t reserved_10_29 : 20; /* [29:10], rsvd, 0x0 */
+ uint32_t c906_rtc_rst : 1; /* [ 30], r/w, 0x0 */
+ uint32_t c906_rtc_en : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } CPU_RTC;
+
+ /* 0x1C : tzc_mmsys_misc */
+ union {
+ struct {
+ uint32_t tzc_mm_cpu0_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t tzc_mm_sram_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mmsys_misc;
+
+ /* 0x20 : peri_apb_ctrl */
+ union {
+ struct {
+ uint32_t reg_mminfra_berr_int_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_berr_int_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_codec_berr_int_en : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_mmcpu_berr_int_en : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t reg_mm_x2hs_sp_bypass : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
+ uint32_t rg_pclk_force_on : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } peri_apb_ctrl;
+
+ /* 0x24 reserved */
+ uint8_t RESERVED0x24[8];
+
+ /* 0x2C : mm_infra_qos_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t reg_mmcpu0_awqos : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_mmcpu0_arqos : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */
+ uint32_t reg_h_wthre_mm2conn : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reg_h_wthre_conn2mm : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_x_wthre_mmhw2pA : 2; /* [21:20], r/w, 0x0 */
+ uint32_t reg_x_wthre_mmhw2ext : 2; /* [23:22], r/w, 0x0 */
+ uint32_t reg_x_wthre_pUHS : 2; /* [25:24], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_infra_qos_ctrl;
+
+ /* 0x30 reserved */
+ uint8_t RESERVED0x30[16];
+
+ /* 0x40 : dma_clk_ctrl */
+ union {
+ struct {
+ uint32_t dma_clk_en : 8; /* [ 7: 0], r/w, 0xff */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } dma_clk_ctrl;
+
+ /* 0x44 reserved */
+ uint8_t RESERVED0x44[12];
+
+ /* 0x50 : vram_ctrl */
+ union {
+ struct {
+ uint32_t reg_sysram_set : 1; /* [ 0], w1p, 0x0 */
+ uint32_t reg_h2pf_sram_rel : 2; /* [ 2: 1], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t reg_vram_sram_rel : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */
+ uint32_t reg_sub_sram_rel : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_blai_sram_rel : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_h2pf_sram_sel : 3; /* [10: 8], r, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t reg_vram_sram_sel : 1; /* [ 12], r, 0x0 */
+ uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */
+ uint32_t reg_sub_sram_sel : 1; /* [ 14], r, 0x0 */
+ uint32_t reg_blai_sram_sel : 1; /* [ 15], r, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } vram_ctrl;
+
+ /* 0x54 reserved */
+ uint8_t RESERVED0x54[12];
+
+ /* 0x60 : sram_parm */
+ union {
+ struct {
+ uint32_t reg_sram_cpu_ram_dvs : 4; /* [ 3: 0], r/w, 0xc */
+ uint32_t reg_sram_cpu_ram_dvse : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_sram_cpu_ram_nap : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_sram_l2ram_dvs : 4; /* [11: 8], r/w, 0xc */
+ uint32_t reg_sram_l2ram_dvse : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_sram_l2ram_nap : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t reg_sram_cdc_ram_dvs : 4; /* [19:16], r/w, 0xc */
+ uint32_t reg_sram_cdc_ram_dvse : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_sram_cdc_ram_nap : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_sram_sub_ram_dvs : 4; /* [27:24], r/w, 0xc */
+ uint32_t reg_sram_sub_ram_dvse : 1; /* [ 28], r/w, 0x0 */
+ uint32_t reg_sram_sub_ram_nap : 1; /* [ 29], r/w, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sram_parm;
+
+ /* 0x64 reserved */
+ uint8_t RESERVED0x64[60];
+
+ /* 0xA0 : MM_INT_STA0 */
+ union {
+ struct {
+ uint32_t mm_int_sta0 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } MM_INT_STA0;
+
+ /* 0xA4 : MM_INT_MASK0 */
+ union {
+ struct {
+ uint32_t mm_int_mask0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } MM_INT_MASK0;
+
+ /* 0xA8 : MM_INT_CLR_0 */
+ union {
+ struct {
+ uint32_t mm_int_clr0 : 32; /* [31: 0], w1p, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } MM_INT_CLR_0;
+
+ /* 0xAC : MM_INT_STA1 */
+ union {
+ struct {
+ uint32_t mm_int_sta1 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } MM_INT_STA1;
+
+ /* 0xB0 : MM_INT_MASK1 */
+ union {
+ struct {
+ uint32_t mm_int_mask1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } MM_INT_MASK1;
+
+ /* 0xB4 : MM_INT_CLR_1 */
+ union {
+ struct {
+ uint32_t mm_int_clr1 : 32; /* [31: 0], w1p, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } MM_INT_CLR_1;
+
+ /* 0xb8 reserved */
+ uint8_t RESERVED0xb8[56];
+
+ /* 0xF0 : mmsys_debug_sel */
+ union {
+ struct {
+ uint32_t mmsys_debug_sel : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mmsys_debug_sel;
+
+ /* 0xf4 reserved */
+ uint8_t RESERVED0xf4[8];
+
+ /* 0xFC : mmsys_misc_dummy */
+ union {
+ struct {
+ uint32_t PIR_ctrl_o : 1; /* [ 0], r/w, 0x0 */
+ uint32_t Light_sensor_ctrl_o : 1; /* [ 1], r/w, 0x0 */
+ uint32_t IR_cut_ctrl_o : 1; /* [ 2], r/w, 0x0 */
+ uint32_t dvp_sensor_pwdn : 1; /* [ 3], r/w, 0x0 */
+ uint32_t dummy_reg : 28; /* [31: 4], r/w, 0xfff0000 */
+ } BF;
+ uint32_t WORD;
+ } mmsys_misc_dummy;
+
+ /* 0x100 : DDR_debug */
+ union {
+ struct {
+ uint32_t ddr_calib_done : 1; /* [ 0], r, 0x0 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } DDR_debug;
+
+ /* 0x104 reserved */
+ uint8_t RESERVED0x104[60];
+
+ /* 0x140 : mm_berr_cfg0 */
+ union {
+ struct {
+ uint32_t reg_berr_en : 3; /* [ 2: 0], r/w, 0x7 */
+ uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
+ uint32_t reg_codec_berr_en : 3; /* [10: 8], r/w, 0x7 */
+ uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
+ uint32_t reg_mmcpu_berr_en : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
+ uint32_t reg_mminfra_berr_en : 5; /* [28:24], r/w, 0x1f */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg0;
+
+ /* 0x144 : mm_berr_cfg1 */
+ union {
+ struct {
+ uint32_t reg_berr_clr : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_codec_berr_clr : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_mmcpu_berr_clr : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_mminfra_berr_clr : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t reg_berr_last : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_codec_berr_last : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg_mmcpu_berr_last : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg_mminfra_berr_last : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t sts_berr : 1; /* [ 16], r, 0x0 */
+ uint32_t sts_codec_berr : 1; /* [ 17], r, 0x0 */
+ uint32_t sts_mmcpu_berr : 1; /* [ 18], r, 0x0 */
+ uint32_t sts_mminfra_berr : 1; /* [ 19], r, 0x0 */
+ uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
+ uint32_t sts_berr_write : 1; /* [ 24], r, 0x0 */
+ uint32_t sts_codec_berr_write : 1; /* [ 25], r, 0x0 */
+ uint32_t sts_mmcpu_berr_write : 1; /* [ 26], r, 0x0 */
+ uint32_t sts_mminfra_berr_write : 1; /* [ 27], r, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg1;
+
+ /* 0x148 : mm_berr_cfg2 */
+ union {
+ struct {
+ uint32_t sts_berr_src : 3; /* [ 2: 0], r, 0x0 */
+ uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
+ uint32_t sts_berr_id : 4; /* [11: 8], r, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t sts_codec_berr_src : 3; /* [18:16], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t sts_codec_berr_id : 1; /* [ 24], r, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg2;
+
+ /* 0x14C : mm_berr_cfg3 */
+ union {
+ struct {
+ uint32_t sts_mmcpu_berr_src : 1; /* [ 0], r, 0x0 */
+ uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
+ uint32_t sts_mmcpu_berr_id : 4; /* [11: 8], r, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t sts_mminfra_berr_src : 5; /* [20:16], r, 0x0 */
+ uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
+ uint32_t sts_mminfra_berr_id : 6; /* [29:24], r, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg3;
+
+ /* 0x150 : mm_berr_cfg4 */
+ union {
+ struct {
+ uint32_t sts_berr_addr : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg4;
+
+ /* 0x154 : mm_berr_cfg5 */
+ union {
+ struct {
+ uint32_t sts_codec_berr_addr : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg5;
+
+ /* 0x158 : mm_berr_cfg6 */
+ union {
+ struct {
+ uint32_t sts_mmcpu_berr_addr : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg6;
+
+ /* 0x15C : mm_berr_cfg7 */
+ union {
+ struct {
+ uint32_t sts_mminfra_berr_addr : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } mm_berr_cfg7;
+};
+
+typedef volatile struct mm_misc_reg mm_misc_reg_t;
+
+#endif /* __MM_MISC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/pds_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/pds_reg.h
new file mode 100644
index 00000000..c69a2a5b
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/pds_reg.h
@@ -0,0 +1,2628 @@
+/**
+ ******************************************************************************
+ * @file pds_reg.h
+ * @version V1.0
+ * @date 2021-09-10
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __PDS_REG_H__
+#define __PDS_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : PDS_CTL */
+#define PDS_CTL_OFFSET (0x0)
+#define PDS_START_PS PDS_START_PS
+#define PDS_START_PS_POS (0U)
+#define PDS_START_PS_LEN (1U)
+#define PDS_START_PS_MSK (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
+#define PDS_START_PS_UMSK (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
+#define PDS_CR_SLEEP_FOREVER PDS_CR_SLEEP_FOREVER
+#define PDS_CR_SLEEP_FOREVER_POS (1U)
+#define PDS_CR_SLEEP_FOREVER_LEN (1U)
+#define PDS_CR_SLEEP_FOREVER_MSK (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
+#define PDS_CR_SLEEP_FOREVER_UMSK (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
+#define PDS_CR_XTAL_FORCE_OFF PDS_CR_XTAL_FORCE_OFF
+#define PDS_CR_XTAL_FORCE_OFF_POS (2U)
+#define PDS_CR_XTAL_FORCE_OFF_LEN (1U)
+#define PDS_CR_XTAL_FORCE_OFF_MSK (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
+#define PDS_CR_XTAL_FORCE_OFF_UMSK (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
+#define PDS_CR_PDS_WIFI_SAVE_STATE PDS_CR_PDS_WIFI_SAVE_STATE
+#define PDS_CR_PDS_WIFI_SAVE_STATE_POS (3U)
+#define PDS_CR_PDS_WIFI_SAVE_STATE_LEN (1U)
+#define PDS_CR_PDS_WIFI_SAVE_STATE_MSK (((1U << PDS_CR_PDS_WIFI_SAVE_STATE_LEN) - 1) << PDS_CR_PDS_WIFI_SAVE_STATE_POS)
+#define PDS_CR_PDS_WIFI_SAVE_STATE_UMSK (~(((1U << PDS_CR_PDS_WIFI_SAVE_STATE_LEN) - 1) << PDS_CR_PDS_WIFI_SAVE_STATE_POS))
+#define PDS_CR_PDS_PD_DCDC11 PDS_CR_PDS_PD_DCDC11
+#define PDS_CR_PDS_PD_DCDC11_POS (4U)
+#define PDS_CR_PDS_PD_DCDC11_LEN (1U)
+#define PDS_CR_PDS_PD_DCDC11_MSK (((1U << PDS_CR_PDS_PD_DCDC11_LEN) - 1) << PDS_CR_PDS_PD_DCDC11_POS)
+#define PDS_CR_PDS_PD_DCDC11_UMSK (~(((1U << PDS_CR_PDS_PD_DCDC11_LEN) - 1) << PDS_CR_PDS_PD_DCDC11_POS))
+#define PDS_CR_PDS_PD_BG_SYS PDS_CR_PDS_PD_BG_SYS
+#define PDS_CR_PDS_PD_BG_SYS_POS (5U)
+#define PDS_CR_PDS_PD_BG_SYS_LEN (1U)
+#define PDS_CR_PDS_PD_BG_SYS_MSK (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
+#define PDS_CR_PDS_PD_BG_SYS_UMSK (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD PDS_CR_PDS_CTRL_GPIO_IE_PU_PD
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS (6U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN (1U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS))
+#define PDS_CR_PDS_PD_DCDC18 PDS_CR_PDS_PD_DCDC18
+#define PDS_CR_PDS_PD_DCDC18_POS (7U)
+#define PDS_CR_PDS_PD_DCDC18_LEN (1U)
+#define PDS_CR_PDS_PD_DCDC18_MSK (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
+#define PDS_CR_PDS_PD_DCDC18_UMSK (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
+#define PDS_CR_PDS_GATE_CLK PDS_CR_PDS_GATE_CLK
+#define PDS_CR_PDS_GATE_CLK_POS (8U)
+#define PDS_CR_PDS_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_GATE_CLK_MSK (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
+#define PDS_CR_PDS_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
+#define PDS_CR_PDS_MEM_STBY PDS_CR_PDS_MEM_STBY
+#define PDS_CR_PDS_MEM_STBY_POS (9U)
+#define PDS_CR_PDS_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_MEM_STBY_MSK (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
+#define PDS_CR_PDS_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT PDS_CR_PDS_GLB_REG_RESET_PROTECT
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS (10U)
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN (1U)
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_MSK (((1U << PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN) - 1) << PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS)
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_UMSK (~(((1U << PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN) - 1) << PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS))
+#define PDS_CR_PDS_ISO_EN PDS_CR_PDS_ISO_EN
+#define PDS_CR_PDS_ISO_EN_POS (11U)
+#define PDS_CR_PDS_ISO_EN_LEN (1U)
+#define PDS_CR_PDS_ISO_EN_MSK (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
+#define PDS_CR_PDS_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
+#define PDS_CR_PDS_WAIT_XTAL_RDY PDS_CR_PDS_WAIT_XTAL_RDY
+#define PDS_CR_PDS_WAIT_XTAL_RDY_POS (12U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN (1U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
+#define PDS_CR_PDS_PWR_OFF PDS_CR_PDS_PWR_OFF
+#define PDS_CR_PDS_PWR_OFF_POS (13U)
+#define PDS_CR_PDS_PWR_OFF_LEN (1U)
+#define PDS_CR_PDS_PWR_OFF_MSK (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
+#define PDS_CR_PDS_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
+#define PDS_CR_PDS_PD_XTAL PDS_CR_PDS_PD_XTAL
+#define PDS_CR_PDS_PD_XTAL_POS (14U)
+#define PDS_CR_PDS_PD_XTAL_LEN (1U)
+#define PDS_CR_PDS_PD_XTAL_MSK (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
+#define PDS_CR_PDS_PD_XTAL_UMSK (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
+#define PDS_CR_PDS_CTRL_SOC_ENB PDS_CR_PDS_CTRL_SOC_ENB
+#define PDS_CR_PDS_CTRL_SOC_ENB_POS (15U)
+#define PDS_CR_PDS_CTRL_SOC_ENB_LEN (1U)
+#define PDS_CR_PDS_CTRL_SOC_ENB_MSK (((1U << PDS_CR_PDS_CTRL_SOC_ENB_LEN) - 1) << PDS_CR_PDS_CTRL_SOC_ENB_POS)
+#define PDS_CR_PDS_CTRL_SOC_ENB_UMSK (~(((1U << PDS_CR_PDS_CTRL_SOC_ENB_LEN) - 1) << PDS_CR_PDS_CTRL_SOC_ENB_POS))
+#define PDS_CR_PDS_RST_SOC PDS_CR_PDS_RST_SOC
+#define PDS_CR_PDS_RST_SOC_POS (16U)
+#define PDS_CR_PDS_RST_SOC_LEN (1U)
+#define PDS_CR_PDS_RST_SOC_MSK (((1U << PDS_CR_PDS_RST_SOC_LEN) - 1) << PDS_CR_PDS_RST_SOC_POS)
+#define PDS_CR_PDS_RST_SOC_UMSK (~(((1U << PDS_CR_PDS_RST_SOC_LEN) - 1) << PDS_CR_PDS_RST_SOC_POS))
+#define PDS_CR_PDS_RC32M_OFF_DIS PDS_CR_PDS_RC32M_OFF_DIS
+#define PDS_CR_PDS_RC32M_OFF_DIS_POS (17U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_LEN (1U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_MSK (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
+#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
+#define PDS_CR_PDS_DCDC11_VSEL_EN PDS_CR_PDS_DCDC11_VSEL_EN
+#define PDS_CR_PDS_DCDC11_VSEL_EN_POS (18U)
+#define PDS_CR_PDS_DCDC11_VSEL_EN_LEN (1U)
+#define PDS_CR_PDS_DCDC11_VSEL_EN_MSK (((1U << PDS_CR_PDS_DCDC11_VSEL_EN_LEN) - 1) << PDS_CR_PDS_DCDC11_VSEL_EN_POS)
+#define PDS_CR_PDS_DCDC11_VSEL_EN_UMSK (~(((1U << PDS_CR_PDS_DCDC11_VSEL_EN_LEN) - 1) << PDS_CR_PDS_DCDC11_VSEL_EN_POS))
+#define PDS_CR_PDS_CTRL_USBPLL_PD PDS_CR_PDS_CTRL_USBPLL_PD
+#define PDS_CR_PDS_CTRL_USBPLL_PD_POS (19U)
+#define PDS_CR_PDS_CTRL_USBPLL_PD_LEN (1U)
+#define PDS_CR_PDS_CTRL_USBPLL_PD_MSK (((1U << PDS_CR_PDS_CTRL_USBPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_USBPLL_PD_POS)
+#define PDS_CR_PDS_CTRL_USBPLL_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_USBPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_USBPLL_PD_POS))
+#define PDS_CR_PDS_CTRL_AUPLL_PD PDS_CR_PDS_CTRL_AUPLL_PD
+#define PDS_CR_PDS_CTRL_AUPLL_PD_POS (20U)
+#define PDS_CR_PDS_CTRL_AUPLL_PD_LEN (1U)
+#define PDS_CR_PDS_CTRL_AUPLL_PD_MSK (((1U << PDS_CR_PDS_CTRL_AUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_AUPLL_PD_POS)
+#define PDS_CR_PDS_CTRL_AUPLL_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_AUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_AUPLL_PD_POS))
+#define PDS_CR_PDS_CTRL_CPUPLL_PD PDS_CR_PDS_CTRL_CPUPLL_PD
+#define PDS_CR_PDS_CTRL_CPUPLL_PD_POS (21U)
+#define PDS_CR_PDS_CTRL_CPUPLL_PD_LEN (1U)
+#define PDS_CR_PDS_CTRL_CPUPLL_PD_MSK (((1U << PDS_CR_PDS_CTRL_CPUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_CPUPLL_PD_POS)
+#define PDS_CR_PDS_CTRL_CPUPLL_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_CPUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_CPUPLL_PD_POS))
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD PDS_CR_PDS_CTRL_WIFIPLL_PD
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_POS (22U)
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN (1U)
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_MSK (((1U << PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_WIFIPLL_PD_POS)
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_WIFIPLL_PD_POS))
+#define PDS_CR_PDS_DCDC11_VOL PDS_CR_PDS_DCDC11_VOL
+#define PDS_CR_PDS_DCDC11_VOL_POS (23U)
+#define PDS_CR_PDS_DCDC11_VOL_LEN (5U)
+#define PDS_CR_PDS_DCDC11_VOL_MSK (((1U << PDS_CR_PDS_DCDC11_VOL_LEN) - 1) << PDS_CR_PDS_DCDC11_VOL_POS)
+#define PDS_CR_PDS_DCDC11_VOL_UMSK (~(((1U << PDS_CR_PDS_DCDC11_VOL_LEN) - 1) << PDS_CR_PDS_DCDC11_VOL_POS))
+#define PDS_CR_PDS_CTRL_RF PDS_CR_PDS_CTRL_RF
+#define PDS_CR_PDS_CTRL_RF_POS (28U)
+#define PDS_CR_PDS_CTRL_RF_LEN (2U)
+#define PDS_CR_PDS_CTRL_RF_MSK (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
+#define PDS_CR_PDS_CTRL_RF_UMSK (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP PDS_CR_PDS_START_USE_TBTT_SLEEP
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_POS (30U)
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN (1U)
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_MSK (((1U << PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN) - 1) << PDS_CR_PDS_START_USE_TBTT_SLEEP_POS)
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_UMSK (~(((1U << PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN) - 1) << PDS_CR_PDS_START_USE_TBTT_SLEEP_POS))
+#define PDS_CR_PDS_GPIO_ISO_MODE PDS_CR_PDS_GPIO_ISO_MODE
+#define PDS_CR_PDS_GPIO_ISO_MODE_POS (31U)
+#define PDS_CR_PDS_GPIO_ISO_MODE_LEN (1U)
+#define PDS_CR_PDS_GPIO_ISO_MODE_MSK (((1U << PDS_CR_PDS_GPIO_ISO_MODE_LEN) - 1) << PDS_CR_PDS_GPIO_ISO_MODE_POS)
+#define PDS_CR_PDS_GPIO_ISO_MODE_UMSK (~(((1U << PDS_CR_PDS_GPIO_ISO_MODE_LEN) - 1) << PDS_CR_PDS_GPIO_ISO_MODE_POS))
+
+/* 0x4 : PDS_TIME1 */
+#define PDS_TIME1_OFFSET (0x4)
+#define PDS_CR_SLEEP_DURATION PDS_CR_SLEEP_DURATION
+#define PDS_CR_SLEEP_DURATION_POS (0U)
+#define PDS_CR_SLEEP_DURATION_LEN (32U)
+#define PDS_CR_SLEEP_DURATION_MSK (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
+#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))
+
+/* 0xC : PDS_INT */
+#define PDS_INT_OFFSET (0xC)
+#define PDS_RO_PDS_WAKE_INT PDS_RO_PDS_WAKE_INT
+#define PDS_RO_PDS_WAKE_INT_POS (0U)
+#define PDS_RO_PDS_WAKE_INT_LEN (1U)
+#define PDS_RO_PDS_WAKE_INT_MSK (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
+#define PDS_RO_PDS_WAKE_INT_UMSK (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
+#define PDS_RO_PDS_RF_DONE_INT PDS_RO_PDS_RF_DONE_INT
+#define PDS_RO_PDS_RF_DONE_INT_POS (1U)
+#define PDS_RO_PDS_RF_DONE_INT_LEN (1U)
+#define PDS_RO_PDS_RF_DONE_INT_MSK (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
+#define PDS_RO_PDS_RF_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS (2U)
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN (1U)
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_MSK (((1U << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS)
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_UMSK (~(((1U << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS))
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS (3U)
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN (1U)
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_MSK (((1U << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS)
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_UMSK (~(((1U << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS))
+#define PDS_CR_PDS_WAKE_INT_MASK PDS_CR_PDS_WAKE_INT_MASK
+#define PDS_CR_PDS_WAKE_INT_MASK_POS (4U)
+#define PDS_CR_PDS_WAKE_INT_MASK_LEN (1U)
+#define PDS_CR_PDS_WAKE_INT_MASK_MSK (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
+#define PDS_CR_PDS_WAKE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
+#define PDS_CR_PDS_RF_DONE_INT_MASK PDS_CR_PDS_RF_DONE_INT_MASK
+#define PDS_CR_PDS_RF_DONE_INT_MASK_POS (5U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN (1U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS (6U)
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN (1U)
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_MSK (((1U << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS)
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_UMSK (~(((1U << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS))
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS (7U)
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN (1U)
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_MSK (((1U << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS)
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_UMSK (~(((1U << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS))
+#define PDS_CR_PDS_INT_CLR PDS_CR_PDS_INT_CLR
+#define PDS_CR_PDS_INT_CLR_POS (8U)
+#define PDS_CR_PDS_INT_CLR_LEN (1U)
+#define PDS_CR_PDS_INT_CLR_MSK (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
+#define PDS_CR_PDS_INT_CLR_UMSK (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
+#define PDS_CR_PDS_WAKEUP_SRC_EN PDS_CR_PDS_WAKEUP_SRC_EN
+#define PDS_CR_PDS_WAKEUP_SRC_EN_POS (10U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN (11U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS))
+#define PDS_RO_PDS_WAKEUP_EVENT PDS_RO_PDS_WAKEUP_EVENT
+#define PDS_RO_PDS_WAKEUP_EVENT_POS (21U)
+#define PDS_RO_PDS_WAKEUP_EVENT_LEN (11U)
+#define PDS_RO_PDS_WAKEUP_EVENT_MSK (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)
+#define PDS_RO_PDS_WAKEUP_EVENT_UMSK (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS))
+
+/* 0x10 : PDS_CTL2 */
+#define PDS_CTL2_OFFSET (0x10)
+#define PDS_CR_PDS_FORCE_MM_PWR_OFF PDS_CR_PDS_FORCE_MM_PWR_OFF
+#define PDS_CR_PDS_FORCE_MM_PWR_OFF_POS (1U)
+#define PDS_CR_PDS_FORCE_MM_PWR_OFF_LEN (1U)
+#define PDS_CR_PDS_FORCE_MM_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_MM_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MM_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_MM_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_MM_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MM_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF PDS_CR_PDS_FORCE_USB_PWR_OFF
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS (3U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN (1U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_MM_ISO_EN PDS_CR_PDS_FORCE_MM_ISO_EN
+#define PDS_CR_PDS_FORCE_MM_ISO_EN_POS (5U)
+#define PDS_CR_PDS_FORCE_MM_ISO_EN_LEN (1U)
+#define PDS_CR_PDS_FORCE_MM_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_MM_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MM_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_MM_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_MM_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MM_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_USB_ISO_EN PDS_CR_PDS_FORCE_USB_ISO_EN
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS (7U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN (1U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_NP_PDS_RST PDS_CR_PDS_FORCE_NP_PDS_RST
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS (8U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN (1U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_MM_PDS_RST PDS_CR_PDS_FORCE_MM_PDS_RST
+#define PDS_CR_PDS_FORCE_MM_PDS_RST_POS (9U)
+#define PDS_CR_PDS_FORCE_MM_PDS_RST_LEN (1U)
+#define PDS_CR_PDS_FORCE_MM_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_MM_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MM_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_MM_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_MM_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MM_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_WB_PDS_RST PDS_CR_PDS_FORCE_WB_PDS_RST
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_POS (10U)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_LEN (1U)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_USB_PDS_RST PDS_CR_PDS_FORCE_USB_PDS_RST
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS (11U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN (1U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY PDS_CR_PDS_FORCE_NP_MEM_STBY
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS (12U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_MM_MEM_STBY PDS_CR_PDS_FORCE_MM_MEM_STBY
+#define PDS_CR_PDS_FORCE_MM_MEM_STBY_POS (13U)
+#define PDS_CR_PDS_FORCE_MM_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_FORCE_MM_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_MM_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MM_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_MM_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MM_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MM_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY PDS_CR_PDS_FORCE_WB_MEM_STBY
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_POS (14U)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY PDS_CR_PDS_FORCE_USB_MEM_STBY
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS (15U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK PDS_CR_PDS_FORCE_NP_GATE_CLK
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS (16U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_MM_GATE_CLK PDS_CR_PDS_FORCE_MM_GATE_CLK
+#define PDS_CR_PDS_FORCE_MM_GATE_CLK_POS (17U)
+#define PDS_CR_PDS_FORCE_MM_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_FORCE_MM_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_MM_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MM_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_MM_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MM_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MM_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK PDS_CR_PDS_FORCE_WB_GATE_CLK
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_POS (18U)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK PDS_CR_PDS_FORCE_USB_GATE_CLK
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS (19U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS))
+
+/* 0x14 : PDS_CTL3 */
+#define PDS_CTL3_OFFSET (0x14)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF PDS_CR_PDS_FORCE_MISC_PWR_OFF
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN PDS_CR_PDS_FORCE_MISC_ISO_EN
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_POS (4U)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN (1U)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST PDS_CR_PDS_FORCE_MISC_PDS_RST
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS (7U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN (1U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY PDS_CR_PDS_FORCE_MISC_MEM_STBY
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS (10U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK PDS_CR_PDS_FORCE_MISC_GATE_CLK
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS (13U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
+#define PDS_CR_PDS_MM_ISO_EN PDS_CR_PDS_MM_ISO_EN
+#define PDS_CR_PDS_MM_ISO_EN_POS (26U)
+#define PDS_CR_PDS_MM_ISO_EN_LEN (1U)
+#define PDS_CR_PDS_MM_ISO_EN_MSK (((1U << PDS_CR_PDS_MM_ISO_EN_LEN) - 1) << PDS_CR_PDS_MM_ISO_EN_POS)
+#define PDS_CR_PDS_MM_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_MM_ISO_EN_LEN) - 1) << PDS_CR_PDS_MM_ISO_EN_POS))
+#define PDS_CR_PDS_USB_ISO_EN PDS_CR_PDS_USB_ISO_EN
+#define PDS_CR_PDS_USB_ISO_EN_POS (29U)
+#define PDS_CR_PDS_USB_ISO_EN_LEN (1U)
+#define PDS_CR_PDS_USB_ISO_EN_MSK (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)
+#define PDS_CR_PDS_USB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS))
+#define PDS_CR_PDS_MISC_ISO_EN PDS_CR_PDS_MISC_ISO_EN
+#define PDS_CR_PDS_MISC_ISO_EN_POS (30U)
+#define PDS_CR_PDS_MISC_ISO_EN_LEN (1U)
+#define PDS_CR_PDS_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))
+
+/* 0x18 : PDS_CTL4 */
+#define PDS_CTL4_OFFSET (0x18)
+#define PDS_CR_PDS_NP_RESET PDS_CR_PDS_NP_RESET
+#define PDS_CR_PDS_NP_RESET_POS (1U)
+#define PDS_CR_PDS_NP_RESET_LEN (1U)
+#define PDS_CR_PDS_NP_RESET_MSK (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
+#define PDS_CR_PDS_NP_RESET_UMSK (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
+#define PDS_CR_PDS_NP_MEM_STBY PDS_CR_PDS_NP_MEM_STBY
+#define PDS_CR_PDS_NP_MEM_STBY_POS (2U)
+#define PDS_CR_PDS_NP_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_NP_GATE_CLK PDS_CR_PDS_NP_GATE_CLK
+#define PDS_CR_PDS_NP_GATE_CLK_POS (3U)
+#define PDS_CR_PDS_NP_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_MM_PWR_OFF PDS_CR_PDS_MM_PWR_OFF
+#define PDS_CR_PDS_MM_PWR_OFF_POS (8U)
+#define PDS_CR_PDS_MM_PWR_OFF_LEN (1U)
+#define PDS_CR_PDS_MM_PWR_OFF_MSK (((1U << PDS_CR_PDS_MM_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MM_PWR_OFF_POS)
+#define PDS_CR_PDS_MM_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MM_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MM_PWR_OFF_POS))
+#define PDS_CR_PDS_MM_RESET PDS_CR_PDS_MM_RESET
+#define PDS_CR_PDS_MM_RESET_POS (9U)
+#define PDS_CR_PDS_MM_RESET_LEN (1U)
+#define PDS_CR_PDS_MM_RESET_MSK (((1U << PDS_CR_PDS_MM_RESET_LEN) - 1) << PDS_CR_PDS_MM_RESET_POS)
+#define PDS_CR_PDS_MM_RESET_UMSK (~(((1U << PDS_CR_PDS_MM_RESET_LEN) - 1) << PDS_CR_PDS_MM_RESET_POS))
+#define PDS_CR_PDS_MM_MEM_STBY PDS_CR_PDS_MM_MEM_STBY
+#define PDS_CR_PDS_MM_MEM_STBY_POS (10U)
+#define PDS_CR_PDS_MM_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_MM_MEM_STBY_MSK (((1U << PDS_CR_PDS_MM_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MM_MEM_STBY_POS)
+#define PDS_CR_PDS_MM_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MM_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MM_MEM_STBY_POS))
+#define PDS_CR_PDS_MM_GATE_CLK PDS_CR_PDS_MM_GATE_CLK
+#define PDS_CR_PDS_MM_GATE_CLK_POS (11U)
+#define PDS_CR_PDS_MM_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_MM_GATE_CLK_MSK (((1U << PDS_CR_PDS_MM_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MM_GATE_CLK_POS)
+#define PDS_CR_PDS_MM_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MM_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MM_GATE_CLK_POS))
+#define PDS_CR_PDS_WB_RESET PDS_CR_PDS_WB_RESET
+#define PDS_CR_PDS_WB_RESET_POS (13U)
+#define PDS_CR_PDS_WB_RESET_LEN (1U)
+#define PDS_CR_PDS_WB_RESET_MSK (((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS)
+#define PDS_CR_PDS_WB_RESET_UMSK (~(((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS))
+#define PDS_CR_PDS_WB_MEM_STBY PDS_CR_PDS_WB_MEM_STBY
+#define PDS_CR_PDS_WB_MEM_STBY_POS (14U)
+#define PDS_CR_PDS_WB_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_WB_MEM_STBY_MSK (((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS)
+#define PDS_CR_PDS_WB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS))
+#define PDS_CR_PDS_WB_GATE_CLK PDS_CR_PDS_WB_GATE_CLK
+#define PDS_CR_PDS_WB_GATE_CLK_POS (15U)
+#define PDS_CR_PDS_WB_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_WB_GATE_CLK_MSK (((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS)
+#define PDS_CR_PDS_WB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS))
+#define PDS_CR_PDS_USB_PWR_OFF PDS_CR_PDS_USB_PWR_OFF
+#define PDS_CR_PDS_USB_PWR_OFF_POS (20U)
+#define PDS_CR_PDS_USB_PWR_OFF_LEN (1U)
+#define PDS_CR_PDS_USB_PWR_OFF_MSK (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_USB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_USB_RESET PDS_CR_PDS_USB_RESET
+#define PDS_CR_PDS_USB_RESET_POS (21U)
+#define PDS_CR_PDS_USB_RESET_LEN (1U)
+#define PDS_CR_PDS_USB_RESET_MSK (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)
+#define PDS_CR_PDS_USB_RESET_UMSK (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS))
+#define PDS_CR_PDS_USB_MEM_STBY PDS_CR_PDS_USB_MEM_STBY
+#define PDS_CR_PDS_USB_MEM_STBY_POS (22U)
+#define PDS_CR_PDS_USB_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_USB_MEM_STBY_MSK (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_USB_GATE_CLK PDS_CR_PDS_USB_GATE_CLK
+#define PDS_CR_PDS_USB_GATE_CLK_POS (23U)
+#define PDS_CR_PDS_USB_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_USB_GATE_CLK_MSK (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS))
+#define PDS_CR_PDS_MISC_PWR_OFF PDS_CR_PDS_MISC_PWR_OFF
+#define PDS_CR_PDS_MISC_PWR_OFF_POS (24U)
+#define PDS_CR_PDS_MISC_PWR_OFF_LEN (1U)
+#define PDS_CR_PDS_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_MISC_RESET PDS_CR_PDS_MISC_RESET
+#define PDS_CR_PDS_MISC_RESET_POS (25U)
+#define PDS_CR_PDS_MISC_RESET_LEN (1U)
+#define PDS_CR_PDS_MISC_RESET_MSK (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
+#define PDS_CR_PDS_MISC_RESET_UMSK (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
+#define PDS_CR_PDS_MISC_MEM_STBY PDS_CR_PDS_MISC_MEM_STBY
+#define PDS_CR_PDS_MISC_MEM_STBY_POS (26U)
+#define PDS_CR_PDS_MISC_MEM_STBY_LEN (1U)
+#define PDS_CR_PDS_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_MISC_GATE_CLK PDS_CR_PDS_MISC_GATE_CLK
+#define PDS_CR_PDS_MISC_GATE_CLK_POS (27U)
+#define PDS_CR_PDS_MISC_GATE_CLK_LEN (1U)
+#define PDS_CR_PDS_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))
+
+/* 0x1C : pds_stat */
+#define PDS_STAT_OFFSET (0x1C)
+#define PDS_RO_PDS_STATE PDS_RO_PDS_STATE
+#define PDS_RO_PDS_STATE_POS (0U)
+#define PDS_RO_PDS_STATE_LEN (5U)
+#define PDS_RO_PDS_STATE_MSK (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
+#define PDS_RO_PDS_STATE_UMSK (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
+#define PDS_RO_PDS_RF_STATE PDS_RO_PDS_RF_STATE
+#define PDS_RO_PDS_RF_STATE_POS (8U)
+#define PDS_RO_PDS_RF_STATE_LEN (5U)
+#define PDS_RO_PDS_RF_STATE_MSK (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
+#define PDS_RO_PDS_RF_STATE_UMSK (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
+#define PDS_RESET_EVENT PDS_RESET_EVENT
+#define PDS_RESET_EVENT_POS (24U)
+#define PDS_RESET_EVENT_LEN (3U)
+#define PDS_RESET_EVENT_MSK (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)
+#define PDS_RESET_EVENT_UMSK (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS))
+#define PDS_CLR_RESET_EVENT PDS_CLR_RESET_EVENT
+#define PDS_CLR_RESET_EVENT_POS (31U)
+#define PDS_CLR_RESET_EVENT_LEN (1U)
+#define PDS_CLR_RESET_EVENT_MSK (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)
+#define PDS_CLR_RESET_EVENT_UMSK (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS))
+
+/* 0x20 : pds_ram1 */
+#define PDS_RAM1_OFFSET (0x20)
+#define PDS_CR_OCRAM_SLP PDS_CR_OCRAM_SLP
+#define PDS_CR_OCRAM_SLP_POS (0U)
+#define PDS_CR_OCRAM_SLP_LEN (4U)
+#define PDS_CR_OCRAM_SLP_MSK (((1U << PDS_CR_OCRAM_SLP_LEN) - 1) << PDS_CR_OCRAM_SLP_POS)
+#define PDS_CR_OCRAM_SLP_UMSK (~(((1U << PDS_CR_OCRAM_SLP_LEN) - 1) << PDS_CR_OCRAM_SLP_POS))
+#define PDS_CR_OCRAM_RET PDS_CR_OCRAM_RET
+#define PDS_CR_OCRAM_RET_POS (4U)
+#define PDS_CR_OCRAM_RET_LEN (4U)
+#define PDS_CR_OCRAM_RET_MSK (((1U << PDS_CR_OCRAM_RET_LEN) - 1) << PDS_CR_OCRAM_RET_POS)
+#define PDS_CR_OCRAM_RET_UMSK (~(((1U << PDS_CR_OCRAM_RET_LEN) - 1) << PDS_CR_OCRAM_RET_POS))
+#define PDS_CR_PDS_RAM_CLK_CNT PDS_CR_PDS_RAM_CLK_CNT
+#define PDS_CR_PDS_RAM_CLK_CNT_POS (8U)
+#define PDS_CR_PDS_RAM_CLK_CNT_LEN (6U)
+#define PDS_CR_PDS_RAM_CLK_CNT_MSK (((1U << PDS_CR_PDS_RAM_CLK_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK_CNT_POS)
+#define PDS_CR_PDS_RAM_CLK_CNT_UMSK (~(((1U << PDS_CR_PDS_RAM_CLK_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK_CNT_POS))
+#define PDS_CR_PDS_RAM_CLK2_CNT PDS_CR_PDS_RAM_CLK2_CNT
+#define PDS_CR_PDS_RAM_CLK2_CNT_POS (16U)
+#define PDS_CR_PDS_RAM_CLK2_CNT_LEN (6U)
+#define PDS_CR_PDS_RAM_CLK2_CNT_MSK (((1U << PDS_CR_PDS_RAM_CLK2_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK2_CNT_POS)
+#define PDS_CR_PDS_RAM_CLK2_CNT_UMSK (~(((1U << PDS_CR_PDS_RAM_CLK2_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK2_CNT_POS))
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK PDS_CR_PDS_CTRL_NP_RAM_CLK
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_POS (24U)
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN (1U)
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_MSK (((1U << PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_NP_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_NP_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_MM_RAM_CLK PDS_CR_PDS_CTRL_MM_RAM_CLK
+#define PDS_CR_PDS_CTRL_MM_RAM_CLK_POS (25U)
+#define PDS_CR_PDS_CTRL_MM_RAM_CLK_LEN (1U)
+#define PDS_CR_PDS_CTRL_MM_RAM_CLK_MSK (((1U << PDS_CR_PDS_CTRL_MM_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MM_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_MM_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_MM_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MM_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK PDS_CR_PDS_CTRL_WB_RAM_CLK
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_POS (26U)
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN (1U)
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_MSK (((1U << PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_WB_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_WB_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK PDS_CR_PDS_CTRL_USB_RAM_CLK
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_POS (27U)
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN (1U)
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_MSK (((1U << PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_USB_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_USB_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK PDS_CR_PDS_CTRL_MISC_RAM_CLK
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS (28U)
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN (1U)
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_MSK (((1U << PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_RAM_CLK2 PDS_CR_PDS_CTRL_RAM_CLK2
+#define PDS_CR_PDS_CTRL_RAM_CLK2_POS (30U)
+#define PDS_CR_PDS_CTRL_RAM_CLK2_LEN (1U)
+#define PDS_CR_PDS_CTRL_RAM_CLK2_MSK (((1U << PDS_CR_PDS_CTRL_RAM_CLK2_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK2_POS)
+#define PDS_CR_PDS_CTRL_RAM_CLK2_UMSK (~(((1U << PDS_CR_PDS_CTRL_RAM_CLK2_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK2_POS))
+#define PDS_CR_PDS_CTRL_RAM_CLK PDS_CR_PDS_CTRL_RAM_CLK
+#define PDS_CR_PDS_CTRL_RAM_CLK_POS (31U)
+#define PDS_CR_PDS_CTRL_RAM_CLK_LEN (1U)
+#define PDS_CR_PDS_CTRL_RAM_CLK_MSK (((1U << PDS_CR_PDS_CTRL_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK_POS))
+
+/* 0x24 : PDS_CTL5 */
+#define PDS_CTL5_OFFSET (0x24)
+#define PDS_CR_NP_WFI_MASK PDS_CR_NP_WFI_MASK
+#define PDS_CR_NP_WFI_MASK_POS (0U)
+#define PDS_CR_NP_WFI_MASK_LEN (1U)
+#define PDS_CR_NP_WFI_MASK_MSK (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
+#define PDS_CR_NP_WFI_MASK_UMSK (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
+#define PDS_CR_MM_WFI_MASK PDS_CR_MM_WFI_MASK
+#define PDS_CR_MM_WFI_MASK_POS (2U)
+#define PDS_CR_MM_WFI_MASK_LEN (1U)
+#define PDS_CR_MM_WFI_MASK_MSK (((1U << PDS_CR_MM_WFI_MASK_LEN) - 1) << PDS_CR_MM_WFI_MASK_POS)
+#define PDS_CR_MM_WFI_MASK_UMSK (~(((1U << PDS_CR_MM_WFI_MASK_LEN) - 1) << PDS_CR_MM_WFI_MASK_POS))
+#define PDS_CR_PICO_WFI_MASK PDS_CR_PICO_WFI_MASK
+#define PDS_CR_PICO_WFI_MASK_POS (4U)
+#define PDS_CR_PICO_WFI_MASK_LEN (1U)
+#define PDS_CR_PICO_WFI_MASK_MSK (((1U << PDS_CR_PICO_WFI_MASK_LEN) - 1) << PDS_CR_PICO_WFI_MASK_POS)
+#define PDS_CR_PICO_WFI_MASK_UMSK (~(((1U << PDS_CR_PICO_WFI_MASK_LEN) - 1) << PDS_CR_PICO_WFI_MASK_POS))
+#define PDS_CR_PDS_CTRL_USB33 PDS_CR_PDS_CTRL_USB33
+#define PDS_CR_PDS_CTRL_USB33_POS (8U)
+#define PDS_CR_PDS_CTRL_USB33_LEN (1U)
+#define PDS_CR_PDS_CTRL_USB33_MSK (((1U << PDS_CR_PDS_CTRL_USB33_LEN) - 1) << PDS_CR_PDS_CTRL_USB33_POS)
+#define PDS_CR_PDS_CTRL_USB33_UMSK (~(((1U << PDS_CR_PDS_CTRL_USB33_LEN) - 1) << PDS_CR_PDS_CTRL_USB33_POS))
+#define PDS_CR_PDS_PD_LDO18IO PDS_CR_PDS_PD_LDO18IO
+#define PDS_CR_PDS_PD_LDO18IO_POS (9U)
+#define PDS_CR_PDS_PD_LDO18IO_LEN (1U)
+#define PDS_CR_PDS_PD_LDO18IO_MSK (((1U << PDS_CR_PDS_PD_LDO18IO_LEN) - 1) << PDS_CR_PDS_PD_LDO18IO_POS)
+#define PDS_CR_PDS_PD_LDO18IO_UMSK (~(((1U << PDS_CR_PDS_PD_LDO18IO_LEN) - 1) << PDS_CR_PDS_PD_LDO18IO_POS))
+#define PDS_CR_PDS_GPIO_KEEP_EN PDS_CR_PDS_GPIO_KEEP_EN
+#define PDS_CR_PDS_GPIO_KEEP_EN_POS (16U)
+#define PDS_CR_PDS_GPIO_KEEP_EN_LEN (3U)
+#define PDS_CR_PDS_GPIO_KEEP_EN_MSK (((1U << PDS_CR_PDS_GPIO_KEEP_EN_LEN) - 1) << PDS_CR_PDS_GPIO_KEEP_EN_POS)
+#define PDS_CR_PDS_GPIO_KEEP_EN_UMSK (~(((1U << PDS_CR_PDS_GPIO_KEEP_EN_LEN) - 1) << PDS_CR_PDS_GPIO_KEEP_EN_POS))
+
+/* 0x28 : PDS_RAM2 */
+#define PDS_RAM2_OFFSET (0x28)
+#define PDS_CR_WRAM_SLP PDS_CR_WRAM_SLP
+#define PDS_CR_WRAM_SLP_POS (0U)
+#define PDS_CR_WRAM_SLP_LEN (10U)
+#define PDS_CR_WRAM_SLP_MSK (((1U << PDS_CR_WRAM_SLP_LEN) - 1) << PDS_CR_WRAM_SLP_POS)
+#define PDS_CR_WRAM_SLP_UMSK (~(((1U << PDS_CR_WRAM_SLP_LEN) - 1) << PDS_CR_WRAM_SLP_POS))
+#define PDS_CR_WRAM_RET PDS_CR_WRAM_RET
+#define PDS_CR_WRAM_RET_POS (10U)
+#define PDS_CR_WRAM_RET_LEN (10U)
+#define PDS_CR_WRAM_RET_MSK (((1U << PDS_CR_WRAM_RET_LEN) - 1) << PDS_CR_WRAM_RET_POS)
+#define PDS_CR_WRAM_RET_UMSK (~(((1U << PDS_CR_WRAM_RET_LEN) - 1) << PDS_CR_WRAM_RET_POS))
+
+/* 0x30 : pds_gpio_i_set */
+#define PDS_GPIO_I_SET_OFFSET (0x30)
+#define PDS_CR_PDS_GPIO_IE_SET PDS_CR_PDS_GPIO_IE_SET
+#define PDS_CR_PDS_GPIO_IE_SET_POS (0U)
+#define PDS_CR_PDS_GPIO_IE_SET_LEN (3U)
+#define PDS_CR_PDS_GPIO_IE_SET_MSK (((1U << PDS_CR_PDS_GPIO_IE_SET_LEN) - 1) << PDS_CR_PDS_GPIO_IE_SET_POS)
+#define PDS_CR_PDS_GPIO_IE_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_IE_SET_LEN) - 1) << PDS_CR_PDS_GPIO_IE_SET_POS))
+#define PDS_CR_PDS_GPIO_PD_SET PDS_CR_PDS_GPIO_PD_SET
+#define PDS_CR_PDS_GPIO_PD_SET_POS (3U)
+#define PDS_CR_PDS_GPIO_PD_SET_LEN (3U)
+#define PDS_CR_PDS_GPIO_PD_SET_MSK (((1U << PDS_CR_PDS_GPIO_PD_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PD_SET_POS)
+#define PDS_CR_PDS_GPIO_PD_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_PD_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PD_SET_POS))
+#define PDS_CR_PDS_GPIO_PU_SET PDS_CR_PDS_GPIO_PU_SET
+#define PDS_CR_PDS_GPIO_PU_SET_POS (6U)
+#define PDS_CR_PDS_GPIO_PU_SET_LEN (3U)
+#define PDS_CR_PDS_GPIO_PU_SET_MSK (((1U << PDS_CR_PDS_GPIO_PU_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PU_SET_POS)
+#define PDS_CR_PDS_GPIO_PU_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_PU_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PU_SET_POS))
+
+/* 0x34 : pds_gpio_pd_set */
+#define PDS_GPIO_PD_SET_OFFSET (0x34)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK PDS_CR_PDS_GPIO_SET_INT_MASK
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_POS (0U)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_LEN (32U)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_MSK (((1U << PDS_CR_PDS_GPIO_SET_INT_MASK_LEN) - 1) << PDS_CR_PDS_GPIO_SET_INT_MASK_POS)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_GPIO_SET_INT_MASK_LEN) - 1) << PDS_CR_PDS_GPIO_SET_INT_MASK_POS))
+
+/* 0x40 : pds_gpio_int */
+#define PDS_GPIO_INT_OFFSET (0x40)
+#define PDS_GPIO_SET1_INT_CLR PDS_GPIO_SET1_INT_CLR
+#define PDS_GPIO_SET1_INT_CLR_POS (2U)
+#define PDS_GPIO_SET1_INT_CLR_LEN (1U)
+#define PDS_GPIO_SET1_INT_CLR_MSK (((1U << PDS_GPIO_SET1_INT_CLR_LEN) - 1) << PDS_GPIO_SET1_INT_CLR_POS)
+#define PDS_GPIO_SET1_INT_CLR_UMSK (~(((1U << PDS_GPIO_SET1_INT_CLR_LEN) - 1) << PDS_GPIO_SET1_INT_CLR_POS))
+#define PDS_GPIO_SET1_INT_MODE PDS_GPIO_SET1_INT_MODE
+#define PDS_GPIO_SET1_INT_MODE_POS (4U)
+#define PDS_GPIO_SET1_INT_MODE_LEN (4U)
+#define PDS_GPIO_SET1_INT_MODE_MSK (((1U << PDS_GPIO_SET1_INT_MODE_LEN) - 1) << PDS_GPIO_SET1_INT_MODE_POS)
+#define PDS_GPIO_SET1_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET1_INT_MODE_LEN) - 1) << PDS_GPIO_SET1_INT_MODE_POS))
+#define PDS_GPIO_SET2_INT_CLR PDS_GPIO_SET2_INT_CLR
+#define PDS_GPIO_SET2_INT_CLR_POS (10U)
+#define PDS_GPIO_SET2_INT_CLR_LEN (1U)
+#define PDS_GPIO_SET2_INT_CLR_MSK (((1U << PDS_GPIO_SET2_INT_CLR_LEN) - 1) << PDS_GPIO_SET2_INT_CLR_POS)
+#define PDS_GPIO_SET2_INT_CLR_UMSK (~(((1U << PDS_GPIO_SET2_INT_CLR_LEN) - 1) << PDS_GPIO_SET2_INT_CLR_POS))
+#define PDS_GPIO_SET2_INT_MODE PDS_GPIO_SET2_INT_MODE
+#define PDS_GPIO_SET2_INT_MODE_POS (12U)
+#define PDS_GPIO_SET2_INT_MODE_LEN (4U)
+#define PDS_GPIO_SET2_INT_MODE_MSK (((1U << PDS_GPIO_SET2_INT_MODE_LEN) - 1) << PDS_GPIO_SET2_INT_MODE_POS)
+#define PDS_GPIO_SET2_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET2_INT_MODE_LEN) - 1) << PDS_GPIO_SET2_INT_MODE_POS))
+#define PDS_GPIO_SET3_INT_CLR PDS_GPIO_SET3_INT_CLR
+#define PDS_GPIO_SET3_INT_CLR_POS (18U)
+#define PDS_GPIO_SET3_INT_CLR_LEN (1U)
+#define PDS_GPIO_SET3_INT_CLR_MSK (((1U << PDS_GPIO_SET3_INT_CLR_LEN) - 1) << PDS_GPIO_SET3_INT_CLR_POS)
+#define PDS_GPIO_SET3_INT_CLR_UMSK (~(((1U << PDS_GPIO_SET3_INT_CLR_LEN) - 1) << PDS_GPIO_SET3_INT_CLR_POS))
+#define PDS_GPIO_SET3_INT_MODE PDS_GPIO_SET3_INT_MODE
+#define PDS_GPIO_SET3_INT_MODE_POS (20U)
+#define PDS_GPIO_SET3_INT_MODE_LEN (4U)
+#define PDS_GPIO_SET3_INT_MODE_MSK (((1U << PDS_GPIO_SET3_INT_MODE_LEN) - 1) << PDS_GPIO_SET3_INT_MODE_POS)
+#define PDS_GPIO_SET3_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET3_INT_MODE_LEN) - 1) << PDS_GPIO_SET3_INT_MODE_POS))
+#define PDS_GPIO_SET4_INT_CLR PDS_GPIO_SET4_INT_CLR
+#define PDS_GPIO_SET4_INT_CLR_POS (26U)
+#define PDS_GPIO_SET4_INT_CLR_LEN (1U)
+#define PDS_GPIO_SET4_INT_CLR_MSK (((1U << PDS_GPIO_SET4_INT_CLR_LEN) - 1) << PDS_GPIO_SET4_INT_CLR_POS)
+#define PDS_GPIO_SET4_INT_CLR_UMSK (~(((1U << PDS_GPIO_SET4_INT_CLR_LEN) - 1) << PDS_GPIO_SET4_INT_CLR_POS))
+#define PDS_GPIO_SET4_INT_MODE PDS_GPIO_SET4_INT_MODE
+#define PDS_GPIO_SET4_INT_MODE_POS (28U)
+#define PDS_GPIO_SET4_INT_MODE_LEN (4U)
+#define PDS_GPIO_SET4_INT_MODE_MSK (((1U << PDS_GPIO_SET4_INT_MODE_LEN) - 1) << PDS_GPIO_SET4_INT_MODE_POS)
+#define PDS_GPIO_SET4_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET4_INT_MODE_LEN) - 1) << PDS_GPIO_SET4_INT_MODE_POS))
+
+/* 0x44 : pds_gpio_stat */
+#define PDS_GPIO_STAT_OFFSET (0x44)
+#define PDS_GPIO_INT_STAT PDS_GPIO_INT_STAT
+#define PDS_GPIO_INT_STAT_POS (0U)
+#define PDS_GPIO_INT_STAT_LEN (32U)
+#define PDS_GPIO_INT_STAT_MSK (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)
+#define PDS_GPIO_INT_STAT_UMSK (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS))
+
+/* 0x110 : cpu_core_cfg0 */
+#define PDS_CPU_CORE_CFG0_OFFSET (0x110)
+#define PDS_REG_PICO_CLK_EN PDS_REG_PICO_CLK_EN
+#define PDS_REG_PICO_CLK_EN_POS (28U)
+#define PDS_REG_PICO_CLK_EN_LEN (1U)
+#define PDS_REG_PICO_CLK_EN_MSK (((1U << PDS_REG_PICO_CLK_EN_LEN) - 1) << PDS_REG_PICO_CLK_EN_POS)
+#define PDS_REG_PICO_CLK_EN_UMSK (~(((1U << PDS_REG_PICO_CLK_EN_LEN) - 1) << PDS_REG_PICO_CLK_EN_POS))
+#define PDS_E902_DFS_REQ PDS_E902_DFS_REQ
+#define PDS_E902_DFS_REQ_POS (29U)
+#define PDS_E902_DFS_REQ_LEN (1U)
+#define PDS_E902_DFS_REQ_MSK (((1U << PDS_E902_DFS_REQ_LEN) - 1) << PDS_E902_DFS_REQ_POS)
+#define PDS_E902_DFS_REQ_UMSK (~(((1U << PDS_E902_DFS_REQ_LEN) - 1) << PDS_E902_DFS_REQ_POS))
+#define PDS_E902_DFS_ACK PDS_E902_DFS_ACK
+#define PDS_E902_DFS_ACK_POS (30U)
+#define PDS_E902_DFS_ACK_LEN (1U)
+#define PDS_E902_DFS_ACK_MSK (((1U << PDS_E902_DFS_ACK_LEN) - 1) << PDS_E902_DFS_ACK_POS)
+#define PDS_E902_DFS_ACK_UMSK (~(((1U << PDS_E902_DFS_ACK_LEN) - 1) << PDS_E902_DFS_ACK_POS))
+
+/* 0x114 : cpu_core_cfg1 */
+#define PDS_CPU_CORE_CFG1_OFFSET (0x114)
+#define PDS_REG_PLL_SEL PDS_REG_PLL_SEL
+#define PDS_REG_PLL_SEL_POS (4U)
+#define PDS_REG_PLL_SEL_LEN (2U)
+#define PDS_REG_PLL_SEL_MSK (((1U << PDS_REG_PLL_SEL_LEN) - 1) << PDS_REG_PLL_SEL_POS)
+#define PDS_REG_PLL_SEL_UMSK (~(((1U << PDS_REG_PLL_SEL_LEN) - 1) << PDS_REG_PLL_SEL_POS))
+#define PDS_REG_MCU1_CLK_EN PDS_REG_MCU1_CLK_EN
+#define PDS_REG_MCU1_CLK_EN_POS (8U)
+#define PDS_REG_MCU1_CLK_EN_LEN (1U)
+#define PDS_REG_MCU1_CLK_EN_MSK (((1U << PDS_REG_MCU1_CLK_EN_LEN) - 1) << PDS_REG_MCU1_CLK_EN_POS)
+#define PDS_REG_MCU1_CLK_EN_UMSK (~(((1U << PDS_REG_MCU1_CLK_EN_LEN) - 1) << PDS_REG_MCU1_CLK_EN_POS))
+
+/* 0x12C : cpu_core_cfg7 */
+#define PDS_CPU_CORE_CFG7_OFFSET (0x12C)
+#define PDS_REG_PICO_DIV PDS_REG_PICO_DIV
+#define PDS_REG_PICO_DIV_POS (0U)
+#define PDS_REG_PICO_DIV_LEN (8U)
+#define PDS_REG_PICO_DIV_MSK (((1U << PDS_REG_PICO_DIV_LEN) - 1) << PDS_REG_PICO_DIV_POS)
+#define PDS_REG_PICO_DIV_UMSK (~(((1U << PDS_REG_PICO_DIV_LEN) - 1) << PDS_REG_PICO_DIV_POS))
+#define PDS_E902_LPMD_B PDS_E902_LPMD_B
+#define PDS_E902_LPMD_B_POS (28U)
+#define PDS_E902_LPMD_B_LEN (2U)
+#define PDS_E902_LPMD_B_MSK (((1U << PDS_E902_LPMD_B_LEN) - 1) << PDS_E902_LPMD_B_POS)
+#define PDS_E902_LPMD_B_UMSK (~(((1U << PDS_E902_LPMD_B_LEN) - 1) << PDS_E902_LPMD_B_POS))
+#define PDS_PICO_RST_MASK PDS_PICO_RST_MASK
+#define PDS_PICO_RST_MASK_POS (31U)
+#define PDS_PICO_RST_MASK_LEN (1U)
+#define PDS_PICO_RST_MASK_MSK (((1U << PDS_PICO_RST_MASK_LEN) - 1) << PDS_PICO_RST_MASK_POS)
+#define PDS_PICO_RST_MASK_UMSK (~(((1U << PDS_PICO_RST_MASK_LEN) - 1) << PDS_PICO_RST_MASK_POS))
+
+/* 0x130 : cpu_core_cfg8 */
+#define PDS_CPU_CORE_CFG8_OFFSET (0x130)
+#define PDS_E902_RTC_DIV PDS_E902_RTC_DIV
+#define PDS_E902_RTC_DIV_POS (0U)
+#define PDS_E902_RTC_DIV_LEN (10U)
+#define PDS_E902_RTC_DIV_MSK (((1U << PDS_E902_RTC_DIV_LEN) - 1) << PDS_E902_RTC_DIV_POS)
+#define PDS_E902_RTC_DIV_UMSK (~(((1U << PDS_E902_RTC_DIV_LEN) - 1) << PDS_E902_RTC_DIV_POS))
+#define PDS_E902_RTC_RST PDS_E902_RTC_RST
+#define PDS_E902_RTC_RST_POS (30U)
+#define PDS_E902_RTC_RST_LEN (1U)
+#define PDS_E902_RTC_RST_MSK (((1U << PDS_E902_RTC_RST_LEN) - 1) << PDS_E902_RTC_RST_POS)
+#define PDS_E902_RTC_RST_UMSK (~(((1U << PDS_E902_RTC_RST_LEN) - 1) << PDS_E902_RTC_RST_POS))
+#define PDS_E902_RTC_EN PDS_E902_RTC_EN
+#define PDS_E902_RTC_EN_POS (31U)
+#define PDS_E902_RTC_EN_LEN (1U)
+#define PDS_E902_RTC_EN_MSK (((1U << PDS_E902_RTC_EN_LEN) - 1) << PDS_E902_RTC_EN_POS)
+#define PDS_E902_RTC_EN_UMSK (~(((1U << PDS_E902_RTC_EN_LEN) - 1) << PDS_E902_RTC_EN_POS))
+
+/* 0x134 : cpu_core_cfg9 */
+#define PDS_CPU_CORE_CFG9_OFFSET (0x134)
+#define PDS_PICO_RTC_CNT_L PDS_PICO_RTC_CNT_L
+#define PDS_PICO_RTC_CNT_L_POS (0U)
+#define PDS_PICO_RTC_CNT_L_LEN (32U)
+#define PDS_PICO_RTC_CNT_L_MSK (((1U << PDS_PICO_RTC_CNT_L_LEN) - 1) << PDS_PICO_RTC_CNT_L_POS)
+#define PDS_PICO_RTC_CNT_L_UMSK (~(((1U << PDS_PICO_RTC_CNT_L_LEN) - 1) << PDS_PICO_RTC_CNT_L_POS))
+
+/* 0x138 : cpu_core_cfg10 */
+#define PDS_CPU_CORE_CFG10_OFFSET (0x138)
+#define PDS_PICO_RTC_CNT_H PDS_PICO_RTC_CNT_H
+#define PDS_PICO_RTC_CNT_H_POS (0U)
+#define PDS_PICO_RTC_CNT_H_LEN (32U)
+#define PDS_PICO_RTC_CNT_H_MSK (((1U << PDS_PICO_RTC_CNT_H_LEN) - 1) << PDS_PICO_RTC_CNT_H_POS)
+#define PDS_PICO_RTC_CNT_H_UMSK (~(((1U << PDS_PICO_RTC_CNT_H_LEN) - 1) << PDS_PICO_RTC_CNT_H_POS))
+
+/* 0x140 : cpu_core_cfg12 */
+#define PDS_CPU_CORE_CFG12_OFFSET (0x140)
+#define PDS_E902_IAHBL_BASE PDS_E902_IAHBL_BASE
+#define PDS_E902_IAHBL_BASE_POS (0U)
+#define PDS_E902_IAHBL_BASE_LEN (12U)
+#define PDS_E902_IAHBL_BASE_MSK (((1U << PDS_E902_IAHBL_BASE_LEN) - 1) << PDS_E902_IAHBL_BASE_POS)
+#define PDS_E902_IAHBL_BASE_UMSK (~(((1U << PDS_E902_IAHBL_BASE_LEN) - 1) << PDS_E902_IAHBL_BASE_POS))
+#define PDS_E902_IAHBL_MASK PDS_E902_IAHBL_MASK
+#define PDS_E902_IAHBL_MASK_POS (16U)
+#define PDS_E902_IAHBL_MASK_LEN (12U)
+#define PDS_E902_IAHBL_MASK_MSK (((1U << PDS_E902_IAHBL_MASK_LEN) - 1) << PDS_E902_IAHBL_MASK_POS)
+#define PDS_E902_IAHBL_MASK_UMSK (~(((1U << PDS_E902_IAHBL_MASK_LEN) - 1) << PDS_E902_IAHBL_MASK_POS))
+
+/* 0x144 : cpu_core_cfg13 */
+#define PDS_CPU_CORE_CFG13_OFFSET (0x144)
+#define PDS_E902_RST_ADDR PDS_E902_RST_ADDR
+#define PDS_E902_RST_ADDR_POS (0U)
+#define PDS_E902_RST_ADDR_LEN (32U)
+#define PDS_E902_RST_ADDR_MSK (((1U << PDS_E902_RST_ADDR_LEN) - 1) << PDS_E902_RST_ADDR_POS)
+#define PDS_E902_RST_ADDR_UMSK (~(((1U << PDS_E902_RST_ADDR_LEN) - 1) << PDS_E902_RST_ADDR_POS))
+
+/* 0x148 : cpu_core_cfg14 */
+#define PDS_CPU_CORE_CFG14_OFFSET (0x148)
+#define PDS_E906_RST_ADDR PDS_E906_RST_ADDR
+#define PDS_E906_RST_ADDR_POS (0U)
+#define PDS_E906_RST_ADDR_LEN (32U)
+#define PDS_E906_RST_ADDR_MSK (((1U << PDS_E906_RST_ADDR_LEN) - 1) << PDS_E906_RST_ADDR_POS)
+#define PDS_E906_RST_ADDR_UMSK (~(((1U << PDS_E906_RST_ADDR_LEN) - 1) << PDS_E906_RST_ADDR_POS))
+
+/* 0x14C : tzc_pds */
+#define PDS_TZC_PDS_OFFSET (0x14C)
+#define PDS_CR_E902_CFG_WR_LOCK PDS_CR_E902_CFG_WR_LOCK
+#define PDS_CR_E902_CFG_WR_LOCK_POS (0U)
+#define PDS_CR_E902_CFG_WR_LOCK_LEN (1U)
+#define PDS_CR_E902_CFG_WR_LOCK_MSK (((1U << PDS_CR_E902_CFG_WR_LOCK_LEN) - 1) << PDS_CR_E902_CFG_WR_LOCK_POS)
+#define PDS_CR_E902_CFG_WR_LOCK_UMSK (~(((1U << PDS_CR_E902_CFG_WR_LOCK_LEN) - 1) << PDS_CR_E902_CFG_WR_LOCK_POS))
+#define PDS_CR_E906_CFG_WR_LOCK PDS_CR_E906_CFG_WR_LOCK
+#define PDS_CR_E906_CFG_WR_LOCK_POS (1U)
+#define PDS_CR_E906_CFG_WR_LOCK_LEN (1U)
+#define PDS_CR_E906_CFG_WR_LOCK_MSK (((1U << PDS_CR_E906_CFG_WR_LOCK_LEN) - 1) << PDS_CR_E906_CFG_WR_LOCK_POS)
+#define PDS_CR_E906_CFG_WR_LOCK_UMSK (~(((1U << PDS_CR_E906_CFG_WR_LOCK_LEN) - 1) << PDS_CR_E906_CFG_WR_LOCK_POS))
+
+/* 0x300 : rc32m_ctrl0 */
+#define PDS_RC32M_CTRL0_OFFSET (0x300)
+#define PDS_RC32M_CAL_DONE PDS_RC32M_CAL_DONE
+#define PDS_RC32M_CAL_DONE_POS (0U)
+#define PDS_RC32M_CAL_DONE_LEN (1U)
+#define PDS_RC32M_CAL_DONE_MSK (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
+#define PDS_RC32M_CAL_DONE_UMSK (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
+#define PDS_RC32M_RDY PDS_RC32M_RDY
+#define PDS_RC32M_RDY_POS (1U)
+#define PDS_RC32M_RDY_LEN (1U)
+#define PDS_RC32M_RDY_MSK (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
+#define PDS_RC32M_RDY_UMSK (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
+#define PDS_RC32M_CAL_INPROGRESS PDS_RC32M_CAL_INPROGRESS
+#define PDS_RC32M_CAL_INPROGRESS_POS (2U)
+#define PDS_RC32M_CAL_INPROGRESS_LEN (1U)
+#define PDS_RC32M_CAL_INPROGRESS_MSK (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
+#define PDS_RC32M_CAL_INPROGRESS_UMSK (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
+#define PDS_RC32M_CAL_DIV PDS_RC32M_CAL_DIV
+#define PDS_RC32M_CAL_DIV_POS (3U)
+#define PDS_RC32M_CAL_DIV_LEN (2U)
+#define PDS_RC32M_CAL_DIV_MSK (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
+#define PDS_RC32M_CAL_DIV_UMSK (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
+#define PDS_RC32M_CAL_PRECHARGE PDS_RC32M_CAL_PRECHARGE
+#define PDS_RC32M_CAL_PRECHARGE_POS (5U)
+#define PDS_RC32M_CAL_PRECHARGE_LEN (1U)
+#define PDS_RC32M_CAL_PRECHARGE_MSK (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
+#define PDS_RC32M_CAL_PRECHARGE_UMSK (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
+#define PDS_RC32M_DIG_CODE_FR_CAL PDS_RC32M_DIG_CODE_FR_CAL
+#define PDS_RC32M_DIG_CODE_FR_CAL_POS (6U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_LEN (8U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_MSK (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
+#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
+#define PDS_RC32M_ALLOW_CAL PDS_RC32M_ALLOW_CAL
+#define PDS_RC32M_ALLOW_CAL_POS (17U)
+#define PDS_RC32M_ALLOW_CAL_LEN (1U)
+#define PDS_RC32M_ALLOW_CAL_MSK (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
+#define PDS_RC32M_ALLOW_CAL_UMSK (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
+#define PDS_RC32M_REFCLK_HALF PDS_RC32M_REFCLK_HALF
+#define PDS_RC32M_REFCLK_HALF_POS (18U)
+#define PDS_RC32M_REFCLK_HALF_LEN (1U)
+#define PDS_RC32M_REFCLK_HALF_MSK (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
+#define PDS_RC32M_REFCLK_HALF_UMSK (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
+#define PDS_RC32M_EXT_CODE_EN PDS_RC32M_EXT_CODE_EN
+#define PDS_RC32M_EXT_CODE_EN_POS (19U)
+#define PDS_RC32M_EXT_CODE_EN_LEN (1U)
+#define PDS_RC32M_EXT_CODE_EN_MSK (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
+#define PDS_RC32M_EXT_CODE_EN_UMSK (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
+#define PDS_RC32M_CAL_EN PDS_RC32M_CAL_EN
+#define PDS_RC32M_CAL_EN_POS (20U)
+#define PDS_RC32M_CAL_EN_LEN (1U)
+#define PDS_RC32M_CAL_EN_MSK (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
+#define PDS_RC32M_CAL_EN_UMSK (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
+#define PDS_RC32M_PD PDS_RC32M_PD
+#define PDS_RC32M_PD_POS (21U)
+#define PDS_RC32M_PD_LEN (1U)
+#define PDS_RC32M_PD_MSK (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
+#define PDS_RC32M_PD_UMSK (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
+#define PDS_RC32M_CODE_FR_EXT PDS_RC32M_CODE_FR_EXT
+#define PDS_RC32M_CODE_FR_EXT_POS (22U)
+#define PDS_RC32M_CODE_FR_EXT_LEN (8U)
+#define PDS_RC32M_CODE_FR_EXT_MSK (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
+#define PDS_RC32M_CODE_FR_EXT_UMSK (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))
+
+/* 0x304 : rc32m_ctrl1 */
+#define PDS_RC32M_CTRL1_OFFSET (0x304)
+#define PDS_RC32M_TEST_EN PDS_RC32M_TEST_EN
+#define PDS_RC32M_TEST_EN_POS (0U)
+#define PDS_RC32M_TEST_EN_LEN (1U)
+#define PDS_RC32M_TEST_EN_MSK (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
+#define PDS_RC32M_TEST_EN_UMSK (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
+#define PDS_RC32M_SOFT_RST PDS_RC32M_SOFT_RST
+#define PDS_RC32M_SOFT_RST_POS (1U)
+#define PDS_RC32M_SOFT_RST_LEN (1U)
+#define PDS_RC32M_SOFT_RST_MSK (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
+#define PDS_RC32M_SOFT_RST_UMSK (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
+#define PDS_RC32M_CLK_SOFT_RST PDS_RC32M_CLK_SOFT_RST
+#define PDS_RC32M_CLK_SOFT_RST_POS (2U)
+#define PDS_RC32M_CLK_SOFT_RST_LEN (1U)
+#define PDS_RC32M_CLK_SOFT_RST_MSK (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
+#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
+#define PDS_RC32M_CLK_INV PDS_RC32M_CLK_INV
+#define PDS_RC32M_CLK_INV_POS (3U)
+#define PDS_RC32M_CLK_INV_LEN (1U)
+#define PDS_RC32M_CLK_INV_MSK (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
+#define PDS_RC32M_CLK_INV_UMSK (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
+#define PDS_RC32M_CLK_FORCE_ON PDS_RC32M_CLK_FORCE_ON
+#define PDS_RC32M_CLK_FORCE_ON_POS (4U)
+#define PDS_RC32M_CLK_FORCE_ON_LEN (1U)
+#define PDS_RC32M_CLK_FORCE_ON_MSK (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
+#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
+#define PDS_RC32M_RESERVED PDS_RC32M_RESERVED
+#define PDS_RC32M_RESERVED_POS (24U)
+#define PDS_RC32M_RESERVED_LEN (8U)
+#define PDS_RC32M_RESERVED_MSK (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
+#define PDS_RC32M_RESERVED_UMSK (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))
+
+/* 0x400 : pu_rst_clkpll */
+#define PDS_PU_RST_CLKPLL_OFFSET (0x400)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG PDS_CR_PDS_PU_CLKPLL_SFREG
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_POS (9U)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_LEN (1U)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_MSK (((1U << PDS_CR_PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_SFREG_POS)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_UMSK (~(((1U << PDS_CR_PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_SFREG_POS))
+#define PDS_CR_PDS_PU_CLKPLL PDS_CR_PDS_PU_CLKPLL
+#define PDS_CR_PDS_PU_CLKPLL_POS (10U)
+#define PDS_CR_PDS_PU_CLKPLL_LEN (1U)
+#define PDS_CR_PDS_PU_CLKPLL_MSK (((1U << PDS_CR_PDS_PU_CLKPLL_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_POS)
+#define PDS_CR_PDS_PU_CLKPLL_UMSK (~(((1U << PDS_CR_PDS_PU_CLKPLL_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_POS))
+
+/* 0x500 : usb_ctl */
+#define PDS_USB_CTL_OFFSET (0x500)
+#define PDS_REG_USB_SW_RST_N PDS_REG_USB_SW_RST_N
+#define PDS_REG_USB_SW_RST_N_POS (0U)
+#define PDS_REG_USB_SW_RST_N_LEN (1U)
+#define PDS_REG_USB_SW_RST_N_MSK (((1U << PDS_REG_USB_SW_RST_N_LEN) - 1) << PDS_REG_USB_SW_RST_N_POS)
+#define PDS_REG_USB_SW_RST_N_UMSK (~(((1U << PDS_REG_USB_SW_RST_N_LEN) - 1) << PDS_REG_USB_SW_RST_N_POS))
+#define PDS_REG_USB_EXT_SUSP_N PDS_REG_USB_EXT_SUSP_N
+#define PDS_REG_USB_EXT_SUSP_N_POS (1U)
+#define PDS_REG_USB_EXT_SUSP_N_LEN (1U)
+#define PDS_REG_USB_EXT_SUSP_N_MSK (((1U << PDS_REG_USB_EXT_SUSP_N_LEN) - 1) << PDS_REG_USB_EXT_SUSP_N_POS)
+#define PDS_REG_USB_EXT_SUSP_N_UMSK (~(((1U << PDS_REG_USB_EXT_SUSP_N_LEN) - 1) << PDS_REG_USB_EXT_SUSP_N_POS))
+#define PDS_REG_USB_WAKEUP PDS_REG_USB_WAKEUP
+#define PDS_REG_USB_WAKEUP_POS (2U)
+#define PDS_REG_USB_WAKEUP_LEN (1U)
+#define PDS_REG_USB_WAKEUP_MSK (((1U << PDS_REG_USB_WAKEUP_LEN) - 1) << PDS_REG_USB_WAKEUP_POS)
+#define PDS_REG_USB_WAKEUP_UMSK (~(((1U << PDS_REG_USB_WAKEUP_LEN) - 1) << PDS_REG_USB_WAKEUP_POS))
+#define PDS_REG_USB_L1_WAKEUP PDS_REG_USB_L1_WAKEUP
+#define PDS_REG_USB_L1_WAKEUP_POS (3U)
+#define PDS_REG_USB_L1_WAKEUP_LEN (1U)
+#define PDS_REG_USB_L1_WAKEUP_MSK (((1U << PDS_REG_USB_L1_WAKEUP_LEN) - 1) << PDS_REG_USB_L1_WAKEUP_POS)
+#define PDS_REG_USB_L1_WAKEUP_UMSK (~(((1U << PDS_REG_USB_L1_WAKEUP_LEN) - 1) << PDS_REG_USB_L1_WAKEUP_POS))
+#define PDS_REG_USB_DRVBUS_POL PDS_REG_USB_DRVBUS_POL
+#define PDS_REG_USB_DRVBUS_POL_POS (4U)
+#define PDS_REG_USB_DRVBUS_POL_LEN (1U)
+#define PDS_REG_USB_DRVBUS_POL_MSK (((1U << PDS_REG_USB_DRVBUS_POL_LEN) - 1) << PDS_REG_USB_DRVBUS_POL_POS)
+#define PDS_REG_USB_DRVBUS_POL_UMSK (~(((1U << PDS_REG_USB_DRVBUS_POL_LEN) - 1) << PDS_REG_USB_DRVBUS_POL_POS))
+#define PDS_REG_USB_IDDIG PDS_REG_USB_IDDIG
+#define PDS_REG_USB_IDDIG_POS (5U)
+#define PDS_REG_USB_IDDIG_LEN (1U)
+#define PDS_REG_USB_IDDIG_MSK (((1U << PDS_REG_USB_IDDIG_LEN) - 1) << PDS_REG_USB_IDDIG_POS)
+#define PDS_REG_USB_IDDIG_UMSK (~(((1U << PDS_REG_USB_IDDIG_LEN) - 1) << PDS_REG_USB_IDDIG_POS))
+
+/* 0x504 : usb_phy_ctrl */
+#define PDS_USB_PHY_CTRL_OFFSET (0x504)
+#define PDS_REG_USB_PHY_PONRST PDS_REG_USB_PHY_PONRST
+#define PDS_REG_USB_PHY_PONRST_POS (0U)
+#define PDS_REG_USB_PHY_PONRST_LEN (1U)
+#define PDS_REG_USB_PHY_PONRST_MSK (((1U << PDS_REG_USB_PHY_PONRST_LEN) - 1) << PDS_REG_USB_PHY_PONRST_POS)
+#define PDS_REG_USB_PHY_PONRST_UMSK (~(((1U << PDS_REG_USB_PHY_PONRST_LEN) - 1) << PDS_REG_USB_PHY_PONRST_POS))
+#define PDS_REG_USB_PHY_OSCOUTEN PDS_REG_USB_PHY_OSCOUTEN
+#define PDS_REG_USB_PHY_OSCOUTEN_POS (1U)
+#define PDS_REG_USB_PHY_OSCOUTEN_LEN (1U)
+#define PDS_REG_USB_PHY_OSCOUTEN_MSK (((1U << PDS_REG_USB_PHY_OSCOUTEN_LEN) - 1) << PDS_REG_USB_PHY_OSCOUTEN_POS)
+#define PDS_REG_USB_PHY_OSCOUTEN_UMSK (~(((1U << PDS_REG_USB_PHY_OSCOUTEN_LEN) - 1) << PDS_REG_USB_PHY_OSCOUTEN_POS))
+#define PDS_REG_USB_PHY_XTLSEL PDS_REG_USB_PHY_XTLSEL
+#define PDS_REG_USB_PHY_XTLSEL_POS (2U)
+#define PDS_REG_USB_PHY_XTLSEL_LEN (2U)
+#define PDS_REG_USB_PHY_XTLSEL_MSK (((1U << PDS_REG_USB_PHY_XTLSEL_LEN) - 1) << PDS_REG_USB_PHY_XTLSEL_POS)
+#define PDS_REG_USB_PHY_XTLSEL_UMSK (~(((1U << PDS_REG_USB_PHY_XTLSEL_LEN) - 1) << PDS_REG_USB_PHY_XTLSEL_POS))
+#define PDS_REG_USB_PHY_OUTCLKSEL PDS_REG_USB_PHY_OUTCLKSEL
+#define PDS_REG_USB_PHY_OUTCLKSEL_POS (4U)
+#define PDS_REG_USB_PHY_OUTCLKSEL_LEN (1U)
+#define PDS_REG_USB_PHY_OUTCLKSEL_MSK (((1U << PDS_REG_USB_PHY_OUTCLKSEL_LEN) - 1) << PDS_REG_USB_PHY_OUTCLKSEL_POS)
+#define PDS_REG_USB_PHY_OUTCLKSEL_UMSK (~(((1U << PDS_REG_USB_PHY_OUTCLKSEL_LEN) - 1) << PDS_REG_USB_PHY_OUTCLKSEL_POS))
+#define PDS_REG_USB_PHY_PLLALIV PDS_REG_USB_PHY_PLLALIV
+#define PDS_REG_USB_PHY_PLLALIV_POS (5U)
+#define PDS_REG_USB_PHY_PLLALIV_LEN (1U)
+#define PDS_REG_USB_PHY_PLLALIV_MSK (((1U << PDS_REG_USB_PHY_PLLALIV_LEN) - 1) << PDS_REG_USB_PHY_PLLALIV_POS)
+#define PDS_REG_USB_PHY_PLLALIV_UMSK (~(((1U << PDS_REG_USB_PHY_PLLALIV_LEN) - 1) << PDS_REG_USB_PHY_PLLALIV_POS))
+#define PDS_REG_PU_USB20_PSW PDS_REG_PU_USB20_PSW
+#define PDS_REG_PU_USB20_PSW_POS (6U)
+#define PDS_REG_PU_USB20_PSW_LEN (1U)
+#define PDS_REG_PU_USB20_PSW_MSK (((1U << PDS_REG_PU_USB20_PSW_LEN) - 1) << PDS_REG_PU_USB20_PSW_POS)
+#define PDS_REG_PU_USB20_PSW_UMSK (~(((1U << PDS_REG_PU_USB20_PSW_LEN) - 1) << PDS_REG_PU_USB20_PSW_POS))
+
+/* 0xA00 : touch channel, clock, ana config1 */
+#define PDS_TOUCH1_OFFSET (0xA00)
+#define PDS_TOUCH_VREF_SEL PDS_TOUCH_VREF_SEL
+#define PDS_TOUCH_VREF_SEL_POS (0U)
+#define PDS_TOUCH_VREF_SEL_LEN (3U)
+#define PDS_TOUCH_VREF_SEL_MSK (((1U << PDS_TOUCH_VREF_SEL_LEN) - 1) << PDS_TOUCH_VREF_SEL_POS)
+#define PDS_TOUCH_VREF_SEL_UMSK (~(((1U << PDS_TOUCH_VREF_SEL_LEN) - 1) << PDS_TOUCH_VREF_SEL_POS))
+#define PDS_TOUCH_VLDO_SEL PDS_TOUCH_VLDO_SEL
+#define PDS_TOUCH_VLDO_SEL_POS (3U)
+#define PDS_TOUCH_VLDO_SEL_LEN (3U)
+#define PDS_TOUCH_VLDO_SEL_MSK (((1U << PDS_TOUCH_VLDO_SEL_LEN) - 1) << PDS_TOUCH_VLDO_SEL_POS)
+#define PDS_TOUCH_VLDO_SEL_UMSK (~(((1U << PDS_TOUCH_VLDO_SEL_LEN) - 1) << PDS_TOUCH_VLDO_SEL_POS))
+#define PDS_TOUCH_COMP_HYS_SEL PDS_TOUCH_COMP_HYS_SEL
+#define PDS_TOUCH_COMP_HYS_SEL_POS (6U)
+#define PDS_TOUCH_COMP_HYS_SEL_LEN (1U)
+#define PDS_TOUCH_COMP_HYS_SEL_MSK (((1U << PDS_TOUCH_COMP_HYS_SEL_LEN) - 1) << PDS_TOUCH_COMP_HYS_SEL_POS)
+#define PDS_TOUCH_COMP_HYS_SEL_UMSK (~(((1U << PDS_TOUCH_COMP_HYS_SEL_LEN) - 1) << PDS_TOUCH_COMP_HYS_SEL_POS))
+#define PDS_TOUCH_CURRENT_SEL PDS_TOUCH_CURRENT_SEL
+#define PDS_TOUCH_CURRENT_SEL_POS (7U)
+#define PDS_TOUCH_CURRENT_SEL_LEN (1U)
+#define PDS_TOUCH_CURRENT_SEL_MSK (((1U << PDS_TOUCH_CURRENT_SEL_LEN) - 1) << PDS_TOUCH_CURRENT_SEL_POS)
+#define PDS_TOUCH_CURRENT_SEL_UMSK (~(((1U << PDS_TOUCH_CURRENT_SEL_LEN) - 1) << PDS_TOUCH_CURRENT_SEL_POS))
+#define PDS_TOUCH_CLK_SEL PDS_TOUCH_CLK_SEL
+#define PDS_TOUCH_CLK_SEL_POS (16U)
+#define PDS_TOUCH_CLK_SEL_LEN (1U)
+#define PDS_TOUCH_CLK_SEL_MSK (((1U << PDS_TOUCH_CLK_SEL_LEN) - 1) << PDS_TOUCH_CLK_SEL_POS)
+#define PDS_TOUCH_CLK_SEL_UMSK (~(((1U << PDS_TOUCH_CLK_SEL_LEN) - 1) << PDS_TOUCH_CLK_SEL_POS))
+#define PDS_TOUCH_CLK_DIV_RATIO PDS_TOUCH_CLK_DIV_RATIO
+#define PDS_TOUCH_CLK_DIV_RATIO_POS (17U)
+#define PDS_TOUCH_CLK_DIV_RATIO_LEN (3U)
+#define PDS_TOUCH_CLK_DIV_RATIO_MSK (((1U << PDS_TOUCH_CLK_DIV_RATIO_LEN) - 1) << PDS_TOUCH_CLK_DIV_RATIO_POS)
+#define PDS_TOUCH_CLK_DIV_RATIO_UMSK (~(((1U << PDS_TOUCH_CLK_DIV_RATIO_LEN) - 1) << PDS_TOUCH_CLK_DIV_RATIO_POS))
+#define PDS_TOUCH_PCHARGE_HIGH PDS_TOUCH_PCHARGE_HIGH
+#define PDS_TOUCH_PCHARGE_HIGH_POS (20U)
+#define PDS_TOUCH_PCHARGE_HIGH_LEN (3U)
+#define PDS_TOUCH_PCHARGE_HIGH_MSK (((1U << PDS_TOUCH_PCHARGE_HIGH_LEN) - 1) << PDS_TOUCH_PCHARGE_HIGH_POS)
+#define PDS_TOUCH_PCHARGE_HIGH_UMSK (~(((1U << PDS_TOUCH_PCHARGE_HIGH_LEN) - 1) << PDS_TOUCH_PCHARGE_HIGH_POS))
+#define PDS_TOUCH_PCHARGE_LOW PDS_TOUCH_PCHARGE_LOW
+#define PDS_TOUCH_PCHARGE_LOW_POS (23U)
+#define PDS_TOUCH_PCHARGE_LOW_LEN (3U)
+#define PDS_TOUCH_PCHARGE_LOW_MSK (((1U << PDS_TOUCH_PCHARGE_LOW_LEN) - 1) << PDS_TOUCH_PCHARGE_LOW_POS)
+#define PDS_TOUCH_PCHARGE_LOW_UMSK (~(((1U << PDS_TOUCH_PCHARGE_LOW_LEN) - 1) << PDS_TOUCH_PCHARGE_LOW_POS))
+#define PDS_TOUCH_CONT_EN PDS_TOUCH_CONT_EN
+#define PDS_TOUCH_CONT_EN_POS (26U)
+#define PDS_TOUCH_CONT_EN_LEN (1U)
+#define PDS_TOUCH_CONT_EN_MSK (((1U << PDS_TOUCH_CONT_EN_LEN) - 1) << PDS_TOUCH_CONT_EN_POS)
+#define PDS_TOUCH_CONT_EN_UMSK (~(((1U << PDS_TOUCH_CONT_EN_LEN) - 1) << PDS_TOUCH_CONT_EN_POS))
+#define PDS_TOUCH_CYCLE_EN PDS_TOUCH_CYCLE_EN
+#define PDS_TOUCH_CYCLE_EN_POS (27U)
+#define PDS_TOUCH_CYCLE_EN_LEN (1U)
+#define PDS_TOUCH_CYCLE_EN_MSK (((1U << PDS_TOUCH_CYCLE_EN_LEN) - 1) << PDS_TOUCH_CYCLE_EN_POS)
+#define PDS_TOUCH_CYCLE_EN_UMSK (~(((1U << PDS_TOUCH_CYCLE_EN_LEN) - 1) << PDS_TOUCH_CYCLE_EN_POS))
+#define PDS_TOUCH_ULP_EN PDS_TOUCH_ULP_EN
+#define PDS_TOUCH_ULP_EN_POS (28U)
+#define PDS_TOUCH_ULP_EN_LEN (1U)
+#define PDS_TOUCH_ULP_EN_MSK (((1U << PDS_TOUCH_ULP_EN_LEN) - 1) << PDS_TOUCH_ULP_EN_POS)
+#define PDS_TOUCH_ULP_EN_UMSK (~(((1U << PDS_TOUCH_ULP_EN_LEN) - 1) << PDS_TOUCH_ULP_EN_POS))
+#define PDS_PU_TOUCH PDS_PU_TOUCH
+#define PDS_PU_TOUCH_POS (30U)
+#define PDS_PU_TOUCH_LEN (1U)
+#define PDS_PU_TOUCH_MSK (((1U << PDS_PU_TOUCH_LEN) - 1) << PDS_PU_TOUCH_POS)
+#define PDS_PU_TOUCH_UMSK (~(((1U << PDS_PU_TOUCH_LEN) - 1) << PDS_PU_TOUCH_POS))
+
+/* 0xA04 : touch channel, clock, ana config2 */
+#define PDS_TOUCH2_OFFSET (0xA04)
+#define PDS_TOUCH_CHANNEL_SEL PDS_TOUCH_CHANNEL_SEL
+#define PDS_TOUCH_CHANNEL_SEL_POS (0U)
+#define PDS_TOUCH_CHANNEL_SEL_LEN (4U)
+#define PDS_TOUCH_CHANNEL_SEL_MSK (((1U << PDS_TOUCH_CHANNEL_SEL_LEN) - 1) << PDS_TOUCH_CHANNEL_SEL_POS)
+#define PDS_TOUCH_CHANNEL_SEL_UMSK (~(((1U << PDS_TOUCH_CHANNEL_SEL_LEN) - 1) << PDS_TOUCH_CHANNEL_SEL_POS))
+#define PDS_TOUCH_CHANNEL0_HIGHZ_EN PDS_TOUCH_CHANNEL0_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL0_HIGHZ_EN_POS (4U)
+#define PDS_TOUCH_CHANNEL0_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL0_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL0_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL0_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL0_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL0_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL0_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL1_HIGHZ_EN PDS_TOUCH_CHANNEL1_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL1_HIGHZ_EN_POS (5U)
+#define PDS_TOUCH_CHANNEL1_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL1_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL1_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL1_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL1_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL1_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL1_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL2_HIGHZ_EN PDS_TOUCH_CHANNEL2_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL2_HIGHZ_EN_POS (6U)
+#define PDS_TOUCH_CHANNEL2_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL2_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL2_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL2_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL2_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL2_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL2_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL3_HIGHZ_EN PDS_TOUCH_CHANNEL3_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL3_HIGHZ_EN_POS (7U)
+#define PDS_TOUCH_CHANNEL3_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL3_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL3_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL3_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL3_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL3_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL3_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL4_HIGHZ_EN PDS_TOUCH_CHANNEL4_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL4_HIGHZ_EN_POS (8U)
+#define PDS_TOUCH_CHANNEL4_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL4_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL4_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL4_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL4_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL4_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL4_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL5_HIGHZ_EN PDS_TOUCH_CHANNEL5_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL5_HIGHZ_EN_POS (9U)
+#define PDS_TOUCH_CHANNEL5_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL5_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL5_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL5_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL5_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL5_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL5_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL6_HIGHZ_EN PDS_TOUCH_CHANNEL6_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL6_HIGHZ_EN_POS (10U)
+#define PDS_TOUCH_CHANNEL6_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL6_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL6_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL6_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL6_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL6_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL6_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL7_HIGHZ_EN PDS_TOUCH_CHANNEL7_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL7_HIGHZ_EN_POS (11U)
+#define PDS_TOUCH_CHANNEL7_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL7_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL7_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL7_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL7_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL7_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL7_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL8_HIGHZ_EN PDS_TOUCH_CHANNEL8_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL8_HIGHZ_EN_POS (12U)
+#define PDS_TOUCH_CHANNEL8_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL8_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL8_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL8_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL8_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL8_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL8_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL9_HIGHZ_EN PDS_TOUCH_CHANNEL9_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL9_HIGHZ_EN_POS (13U)
+#define PDS_TOUCH_CHANNEL9_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL9_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL9_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL9_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL9_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL9_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL9_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL10_HIGHZ_EN PDS_TOUCH_CHANNEL10_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL10_HIGHZ_EN_POS (14U)
+#define PDS_TOUCH_CHANNEL10_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL10_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL10_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL10_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL10_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL10_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL10_HIGHZ_EN_POS))
+#define PDS_TOUCH_CHANNEL11_HIGHZ_EN PDS_TOUCH_CHANNEL11_HIGHZ_EN
+#define PDS_TOUCH_CHANNEL11_HIGHZ_EN_POS (15U)
+#define PDS_TOUCH_CHANNEL11_HIGHZ_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL11_HIGHZ_EN_MSK (((1U << PDS_TOUCH_CHANNEL11_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL11_HIGHZ_EN_POS)
+#define PDS_TOUCH_CHANNEL11_HIGHZ_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL11_HIGHZ_EN_LEN) - 1) << PDS_TOUCH_CHANNEL11_HIGHZ_EN_POS))
+
+/* 0xA08 : touch data process */
+#define PDS_TOUCH3_OFFSET (0xA08)
+#define PDS_TOUCH_CHANNEL_CAL_EN PDS_TOUCH_CHANNEL_CAL_EN
+#define PDS_TOUCH_CHANNEL_CAL_EN_POS (0U)
+#define PDS_TOUCH_CHANNEL_CAL_EN_LEN (1U)
+#define PDS_TOUCH_CHANNEL_CAL_EN_MSK (((1U << PDS_TOUCH_CHANNEL_CAL_EN_LEN) - 1) << PDS_TOUCH_CHANNEL_CAL_EN_POS)
+#define PDS_TOUCH_CHANNEL_CAL_EN_UMSK (~(((1U << PDS_TOUCH_CHANNEL_CAL_EN_LEN) - 1) << PDS_TOUCH_CHANNEL_CAL_EN_POS))
+#define PDS_TOUCH_FORCE_VALUE_EN PDS_TOUCH_FORCE_VALUE_EN
+#define PDS_TOUCH_FORCE_VALUE_EN_POS (1U)
+#define PDS_TOUCH_FORCE_VALUE_EN_LEN (1U)
+#define PDS_TOUCH_FORCE_VALUE_EN_MSK (((1U << PDS_TOUCH_FORCE_VALUE_EN_LEN) - 1) << PDS_TOUCH_FORCE_VALUE_EN_POS)
+#define PDS_TOUCH_FORCE_VALUE_EN_UMSK (~(((1U << PDS_TOUCH_FORCE_VALUE_EN_LEN) - 1) << PDS_TOUCH_FORCE_VALUE_EN_POS))
+#define PDS_TOUCH_DATA_HYS_EN PDS_TOUCH_DATA_HYS_EN
+#define PDS_TOUCH_DATA_HYS_EN_POS (2U)
+#define PDS_TOUCH_DATA_HYS_EN_LEN (1U)
+#define PDS_TOUCH_DATA_HYS_EN_MSK (((1U << PDS_TOUCH_DATA_HYS_EN_LEN) - 1) << PDS_TOUCH_DATA_HYS_EN_POS)
+#define PDS_TOUCH_DATA_HYS_EN_UMSK (~(((1U << PDS_TOUCH_DATA_HYS_EN_LEN) - 1) << PDS_TOUCH_DATA_HYS_EN_POS))
+#define PDS_TOUCH_LTA_EN PDS_TOUCH_LTA_EN
+#define PDS_TOUCH_LTA_EN_POS (4U)
+#define PDS_TOUCH_LTA_EN_LEN (1U)
+#define PDS_TOUCH_LTA_EN_MSK (((1U << PDS_TOUCH_LTA_EN_LEN) - 1) << PDS_TOUCH_LTA_EN_POS)
+#define PDS_TOUCH_LTA_EN_UMSK (~(((1U << PDS_TOUCH_LTA_EN_LEN) - 1) << PDS_TOUCH_LTA_EN_POS))
+#define PDS_TOUCH_LTA_ORDER PDS_TOUCH_LTA_ORDER
+#define PDS_TOUCH_LTA_ORDER_POS (5U)
+#define PDS_TOUCH_LTA_ORDER_LEN (3U)
+#define PDS_TOUCH_LTA_ORDER_MSK (((1U << PDS_TOUCH_LTA_ORDER_LEN) - 1) << PDS_TOUCH_LTA_ORDER_POS)
+#define PDS_TOUCH_LTA_ORDER_UMSK (~(((1U << PDS_TOUCH_LTA_ORDER_LEN) - 1) << PDS_TOUCH_LTA_ORDER_POS))
+#define PDS_TOUCH_FLT_EN PDS_TOUCH_FLT_EN
+#define PDS_TOUCH_FLT_EN_POS (8U)
+#define PDS_TOUCH_FLT_EN_LEN (1U)
+#define PDS_TOUCH_FLT_EN_MSK (((1U << PDS_TOUCH_FLT_EN_LEN) - 1) << PDS_TOUCH_FLT_EN_POS)
+#define PDS_TOUCH_FLT_EN_UMSK (~(((1U << PDS_TOUCH_FLT_EN_LEN) - 1) << PDS_TOUCH_FLT_EN_POS))
+#define PDS_TOUCH_FLT_ORDER PDS_TOUCH_FLT_ORDER
+#define PDS_TOUCH_FLT_ORDER_POS (9U)
+#define PDS_TOUCH_FLT_ORDER_LEN (3U)
+#define PDS_TOUCH_FLT_ORDER_MSK (((1U << PDS_TOUCH_FLT_ORDER_LEN) - 1) << PDS_TOUCH_FLT_ORDER_POS)
+#define PDS_TOUCH_FLT_ORDER_UMSK (~(((1U << PDS_TOUCH_FLT_ORDER_LEN) - 1) << PDS_TOUCH_FLT_ORDER_POS))
+#define PDS_TOUCH_SELF_MUTUAL_SEL PDS_TOUCH_SELF_MUTUAL_SEL
+#define PDS_TOUCH_SELF_MUTUAL_SEL_POS (12U)
+#define PDS_TOUCH_SELF_MUTUAL_SEL_LEN (1U)
+#define PDS_TOUCH_SELF_MUTUAL_SEL_MSK (((1U << PDS_TOUCH_SELF_MUTUAL_SEL_LEN) - 1) << PDS_TOUCH_SELF_MUTUAL_SEL_POS)
+#define PDS_TOUCH_SELF_MUTUAL_SEL_UMSK (~(((1U << PDS_TOUCH_SELF_MUTUAL_SEL_LEN) - 1) << PDS_TOUCH_SELF_MUTUAL_SEL_POS))
+#define PDS_TOUCH_VLDO_CCSEL PDS_TOUCH_VLDO_CCSEL
+#define PDS_TOUCH_VLDO_CCSEL_POS (13U)
+#define PDS_TOUCH_VLDO_CCSEL_LEN (2U)
+#define PDS_TOUCH_VLDO_CCSEL_MSK (((1U << PDS_TOUCH_VLDO_CCSEL_LEN) - 1) << PDS_TOUCH_VLDO_CCSEL_POS)
+#define PDS_TOUCH_VLDO_CCSEL_UMSK (~(((1U << PDS_TOUCH_VLDO_CCSEL_LEN) - 1) << PDS_TOUCH_VLDO_CCSEL_POS))
+#define PDS_TEN_TOUCH PDS_TEN_TOUCH
+#define PDS_TEN_TOUCH_POS (18U)
+#define PDS_TEN_TOUCH_LEN (1U)
+#define PDS_TEN_TOUCH_MSK (((1U << PDS_TEN_TOUCH_LEN) - 1) << PDS_TEN_TOUCH_POS)
+#define PDS_TEN_TOUCH_UMSK (~(((1U << PDS_TEN_TOUCH_LEN) - 1) << PDS_TEN_TOUCH_POS))
+
+/* 0xA0C : Touch_sleep_time */
+#define PDS_TOUCH_SLEEP_TIME_OFFSET (0xA0C)
+#define PDS_TOUCH_SLEEP_CYCLE PDS_TOUCH_SLEEP_CYCLE
+#define PDS_TOUCH_SLEEP_CYCLE_POS (0U)
+#define PDS_TOUCH_SLEEP_CYCLE_LEN (23U)
+#define PDS_TOUCH_SLEEP_CYCLE_MSK (((1U << PDS_TOUCH_SLEEP_CYCLE_LEN) - 1) << PDS_TOUCH_SLEEP_CYCLE_POS)
+#define PDS_TOUCH_SLEEP_CYCLE_UMSK (~(((1U << PDS_TOUCH_SLEEP_CYCLE_LEN) - 1) << PDS_TOUCH_SLEEP_CYCLE_POS))
+
+/* 0xA10 : touch_data_hystersis */
+#define PDS_TOUCH_DATA_HYSTERSIS_OFFSET (0xA10)
+#define PDS_TOUCH_DATA_HYS PDS_TOUCH_DATA_HYS
+#define PDS_TOUCH_DATA_HYS_POS (0U)
+#define PDS_TOUCH_DATA_HYS_LEN (9U)
+#define PDS_TOUCH_DATA_HYS_MSK (((1U << PDS_TOUCH_DATA_HYS_LEN) - 1) << PDS_TOUCH_DATA_HYS_POS)
+#define PDS_TOUCH_DATA_HYS_UMSK (~(((1U << PDS_TOUCH_DATA_HYS_LEN) - 1) << PDS_TOUCH_DATA_HYS_POS))
+
+/* 0xA14 : Channel_force_data_0 */
+#define PDS_CHANNEL_FORCE_DATA_0_OFFSET (0xA14)
+#define PDS_TOUCH_FORCE_DATA_CH0 PDS_TOUCH_FORCE_DATA_CH0
+#define PDS_TOUCH_FORCE_DATA_CH0_POS (0U)
+#define PDS_TOUCH_FORCE_DATA_CH0_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH0_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH0_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH0_POS)
+#define PDS_TOUCH_FORCE_DATA_CH0_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH0_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH0_POS))
+#define PDS_TOUCH_FORCE_DATA_CH1 PDS_TOUCH_FORCE_DATA_CH1
+#define PDS_TOUCH_FORCE_DATA_CH1_POS (16U)
+#define PDS_TOUCH_FORCE_DATA_CH1_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH1_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH1_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH1_POS)
+#define PDS_TOUCH_FORCE_DATA_CH1_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH1_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH1_POS))
+
+/* 0xA18 : Channel_force_data_1 */
+#define PDS_CHANNEL_FORCE_DATA_1_OFFSET (0xA18)
+#define PDS_TOUCH_FORCE_DATA_CH2 PDS_TOUCH_FORCE_DATA_CH2
+#define PDS_TOUCH_FORCE_DATA_CH2_POS (0U)
+#define PDS_TOUCH_FORCE_DATA_CH2_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH2_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH2_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH2_POS)
+#define PDS_TOUCH_FORCE_DATA_CH2_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH2_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH2_POS))
+#define PDS_TOUCH_FORCE_DATA_CH3 PDS_TOUCH_FORCE_DATA_CH3
+#define PDS_TOUCH_FORCE_DATA_CH3_POS (16U)
+#define PDS_TOUCH_FORCE_DATA_CH3_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH3_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH3_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH3_POS)
+#define PDS_TOUCH_FORCE_DATA_CH3_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH3_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH3_POS))
+
+/* 0xA1C : Channel_force_data_2 */
+#define PDS_CHANNEL_FORCE_DATA_2_OFFSET (0xA1C)
+#define PDS_TOUCH_FORCE_DATA_CH4 PDS_TOUCH_FORCE_DATA_CH4
+#define PDS_TOUCH_FORCE_DATA_CH4_POS (0U)
+#define PDS_TOUCH_FORCE_DATA_CH4_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH4_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH4_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH4_POS)
+#define PDS_TOUCH_FORCE_DATA_CH4_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH4_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH4_POS))
+#define PDS_TOUCH_FORCE_DATA_CH5 PDS_TOUCH_FORCE_DATA_CH5
+#define PDS_TOUCH_FORCE_DATA_CH5_POS (16U)
+#define PDS_TOUCH_FORCE_DATA_CH5_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH5_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH5_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH5_POS)
+#define PDS_TOUCH_FORCE_DATA_CH5_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH5_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH5_POS))
+
+/* 0xA20 : Channel_force_data_3 */
+#define PDS_CHANNEL_FORCE_DATA_3_OFFSET (0xA20)
+#define PDS_TOUCH_FORCE_DATA_CH6 PDS_TOUCH_FORCE_DATA_CH6
+#define PDS_TOUCH_FORCE_DATA_CH6_POS (0U)
+#define PDS_TOUCH_FORCE_DATA_CH6_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH6_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH6_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH6_POS)
+#define PDS_TOUCH_FORCE_DATA_CH6_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH6_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH6_POS))
+#define PDS_TOUCH_FORCE_DATA_CH7 PDS_TOUCH_FORCE_DATA_CH7
+#define PDS_TOUCH_FORCE_DATA_CH7_POS (16U)
+#define PDS_TOUCH_FORCE_DATA_CH7_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH7_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH7_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH7_POS)
+#define PDS_TOUCH_FORCE_DATA_CH7_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH7_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH7_POS))
+
+/* 0xA24 : Channel_force_data_4 */
+#define PDS_CHANNEL_FORCE_DATA_4_OFFSET (0xA24)
+#define PDS_TOUCH_FORCE_DATA_CH8 PDS_TOUCH_FORCE_DATA_CH8
+#define PDS_TOUCH_FORCE_DATA_CH8_POS (0U)
+#define PDS_TOUCH_FORCE_DATA_CH8_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH8_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH8_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH8_POS)
+#define PDS_TOUCH_FORCE_DATA_CH8_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH8_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH8_POS))
+#define PDS_TOUCH_FORCE_DATA_CH9 PDS_TOUCH_FORCE_DATA_CH9
+#define PDS_TOUCH_FORCE_DATA_CH9_POS (16U)
+#define PDS_TOUCH_FORCE_DATA_CH9_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH9_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH9_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH9_POS)
+#define PDS_TOUCH_FORCE_DATA_CH9_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH9_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH9_POS))
+
+/* 0xA28 : Channel_force_data_5 */
+#define PDS_CHANNEL_FORCE_DATA_5_OFFSET (0xA28)
+#define PDS_TOUCH_FORCE_DATA_CH10 PDS_TOUCH_FORCE_DATA_CH10
+#define PDS_TOUCH_FORCE_DATA_CH10_POS (0U)
+#define PDS_TOUCH_FORCE_DATA_CH10_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH10_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH10_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH10_POS)
+#define PDS_TOUCH_FORCE_DATA_CH10_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH10_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH10_POS))
+#define PDS_TOUCH_FORCE_DATA_CH11 PDS_TOUCH_FORCE_DATA_CH11
+#define PDS_TOUCH_FORCE_DATA_CH11_POS (16U)
+#define PDS_TOUCH_FORCE_DATA_CH11_LEN (16U)
+#define PDS_TOUCH_FORCE_DATA_CH11_MSK (((1U << PDS_TOUCH_FORCE_DATA_CH11_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH11_POS)
+#define PDS_TOUCH_FORCE_DATA_CH11_UMSK (~(((1U << PDS_TOUCH_FORCE_DATA_CH11_LEN) - 1) << PDS_TOUCH_FORCE_DATA_CH11_POS))
+
+/* 0xA2C : Channel_vth_data_0 */
+#define PDS_CHANNEL_VTH_DATA_0_OFFSET (0xA2C)
+#define PDS_TOUCH_VTH_DATA_CH0 PDS_TOUCH_VTH_DATA_CH0
+#define PDS_TOUCH_VTH_DATA_CH0_POS (0U)
+#define PDS_TOUCH_VTH_DATA_CH0_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH0_MSK (((1U << PDS_TOUCH_VTH_DATA_CH0_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH0_POS)
+#define PDS_TOUCH_VTH_DATA_CH0_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH0_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH0_POS))
+#define PDS_TOUCH_VTH_DATA_CH1 PDS_TOUCH_VTH_DATA_CH1
+#define PDS_TOUCH_VTH_DATA_CH1_POS (8U)
+#define PDS_TOUCH_VTH_DATA_CH1_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH1_MSK (((1U << PDS_TOUCH_VTH_DATA_CH1_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH1_POS)
+#define PDS_TOUCH_VTH_DATA_CH1_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH1_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH1_POS))
+#define PDS_TOUCH_VTH_DATA_CH2 PDS_TOUCH_VTH_DATA_CH2
+#define PDS_TOUCH_VTH_DATA_CH2_POS (16U)
+#define PDS_TOUCH_VTH_DATA_CH2_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH2_MSK (((1U << PDS_TOUCH_VTH_DATA_CH2_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH2_POS)
+#define PDS_TOUCH_VTH_DATA_CH2_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH2_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH2_POS))
+#define PDS_TOUCH_VTH_DATA_CH3 PDS_TOUCH_VTH_DATA_CH3
+#define PDS_TOUCH_VTH_DATA_CH3_POS (24U)
+#define PDS_TOUCH_VTH_DATA_CH3_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH3_MSK (((1U << PDS_TOUCH_VTH_DATA_CH3_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH3_POS)
+#define PDS_TOUCH_VTH_DATA_CH3_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH3_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH3_POS))
+
+/* 0xA30 : Channel_vth_data_1 */
+#define PDS_CHANNEL_VTH_DATA_1_OFFSET (0xA30)
+#define PDS_TOUCH_VTH_DATA_CH4 PDS_TOUCH_VTH_DATA_CH4
+#define PDS_TOUCH_VTH_DATA_CH4_POS (0U)
+#define PDS_TOUCH_VTH_DATA_CH4_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH4_MSK (((1U << PDS_TOUCH_VTH_DATA_CH4_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH4_POS)
+#define PDS_TOUCH_VTH_DATA_CH4_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH4_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH4_POS))
+#define PDS_TOUCH_VTH_DATA_CH5 PDS_TOUCH_VTH_DATA_CH5
+#define PDS_TOUCH_VTH_DATA_CH5_POS (8U)
+#define PDS_TOUCH_VTH_DATA_CH5_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH5_MSK (((1U << PDS_TOUCH_VTH_DATA_CH5_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH5_POS)
+#define PDS_TOUCH_VTH_DATA_CH5_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH5_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH5_POS))
+#define PDS_TOUCH_VTH_DATA_CH6 PDS_TOUCH_VTH_DATA_CH6
+#define PDS_TOUCH_VTH_DATA_CH6_POS (16U)
+#define PDS_TOUCH_VTH_DATA_CH6_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH6_MSK (((1U << PDS_TOUCH_VTH_DATA_CH6_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH6_POS)
+#define PDS_TOUCH_VTH_DATA_CH6_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH6_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH6_POS))
+#define PDS_TOUCH_VTH_DATA_CH7 PDS_TOUCH_VTH_DATA_CH7
+#define PDS_TOUCH_VTH_DATA_CH7_POS (24U)
+#define PDS_TOUCH_VTH_DATA_CH7_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH7_MSK (((1U << PDS_TOUCH_VTH_DATA_CH7_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH7_POS)
+#define PDS_TOUCH_VTH_DATA_CH7_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH7_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH7_POS))
+
+/* 0xA34 : Channel_vth_data_2 */
+#define PDS_CHANNEL_VTH_DATA_2_OFFSET (0xA34)
+#define PDS_TOUCH_VTH_DATA_CH8 PDS_TOUCH_VTH_DATA_CH8
+#define PDS_TOUCH_VTH_DATA_CH8_POS (0U)
+#define PDS_TOUCH_VTH_DATA_CH8_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH8_MSK (((1U << PDS_TOUCH_VTH_DATA_CH8_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH8_POS)
+#define PDS_TOUCH_VTH_DATA_CH8_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH8_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH8_POS))
+#define PDS_TOUCH_VTH_DATA_CH9 PDS_TOUCH_VTH_DATA_CH9
+#define PDS_TOUCH_VTH_DATA_CH9_POS (8U)
+#define PDS_TOUCH_VTH_DATA_CH9_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH9_MSK (((1U << PDS_TOUCH_VTH_DATA_CH9_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH9_POS)
+#define PDS_TOUCH_VTH_DATA_CH9_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH9_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH9_POS))
+#define PDS_TOUCH_VTH_DATA_CH10 PDS_TOUCH_VTH_DATA_CH10
+#define PDS_TOUCH_VTH_DATA_CH10_POS (16U)
+#define PDS_TOUCH_VTH_DATA_CH10_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH10_MSK (((1U << PDS_TOUCH_VTH_DATA_CH10_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH10_POS)
+#define PDS_TOUCH_VTH_DATA_CH10_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH10_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH10_POS))
+#define PDS_TOUCH_VTH_DATA_CH11 PDS_TOUCH_VTH_DATA_CH11
+#define PDS_TOUCH_VTH_DATA_CH11_POS (24U)
+#define PDS_TOUCH_VTH_DATA_CH11_LEN (8U)
+#define PDS_TOUCH_VTH_DATA_CH11_MSK (((1U << PDS_TOUCH_VTH_DATA_CH11_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH11_POS)
+#define PDS_TOUCH_VTH_DATA_CH11_UMSK (~(((1U << PDS_TOUCH_VTH_DATA_CH11_LEN) - 1) << PDS_TOUCH_VTH_DATA_CH11_POS))
+
+/* 0xA38 : Channel_raw_data_0 */
+#define PDS_CHANNEL_RAW_DATA_0_OFFSET (0xA38)
+#define PDS_TOUCH_RAW_DATA_CH0 PDS_TOUCH_RAW_DATA_CH0
+#define PDS_TOUCH_RAW_DATA_CH0_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH0_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH0_MSK (((1U << PDS_TOUCH_RAW_DATA_CH0_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH0_POS)
+#define PDS_TOUCH_RAW_DATA_CH0_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH0_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH0_POS))
+
+/* 0xA3C : Channel_raw_data_1 */
+#define PDS_CHANNEL_RAW_DATA_1_OFFSET (0xA3C)
+#define PDS_TOUCH_RAW_DATA_CH1 PDS_TOUCH_RAW_DATA_CH1
+#define PDS_TOUCH_RAW_DATA_CH1_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH1_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH1_MSK (((1U << PDS_TOUCH_RAW_DATA_CH1_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH1_POS)
+#define PDS_TOUCH_RAW_DATA_CH1_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH1_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH1_POS))
+
+/* 0xA40 : Channel_raw_data_2 */
+#define PDS_CHANNEL_RAW_DATA_2_OFFSET (0xA40)
+#define PDS_TOUCH_RAW_DATA_CH2 PDS_TOUCH_RAW_DATA_CH2
+#define PDS_TOUCH_RAW_DATA_CH2_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH2_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH2_MSK (((1U << PDS_TOUCH_RAW_DATA_CH2_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH2_POS)
+#define PDS_TOUCH_RAW_DATA_CH2_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH2_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH2_POS))
+
+/* 0xA44 : Channel_raw_data_3 */
+#define PDS_CHANNEL_RAW_DATA_3_OFFSET (0xA44)
+#define PDS_TOUCH_RAW_DATA_CH3 PDS_TOUCH_RAW_DATA_CH3
+#define PDS_TOUCH_RAW_DATA_CH3_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH3_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH3_MSK (((1U << PDS_TOUCH_RAW_DATA_CH3_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH3_POS)
+#define PDS_TOUCH_RAW_DATA_CH3_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH3_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH3_POS))
+
+/* 0xA48 : Channel_raw_data_4 */
+#define PDS_CHANNEL_RAW_DATA_4_OFFSET (0xA48)
+#define PDS_TOUCH_RAW_DATA_CH4 PDS_TOUCH_RAW_DATA_CH4
+#define PDS_TOUCH_RAW_DATA_CH4_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH4_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH4_MSK (((1U << PDS_TOUCH_RAW_DATA_CH4_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH4_POS)
+#define PDS_TOUCH_RAW_DATA_CH4_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH4_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH4_POS))
+
+/* 0xA4C : Channel_raw_data_5 */
+#define PDS_CHANNEL_RAW_DATA_5_OFFSET (0xA4C)
+#define PDS_TOUCH_RAW_DATA_CH5 PDS_TOUCH_RAW_DATA_CH5
+#define PDS_TOUCH_RAW_DATA_CH5_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH5_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH5_MSK (((1U << PDS_TOUCH_RAW_DATA_CH5_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH5_POS)
+#define PDS_TOUCH_RAW_DATA_CH5_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH5_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH5_POS))
+
+/* 0xA50 : Channel_raw_data_6 */
+#define PDS_CHANNEL_RAW_DATA_6_OFFSET (0xA50)
+#define PDS_TOUCH_RAW_DATA_CH6 PDS_TOUCH_RAW_DATA_CH6
+#define PDS_TOUCH_RAW_DATA_CH6_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH6_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH6_MSK (((1U << PDS_TOUCH_RAW_DATA_CH6_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH6_POS)
+#define PDS_TOUCH_RAW_DATA_CH6_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH6_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH6_POS))
+
+/* 0xA54 : Channel_raw_data_7 */
+#define PDS_CHANNEL_RAW_DATA_7_OFFSET (0xA54)
+#define PDS_TOUCH_RAW_DATA_CH7 PDS_TOUCH_RAW_DATA_CH7
+#define PDS_TOUCH_RAW_DATA_CH7_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH7_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH7_MSK (((1U << PDS_TOUCH_RAW_DATA_CH7_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH7_POS)
+#define PDS_TOUCH_RAW_DATA_CH7_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH7_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH7_POS))
+
+/* 0xA58 : Channel_raw_data_8 */
+#define PDS_CHANNEL_RAW_DATA_8_OFFSET (0xA58)
+#define PDS_TOUCH_RAW_DATA_CH8 PDS_TOUCH_RAW_DATA_CH8
+#define PDS_TOUCH_RAW_DATA_CH8_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH8_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH8_MSK (((1U << PDS_TOUCH_RAW_DATA_CH8_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH8_POS)
+#define PDS_TOUCH_RAW_DATA_CH8_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH8_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH8_POS))
+
+/* 0xA5C : Channel_raw_data_9 */
+#define PDS_CHANNEL_RAW_DATA_9_OFFSET (0xA5C)
+#define PDS_TOUCH_RAW_DATA_CH9 PDS_TOUCH_RAW_DATA_CH9
+#define PDS_TOUCH_RAW_DATA_CH9_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH9_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH9_MSK (((1U << PDS_TOUCH_RAW_DATA_CH9_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH9_POS)
+#define PDS_TOUCH_RAW_DATA_CH9_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH9_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH9_POS))
+
+/* 0xA60 : Channel_raw_data_10 */
+#define PDS_CHANNEL_RAW_DATA_10_OFFSET (0xA60)
+#define PDS_TOUCH_RAW_DATA_CH10 PDS_TOUCH_RAW_DATA_CH10
+#define PDS_TOUCH_RAW_DATA_CH10_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH10_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH10_MSK (((1U << PDS_TOUCH_RAW_DATA_CH10_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH10_POS)
+#define PDS_TOUCH_RAW_DATA_CH10_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH10_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH10_POS))
+
+/* 0xA64 : Channel_raw_data_11 */
+#define PDS_CHANNEL_RAW_DATA_11_OFFSET (0xA64)
+#define PDS_TOUCH_RAW_DATA_CH11 PDS_TOUCH_RAW_DATA_CH11
+#define PDS_TOUCH_RAW_DATA_CH11_POS (0U)
+#define PDS_TOUCH_RAW_DATA_CH11_LEN (16U)
+#define PDS_TOUCH_RAW_DATA_CH11_MSK (((1U << PDS_TOUCH_RAW_DATA_CH11_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH11_POS)
+#define PDS_TOUCH_RAW_DATA_CH11_UMSK (~(((1U << PDS_TOUCH_RAW_DATA_CH11_LEN) - 1) << PDS_TOUCH_RAW_DATA_CH11_POS))
+
+/* 0xA68 : Channel_LTA_data_0 */
+#define PDS_CHANNEL_LTA_DATA_0_OFFSET (0xA68)
+#define PDS_TOUCH_LTA_DATA_CH0 PDS_TOUCH_LTA_DATA_CH0
+#define PDS_TOUCH_LTA_DATA_CH0_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH0_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH0_MSK (((1U << PDS_TOUCH_LTA_DATA_CH0_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH0_POS)
+#define PDS_TOUCH_LTA_DATA_CH0_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH0_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH0_POS))
+
+/* 0xA6C : Channel_LTA_data_1 */
+#define PDS_CHANNEL_LTA_DATA_1_OFFSET (0xA6C)
+#define PDS_TOUCH_LTA_DATA_CH1 PDS_TOUCH_LTA_DATA_CH1
+#define PDS_TOUCH_LTA_DATA_CH1_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH1_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH1_MSK (((1U << PDS_TOUCH_LTA_DATA_CH1_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH1_POS)
+#define PDS_TOUCH_LTA_DATA_CH1_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH1_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH1_POS))
+
+/* 0xA70 : Channel_LTA_data_2 */
+#define PDS_CHANNEL_LTA_DATA_2_OFFSET (0xA70)
+#define PDS_TOUCH_LTA_DATA_CH2 PDS_TOUCH_LTA_DATA_CH2
+#define PDS_TOUCH_LTA_DATA_CH2_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH2_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH2_MSK (((1U << PDS_TOUCH_LTA_DATA_CH2_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH2_POS)
+#define PDS_TOUCH_LTA_DATA_CH2_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH2_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH2_POS))
+
+/* 0xA74 : Channel_LTA_data_3 */
+#define PDS_CHANNEL_LTA_DATA_3_OFFSET (0xA74)
+#define PDS_TOUCH_LTA_DATA_CH3 PDS_TOUCH_LTA_DATA_CH3
+#define PDS_TOUCH_LTA_DATA_CH3_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH3_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH3_MSK (((1U << PDS_TOUCH_LTA_DATA_CH3_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH3_POS)
+#define PDS_TOUCH_LTA_DATA_CH3_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH3_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH3_POS))
+
+/* 0xA78 : Channel_LTA_data_4 */
+#define PDS_CHANNEL_LTA_DATA_4_OFFSET (0xA78)
+#define PDS_TOUCH_LTA_DATA_CH4 PDS_TOUCH_LTA_DATA_CH4
+#define PDS_TOUCH_LTA_DATA_CH4_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH4_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH4_MSK (((1U << PDS_TOUCH_LTA_DATA_CH4_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH4_POS)
+#define PDS_TOUCH_LTA_DATA_CH4_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH4_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH4_POS))
+
+/* 0xA7C : Channel_LTA_data_5 */
+#define PDS_CHANNEL_LTA_DATA_5_OFFSET (0xA7C)
+#define PDS_TOUCH_LTA_DATA_CH5 PDS_TOUCH_LTA_DATA_CH5
+#define PDS_TOUCH_LTA_DATA_CH5_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH5_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH5_MSK (((1U << PDS_TOUCH_LTA_DATA_CH5_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH5_POS)
+#define PDS_TOUCH_LTA_DATA_CH5_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH5_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH5_POS))
+
+/* 0xA80 : Channel_LTA_data_6 */
+#define PDS_CHANNEL_LTA_DATA_6_OFFSET (0xA80)
+#define PDS_TOUCH_LTA_DATA_CH6 PDS_TOUCH_LTA_DATA_CH6
+#define PDS_TOUCH_LTA_DATA_CH6_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH6_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH6_MSK (((1U << PDS_TOUCH_LTA_DATA_CH6_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH6_POS)
+#define PDS_TOUCH_LTA_DATA_CH6_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH6_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH6_POS))
+
+/* 0xA84 : Channel_LTA_data_7 */
+#define PDS_CHANNEL_LTA_DATA_7_OFFSET (0xA84)
+#define PDS_TOUCH_LTA_DATA_CH7 PDS_TOUCH_LTA_DATA_CH7
+#define PDS_TOUCH_LTA_DATA_CH7_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH7_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH7_MSK (((1U << PDS_TOUCH_LTA_DATA_CH7_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH7_POS)
+#define PDS_TOUCH_LTA_DATA_CH7_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH7_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH7_POS))
+
+/* 0xA88 : Channel_LTA_data_8 */
+#define PDS_CHANNEL_LTA_DATA_8_OFFSET (0xA88)
+#define PDS_TOUCH_LTA_DATA_CH8 PDS_TOUCH_LTA_DATA_CH8
+#define PDS_TOUCH_LTA_DATA_CH8_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH8_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH8_MSK (((1U << PDS_TOUCH_LTA_DATA_CH8_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH8_POS)
+#define PDS_TOUCH_LTA_DATA_CH8_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH8_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH8_POS))
+
+/* 0xA8C : Channel_LTA_data_9 */
+#define PDS_CHANNEL_LTA_DATA_9_OFFSET (0xA8C)
+#define PDS_TOUCH_LTA_DATA_CH9 PDS_TOUCH_LTA_DATA_CH9
+#define PDS_TOUCH_LTA_DATA_CH9_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH9_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH9_MSK (((1U << PDS_TOUCH_LTA_DATA_CH9_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH9_POS)
+#define PDS_TOUCH_LTA_DATA_CH9_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH9_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH9_POS))
+
+/* 0xA90 : Channel_LTA_data_10 */
+#define PDS_CHANNEL_LTA_DATA_10_OFFSET (0xA90)
+#define PDS_TOUCH_LTA_DATA_CH10 PDS_TOUCH_LTA_DATA_CH10
+#define PDS_TOUCH_LTA_DATA_CH10_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH10_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH10_MSK (((1U << PDS_TOUCH_LTA_DATA_CH10_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH10_POS)
+#define PDS_TOUCH_LTA_DATA_CH10_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH10_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH10_POS))
+
+/* 0xA94 : Channel_LTA_data_11 */
+#define PDS_CHANNEL_LTA_DATA_11_OFFSET (0xA94)
+#define PDS_TOUCH_LTA_DATA_CH11 PDS_TOUCH_LTA_DATA_CH11
+#define PDS_TOUCH_LTA_DATA_CH11_POS (0U)
+#define PDS_TOUCH_LTA_DATA_CH11_LEN (16U)
+#define PDS_TOUCH_LTA_DATA_CH11_MSK (((1U << PDS_TOUCH_LTA_DATA_CH11_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH11_POS)
+#define PDS_TOUCH_LTA_DATA_CH11_UMSK (~(((1U << PDS_TOUCH_LTA_DATA_CH11_LEN) - 1) << PDS_TOUCH_LTA_DATA_CH11_POS))
+
+/* 0xA98 : Channel_FLT_data_0 */
+#define PDS_CHANNEL_FLT_DATA_0_OFFSET (0xA98)
+#define PDS_TOUCH_FLT_DATA_CH0 PDS_TOUCH_FLT_DATA_CH0
+#define PDS_TOUCH_FLT_DATA_CH0_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH0_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH0_MSK (((1U << PDS_TOUCH_FLT_DATA_CH0_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH0_POS)
+#define PDS_TOUCH_FLT_DATA_CH0_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH0_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH0_POS))
+
+/* 0xA9C : Channel_FLT_data_1 */
+#define PDS_CHANNEL_FLT_DATA_1_OFFSET (0xA9C)
+#define PDS_TOUCH_FLT_DATA_CH1 PDS_TOUCH_FLT_DATA_CH1
+#define PDS_TOUCH_FLT_DATA_CH1_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH1_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH1_MSK (((1U << PDS_TOUCH_FLT_DATA_CH1_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH1_POS)
+#define PDS_TOUCH_FLT_DATA_CH1_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH1_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH1_POS))
+
+/* 0xAA0 : Channel_FLT_data_2 */
+#define PDS_CHANNEL_FLT_DATA_2_OFFSET (0xAA0)
+#define PDS_TOUCH_FLT_DATA_CH2 PDS_TOUCH_FLT_DATA_CH2
+#define PDS_TOUCH_FLT_DATA_CH2_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH2_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH2_MSK (((1U << PDS_TOUCH_FLT_DATA_CH2_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH2_POS)
+#define PDS_TOUCH_FLT_DATA_CH2_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH2_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH2_POS))
+
+/* 0xAA4 : Channel_FLT_data_3 */
+#define PDS_CHANNEL_FLT_DATA_3_OFFSET (0xAA4)
+#define PDS_TOUCH_FLT_DATA_CH3 PDS_TOUCH_FLT_DATA_CH3
+#define PDS_TOUCH_FLT_DATA_CH3_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH3_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH3_MSK (((1U << PDS_TOUCH_FLT_DATA_CH3_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH3_POS)
+#define PDS_TOUCH_FLT_DATA_CH3_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH3_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH3_POS))
+
+/* 0xAA8 : Channel_FLT_data_4 */
+#define PDS_CHANNEL_FLT_DATA_4_OFFSET (0xAA8)
+#define PDS_TOUCH_FLT_DATA_CH4 PDS_TOUCH_FLT_DATA_CH4
+#define PDS_TOUCH_FLT_DATA_CH4_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH4_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH4_MSK (((1U << PDS_TOUCH_FLT_DATA_CH4_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH4_POS)
+#define PDS_TOUCH_FLT_DATA_CH4_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH4_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH4_POS))
+
+/* 0xAAC : Channel_FLT_data_5 */
+#define PDS_CHANNEL_FLT_DATA_5_OFFSET (0xAAC)
+#define PDS_TOUCH_FLT_DATA_CH5 PDS_TOUCH_FLT_DATA_CH5
+#define PDS_TOUCH_FLT_DATA_CH5_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH5_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH5_MSK (((1U << PDS_TOUCH_FLT_DATA_CH5_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH5_POS)
+#define PDS_TOUCH_FLT_DATA_CH5_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH5_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH5_POS))
+
+/* 0xAB0 : Channel_FLT_data_6 */
+#define PDS_CHANNEL_FLT_DATA_6_OFFSET (0xAB0)
+#define PDS_TOUCH_FLT_DATA_CH6 PDS_TOUCH_FLT_DATA_CH6
+#define PDS_TOUCH_FLT_DATA_CH6_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH6_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH6_MSK (((1U << PDS_TOUCH_FLT_DATA_CH6_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH6_POS)
+#define PDS_TOUCH_FLT_DATA_CH6_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH6_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH6_POS))
+
+/* 0xAB4 : Channel_FLT_data_7 */
+#define PDS_CHANNEL_FLT_DATA_7_OFFSET (0xAB4)
+#define PDS_TOUCH_FLT_DATA_CH7 PDS_TOUCH_FLT_DATA_CH7
+#define PDS_TOUCH_FLT_DATA_CH7_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH7_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH7_MSK (((1U << PDS_TOUCH_FLT_DATA_CH7_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH7_POS)
+#define PDS_TOUCH_FLT_DATA_CH7_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH7_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH7_POS))
+
+/* 0xAB8 : Channel_FLT_data_8 */
+#define PDS_CHANNEL_FLT_DATA_8_OFFSET (0xAB8)
+#define PDS_TOUCH_FLT_DATA_CH8 PDS_TOUCH_FLT_DATA_CH8
+#define PDS_TOUCH_FLT_DATA_CH8_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH8_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH8_MSK (((1U << PDS_TOUCH_FLT_DATA_CH8_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH8_POS)
+#define PDS_TOUCH_FLT_DATA_CH8_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH8_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH8_POS))
+
+/* 0xABC : Channel_FLT_data_9 */
+#define PDS_CHANNEL_FLT_DATA_9_OFFSET (0xABC)
+#define PDS_TOUCH_FLT_DATA_CH9 PDS_TOUCH_FLT_DATA_CH9
+#define PDS_TOUCH_FLT_DATA_CH9_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH9_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH9_MSK (((1U << PDS_TOUCH_FLT_DATA_CH9_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH9_POS)
+#define PDS_TOUCH_FLT_DATA_CH9_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH9_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH9_POS))
+
+/* 0xAC0 : Channel_FLT_data_10 */
+#define PDS_CHANNEL_FLT_DATA_10_OFFSET (0xAC0)
+#define PDS_TOUCH_FLT_DATA_CH10 PDS_TOUCH_FLT_DATA_CH10
+#define PDS_TOUCH_FLT_DATA_CH10_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH10_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH10_MSK (((1U << PDS_TOUCH_FLT_DATA_CH10_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH10_POS)
+#define PDS_TOUCH_FLT_DATA_CH10_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH10_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH10_POS))
+
+/* 0xAC4 : Channel_FLT_data_11 */
+#define PDS_CHANNEL_FLT_DATA_11_OFFSET (0xAC4)
+#define PDS_TOUCH_FLT_DATA_CH11 PDS_TOUCH_FLT_DATA_CH11
+#define PDS_TOUCH_FLT_DATA_CH11_POS (0U)
+#define PDS_TOUCH_FLT_DATA_CH11_LEN (16U)
+#define PDS_TOUCH_FLT_DATA_CH11_MSK (((1U << PDS_TOUCH_FLT_DATA_CH11_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH11_POS)
+#define PDS_TOUCH_FLT_DATA_CH11_UMSK (~(((1U << PDS_TOUCH_FLT_DATA_CH11_LEN) - 1) << PDS_TOUCH_FLT_DATA_CH11_POS))
+
+/* 0xAC8 : touch_rsvd */
+#define PDS_TOUCH_RSVD_OFFSET (0xAC8)
+#define PDS_TOUCH_RESERVED PDS_TOUCH_RESERVED
+#define PDS_TOUCH_RESERVED_POS (0U)
+#define PDS_TOUCH_RESERVED_LEN (8U)
+#define PDS_TOUCH_RESERVED_MSK (((1U << PDS_TOUCH_RESERVED_LEN) - 1) << PDS_TOUCH_RESERVED_POS)
+#define PDS_TOUCH_RESERVED_UMSK (~(((1U << PDS_TOUCH_RESERVED_LEN) - 1) << PDS_TOUCH_RESERVED_POS))
+
+/* 0xACC : touch_int_setting */
+#define PDS_TOUCH_INT_SETTING_OFFSET (0xACC)
+#define PDS_TOUCH_INT_CLR PDS_TOUCH_INT_CLR
+#define PDS_TOUCH_INT_CLR_POS (0U)
+#define PDS_TOUCH_INT_CLR_LEN (12U)
+#define PDS_TOUCH_INT_CLR_MSK (((1U << PDS_TOUCH_INT_CLR_LEN) - 1) << PDS_TOUCH_INT_CLR_POS)
+#define PDS_TOUCH_INT_CLR_UMSK (~(((1U << PDS_TOUCH_INT_CLR_LEN) - 1) << PDS_TOUCH_INT_CLR_POS))
+#define PDS_TOUCH_INT_MASK PDS_TOUCH_INT_MASK
+#define PDS_TOUCH_INT_MASK_POS (16U)
+#define PDS_TOUCH_INT_MASK_LEN (12U)
+#define PDS_TOUCH_INT_MASK_MSK (((1U << PDS_TOUCH_INT_MASK_LEN) - 1) << PDS_TOUCH_INT_MASK_POS)
+#define PDS_TOUCH_INT_MASK_UMSK (~(((1U << PDS_TOUCH_INT_MASK_LEN) - 1) << PDS_TOUCH_INT_MASK_POS))
+#define PDS_TOUCH_INT_EN PDS_TOUCH_INT_EN
+#define PDS_TOUCH_INT_EN_POS (31U)
+#define PDS_TOUCH_INT_EN_LEN (1U)
+#define PDS_TOUCH_INT_EN_MSK (((1U << PDS_TOUCH_INT_EN_LEN) - 1) << PDS_TOUCH_INT_EN_POS)
+#define PDS_TOUCH_INT_EN_UMSK (~(((1U << PDS_TOUCH_INT_EN_LEN) - 1) << PDS_TOUCH_INT_EN_POS))
+
+/* 0xAD0 : touch_int_status */
+#define PDS_TOUCH_INT_STATUS_OFFSET (0xAD0)
+#define PDS_TOUCH_INT_STATUS PDS_TOUCH_INT_STATUS
+#define PDS_TOUCH_INT_STATUS_POS (0U)
+#define PDS_TOUCH_INT_STATUS_LEN (12U)
+#define PDS_TOUCH_INT_STATUS_MSK (((1U << PDS_TOUCH_INT_STATUS_LEN) - 1) << PDS_TOUCH_INT_STATUS_POS)
+#define PDS_TOUCH_INT_STATUS_UMSK (~(((1U << PDS_TOUCH_INT_STATUS_LEN) - 1) << PDS_TOUCH_INT_STATUS_POS))
+#define PDS_TOUCH_END_FLAG PDS_TOUCH_END_FLAG
+#define PDS_TOUCH_END_FLAG_POS (12U)
+#define PDS_TOUCH_END_FLAG_LEN (1U)
+#define PDS_TOUCH_END_FLAG_MSK (((1U << PDS_TOUCH_END_FLAG_LEN) - 1) << PDS_TOUCH_END_FLAG_POS)
+#define PDS_TOUCH_END_FLAG_UMSK (~(((1U << PDS_TOUCH_END_FLAG_LEN) - 1) << PDS_TOUCH_END_FLAG_POS))
+
+struct pds_reg {
+ /* 0x0 : PDS_CTL */
+ union {
+ struct {
+ uint32_t pds_start_ps : 1; /* [ 0], w1p, 0x0 */
+ uint32_t cr_sleep_forever : 1; /* [ 1], r/w, 0x0 */
+ uint32_t cr_xtal_force_off : 1; /* [ 2], r/w, 0x0 */
+ uint32_t cr_pds_wifi_save_state : 1; /* [ 3], r/w, 0x0 */
+ uint32_t cr_pds_pd_dcdc11 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t cr_pds_pd_bg_sys : 1; /* [ 5], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_gpio_ie_pu_pd : 1; /* [ 6], r/w, 0x0 */
+ uint32_t cr_pds_pd_dcdc18 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t cr_pds_gate_clk : 1; /* [ 8], r/w, 0x1 */
+ uint32_t cr_pds_mem_stby : 1; /* [ 9], r/w, 0x1 */
+ uint32_t cr_pds_glb_reg_reset_protect : 1; /* [ 10], r/w, 0x0 */
+ uint32_t cr_pds_iso_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t cr_pds_wait_xtal_rdy : 1; /* [ 12], r/w, 0x0 */
+ uint32_t cr_pds_pwr_off : 1; /* [ 13], r/w, 0x1 */
+ uint32_t cr_pds_pd_xtal : 1; /* [ 14], r/w, 0x1 */
+ uint32_t cr_pds_ctrl_soc_enb : 1; /* [ 15], r/w, 0x0 */
+ uint32_t cr_pds_rst_soc : 1; /* [ 16], r/w, 0x0 */
+ uint32_t cr_pds_rc32m_off_dis : 1; /* [ 17], r/w, 0x0 */
+ uint32_t cr_pds_dcdc11_vsel_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_usbpll_pd : 1; /* [ 19], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_aupll_pd : 1; /* [ 20], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_cpupll_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_wifipll_pd : 1; /* [ 22], r/w, 0x0 */
+ uint32_t cr_pds_dcdc11_vol : 5; /* [27:23], r/w, 0x8 */
+ uint32_t cr_pds_ctrl_rf : 2; /* [29:28], r/w, 0x1 */
+ uint32_t cr_pds_start_use_tbtt_sleep : 1; /* [ 30], r/w, 0x0 */
+ uint32_t cr_pds_gpio_iso_mode : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } PDS_CTL;
+
+ /* 0x4 : PDS_TIME1 */
+ union {
+ struct {
+ uint32_t cr_sleep_duration : 32; /* [31: 0], r/w, 0xca8 */
+ } BF;
+ uint32_t WORD;
+ } PDS_TIME1;
+
+ /* 0x8 reserved */
+ uint8_t RESERVED0x8[4];
+
+ /* 0xC : PDS_INT */
+ union {
+ struct {
+ uint32_t ro_pds_wake_int : 1; /* [ 0], r, 0x0 */
+ uint32_t ro_pds_rf_done_int : 1; /* [ 1], r, 0x0 */
+ uint32_t ro_pds_wifi_tbtt_sleep_irq : 1; /* [ 2], r, 0x0 */
+ uint32_t ro_pds_wifi_tbtt_wakeup_irq : 1; /* [ 3], r, 0x0 */
+ uint32_t cr_pds_wake_int_mask : 1; /* [ 4], r/w, 0x0 */
+ uint32_t cr_pds_rf_done_int_mask : 1; /* [ 5], r/w, 0x0 */
+ uint32_t cr_pds_wifi_tbtt_sleep_irq_mask : 1; /* [ 6], r/w, 0x0 */
+ uint32_t cr_pds_wifi_tbtt_wakeup_irq_mask : 1; /* [ 7], r/w, 0x0 */
+ uint32_t cr_pds_int_clr : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
+ uint32_t cr_pds_wakeup_src_en : 11; /* [20:10], r/w, 0x7ff */
+ uint32_t ro_pds_wakeup_event : 11; /* [31:21], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } PDS_INT;
+
+ /* 0x10 : PDS_CTL2 */
+ union {
+ struct {
+ uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
+ uint32_t cr_pds_force_mm_pwr_off : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */
+ uint32_t cr_pds_force_usb_pwr_off : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reserved_4 : 1; /* [ 4], rsvd, 0x0 */
+ uint32_t cr_pds_force_mm_iso_en : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t cr_pds_force_usb_iso_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t cr_pds_force_np_pds_rst : 1; /* [ 8], r/w, 0x0 */
+ uint32_t cr_pds_force_mm_pds_rst : 1; /* [ 9], r/w, 0x1 */
+ uint32_t cr_pds_force_wb_pds_rst : 1; /* [ 10], r/w, 0x0 */
+ uint32_t cr_pds_force_usb_pds_rst : 1; /* [ 11], r/w, 0x0 */
+ uint32_t cr_pds_force_np_mem_stby : 1; /* [ 12], r/w, 0x0 */
+ uint32_t cr_pds_force_mm_mem_stby : 1; /* [ 13], r/w, 0x1 */
+ uint32_t cr_pds_force_wb_mem_stby : 1; /* [ 14], r/w, 0x0 */
+ uint32_t cr_pds_force_usb_mem_stby : 1; /* [ 15], r/w, 0x0 */
+ uint32_t cr_pds_force_np_gate_clk : 1; /* [ 16], r/w, 0x0 */
+ uint32_t cr_pds_force_mm_gate_clk : 1; /* [ 17], r/w, 0x1 */
+ uint32_t cr_pds_force_wb_gate_clk : 1; /* [ 18], r/w, 0x0 */
+ uint32_t cr_pds_force_usb_gate_clk : 1; /* [ 19], r/w, 0x0 */
+ uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } PDS_CTL2;
+
+ /* 0x14 : PDS_CTL3 */
+ union {
+ struct {
+ uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
+ uint32_t cr_pds_force_misc_pwr_off : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t cr_pds_force_misc_iso_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */
+ uint32_t cr_pds_force_misc_pds_rst : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */
+ uint32_t cr_pds_force_misc_mem_stby : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_12 : 2; /* [12:11], rsvd, 0x0 */
+ uint32_t cr_pds_force_misc_gate_clk : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14_25 : 12; /* [25:14], rsvd, 0x0 */
+ uint32_t cr_pds_mm_iso_en : 1; /* [ 26], r/w, 0x1 */
+ uint32_t reserved_27_28 : 2; /* [28:27], rsvd, 0x0 */
+ uint32_t cr_pds_usb_iso_en : 1; /* [ 29], r/w, 0x1 */
+ uint32_t cr_pds_misc_iso_en : 1; /* [ 30], r/w, 0x1 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } PDS_CTL3;
+
+ /* 0x18 : PDS_CTL4 */
+ union {
+ struct {
+ uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
+ uint32_t cr_pds_np_reset : 1; /* [ 1], r/w, 0x1 */
+ uint32_t cr_pds_np_mem_stby : 1; /* [ 2], r/w, 0x1 */
+ uint32_t cr_pds_np_gate_clk : 1; /* [ 3], r/w, 0x1 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t cr_pds_mm_pwr_off : 1; /* [ 8], r/w, 0x1 */
+ uint32_t cr_pds_mm_reset : 1; /* [ 9], r/w, 0x1 */
+ uint32_t cr_pds_mm_mem_stby : 1; /* [ 10], r/w, 0x1 */
+ uint32_t cr_pds_mm_gate_clk : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */
+ uint32_t cr_pds_wb_reset : 1; /* [ 13], r/w, 0x1 */
+ uint32_t cr_pds_wb_mem_stby : 1; /* [ 14], r/w, 0x1 */
+ uint32_t cr_pds_wb_gate_clk : 1; /* [ 15], r/w, 0x1 */
+ uint32_t reserved_16_19 : 4; /* [19:16], rsvd, 0x0 */
+ uint32_t cr_pds_usb_pwr_off : 1; /* [ 20], r/w, 0x1 */
+ uint32_t cr_pds_usb_reset : 1; /* [ 21], r/w, 0x1 */
+ uint32_t cr_pds_usb_mem_stby : 1; /* [ 22], r/w, 0x1 */
+ uint32_t cr_pds_usb_gate_clk : 1; /* [ 23], r/w, 0x1 */
+ uint32_t cr_pds_misc_pwr_off : 1; /* [ 24], r/w, 0x1 */
+ uint32_t cr_pds_misc_reset : 1; /* [ 25], r/w, 0x1 */
+ uint32_t cr_pds_misc_mem_stby : 1; /* [ 26], r/w, 0x1 */
+ uint32_t cr_pds_misc_gate_clk : 1; /* [ 27], r/w, 0x1 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } PDS_CTL4;
+
+ /* 0x1C : pds_stat */
+ union {
+ struct {
+ uint32_t ro_pds_state : 5; /* [ 4: 0], r, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t ro_pds_rf_state : 5; /* [12: 8], r, 0x0 */
+ uint32_t reserved_13_23 : 11; /* [23:13], rsvd, 0x0 */
+ uint32_t pds_reset_event : 3; /* [26:24], r, 0x0 */
+ uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */
+ uint32_t pds_clr_reset_event : 1; /* [ 31], w1c, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pds_stat;
+
+ /* 0x20 : pds_ram1 */
+ union {
+ struct {
+ uint32_t cr_ocram_slp : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t cr_ocram_ret : 4; /* [ 7: 4], r/w, 0x0 */
+ uint32_t cr_pds_ram_clk_cnt : 6; /* [13: 8], r/w, 0x8 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t cr_pds_ram_clk2_cnt : 6; /* [21:16], r/w, 0x18 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t cr_pds_ctrl_np_ram_clk : 1; /* [ 24], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_mm_ram_clk : 1; /* [ 25], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_wb_ram_clk : 1; /* [ 26], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_usb_ram_clk : 1; /* [ 27], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_misc_ram_clk : 1; /* [ 28], r/w, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t cr_pds_ctrl_ram_clk2 : 1; /* [ 30], r/w, 0x0 */
+ uint32_t cr_pds_ctrl_ram_clk : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pds_ram1;
+
+ /* 0x24 : PDS_CTL5 */
+ union {
+ struct {
+ uint32_t cr_np_wfi_mask : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
+ uint32_t cr_mm_wfi_mask : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t cr_pico_wfi_mask : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t cr_pds_ctrl_usb33 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t cr_pds_pd_ldo18io : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t cr_pds_gpio_keep_en : 3; /* [18:16], r/w, 0x7 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } PDS_CTL5;
+
+ /* 0x28 : PDS_RAM2 */
+ union {
+ struct {
+ uint32_t cr_wram_slp : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t cr_wram_ret : 10; /* [19:10], r/w, 0x0 */
+ uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } PDS_RAM2;
+
+ /* 0x2c reserved */
+ uint8_t RESERVED0x2c[4];
+
+ /* 0x30 : pds_gpio_i_set */
+ union {
+ struct {
+ uint32_t cr_pds_gpio_ie_set : 3; /* [ 2: 0], r/w, 0x0 */
+ uint32_t cr_pds_gpio_pd_set : 3; /* [ 5: 3], r/w, 0x0 */
+ uint32_t cr_pds_gpio_pu_set : 3; /* [ 8: 6], r/w, 0x0 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pds_gpio_i_set;
+
+ /* 0x34 : pds_gpio_pd_set */
+ union {
+ struct {
+ uint32_t cr_pds_gpio_set_int_mask : 32; /* [31: 0], r/w, 0xffffffff */
+ } BF;
+ uint32_t WORD;
+ } pds_gpio_pd_set;
+
+ /* 0x38 reserved */
+ uint8_t RESERVED0x38[8];
+
+ /* 0x40 : pds_gpio_int */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t pds_gpio_set1_int_clr : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t pds_gpio_set1_int_mode : 4; /* [ 7: 4], r/w, 0x0 */
+ uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */
+ uint32_t pds_gpio_set2_int_clr : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t pds_gpio_set2_int_mode : 4; /* [15:12], r/w, 0x0 */
+ uint32_t reserved_16_17 : 2; /* [17:16], rsvd, 0x0 */
+ uint32_t pds_gpio_set3_int_clr : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t pds_gpio_set3_int_mode : 4; /* [23:20], r/w, 0x0 */
+ uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */
+ uint32_t pds_gpio_set4_int_clr : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t pds_gpio_set4_int_mode : 4; /* [31:28], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pds_gpio_int;
+
+ /* 0x44 : pds_gpio_stat */
+ union {
+ struct {
+ uint32_t pds_gpio_int_stat : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pds_gpio_stat;
+
+ /* 0x48 reserved */
+ uint8_t RESERVED0x48[200];
+
+ /* 0x110 : cpu_core_cfg0 */
+ union {
+ struct {
+ uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */
+ uint32_t reg_pico_clk_en : 1; /* [ 28], r/w, 0x0 */
+ uint32_t e902_dfs_req : 1; /* [ 29], r/w, 0x0 */
+ uint32_t e902_dfs_ack : 1; /* [ 30], r, 0x0 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg0;
+
+ /* 0x114 : cpu_core_cfg1 */
+ union {
+ struct {
+ uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */
+ uint32_t reg_pll_sel : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_mcu1_clk_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg1;
+
+ /* 0x118 reserved */
+ uint8_t RESERVED0x118[20];
+
+ /* 0x12C : cpu_core_cfg7 */
+ union {
+ struct {
+ uint32_t reg_pico_div : 8; /* [ 7: 0], r/w, 0x1 */
+ uint32_t reserved_8_27 : 20; /* [27: 8], rsvd, 0x0 */
+ uint32_t e902_lpmd_b : 2; /* [29:28], r, 0x0 */
+ uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */
+ uint32_t pico_rst_mask : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg7;
+
+ /* 0x130 : cpu_core_cfg8 */
+ union {
+ struct {
+ uint32_t e902_rtc_div : 10; /* [ 9: 0], r/w, 0xa */
+ uint32_t reserved_10_29 : 20; /* [29:10], rsvd, 0x0 */
+ uint32_t e902_rtc_rst : 1; /* [ 30], r/w, 0x0 */
+ uint32_t e902_rtc_en : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg8;
+
+ /* 0x134 : cpu_core_cfg9 */
+ union {
+ struct {
+ uint32_t pico_rtc_cnt_l : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg9;
+
+ /* 0x138 : cpu_core_cfg10 */
+ union {
+ struct {
+ uint32_t pico_rtc_cnt_h : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg10;
+
+ /* 0x13c reserved */
+ uint8_t RESERVED0x13c[4];
+
+ /* 0x140 : cpu_core_cfg12 */
+ union {
+ struct {
+ uint32_t e902_iahbl_base : 12; /* [11: 0], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t e902_iahbl_mask : 12; /* [27:16], r/w, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg12;
+
+ /* 0x144 : cpu_core_cfg13 */
+ union {
+ struct {
+ uint32_t e902_rst_addr : 32; /* [31: 0], r/w, 0x22010000 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg13;
+
+ /* 0x148 : cpu_core_cfg14 */
+ union {
+ struct {
+ uint32_t e906_rst_addr : 32; /* [31: 0], r/w, 0x90000000 */
+ } BF;
+ uint32_t WORD;
+ } cpu_core_cfg14;
+
+ /* 0x14C : tzc_pds */
+ union {
+ struct {
+ uint32_t cr_e902_cfg_wr_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t cr_e906_cfg_wr_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_pds;
+
+ /* 0x150 reserved */
+ uint8_t RESERVED0x150[432];
+
+ /* 0x300 : rc32m_ctrl0 */
+ union {
+ struct {
+ uint32_t rc32m_cal_done : 1; /* [ 0], r, 0x0 */
+ uint32_t rc32m_rdy : 1; /* [ 1], r, 0x0 */
+ uint32_t rc32m_cal_inprogress : 1; /* [ 2], r, 0x0 */
+ uint32_t rc32m_cal_div : 2; /* [ 4: 3], r/w, 0x3 */
+ uint32_t rc32m_cal_precharge : 1; /* [ 5], r, 0x0 */
+ uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6], r, 0x0 */
+ uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */
+ uint32_t rc32m_allow_cal : 1; /* [ 17], r/w, 0x0 */
+ uint32_t rc32m_refclk_half : 1; /* [ 18], r/w, 0x0 */
+ uint32_t rc32m_ext_code_en : 1; /* [ 19], r/w, 0x1 */
+ uint32_t rc32m_cal_en : 1; /* [ 20], r/w, 0x0 */
+ uint32_t rc32m_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t rc32m_code_fr_ext : 8; /* [29:22], r/w, 0x60 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } rc32m_ctrl0;
+
+ /* 0x304 : rc32m_ctrl1 */
+ union {
+ struct {
+ uint32_t rc32m_test_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t rc32m_soft_rst : 1; /* [ 1], r/w, 0x0 */
+ uint32_t rc32m_clk_soft_rst : 1; /* [ 2], r/w, 0x0 */
+ uint32_t rc32m_clk_inv : 1; /* [ 3], r/w, 0x0 */
+ uint32_t rc32m_clk_force_on : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_23 : 19; /* [23: 5], rsvd, 0x0 */
+ uint32_t rc32m_reserved : 8; /* [31:24], r/w, 0xf */
+ } BF;
+ uint32_t WORD;
+ } rc32m_ctrl1;
+
+ /* 0x308 reserved */
+ uint8_t RESERVED0x308[248];
+
+ /* 0x400 : pu_rst_clkpll */
+ union {
+ struct {
+ uint32_t reserved_0_8 : 9; /* [ 8: 0], rsvd, 0x0 */
+ uint32_t cr_pds_pu_clkpll_sfreg : 1; /* [ 9], r/w, 0x0 */
+ uint32_t cr_pds_pu_clkpll : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } pu_rst_clkpll;
+
+ /* 0x404 reserved */
+ uint8_t RESERVED0x404[252];
+
+ /* 0x500 : usb_ctl */
+ union {
+ struct {
+ uint32_t reg_usb_sw_rst_n : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_usb_ext_susp_n : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_usb_wakeup : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_usb_l1_wakeup : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg_usb_drvbus_pol : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_usb_iddig : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } usb_ctl;
+
+ /* 0x504 : usb_phy_ctrl */
+ union {
+ struct {
+ uint32_t reg_usb_phy_ponrst : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_usb_phy_oscouten : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_usb_phy_xtlsel : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_usb_phy_outclksel : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_usb_phy_pllaliv : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_pu_usb20_psw : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } usb_phy_ctrl;
+
+ /* 0x508 reserved */
+ uint8_t RESERVED0x508[1272];
+
+ /* 0xA00 : touch channel, clock, ana config1 */
+ union {
+ struct {
+ uint32_t touch_vref_sel : 3; /* [ 2: 0], r/w, 0x3 */
+ uint32_t touch_vldo_sel : 3; /* [ 5: 3], r/w, 0x3 */
+ uint32_t touch_comp_hys_sel : 1; /* [ 6], r/w, 0x0 */
+ uint32_t touch_current_sel : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */
+ uint32_t touch_clk_sel : 1; /* [ 16], r/w, 0x1 */
+ uint32_t touch_clk_div_ratio : 3; /* [19:17], r/w, 0x1 */
+ uint32_t touch_pcharge_high : 3; /* [22:20], r/w, 0x2 */
+ uint32_t touch_pcharge_low : 3; /* [25:23], r/w, 0x1 */
+ uint32_t touch_cont_en : 1; /* [ 26], r/w, 0x0 */
+ uint32_t touch_cycle_en : 1; /* [ 27], r/w, 0x0 */
+ uint32_t touch_ulp_en : 1; /* [ 28], r/w, 0x0 */
+ uint32_t reserved_29 : 1; /* [ 29], rsvd, 0x0 */
+ uint32_t pu_touch : 1; /* [ 30], r/w, 0x0 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } touch1;
+
+ /* 0xA04 : touch channel, clock, ana config2 */
+ union {
+ struct {
+ uint32_t touch_channel_sel : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t touch_channel0_highz_en : 1; /* [ 4], r/w, 0x1 */
+ uint32_t touch_channel1_highz_en : 1; /* [ 5], r/w, 0x1 */
+ uint32_t touch_channel2_highz_en : 1; /* [ 6], r/w, 0x1 */
+ uint32_t touch_channel3_highz_en : 1; /* [ 7], r/w, 0x1 */
+ uint32_t touch_channel4_highz_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t touch_channel5_highz_en : 1; /* [ 9], r/w, 0x1 */
+ uint32_t touch_channel6_highz_en : 1; /* [ 10], r/w, 0x1 */
+ uint32_t touch_channel7_highz_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t touch_channel8_highz_en : 1; /* [ 12], r/w, 0x1 */
+ uint32_t touch_channel9_highz_en : 1; /* [ 13], r/w, 0x1 */
+ uint32_t touch_channel10_highz_en : 1; /* [ 14], r/w, 0x1 */
+ uint32_t touch_channel11_highz_en : 1; /* [ 15], r/w, 0x1 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } touch2;
+
+ /* 0xA08 : touch data process */
+ union {
+ struct {
+ uint32_t touch_channel_cal_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t touch_force_value_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t touch_data_hys_en : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t touch_lta_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t touch_lta_order : 3; /* [ 7: 5], r/w, 0x3 */
+ uint32_t touch_flt_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t touch_flt_order : 3; /* [11: 9], r/w, 0x3 */
+ uint32_t touch_self_mutual_sel : 1; /* [ 12], r/w, 0x0 */
+ uint32_t touch_vldo_ccsel : 2; /* [14:13], r/w, 0x0 */
+ uint32_t reserved_15_17 : 3; /* [17:15], rsvd, 0x0 */
+ uint32_t ten_touch : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } touch3;
+
+ /* 0xA0C : Touch_sleep_time */
+ union {
+ struct {
+ uint32_t touch_sleep_cycle : 23; /* [22: 0], r/w, 0x7ffff */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Touch_sleep_time;
+
+ /* 0xA10 : touch_data_hystersis */
+ union {
+ struct {
+ uint32_t touch_data_hys : 9; /* [ 8: 0], r/w, 0x0 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } touch_data_hystersis;
+
+ /* 0xA14 : Channel_force_data_0 */
+ union {
+ struct {
+ uint32_t touch_force_data_ch0 : 16; /* [15: 0], r/w, 0x400 */
+ uint32_t touch_force_data_ch1 : 16; /* [31:16], r/w, 0x400 */
+ } BF;
+ uint32_t WORD;
+ } Channel_force_data_0;
+
+ /* 0xA18 : Channel_force_data_1 */
+ union {
+ struct {
+ uint32_t touch_force_data_ch2 : 16; /* [15: 0], r/w, 0x400 */
+ uint32_t touch_force_data_ch3 : 16; /* [31:16], r/w, 0x400 */
+ } BF;
+ uint32_t WORD;
+ } Channel_force_data_1;
+
+ /* 0xA1C : Channel_force_data_2 */
+ union {
+ struct {
+ uint32_t touch_force_data_ch4 : 16; /* [15: 0], r/w, 0x400 */
+ uint32_t touch_force_data_ch5 : 16; /* [31:16], r/w, 0x400 */
+ } BF;
+ uint32_t WORD;
+ } Channel_force_data_2;
+
+ /* 0xA20 : Channel_force_data_3 */
+ union {
+ struct {
+ uint32_t touch_force_data_ch6 : 16; /* [15: 0], r/w, 0x400 */
+ uint32_t touch_force_data_ch7 : 16; /* [31:16], r/w, 0x400 */
+ } BF;
+ uint32_t WORD;
+ } Channel_force_data_3;
+
+ /* 0xA24 : Channel_force_data_4 */
+ union {
+ struct {
+ uint32_t touch_force_data_ch8 : 16; /* [15: 0], r/w, 0x400 */
+ uint32_t touch_force_data_ch9 : 16; /* [31:16], r/w, 0x400 */
+ } BF;
+ uint32_t WORD;
+ } Channel_force_data_4;
+
+ /* 0xA28 : Channel_force_data_5 */
+ union {
+ struct {
+ uint32_t touch_force_data_ch10 : 16; /* [15: 0], r/w, 0x400 */
+ uint32_t touch_force_data_ch11 : 16; /* [31:16], r/w, 0x400 */
+ } BF;
+ uint32_t WORD;
+ } Channel_force_data_5;
+
+ /* 0xA2C : Channel_vth_data_0 */
+ union {
+ struct {
+ uint32_t touch_vth_data_ch0 : 8; /* [ 7: 0], r/w, 0x3f */
+ uint32_t touch_vth_data_ch1 : 8; /* [15: 8], r/w, 0x3f */
+ uint32_t touch_vth_data_ch2 : 8; /* [23:16], r/w, 0x3f */
+ uint32_t touch_vth_data_ch3 : 8; /* [31:24], r/w, 0x3f */
+ } BF;
+ uint32_t WORD;
+ } Channel_vth_data_0;
+
+ /* 0xA30 : Channel_vth_data_1 */
+ union {
+ struct {
+ uint32_t touch_vth_data_ch4 : 8; /* [ 7: 0], r/w, 0x1f */
+ uint32_t touch_vth_data_ch5 : 8; /* [15: 8], r/w, 0x1f */
+ uint32_t touch_vth_data_ch6 : 8; /* [23:16], r/w, 0x1f */
+ uint32_t touch_vth_data_ch7 : 8; /* [31:24], r/w, 0x3f */
+ } BF;
+ uint32_t WORD;
+ } Channel_vth_data_1;
+
+ /* 0xA34 : Channel_vth_data_2 */
+ union {
+ struct {
+ uint32_t touch_vth_data_ch8 : 8; /* [ 7: 0], r/w, 0x3f */
+ uint32_t touch_vth_data_ch9 : 8; /* [15: 8], r/w, 0x3f */
+ uint32_t touch_vth_data_ch10 : 8; /* [23:16], r/w, 0x3f */
+ uint32_t touch_vth_data_ch11 : 8; /* [31:24], r/w, 0x3f */
+ } BF;
+ uint32_t WORD;
+ } Channel_vth_data_2;
+
+ /* 0xA38 : Channel_raw_data_0 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch0 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_0;
+
+ /* 0xA3C : Channel_raw_data_1 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch1 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_1;
+
+ /* 0xA40 : Channel_raw_data_2 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch2 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_2;
+
+ /* 0xA44 : Channel_raw_data_3 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch3 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_3;
+
+ /* 0xA48 : Channel_raw_data_4 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch4 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_4;
+
+ /* 0xA4C : Channel_raw_data_5 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch5 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_5;
+
+ /* 0xA50 : Channel_raw_data_6 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch6 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_6;
+
+ /* 0xA54 : Channel_raw_data_7 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch7 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_7;
+
+ /* 0xA58 : Channel_raw_data_8 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch8 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_8;
+
+ /* 0xA5C : Channel_raw_data_9 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch9 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_9;
+
+ /* 0xA60 : Channel_raw_data_10 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch10 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_10;
+
+ /* 0xA64 : Channel_raw_data_11 */
+ union {
+ struct {
+ uint32_t touch_raw_data_ch11 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_raw_data_11;
+
+ /* 0xA68 : Channel_LTA_data_0 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch0 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_0;
+
+ /* 0xA6C : Channel_LTA_data_1 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch1 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_1;
+
+ /* 0xA70 : Channel_LTA_data_2 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch2 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_2;
+
+ /* 0xA74 : Channel_LTA_data_3 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch3 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_3;
+
+ /* 0xA78 : Channel_LTA_data_4 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch4 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_4;
+
+ /* 0xA7C : Channel_LTA_data_5 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch5 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_5;
+
+ /* 0xA80 : Channel_LTA_data_6 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch6 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_6;
+
+ /* 0xA84 : Channel_LTA_data_7 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch7 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_7;
+
+ /* 0xA88 : Channel_LTA_data_8 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch8 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_8;
+
+ /* 0xA8C : Channel_LTA_data_9 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch9 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_9;
+
+ /* 0xA90 : Channel_LTA_data_10 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch10 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_10;
+
+ /* 0xA94 : Channel_LTA_data_11 */
+ union {
+ struct {
+ uint32_t touch_lta_data_ch11 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_LTA_data_11;
+
+ /* 0xA98 : Channel_FLT_data_0 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch0 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_0;
+
+ /* 0xA9C : Channel_FLT_data_1 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch1 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_1;
+
+ /* 0xAA0 : Channel_FLT_data_2 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch2 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_2;
+
+ /* 0xAA4 : Channel_FLT_data_3 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch3 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_3;
+
+ /* 0xAA8 : Channel_FLT_data_4 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch4 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_4;
+
+ /* 0xAAC : Channel_FLT_data_5 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch5 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_5;
+
+ /* 0xAB0 : Channel_FLT_data_6 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch6 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_6;
+
+ /* 0xAB4 : Channel_FLT_data_7 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch7 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_7;
+
+ /* 0xAB8 : Channel_FLT_data_8 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch8 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_8;
+
+ /* 0xABC : Channel_FLT_data_9 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch9 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_9;
+
+ /* 0xAC0 : Channel_FLT_data_10 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch10 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_10;
+
+ /* 0xAC4 : Channel_FLT_data_11 */
+ union {
+ struct {
+ uint32_t touch_flt_data_ch11 : 16; /* [15: 0], R, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } Channel_FLT_data_11;
+
+ /* 0xAC8 : touch_rsvd */
+ union {
+ struct {
+ uint32_t touch_reserved : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } touch_rsvd;
+
+ /* 0xACC : touch_int_setting */
+ union {
+ struct {
+ uint32_t touch_int_clr : 12; /* [11: 0], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t touch_int_mask : 12; /* [27:16], r/w, 0x0 */
+ uint32_t reserved_28_30 : 3; /* [30:28], rsvd, 0x0 */
+ uint32_t touch_int_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } touch_int_setting;
+
+ /* 0xAD0 : touch_int_status */
+ union {
+ struct {
+ uint32_t touch_int_status : 12; /* [11: 0], R, 0x0 */
+ uint32_t touch_end_flag : 1; /* [ 12], R, 0x0 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } touch_int_status;
+};
+
+typedef volatile struct pds_reg pds_reg_t;
+
+#endif /* __PDS_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/psram_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/psram_reg.h
new file mode 100644
index 00000000..74c25f62
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/psram_reg.h
@@ -0,0 +1,1551 @@
+/**
+ ******************************************************************************
+ * @file psram_reg.h
+ * @version V1.0
+ * @date 2021-03-17
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __PSRAM_REG_H__
+#define __PSRAM_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : psram_configure */
+#define PSRAM_CONFIGURE_OFFSET (0x0)
+#define PSRAM_REG_VENDOR_SEL PSRAM_REG_VENDOR_SEL
+#define PSRAM_REG_VENDOR_SEL_POS (0U)
+#define PSRAM_REG_VENDOR_SEL_LEN (3U)
+#define PSRAM_REG_VENDOR_SEL_MSK (((1U << PSRAM_REG_VENDOR_SEL_LEN) - 1) << PSRAM_REG_VENDOR_SEL_POS)
+#define PSRAM_REG_VENDOR_SEL_UMSK (~(((1U << PSRAM_REG_VENDOR_SEL_LEN) - 1) << PSRAM_REG_VENDOR_SEL_POS))
+#define PSRAM_REG_AP_MR PSRAM_REG_AP_MR
+#define PSRAM_REG_AP_MR_POS (4U)
+#define PSRAM_REG_AP_MR_LEN (3U)
+#define PSRAM_REG_AP_MR_MSK (((1U << PSRAM_REG_AP_MR_LEN) - 1) << PSRAM_REG_AP_MR_POS)
+#define PSRAM_REG_AP_MR_UMSK (~(((1U << PSRAM_REG_AP_MR_LEN) - 1) << PSRAM_REG_AP_MR_POS))
+#define PSRAM_REG_WB_REG_SEL PSRAM_REG_WB_REG_SEL
+#define PSRAM_REG_WB_REG_SEL_POS (8U)
+#define PSRAM_REG_WB_REG_SEL_LEN (3U)
+#define PSRAM_REG_WB_REG_SEL_MSK (((1U << PSRAM_REG_WB_REG_SEL_LEN) - 1) << PSRAM_REG_WB_REG_SEL_POS)
+#define PSRAM_REG_WB_REG_SEL_UMSK (~(((1U << PSRAM_REG_WB_REG_SEL_LEN) - 1) << PSRAM_REG_WB_REG_SEL_POS))
+#define PSRAM_REG_CONFIG_W_PUSLE PSRAM_REG_CONFIG_W_PUSLE
+#define PSRAM_REG_CONFIG_W_PUSLE_POS (12U)
+#define PSRAM_REG_CONFIG_W_PUSLE_LEN (1U)
+#define PSRAM_REG_CONFIG_W_PUSLE_MSK (((1U << PSRAM_REG_CONFIG_W_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_W_PUSLE_POS)
+#define PSRAM_REG_CONFIG_W_PUSLE_UMSK (~(((1U << PSRAM_REG_CONFIG_W_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_W_PUSLE_POS))
+#define PSRAM_REG_CONFIG_R_PUSLE PSRAM_REG_CONFIG_R_PUSLE
+#define PSRAM_REG_CONFIG_R_PUSLE_POS (13U)
+#define PSRAM_REG_CONFIG_R_PUSLE_LEN (1U)
+#define PSRAM_REG_CONFIG_R_PUSLE_MSK (((1U << PSRAM_REG_CONFIG_R_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_R_PUSLE_POS)
+#define PSRAM_REG_CONFIG_R_PUSLE_UMSK (~(((1U << PSRAM_REG_CONFIG_R_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_R_PUSLE_POS))
+#define PSRAM_STS_CONFIG_W_DONE PSRAM_STS_CONFIG_W_DONE
+#define PSRAM_STS_CONFIG_W_DONE_POS (14U)
+#define PSRAM_STS_CONFIG_W_DONE_LEN (1U)
+#define PSRAM_STS_CONFIG_W_DONE_MSK (((1U << PSRAM_STS_CONFIG_W_DONE_LEN) - 1) << PSRAM_STS_CONFIG_W_DONE_POS)
+#define PSRAM_STS_CONFIG_W_DONE_UMSK (~(((1U << PSRAM_STS_CONFIG_W_DONE_LEN) - 1) << PSRAM_STS_CONFIG_W_DONE_POS))
+#define PSRAM_STS_CONFIG_R_DONE PSRAM_STS_CONFIG_R_DONE
+#define PSRAM_STS_CONFIG_R_DONE_POS (15U)
+#define PSRAM_STS_CONFIG_R_DONE_LEN (1U)
+#define PSRAM_STS_CONFIG_R_DONE_MSK (((1U << PSRAM_STS_CONFIG_R_DONE_LEN) - 1) << PSRAM_STS_CONFIG_R_DONE_POS)
+#define PSRAM_STS_CONFIG_R_DONE_UMSK (~(((1U << PSRAM_STS_CONFIG_R_DONE_LEN) - 1) << PSRAM_STS_CONFIG_R_DONE_POS))
+#define PSRAM_REG_CONFIG_REQ PSRAM_REG_CONFIG_REQ
+#define PSRAM_REG_CONFIG_REQ_POS (16U)
+#define PSRAM_REG_CONFIG_REQ_LEN (1U)
+#define PSRAM_REG_CONFIG_REQ_MSK (((1U << PSRAM_REG_CONFIG_REQ_LEN) - 1) << PSRAM_REG_CONFIG_REQ_POS)
+#define PSRAM_REG_CONFIG_REQ_UMSK (~(((1U << PSRAM_REG_CONFIG_REQ_LEN) - 1) << PSRAM_REG_CONFIG_REQ_POS))
+#define PSRAM_REG_CONFIG_GNT PSRAM_REG_CONFIG_GNT
+#define PSRAM_REG_CONFIG_GNT_POS (17U)
+#define PSRAM_REG_CONFIG_GNT_LEN (1U)
+#define PSRAM_REG_CONFIG_GNT_MSK (((1U << PSRAM_REG_CONFIG_GNT_LEN) - 1) << PSRAM_REG_CONFIG_GNT_POS)
+#define PSRAM_REG_CONFIG_GNT_UMSK (~(((1U << PSRAM_REG_CONFIG_GNT_LEN) - 1) << PSRAM_REG_CONFIG_GNT_POS))
+#define PSRAM_REG_X16_MODE PSRAM_REG_X16_MODE
+#define PSRAM_REG_X16_MODE_POS (18U)
+#define PSRAM_REG_X16_MODE_LEN (1U)
+#define PSRAM_REG_X16_MODE_MSK (((1U << PSRAM_REG_X16_MODE_LEN) - 1) << PSRAM_REG_X16_MODE_POS)
+#define PSRAM_REG_X16_MODE_UMSK (~(((1U << PSRAM_REG_X16_MODE_LEN) - 1) << PSRAM_REG_X16_MODE_POS))
+#define PSRAM_REG_WB_HYPER3 PSRAM_REG_WB_HYPER3
+#define PSRAM_REG_WB_HYPER3_POS (19U)
+#define PSRAM_REG_WB_HYPER3_LEN (1U)
+#define PSRAM_REG_WB_HYPER3_MSK (((1U << PSRAM_REG_WB_HYPER3_LEN) - 1) << PSRAM_REG_WB_HYPER3_POS)
+#define PSRAM_REG_WB_HYPER3_UMSK (~(((1U << PSRAM_REG_WB_HYPER3_LEN) - 1) << PSRAM_REG_WB_HYPER3_POS))
+#define PSRAM_REG_PCK_S_DIV PSRAM_REG_PCK_S_DIV
+#define PSRAM_REG_PCK_S_DIV_POS (20U)
+#define PSRAM_REG_PCK_S_DIV_LEN (3U)
+#define PSRAM_REG_PCK_S_DIV_MSK (((1U << PSRAM_REG_PCK_S_DIV_LEN) - 1) << PSRAM_REG_PCK_S_DIV_POS)
+#define PSRAM_REG_PCK_S_DIV_UMSK (~(((1U << PSRAM_REG_PCK_S_DIV_LEN) - 1) << PSRAM_REG_PCK_S_DIV_POS))
+#define PSRAM_REG_CLKN_FREE PSRAM_REG_CLKN_FREE
+#define PSRAM_REG_CLKN_FREE_POS (23U)
+#define PSRAM_REG_CLKN_FREE_LEN (1U)
+#define PSRAM_REG_CLKN_FREE_MSK (((1U << PSRAM_REG_CLKN_FREE_LEN) - 1) << PSRAM_REG_CLKN_FREE_POS)
+#define PSRAM_REG_CLKN_FREE_UMSK (~(((1U << PSRAM_REG_CLKN_FREE_LEN) - 1) << PSRAM_REG_CLKN_FREE_POS))
+#define PSRAM_REG_LINEAR_BND_B PSRAM_REG_LINEAR_BND_B
+#define PSRAM_REG_LINEAR_BND_B_POS (28U)
+#define PSRAM_REG_LINEAR_BND_B_LEN (4U)
+#define PSRAM_REG_LINEAR_BND_B_MSK (((1U << PSRAM_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_REG_LINEAR_BND_B_POS)
+#define PSRAM_REG_LINEAR_BND_B_UMSK (~(((1U << PSRAM_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_REG_LINEAR_BND_B_POS))
+
+/* 0x4 : psram_manual_control */
+#define PSRAM_MANUAL_CONTROL_OFFSET (0x4)
+#define PSRAM_REG_WC_SW PSRAM_REG_WC_SW
+#define PSRAM_REG_WC_SW_POS (0U)
+#define PSRAM_REG_WC_SW_LEN (7U)
+#define PSRAM_REG_WC_SW_MSK (((1U << PSRAM_REG_WC_SW_LEN) - 1) << PSRAM_REG_WC_SW_POS)
+#define PSRAM_REG_WC_SW_UMSK (~(((1U << PSRAM_REG_WC_SW_LEN) - 1) << PSRAM_REG_WC_SW_POS))
+#define PSRAM_REG_WC_SW_EN PSRAM_REG_WC_SW_EN
+#define PSRAM_REG_WC_SW_EN_POS (8U)
+#define PSRAM_REG_WC_SW_EN_LEN (1U)
+#define PSRAM_REG_WC_SW_EN_MSK (((1U << PSRAM_REG_WC_SW_EN_LEN) - 1) << PSRAM_REG_WC_SW_EN_POS)
+#define PSRAM_REG_WC_SW_EN_UMSK (~(((1U << PSRAM_REG_WC_SW_EN_LEN) - 1) << PSRAM_REG_WC_SW_EN_POS))
+#define PSRAM_REG_STATE_HOLD_TICK PSRAM_REG_STATE_HOLD_TICK
+#define PSRAM_REG_STATE_HOLD_TICK_POS (9U)
+#define PSRAM_REG_STATE_HOLD_TICK_LEN (1U)
+#define PSRAM_REG_STATE_HOLD_TICK_MSK (((1U << PSRAM_REG_STATE_HOLD_TICK_LEN) - 1) << PSRAM_REG_STATE_HOLD_TICK_POS)
+#define PSRAM_REG_STATE_HOLD_TICK_UMSK (~(((1U << PSRAM_REG_STATE_HOLD_TICK_LEN) - 1) << PSRAM_REG_STATE_HOLD_TICK_POS))
+#define PSRAM_REG_DQS_LATCH_INV PSRAM_REG_DQS_LATCH_INV
+#define PSRAM_REG_DQS_LATCH_INV_POS (10U)
+#define PSRAM_REG_DQS_LATCH_INV_LEN (1U)
+#define PSRAM_REG_DQS_LATCH_INV_MSK (((1U << PSRAM_REG_DQS_LATCH_INV_LEN) - 1) << PSRAM_REG_DQS_LATCH_INV_POS)
+#define PSRAM_REG_DQS_LATCH_INV_UMSK (~(((1U << PSRAM_REG_DQS_LATCH_INV_LEN) - 1) << PSRAM_REG_DQS_LATCH_INV_POS))
+#define PSRAM_REG_WB_BL2_MASK PSRAM_REG_WB_BL2_MASK
+#define PSRAM_REG_WB_BL2_MASK_POS (11U)
+#define PSRAM_REG_WB_BL2_MASK_LEN (1U)
+#define PSRAM_REG_WB_BL2_MASK_MSK (((1U << PSRAM_REG_WB_BL2_MASK_LEN) - 1) << PSRAM_REG_WB_BL2_MASK_POS)
+#define PSRAM_REG_WB_BL2_MASK_UMSK (~(((1U << PSRAM_REG_WB_BL2_MASK_LEN) - 1) << PSRAM_REG_WB_BL2_MASK_POS))
+#define PSRAM_REG_FORCE_CEB_LOW PSRAM_REG_FORCE_CEB_LOW
+#define PSRAM_REG_FORCE_CEB_LOW_POS (12U)
+#define PSRAM_REG_FORCE_CEB_LOW_LEN (1U)
+#define PSRAM_REG_FORCE_CEB_LOW_MSK (((1U << PSRAM_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_REG_FORCE_CEB_LOW_POS)
+#define PSRAM_REG_FORCE_CEB_LOW_UMSK (~(((1U << PSRAM_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_REG_FORCE_CEB_LOW_POS))
+#define PSRAM_REG_FORCE_CEB_HIGH PSRAM_REG_FORCE_CEB_HIGH
+#define PSRAM_REG_FORCE_CEB_HIGH_POS (13U)
+#define PSRAM_REG_FORCE_CEB_HIGH_LEN (1U)
+#define PSRAM_REG_FORCE_CEB_HIGH_MSK (((1U << PSRAM_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_REG_FORCE_CEB_HIGH_POS)
+#define PSRAM_REG_FORCE_CEB_HIGH_UMSK (~(((1U << PSRAM_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_REG_FORCE_CEB_HIGH_POS))
+#define PSRAM_REG_PSRAM_RESETB PSRAM_REG_PSRAM_RESETB
+#define PSRAM_REG_PSRAM_RESETB_POS (14U)
+#define PSRAM_REG_PSRAM_RESETB_LEN (1U)
+#define PSRAM_REG_PSRAM_RESETB_MSK (((1U << PSRAM_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_REG_PSRAM_RESETB_POS)
+#define PSRAM_REG_PSRAM_RESETB_UMSK (~(((1U << PSRAM_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_REG_PSRAM_RESETB_POS))
+#define PSRAM_REG_CK_EDGE_NALI PSRAM_REG_CK_EDGE_NALI
+#define PSRAM_REG_CK_EDGE_NALI_POS (15U)
+#define PSRAM_REG_CK_EDGE_NALI_LEN (1U)
+#define PSRAM_REG_CK_EDGE_NALI_MSK (((1U << PSRAM_REG_CK_EDGE_NALI_LEN) - 1) << PSRAM_REG_CK_EDGE_NALI_POS)
+#define PSRAM_REG_CK_EDGE_NALI_UMSK (~(((1U << PSRAM_REG_CK_EDGE_NALI_LEN) - 1) << PSRAM_REG_CK_EDGE_NALI_POS))
+#define PSRAM_STS_CONFIG_READ PSRAM_STS_CONFIG_READ
+#define PSRAM_STS_CONFIG_READ_POS (16U)
+#define PSRAM_STS_CONFIG_READ_LEN (16U)
+#define PSRAM_STS_CONFIG_READ_MSK (((1U << PSRAM_STS_CONFIG_READ_LEN) - 1) << PSRAM_STS_CONFIG_READ_POS)
+#define PSRAM_STS_CONFIG_READ_UMSK (~(((1U << PSRAM_STS_CONFIG_READ_LEN) - 1) << PSRAM_STS_CONFIG_READ_POS))
+
+/* 0x8 : fifo_thres_control */
+#define PSRAM_FIFO_THRES_CONTROL_OFFSET (0x8)
+#define PSRAM_REG_MASK_W_FIFO_CNT PSRAM_REG_MASK_W_FIFO_CNT
+#define PSRAM_REG_MASK_W_FIFO_CNT_POS (0U)
+#define PSRAM_REG_MASK_W_FIFO_CNT_LEN (16U)
+#define PSRAM_REG_MASK_W_FIFO_CNT_MSK (((1U << PSRAM_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_REG_MASK_W_FIFO_CNT_POS)
+#define PSRAM_REG_MASK_W_FIFO_CNT_UMSK (~(((1U << PSRAM_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_REG_MASK_W_FIFO_CNT_POS))
+#define PSRAM_REG_MASK_R_FIFO_REM PSRAM_REG_MASK_R_FIFO_REM
+#define PSRAM_REG_MASK_R_FIFO_REM_POS (16U)
+#define PSRAM_REG_MASK_R_FIFO_REM_LEN (16U)
+#define PSRAM_REG_MASK_R_FIFO_REM_MSK (((1U << PSRAM_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_REG_MASK_R_FIFO_REM_POS)
+#define PSRAM_REG_MASK_R_FIFO_REM_UMSK (~(((1U << PSRAM_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_REG_MASK_R_FIFO_REM_POS))
+
+/* 0xC : psram_manual_control2 */
+#define PSRAM_MANUAL_CONTROL2_OFFSET (0xC)
+#define PSRAM_REG_HOLD_CYCLE_SW PSRAM_REG_HOLD_CYCLE_SW
+#define PSRAM_REG_HOLD_CYCLE_SW_POS (0U)
+#define PSRAM_REG_HOLD_CYCLE_SW_LEN (7U)
+#define PSRAM_REG_HOLD_CYCLE_SW_MSK (((1U << PSRAM_REG_HOLD_CYCLE_SW_LEN) - 1) << PSRAM_REG_HOLD_CYCLE_SW_POS)
+#define PSRAM_REG_HOLD_CYCLE_SW_UMSK (~(((1U << PSRAM_REG_HOLD_CYCLE_SW_LEN) - 1) << PSRAM_REG_HOLD_CYCLE_SW_POS))
+#define PSRAM_REG_HC_SW_EN PSRAM_REG_HC_SW_EN
+#define PSRAM_REG_HC_SW_EN_POS (7U)
+#define PSRAM_REG_HC_SW_EN_LEN (1U)
+#define PSRAM_REG_HC_SW_EN_MSK (((1U << PSRAM_REG_HC_SW_EN_LEN) - 1) << PSRAM_REG_HC_SW_EN_POS)
+#define PSRAM_REG_HC_SW_EN_UMSK (~(((1U << PSRAM_REG_HC_SW_EN_LEN) - 1) << PSRAM_REG_HC_SW_EN_POS))
+#define PSRAM_REG_DQS_REL_VAL PSRAM_REG_DQS_REL_VAL
+#define PSRAM_REG_DQS_REL_VAL_POS (8U)
+#define PSRAM_REG_DQS_REL_VAL_LEN (7U)
+#define PSRAM_REG_DQS_REL_VAL_MSK (((1U << PSRAM_REG_DQS_REL_VAL_LEN) - 1) << PSRAM_REG_DQS_REL_VAL_POS)
+#define PSRAM_REG_DQS_REL_VAL_UMSK (~(((1U << PSRAM_REG_DQS_REL_VAL_LEN) - 1) << PSRAM_REG_DQS_REL_VAL_POS))
+#define PSRAM_REG_PWRAP_SW_SHT_B PSRAM_REG_PWRAP_SW_SHT_B
+#define PSRAM_REG_PWRAP_SW_SHT_B_POS (16U)
+#define PSRAM_REG_PWRAP_SW_SHT_B_LEN (4U)
+#define PSRAM_REG_PWRAP_SW_SHT_B_MSK (((1U << PSRAM_REG_PWRAP_SW_SHT_B_LEN) - 1) << PSRAM_REG_PWRAP_SW_SHT_B_POS)
+#define PSRAM_REG_PWRAP_SW_SHT_B_UMSK (~(((1U << PSRAM_REG_PWRAP_SW_SHT_B_LEN) - 1) << PSRAM_REG_PWRAP_SW_SHT_B_POS))
+#define PSRAM_REG_PWRAP_SW_EN PSRAM_REG_PWRAP_SW_EN
+#define PSRAM_REG_PWRAP_SW_EN_POS (23U)
+#define PSRAM_REG_PWRAP_SW_EN_LEN (1U)
+#define PSRAM_REG_PWRAP_SW_EN_MSK (((1U << PSRAM_REG_PWRAP_SW_EN_LEN) - 1) << PSRAM_REG_PWRAP_SW_EN_POS)
+#define PSRAM_REG_PWRAP_SW_EN_UMSK (~(((1U << PSRAM_REG_PWRAP_SW_EN_LEN) - 1) << PSRAM_REG_PWRAP_SW_EN_POS))
+#define PSRAM_REG_ADDR_MASK PSRAM_REG_ADDR_MASK
+#define PSRAM_REG_ADDR_MASK_POS (24U)
+#define PSRAM_REG_ADDR_MASK_LEN (8U)
+#define PSRAM_REG_ADDR_MASK_MSK (((1U << PSRAM_REG_ADDR_MASK_LEN) - 1) << PSRAM_REG_ADDR_MASK_POS)
+#define PSRAM_REG_ADDR_MASK_UMSK (~(((1U << PSRAM_REG_ADDR_MASK_LEN) - 1) << PSRAM_REG_ADDR_MASK_POS))
+
+/* 0x10 : winbond_psram_configure */
+#define PSRAM_WINBOND_PSRAM_CONFIGURE_OFFSET (0x10)
+#define PSRAM_REG_WB_LATENCY PSRAM_REG_WB_LATENCY
+#define PSRAM_REG_WB_LATENCY_POS (0U)
+#define PSRAM_REG_WB_LATENCY_LEN (4U)
+#define PSRAM_REG_WB_LATENCY_MSK (((1U << PSRAM_REG_WB_LATENCY_LEN) - 1) << PSRAM_REG_WB_LATENCY_POS)
+#define PSRAM_REG_WB_LATENCY_UMSK (~(((1U << PSRAM_REG_WB_LATENCY_LEN) - 1) << PSRAM_REG_WB_LATENCY_POS))
+#define PSRAM_REG_WB_DRIVE_ST PSRAM_REG_WB_DRIVE_ST
+#define PSRAM_REG_WB_DRIVE_ST_POS (4U)
+#define PSRAM_REG_WB_DRIVE_ST_LEN (3U)
+#define PSRAM_REG_WB_DRIVE_ST_MSK (((1U << PSRAM_REG_WB_DRIVE_ST_LEN) - 1) << PSRAM_REG_WB_DRIVE_ST_POS)
+#define PSRAM_REG_WB_DRIVE_ST_UMSK (~(((1U << PSRAM_REG_WB_DRIVE_ST_LEN) - 1) << PSRAM_REG_WB_DRIVE_ST_POS))
+#define PSRAM_REG_WB_HYBRID_EN PSRAM_REG_WB_HYBRID_EN
+#define PSRAM_REG_WB_HYBRID_EN_POS (7U)
+#define PSRAM_REG_WB_HYBRID_EN_LEN (1U)
+#define PSRAM_REG_WB_HYBRID_EN_MSK (((1U << PSRAM_REG_WB_HYBRID_EN_LEN) - 1) << PSRAM_REG_WB_HYBRID_EN_POS)
+#define PSRAM_REG_WB_HYBRID_EN_UMSK (~(((1U << PSRAM_REG_WB_HYBRID_EN_LEN) - 1) << PSRAM_REG_WB_HYBRID_EN_POS))
+#define PSRAM_REG_WB_BURST_LENGTH PSRAM_REG_WB_BURST_LENGTH
+#define PSRAM_REG_WB_BURST_LENGTH_POS (8U)
+#define PSRAM_REG_WB_BURST_LENGTH_LEN (3U)
+#define PSRAM_REG_WB_BURST_LENGTH_MSK (((1U << PSRAM_REG_WB_BURST_LENGTH_LEN) - 1) << PSRAM_REG_WB_BURST_LENGTH_POS)
+#define PSRAM_REG_WB_BURST_LENGTH_UMSK (~(((1U << PSRAM_REG_WB_BURST_LENGTH_LEN) - 1) << PSRAM_REG_WB_BURST_LENGTH_POS))
+#define PSRAM_REG_WB_FIX_LATENCY PSRAM_REG_WB_FIX_LATENCY
+#define PSRAM_REG_WB_FIX_LATENCY_POS (12U)
+#define PSRAM_REG_WB_FIX_LATENCY_LEN (1U)
+#define PSRAM_REG_WB_FIX_LATENCY_MSK (((1U << PSRAM_REG_WB_FIX_LATENCY_LEN) - 1) << PSRAM_REG_WB_FIX_LATENCY_POS)
+#define PSRAM_REG_WB_FIX_LATENCY_UMSK (~(((1U << PSRAM_REG_WB_FIX_LATENCY_LEN) - 1) << PSRAM_REG_WB_FIX_LATENCY_POS))
+#define PSRAM_REG_WB_DPD_DIS PSRAM_REG_WB_DPD_DIS
+#define PSRAM_REG_WB_DPD_DIS_POS (13U)
+#define PSRAM_REG_WB_DPD_DIS_LEN (1U)
+#define PSRAM_REG_WB_DPD_DIS_MSK (((1U << PSRAM_REG_WB_DPD_DIS_LEN) - 1) << PSRAM_REG_WB_DPD_DIS_POS)
+#define PSRAM_REG_WB_DPD_DIS_UMSK (~(((1U << PSRAM_REG_WB_DPD_DIS_LEN) - 1) << PSRAM_REG_WB_DPD_DIS_POS))
+#define PSRAM_REG_WB_PASR PSRAM_REG_WB_PASR
+#define PSRAM_REG_WB_PASR_POS (16U)
+#define PSRAM_REG_WB_PASR_LEN (5U)
+#define PSRAM_REG_WB_PASR_MSK (((1U << PSRAM_REG_WB_PASR_LEN) - 1) << PSRAM_REG_WB_PASR_POS)
+#define PSRAM_REG_WB_PASR_UMSK (~(((1U << PSRAM_REG_WB_PASR_LEN) - 1) << PSRAM_REG_WB_PASR_POS))
+#define PSRAM_REG_WB_HYBRID_SLP PSRAM_REG_WB_HYBRID_SLP
+#define PSRAM_REG_WB_HYBRID_SLP_POS (24U)
+#define PSRAM_REG_WB_HYBRID_SLP_LEN (1U)
+#define PSRAM_REG_WB_HYBRID_SLP_MSK (((1U << PSRAM_REG_WB_HYBRID_SLP_LEN) - 1) << PSRAM_REG_WB_HYBRID_SLP_POS)
+#define PSRAM_REG_WB_HYBRID_SLP_UMSK (~(((1U << PSRAM_REG_WB_HYBRID_SLP_LEN) - 1) << PSRAM_REG_WB_HYBRID_SLP_POS))
+#define PSRAM_REG_WB_LINEAR_DIS PSRAM_REG_WB_LINEAR_DIS
+#define PSRAM_REG_WB_LINEAR_DIS_POS (25U)
+#define PSRAM_REG_WB_LINEAR_DIS_LEN (1U)
+#define PSRAM_REG_WB_LINEAR_DIS_MSK (((1U << PSRAM_REG_WB_LINEAR_DIS_LEN) - 1) << PSRAM_REG_WB_LINEAR_DIS_POS)
+#define PSRAM_REG_WB_LINEAR_DIS_UMSK (~(((1U << PSRAM_REG_WB_LINEAR_DIS_LEN) - 1) << PSRAM_REG_WB_LINEAR_DIS_POS))
+#define PSRAM_REG_WB_IPD PSRAM_REG_WB_IPD
+#define PSRAM_REG_WB_IPD_POS (29U)
+#define PSRAM_REG_WB_IPD_LEN (1U)
+#define PSRAM_REG_WB_IPD_MSK (((1U << PSRAM_REG_WB_IPD_LEN) - 1) << PSRAM_REG_WB_IPD_POS)
+#define PSRAM_REG_WB_IPD_UMSK (~(((1U << PSRAM_REG_WB_IPD_LEN) - 1) << PSRAM_REG_WB_IPD_POS))
+#define PSRAM_REG_WB_MCLK_TYPE PSRAM_REG_WB_MCLK_TYPE
+#define PSRAM_REG_WB_MCLK_TYPE_POS (30U)
+#define PSRAM_REG_WB_MCLK_TYPE_LEN (1U)
+#define PSRAM_REG_WB_MCLK_TYPE_MSK (((1U << PSRAM_REG_WB_MCLK_TYPE_LEN) - 1) << PSRAM_REG_WB_MCLK_TYPE_POS)
+#define PSRAM_REG_WB_MCLK_TYPE_UMSK (~(((1U << PSRAM_REG_WB_MCLK_TYPE_LEN) - 1) << PSRAM_REG_WB_MCLK_TYPE_POS))
+#define PSRAM_REG_WB_SW_RST PSRAM_REG_WB_SW_RST
+#define PSRAM_REG_WB_SW_RST_POS (31U)
+#define PSRAM_REG_WB_SW_RST_LEN (1U)
+#define PSRAM_REG_WB_SW_RST_MSK (((1U << PSRAM_REG_WB_SW_RST_LEN) - 1) << PSRAM_REG_WB_SW_RST_POS)
+#define PSRAM_REG_WB_SW_RST_UMSK (~(((1U << PSRAM_REG_WB_SW_RST_LEN) - 1) << PSRAM_REG_WB_SW_RST_POS))
+
+/* 0x14 : winbond_psram_status */
+#define PSRAM_WINBOND_PSRAM_STATUS_OFFSET (0x14)
+#define PSRAM_STS_WB_LATENCY PSRAM_STS_WB_LATENCY
+#define PSRAM_STS_WB_LATENCY_POS (0U)
+#define PSRAM_STS_WB_LATENCY_LEN (4U)
+#define PSRAM_STS_WB_LATENCY_MSK (((1U << PSRAM_STS_WB_LATENCY_LEN) - 1) << PSRAM_STS_WB_LATENCY_POS)
+#define PSRAM_STS_WB_LATENCY_UMSK (~(((1U << PSRAM_STS_WB_LATENCY_LEN) - 1) << PSRAM_STS_WB_LATENCY_POS))
+#define PSRAM_STS_WB_DRIVE_ST PSRAM_STS_WB_DRIVE_ST
+#define PSRAM_STS_WB_DRIVE_ST_POS (4U)
+#define PSRAM_STS_WB_DRIVE_ST_LEN (3U)
+#define PSRAM_STS_WB_DRIVE_ST_MSK (((1U << PSRAM_STS_WB_DRIVE_ST_LEN) - 1) << PSRAM_STS_WB_DRIVE_ST_POS)
+#define PSRAM_STS_WB_DRIVE_ST_UMSK (~(((1U << PSRAM_STS_WB_DRIVE_ST_LEN) - 1) << PSRAM_STS_WB_DRIVE_ST_POS))
+#define PSRAM_STS_WB_HYBRID_EN PSRAM_STS_WB_HYBRID_EN
+#define PSRAM_STS_WB_HYBRID_EN_POS (7U)
+#define PSRAM_STS_WB_HYBRID_EN_LEN (1U)
+#define PSRAM_STS_WB_HYBRID_EN_MSK (((1U << PSRAM_STS_WB_HYBRID_EN_LEN) - 1) << PSRAM_STS_WB_HYBRID_EN_POS)
+#define PSRAM_STS_WB_HYBRID_EN_UMSK (~(((1U << PSRAM_STS_WB_HYBRID_EN_LEN) - 1) << PSRAM_STS_WB_HYBRID_EN_POS))
+#define PSRAM_STS_WB_BURST_LENGTH PSRAM_STS_WB_BURST_LENGTH
+#define PSRAM_STS_WB_BURST_LENGTH_POS (8U)
+#define PSRAM_STS_WB_BURST_LENGTH_LEN (3U)
+#define PSRAM_STS_WB_BURST_LENGTH_MSK (((1U << PSRAM_STS_WB_BURST_LENGTH_LEN) - 1) << PSRAM_STS_WB_BURST_LENGTH_POS)
+#define PSRAM_STS_WB_BURST_LENGTH_UMSK (~(((1U << PSRAM_STS_WB_BURST_LENGTH_LEN) - 1) << PSRAM_STS_WB_BURST_LENGTH_POS))
+#define PSRAM_STS_WB_FIX_LATENCY PSRAM_STS_WB_FIX_LATENCY
+#define PSRAM_STS_WB_FIX_LATENCY_POS (12U)
+#define PSRAM_STS_WB_FIX_LATENCY_LEN (1U)
+#define PSRAM_STS_WB_FIX_LATENCY_MSK (((1U << PSRAM_STS_WB_FIX_LATENCY_LEN) - 1) << PSRAM_STS_WB_FIX_LATENCY_POS)
+#define PSRAM_STS_WB_FIX_LATENCY_UMSK (~(((1U << PSRAM_STS_WB_FIX_LATENCY_LEN) - 1) << PSRAM_STS_WB_FIX_LATENCY_POS))
+#define PSRAM_STS_WB_DPD_DIS PSRAM_STS_WB_DPD_DIS
+#define PSRAM_STS_WB_DPD_DIS_POS (13U)
+#define PSRAM_STS_WB_DPD_DIS_LEN (1U)
+#define PSRAM_STS_WB_DPD_DIS_MSK (((1U << PSRAM_STS_WB_DPD_DIS_LEN) - 1) << PSRAM_STS_WB_DPD_DIS_POS)
+#define PSRAM_STS_WB_DPD_DIS_UMSK (~(((1U << PSRAM_STS_WB_DPD_DIS_LEN) - 1) << PSRAM_STS_WB_DPD_DIS_POS))
+#define PSRAM_STS_WB_PASR PSRAM_STS_WB_PASR
+#define PSRAM_STS_WB_PASR_POS (16U)
+#define PSRAM_STS_WB_PASR_LEN (5U)
+#define PSRAM_STS_WB_PASR_MSK (((1U << PSRAM_STS_WB_PASR_LEN) - 1) << PSRAM_STS_WB_PASR_POS)
+#define PSRAM_STS_WB_PASR_UMSK (~(((1U << PSRAM_STS_WB_PASR_LEN) - 1) << PSRAM_STS_WB_PASR_POS))
+#define PSRAM_STS_WB_HYBRID_SLP PSRAM_STS_WB_HYBRID_SLP
+#define PSRAM_STS_WB_HYBRID_SLP_POS (24U)
+#define PSRAM_STS_WB_HYBRID_SLP_LEN (1U)
+#define PSRAM_STS_WB_HYBRID_SLP_MSK (((1U << PSRAM_STS_WB_HYBRID_SLP_LEN) - 1) << PSRAM_STS_WB_HYBRID_SLP_POS)
+#define PSRAM_STS_WB_HYBRID_SLP_UMSK (~(((1U << PSRAM_STS_WB_HYBRID_SLP_LEN) - 1) << PSRAM_STS_WB_HYBRID_SLP_POS))
+#define PSRAM_STS_WB_MCLK_TYPE PSRAM_STS_WB_MCLK_TYPE
+#define PSRAM_STS_WB_MCLK_TYPE_POS (30U)
+#define PSRAM_STS_WB_MCLK_TYPE_LEN (1U)
+#define PSRAM_STS_WB_MCLK_TYPE_MSK (((1U << PSRAM_STS_WB_MCLK_TYPE_LEN) - 1) << PSRAM_STS_WB_MCLK_TYPE_POS)
+#define PSRAM_STS_WB_MCLK_TYPE_UMSK (~(((1U << PSRAM_STS_WB_MCLK_TYPE_LEN) - 1) << PSRAM_STS_WB_MCLK_TYPE_POS))
+
+/* 0x18 : winbond_psram_configure2 */
+#define PSRAM_WINBOND_PSRAM_CONFIGURE2_OFFSET (0x18)
+#define PSRAM_REG_WB_ZQ_CODE PSRAM_REG_WB_ZQ_CODE
+#define PSRAM_REG_WB_ZQ_CODE_POS (0U)
+#define PSRAM_REG_WB_ZQ_CODE_LEN (4U)
+#define PSRAM_REG_WB_ZQ_CODE_MSK (((1U << PSRAM_REG_WB_ZQ_CODE_LEN) - 1) << PSRAM_REG_WB_ZQ_CODE_POS)
+#define PSRAM_REG_WB_ZQ_CODE_UMSK (~(((1U << PSRAM_REG_WB_ZQ_CODE_LEN) - 1) << PSRAM_REG_WB_ZQ_CODE_POS))
+
+/* 0x20 : apmemory_psram_configure */
+#define PSRAM_APMEMORY_PSRAM_CONFIGURE_OFFSET (0x20)
+#define PSRAM_REG_AP_BURST_LENGTH PSRAM_REG_AP_BURST_LENGTH
+#define PSRAM_REG_AP_BURST_LENGTH_POS (0U)
+#define PSRAM_REG_AP_BURST_LENGTH_LEN (2U)
+#define PSRAM_REG_AP_BURST_LENGTH_MSK (((1U << PSRAM_REG_AP_BURST_LENGTH_LEN) - 1) << PSRAM_REG_AP_BURST_LENGTH_POS)
+#define PSRAM_REG_AP_BURST_LENGTH_UMSK (~(((1U << PSRAM_REG_AP_BURST_LENGTH_LEN) - 1) << PSRAM_REG_AP_BURST_LENGTH_POS))
+#define PSRAM_REG_AP_BURST_TYPE PSRAM_REG_AP_BURST_TYPE
+#define PSRAM_REG_AP_BURST_TYPE_POS (4U)
+#define PSRAM_REG_AP_BURST_TYPE_LEN (1U)
+#define PSRAM_REG_AP_BURST_TYPE_MSK (((1U << PSRAM_REG_AP_BURST_TYPE_LEN) - 1) << PSRAM_REG_AP_BURST_TYPE_POS)
+#define PSRAM_REG_AP_BURST_TYPE_UMSK (~(((1U << PSRAM_REG_AP_BURST_TYPE_LEN) - 1) << PSRAM_REG_AP_BURST_TYPE_POS))
+#define PSRAM_REG_AP_RBX PSRAM_REG_AP_RBX
+#define PSRAM_REG_AP_RBX_POS (5U)
+#define PSRAM_REG_AP_RBX_LEN (1U)
+#define PSRAM_REG_AP_RBX_MSK (((1U << PSRAM_REG_AP_RBX_LEN) - 1) << PSRAM_REG_AP_RBX_POS)
+#define PSRAM_REG_AP_RBX_UMSK (~(((1U << PSRAM_REG_AP_RBX_LEN) - 1) << PSRAM_REG_AP_RBX_POS))
+#define PSRAM_REG_AP_DPD PSRAM_REG_AP_DPD
+#define PSRAM_REG_AP_DPD_POS (6U)
+#define PSRAM_REG_AP_DPD_LEN (1U)
+#define PSRAM_REG_AP_DPD_MSK (((1U << PSRAM_REG_AP_DPD_LEN) - 1) << PSRAM_REG_AP_DPD_POS)
+#define PSRAM_REG_AP_DPD_UMSK (~(((1U << PSRAM_REG_AP_DPD_LEN) - 1) << PSRAM_REG_AP_DPD_POS))
+#define PSRAM_REG_AP_SLEEP PSRAM_REG_AP_SLEEP
+#define PSRAM_REG_AP_SLEEP_POS (7U)
+#define PSRAM_REG_AP_SLEEP_LEN (1U)
+#define PSRAM_REG_AP_SLEEP_MSK (((1U << PSRAM_REG_AP_SLEEP_LEN) - 1) << PSRAM_REG_AP_SLEEP_POS)
+#define PSRAM_REG_AP_SLEEP_UMSK (~(((1U << PSRAM_REG_AP_SLEEP_LEN) - 1) << PSRAM_REG_AP_SLEEP_POS))
+#define PSRAM_REG_AP_PASR PSRAM_REG_AP_PASR
+#define PSRAM_REG_AP_PASR_POS (8U)
+#define PSRAM_REG_AP_PASR_LEN (3U)
+#define PSRAM_REG_AP_PASR_MSK (((1U << PSRAM_REG_AP_PASR_LEN) - 1) << PSRAM_REG_AP_PASR_POS)
+#define PSRAM_REG_AP_PASR_UMSK (~(((1U << PSRAM_REG_AP_PASR_LEN) - 1) << PSRAM_REG_AP_PASR_POS))
+#define PSRAM_REG_AP_W_LATENCY_CODE PSRAM_REG_AP_W_LATENCY_CODE
+#define PSRAM_REG_AP_W_LATENCY_CODE_POS (12U)
+#define PSRAM_REG_AP_W_LATENCY_CODE_LEN (3U)
+#define PSRAM_REG_AP_W_LATENCY_CODE_MSK (((1U << PSRAM_REG_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_W_LATENCY_CODE_POS)
+#define PSRAM_REG_AP_W_LATENCY_CODE_UMSK (~(((1U << PSRAM_REG_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_W_LATENCY_CODE_POS))
+#define PSRAM_REG_AP_DRIVE_ST PSRAM_REG_AP_DRIVE_ST
+#define PSRAM_REG_AP_DRIVE_ST_POS (16U)
+#define PSRAM_REG_AP_DRIVE_ST_LEN (2U)
+#define PSRAM_REG_AP_DRIVE_ST_MSK (((1U << PSRAM_REG_AP_DRIVE_ST_LEN) - 1) << PSRAM_REG_AP_DRIVE_ST_POS)
+#define PSRAM_REG_AP_DRIVE_ST_UMSK (~(((1U << PSRAM_REG_AP_DRIVE_ST_LEN) - 1) << PSRAM_REG_AP_DRIVE_ST_POS))
+#define PSRAM_REG_AP_RF PSRAM_REG_AP_RF
+#define PSRAM_REG_AP_RF_POS (18U)
+#define PSRAM_REG_AP_RF_LEN (2U)
+#define PSRAM_REG_AP_RF_MSK (((1U << PSRAM_REG_AP_RF_LEN) - 1) << PSRAM_REG_AP_RF_POS)
+#define PSRAM_REG_AP_RF_UMSK (~(((1U << PSRAM_REG_AP_RF_LEN) - 1) << PSRAM_REG_AP_RF_POS))
+#define PSRAM_REG_AP_R_LATENCY_CODE PSRAM_REG_AP_R_LATENCY_CODE
+#define PSRAM_REG_AP_R_LATENCY_CODE_POS (20U)
+#define PSRAM_REG_AP_R_LATENCY_CODE_LEN (3U)
+#define PSRAM_REG_AP_R_LATENCY_CODE_MSK (((1U << PSRAM_REG_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_CODE_POS)
+#define PSRAM_REG_AP_R_LATENCY_CODE_UMSK (~(((1U << PSRAM_REG_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_CODE_POS))
+#define PSRAM_REG_AP_R_LATENCY_TYPE PSRAM_REG_AP_R_LATENCY_TYPE
+#define PSRAM_REG_AP_R_LATENCY_TYPE_POS (24U)
+#define PSRAM_REG_AP_R_LATENCY_TYPE_LEN (1U)
+#define PSRAM_REG_AP_R_LATENCY_TYPE_MSK (((1U << PSRAM_REG_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_TYPE_POS)
+#define PSRAM_REG_AP_R_LATENCY_TYPE_UMSK (~(((1U << PSRAM_REG_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_TYPE_POS))
+#define PSRAM_REG_AP_LINEAR_DIS PSRAM_REG_AP_LINEAR_DIS
+#define PSRAM_REG_AP_LINEAR_DIS_POS (25U)
+#define PSRAM_REG_AP_LINEAR_DIS_LEN (1U)
+#define PSRAM_REG_AP_LINEAR_DIS_MSK (((1U << PSRAM_REG_AP_LINEAR_DIS_LEN) - 1) << PSRAM_REG_AP_LINEAR_DIS_POS)
+#define PSRAM_REG_AP_LINEAR_DIS_UMSK (~(((1U << PSRAM_REG_AP_LINEAR_DIS_LEN) - 1) << PSRAM_REG_AP_LINEAR_DIS_POS))
+#define PSRAM_REG_GLB_RESET_PULSE PSRAM_REG_GLB_RESET_PULSE
+#define PSRAM_REG_GLB_RESET_PULSE_POS (28U)
+#define PSRAM_REG_GLB_RESET_PULSE_LEN (1U)
+#define PSRAM_REG_GLB_RESET_PULSE_MSK (((1U << PSRAM_REG_GLB_RESET_PULSE_LEN) - 1) << PSRAM_REG_GLB_RESET_PULSE_POS)
+#define PSRAM_REG_GLB_RESET_PULSE_UMSK (~(((1U << PSRAM_REG_GLB_RESET_PULSE_LEN) - 1) << PSRAM_REG_GLB_RESET_PULSE_POS))
+
+/* 0x24 : apmemory_psram_status */
+#define PSRAM_APMEMORY_PSRAM_STATUS_OFFSET (0x24)
+#define PSRAM_STS_AP_BURST_LENGTH PSRAM_STS_AP_BURST_LENGTH
+#define PSRAM_STS_AP_BURST_LENGTH_POS (0U)
+#define PSRAM_STS_AP_BURST_LENGTH_LEN (2U)
+#define PSRAM_STS_AP_BURST_LENGTH_MSK (((1U << PSRAM_STS_AP_BURST_LENGTH_LEN) - 1) << PSRAM_STS_AP_BURST_LENGTH_POS)
+#define PSRAM_STS_AP_BURST_LENGTH_UMSK (~(((1U << PSRAM_STS_AP_BURST_LENGTH_LEN) - 1) << PSRAM_STS_AP_BURST_LENGTH_POS))
+#define PSRAM_STS_AP_BURST_TYPE PSRAM_STS_AP_BURST_TYPE
+#define PSRAM_STS_AP_BURST_TYPE_POS (4U)
+#define PSRAM_STS_AP_BURST_TYPE_LEN (1U)
+#define PSRAM_STS_AP_BURST_TYPE_MSK (((1U << PSRAM_STS_AP_BURST_TYPE_LEN) - 1) << PSRAM_STS_AP_BURST_TYPE_POS)
+#define PSRAM_STS_AP_BURST_TYPE_UMSK (~(((1U << PSRAM_STS_AP_BURST_TYPE_LEN) - 1) << PSRAM_STS_AP_BURST_TYPE_POS))
+#define PSRAM_STS_AP_RBX PSRAM_STS_AP_RBX
+#define PSRAM_STS_AP_RBX_POS (5U)
+#define PSRAM_STS_AP_RBX_LEN (1U)
+#define PSRAM_STS_AP_RBX_MSK (((1U << PSRAM_STS_AP_RBX_LEN) - 1) << PSRAM_STS_AP_RBX_POS)
+#define PSRAM_STS_AP_RBX_UMSK (~(((1U << PSRAM_STS_AP_RBX_LEN) - 1) << PSRAM_STS_AP_RBX_POS))
+#define PSRAM_STS_AP_X16_MODE PSRAM_STS_AP_X16_MODE
+#define PSRAM_STS_AP_X16_MODE_POS (6U)
+#define PSRAM_STS_AP_X16_MODE_LEN (1U)
+#define PSRAM_STS_AP_X16_MODE_MSK (((1U << PSRAM_STS_AP_X16_MODE_LEN) - 1) << PSRAM_STS_AP_X16_MODE_POS)
+#define PSRAM_STS_AP_X16_MODE_UMSK (~(((1U << PSRAM_STS_AP_X16_MODE_LEN) - 1) << PSRAM_STS_AP_X16_MODE_POS))
+#define PSRAM_STS_AP_PASR PSRAM_STS_AP_PASR
+#define PSRAM_STS_AP_PASR_POS (8U)
+#define PSRAM_STS_AP_PASR_LEN (3U)
+#define PSRAM_STS_AP_PASR_MSK (((1U << PSRAM_STS_AP_PASR_LEN) - 1) << PSRAM_STS_AP_PASR_POS)
+#define PSRAM_STS_AP_PASR_UMSK (~(((1U << PSRAM_STS_AP_PASR_LEN) - 1) << PSRAM_STS_AP_PASR_POS))
+#define PSRAM_STS_AP_W_LATENCY_CODE PSRAM_STS_AP_W_LATENCY_CODE
+#define PSRAM_STS_AP_W_LATENCY_CODE_POS (12U)
+#define PSRAM_STS_AP_W_LATENCY_CODE_LEN (3U)
+#define PSRAM_STS_AP_W_LATENCY_CODE_MSK (((1U << PSRAM_STS_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_W_LATENCY_CODE_POS)
+#define PSRAM_STS_AP_W_LATENCY_CODE_UMSK (~(((1U << PSRAM_STS_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_W_LATENCY_CODE_POS))
+#define PSRAM_STS_AP_DRIVE_ST PSRAM_STS_AP_DRIVE_ST
+#define PSRAM_STS_AP_DRIVE_ST_POS (16U)
+#define PSRAM_STS_AP_DRIVE_ST_LEN (2U)
+#define PSRAM_STS_AP_DRIVE_ST_MSK (((1U << PSRAM_STS_AP_DRIVE_ST_LEN) - 1) << PSRAM_STS_AP_DRIVE_ST_POS)
+#define PSRAM_STS_AP_DRIVE_ST_UMSK (~(((1U << PSRAM_STS_AP_DRIVE_ST_LEN) - 1) << PSRAM_STS_AP_DRIVE_ST_POS))
+#define PSRAM_STS_AP_RF PSRAM_STS_AP_RF
+#define PSRAM_STS_AP_RF_POS (18U)
+#define PSRAM_STS_AP_RF_LEN (2U)
+#define PSRAM_STS_AP_RF_MSK (((1U << PSRAM_STS_AP_RF_LEN) - 1) << PSRAM_STS_AP_RF_POS)
+#define PSRAM_STS_AP_RF_UMSK (~(((1U << PSRAM_STS_AP_RF_LEN) - 1) << PSRAM_STS_AP_RF_POS))
+#define PSRAM_STS_AP_R_LATENCY_CODE PSRAM_STS_AP_R_LATENCY_CODE
+#define PSRAM_STS_AP_R_LATENCY_CODE_POS (20U)
+#define PSRAM_STS_AP_R_LATENCY_CODE_LEN (3U)
+#define PSRAM_STS_AP_R_LATENCY_CODE_MSK (((1U << PSRAM_STS_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_CODE_POS)
+#define PSRAM_STS_AP_R_LATENCY_CODE_UMSK (~(((1U << PSRAM_STS_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_CODE_POS))
+#define PSRAM_STS_AP_R_LATENCY_TYPE PSRAM_STS_AP_R_LATENCY_TYPE
+#define PSRAM_STS_AP_R_LATENCY_TYPE_POS (24U)
+#define PSRAM_STS_AP_R_LATENCY_TYPE_LEN (1U)
+#define PSRAM_STS_AP_R_LATENCY_TYPE_MSK (((1U << PSRAM_STS_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_TYPE_POS)
+#define PSRAM_STS_AP_R_LATENCY_TYPE_UMSK (~(((1U << PSRAM_STS_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_TYPE_POS))
+
+/* 0x30 : psram_manual_control3 */
+#define PSRAM_MANUAL_CONTROL3_OFFSET (0x30)
+#define PSRAM_REG_ADQ_REL_VAL PSRAM_REG_ADQ_REL_VAL
+#define PSRAM_REG_ADQ_REL_VAL_POS (0U)
+#define PSRAM_REG_ADQ_REL_VAL_LEN (7U)
+#define PSRAM_REG_ADQ_REL_VAL_MSK (((1U << PSRAM_REG_ADQ_REL_VAL_LEN) - 1) << PSRAM_REG_ADQ_REL_VAL_POS)
+#define PSRAM_REG_ADQ_REL_VAL_UMSK (~(((1U << PSRAM_REG_ADQ_REL_VAL_LEN) - 1) << PSRAM_REG_ADQ_REL_VAL_POS))
+#define PSRAM_REG_WRAP2INCR_EN PSRAM_REG_WRAP2INCR_EN
+#define PSRAM_REG_WRAP2INCR_EN_POS (8U)
+#define PSRAM_REG_WRAP2INCR_EN_LEN (1U)
+#define PSRAM_REG_WRAP2INCR_EN_MSK (((1U << PSRAM_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_REG_WRAP2INCR_EN_POS)
+#define PSRAM_REG_WRAP2INCR_EN_UMSK (~(((1U << PSRAM_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_REG_WRAP2INCR_EN_POS))
+
+/* 0x80 : psram_intf_delay_ctrl0 */
+#define PSRAM_INTF_DELAY_CTRL0_OFFSET (0x80)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0 PSRAM_REG_DELAY_SEL_O_DQS_OEN0
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS (0U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_MSK (((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS))
+#define PSRAM_REG_DELAY_SEL_O_CEB PSRAM_REG_DELAY_SEL_O_CEB
+#define PSRAM_REG_DELAY_SEL_O_CEB_POS (8U)
+#define PSRAM_REG_DELAY_SEL_O_CEB_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_CEB_MSK (((1U << PSRAM_REG_DELAY_SEL_O_CEB_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CEB_POS)
+#define PSRAM_REG_DELAY_SEL_O_CEB_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_CEB_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CEB_POS))
+#define PSRAM_REG_DELAY_SEL_O_CLK_N PSRAM_REG_DELAY_SEL_O_CLK_N
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_POS (16U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_MSK (((1U << PSRAM_REG_DELAY_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_N_POS)
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_N_POS))
+#define PSRAM_REG_DELAY_SEL_O_CLK PSRAM_REG_DELAY_SEL_O_CLK
+#define PSRAM_REG_DELAY_SEL_O_CLK_POS (24U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_MSK (((1U << PSRAM_REG_DELAY_SEL_O_CLK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_POS)
+#define PSRAM_REG_DELAY_SEL_O_CLK_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_CLK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_POS))
+
+/* 0x84 : psram_intf_delay_ctrl1 */
+#define PSRAM_INTF_DELAY_CTRL1_OFFSET (0x84)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1 PSRAM_REG_DELAY_SEL_O_ADQ1
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_POS (0U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ1_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ1_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ0 PSRAM_REG_DELAY_SEL_O_ADQ0
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_POS (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ0_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ0_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0 PSRAM_REG_DELAY_SEL_O_ADQ_OEN0
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS))
+#define PSRAM_REG_DELAY_SEL_O_DQS0 PSRAM_REG_DELAY_SEL_O_DQS0
+#define PSRAM_REG_DELAY_SEL_O_DQS0_POS (24U)
+#define PSRAM_REG_DELAY_SEL_O_DQS0_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS0_MSK (((1U << PSRAM_REG_DELAY_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS0_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS0_POS))
+
+/* 0x88 : psram_intf_delay_ctrl2 */
+#define PSRAM_INTF_DELAY_CTRL2_OFFSET (0x88)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5 PSRAM_REG_DELAY_SEL_O_ADQ5
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_POS (0U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ5_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ5_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ4 PSRAM_REG_DELAY_SEL_O_ADQ4
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_POS (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ4_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ4_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ3 PSRAM_REG_DELAY_SEL_O_ADQ3
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_POS (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ3_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ3_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ2 PSRAM_REG_DELAY_SEL_O_ADQ2
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_POS (24U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ2_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ2_POS))
+
+/* 0x8C : psram_intf_delay_ctrl3 */
+#define PSRAM_INTF_DELAY_CTRL3_OFFSET (0x8C)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1 PSRAM_REG_DELAY_SEL_I_ADQ1
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_POS (0U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ1_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ1_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ0 PSRAM_REG_DELAY_SEL_I_ADQ0
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_POS (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ0_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ0_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ7 PSRAM_REG_DELAY_SEL_O_ADQ7
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_POS (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ7_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ7_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ6 PSRAM_REG_DELAY_SEL_O_ADQ6
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_POS (24U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ6_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ6_POS))
+
+/* 0x90 : psram_intf_delay_ctrl4 */
+#define PSRAM_INTF_DELAY_CTRL4_OFFSET (0x90)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5 PSRAM_REG_DELAY_SEL_I_ADQ5
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_POS (0U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ5_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ5_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ4 PSRAM_REG_DELAY_SEL_I_ADQ4
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_POS (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ4_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ4_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ3 PSRAM_REG_DELAY_SEL_I_ADQ3
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_POS (16U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ3_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ3_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ2 PSRAM_REG_DELAY_SEL_I_ADQ2
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_POS (24U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ2_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ2_POS))
+
+/* 0x94 : psram_intf_delay_ctrl5 */
+#define PSRAM_INTF_DELAY_CTRL5_OFFSET (0x94)
+#define PSRAM_REG_DELAY_SEL_I_DQS0 PSRAM_REG_DELAY_SEL_I_DQS0
+#define PSRAM_REG_DELAY_SEL_I_DQS0_POS (0U)
+#define PSRAM_REG_DELAY_SEL_I_DQS0_LEN (16U)
+#define PSRAM_REG_DELAY_SEL_I_DQS0_MSK (((1U << PSRAM_REG_DELAY_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS0_POS)
+#define PSRAM_REG_DELAY_SEL_I_DQS0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS0_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ7 PSRAM_REG_DELAY_SEL_I_ADQ7
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_POS (16U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ7_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ7_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ6 PSRAM_REG_DELAY_SEL_I_ADQ6
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_POS (24U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ6_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ6_POS))
+
+/* 0x98 : psram_intf_delay_ctrl6 */
+#define PSRAM_INTF_DELAY_CTRL6_OFFSET (0x98)
+#define PSRAM_REG_DELAY_SEL_O_ADQ9 PSRAM_REG_DELAY_SEL_O_ADQ9
+#define PSRAM_REG_DELAY_SEL_O_ADQ9_POS (0U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ9_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ9_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ9_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ9_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ9_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ8 PSRAM_REG_DELAY_SEL_O_ADQ8
+#define PSRAM_REG_DELAY_SEL_O_ADQ8_POS (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ8_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ8_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ8_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ8_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ8_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1 PSRAM_REG_DELAY_SEL_O_ADQ_OEN1
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS))
+#define PSRAM_REG_DELAY_SEL_O_DQS1 PSRAM_REG_DELAY_SEL_O_DQS1
+#define PSRAM_REG_DELAY_SEL_O_DQS1_POS (24U)
+#define PSRAM_REG_DELAY_SEL_O_DQS1_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS1_MSK (((1U << PSRAM_REG_DELAY_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS1_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS1_POS))
+
+/* 0x9C : psram_intf_delay_ctrl7 */
+#define PSRAM_INTF_DELAY_CTRL7_OFFSET (0x9C)
+#define PSRAM_REG_DELAY_SEL_O_ADQ13 PSRAM_REG_DELAY_SEL_O_ADQ13
+#define PSRAM_REG_DELAY_SEL_O_ADQ13_POS (0U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ13_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ13_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ13_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ13_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ13_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ12 PSRAM_REG_DELAY_SEL_O_ADQ12
+#define PSRAM_REG_DELAY_SEL_O_ADQ12_POS (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ12_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ12_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ12_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ12_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ12_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ11 PSRAM_REG_DELAY_SEL_O_ADQ11
+#define PSRAM_REG_DELAY_SEL_O_ADQ11_POS (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ11_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ11_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ11_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ11_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ11_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ10 PSRAM_REG_DELAY_SEL_O_ADQ10
+#define PSRAM_REG_DELAY_SEL_O_ADQ10_POS (24U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ10_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ10_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ10_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ10_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ10_POS))
+
+/* 0xA0 : psram_intf_delay_ctrl8 */
+#define PSRAM_INTF_DELAY_CTRL8_OFFSET (0xA0)
+#define PSRAM_REG_DELAY_SEL_I_ADQ9 PSRAM_REG_DELAY_SEL_I_ADQ9
+#define PSRAM_REG_DELAY_SEL_I_ADQ9_POS (0U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ9_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ9_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ9_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ9_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ9_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ8 PSRAM_REG_DELAY_SEL_I_ADQ8
+#define PSRAM_REG_DELAY_SEL_I_ADQ8_POS (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ8_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ8_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ8_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ8_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ8_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ15 PSRAM_REG_DELAY_SEL_O_ADQ15
+#define PSRAM_REG_DELAY_SEL_O_ADQ15_POS (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ15_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ15_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ15_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ15_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ15_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ14 PSRAM_REG_DELAY_SEL_O_ADQ14
+#define PSRAM_REG_DELAY_SEL_O_ADQ14_POS (24U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ14_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ14_MSK (((1U << PSRAM_REG_DELAY_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ14_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ14_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ14_POS))
+
+/* 0xA4 : psram_intf_delay_ctrl9 */
+#define PSRAM_INTF_DELAY_CTRL9_OFFSET (0xA4)
+#define PSRAM_REG_DELAY_SEL_I_ADQ13 PSRAM_REG_DELAY_SEL_I_ADQ13
+#define PSRAM_REG_DELAY_SEL_I_ADQ13_POS (0U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ13_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ13_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ13_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ13_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ13_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ12 PSRAM_REG_DELAY_SEL_I_ADQ12
+#define PSRAM_REG_DELAY_SEL_I_ADQ12_POS (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ12_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ12_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ12_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ12_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ12_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ11 PSRAM_REG_DELAY_SEL_I_ADQ11
+#define PSRAM_REG_DELAY_SEL_I_ADQ11_POS (16U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ11_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ11_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ11_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ11_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ11_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ10 PSRAM_REG_DELAY_SEL_I_ADQ10
+#define PSRAM_REG_DELAY_SEL_I_ADQ10_POS (24U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ10_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ10_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ10_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ10_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ10_POS))
+
+/* 0xA8 : psram_intf_delay_ctrlA */
+#define PSRAM_INTF_DELAY_CTRLA_OFFSET (0xA8)
+#define PSRAM_REG_DELAY_SEL_I_DQS1 PSRAM_REG_DELAY_SEL_I_DQS1
+#define PSRAM_REG_DELAY_SEL_I_DQS1_POS (0U)
+#define PSRAM_REG_DELAY_SEL_I_DQS1_LEN (16U)
+#define PSRAM_REG_DELAY_SEL_I_DQS1_MSK (((1U << PSRAM_REG_DELAY_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS1_POS)
+#define PSRAM_REG_DELAY_SEL_I_DQS1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS1_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ15 PSRAM_REG_DELAY_SEL_I_ADQ15
+#define PSRAM_REG_DELAY_SEL_I_ADQ15_POS (16U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ15_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ15_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ15_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ15_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ15_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ14 PSRAM_REG_DELAY_SEL_I_ADQ14
+#define PSRAM_REG_DELAY_SEL_I_ADQ14_POS (24U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ14_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ14_MSK (((1U << PSRAM_REG_DELAY_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ14_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ14_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ14_POS))
+
+/* 0xAC : psram_intf_delay_ctrlB */
+#define PSRAM_INTF_DELAY_CTRLB_OFFSET (0xAC)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK PSRAM_REG_DELAY_SEL_O_DQS_MASK
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS (0U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_MSK (((1U << PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS))
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN1 PSRAM_REG_DELAY_SEL_O_DQS_OEN1
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN1_POS (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN1_LEN (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN1_MSK (((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN1_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN1_POS))
+
+/* 0xC0 : psram_dbg_sel */
+#define PSRAM_DBG_SEL_OFFSET (0xC0)
+#define PSRAM_REG_PSRAM_DBG_EN PSRAM_REG_PSRAM_DBG_EN
+#define PSRAM_REG_PSRAM_DBG_EN_POS (0U)
+#define PSRAM_REG_PSRAM_DBG_EN_LEN (1U)
+#define PSRAM_REG_PSRAM_DBG_EN_MSK (((1U << PSRAM_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_REG_PSRAM_DBG_EN_POS)
+#define PSRAM_REG_PSRAM_DBG_EN_UMSK (~(((1U << PSRAM_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_REG_PSRAM_DBG_EN_POS))
+#define PSRAM_REG_PSRAM_DBG_SEL PSRAM_REG_PSRAM_DBG_SEL
+#define PSRAM_REG_PSRAM_DBG_SEL_POS (4U)
+#define PSRAM_REG_PSRAM_DBG_SEL_LEN (4U)
+#define PSRAM_REG_PSRAM_DBG_SEL_MSK (((1U << PSRAM_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_REG_PSRAM_DBG_SEL_POS)
+#define PSRAM_REG_PSRAM_DBG_SEL_UMSK (~(((1U << PSRAM_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_REG_PSRAM_DBG_SEL_POS))
+
+/* 0xF0 : psram_dummy_reg */
+#define PSRAM_DUMMY_REG_OFFSET (0xF0)
+#define PSRAM_REG_PSRAM_DUMMY_REG PSRAM_REG_PSRAM_DUMMY_REG
+#define PSRAM_REG_PSRAM_DUMMY_REG_POS (0U)
+#define PSRAM_REG_PSRAM_DUMMY_REG_LEN (32U)
+#define PSRAM_REG_PSRAM_DUMMY_REG_MSK (((1U << PSRAM_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_REG_PSRAM_DUMMY_REG_POS)
+#define PSRAM_REG_PSRAM_DUMMY_REG_UMSK (~(((1U << PSRAM_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_REG_PSRAM_DUMMY_REG_POS))
+
+/* 0xF4 : psram_timeout_reg */
+#define PSRAM_TIMEOUT_REG_OFFSET (0xF4)
+#define PSRAM_REG_TIMEOUT_EN PSRAM_REG_TIMEOUT_EN
+#define PSRAM_REG_TIMEOUT_EN_POS (0U)
+#define PSRAM_REG_TIMEOUT_EN_LEN (1U)
+#define PSRAM_REG_TIMEOUT_EN_MSK (((1U << PSRAM_REG_TIMEOUT_EN_LEN) - 1) << PSRAM_REG_TIMEOUT_EN_POS)
+#define PSRAM_REG_TIMEOUT_EN_UMSK (~(((1U << PSRAM_REG_TIMEOUT_EN_LEN) - 1) << PSRAM_REG_TIMEOUT_EN_POS))
+#define PSRAM_REG_TIMEOUT_CLR PSRAM_REG_TIMEOUT_CLR
+#define PSRAM_REG_TIMEOUT_CLR_POS (1U)
+#define PSRAM_REG_TIMEOUT_CLR_LEN (1U)
+#define PSRAM_REG_TIMEOUT_CLR_MSK (((1U << PSRAM_REG_TIMEOUT_CLR_LEN) - 1) << PSRAM_REG_TIMEOUT_CLR_POS)
+#define PSRAM_REG_TIMEOUT_CLR_UMSK (~(((1U << PSRAM_REG_TIMEOUT_CLR_LEN) - 1) << PSRAM_REG_TIMEOUT_CLR_POS))
+#define PSRAM_STS_TIMEOUT PSRAM_STS_TIMEOUT
+#define PSRAM_STS_TIMEOUT_POS (2U)
+#define PSRAM_STS_TIMEOUT_LEN (1U)
+#define PSRAM_STS_TIMEOUT_MSK (((1U << PSRAM_STS_TIMEOUT_LEN) - 1) << PSRAM_STS_TIMEOUT_POS)
+#define PSRAM_STS_TIMEOUT_UMSK (~(((1U << PSRAM_STS_TIMEOUT_LEN) - 1) << PSRAM_STS_TIMEOUT_POS))
+#define PSRAM_REG_TIMEOUT_CNT PSRAM_REG_TIMEOUT_CNT
+#define PSRAM_REG_TIMEOUT_CNT_POS (16U)
+#define PSRAM_REG_TIMEOUT_CNT_LEN (12U)
+#define PSRAM_REG_TIMEOUT_CNT_MSK (((1U << PSRAM_REG_TIMEOUT_CNT_LEN) - 1) << PSRAM_REG_TIMEOUT_CNT_POS)
+#define PSRAM_REG_TIMEOUT_CNT_UMSK (~(((1U << PSRAM_REG_TIMEOUT_CNT_LEN) - 1) << PSRAM_REG_TIMEOUT_CNT_POS))
+
+/* 0x100 : psram_rough_delay_ctrl0 */
+#define PSRAM_ROUGH_DELAY_CTRL0_OFFSET (0x100)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0 PSRAM_REG_ROUGH_SEL_O_DQS_OEN0
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_CEB PSRAM_REG_ROUGH_SEL_O_CEB
+#define PSRAM_REG_ROUGH_SEL_O_CEB_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CEB_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CEB_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_CEB_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CEB_POS)
+#define PSRAM_REG_ROUGH_SEL_O_CEB_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_CEB_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CEB_POS))
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N PSRAM_REG_ROUGH_SEL_O_CLK_N
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_N_POS)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_N_POS))
+#define PSRAM_REG_ROUGH_SEL_O_CLK PSRAM_REG_ROUGH_SEL_O_CLK
+#define PSRAM_REG_ROUGH_SEL_O_CLK_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_CLK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_POS)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_CLK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_POS))
+
+/* 0x104 : psram_rough_delay_ctrl1 */
+#define PSRAM_ROUGH_DELAY_CTRL1_OFFSET (0x104)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1 PSRAM_REG_ROUGH_SEL_O_ADQ1
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ1_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0 PSRAM_REG_ROUGH_SEL_O_ADQ0
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0 PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_DQS0 PSRAM_REG_ROUGH_SEL_O_DQS0
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS0_POS))
+
+/* 0x108 : psram_rough_delay_ctrl2 */
+#define PSRAM_ROUGH_DELAY_CTRL2_OFFSET (0x108)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5 PSRAM_REG_ROUGH_SEL_O_ADQ5
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ5_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ5_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4 PSRAM_REG_ROUGH_SEL_O_ADQ4
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ4_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ4_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3 PSRAM_REG_ROUGH_SEL_O_ADQ3
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ3_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ3_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2 PSRAM_REG_ROUGH_SEL_O_ADQ2
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ2_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ2_POS))
+
+/* 0x10C : psram_rough_delay_ctrl3 */
+#define PSRAM_ROUGH_DELAY_CTRL3_OFFSET (0x10C)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1 PSRAM_REG_ROUGH_SEL_I_ADQ1
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ1_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ1_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0 PSRAM_REG_ROUGH_SEL_I_ADQ0
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ0_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7 PSRAM_REG_ROUGH_SEL_O_ADQ7
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ7_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ7_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6 PSRAM_REG_ROUGH_SEL_O_ADQ6
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ6_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ6_POS))
+
+/* 0x110 : psram_rough_delay_ctrl4 */
+#define PSRAM_ROUGH_DELAY_CTRL4_OFFSET (0x110)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5 PSRAM_REG_ROUGH_SEL_I_ADQ5
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ5_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ5_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4 PSRAM_REG_ROUGH_SEL_I_ADQ4
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ4_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ4_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3 PSRAM_REG_ROUGH_SEL_I_ADQ3
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ3_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ3_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2 PSRAM_REG_ROUGH_SEL_I_ADQ2
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ2_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ2_POS))
+
+/* 0x114 : psram_rough_delay_ctrl5 */
+#define PSRAM_ROUGH_DELAY_CTRL5_OFFSET (0x114)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0 PSRAM_REG_ROUGH_SEL_I_DQS0
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_LEN (16U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS0_POS)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS0_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7 PSRAM_REG_ROUGH_SEL_I_ADQ7
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ7_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ7_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6 PSRAM_REG_ROUGH_SEL_I_ADQ6
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ6_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ6_POS))
+
+/* 0x118 : psram_rough_delay_ctrl6 */
+#define PSRAM_ROUGH_DELAY_CTRL6_OFFSET (0x118)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9 PSRAM_REG_ROUGH_SEL_O_ADQ9
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ9_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ9_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8 PSRAM_REG_ROUGH_SEL_O_ADQ8
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ8_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ8_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1 PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS))
+#define PSRAM_REG_ROUGH_SEL_O_DQS1 PSRAM_REG_ROUGH_SEL_O_DQS1
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS1_POS))
+
+/* 0x11C : psram_rough_delay_ctrl7 */
+#define PSRAM_ROUGH_DELAY_CTRL7_OFFSET (0x11C)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13 PSRAM_REG_ROUGH_SEL_O_ADQ13
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ13_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ13_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12 PSRAM_REG_ROUGH_SEL_O_ADQ12
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ12_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ12_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11 PSRAM_REG_ROUGH_SEL_O_ADQ11
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ11_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ11_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10 PSRAM_REG_ROUGH_SEL_O_ADQ10
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ10_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ10_POS))
+
+/* 0x120 : psram_rough_delay_ctrl8 */
+#define PSRAM_ROUGH_DELAY_CTRL8_OFFSET (0x120)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9 PSRAM_REG_ROUGH_SEL_I_ADQ9
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ9_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ9_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8 PSRAM_REG_ROUGH_SEL_I_ADQ8
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ8_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ8_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15 PSRAM_REG_ROUGH_SEL_O_ADQ15
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ15_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ15_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14 PSRAM_REG_ROUGH_SEL_O_ADQ14
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ14_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ14_POS))
+
+/* 0x124 : psram_rough_delay_ctrl9 */
+#define PSRAM_ROUGH_DELAY_CTRL9_OFFSET (0x124)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13 PSRAM_REG_ROUGH_SEL_I_ADQ13
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ13_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ13_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12 PSRAM_REG_ROUGH_SEL_I_ADQ12
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ12_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ12_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11 PSRAM_REG_ROUGH_SEL_I_ADQ11
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ11_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ11_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10 PSRAM_REG_ROUGH_SEL_I_ADQ10
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ10_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ10_POS))
+
+/* 0x128 : psram_rough_delay_ctrlA */
+#define PSRAM_ROUGH_DELAY_CTRLA_OFFSET (0x128)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1 PSRAM_REG_ROUGH_SEL_I_DQS1
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_LEN (16U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS1_POS)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS1_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15 PSRAM_REG_ROUGH_SEL_I_ADQ15
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_POS (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ15_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ15_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14 PSRAM_REG_ROUGH_SEL_I_ADQ14
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_POS (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_MSK (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ14_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ14_POS))
+
+/* 0x12C : psram_rough_delay_ctrlB */
+#define PSRAM_ROUGH_DELAY_CTRLB_OFFSET (0x12C)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK PSRAM_REG_ROUGH_SEL_O_DQS_MASK
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS (0U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS))
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1 PSRAM_REG_ROUGH_SEL_O_DQS_OEN1
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_MSK (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS))
+
+struct psram_reg {
+ /* 0x0 : psram_configure */
+ union {
+ struct
+ {
+ uint32_t reg_vendor_sel : 3; /* [ 2: 0], r/w, 0x2 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t reg_ap_mr : 3; /* [ 6: 4], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_wb_reg_sel : 3; /* [10: 8], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t reg_config_w_pusle : 1; /* [ 12], w1p, 0x0 */
+ uint32_t reg_config_r_pusle : 1; /* [ 13], w1p, 0x0 */
+ uint32_t sts_config_w_done : 1; /* [ 14], r, 0x1 */
+ uint32_t sts_config_r_done : 1; /* [ 15], r, 0x1 */
+ uint32_t reg_config_req : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reg_config_gnt : 1; /* [ 17], r, 0x0 */
+ uint32_t reg_x16_mode : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reg_wb_hyper3 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t reg_pck_s_div : 3; /* [22:20], r/w, 0x0 */
+ uint32_t reg_clkn_free : 1; /* [ 23], r/w, 0x1 */
+ uint32_t reserved_24_27 : 4; /* [27:24], rsvd, 0x0 */
+ uint32_t reg_linear_bnd_b : 4; /* [31:28], r/w, 0xa */
+ } BF;
+ uint32_t WORD;
+ } psram_configure;
+
+ /* 0x4 : psram_manual_control */
+ union {
+ struct
+ {
+ uint32_t reg_wc_sw : 7; /* [ 6: 0], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_wc_sw_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_state_hold_tick : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg_dqs_latch_inv : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg_wb_bl2_mask : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reg_force_ceb_low : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_force_ceb_high : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reg_psram_resetb : 1; /* [ 14], r/w, 0x1 */
+ uint32_t reg_ck_edge_nali : 1; /* [ 15], r/w, 0x0 */
+ uint32_t sts_config_read : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_manual_control;
+
+ /* 0x8 : fifo_thres_control */
+ union {
+ struct
+ {
+ uint32_t reg_mask_w_fifo_cnt : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reg_mask_r_fifo_rem : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } fifo_thres_control;
+
+ /* 0xC : psram_manual_control2 */
+ union {
+ struct
+ {
+ uint32_t reg_hold_cycle_sw : 7; /* [ 6: 0], r/w, 0x8 */
+ uint32_t reg_hc_sw_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_dqs_rel_val : 7; /* [14: 8], r/w, 0x20 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t reg_pwrap_sw_sht_b : 4; /* [19:16], r/w, 0x8 */
+ uint32_t reserved_20_22 : 3; /* [22:20], rsvd, 0x0 */
+ uint32_t reg_pwrap_sw_en : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reg_addr_mask : 8; /* [31:24], r/w, 0x1f */
+ } BF;
+ uint32_t WORD;
+ } psram_manual_control2;
+
+ /* 0x10 : winbond_psram_configure */
+ union {
+ struct
+ {
+ uint32_t reg_wb_latency : 4; /* [ 3: 0], r/w, 0x2 */
+ uint32_t reg_wb_drive_st : 3; /* [ 6: 4], r/w, 0x0 */
+ uint32_t reg_wb_hybrid_en : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reg_wb_burst_length : 3; /* [10: 8], r/w, 0x7 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t reg_wb_fix_latency : 1; /* [ 12], r/w, 0x1 */
+ uint32_t reg_wb_dpd_dis : 1; /* [ 13], r/w, 0x1 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t reg_wb_pasr : 5; /* [20:16], r/w, 0x0 */
+ uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
+ uint32_t reg_wb_hybrid_slp : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_wb_linear_dis : 1; /* [ 25], r/w, 0x0 */
+ uint32_t reserved_26_28 : 3; /* [28:26], rsvd, 0x0 */
+ uint32_t reg_wb_ipd : 1; /* [ 29], r/w, 0x0 */
+ uint32_t reg_wb_mclk_type : 1; /* [ 30], r/w, 0x1 */
+ uint32_t reg_wb_sw_rst : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } winbond_psram_configure;
+
+ /* 0x14 : winbond_psram_status */
+ union {
+ struct
+ {
+ uint32_t sts_wb_latency : 4; /* [ 3: 0], r, 0x2 */
+ uint32_t sts_wb_drive_st : 3; /* [ 6: 4], r, 0x0 */
+ uint32_t sts_wb_hybrid_en : 1; /* [ 7], r, 0x1 */
+ uint32_t sts_wb_burst_length : 3; /* [10: 8], r, 0x3 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t sts_wb_fix_latency : 1; /* [ 12], r, 0x1 */
+ uint32_t sts_wb_dpd_dis : 1; /* [ 13], r, 0x1 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t sts_wb_pasr : 5; /* [20:16], r, 0x0 */
+ uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
+ uint32_t sts_wb_hybrid_slp : 1; /* [ 24], r, 0x0 */
+ uint32_t reserved_25_29 : 5; /* [29:25], rsvd, 0x0 */
+ uint32_t sts_wb_mclk_type : 1; /* [ 30], r, 0x1 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } winbond_psram_status;
+
+ /* 0x18 : winbond_psram_configure2 */
+ union {
+ struct
+ {
+ uint32_t reg_wb_zq_code : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } winbond_psram_configure2;
+
+ /* 0x1c reserved */
+ uint8_t RESERVED0x1c[4];
+
+ /* 0x20 : apmemory_psram_configure */
+ union {
+ struct
+ {
+ uint32_t reg_ap_burst_length : 2; /* [ 1: 0], r/w, 0x1 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t reg_ap_burst_type : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reg_ap_rbx : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_ap_dpd : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_ap_sleep : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_ap_pasr : 3; /* [10: 8], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t reg_ap_w_latency_code : 3; /* [14:12], r/w, 0x2 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t reg_ap_drive_st : 2; /* [17:16], r/w, 0x1 */
+ uint32_t reg_ap_rf : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_ap_r_latency_code : 3; /* [22:20], r/w, 0x2 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t reg_ap_r_latency_type : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reg_ap_linear_dis : 1; /* [ 25], r/w, 0x0 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t reg_glb_reset_pulse : 1; /* [ 28], w1p, 0x0 */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } apmemory_psram_configure;
+
+ /* 0x24 : apmemory_psram_status */
+ union {
+ struct
+ {
+ uint32_t sts_ap_burst_length : 2; /* [ 1: 0], r, 0x1 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t sts_ap_burst_type : 1; /* [ 4], r, 0x1 */
+ uint32_t sts_ap_rbx : 1; /* [ 5], r, 0x0 */
+ uint32_t sts_ap_x16_mode : 1; /* [ 6], r, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t sts_ap_pasr : 3; /* [10: 8], r, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t sts_ap_w_latency_code : 3; /* [14:12], r, 0x2 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t sts_ap_drive_st : 2; /* [17:16], r, 0x1 */
+ uint32_t sts_ap_rf : 2; /* [19:18], r, 0x0 */
+ uint32_t sts_ap_r_latency_code : 3; /* [22:20], r, 0x2 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t sts_ap_r_latency_type : 1; /* [ 24], r, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } apmemory_psram_status;
+
+ /* 0x28 reserved */
+ uint8_t RESERVED0x28[8];
+
+ /* 0x30 : psram_manual_control3 */
+ union {
+ struct
+ {
+ uint32_t reg_adq_rel_val : 7; /* [ 6: 0], r/w, 0x20 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reg_wrap2incr_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_manual_control3;
+
+ /* 0x34 reserved */
+ uint8_t RESERVED0x34[76];
+
+ /* 0x80 : psram_intf_delay_ctrl0 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_o_dqs_oen0 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_ceb : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_clk_n : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_clk : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl0;
+
+ /* 0x84 : psram_intf_delay_ctrl1 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_o_adq1 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq0 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq_oen0 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_dqs0 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl1;
+
+ /* 0x88 : psram_intf_delay_ctrl2 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_o_adq5 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq4 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq3 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq2 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl2;
+
+ /* 0x8C : psram_intf_delay_ctrl3 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_i_adq1 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq0 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq7 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq6 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl3;
+
+ /* 0x90 : psram_intf_delay_ctrl4 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_i_adq5 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq4 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq3 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq2 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl4;
+
+ /* 0x94 : psram_intf_delay_ctrl5 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_i_dqs0 : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq7 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq6 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl5;
+
+ /* 0x98 : psram_intf_delay_ctrl6 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_o_adq9 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq8 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq_oen1 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_dqs1 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl6;
+
+ /* 0x9C : psram_intf_delay_ctrl7 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_o_adq13 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq12 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq11 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq10 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl7;
+
+ /* 0xA0 : psram_intf_delay_ctrl8 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_i_adq9 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq8 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq15 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_adq14 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl8;
+
+ /* 0xA4 : psram_intf_delay_ctrl9 */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_i_adq13 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq12 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq11 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq10 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrl9;
+
+ /* 0xA8 : psram_intf_delay_ctrlA */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_i_dqs1 : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq15 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_delay_sel_i_adq14 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrlA;
+
+ /* 0xAC : psram_intf_delay_ctrlB */
+ union {
+ struct
+ {
+ uint32_t reg_delay_sel_o_dqs_mask : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_delay_sel_o_dqs_oen1 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_intf_delay_ctrlB;
+
+ /* 0xb0 reserved */
+ uint8_t RESERVED0xb0[16];
+
+ /* 0xC0 : psram_dbg_sel */
+ union {
+ struct
+ {
+ uint32_t reg_psram_dbg_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t reg_psram_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_dbg_sel;
+
+ /* 0xc4 reserved */
+ uint8_t RESERVED0xc4[44];
+
+ /* 0xF0 : psram_dummy_reg */
+ union {
+ struct
+ {
+ uint32_t reg_psram_dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */
+ } BF;
+ uint32_t WORD;
+ } psram_dummy_reg;
+
+ /* 0xF4 : psram_timeout_reg */
+ union {
+ struct
+ {
+ uint32_t reg_timeout_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_timeout_clr : 1; /* [ 1], r/w, 0x0 */
+ uint32_t sts_timeout : 1; /* [ 2], r, 0x0 */
+ uint32_t reserved_3_15 : 13; /* [15: 3], rsvd, 0x0 */
+ uint32_t reg_timeout_cnt : 12; /* [27:16], r/w, 0x100 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_timeout_reg;
+
+ /* 0xf8 reserved */
+ uint8_t RESERVED0xf8[8];
+
+ /* 0x100 : psram_rough_delay_ctrl0 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_o_dqs_oen0 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_ceb : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_clk_n : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_clk : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl0;
+
+ /* 0x104 : psram_rough_delay_ctrl1 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_o_adq1 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq0 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq_oen0 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_dqs0 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl1;
+
+ /* 0x108 : psram_rough_delay_ctrl2 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_o_adq5 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq4 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq3 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq2 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl2;
+
+ /* 0x10C : psram_rough_delay_ctrl3 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_i_adq1 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq0 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq7 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq6 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl3;
+
+ /* 0x110 : psram_rough_delay_ctrl4 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_i_adq5 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq4 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq3 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq2 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl4;
+
+ /* 0x114 : psram_rough_delay_ctrl5 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_i_dqs0 : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq7 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq6 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl5;
+
+ /* 0x118 : psram_rough_delay_ctrl6 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_o_adq9 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq8 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq_oen1 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_dqs1 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl6;
+
+ /* 0x11C : psram_rough_delay_ctrl7 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_o_adq13 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq12 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq11 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq10 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl7;
+
+ /* 0x120 : psram_rough_delay_ctrl8 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_i_adq9 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq8 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq15 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_adq14 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl8;
+
+ /* 0x124 : psram_rough_delay_ctrl9 */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_i_adq13 : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq12 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq11 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq10 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrl9;
+
+ /* 0x128 : psram_rough_delay_ctrlA */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_i_dqs1 : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq15 : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_rough_sel_i_adq14 : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrlA;
+
+ /* 0x12C : psram_rough_delay_ctrlB */
+ union {
+ struct
+ {
+ uint32_t reg_rough_sel_o_dqs_mask : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_rough_sel_o_dqs_oen1 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } psram_rough_delay_ctrlB;
+};
+
+typedef volatile struct psram_reg psram_reg_t;
+
+#endif /* __PSRAM_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/psram_uhs_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/psram_uhs_reg.h
new file mode 100644
index 00000000..622e41f6
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/psram_uhs_reg.h
@@ -0,0 +1,1568 @@
+/**
+ ******************************************************************************
+ * @file psram_uhs_reg.h
+ * @version V1.0
+ * @date 2021-07-13
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __PSRAM_UHS_REG_H__
+#define __PSRAM_UHS_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : UHS_basic */
+#define PSRAM_UHS_UHS_BASIC_OFFSET (0x0)
+#define PSRAM_UHS_REG_INIT_EN PSRAM_UHS_REG_INIT_EN
+#define PSRAM_UHS_REG_INIT_EN_POS (0U)
+#define PSRAM_UHS_REG_INIT_EN_LEN (1U)
+#define PSRAM_UHS_REG_INIT_EN_MSK (((1U << PSRAM_UHS_REG_INIT_EN_LEN) - 1) << PSRAM_UHS_REG_INIT_EN_POS)
+#define PSRAM_UHS_REG_INIT_EN_UMSK (~(((1U << PSRAM_UHS_REG_INIT_EN_LEN) - 1) << PSRAM_UHS_REG_INIT_EN_POS))
+#define PSRAM_UHS_REG_AF_EN PSRAM_UHS_REG_AF_EN
+#define PSRAM_UHS_REG_AF_EN_POS (1U)
+#define PSRAM_UHS_REG_AF_EN_LEN (1U)
+#define PSRAM_UHS_REG_AF_EN_MSK (((1U << PSRAM_UHS_REG_AF_EN_LEN) - 1) << PSRAM_UHS_REG_AF_EN_POS)
+#define PSRAM_UHS_REG_AF_EN_UMSK (~(((1U << PSRAM_UHS_REG_AF_EN_LEN) - 1) << PSRAM_UHS_REG_AF_EN_POS))
+#define PSRAM_UHS_REG_CONFIG_REQ PSRAM_UHS_REG_CONFIG_REQ
+#define PSRAM_UHS_REG_CONFIG_REQ_POS (2U)
+#define PSRAM_UHS_REG_CONFIG_REQ_LEN (1U)
+#define PSRAM_UHS_REG_CONFIG_REQ_MSK (((1U << PSRAM_UHS_REG_CONFIG_REQ_LEN) - 1) << PSRAM_UHS_REG_CONFIG_REQ_POS)
+#define PSRAM_UHS_REG_CONFIG_REQ_UMSK (~(((1U << PSRAM_UHS_REG_CONFIG_REQ_LEN) - 1) << PSRAM_UHS_REG_CONFIG_REQ_POS))
+#define PSRAM_UHS_REG_CONFIG_GNT PSRAM_UHS_REG_CONFIG_GNT
+#define PSRAM_UHS_REG_CONFIG_GNT_POS (3U)
+#define PSRAM_UHS_REG_CONFIG_GNT_LEN (1U)
+#define PSRAM_UHS_REG_CONFIG_GNT_MSK (((1U << PSRAM_UHS_REG_CONFIG_GNT_LEN) - 1) << PSRAM_UHS_REG_CONFIG_GNT_POS)
+#define PSRAM_UHS_REG_CONFIG_GNT_UMSK (~(((1U << PSRAM_UHS_REG_CONFIG_GNT_LEN) - 1) << PSRAM_UHS_REG_CONFIG_GNT_POS))
+#define PSRAM_UHS_REG_MODE_REG PSRAM_UHS_REG_MODE_REG
+#define PSRAM_UHS_REG_MODE_REG_POS (8U)
+#define PSRAM_UHS_REG_MODE_REG_LEN (8U)
+#define PSRAM_UHS_REG_MODE_REG_MSK (((1U << PSRAM_UHS_REG_MODE_REG_LEN) - 1) << PSRAM_UHS_REG_MODE_REG_POS)
+#define PSRAM_UHS_REG_MODE_REG_UMSK (~(((1U << PSRAM_UHS_REG_MODE_REG_LEN) - 1) << PSRAM_UHS_REG_MODE_REG_POS))
+#define PSRAM_UHS_REG_ADDRMB_MSK PSRAM_UHS_REG_ADDRMB_MSK
+#define PSRAM_UHS_REG_ADDRMB_MSK_POS (16U)
+#define PSRAM_UHS_REG_ADDRMB_MSK_LEN (8U)
+#define PSRAM_UHS_REG_ADDRMB_MSK_MSK (((1U << PSRAM_UHS_REG_ADDRMB_MSK_LEN) - 1) << PSRAM_UHS_REG_ADDRMB_MSK_POS)
+#define PSRAM_UHS_REG_ADDRMB_MSK_UMSK (~(((1U << PSRAM_UHS_REG_ADDRMB_MSK_LEN) - 1) << PSRAM_UHS_REG_ADDRMB_MSK_POS))
+#define PSRAM_UHS_REG_LINEAR_BND_B PSRAM_UHS_REG_LINEAR_BND_B
+#define PSRAM_UHS_REG_LINEAR_BND_B_POS (28U)
+#define PSRAM_UHS_REG_LINEAR_BND_B_LEN (4U)
+#define PSRAM_UHS_REG_LINEAR_BND_B_MSK (((1U << PSRAM_UHS_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_UHS_REG_LINEAR_BND_B_POS)
+#define PSRAM_UHS_REG_LINEAR_BND_B_UMSK (~(((1U << PSRAM_UHS_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_UHS_REG_LINEAR_BND_B_POS))
+
+/* 0x4 : UHS_cmd */
+#define PSRAM_UHS_UHS_CMD_OFFSET (0x4)
+#define PSRAM_UHS_REG_GLBR_PULSE PSRAM_UHS_REG_GLBR_PULSE
+#define PSRAM_UHS_REG_GLBR_PULSE_POS (0U)
+#define PSRAM_UHS_REG_GLBR_PULSE_LEN (1U)
+#define PSRAM_UHS_REG_GLBR_PULSE_MSK (((1U << PSRAM_UHS_REG_GLBR_PULSE_LEN) - 1) << PSRAM_UHS_REG_GLBR_PULSE_POS)
+#define PSRAM_UHS_REG_GLBR_PULSE_UMSK (~(((1U << PSRAM_UHS_REG_GLBR_PULSE_LEN) - 1) << PSRAM_UHS_REG_GLBR_PULSE_POS))
+#define PSRAM_UHS_REG_SRFI_PULSE PSRAM_UHS_REG_SRFI_PULSE
+#define PSRAM_UHS_REG_SRFI_PULSE_POS (1U)
+#define PSRAM_UHS_REG_SRFI_PULSE_LEN (1U)
+#define PSRAM_UHS_REG_SRFI_PULSE_MSK (((1U << PSRAM_UHS_REG_SRFI_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFI_PULSE_POS)
+#define PSRAM_UHS_REG_SRFI_PULSE_UMSK (~(((1U << PSRAM_UHS_REG_SRFI_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFI_PULSE_POS))
+#define PSRAM_UHS_REG_SRFO_PULSE PSRAM_UHS_REG_SRFO_PULSE
+#define PSRAM_UHS_REG_SRFO_PULSE_POS (2U)
+#define PSRAM_UHS_REG_SRFO_PULSE_LEN (1U)
+#define PSRAM_UHS_REG_SRFO_PULSE_MSK (((1U << PSRAM_UHS_REG_SRFO_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFO_PULSE_POS)
+#define PSRAM_UHS_REG_SRFO_PULSE_UMSK (~(((1U << PSRAM_UHS_REG_SRFO_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFO_PULSE_POS))
+#define PSRAM_UHS_REG_REGW_PULSE PSRAM_UHS_REG_REGW_PULSE
+#define PSRAM_UHS_REG_REGW_PULSE_POS (3U)
+#define PSRAM_UHS_REG_REGW_PULSE_LEN (1U)
+#define PSRAM_UHS_REG_REGW_PULSE_MSK (((1U << PSRAM_UHS_REG_REGW_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGW_PULSE_POS)
+#define PSRAM_UHS_REG_REGW_PULSE_UMSK (~(((1U << PSRAM_UHS_REG_REGW_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGW_PULSE_POS))
+#define PSRAM_UHS_REG_REGR_PULSE PSRAM_UHS_REG_REGR_PULSE
+#define PSRAM_UHS_REG_REGR_PULSE_POS (4U)
+#define PSRAM_UHS_REG_REGR_PULSE_LEN (1U)
+#define PSRAM_UHS_REG_REGR_PULSE_MSK (((1U << PSRAM_UHS_REG_REGR_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGR_PULSE_POS)
+#define PSRAM_UHS_REG_REGR_PULSE_UMSK (~(((1U << PSRAM_UHS_REG_REGR_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGR_PULSE_POS))
+#define PSRAM_UHS_STS_GLBR_DONE PSRAM_UHS_STS_GLBR_DONE
+#define PSRAM_UHS_STS_GLBR_DONE_POS (8U)
+#define PSRAM_UHS_STS_GLBR_DONE_LEN (1U)
+#define PSRAM_UHS_STS_GLBR_DONE_MSK (((1U << PSRAM_UHS_STS_GLBR_DONE_LEN) - 1) << PSRAM_UHS_STS_GLBR_DONE_POS)
+#define PSRAM_UHS_STS_GLBR_DONE_UMSK (~(((1U << PSRAM_UHS_STS_GLBR_DONE_LEN) - 1) << PSRAM_UHS_STS_GLBR_DONE_POS))
+#define PSRAM_UHS_STS_SRFI_DONE PSRAM_UHS_STS_SRFI_DONE
+#define PSRAM_UHS_STS_SRFI_DONE_POS (9U)
+#define PSRAM_UHS_STS_SRFI_DONE_LEN (1U)
+#define PSRAM_UHS_STS_SRFI_DONE_MSK (((1U << PSRAM_UHS_STS_SRFI_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFI_DONE_POS)
+#define PSRAM_UHS_STS_SRFI_DONE_UMSK (~(((1U << PSRAM_UHS_STS_SRFI_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFI_DONE_POS))
+#define PSRAM_UHS_STS_SRFO_DONE PSRAM_UHS_STS_SRFO_DONE
+#define PSRAM_UHS_STS_SRFO_DONE_POS (10U)
+#define PSRAM_UHS_STS_SRFO_DONE_LEN (1U)
+#define PSRAM_UHS_STS_SRFO_DONE_MSK (((1U << PSRAM_UHS_STS_SRFO_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFO_DONE_POS)
+#define PSRAM_UHS_STS_SRFO_DONE_UMSK (~(((1U << PSRAM_UHS_STS_SRFO_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFO_DONE_POS))
+#define PSRAM_UHS_STS_REGW_DONE PSRAM_UHS_STS_REGW_DONE
+#define PSRAM_UHS_STS_REGW_DONE_POS (11U)
+#define PSRAM_UHS_STS_REGW_DONE_LEN (1U)
+#define PSRAM_UHS_STS_REGW_DONE_MSK (((1U << PSRAM_UHS_STS_REGW_DONE_LEN) - 1) << PSRAM_UHS_STS_REGW_DONE_POS)
+#define PSRAM_UHS_STS_REGW_DONE_UMSK (~(((1U << PSRAM_UHS_STS_REGW_DONE_LEN) - 1) << PSRAM_UHS_STS_REGW_DONE_POS))
+#define PSRAM_UHS_STS_REGR_DONE PSRAM_UHS_STS_REGR_DONE
+#define PSRAM_UHS_STS_REGR_DONE_POS (12U)
+#define PSRAM_UHS_STS_REGR_DONE_LEN (1U)
+#define PSRAM_UHS_STS_REGR_DONE_MSK (((1U << PSRAM_UHS_STS_REGR_DONE_LEN) - 1) << PSRAM_UHS_STS_REGR_DONE_POS)
+#define PSRAM_UHS_STS_REGR_DONE_UMSK (~(((1U << PSRAM_UHS_STS_REGR_DONE_LEN) - 1) << PSRAM_UHS_STS_REGR_DONE_POS))
+#define PSRAM_UHS_STS_INIT_DONE PSRAM_UHS_STS_INIT_DONE
+#define PSRAM_UHS_STS_INIT_DONE_POS (13U)
+#define PSRAM_UHS_STS_INIT_DONE_LEN (1U)
+#define PSRAM_UHS_STS_INIT_DONE_MSK (((1U << PSRAM_UHS_STS_INIT_DONE_LEN) - 1) << PSRAM_UHS_STS_INIT_DONE_POS)
+#define PSRAM_UHS_STS_INIT_DONE_UMSK (~(((1U << PSRAM_UHS_STS_INIT_DONE_LEN) - 1) << PSRAM_UHS_STS_INIT_DONE_POS))
+#define PSRAM_UHS_STS_CONFIG_READ PSRAM_UHS_STS_CONFIG_READ
+#define PSRAM_UHS_STS_CONFIG_READ_POS (24U)
+#define PSRAM_UHS_STS_CONFIG_READ_LEN (8U)
+#define PSRAM_UHS_STS_CONFIG_READ_MSK (((1U << PSRAM_UHS_STS_CONFIG_READ_LEN) - 1) << PSRAM_UHS_STS_CONFIG_READ_POS)
+#define PSRAM_UHS_STS_CONFIG_READ_UMSK (~(((1U << PSRAM_UHS_STS_CONFIG_READ_LEN) - 1) << PSRAM_UHS_STS_CONFIG_READ_POS))
+
+/* 0x8 : UHS_fifo_thre */
+#define PSRAM_UHS_UHS_FIFO_THRE_OFFSET (0x8)
+#define PSRAM_UHS_REG_MASK_W_FIFO_CNT PSRAM_UHS_REG_MASK_W_FIFO_CNT
+#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_POS (0U)
+#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_LEN (16U)
+#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_MSK (((1U << PSRAM_UHS_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_UHS_REG_MASK_W_FIFO_CNT_POS)
+#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_UMSK (~(((1U << PSRAM_UHS_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_UHS_REG_MASK_W_FIFO_CNT_POS))
+#define PSRAM_UHS_REG_MASK_R_FIFO_REM PSRAM_UHS_REG_MASK_R_FIFO_REM
+#define PSRAM_UHS_REG_MASK_R_FIFO_REM_POS (16U)
+#define PSRAM_UHS_REG_MASK_R_FIFO_REM_LEN (16U)
+#define PSRAM_UHS_REG_MASK_R_FIFO_REM_MSK (((1U << PSRAM_UHS_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_UHS_REG_MASK_R_FIFO_REM_POS)
+#define PSRAM_UHS_REG_MASK_R_FIFO_REM_UMSK (~(((1U << PSRAM_UHS_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_UHS_REG_MASK_R_FIFO_REM_POS))
+
+/* 0xC : UHS_manual */
+#define PSRAM_UHS_UHS_MANUAL_OFFSET (0xC)
+#define PSRAM_UHS_REG_FORCE_CEB_LOW PSRAM_UHS_REG_FORCE_CEB_LOW
+#define PSRAM_UHS_REG_FORCE_CEB_LOW_POS (0U)
+#define PSRAM_UHS_REG_FORCE_CEB_LOW_LEN (1U)
+#define PSRAM_UHS_REG_FORCE_CEB_LOW_MSK (((1U << PSRAM_UHS_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_LOW_POS)
+#define PSRAM_UHS_REG_FORCE_CEB_LOW_UMSK (~(((1U << PSRAM_UHS_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_LOW_POS))
+#define PSRAM_UHS_REG_FORCE_CEB_HIGH PSRAM_UHS_REG_FORCE_CEB_HIGH
+#define PSRAM_UHS_REG_FORCE_CEB_HIGH_POS (1U)
+#define PSRAM_UHS_REG_FORCE_CEB_HIGH_LEN (1U)
+#define PSRAM_UHS_REG_FORCE_CEB_HIGH_MSK (((1U << PSRAM_UHS_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_HIGH_POS)
+#define PSRAM_UHS_REG_FORCE_CEB_HIGH_UMSK (~(((1U << PSRAM_UHS_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_HIGH_POS))
+#define PSRAM_UHS_REG_PSRAM_RESETB PSRAM_UHS_REG_PSRAM_RESETB
+#define PSRAM_UHS_REG_PSRAM_RESETB_POS (2U)
+#define PSRAM_UHS_REG_PSRAM_RESETB_LEN (1U)
+#define PSRAM_UHS_REG_PSRAM_RESETB_MSK (((1U << PSRAM_UHS_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_UHS_REG_PSRAM_RESETB_POS)
+#define PSRAM_UHS_REG_PSRAM_RESETB_UMSK (~(((1U << PSRAM_UHS_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_UHS_REG_PSRAM_RESETB_POS))
+#define PSRAM_UHS_REG_X16_MODE PSRAM_UHS_REG_X16_MODE
+#define PSRAM_UHS_REG_X16_MODE_POS (3U)
+#define PSRAM_UHS_REG_X16_MODE_LEN (1U)
+#define PSRAM_UHS_REG_X16_MODE_MSK (((1U << PSRAM_UHS_REG_X16_MODE_LEN) - 1) << PSRAM_UHS_REG_X16_MODE_POS)
+#define PSRAM_UHS_REG_X16_MODE_UMSK (~(((1U << PSRAM_UHS_REG_X16_MODE_LEN) - 1) << PSRAM_UHS_REG_X16_MODE_POS))
+#define PSRAM_UHS_REG_WRAP2INCR_EN PSRAM_UHS_REG_WRAP2INCR_EN
+#define PSRAM_UHS_REG_WRAP2INCR_EN_POS (4U)
+#define PSRAM_UHS_REG_WRAP2INCR_EN_LEN (1U)
+#define PSRAM_UHS_REG_WRAP2INCR_EN_MSK (((1U << PSRAM_UHS_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_UHS_REG_WRAP2INCR_EN_POS)
+#define PSRAM_UHS_REG_WRAP2INCR_EN_UMSK (~(((1U << PSRAM_UHS_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_UHS_REG_WRAP2INCR_EN_POS))
+#define PSRAM_UHS_REG_PCK_S_DIV PSRAM_UHS_REG_PCK_S_DIV
+#define PSRAM_UHS_REG_PCK_S_DIV_POS (16U)
+#define PSRAM_UHS_REG_PCK_S_DIV_LEN (3U)
+#define PSRAM_UHS_REG_PCK_S_DIV_MSK (((1U << PSRAM_UHS_REG_PCK_S_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_S_DIV_POS)
+#define PSRAM_UHS_REG_PCK_S_DIV_UMSK (~(((1U << PSRAM_UHS_REG_PCK_S_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_S_DIV_POS))
+#define PSRAM_UHS_REG_PCK_T_DIV PSRAM_UHS_REG_PCK_T_DIV
+#define PSRAM_UHS_REG_PCK_T_DIV_POS (24U)
+#define PSRAM_UHS_REG_PCK_T_DIV_LEN (8U)
+#define PSRAM_UHS_REG_PCK_T_DIV_MSK (((1U << PSRAM_UHS_REG_PCK_T_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_T_DIV_POS)
+#define PSRAM_UHS_REG_PCK_T_DIV_UMSK (~(((1U << PSRAM_UHS_REG_PCK_T_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_T_DIV_POS))
+
+/* 0x10 : UHS_auto_fresh_1 */
+#define PSRAM_UHS_UHS_AUTO_FRESH_1_OFFSET (0x10)
+#define PSRAM_UHS_REG_WIN_CYCLE PSRAM_UHS_REG_WIN_CYCLE
+#define PSRAM_UHS_REG_WIN_CYCLE_POS (0U)
+#define PSRAM_UHS_REG_WIN_CYCLE_LEN (28U)
+#define PSRAM_UHS_REG_WIN_CYCLE_MSK (((1U << PSRAM_UHS_REG_WIN_CYCLE_LEN) - 1) << PSRAM_UHS_REG_WIN_CYCLE_POS)
+#define PSRAM_UHS_REG_WIN_CYCLE_UMSK (~(((1U << PSRAM_UHS_REG_WIN_CYCLE_LEN) - 1) << PSRAM_UHS_REG_WIN_CYCLE_POS))
+
+/* 0x14 : UHS_auto_fresh_2 */
+#define PSRAM_UHS_UHS_AUTO_FRESH_2_OFFSET (0x14)
+#define PSRAM_UHS_REG_REFI_CYCLE PSRAM_UHS_REG_REFI_CYCLE
+#define PSRAM_UHS_REG_REFI_CYCLE_POS (0U)
+#define PSRAM_UHS_REG_REFI_CYCLE_LEN (16U)
+#define PSRAM_UHS_REG_REFI_CYCLE_MSK (((1U << PSRAM_UHS_REG_REFI_CYCLE_LEN) - 1) << PSRAM_UHS_REG_REFI_CYCLE_POS)
+#define PSRAM_UHS_REG_REFI_CYCLE_UMSK (~(((1U << PSRAM_UHS_REG_REFI_CYCLE_LEN) - 1) << PSRAM_UHS_REG_REFI_CYCLE_POS))
+#define PSRAM_UHS_REG_WIN_REF_CNT PSRAM_UHS_REG_WIN_REF_CNT
+#define PSRAM_UHS_REG_WIN_REF_CNT_POS (16U)
+#define PSRAM_UHS_REG_WIN_REF_CNT_LEN (13U)
+#define PSRAM_UHS_REG_WIN_REF_CNT_MSK (((1U << PSRAM_UHS_REG_WIN_REF_CNT_LEN) - 1) << PSRAM_UHS_REG_WIN_REF_CNT_POS)
+#define PSRAM_UHS_REG_WIN_REF_CNT_UMSK (~(((1U << PSRAM_UHS_REG_WIN_REF_CNT_LEN) - 1) << PSRAM_UHS_REG_WIN_REF_CNT_POS))
+
+/* 0x18 : UHS_auto_fresh_3 */
+#define PSRAM_UHS_UHS_AUTO_FRESH_3_OFFSET (0x18)
+#define PSRAM_UHS_REG_AUTO_REF_THRE PSRAM_UHS_REG_AUTO_REF_THRE
+#define PSRAM_UHS_REG_AUTO_REF_THRE_POS (0U)
+#define PSRAM_UHS_REG_AUTO_REF_THRE_LEN (12U)
+#define PSRAM_UHS_REG_AUTO_REF_THRE_MSK (((1U << PSRAM_UHS_REG_AUTO_REF_THRE_LEN) - 1) << PSRAM_UHS_REG_AUTO_REF_THRE_POS)
+#define PSRAM_UHS_REG_AUTO_REF_THRE_UMSK (~(((1U << PSRAM_UHS_REG_AUTO_REF_THRE_LEN) - 1) << PSRAM_UHS_REG_AUTO_REF_THRE_POS))
+#define PSRAM_UHS_AUTO_REFRESH_LEVEL PSRAM_UHS_AUTO_REFRESH_LEVEL
+#define PSRAM_UHS_AUTO_REFRESH_LEVEL_POS (16U)
+#define PSRAM_UHS_AUTO_REFRESH_LEVEL_LEN (12U)
+#define PSRAM_UHS_AUTO_REFRESH_LEVEL_MSK (((1U << PSRAM_UHS_AUTO_REFRESH_LEVEL_LEN) - 1) << PSRAM_UHS_AUTO_REFRESH_LEVEL_POS)
+#define PSRAM_UHS_AUTO_REFRESH_LEVEL_UMSK (~(((1U << PSRAM_UHS_AUTO_REFRESH_LEVEL_LEN) - 1) << PSRAM_UHS_AUTO_REFRESH_LEVEL_POS))
+
+/* 0x1C : UHS_auto_fresh_4 */
+#define PSRAM_UHS_UHS_AUTO_FRESH_4_OFFSET (0x1C)
+#define PSRAM_UHS_REG_BUST_CYCLE PSRAM_UHS_REG_BUST_CYCLE
+#define PSRAM_UHS_REG_BUST_CYCLE_POS (0U)
+#define PSRAM_UHS_REG_BUST_CYCLE_LEN (7U)
+#define PSRAM_UHS_REG_BUST_CYCLE_MSK (((1U << PSRAM_UHS_REG_BUST_CYCLE_LEN) - 1) << PSRAM_UHS_REG_BUST_CYCLE_POS)
+#define PSRAM_UHS_REG_BUST_CYCLE_UMSK (~(((1U << PSRAM_UHS_REG_BUST_CYCLE_LEN) - 1) << PSRAM_UHS_REG_BUST_CYCLE_POS))
+
+/* 0x20 : UHS_psram_configure */
+#define PSRAM_UHS_UHS_PSRAM_CONFIGURE_OFFSET (0x20)
+#define PSRAM_UHS_REG_UHS_LATENCY PSRAM_UHS_REG_UHS_LATENCY
+#define PSRAM_UHS_REG_UHS_LATENCY_POS (0U)
+#define PSRAM_UHS_REG_UHS_LATENCY_LEN (3U)
+#define PSRAM_UHS_REG_UHS_LATENCY_MSK (((1U << PSRAM_UHS_REG_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_REG_UHS_LATENCY_POS)
+#define PSRAM_UHS_REG_UHS_LATENCY_UMSK (~(((1U << PSRAM_UHS_REG_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_REG_UHS_LATENCY_POS))
+#define PSRAM_UHS_REG_UHS_DRIVE_ST PSRAM_UHS_REG_UHS_DRIVE_ST
+#define PSRAM_UHS_REG_UHS_DRIVE_ST_POS (4U)
+#define PSRAM_UHS_REG_UHS_DRIVE_ST_LEN (4U)
+#define PSRAM_UHS_REG_UHS_DRIVE_ST_MSK (((1U << PSRAM_UHS_REG_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_REG_UHS_DRIVE_ST_POS)
+#define PSRAM_UHS_REG_UHS_DRIVE_ST_UMSK (~(((1U << PSRAM_UHS_REG_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_REG_UHS_DRIVE_ST_POS))
+#define PSRAM_UHS_REG_UHS_BL_16 PSRAM_UHS_REG_UHS_BL_16
+#define PSRAM_UHS_REG_UHS_BL_16_POS (8U)
+#define PSRAM_UHS_REG_UHS_BL_16_LEN (1U)
+#define PSRAM_UHS_REG_UHS_BL_16_MSK (((1U << PSRAM_UHS_REG_UHS_BL_16_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_16_POS)
+#define PSRAM_UHS_REG_UHS_BL_16_UMSK (~(((1U << PSRAM_UHS_REG_UHS_BL_16_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_16_POS))
+#define PSRAM_UHS_REG_UHS_BL_32 PSRAM_UHS_REG_UHS_BL_32
+#define PSRAM_UHS_REG_UHS_BL_32_POS (9U)
+#define PSRAM_UHS_REG_UHS_BL_32_LEN (1U)
+#define PSRAM_UHS_REG_UHS_BL_32_MSK (((1U << PSRAM_UHS_REG_UHS_BL_32_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_32_POS)
+#define PSRAM_UHS_REG_UHS_BL_32_UMSK (~(((1U << PSRAM_UHS_REG_UHS_BL_32_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_32_POS))
+#define PSRAM_UHS_REG_UHS_BL_64 PSRAM_UHS_REG_UHS_BL_64
+#define PSRAM_UHS_REG_UHS_BL_64_POS (10U)
+#define PSRAM_UHS_REG_UHS_BL_64_LEN (1U)
+#define PSRAM_UHS_REG_UHS_BL_64_MSK (((1U << PSRAM_UHS_REG_UHS_BL_64_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_64_POS)
+#define PSRAM_UHS_REG_UHS_BL_64_UMSK (~(((1U << PSRAM_UHS_REG_UHS_BL_64_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_64_POS))
+
+/* 0x24 : UHS_psram_status */
+#define PSRAM_UHS_UHS_PSRAM_STATUS_OFFSET (0x24)
+#define PSRAM_UHS_STS_UHS_LATENCY PSRAM_UHS_STS_UHS_LATENCY
+#define PSRAM_UHS_STS_UHS_LATENCY_POS (0U)
+#define PSRAM_UHS_STS_UHS_LATENCY_LEN (3U)
+#define PSRAM_UHS_STS_UHS_LATENCY_MSK (((1U << PSRAM_UHS_STS_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_STS_UHS_LATENCY_POS)
+#define PSRAM_UHS_STS_UHS_LATENCY_UMSK (~(((1U << PSRAM_UHS_STS_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_STS_UHS_LATENCY_POS))
+#define PSRAM_UHS_STS_UHS_DRIVE_ST PSRAM_UHS_STS_UHS_DRIVE_ST
+#define PSRAM_UHS_STS_UHS_DRIVE_ST_POS (4U)
+#define PSRAM_UHS_STS_UHS_DRIVE_ST_LEN (4U)
+#define PSRAM_UHS_STS_UHS_DRIVE_ST_MSK (((1U << PSRAM_UHS_STS_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_STS_UHS_DRIVE_ST_POS)
+#define PSRAM_UHS_STS_UHS_DRIVE_ST_UMSK (~(((1U << PSRAM_UHS_STS_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_STS_UHS_DRIVE_ST_POS))
+#define PSRAM_UHS_STS_UHS_BL_16 PSRAM_UHS_STS_UHS_BL_16
+#define PSRAM_UHS_STS_UHS_BL_16_POS (8U)
+#define PSRAM_UHS_STS_UHS_BL_16_LEN (1U)
+#define PSRAM_UHS_STS_UHS_BL_16_MSK (((1U << PSRAM_UHS_STS_UHS_BL_16_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_16_POS)
+#define PSRAM_UHS_STS_UHS_BL_16_UMSK (~(((1U << PSRAM_UHS_STS_UHS_BL_16_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_16_POS))
+#define PSRAM_UHS_STS_UHS_BL_32 PSRAM_UHS_STS_UHS_BL_32
+#define PSRAM_UHS_STS_UHS_BL_32_POS (9U)
+#define PSRAM_UHS_STS_UHS_BL_32_LEN (1U)
+#define PSRAM_UHS_STS_UHS_BL_32_MSK (((1U << PSRAM_UHS_STS_UHS_BL_32_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_32_POS)
+#define PSRAM_UHS_STS_UHS_BL_32_UMSK (~(((1U << PSRAM_UHS_STS_UHS_BL_32_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_32_POS))
+#define PSRAM_UHS_STS_UHS_BL_64 PSRAM_UHS_STS_UHS_BL_64
+#define PSRAM_UHS_STS_UHS_BL_64_POS (10U)
+#define PSRAM_UHS_STS_UHS_BL_64_LEN (1U)
+#define PSRAM_UHS_STS_UHS_BL_64_MSK (((1U << PSRAM_UHS_STS_UHS_BL_64_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_64_POS)
+#define PSRAM_UHS_STS_UHS_BL_64_UMSK (~(((1U << PSRAM_UHS_STS_UHS_BL_64_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_64_POS))
+
+/* 0x30 : UHS_timing_ctrl */
+#define PSRAM_UHS_UHS_TIMING_CTRL_OFFSET (0x30)
+#define PSRAM_UHS_REG_TRC_CYCLE PSRAM_UHS_REG_TRC_CYCLE
+#define PSRAM_UHS_REG_TRC_CYCLE_POS (0U)
+#define PSRAM_UHS_REG_TRC_CYCLE_LEN (8U)
+#define PSRAM_UHS_REG_TRC_CYCLE_MSK (((1U << PSRAM_UHS_REG_TRC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRC_CYCLE_POS)
+#define PSRAM_UHS_REG_TRC_CYCLE_UMSK (~(((1U << PSRAM_UHS_REG_TRC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRC_CYCLE_POS))
+#define PSRAM_UHS_REG_TCPHR_CYCLE PSRAM_UHS_REG_TCPHR_CYCLE
+#define PSRAM_UHS_REG_TCPHR_CYCLE_POS (8U)
+#define PSRAM_UHS_REG_TCPHR_CYCLE_LEN (8U)
+#define PSRAM_UHS_REG_TCPHR_CYCLE_MSK (((1U << PSRAM_UHS_REG_TCPHR_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHR_CYCLE_POS)
+#define PSRAM_UHS_REG_TCPHR_CYCLE_UMSK (~(((1U << PSRAM_UHS_REG_TCPHR_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHR_CYCLE_POS))
+#define PSRAM_UHS_REG_TCPHW_CYCLE PSRAM_UHS_REG_TCPHW_CYCLE
+#define PSRAM_UHS_REG_TCPHW_CYCLE_POS (16U)
+#define PSRAM_UHS_REG_TCPHW_CYCLE_LEN (8U)
+#define PSRAM_UHS_REG_TCPHW_CYCLE_MSK (((1U << PSRAM_UHS_REG_TCPHW_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHW_CYCLE_POS)
+#define PSRAM_UHS_REG_TCPHW_CYCLE_UMSK (~(((1U << PSRAM_UHS_REG_TCPHW_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHW_CYCLE_POS))
+#define PSRAM_UHS_REG_TRFC_CYCLE PSRAM_UHS_REG_TRFC_CYCLE
+#define PSRAM_UHS_REG_TRFC_CYCLE_POS (24U)
+#define PSRAM_UHS_REG_TRFC_CYCLE_LEN (8U)
+#define PSRAM_UHS_REG_TRFC_CYCLE_MSK (((1U << PSRAM_UHS_REG_TRFC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRFC_CYCLE_POS)
+#define PSRAM_UHS_REG_TRFC_CYCLE_UMSK (~(((1U << PSRAM_UHS_REG_TRFC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRFC_CYCLE_POS))
+
+/* 0x34 : UHS_rsvd_reg */
+#define PSRAM_UHS_UHS_RSVD_REG_OFFSET (0x34)
+#define PSRAM_UHS_REG_MR0_7 PSRAM_UHS_REG_MR0_7
+#define PSRAM_UHS_REG_MR0_7_POS (0U)
+#define PSRAM_UHS_REG_MR0_7_LEN (1U)
+#define PSRAM_UHS_REG_MR0_7_MSK (((1U << PSRAM_UHS_REG_MR0_7_LEN) - 1) << PSRAM_UHS_REG_MR0_7_POS)
+#define PSRAM_UHS_REG_MR0_7_UMSK (~(((1U << PSRAM_UHS_REG_MR0_7_LEN) - 1) << PSRAM_UHS_REG_MR0_7_POS))
+#define PSRAM_UHS_REG_MR2_2_0 PSRAM_UHS_REG_MR2_2_0
+#define PSRAM_UHS_REG_MR2_2_0_POS (1U)
+#define PSRAM_UHS_REG_MR2_2_0_LEN (3U)
+#define PSRAM_UHS_REG_MR2_2_0_MSK (((1U << PSRAM_UHS_REG_MR2_2_0_LEN) - 1) << PSRAM_UHS_REG_MR2_2_0_POS)
+#define PSRAM_UHS_REG_MR2_2_0_UMSK (~(((1U << PSRAM_UHS_REG_MR2_2_0_LEN) - 1) << PSRAM_UHS_REG_MR2_2_0_POS))
+#define PSRAM_UHS_REG_MR2_7_6 PSRAM_UHS_REG_MR2_7_6
+#define PSRAM_UHS_REG_MR2_7_6_POS (4U)
+#define PSRAM_UHS_REG_MR2_7_6_LEN (2U)
+#define PSRAM_UHS_REG_MR2_7_6_MSK (((1U << PSRAM_UHS_REG_MR2_7_6_LEN) - 1) << PSRAM_UHS_REG_MR2_7_6_POS)
+#define PSRAM_UHS_REG_MR2_7_6_UMSK (~(((1U << PSRAM_UHS_REG_MR2_7_6_LEN) - 1) << PSRAM_UHS_REG_MR2_7_6_POS))
+
+/* 0xC0 : UHS_dbg_sel */
+#define PSRAM_UHS_UHS_DBG_SEL_OFFSET (0xC0)
+#define PSRAM_UHS_REG_PSRAM_DBG_EN PSRAM_UHS_REG_PSRAM_DBG_EN
+#define PSRAM_UHS_REG_PSRAM_DBG_EN_POS (0U)
+#define PSRAM_UHS_REG_PSRAM_DBG_EN_LEN (1U)
+#define PSRAM_UHS_REG_PSRAM_DBG_EN_MSK (((1U << PSRAM_UHS_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_EN_POS)
+#define PSRAM_UHS_REG_PSRAM_DBG_EN_UMSK (~(((1U << PSRAM_UHS_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_EN_POS))
+#define PSRAM_UHS_REG_PSRAM_DBG_SEL PSRAM_UHS_REG_PSRAM_DBG_SEL
+#define PSRAM_UHS_REG_PSRAM_DBG_SEL_POS (4U)
+#define PSRAM_UHS_REG_PSRAM_DBG_SEL_LEN (4U)
+#define PSRAM_UHS_REG_PSRAM_DBG_SEL_MSK (((1U << PSRAM_UHS_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_SEL_POS)
+#define PSRAM_UHS_REG_PSRAM_DBG_SEL_UMSK (~(((1U << PSRAM_UHS_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_SEL_POS))
+
+/* 0xF0 : UHS_dummy_reg */
+#define PSRAM_UHS_UHS_DUMMY_REG_OFFSET (0xF0)
+#define PSRAM_UHS_REG_PSRAM_DUMMY_REG PSRAM_UHS_REG_PSRAM_DUMMY_REG
+#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_POS (0U)
+#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_LEN (32U)
+#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_MSK (((1U << PSRAM_UHS_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DUMMY_REG_POS)
+#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_UMSK (~(((1U << PSRAM_UHS_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DUMMY_REG_POS))
+
+/* 0x100 : phy_cfg_00 */
+#define PSRAM_UHS_PHY_CFG_00_OFFSET (0x100)
+#define PSRAM_UHS_DQS_RDY PSRAM_UHS_DQS_RDY
+#define PSRAM_UHS_DQS_RDY_POS (0U)
+#define PSRAM_UHS_DQS_RDY_LEN (1U)
+#define PSRAM_UHS_DQS_RDY_MSK (((1U << PSRAM_UHS_DQS_RDY_LEN) - 1) << PSRAM_UHS_DQS_RDY_POS)
+#define PSRAM_UHS_DQS_RDY_UMSK (~(((1U << PSRAM_UHS_DQS_RDY_LEN) - 1) << PSRAM_UHS_DQS_RDY_POS))
+#define PSRAM_UHS_CK_SR PSRAM_UHS_CK_SR
+#define PSRAM_UHS_CK_SR_POS (8U)
+#define PSRAM_UHS_CK_SR_LEN (2U)
+#define PSRAM_UHS_CK_SR_MSK (((1U << PSRAM_UHS_CK_SR_LEN) - 1) << PSRAM_UHS_CK_SR_POS)
+#define PSRAM_UHS_CK_SR_UMSK (~(((1U << PSRAM_UHS_CK_SR_LEN) - 1) << PSRAM_UHS_CK_SR_POS))
+#define PSRAM_UHS_CLK0_POLARITY PSRAM_UHS_CLK0_POLARITY
+#define PSRAM_UHS_CLK0_POLARITY_POS (15U)
+#define PSRAM_UHS_CLK0_POLARITY_LEN (1U)
+#define PSRAM_UHS_CLK0_POLARITY_MSK (((1U << PSRAM_UHS_CLK0_POLARITY_LEN) - 1) << PSRAM_UHS_CLK0_POLARITY_POS)
+#define PSRAM_UHS_CLK0_POLARITY_UMSK (~(((1U << PSRAM_UHS_CLK0_POLARITY_LEN) - 1) << PSRAM_UHS_CLK0_POLARITY_POS))
+#define PSRAM_UHS_CK_DLY_DRV PSRAM_UHS_CK_DLY_DRV
+#define PSRAM_UHS_CK_DLY_DRV_POS (16U)
+#define PSRAM_UHS_CK_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_CK_DLY_DRV_MSK (((1U << PSRAM_UHS_CK_DLY_DRV_LEN) - 1) << PSRAM_UHS_CK_DLY_DRV_POS)
+#define PSRAM_UHS_CK_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_CK_DLY_DRV_LEN) - 1) << PSRAM_UHS_CK_DLY_DRV_POS))
+#define PSRAM_UHS_CEN_SR PSRAM_UHS_CEN_SR
+#define PSRAM_UHS_CEN_SR_POS (20U)
+#define PSRAM_UHS_CEN_SR_LEN (2U)
+#define PSRAM_UHS_CEN_SR_MSK (((1U << PSRAM_UHS_CEN_SR_LEN) - 1) << PSRAM_UHS_CEN_SR_POS)
+#define PSRAM_UHS_CEN_SR_UMSK (~(((1U << PSRAM_UHS_CEN_SR_LEN) - 1) << PSRAM_UHS_CEN_SR_POS))
+#define PSRAM_UHS_CEN_DLY_DRV PSRAM_UHS_CEN_DLY_DRV
+#define PSRAM_UHS_CEN_DLY_DRV_POS (28U)
+#define PSRAM_UHS_CEN_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_CEN_DLY_DRV_MSK (((1U << PSRAM_UHS_CEN_DLY_DRV_LEN) - 1) << PSRAM_UHS_CEN_DLY_DRV_POS)
+#define PSRAM_UHS_CEN_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_CEN_DLY_DRV_LEN) - 1) << PSRAM_UHS_CEN_DLY_DRV_POS))
+
+/* 0x104 : phy_cfg_04 */
+#define PSRAM_UHS_PHY_CFG_04_OFFSET (0x104)
+#define PSRAM_UHS_DM1_SR PSRAM_UHS_DM1_SR
+#define PSRAM_UHS_DM1_SR_POS (4U)
+#define PSRAM_UHS_DM1_SR_LEN (2U)
+#define PSRAM_UHS_DM1_SR_MSK (((1U << PSRAM_UHS_DM1_SR_LEN) - 1) << PSRAM_UHS_DM1_SR_POS)
+#define PSRAM_UHS_DM1_SR_UMSK (~(((1U << PSRAM_UHS_DM1_SR_LEN) - 1) << PSRAM_UHS_DM1_SR_POS))
+#define PSRAM_UHS_DM1_DLY_DRV PSRAM_UHS_DM1_DLY_DRV
+#define PSRAM_UHS_DM1_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DM1_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DM1_DLY_DRV_MSK (((1U << PSRAM_UHS_DM1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM1_DLY_DRV_POS)
+#define PSRAM_UHS_DM1_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DM1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM1_DLY_DRV_POS))
+#define PSRAM_UHS_DM0_SR PSRAM_UHS_DM0_SR
+#define PSRAM_UHS_DM0_SR_POS (20U)
+#define PSRAM_UHS_DM0_SR_LEN (2U)
+#define PSRAM_UHS_DM0_SR_MSK (((1U << PSRAM_UHS_DM0_SR_LEN) - 1) << PSRAM_UHS_DM0_SR_POS)
+#define PSRAM_UHS_DM0_SR_UMSK (~(((1U << PSRAM_UHS_DM0_SR_LEN) - 1) << PSRAM_UHS_DM0_SR_POS))
+#define PSRAM_UHS_DM0_DLY_DRV PSRAM_UHS_DM0_DLY_DRV
+#define PSRAM_UHS_DM0_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DM0_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DM0_DLY_DRV_MSK (((1U << PSRAM_UHS_DM0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM0_DLY_DRV_POS)
+#define PSRAM_UHS_DM0_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DM0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM0_DLY_DRV_POS))
+
+/* 0x108 : phy_cfg_08 */
+#define PSRAM_UHS_PHY_CFG_08_OFFSET (0x108)
+#define PSRAM_UHS_DQ1_SR PSRAM_UHS_DQ1_SR
+#define PSRAM_UHS_DQ1_SR_POS (0U)
+#define PSRAM_UHS_DQ1_SR_LEN (2U)
+#define PSRAM_UHS_DQ1_SR_MSK (((1U << PSRAM_UHS_DQ1_SR_LEN) - 1) << PSRAM_UHS_DQ1_SR_POS)
+#define PSRAM_UHS_DQ1_SR_UMSK (~(((1U << PSRAM_UHS_DQ1_SR_LEN) - 1) << PSRAM_UHS_DQ1_SR_POS))
+#define PSRAM_UHS_DQ1_DLY_RX PSRAM_UHS_DQ1_DLY_RX
+#define PSRAM_UHS_DQ1_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ1_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ1_DLY_RX_MSK (((1U << PSRAM_UHS_DQ1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ1_DLY_RX_POS)
+#define PSRAM_UHS_DQ1_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ1_DLY_RX_POS))
+#define PSRAM_UHS_DQ1_DLY_DRV PSRAM_UHS_DQ1_DLY_DRV
+#define PSRAM_UHS_DQ1_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ1_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ1_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ1_DLY_DRV_POS)
+#define PSRAM_UHS_DQ1_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ1_DLY_DRV_POS))
+#define PSRAM_UHS_DQ0_SR PSRAM_UHS_DQ0_SR
+#define PSRAM_UHS_DQ0_SR_POS (16U)
+#define PSRAM_UHS_DQ0_SR_LEN (2U)
+#define PSRAM_UHS_DQ0_SR_MSK (((1U << PSRAM_UHS_DQ0_SR_LEN) - 1) << PSRAM_UHS_DQ0_SR_POS)
+#define PSRAM_UHS_DQ0_SR_UMSK (~(((1U << PSRAM_UHS_DQ0_SR_LEN) - 1) << PSRAM_UHS_DQ0_SR_POS))
+#define PSRAM_UHS_DQ0_DLY_RX PSRAM_UHS_DQ0_DLY_RX
+#define PSRAM_UHS_DQ0_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ0_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ0_DLY_RX_MSK (((1U << PSRAM_UHS_DQ0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ0_DLY_RX_POS)
+#define PSRAM_UHS_DQ0_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ0_DLY_RX_POS))
+#define PSRAM_UHS_DQ0_DLY_DRV PSRAM_UHS_DQ0_DLY_DRV
+#define PSRAM_UHS_DQ0_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ0_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ0_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ0_DLY_DRV_POS)
+#define PSRAM_UHS_DQ0_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ0_DLY_DRV_POS))
+
+/* 0x10C : phy_cfg_0C */
+#define PSRAM_UHS_PHY_CFG_0C_OFFSET (0x10C)
+#define PSRAM_UHS_DQ3_SR PSRAM_UHS_DQ3_SR
+#define PSRAM_UHS_DQ3_SR_POS (0U)
+#define PSRAM_UHS_DQ3_SR_LEN (2U)
+#define PSRAM_UHS_DQ3_SR_MSK (((1U << PSRAM_UHS_DQ3_SR_LEN) - 1) << PSRAM_UHS_DQ3_SR_POS)
+#define PSRAM_UHS_DQ3_SR_UMSK (~(((1U << PSRAM_UHS_DQ3_SR_LEN) - 1) << PSRAM_UHS_DQ3_SR_POS))
+#define PSRAM_UHS_DQ3_DLY_RX PSRAM_UHS_DQ3_DLY_RX
+#define PSRAM_UHS_DQ3_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ3_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ3_DLY_RX_MSK (((1U << PSRAM_UHS_DQ3_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ3_DLY_RX_POS)
+#define PSRAM_UHS_DQ3_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ3_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ3_DLY_RX_POS))
+#define PSRAM_UHS_DQ3_DLY_DRV PSRAM_UHS_DQ3_DLY_DRV
+#define PSRAM_UHS_DQ3_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ3_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ3_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ3_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ3_DLY_DRV_POS)
+#define PSRAM_UHS_DQ3_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ3_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ3_DLY_DRV_POS))
+#define PSRAM_UHS_DQ2_SR PSRAM_UHS_DQ2_SR
+#define PSRAM_UHS_DQ2_SR_POS (16U)
+#define PSRAM_UHS_DQ2_SR_LEN (2U)
+#define PSRAM_UHS_DQ2_SR_MSK (((1U << PSRAM_UHS_DQ2_SR_LEN) - 1) << PSRAM_UHS_DQ2_SR_POS)
+#define PSRAM_UHS_DQ2_SR_UMSK (~(((1U << PSRAM_UHS_DQ2_SR_LEN) - 1) << PSRAM_UHS_DQ2_SR_POS))
+#define PSRAM_UHS_DQ2_DLY_RX PSRAM_UHS_DQ2_DLY_RX
+#define PSRAM_UHS_DQ2_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ2_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ2_DLY_RX_MSK (((1U << PSRAM_UHS_DQ2_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ2_DLY_RX_POS)
+#define PSRAM_UHS_DQ2_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ2_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ2_DLY_RX_POS))
+#define PSRAM_UHS_DQ2_DLY_DRV PSRAM_UHS_DQ2_DLY_DRV
+#define PSRAM_UHS_DQ2_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ2_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ2_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ2_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ2_DLY_DRV_POS)
+#define PSRAM_UHS_DQ2_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ2_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ2_DLY_DRV_POS))
+
+/* 0x110 : phy_cfg_10 */
+#define PSRAM_UHS_PHY_CFG_10_OFFSET (0x110)
+#define PSRAM_UHS_DQ5_SR PSRAM_UHS_DQ5_SR
+#define PSRAM_UHS_DQ5_SR_POS (0U)
+#define PSRAM_UHS_DQ5_SR_LEN (2U)
+#define PSRAM_UHS_DQ5_SR_MSK (((1U << PSRAM_UHS_DQ5_SR_LEN) - 1) << PSRAM_UHS_DQ5_SR_POS)
+#define PSRAM_UHS_DQ5_SR_UMSK (~(((1U << PSRAM_UHS_DQ5_SR_LEN) - 1) << PSRAM_UHS_DQ5_SR_POS))
+#define PSRAM_UHS_DQ5_DLY_RX PSRAM_UHS_DQ5_DLY_RX
+#define PSRAM_UHS_DQ5_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ5_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ5_DLY_RX_MSK (((1U << PSRAM_UHS_DQ5_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ5_DLY_RX_POS)
+#define PSRAM_UHS_DQ5_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ5_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ5_DLY_RX_POS))
+#define PSRAM_UHS_DQ5_DLY_DRV PSRAM_UHS_DQ5_DLY_DRV
+#define PSRAM_UHS_DQ5_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ5_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ5_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ5_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ5_DLY_DRV_POS)
+#define PSRAM_UHS_DQ5_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ5_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ5_DLY_DRV_POS))
+#define PSRAM_UHS_DQ4_SR PSRAM_UHS_DQ4_SR
+#define PSRAM_UHS_DQ4_SR_POS (16U)
+#define PSRAM_UHS_DQ4_SR_LEN (2U)
+#define PSRAM_UHS_DQ4_SR_MSK (((1U << PSRAM_UHS_DQ4_SR_LEN) - 1) << PSRAM_UHS_DQ4_SR_POS)
+#define PSRAM_UHS_DQ4_SR_UMSK (~(((1U << PSRAM_UHS_DQ4_SR_LEN) - 1) << PSRAM_UHS_DQ4_SR_POS))
+#define PSRAM_UHS_DQ4_DLY_RX PSRAM_UHS_DQ4_DLY_RX
+#define PSRAM_UHS_DQ4_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ4_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ4_DLY_RX_MSK (((1U << PSRAM_UHS_DQ4_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ4_DLY_RX_POS)
+#define PSRAM_UHS_DQ4_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ4_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ4_DLY_RX_POS))
+#define PSRAM_UHS_DQ4_DLY_DRV PSRAM_UHS_DQ4_DLY_DRV
+#define PSRAM_UHS_DQ4_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ4_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ4_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ4_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ4_DLY_DRV_POS)
+#define PSRAM_UHS_DQ4_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ4_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ4_DLY_DRV_POS))
+
+/* 0x114 : phy_cfg_14 */
+#define PSRAM_UHS_PHY_CFG_14_OFFSET (0x114)
+#define PSRAM_UHS_DQ7_SR PSRAM_UHS_DQ7_SR
+#define PSRAM_UHS_DQ7_SR_POS (0U)
+#define PSRAM_UHS_DQ7_SR_LEN (2U)
+#define PSRAM_UHS_DQ7_SR_MSK (((1U << PSRAM_UHS_DQ7_SR_LEN) - 1) << PSRAM_UHS_DQ7_SR_POS)
+#define PSRAM_UHS_DQ7_SR_UMSK (~(((1U << PSRAM_UHS_DQ7_SR_LEN) - 1) << PSRAM_UHS_DQ7_SR_POS))
+#define PSRAM_UHS_DQ7_DLY_RX PSRAM_UHS_DQ7_DLY_RX
+#define PSRAM_UHS_DQ7_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ7_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ7_DLY_RX_MSK (((1U << PSRAM_UHS_DQ7_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ7_DLY_RX_POS)
+#define PSRAM_UHS_DQ7_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ7_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ7_DLY_RX_POS))
+#define PSRAM_UHS_DQ7_DLY_DRV PSRAM_UHS_DQ7_DLY_DRV
+#define PSRAM_UHS_DQ7_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ7_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ7_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ7_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ7_DLY_DRV_POS)
+#define PSRAM_UHS_DQ7_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ7_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ7_DLY_DRV_POS))
+#define PSRAM_UHS_DQ6_SR PSRAM_UHS_DQ6_SR
+#define PSRAM_UHS_DQ6_SR_POS (16U)
+#define PSRAM_UHS_DQ6_SR_LEN (2U)
+#define PSRAM_UHS_DQ6_SR_MSK (((1U << PSRAM_UHS_DQ6_SR_LEN) - 1) << PSRAM_UHS_DQ6_SR_POS)
+#define PSRAM_UHS_DQ6_SR_UMSK (~(((1U << PSRAM_UHS_DQ6_SR_LEN) - 1) << PSRAM_UHS_DQ6_SR_POS))
+#define PSRAM_UHS_DQ6_DLY_RX PSRAM_UHS_DQ6_DLY_RX
+#define PSRAM_UHS_DQ6_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ6_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ6_DLY_RX_MSK (((1U << PSRAM_UHS_DQ6_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ6_DLY_RX_POS)
+#define PSRAM_UHS_DQ6_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ6_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ6_DLY_RX_POS))
+#define PSRAM_UHS_DQ6_DLY_DRV PSRAM_UHS_DQ6_DLY_DRV
+#define PSRAM_UHS_DQ6_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ6_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ6_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ6_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ6_DLY_DRV_POS)
+#define PSRAM_UHS_DQ6_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ6_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ6_DLY_DRV_POS))
+
+/* 0x118 : phy_cfg_18 */
+#define PSRAM_UHS_PHY_CFG_18_OFFSET (0x118)
+#define PSRAM_UHS_DQ9_SR PSRAM_UHS_DQ9_SR
+#define PSRAM_UHS_DQ9_SR_POS (0U)
+#define PSRAM_UHS_DQ9_SR_LEN (2U)
+#define PSRAM_UHS_DQ9_SR_MSK (((1U << PSRAM_UHS_DQ9_SR_LEN) - 1) << PSRAM_UHS_DQ9_SR_POS)
+#define PSRAM_UHS_DQ9_SR_UMSK (~(((1U << PSRAM_UHS_DQ9_SR_LEN) - 1) << PSRAM_UHS_DQ9_SR_POS))
+#define PSRAM_UHS_DQ9_DLY_RX PSRAM_UHS_DQ9_DLY_RX
+#define PSRAM_UHS_DQ9_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ9_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ9_DLY_RX_MSK (((1U << PSRAM_UHS_DQ9_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ9_DLY_RX_POS)
+#define PSRAM_UHS_DQ9_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ9_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ9_DLY_RX_POS))
+#define PSRAM_UHS_DQ9_DLY_DRV PSRAM_UHS_DQ9_DLY_DRV
+#define PSRAM_UHS_DQ9_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ9_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ9_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ9_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ9_DLY_DRV_POS)
+#define PSRAM_UHS_DQ9_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ9_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ9_DLY_DRV_POS))
+#define PSRAM_UHS_DQ8_SR PSRAM_UHS_DQ8_SR
+#define PSRAM_UHS_DQ8_SR_POS (16U)
+#define PSRAM_UHS_DQ8_SR_LEN (2U)
+#define PSRAM_UHS_DQ8_SR_MSK (((1U << PSRAM_UHS_DQ8_SR_LEN) - 1) << PSRAM_UHS_DQ8_SR_POS)
+#define PSRAM_UHS_DQ8_SR_UMSK (~(((1U << PSRAM_UHS_DQ8_SR_LEN) - 1) << PSRAM_UHS_DQ8_SR_POS))
+#define PSRAM_UHS_DQ8_DLY_RX PSRAM_UHS_DQ8_DLY_RX
+#define PSRAM_UHS_DQ8_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ8_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ8_DLY_RX_MSK (((1U << PSRAM_UHS_DQ8_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ8_DLY_RX_POS)
+#define PSRAM_UHS_DQ8_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ8_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ8_DLY_RX_POS))
+#define PSRAM_UHS_DQ8_DLY_DRV PSRAM_UHS_DQ8_DLY_DRV
+#define PSRAM_UHS_DQ8_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ8_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ8_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ8_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ8_DLY_DRV_POS)
+#define PSRAM_UHS_DQ8_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ8_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ8_DLY_DRV_POS))
+
+/* 0x11C : phy_cfg_1C */
+#define PSRAM_UHS_PHY_CFG_1C_OFFSET (0x11C)
+#define PSRAM_UHS_DQ11_SR PSRAM_UHS_DQ11_SR
+#define PSRAM_UHS_DQ11_SR_POS (0U)
+#define PSRAM_UHS_DQ11_SR_LEN (2U)
+#define PSRAM_UHS_DQ11_SR_MSK (((1U << PSRAM_UHS_DQ11_SR_LEN) - 1) << PSRAM_UHS_DQ11_SR_POS)
+#define PSRAM_UHS_DQ11_SR_UMSK (~(((1U << PSRAM_UHS_DQ11_SR_LEN) - 1) << PSRAM_UHS_DQ11_SR_POS))
+#define PSRAM_UHS_DQ11_DLY_RX PSRAM_UHS_DQ11_DLY_RX
+#define PSRAM_UHS_DQ11_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ11_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ11_DLY_RX_MSK (((1U << PSRAM_UHS_DQ11_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ11_DLY_RX_POS)
+#define PSRAM_UHS_DQ11_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ11_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ11_DLY_RX_POS))
+#define PSRAM_UHS_DQ11_DLY_DRV PSRAM_UHS_DQ11_DLY_DRV
+#define PSRAM_UHS_DQ11_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ11_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ11_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ11_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ11_DLY_DRV_POS)
+#define PSRAM_UHS_DQ11_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ11_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ11_DLY_DRV_POS))
+#define PSRAM_UHS_DQ10_SR PSRAM_UHS_DQ10_SR
+#define PSRAM_UHS_DQ10_SR_POS (16U)
+#define PSRAM_UHS_DQ10_SR_LEN (2U)
+#define PSRAM_UHS_DQ10_SR_MSK (((1U << PSRAM_UHS_DQ10_SR_LEN) - 1) << PSRAM_UHS_DQ10_SR_POS)
+#define PSRAM_UHS_DQ10_SR_UMSK (~(((1U << PSRAM_UHS_DQ10_SR_LEN) - 1) << PSRAM_UHS_DQ10_SR_POS))
+#define PSRAM_UHS_DQ10_DLY_RX PSRAM_UHS_DQ10_DLY_RX
+#define PSRAM_UHS_DQ10_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ10_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ10_DLY_RX_MSK (((1U << PSRAM_UHS_DQ10_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ10_DLY_RX_POS)
+#define PSRAM_UHS_DQ10_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ10_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ10_DLY_RX_POS))
+#define PSRAM_UHS_DQ10_DLY_DRV PSRAM_UHS_DQ10_DLY_DRV
+#define PSRAM_UHS_DQ10_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ10_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ10_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ10_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ10_DLY_DRV_POS)
+#define PSRAM_UHS_DQ10_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ10_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ10_DLY_DRV_POS))
+
+/* 0x120 : phy_cfg_20 */
+#define PSRAM_UHS_PHY_CFG_20_OFFSET (0x120)
+#define PSRAM_UHS_DQ13_SR PSRAM_UHS_DQ13_SR
+#define PSRAM_UHS_DQ13_SR_POS (0U)
+#define PSRAM_UHS_DQ13_SR_LEN (2U)
+#define PSRAM_UHS_DQ13_SR_MSK (((1U << PSRAM_UHS_DQ13_SR_LEN) - 1) << PSRAM_UHS_DQ13_SR_POS)
+#define PSRAM_UHS_DQ13_SR_UMSK (~(((1U << PSRAM_UHS_DQ13_SR_LEN) - 1) << PSRAM_UHS_DQ13_SR_POS))
+#define PSRAM_UHS_DQ13_DLY_RX PSRAM_UHS_DQ13_DLY_RX
+#define PSRAM_UHS_DQ13_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ13_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ13_DLY_RX_MSK (((1U << PSRAM_UHS_DQ13_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ13_DLY_RX_POS)
+#define PSRAM_UHS_DQ13_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ13_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ13_DLY_RX_POS))
+#define PSRAM_UHS_DQ13_DLY_DRV PSRAM_UHS_DQ13_DLY_DRV
+#define PSRAM_UHS_DQ13_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ13_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ13_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ13_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ13_DLY_DRV_POS)
+#define PSRAM_UHS_DQ13_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ13_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ13_DLY_DRV_POS))
+#define PSRAM_UHS_DQ12_SR PSRAM_UHS_DQ12_SR
+#define PSRAM_UHS_DQ12_SR_POS (16U)
+#define PSRAM_UHS_DQ12_SR_LEN (2U)
+#define PSRAM_UHS_DQ12_SR_MSK (((1U << PSRAM_UHS_DQ12_SR_LEN) - 1) << PSRAM_UHS_DQ12_SR_POS)
+#define PSRAM_UHS_DQ12_SR_UMSK (~(((1U << PSRAM_UHS_DQ12_SR_LEN) - 1) << PSRAM_UHS_DQ12_SR_POS))
+#define PSRAM_UHS_DQ12_DLY_RX PSRAM_UHS_DQ12_DLY_RX
+#define PSRAM_UHS_DQ12_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ12_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ12_DLY_RX_MSK (((1U << PSRAM_UHS_DQ12_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ12_DLY_RX_POS)
+#define PSRAM_UHS_DQ12_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ12_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ12_DLY_RX_POS))
+#define PSRAM_UHS_DQ12_DLY_DRV PSRAM_UHS_DQ12_DLY_DRV
+#define PSRAM_UHS_DQ12_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ12_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ12_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ12_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ12_DLY_DRV_POS)
+#define PSRAM_UHS_DQ12_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ12_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ12_DLY_DRV_POS))
+
+/* 0x124 : phy_cfg_24 */
+#define PSRAM_UHS_PHY_CFG_24_OFFSET (0x124)
+#define PSRAM_UHS_DQ15_SR PSRAM_UHS_DQ15_SR
+#define PSRAM_UHS_DQ15_SR_POS (0U)
+#define PSRAM_UHS_DQ15_SR_LEN (2U)
+#define PSRAM_UHS_DQ15_SR_MSK (((1U << PSRAM_UHS_DQ15_SR_LEN) - 1) << PSRAM_UHS_DQ15_SR_POS)
+#define PSRAM_UHS_DQ15_SR_UMSK (~(((1U << PSRAM_UHS_DQ15_SR_LEN) - 1) << PSRAM_UHS_DQ15_SR_POS))
+#define PSRAM_UHS_DQ15_DLY_RX PSRAM_UHS_DQ15_DLY_RX
+#define PSRAM_UHS_DQ15_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQ15_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ15_DLY_RX_MSK (((1U << PSRAM_UHS_DQ15_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ15_DLY_RX_POS)
+#define PSRAM_UHS_DQ15_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ15_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ15_DLY_RX_POS))
+#define PSRAM_UHS_DQ15_DLY_DRV PSRAM_UHS_DQ15_DLY_DRV
+#define PSRAM_UHS_DQ15_DLY_DRV_POS (12U)
+#define PSRAM_UHS_DQ15_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ15_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ15_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ15_DLY_DRV_POS)
+#define PSRAM_UHS_DQ15_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ15_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ15_DLY_DRV_POS))
+#define PSRAM_UHS_DQ14_SR PSRAM_UHS_DQ14_SR
+#define PSRAM_UHS_DQ14_SR_POS (16U)
+#define PSRAM_UHS_DQ14_SR_LEN (2U)
+#define PSRAM_UHS_DQ14_SR_MSK (((1U << PSRAM_UHS_DQ14_SR_LEN) - 1) << PSRAM_UHS_DQ14_SR_POS)
+#define PSRAM_UHS_DQ14_SR_UMSK (~(((1U << PSRAM_UHS_DQ14_SR_LEN) - 1) << PSRAM_UHS_DQ14_SR_POS))
+#define PSRAM_UHS_DQ14_DLY_RX PSRAM_UHS_DQ14_DLY_RX
+#define PSRAM_UHS_DQ14_DLY_RX_POS (24U)
+#define PSRAM_UHS_DQ14_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQ14_DLY_RX_MSK (((1U << PSRAM_UHS_DQ14_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ14_DLY_RX_POS)
+#define PSRAM_UHS_DQ14_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQ14_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ14_DLY_RX_POS))
+#define PSRAM_UHS_DQ14_DLY_DRV PSRAM_UHS_DQ14_DLY_DRV
+#define PSRAM_UHS_DQ14_DLY_DRV_POS (28U)
+#define PSRAM_UHS_DQ14_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQ14_DLY_DRV_MSK (((1U << PSRAM_UHS_DQ14_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ14_DLY_DRV_POS)
+#define PSRAM_UHS_DQ14_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ14_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ14_DLY_DRV_POS))
+
+/* 0x128 : phy_cfg_28 */
+#define PSRAM_UHS_PHY_CFG_28_OFFSET (0x128)
+#define PSRAM_UHS_DQS0N_DLY_RX PSRAM_UHS_DQS0N_DLY_RX
+#define PSRAM_UHS_DQS0N_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQS0N_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQS0N_DLY_RX_MSK (((1U << PSRAM_UHS_DQS0N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0N_DLY_RX_POS)
+#define PSRAM_UHS_DQS0N_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS0N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0N_DLY_RX_POS))
+#define PSRAM_UHS_DQS0_SR PSRAM_UHS_DQS0_SR
+#define PSRAM_UHS_DQS0_SR_POS (12U)
+#define PSRAM_UHS_DQS0_SR_LEN (2U)
+#define PSRAM_UHS_DQS0_SR_MSK (((1U << PSRAM_UHS_DQS0_SR_LEN) - 1) << PSRAM_UHS_DQS0_SR_POS)
+#define PSRAM_UHS_DQS0_SR_UMSK (~(((1U << PSRAM_UHS_DQS0_SR_LEN) - 1) << PSRAM_UHS_DQS0_SR_POS))
+#define PSRAM_UHS_DQS0_SEL PSRAM_UHS_DQS0_SEL
+#define PSRAM_UHS_DQS0_SEL_POS (14U)
+#define PSRAM_UHS_DQS0_SEL_LEN (2U)
+#define PSRAM_UHS_DQS0_SEL_MSK (((1U << PSRAM_UHS_DQS0_SEL_LEN) - 1) << PSRAM_UHS_DQS0_SEL_POS)
+#define PSRAM_UHS_DQS0_SEL_UMSK (~(((1U << PSRAM_UHS_DQS0_SEL_LEN) - 1) << PSRAM_UHS_DQS0_SEL_POS))
+#define PSRAM_UHS_DQS0_DLY_RX PSRAM_UHS_DQS0_DLY_RX
+#define PSRAM_UHS_DQS0_DLY_RX_POS (20U)
+#define PSRAM_UHS_DQS0_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQS0_DLY_RX_MSK (((1U << PSRAM_UHS_DQS0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DLY_RX_POS)
+#define PSRAM_UHS_DQS0_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DLY_RX_POS))
+#define PSRAM_UHS_DQS0_DLY_DRV PSRAM_UHS_DQS0_DLY_DRV
+#define PSRAM_UHS_DQS0_DLY_DRV_POS (24U)
+#define PSRAM_UHS_DQS0_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQS0_DLY_DRV_MSK (((1U << PSRAM_UHS_DQS0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS0_DLY_DRV_POS)
+#define PSRAM_UHS_DQS0_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQS0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS0_DLY_DRV_POS))
+#define PSRAM_UHS_DQS0_DIFF_DLY_RX PSRAM_UHS_DQS0_DIFF_DLY_RX
+#define PSRAM_UHS_DQS0_DIFF_DLY_RX_POS (28U)
+#define PSRAM_UHS_DQS0_DIFF_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQS0_DIFF_DLY_RX_MSK (((1U << PSRAM_UHS_DQS0_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DIFF_DLY_RX_POS)
+#define PSRAM_UHS_DQS0_DIFF_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS0_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DIFF_DLY_RX_POS))
+
+/* 0x12C : phy_cfg_2C */
+#define PSRAM_UHS_PHY_CFG_2C_OFFSET (0x12C)
+#define PSRAM_UHS_IPP5UN_LPDDR PSRAM_UHS_IPP5UN_LPDDR
+#define PSRAM_UHS_IPP5UN_LPDDR_POS (0U)
+#define PSRAM_UHS_IPP5UN_LPDDR_LEN (1U)
+#define PSRAM_UHS_IPP5UN_LPDDR_MSK (((1U << PSRAM_UHS_IPP5UN_LPDDR_LEN) - 1) << PSRAM_UHS_IPP5UN_LPDDR_POS)
+#define PSRAM_UHS_IPP5UN_LPDDR_UMSK (~(((1U << PSRAM_UHS_IPP5UN_LPDDR_LEN) - 1) << PSRAM_UHS_IPP5UN_LPDDR_POS))
+#define PSRAM_UHS_EN_RX_FE PSRAM_UHS_EN_RX_FE
+#define PSRAM_UHS_EN_RX_FE_POS (1U)
+#define PSRAM_UHS_EN_RX_FE_LEN (1U)
+#define PSRAM_UHS_EN_RX_FE_MSK (((1U << PSRAM_UHS_EN_RX_FE_LEN) - 1) << PSRAM_UHS_EN_RX_FE_POS)
+#define PSRAM_UHS_EN_RX_FE_UMSK (~(((1U << PSRAM_UHS_EN_RX_FE_LEN) - 1) << PSRAM_UHS_EN_RX_FE_POS))
+#define PSRAM_UHS_EN_BIAS PSRAM_UHS_EN_BIAS
+#define PSRAM_UHS_EN_BIAS_POS (2U)
+#define PSRAM_UHS_EN_BIAS_LEN (1U)
+#define PSRAM_UHS_EN_BIAS_MSK (((1U << PSRAM_UHS_EN_BIAS_LEN) - 1) << PSRAM_UHS_EN_BIAS_POS)
+#define PSRAM_UHS_EN_BIAS_UMSK (~(((1U << PSRAM_UHS_EN_BIAS_LEN) - 1) << PSRAM_UHS_EN_BIAS_POS))
+#define PSRAM_UHS_DQS1N_DLY_RX PSRAM_UHS_DQS1N_DLY_RX
+#define PSRAM_UHS_DQS1N_DLY_RX_POS (8U)
+#define PSRAM_UHS_DQS1N_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQS1N_DLY_RX_MSK (((1U << PSRAM_UHS_DQS1N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1N_DLY_RX_POS)
+#define PSRAM_UHS_DQS1N_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS1N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1N_DLY_RX_POS))
+#define PSRAM_UHS_DQS1_SR PSRAM_UHS_DQS1_SR
+#define PSRAM_UHS_DQS1_SR_POS (12U)
+#define PSRAM_UHS_DQS1_SR_LEN (2U)
+#define PSRAM_UHS_DQS1_SR_MSK (((1U << PSRAM_UHS_DQS1_SR_LEN) - 1) << PSRAM_UHS_DQS1_SR_POS)
+#define PSRAM_UHS_DQS1_SR_UMSK (~(((1U << PSRAM_UHS_DQS1_SR_LEN) - 1) << PSRAM_UHS_DQS1_SR_POS))
+#define PSRAM_UHS_DQS1_SEL PSRAM_UHS_DQS1_SEL
+#define PSRAM_UHS_DQS1_SEL_POS (14U)
+#define PSRAM_UHS_DQS1_SEL_LEN (2U)
+#define PSRAM_UHS_DQS1_SEL_MSK (((1U << PSRAM_UHS_DQS1_SEL_LEN) - 1) << PSRAM_UHS_DQS1_SEL_POS)
+#define PSRAM_UHS_DQS1_SEL_UMSK (~(((1U << PSRAM_UHS_DQS1_SEL_LEN) - 1) << PSRAM_UHS_DQS1_SEL_POS))
+#define PSRAM_UHS_DQS1_DLY_RX PSRAM_UHS_DQS1_DLY_RX
+#define PSRAM_UHS_DQS1_DLY_RX_POS (20U)
+#define PSRAM_UHS_DQS1_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQS1_DLY_RX_MSK (((1U << PSRAM_UHS_DQS1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DLY_RX_POS)
+#define PSRAM_UHS_DQS1_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DLY_RX_POS))
+#define PSRAM_UHS_DQS1_DLY_DRV PSRAM_UHS_DQS1_DLY_DRV
+#define PSRAM_UHS_DQS1_DLY_DRV_POS (24U)
+#define PSRAM_UHS_DQS1_DLY_DRV_LEN (4U)
+#define PSRAM_UHS_DQS1_DLY_DRV_MSK (((1U << PSRAM_UHS_DQS1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS1_DLY_DRV_POS)
+#define PSRAM_UHS_DQS1_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQS1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS1_DLY_DRV_POS))
+#define PSRAM_UHS_DQS1_DIFF_DLY_RX PSRAM_UHS_DQS1_DIFF_DLY_RX
+#define PSRAM_UHS_DQS1_DIFF_DLY_RX_POS (28U)
+#define PSRAM_UHS_DQS1_DIFF_DLY_RX_LEN (4U)
+#define PSRAM_UHS_DQS1_DIFF_DLY_RX_MSK (((1U << PSRAM_UHS_DQS1_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DIFF_DLY_RX_POS)
+#define PSRAM_UHS_DQS1_DIFF_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS1_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DIFF_DLY_RX_POS))
+
+/* 0x130 : phy_cfg_30 */
+#define PSRAM_UHS_PHY_CFG_30_OFFSET (0x130)
+#define PSRAM_UHS_PHY_WL_DQ_DIG PSRAM_UHS_PHY_WL_DQ_DIG
+#define PSRAM_UHS_PHY_WL_DQ_DIG_POS (0U)
+#define PSRAM_UHS_PHY_WL_DQ_DIG_LEN (3U)
+#define PSRAM_UHS_PHY_WL_DQ_DIG_MSK (((1U << PSRAM_UHS_PHY_WL_DQ_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_DIG_POS)
+#define PSRAM_UHS_PHY_WL_DQ_DIG_UMSK (~(((1U << PSRAM_UHS_PHY_WL_DQ_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_DIG_POS))
+#define PSRAM_UHS_PHY_WL_DQ_ANA PSRAM_UHS_PHY_WL_DQ_ANA
+#define PSRAM_UHS_PHY_WL_DQ_ANA_POS (4U)
+#define PSRAM_UHS_PHY_WL_DQ_ANA_LEN (3U)
+#define PSRAM_UHS_PHY_WL_DQ_ANA_MSK (((1U << PSRAM_UHS_PHY_WL_DQ_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_ANA_POS)
+#define PSRAM_UHS_PHY_WL_DQ_ANA_UMSK (~(((1U << PSRAM_UHS_PHY_WL_DQ_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_ANA_POS))
+#define PSRAM_UHS_PHY_WL_DIG PSRAM_UHS_PHY_WL_DIG
+#define PSRAM_UHS_PHY_WL_DIG_POS (8U)
+#define PSRAM_UHS_PHY_WL_DIG_LEN (3U)
+#define PSRAM_UHS_PHY_WL_DIG_MSK (((1U << PSRAM_UHS_PHY_WL_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DIG_POS)
+#define PSRAM_UHS_PHY_WL_DIG_UMSK (~(((1U << PSRAM_UHS_PHY_WL_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DIG_POS))
+#define PSRAM_UHS_PHY_WL_ANA PSRAM_UHS_PHY_WL_ANA
+#define PSRAM_UHS_PHY_WL_ANA_POS (12U)
+#define PSRAM_UHS_PHY_WL_ANA_LEN (3U)
+#define PSRAM_UHS_PHY_WL_ANA_MSK (((1U << PSRAM_UHS_PHY_WL_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_ANA_POS)
+#define PSRAM_UHS_PHY_WL_ANA_UMSK (~(((1U << PSRAM_UHS_PHY_WL_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_ANA_POS))
+#define PSRAM_UHS_PHY_RL_DIG PSRAM_UHS_PHY_RL_DIG
+#define PSRAM_UHS_PHY_RL_DIG_POS (16U)
+#define PSRAM_UHS_PHY_RL_DIG_LEN (4U)
+#define PSRAM_UHS_PHY_RL_DIG_MSK (((1U << PSRAM_UHS_PHY_RL_DIG_LEN) - 1) << PSRAM_UHS_PHY_RL_DIG_POS)
+#define PSRAM_UHS_PHY_RL_DIG_UMSK (~(((1U << PSRAM_UHS_PHY_RL_DIG_LEN) - 1) << PSRAM_UHS_PHY_RL_DIG_POS))
+#define PSRAM_UHS_PHY_RL_ANA PSRAM_UHS_PHY_RL_ANA
+#define PSRAM_UHS_PHY_RL_ANA_POS (20U)
+#define PSRAM_UHS_PHY_RL_ANA_LEN (3U)
+#define PSRAM_UHS_PHY_RL_ANA_MSK (((1U << PSRAM_UHS_PHY_RL_ANA_LEN) - 1) << PSRAM_UHS_PHY_RL_ANA_POS)
+#define PSRAM_UHS_PHY_RL_ANA_UMSK (~(((1U << PSRAM_UHS_PHY_RL_ANA_LEN) - 1) << PSRAM_UHS_PHY_RL_ANA_POS))
+#define PSRAM_UHS_OE_TIMER PSRAM_UHS_OE_TIMER
+#define PSRAM_UHS_OE_TIMER_POS (24U)
+#define PSRAM_UHS_OE_TIMER_LEN (2U)
+#define PSRAM_UHS_OE_TIMER_MSK (((1U << PSRAM_UHS_OE_TIMER_LEN) - 1) << PSRAM_UHS_OE_TIMER_POS)
+#define PSRAM_UHS_OE_TIMER_UMSK (~(((1U << PSRAM_UHS_OE_TIMER_LEN) - 1) << PSRAM_UHS_OE_TIMER_POS))
+#define PSRAM_UHS_VREF_MODE PSRAM_UHS_VREF_MODE
+#define PSRAM_UHS_VREF_MODE_POS (26U)
+#define PSRAM_UHS_VREF_MODE_LEN (1U)
+#define PSRAM_UHS_VREF_MODE_MSK (((1U << PSRAM_UHS_VREF_MODE_LEN) - 1) << PSRAM_UHS_VREF_MODE_POS)
+#define PSRAM_UHS_VREF_MODE_UMSK (~(((1U << PSRAM_UHS_VREF_MODE_LEN) - 1) << PSRAM_UHS_VREF_MODE_POS))
+#define PSRAM_UHS_OE_CTRL_HW PSRAM_UHS_OE_CTRL_HW
+#define PSRAM_UHS_OE_CTRL_HW_POS (27U)
+#define PSRAM_UHS_OE_CTRL_HW_LEN (1U)
+#define PSRAM_UHS_OE_CTRL_HW_MSK (((1U << PSRAM_UHS_OE_CTRL_HW_LEN) - 1) << PSRAM_UHS_OE_CTRL_HW_POS)
+#define PSRAM_UHS_OE_CTRL_HW_UMSK (~(((1U << PSRAM_UHS_OE_CTRL_HW_LEN) - 1) << PSRAM_UHS_OE_CTRL_HW_POS))
+#define PSRAM_UHS_ODT_SEL PSRAM_UHS_ODT_SEL
+#define PSRAM_UHS_ODT_SEL_POS (28U)
+#define PSRAM_UHS_ODT_SEL_LEN (4U)
+#define PSRAM_UHS_ODT_SEL_MSK (((1U << PSRAM_UHS_ODT_SEL_LEN) - 1) << PSRAM_UHS_ODT_SEL_POS)
+#define PSRAM_UHS_ODT_SEL_UMSK (~(((1U << PSRAM_UHS_ODT_SEL_LEN) - 1) << PSRAM_UHS_ODT_SEL_POS))
+
+/* 0x134 : phy_cfg_34 */
+#define PSRAM_UHS_PHY_CFG_34_OFFSET (0x134)
+#define PSRAM_UHS_REG_TIMER_DQS_START PSRAM_UHS_REG_TIMER_DQS_START
+#define PSRAM_UHS_REG_TIMER_DQS_START_POS (0U)
+#define PSRAM_UHS_REG_TIMER_DQS_START_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_DQS_START_MSK (((1U << PSRAM_UHS_REG_TIMER_DQS_START_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_START_POS)
+#define PSRAM_UHS_REG_TIMER_DQS_START_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_DQS_START_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_START_POS))
+#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP
+#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_POS (8U)
+#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_MSK (((1U << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_POS)
+#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_POS))
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE PSRAM_UHS_REG_TIMER_ARRAY_WRITE
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_POS (16U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_MSK (((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_POS)
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_POS))
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ PSRAM_UHS_REG_TIMER_ARRAY_READ
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_POS (24U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_MSK (((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_POS)
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_POS))
+
+/* 0x138 : phy_cfg_38 */
+#define PSRAM_UHS_PHY_CFG_38_OFFSET (0x138)
+#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH PSRAM_UHS_REG_TIMER_AUTO_REFRESH
+#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_POS (0U)
+#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_MSK (((1U << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_LEN) - 1) << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_POS)
+#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_LEN) - 1) << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_POS))
+#define PSRAM_UHS_REG_TIMER_REG_WRITE PSRAM_UHS_REG_TIMER_REG_WRITE
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_POS (8U)
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_MSK (((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_POS)
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_POS))
+#define PSRAM_UHS_REG_TIMER_REG_READ PSRAM_UHS_REG_TIMER_REG_READ
+#define PSRAM_UHS_REG_TIMER_REG_READ_POS (16U)
+#define PSRAM_UHS_REG_TIMER_REG_READ_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_REG_READ_MSK (((1U << PSRAM_UHS_REG_TIMER_REG_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_POS)
+#define PSRAM_UHS_REG_TIMER_REG_READ_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_REG_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_POS))
+#define PSRAM_UHS_REG_TIMER_DQS_STOP PSRAM_UHS_REG_TIMER_DQS_STOP
+#define PSRAM_UHS_REG_TIMER_DQS_STOP_POS (24U)
+#define PSRAM_UHS_REG_TIMER_DQS_STOP_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_DQS_STOP_MSK (((1U << PSRAM_UHS_REG_TIMER_DQS_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_STOP_POS)
+#define PSRAM_UHS_REG_TIMER_DQS_STOP_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_DQS_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_STOP_POS))
+
+/* 0x13C : phy_cfg_3C */
+#define PSRAM_UHS_PHY_CFG_3C_OFFSET (0x13C)
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_POS (0U)
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_MSK (((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_POS)
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_POS))
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_POS (8U)
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_MSK (((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_POS)
+#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_POS))
+#define PSRAM_UHS_REG_TIMER_GLOBAL_RST PSRAM_UHS_REG_TIMER_GLOBAL_RST
+#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_POS (16U)
+#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_LEN (14U)
+#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_MSK (((1U << PSRAM_UHS_REG_TIMER_GLOBAL_RST_LEN) - 1) << PSRAM_UHS_REG_TIMER_GLOBAL_RST_POS)
+#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_GLOBAL_RST_LEN) - 1) << PSRAM_UHS_REG_TIMER_GLOBAL_RST_POS))
+
+/* 0x140 : phy_cfg_40 */
+#define PSRAM_UHS_PHY_CFG_40_OFFSET (0x140)
+#define PSRAM_UHS_VREF_SEL PSRAM_UHS_VREF_SEL
+#define PSRAM_UHS_VREF_SEL_POS (0U)
+#define PSRAM_UHS_VREF_SEL_LEN (4U)
+#define PSRAM_UHS_VREF_SEL_MSK (((1U << PSRAM_UHS_VREF_SEL_LEN) - 1) << PSRAM_UHS_VREF_SEL_POS)
+#define PSRAM_UHS_VREF_SEL_UMSK (~(((1U << PSRAM_UHS_VREF_SEL_LEN) - 1) << PSRAM_UHS_VREF_SEL_POS))
+#define PSRAM_UHS_VREF_DQ_SEL PSRAM_UHS_VREF_DQ_SEL
+#define PSRAM_UHS_VREF_DQ_SEL_POS (4U)
+#define PSRAM_UHS_VREF_DQ_SEL_LEN (4U)
+#define PSRAM_UHS_VREF_DQ_SEL_MSK (((1U << PSRAM_UHS_VREF_DQ_SEL_LEN) - 1) << PSRAM_UHS_VREF_DQ_SEL_POS)
+#define PSRAM_UHS_VREF_DQ_SEL_UMSK (~(((1U << PSRAM_UHS_VREF_DQ_SEL_LEN) - 1) << PSRAM_UHS_VREF_DQ_SEL_POS))
+#define PSRAM_UHS_REG_UHS_DMY0 PSRAM_UHS_REG_UHS_DMY0
+#define PSRAM_UHS_REG_UHS_DMY0_POS (8U)
+#define PSRAM_UHS_REG_UHS_DMY0_LEN (8U)
+#define PSRAM_UHS_REG_UHS_DMY0_MSK (((1U << PSRAM_UHS_REG_UHS_DMY0_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY0_POS)
+#define PSRAM_UHS_REG_UHS_DMY0_UMSK (~(((1U << PSRAM_UHS_REG_UHS_DMY0_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY0_POS))
+#define PSRAM_UHS_REG_UHS_DMY1 PSRAM_UHS_REG_UHS_DMY1
+#define PSRAM_UHS_REG_UHS_DMY1_POS (16U)
+#define PSRAM_UHS_REG_UHS_DMY1_LEN (8U)
+#define PSRAM_UHS_REG_UHS_DMY1_MSK (((1U << PSRAM_UHS_REG_UHS_DMY1_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY1_POS)
+#define PSRAM_UHS_REG_UHS_DMY1_UMSK (~(((1U << PSRAM_UHS_REG_UHS_DMY1_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY1_POS))
+#define PSRAM_UHS_REG_UHS_PHY_TEN PSRAM_UHS_REG_UHS_PHY_TEN
+#define PSRAM_UHS_REG_UHS_PHY_TEN_POS (24U)
+#define PSRAM_UHS_REG_UHS_PHY_TEN_LEN (1U)
+#define PSRAM_UHS_REG_UHS_PHY_TEN_MSK (((1U << PSRAM_UHS_REG_UHS_PHY_TEN_LEN) - 1) << PSRAM_UHS_REG_UHS_PHY_TEN_POS)
+#define PSRAM_UHS_REG_UHS_PHY_TEN_UMSK (~(((1U << PSRAM_UHS_REG_UHS_PHY_TEN_LEN) - 1) << PSRAM_UHS_REG_UHS_PHY_TEN_POS))
+#define PSRAM_UHS_SOC_EN_AON PSRAM_UHS_SOC_EN_AON
+#define PSRAM_UHS_SOC_EN_AON_POS (25U)
+#define PSRAM_UHS_SOC_EN_AON_LEN (1U)
+#define PSRAM_UHS_SOC_EN_AON_MSK (((1U << PSRAM_UHS_SOC_EN_AON_LEN) - 1) << PSRAM_UHS_SOC_EN_AON_POS)
+#define PSRAM_UHS_SOC_EN_AON_UMSK (~(((1U << PSRAM_UHS_SOC_EN_AON_LEN) - 1) << PSRAM_UHS_SOC_EN_AON_POS))
+#define PSRAM_UHS_TEN_UHS_PHY PSRAM_UHS_TEN_UHS_PHY
+#define PSRAM_UHS_TEN_UHS_PHY_POS (26U)
+#define PSRAM_UHS_TEN_UHS_PHY_LEN (1U)
+#define PSRAM_UHS_TEN_UHS_PHY_MSK (((1U << PSRAM_UHS_TEN_UHS_PHY_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_POS)
+#define PSRAM_UHS_TEN_UHS_PHY_UMSK (~(((1U << PSRAM_UHS_TEN_UHS_PHY_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_POS))
+#define PSRAM_UHS_TEN_UHS_PHY_DIG PSRAM_UHS_TEN_UHS_PHY_DIG
+#define PSRAM_UHS_TEN_UHS_PHY_DIG_POS (27U)
+#define PSRAM_UHS_TEN_UHS_PHY_DIG_LEN (1U)
+#define PSRAM_UHS_TEN_UHS_PHY_DIG_MSK (((1U << PSRAM_UHS_TEN_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_DIG_POS)
+#define PSRAM_UHS_TEN_UHS_PHY_DIG_UMSK (~(((1U << PSRAM_UHS_TEN_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_DIG_POS))
+#define PSRAM_UHS_TX_CLKTREE_GATE_HW PSRAM_UHS_TX_CLKTREE_GATE_HW
+#define PSRAM_UHS_TX_CLKTREE_GATE_HW_POS (29U)
+#define PSRAM_UHS_TX_CLKTREE_GATE_HW_LEN (1U)
+#define PSRAM_UHS_TX_CLKTREE_GATE_HW_MSK (((1U << PSRAM_UHS_TX_CLKTREE_GATE_HW_LEN) - 1) << PSRAM_UHS_TX_CLKTREE_GATE_HW_POS)
+#define PSRAM_UHS_TX_CLKTREE_GATE_HW_UMSK (~(((1U << PSRAM_UHS_TX_CLKTREE_GATE_HW_LEN) - 1) << PSRAM_UHS_TX_CLKTREE_GATE_HW_POS))
+#define PSRAM_UHS_UHS_DC_TP_OUT_EN PSRAM_UHS_UHS_DC_TP_OUT_EN
+#define PSRAM_UHS_UHS_DC_TP_OUT_EN_POS (30U)
+#define PSRAM_UHS_UHS_DC_TP_OUT_EN_LEN (1U)
+#define PSRAM_UHS_UHS_DC_TP_OUT_EN_MSK (((1U << PSRAM_UHS_UHS_DC_TP_OUT_EN_LEN) - 1) << PSRAM_UHS_UHS_DC_TP_OUT_EN_POS)
+#define PSRAM_UHS_UHS_DC_TP_OUT_EN_UMSK (~(((1U << PSRAM_UHS_UHS_DC_TP_OUT_EN_LEN) - 1) << PSRAM_UHS_UHS_DC_TP_OUT_EN_POS))
+#define PSRAM_UHS_UHS_PHY_DQS_DIFF PSRAM_UHS_UHS_PHY_DQS_DIFF
+#define PSRAM_UHS_UHS_PHY_DQS_DIFF_POS (31U)
+#define PSRAM_UHS_UHS_PHY_DQS_DIFF_LEN (1U)
+#define PSRAM_UHS_UHS_PHY_DQS_DIFF_MSK (((1U << PSRAM_UHS_UHS_PHY_DQS_DIFF_LEN) - 1) << PSRAM_UHS_UHS_PHY_DQS_DIFF_POS)
+#define PSRAM_UHS_UHS_PHY_DQS_DIFF_UMSK (~(((1U << PSRAM_UHS_UHS_PHY_DQS_DIFF_LEN) - 1) << PSRAM_UHS_UHS_PHY_DQS_DIFF_POS))
+
+/* 0x144 : phy_cfg_44 */
+#define PSRAM_UHS_PHY_CFG_44_OFFSET (0x144)
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_POS (0U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_MSK (((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_POS)
+#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_POS))
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_POS (8U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_MSK (((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_POS)
+#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_POS))
+#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY PSRAM_UHS_REG_TIMER_REG_READ_BUSY
+#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_POS (16U)
+#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_MSK (((1U << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_POS)
+#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_POS))
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_POS (24U)
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_LEN (8U)
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_MSK (((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_POS)
+#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_POS))
+
+/* 0x148 : phy_cfg_48 */
+#define PSRAM_UHS_PHY_CFG_48_OFFSET (0x148)
+#define PSRAM_UHS_TMUX PSRAM_UHS_TMUX
+#define PSRAM_UHS_TMUX_POS (0U)
+#define PSRAM_UHS_TMUX_LEN (3U)
+#define PSRAM_UHS_TMUX_MSK (((1U << PSRAM_UHS_TMUX_LEN) - 1) << PSRAM_UHS_TMUX_POS)
+#define PSRAM_UHS_TMUX_UMSK (~(((1U << PSRAM_UHS_TMUX_LEN) - 1) << PSRAM_UHS_TMUX_POS))
+#define PSRAM_UHS_CHIP_EN_33 PSRAM_UHS_CHIP_EN_33
+#define PSRAM_UHS_CHIP_EN_33_POS (3U)
+#define PSRAM_UHS_CHIP_EN_33_LEN (1U)
+#define PSRAM_UHS_CHIP_EN_33_MSK (((1U << PSRAM_UHS_CHIP_EN_33_LEN) - 1) << PSRAM_UHS_CHIP_EN_33_POS)
+#define PSRAM_UHS_CHIP_EN_33_UMSK (~(((1U << PSRAM_UHS_CHIP_EN_33_LEN) - 1) << PSRAM_UHS_CHIP_EN_33_POS))
+#define PSRAM_UHS_TMUX_UHS_PHY_DIG PSRAM_UHS_TMUX_UHS_PHY_DIG
+#define PSRAM_UHS_TMUX_UHS_PHY_DIG_POS (4U)
+#define PSRAM_UHS_TMUX_UHS_PHY_DIG_LEN (3U)
+#define PSRAM_UHS_TMUX_UHS_PHY_DIG_MSK (((1U << PSRAM_UHS_TMUX_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TMUX_UHS_PHY_DIG_POS)
+#define PSRAM_UHS_TMUX_UHS_PHY_DIG_UMSK (~(((1U << PSRAM_UHS_TMUX_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TMUX_UHS_PHY_DIG_POS))
+#define PSRAM_UHS_PSRAM_TYPE PSRAM_UHS_PSRAM_TYPE
+#define PSRAM_UHS_PSRAM_TYPE_POS (8U)
+#define PSRAM_UHS_PSRAM_TYPE_LEN (2U)
+#define PSRAM_UHS_PSRAM_TYPE_MSK (((1U << PSRAM_UHS_PSRAM_TYPE_LEN) - 1) << PSRAM_UHS_PSRAM_TYPE_POS)
+#define PSRAM_UHS_PSRAM_TYPE_UMSK (~(((1U << PSRAM_UHS_PSRAM_TYPE_LEN) - 1) << PSRAM_UHS_PSRAM_TYPE_POS))
+#define PSRAM_UHS_PU_UHS_PW1P8 PSRAM_UHS_PU_UHS_PW1P8
+#define PSRAM_UHS_PU_UHS_PW1P8_POS (11U)
+#define PSRAM_UHS_PU_UHS_PW1P8_LEN (1U)
+#define PSRAM_UHS_PU_UHS_PW1P8_MSK (((1U << PSRAM_UHS_PU_UHS_PW1P8_LEN) - 1) << PSRAM_UHS_PU_UHS_PW1P8_POS)
+#define PSRAM_UHS_PU_UHS_PW1P8_UMSK (~(((1U << PSRAM_UHS_PU_UHS_PW1P8_LEN) - 1) << PSRAM_UHS_PU_UHS_PW1P8_POS))
+#define PSRAM_UHS_REG_TEST_DIV_SEL PSRAM_UHS_REG_TEST_DIV_SEL
+#define PSRAM_UHS_REG_TEST_DIV_SEL_POS (12U)
+#define PSRAM_UHS_REG_TEST_DIV_SEL_LEN (3U)
+#define PSRAM_UHS_REG_TEST_DIV_SEL_MSK (((1U << PSRAM_UHS_REG_TEST_DIV_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_DIV_SEL_POS)
+#define PSRAM_UHS_REG_TEST_DIV_SEL_UMSK (~(((1U << PSRAM_UHS_REG_TEST_DIV_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_DIV_SEL_POS))
+#define PSRAM_UHS_EN_RX_FE_HW PSRAM_UHS_EN_RX_FE_HW
+#define PSRAM_UHS_EN_RX_FE_HW_POS (15U)
+#define PSRAM_UHS_EN_RX_FE_HW_LEN (1U)
+#define PSRAM_UHS_EN_RX_FE_HW_MSK (((1U << PSRAM_UHS_EN_RX_FE_HW_LEN) - 1) << PSRAM_UHS_EN_RX_FE_HW_POS)
+#define PSRAM_UHS_EN_RX_FE_HW_UMSK (~(((1U << PSRAM_UHS_EN_RX_FE_HW_LEN) - 1) << PSRAM_UHS_EN_RX_FE_HW_POS))
+#define PSRAM_UHS_REG_TEST_MUX_SEL PSRAM_UHS_REG_TEST_MUX_SEL
+#define PSRAM_UHS_REG_TEST_MUX_SEL_POS (16U)
+#define PSRAM_UHS_REG_TEST_MUX_SEL_LEN (3U)
+#define PSRAM_UHS_REG_TEST_MUX_SEL_MSK (((1U << PSRAM_UHS_REG_TEST_MUX_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_MUX_SEL_POS)
+#define PSRAM_UHS_REG_TEST_MUX_SEL_UMSK (~(((1U << PSRAM_UHS_REG_TEST_MUX_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_MUX_SEL_POS))
+#define PSRAM_UHS_FORCE_FSM PSRAM_UHS_FORCE_FSM
+#define PSRAM_UHS_FORCE_FSM_POS (19U)
+#define PSRAM_UHS_FORCE_FSM_LEN (1U)
+#define PSRAM_UHS_FORCE_FSM_MSK (((1U << PSRAM_UHS_FORCE_FSM_LEN) - 1) << PSRAM_UHS_FORCE_FSM_POS)
+#define PSRAM_UHS_FORCE_FSM_UMSK (~(((1U << PSRAM_UHS_FORCE_FSM_LEN) - 1) << PSRAM_UHS_FORCE_FSM_POS))
+#define PSRAM_UHS_EN_RX_FE_DLY PSRAM_UHS_EN_RX_FE_DLY
+#define PSRAM_UHS_EN_RX_FE_DLY_POS (20U)
+#define PSRAM_UHS_EN_RX_FE_DLY_LEN (4U)
+#define PSRAM_UHS_EN_RX_FE_DLY_MSK (((1U << PSRAM_UHS_EN_RX_FE_DLY_LEN) - 1) << PSRAM_UHS_EN_RX_FE_DLY_POS)
+#define PSRAM_UHS_EN_RX_FE_DLY_UMSK (~(((1U << PSRAM_UHS_EN_RX_FE_DLY_LEN) - 1) << PSRAM_UHS_EN_RX_FE_DLY_POS))
+
+/* 0x14C : phy_cfg_4C */
+#define PSRAM_UHS_PHY_CFG_4C_OFFSET (0x14C)
+#define PSRAM_UHS_TOUT_UHS_PHY_DIG PSRAM_UHS_TOUT_UHS_PHY_DIG
+#define PSRAM_UHS_TOUT_UHS_PHY_DIG_POS (0U)
+#define PSRAM_UHS_TOUT_UHS_PHY_DIG_LEN (16U)
+#define PSRAM_UHS_TOUT_UHS_PHY_DIG_MSK (((1U << PSRAM_UHS_TOUT_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TOUT_UHS_PHY_DIG_POS)
+#define PSRAM_UHS_TOUT_UHS_PHY_DIG_UMSK (~(((1U << PSRAM_UHS_TOUT_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TOUT_UHS_PHY_DIG_POS))
+#define PSRAM_UHS_ODT_SEL_DLY PSRAM_UHS_ODT_SEL_DLY
+#define PSRAM_UHS_ODT_SEL_DLY_POS (16U)
+#define PSRAM_UHS_ODT_SEL_DLY_LEN (4U)
+#define PSRAM_UHS_ODT_SEL_DLY_MSK (((1U << PSRAM_UHS_ODT_SEL_DLY_LEN) - 1) << PSRAM_UHS_ODT_SEL_DLY_POS)
+#define PSRAM_UHS_ODT_SEL_DLY_UMSK (~(((1U << PSRAM_UHS_ODT_SEL_DLY_LEN) - 1) << PSRAM_UHS_ODT_SEL_DLY_POS))
+#define PSRAM_UHS_ODT_SEL_HW PSRAM_UHS_ODT_SEL_HW
+#define PSRAM_UHS_ODT_SEL_HW_POS (20U)
+#define PSRAM_UHS_ODT_SEL_HW_LEN (1U)
+#define PSRAM_UHS_ODT_SEL_HW_MSK (((1U << PSRAM_UHS_ODT_SEL_HW_LEN) - 1) << PSRAM_UHS_ODT_SEL_HW_POS)
+#define PSRAM_UHS_ODT_SEL_HW_UMSK (~(((1U << PSRAM_UHS_ODT_SEL_HW_LEN) - 1) << PSRAM_UHS_ODT_SEL_HW_POS))
+
+/* 0x150 : phy_cfg_50 */
+#define PSRAM_UHS_PHY_CFG_50_OFFSET (0x150)
+#define PSRAM_UHS_DQ_OE_UP_P_REG PSRAM_UHS_DQ_OE_UP_P_REG
+#define PSRAM_UHS_DQ_OE_UP_P_REG_POS (0U)
+#define PSRAM_UHS_DQ_OE_UP_P_REG_LEN (3U)
+#define PSRAM_UHS_DQ_OE_UP_P_REG_MSK (((1U << PSRAM_UHS_DQ_OE_UP_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_P_REG_POS)
+#define PSRAM_UHS_DQ_OE_UP_P_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_UP_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_P_REG_POS))
+#define PSRAM_UHS_DQ_OE_UP_N_REG PSRAM_UHS_DQ_OE_UP_N_REG
+#define PSRAM_UHS_DQ_OE_UP_N_REG_POS (4U)
+#define PSRAM_UHS_DQ_OE_UP_N_REG_LEN (3U)
+#define PSRAM_UHS_DQ_OE_UP_N_REG_MSK (((1U << PSRAM_UHS_DQ_OE_UP_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_N_REG_POS)
+#define PSRAM_UHS_DQ_OE_UP_N_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_UP_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_N_REG_POS))
+#define PSRAM_UHS_DQ_OE_MID_P_REG PSRAM_UHS_DQ_OE_MID_P_REG
+#define PSRAM_UHS_DQ_OE_MID_P_REG_POS (8U)
+#define PSRAM_UHS_DQ_OE_MID_P_REG_LEN (3U)
+#define PSRAM_UHS_DQ_OE_MID_P_REG_MSK (((1U << PSRAM_UHS_DQ_OE_MID_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_P_REG_POS)
+#define PSRAM_UHS_DQ_OE_MID_P_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_MID_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_P_REG_POS))
+#define PSRAM_UHS_DQ_OE_MID_N_REG PSRAM_UHS_DQ_OE_MID_N_REG
+#define PSRAM_UHS_DQ_OE_MID_N_REG_POS (12U)
+#define PSRAM_UHS_DQ_OE_MID_N_REG_LEN (3U)
+#define PSRAM_UHS_DQ_OE_MID_N_REG_MSK (((1U << PSRAM_UHS_DQ_OE_MID_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_N_REG_POS)
+#define PSRAM_UHS_DQ_OE_MID_N_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_MID_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_N_REG_POS))
+#define PSRAM_UHS_DQ_OE_DN_P_REG PSRAM_UHS_DQ_OE_DN_P_REG
+#define PSRAM_UHS_DQ_OE_DN_P_REG_POS (16U)
+#define PSRAM_UHS_DQ_OE_DN_P_REG_LEN (3U)
+#define PSRAM_UHS_DQ_OE_DN_P_REG_MSK (((1U << PSRAM_UHS_DQ_OE_DN_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_P_REG_POS)
+#define PSRAM_UHS_DQ_OE_DN_P_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_DN_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_P_REG_POS))
+#define PSRAM_UHS_DQ_OE_DN_N_REG PSRAM_UHS_DQ_OE_DN_N_REG
+#define PSRAM_UHS_DQ_OE_DN_N_REG_POS (20U)
+#define PSRAM_UHS_DQ_OE_DN_N_REG_LEN (3U)
+#define PSRAM_UHS_DQ_OE_DN_N_REG_MSK (((1U << PSRAM_UHS_DQ_OE_DN_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_N_REG_POS)
+#define PSRAM_UHS_DQ_OE_DN_N_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_DN_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_N_REG_POS))
+#define PSRAM_UHS_PHY_WL_CEN_ANA PSRAM_UHS_PHY_WL_CEN_ANA
+#define PSRAM_UHS_PHY_WL_CEN_ANA_POS (24U)
+#define PSRAM_UHS_PHY_WL_CEN_ANA_LEN (3U)
+#define PSRAM_UHS_PHY_WL_CEN_ANA_MSK (((1U << PSRAM_UHS_PHY_WL_CEN_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_CEN_ANA_POS)
+#define PSRAM_UHS_PHY_WL_CEN_ANA_UMSK (~(((1U << PSRAM_UHS_PHY_WL_CEN_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_CEN_ANA_POS))
+
+struct psram_uhs_reg {
+ /* 0x0 : UHS_basic */
+ union {
+ struct {
+ uint32_t reg_init_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_af_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_config_req : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_config_gnt : 1; /* [ 3], r, 0x0 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t reg_mode_reg : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_addrMB_msk : 8; /* [23:16], r/w, 0x1f */
+ uint32_t reserved_24_27 : 4; /* [27:24], rsvd, 0x0 */
+ uint32_t reg_linear_bnd_b : 4; /* [31:28], r/w, 0xa */
+ } BF;
+ uint32_t WORD;
+ } UHS_basic;
+
+ /* 0x4 : UHS_cmd */
+ union {
+ struct {
+ uint32_t reg_glbr_pulse : 1; /* [ 0], w1p, 0x0 */
+ uint32_t reg_srfi_pulse : 1; /* [ 1], w1p, 0x0 */
+ uint32_t reg_srfo_pulse : 1; /* [ 2], w1p, 0x0 */
+ uint32_t reg_regw_pulse : 1; /* [ 3], w1p, 0x0 */
+ uint32_t reg_regr_pulse : 1; /* [ 4], w1p, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t sts_glbr_done : 1; /* [ 8], r, 0x0 */
+ uint32_t sts_srfi_done : 1; /* [ 9], r, 0x0 */
+ uint32_t sts_srfo_done : 1; /* [ 10], r, 0x0 */
+ uint32_t sts_regw_done : 1; /* [ 11], r, 0x0 */
+ uint32_t sts_regr_done : 1; /* [ 12], r, 0x0 */
+ uint32_t sts_init_done : 1; /* [ 13], r, 0x0 */
+ uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */
+ uint32_t sts_config_read : 8; /* [31:24], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_cmd;
+
+ /* 0x8 : UHS_fifo_thre */
+ union {
+ struct {
+ uint32_t reg_mask_w_fifo_cnt : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t reg_mask_r_fifo_rem : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_fifo_thre;
+
+ /* 0xC : UHS_manual */
+ union {
+ struct {
+ uint32_t reg_force_ceb_low : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_force_ceb_high : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_psram_resetb : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reg_x16_mode : 1; /* [ 3], r/w, 0x1 */
+ uint32_t reg_wrap2incr_en : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
+ uint32_t reg_pck_s_div : 3; /* [18:16], r/w, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t reg_pck_t_div : 8; /* [31:24], r/w, 0x40 */
+ } BF;
+ uint32_t WORD;
+ } UHS_manual;
+
+ /* 0x10 : UHS_auto_fresh_1 */
+ union {
+ struct {
+ uint32_t reg_win_cycle : 28; /* [27: 0], r/w, 0x27100 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_auto_fresh_1;
+
+ /* 0x14 : UHS_auto_fresh_2 */
+ union {
+ struct {
+ uint32_t reg_refi_cycle : 16; /* [15: 0], r/w, 0x27 */
+ uint32_t reg_win_ref_cnt : 13; /* [28:16], r/w, 0x1000 */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_auto_fresh_2;
+
+ /* 0x18 : UHS_auto_fresh_3 */
+ union {
+ struct {
+ uint32_t reg_auto_ref_thre : 12; /* [11: 0], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t auto_refresh_level : 12; /* [27:16], r, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_auto_fresh_3;
+
+ /* 0x1C : UHS_auto_fresh_4 */
+ union {
+ struct {
+ uint32_t reg_bust_cycle : 7; /* [ 6: 0], r/w, 0x1d */
+ uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_auto_fresh_4;
+
+ /* 0x20 : UHS_psram_configure */
+ union {
+ struct {
+ uint32_t reg_uhs_latency : 3; /* [ 2: 0], r/w, 0x5 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t reg_uhs_drive_st : 4; /* [ 7: 4], r/w, 0xa */
+ uint32_t reg_uhs_bl_16 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_uhs_bl_32 : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg_uhs_bl_64 : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_psram_configure;
+
+ /* 0x24 : UHS_psram_status */
+ union {
+ struct {
+ uint32_t sts_uhs_latency : 3; /* [ 2: 0], r, 0x5 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t sts_uhs_drive_st : 4; /* [ 7: 4], r, 0xa */
+ uint32_t sts_uhs_bl_16 : 1; /* [ 8], r, 0x0 */
+ uint32_t sts_uhs_bl_32 : 1; /* [ 9], r, 0x0 */
+ uint32_t sts_uhs_bl_64 : 1; /* [ 10], r, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_psram_status;
+
+ /* 0x28 reserved */
+ uint8_t RESERVED0x28[8];
+
+ /* 0x30 : UHS_timing_ctrl */
+ union {
+ struct {
+ uint32_t reg_trc_cycle : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reg_tcphr_cycle : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_tcphw_cycle : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_trfc_cycle : 8; /* [31:24], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_timing_ctrl;
+
+ /* 0x34 : UHS_rsvd_reg */
+ union {
+ struct {
+ uint32_t reg_mr0_7 : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_mr2_2_0 : 3; /* [ 3: 1], r/w, 0x0 */
+ uint32_t reg_mr2_7_6 : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_rsvd_reg;
+
+ /* 0x38 reserved */
+ uint8_t RESERVED0x38[136];
+
+ /* 0xC0 : UHS_dbg_sel */
+ union {
+ struct {
+ uint32_t reg_psram_dbg_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t reg_psram_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } UHS_dbg_sel;
+
+ /* 0xc4 reserved */
+ uint8_t RESERVED0xc4[44];
+
+ /* 0xF0 : UHS_dummy_reg */
+ union {
+ struct {
+ uint32_t reg_psram_dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */
+ } BF;
+ uint32_t WORD;
+ } UHS_dummy_reg;
+
+ /* 0xf4 reserved */
+ uint8_t RESERVED0xf4[12];
+
+ /* 0x100 : phy_cfg_00 */
+ union {
+ struct {
+ uint32_t dqs_rdy : 1; /* [ 0], r, 0x0 */
+ uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
+ uint32_t ck_sr : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_14 : 5; /* [14:10], rsvd, 0x0 */
+ uint32_t clk0_polarity : 1; /* [ 15], r/w, 0x0 */
+ uint32_t ck_dly_drv : 4; /* [19:16], r/w, 0x8 */
+ uint32_t cen_sr : 2; /* [21:20], r/w, 0x0 */
+ uint32_t reserved_22_27 : 6; /* [27:22], rsvd, 0x0 */
+ uint32_t cen_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_00;
+
+ /* 0x104 : phy_cfg_04 */
+ union {
+ struct {
+ uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */
+ uint32_t dm1_sr : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t reserved_6_11 : 6; /* [11: 6], rsvd, 0x0 */
+ uint32_t dm1_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t reserved_16_19 : 4; /* [19:16], rsvd, 0x0 */
+ uint32_t dm0_sr : 2; /* [21:20], r/w, 0x0 */
+ uint32_t reserved_22_27 : 6; /* [27:22], rsvd, 0x0 */
+ uint32_t dm0_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_04;
+
+ /* 0x108 : phy_cfg_08 */
+ union {
+ struct {
+ uint32_t dq1_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq1_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq1_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq0_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq0_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq0_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_08;
+
+ /* 0x10C : phy_cfg_0C */
+ union {
+ struct {
+ uint32_t dq3_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq3_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq3_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq2_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq2_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq2_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_0C;
+
+ /* 0x110 : phy_cfg_10 */
+ union {
+ struct {
+ uint32_t dq5_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq5_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq5_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq4_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq4_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq4_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_10;
+
+ /* 0x114 : phy_cfg_14 */
+ union {
+ struct {
+ uint32_t dq7_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq7_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq7_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq6_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq6_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq6_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_14;
+
+ /* 0x118 : phy_cfg_18 */
+ union {
+ struct {
+ uint32_t dq9_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq9_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq9_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq8_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq8_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq8_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_18;
+
+ /* 0x11C : phy_cfg_1C */
+ union {
+ struct {
+ uint32_t dq11_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq11_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq11_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq10_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq10_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq10_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_1C;
+
+ /* 0x120 : phy_cfg_20 */
+ union {
+ struct {
+ uint32_t dq13_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq13_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq13_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq12_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq12_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq12_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_20;
+
+ /* 0x124 : phy_cfg_24 */
+ union {
+ struct {
+ uint32_t dq15_sr : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t dq15_dly_rx : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t dq15_dly_drv : 4; /* [15:12], r/w, 0x8 */
+ uint32_t dq14_sr : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
+ uint32_t dq14_dly_rx : 4; /* [27:24], r/w, 0x1 */
+ uint32_t dq14_dly_drv : 4; /* [31:28], r/w, 0x8 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_24;
+
+ /* 0x128 : phy_cfg_28 */
+ union {
+ struct {
+ uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */
+ uint32_t dqs0n_dly_rx : 4; /* [11: 8], r/w, 0x3 */
+ uint32_t dqs0_sr : 2; /* [13:12], r/w, 0x0 */
+ uint32_t dqs0_sel : 2; /* [15:14], r/w, 0x0 */
+ uint32_t reserved_16_19 : 4; /* [19:16], rsvd, 0x0 */
+ uint32_t dqs0_dly_rx : 4; /* [23:20], r/w, 0x3 */
+ uint32_t dqs0_dly_drv : 4; /* [27:24], r/w, 0x8 */
+ uint32_t dqs0_diff_dly_rx : 4; /* [31:28], r/w, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_28;
+
+ /* 0x12C : phy_cfg_2C */
+ union {
+ struct {
+ uint32_t ipp5un_lpddr : 1; /* [ 0], r/w, 0x0 */
+ uint32_t en_rx_fe : 1; /* [ 1], r/w, 0x1 */
+ uint32_t en_bias : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
+ uint32_t dqs1n_dly_rx : 4; /* [11: 8], r/w, 0x3 */
+ uint32_t dqs1_sr : 2; /* [13:12], r/w, 0x0 */
+ uint32_t dqs1_sel : 2; /* [15:14], r/w, 0x0 */
+ uint32_t reserved_16_19 : 4; /* [19:16], rsvd, 0x0 */
+ uint32_t dqs1_dly_rx : 4; /* [23:20], r/w, 0x3 */
+ uint32_t dqs1_dly_drv : 4; /* [27:24], r/w, 0x8 */
+ uint32_t dqs1_diff_dly_rx : 4; /* [31:28], r/w, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_2C;
+
+ /* 0x130 : phy_cfg_30 */
+ union {
+ struct {
+ uint32_t phy_wl_dq_dig : 3; /* [ 2: 0], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t phy_wl_dq_ana : 3; /* [ 6: 4], r/w, 0x2 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t phy_wl_dig : 3; /* [10: 8], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t phy_wl_ana : 3; /* [14:12], r/w, 0x1 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t phy_rl_dig : 4; /* [19:16], r/w, 0x3 */
+ uint32_t phy_rl_ana : 3; /* [22:20], r/w, 0x3 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t oe_timer : 2; /* [25:24], r/w, 0x2 */
+ uint32_t vref_mode : 1; /* [ 26], r/w, 0x0 */
+ uint32_t oe_ctrl_hw : 1; /* [ 27], r/w, 0x1 */
+ uint32_t odt_sel : 4; /* [31:28], r/w, 0xa */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_30;
+
+ /* 0x134 : phy_cfg_34 */
+ union {
+ struct {
+ uint32_t reg_timer_dqs_start : 8; /* [ 7: 0], r/w, 0x1 */
+ uint32_t reg_timer_dqs_array_stop : 8; /* [15: 8], r/w, 0x1 */
+ uint32_t reg_timer_array_write : 8; /* [23:16], r/w, 0x0 */
+ uint32_t reg_timer_array_read : 8; /* [31:24], r/w, 0x5 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_34;
+
+ /* 0x138 : phy_cfg_38 */
+ union {
+ struct {
+ uint32_t reg_timer_auto_refresh : 8; /* [ 7: 0], r/w, 0x7 */
+ uint32_t reg_timer_reg_write : 8; /* [15: 8], r/w, 0x1 */
+ uint32_t reg_timer_reg_read : 8; /* [23:16], r/w, 0x8 */
+ uint32_t reg_timer_dqs_stop : 8; /* [31:24], r/w, 0x2 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_38;
+
+ /* 0x13C : phy_cfg_3C */
+ union {
+ struct {
+ uint32_t reg_timer_self_refresh1_in : 8; /* [ 7: 0], r/w, 0x8 */
+ uint32_t reg_timer_self_refresh1_exit : 8; /* [15: 8], r/w, 0x8 */
+ uint32_t reg_timer_global_rst : 14; /* [29:16], r/w, 0x272 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_3C;
+
+ /* 0x140 : phy_cfg_40 */
+ union {
+ struct {
+ uint32_t vref_sel : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t vref_dq_sel : 4; /* [ 7: 4], r/w, 0x0 */
+ uint32_t reg_uhs_dmy0 : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_uhs_dmy1 : 8; /* [23:16], r/w, 0xff */
+ uint32_t reg_uhs_phy_ten : 1; /* [ 24], r/w, 0x0 */
+ uint32_t soc_en_aon : 1; /* [ 25], r/w, 0x1 */
+ uint32_t ten_uhs_phy : 1; /* [ 26], r/w, 0x0 */
+ uint32_t ten_uhs_phy_dig : 1; /* [ 27], r/w, 0x0 */
+ uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */
+ uint32_t tx_clktree_gate_hw : 1; /* [ 29], r/w, 0x1 */
+ uint32_t uhs_dc_tp_out_en : 1; /* [ 30], r/w, 0x0 */
+ uint32_t uhs_phy_dqs_diff : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_40;
+
+ /* 0x144 : phy_cfg_44 */
+ union {
+ struct {
+ uint32_t reg_timer_array_read_busy : 8; /* [ 7: 0], r/w, 0x8 */
+ uint32_t reg_timer_array_write_busy : 8; /* [15: 8], r/w, 0x3 */
+ uint32_t reg_timer_reg_read_busy : 8; /* [23:16], r/w, 0xb */
+ uint32_t reg_timer_reg_write_busy : 8; /* [31:24], r/w, 0x4 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_44;
+
+ /* 0x148 : phy_cfg_48 */
+ union {
+ struct {
+ uint32_t tmux : 3; /* [ 2: 0], r/w, 0x0 */
+ uint32_t chip_en_33 : 1; /* [ 3], r/w, 0x1 */
+ uint32_t tmux_uhs_phy_dig : 3; /* [ 6: 4], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t psram_type : 2; /* [ 9: 8], r/w, 0x1 */
+ uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
+ uint32_t pu_uhs_pw1p8 : 1; /* [ 11], r/w, 0x1 */
+ uint32_t reg_test_div_sel : 3; /* [14:12], r/w, 0x0 */
+ uint32_t en_rx_fe_hw : 1; /* [ 15], r/w, 0x1 */
+ uint32_t reg_test_mux_sel : 3; /* [18:16], r/w, 0x0 */
+ uint32_t force_fsm : 1; /* [ 19], r/w, 0x0 */
+ uint32_t en_rx_fe_dly : 4; /* [23:20], r/w, 0x2 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_48;
+
+ /* 0x14C : phy_cfg_4C */
+ union {
+ struct {
+ uint32_t tout_uhs_phy_dig : 16; /* [15: 0], r, 0x0 */
+ uint32_t odt_sel_dly : 4; /* [19:16], r/w, 0x3 */
+ uint32_t odt_sel_hw : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_4C;
+
+ /* 0x150 : phy_cfg_50 */
+ union {
+ struct {
+ uint32_t dq_oe_up_p_reg : 3; /* [ 2: 0], r/w, 0x4 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t dq_oe_up_n_reg : 3; /* [ 6: 4], r/w, 0x4 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t dq_oe_mid_p_reg : 3; /* [10: 8], r/w, 0x4 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t dq_oe_mid_n_reg : 3; /* [14:12], r/w, 0x4 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t dq_oe_dn_p_reg : 3; /* [18:16], r/w, 0x4 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t dq_oe_dn_n_reg : 3; /* [22:20], r/w, 0x4 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t phy_wl_cen_ana : 3; /* [26:24], r/w, 0x1 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } phy_cfg_50;
+};
+
+typedef volatile struct psram_uhs_reg psram_uhs_reg_t;
+
+#endif /* __PSRAM_UHS_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/sdh_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/sdh_reg.h
new file mode 100644
index 00000000..f7eb5f49
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/sdh_reg.h
@@ -0,0 +1,2732 @@
+/**
+ ******************************************************************************
+ * @file sdh_reg.h
+ * @version V1.2
+ * @date 2018-10-08
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2018 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __SDH_REG_H__
+#define __SDH_REG_H__
+
+#include "bl808.h"
+
+/* 0x00 : System Address Low Register */
+#define SDH_SD_SYS_ADDR_LOW_OFFSET (0x00)
+#define SDH_DMA_ADDR_L SDH_DMA_ADDR_L
+#define SDH_DMA_ADDR_L_POS (0U)
+#define SDH_DMA_ADDR_L_LEN (16U)
+#define SDH_DMA_ADDR_L_MSK (((1U << SDH_DMA_ADDR_L_LEN) - 1) << SDH_DMA_ADDR_L_POS)
+#define SDH_DMA_ADDR_L_UMSK (~(((1U << SDH_DMA_ADDR_L_LEN) - 1) << SDH_DMA_ADDR_L_POS))
+
+/* 0x02 : System Address High Register */
+#define SDH_SD_SYS_ADDR_HIGH_OFFSET (0x02)
+#define SDH_DMA_ADDR_H SDH_DMA_ADDR_H
+#define SDH_DMA_ADDR_H_POS (0U)
+#define SDH_DMA_ADDR_H_LEN (16U)
+#define SDH_DMA_ADDR_H_MSK (((1U << SDH_DMA_ADDR_H_LEN) - 1) << SDH_DMA_ADDR_H_POS)
+#define SDH_DMA_ADDR_H_UMSK (~(((1U << SDH_DMA_ADDR_H_LEN) - 1) << SDH_DMA_ADDR_H_POS))
+
+/* 0x04 : Block Size Register */
+#define SDH_SD_BLOCK_SIZE_OFFSET (0x04)
+#define SDH_BLOCK_SIZE SDH_BLOCK_SIZE
+#define SDH_BLOCK_SIZE_POS (0U)
+#define SDH_BLOCK_SIZE_LEN (12U)
+#define SDH_BLOCK_SIZE_MSK (((1U << SDH_BLOCK_SIZE_LEN) - 1) << SDH_BLOCK_SIZE_POS)
+#define SDH_BLOCK_SIZE_UMSK (~(((1U << SDH_BLOCK_SIZE_LEN) - 1) << SDH_BLOCK_SIZE_POS))
+#define SDH_HOST_DMA_BDRY SDH_HOST_DMA_BDRY
+#define SDH_HOST_DMA_BDRY_POS (12U)
+#define SDH_HOST_DMA_BDRY_LEN (3U)
+#define SDH_HOST_DMA_BDRY_MSK (((1U << SDH_HOST_DMA_BDRY_LEN) - 1) << SDH_HOST_DMA_BDRY_POS)
+#define SDH_HOST_DMA_BDRY_UMSK (~(((1U << SDH_HOST_DMA_BDRY_LEN) - 1) << SDH_HOST_DMA_BDRY_POS))
+
+/* 0x06 : Block Count Register */
+#define SDH_SD_BLOCK_COUNT_OFFSET (0x06)
+#define SDH_BLOCK_COUNT SDH_BLOCK_COUNT
+#define SDH_BLOCK_COUNT_POS (0U)
+#define SDH_BLOCK_COUNT_LEN (16U)
+#define SDH_BLOCK_COUNT_MSK (((1U << SDH_BLOCK_COUNT_LEN) - 1) << SDH_BLOCK_COUNT_POS)
+#define SDH_BLOCK_COUNT_UMSK (~(((1U << SDH_BLOCK_COUNT_LEN) - 1) << SDH_BLOCK_COUNT_POS))
+
+/* 0x08 : Argument Low Register */
+#define SDH_SD_ARG_LOW_OFFSET (0x08)
+#define SDH_ARG_L SDH_ARG_L
+#define SDH_ARG_L_POS (0U)
+#define SDH_ARG_L_LEN (16U)
+#define SDH_ARG_L_MSK (((1U << SDH_ARG_L_LEN) - 1) << SDH_ARG_L_POS)
+#define SDH_ARG_L_UMSK (~(((1U << SDH_ARG_L_LEN) - 1) << SDH_ARG_L_POS))
+
+/* 0x0A : Argument High Register */
+#define SDH_SD_ARG_HIGH_OFFSET (0x0A)
+#define SDH_ARG_H SDH_ARG_H
+#define SDH_ARG_H_POS (0U)
+#define SDH_ARG_H_LEN (16U)
+#define SDH_ARG_H_MSK (((1U << SDH_ARG_H_LEN) - 1) << SDH_ARG_H_POS)
+#define SDH_ARG_H_UMSK (~(((1U << SDH_ARG_H_LEN) - 1) << SDH_ARG_H_POS))
+
+/* 0x0C : Transfer Mode Register */
+#define SDH_SD_TRANSFER_MODE_OFFSET (0x0C)
+#define SDH_DMA_EN SDH_DMA_EN
+#define SDH_DMA_EN_POS (0U)
+#define SDH_DMA_EN_LEN (1U)
+#define SDH_DMA_EN_MSK (((1U << SDH_DMA_EN_LEN) - 1) << SDH_DMA_EN_POS)
+#define SDH_DMA_EN_UMSK (~(((1U << SDH_DMA_EN_LEN) - 1) << SDH_DMA_EN_POS))
+#define SDH_BLK_CNT_EN SDH_BLK_CNT_EN
+#define SDH_BLK_CNT_EN_POS (1U)
+#define SDH_BLK_CNT_EN_LEN (1U)
+#define SDH_BLK_CNT_EN_MSK (((1U << SDH_BLK_CNT_EN_LEN) - 1) << SDH_BLK_CNT_EN_POS)
+#define SDH_BLK_CNT_EN_UMSK (~(((1U << SDH_BLK_CNT_EN_LEN) - 1) << SDH_BLK_CNT_EN_POS))
+#define SDH_AUTO_CMD_EN SDH_AUTO_CMD_EN
+#define SDH_AUTO_CMD_EN_POS (2U)
+#define SDH_AUTO_CMD_EN_LEN (2U)
+#define SDH_AUTO_CMD_EN_MSK (((1U << SDH_AUTO_CMD_EN_LEN) - 1) << SDH_AUTO_CMD_EN_POS)
+#define SDH_AUTO_CMD_EN_UMSK (~(((1U << SDH_AUTO_CMD_EN_LEN) - 1) << SDH_AUTO_CMD_EN_POS))
+#define SDH_TO_HOST_DIR SDH_TO_HOST_DIR
+#define SDH_TO_HOST_DIR_POS (4U)
+#define SDH_TO_HOST_DIR_LEN (1U)
+#define SDH_TO_HOST_DIR_MSK (((1U << SDH_TO_HOST_DIR_LEN) - 1) << SDH_TO_HOST_DIR_POS)
+#define SDH_TO_HOST_DIR_UMSK (~(((1U << SDH_TO_HOST_DIR_LEN) - 1) << SDH_TO_HOST_DIR_POS))
+#define SDH_MULTI_BLK_SEL SDH_MULTI_BLK_SEL
+#define SDH_MULTI_BLK_SEL_POS (5U)
+#define SDH_MULTI_BLK_SEL_LEN (1U)
+#define SDH_MULTI_BLK_SEL_MSK (((1U << SDH_MULTI_BLK_SEL_LEN) - 1) << SDH_MULTI_BLK_SEL_POS)
+#define SDH_MULTI_BLK_SEL_UMSK (~(((1U << SDH_MULTI_BLK_SEL_LEN) - 1) << SDH_MULTI_BLK_SEL_POS))
+
+/* 0x0E : Command Register */
+#define SDH_SD_CMD_OFFSET (0x0E)
+#define SDH_RESP_TYPE SDH_RESP_TYPE
+#define SDH_RESP_TYPE_POS (0U)
+#define SDH_RESP_TYPE_LEN (2U)
+#define SDH_RESP_TYPE_MSK (((1U << SDH_RESP_TYPE_LEN) - 1) << SDH_RESP_TYPE_POS)
+#define SDH_RESP_TYPE_UMSK (~(((1U << SDH_RESP_TYPE_LEN) - 1) << SDH_RESP_TYPE_POS))
+#define SDH_CMD_CRC_CHK_EN SDH_CMD_CRC_CHK_EN
+#define SDH_CMD_CRC_CHK_EN_POS (3U)
+#define SDH_CMD_CRC_CHK_EN_LEN (1U)
+#define SDH_CMD_CRC_CHK_EN_MSK (((1U << SDH_CMD_CRC_CHK_EN_LEN) - 1) << SDH_CMD_CRC_CHK_EN_POS)
+#define SDH_CMD_CRC_CHK_EN_UMSK (~(((1U << SDH_CMD_CRC_CHK_EN_LEN) - 1) << SDH_CMD_CRC_CHK_EN_POS))
+#define SDH_CMD_INDEX_CHK_EN SDH_CMD_INDEX_CHK_EN
+#define SDH_CMD_INDEX_CHK_EN_POS (4U)
+#define SDH_CMD_INDEX_CHK_EN_LEN (1U)
+#define SDH_CMD_INDEX_CHK_EN_MSK (((1U << SDH_CMD_INDEX_CHK_EN_LEN) - 1) << SDH_CMD_INDEX_CHK_EN_POS)
+#define SDH_CMD_INDEX_CHK_EN_UMSK (~(((1U << SDH_CMD_INDEX_CHK_EN_LEN) - 1) << SDH_CMD_INDEX_CHK_EN_POS))
+#define SDH_DATA_PRESENT SDH_DATA_PRESENT
+#define SDH_DATA_PRESENT_POS (5U)
+#define SDH_DATA_PRESENT_LEN (1U)
+#define SDH_DATA_PRESENT_MSK (((1U << SDH_DATA_PRESENT_LEN) - 1) << SDH_DATA_PRESENT_POS)
+#define SDH_DATA_PRESENT_UMSK (~(((1U << SDH_DATA_PRESENT_LEN) - 1) << SDH_DATA_PRESENT_POS))
+#define SDH_CMD_TYPE SDH_CMD_TYPE
+#define SDH_CMD_TYPE_POS (6U)
+#define SDH_CMD_TYPE_LEN (2U)
+#define SDH_CMD_TYPE_MSK (((1U << SDH_CMD_TYPE_LEN) - 1) << SDH_CMD_TYPE_POS)
+#define SDH_CMD_TYPE_UMSK (~(((1U << SDH_CMD_TYPE_LEN) - 1) << SDH_CMD_TYPE_POS))
+#define SDH_CMD_INDEX SDH_CMD_INDEX
+#define SDH_CMD_INDEX_POS (8U)
+#define SDH_CMD_INDEX_LEN (6U)
+#define SDH_CMD_INDEX_MSK (((1U << SDH_CMD_INDEX_LEN) - 1) << SDH_CMD_INDEX_POS)
+#define SDH_CMD_INDEX_UMSK (~(((1U << SDH_CMD_INDEX_LEN) - 1) << SDH_CMD_INDEX_POS))
+
+/* 0x10 : Response Register 0 */
+#define SDH_SD_RESP_0_OFFSET (0x10)
+#define SDH_RESP0 SDH_RESP0
+#define SDH_RESP0_POS (0U)
+#define SDH_RESP0_LEN (16U)
+#define SDH_RESP0_MSK (((1U << SDH_RESP0_LEN) - 1) << SDH_RESP0_POS)
+#define SDH_RESP0_UMSK (~(((1U << SDH_RESP0_LEN) - 1) << SDH_RESP0_POS))
+
+/* 0x12 : Response Register 1 */
+#define SDH_SD_RESP_1_OFFSET (0x12)
+#define SDH_RESP1 SDH_RESP1
+#define SDH_RESP1_POS (0U)
+#define SDH_RESP1_LEN (16U)
+#define SDH_RESP1_MSK (((1U << SDH_RESP1_LEN) - 1) << SDH_RESP1_POS)
+#define SDH_RESP1_UMSK (~(((1U << SDH_RESP1_LEN) - 1) << SDH_RESP1_POS))
+
+/* 0x14 : Response Register 2 */
+#define SDH_SD_RESP_2_OFFSET (0x14)
+#define SDH_RESP2 SDH_RESP2
+#define SDH_RESP2_POS (0U)
+#define SDH_RESP2_LEN (16U)
+#define SDH_RESP2_MSK (((1U << SDH_RESP2_LEN) - 1) << SDH_RESP2_POS)
+#define SDH_RESP2_UMSK (~(((1U << SDH_RESP2_LEN) - 1) << SDH_RESP2_POS))
+
+/* 0x16 : Response Register 3 */
+#define SDH_SD_RESP_3_OFFSET (0x16)
+#define SDH_RESP3 SDH_RESP3
+#define SDH_RESP3_POS (0U)
+#define SDH_RESP3_LEN (16U)
+#define SDH_RESP3_MSK (((1U << SDH_RESP3_LEN) - 1) << SDH_RESP3_POS)
+#define SDH_RESP3_UMSK (~(((1U << SDH_RESP3_LEN) - 1) << SDH_RESP3_POS))
+
+/* 0x18 : Response Register 4 */
+#define SDH_SD_RESP_4_OFFSET (0x18)
+#define SDH_RESP4 SDH_RESP4
+#define SDH_RESP4_POS (0U)
+#define SDH_RESP4_LEN (16U)
+#define SDH_RESP4_MSK (((1U << SDH_RESP4_LEN) - 1) << SDH_RESP4_POS)
+#define SDH_RESP4_UMSK (~(((1U << SDH_RESP4_LEN) - 1) << SDH_RESP4_POS))
+
+/* 0x1A : Response Register 5 */
+#define SDH_SD_RESP_5_OFFSET (0x1A)
+#define SDH_RESP5 SDH_RESP5
+#define SDH_RESP5_POS (0U)
+#define SDH_RESP5_LEN (16U)
+#define SDH_RESP5_MSK (((1U << SDH_RESP5_LEN) - 1) << SDH_RESP5_POS)
+#define SDH_RESP5_UMSK (~(((1U << SDH_RESP5_LEN) - 1) << SDH_RESP5_POS))
+
+/* 0x1C : Response Register 6 */
+#define SDH_SD_RESP_6_OFFSET (0x1C)
+#define SDH_RESP6 SDH_RESP6
+#define SDH_RESP6_POS (0U)
+#define SDH_RESP6_LEN (16U)
+#define SDH_RESP6_MSK (((1U << SDH_RESP6_LEN) - 1) << SDH_RESP6_POS)
+#define SDH_RESP6_UMSK (~(((1U << SDH_RESP6_LEN) - 1) << SDH_RESP6_POS))
+
+/* 0x1E : Response Register 7 */
+#define SDH_SD_RESP_7_OFFSET (0x1E)
+#define SDH_RESP7 SDH_RESP7
+#define SDH_RESP7_POS (0U)
+#define SDH_RESP7_LEN (16U)
+#define SDH_RESP7_MSK (((1U << SDH_RESP7_LEN) - 1) << SDH_RESP7_POS)
+#define SDH_RESP7_UMSK (~(((1U << SDH_RESP7_LEN) - 1) << SDH_RESP7_POS))
+
+/* 0x20 : Buffer Data Port 0 Register */
+#define SDH_SD_BUFFER_DATA_PORT_0_OFFSET (0x20)
+#define SDH_CPU_DATA0 SDH_CPU_DATA0
+#define SDH_CPU_DATA0_POS (0U)
+#define SDH_CPU_DATA0_LEN (16U)
+#define SDH_CPU_DATA0_MSK (((1U << SDH_CPU_DATA0_LEN) - 1) << SDH_CPU_DATA0_POS)
+#define SDH_CPU_DATA0_UMSK (~(((1U << SDH_CPU_DATA0_LEN) - 1) << SDH_CPU_DATA0_POS))
+
+/* 0x22 : Buffer Data Port 1 Register */
+#define SDH_SD_BUFFER_DATA_PORT_1_OFFSET (0x22)
+#define SDH_CPU_DATA1 SDH_CPU_DATA1
+#define SDH_CPU_DATA1_POS (0U)
+#define SDH_CPU_DATA1_LEN (16U)
+#define SDH_CPU_DATA1_MSK (((1U << SDH_CPU_DATA1_LEN) - 1) << SDH_CPU_DATA1_POS)
+#define SDH_CPU_DATA1_UMSK (~(((1U << SDH_CPU_DATA1_LEN) - 1) << SDH_CPU_DATA1_POS))
+
+/* 0x24 : Present State Register 1 */
+#define SDH_SD_PRESENT_STATE_1_OFFSET (0x24)
+#define SDH_CMD_INHIBIT_CMD SDH_CMD_INHIBIT_CMD
+#define SDH_CMD_INHIBIT_CMD_POS (0U)
+#define SDH_CMD_INHIBIT_CMD_LEN (1U)
+#define SDH_CMD_INHIBIT_CMD_MSK (((1U << SDH_CMD_INHIBIT_CMD_LEN) - 1) << SDH_CMD_INHIBIT_CMD_POS)
+#define SDH_CMD_INHIBIT_CMD_UMSK (~(((1U << SDH_CMD_INHIBIT_CMD_LEN) - 1) << SDH_CMD_INHIBIT_CMD_POS))
+#define SDH_CMD_INHIBIT_DAT SDH_CMD_INHIBIT_DAT
+#define SDH_CMD_INHIBIT_DAT_POS (1U)
+#define SDH_CMD_INHIBIT_DAT_LEN (1U)
+#define SDH_CMD_INHIBIT_DAT_MSK (((1U << SDH_CMD_INHIBIT_DAT_LEN) - 1) << SDH_CMD_INHIBIT_DAT_POS)
+#define SDH_CMD_INHIBIT_DAT_UMSK (~(((1U << SDH_CMD_INHIBIT_DAT_LEN) - 1) << SDH_CMD_INHIBIT_DAT_POS))
+#define SDH__DAT_ACTIVE SDH__DAT_ACTIVE
+#define SDH__DAT_ACTIVE_POS (2U)
+#define SDH__DAT_ACTIVE_LEN (1U)
+#define SDH__DAT_ACTIVE_MSK (((1U << SDH__DAT_ACTIVE_LEN) - 1) << SDH__DAT_ACTIVE_POS)
+#define SDH__DAT_ACTIVE_UMSK (~(((1U << SDH__DAT_ACTIVE_LEN) - 1) << SDH__DAT_ACTIVE_POS))
+#define SDH_RETUNING_REQ SDH_RETUNING_REQ
+#define SDH_RETUNING_REQ_POS (3U)
+#define SDH_RETUNING_REQ_LEN (1U)
+#define SDH_RETUNING_REQ_MSK (((1U << SDH_RETUNING_REQ_LEN) - 1) << SDH_RETUNING_REQ_POS)
+#define SDH_RETUNING_REQ_UMSK (~(((1U << SDH_RETUNING_REQ_LEN) - 1) << SDH_RETUNING_REQ_POS))
+#define SDH_TX_ACTIVE SDH_TX_ACTIVE
+#define SDH_TX_ACTIVE_POS (8U)
+#define SDH_TX_ACTIVE_LEN (1U)
+#define SDH_TX_ACTIVE_MSK (((1U << SDH_TX_ACTIVE_LEN) - 1) << SDH_TX_ACTIVE_POS)
+#define SDH_TX_ACTIVE_UMSK (~(((1U << SDH_TX_ACTIVE_LEN) - 1) << SDH_TX_ACTIVE_POS))
+#define SDH_RX_ACTIVE SDH_RX_ACTIVE
+#define SDH_RX_ACTIVE_POS (9U)
+#define SDH_RX_ACTIVE_LEN (1U)
+#define SDH_RX_ACTIVE_MSK (((1U << SDH_RX_ACTIVE_LEN) - 1) << SDH_RX_ACTIVE_POS)
+#define SDH_RX_ACTIVE_UMSK (~(((1U << SDH_RX_ACTIVE_LEN) - 1) << SDH_RX_ACTIVE_POS))
+#define SDH_BUFFER_WR_EN SDH_BUFFER_WR_EN
+#define SDH_BUFFER_WR_EN_POS (10U)
+#define SDH_BUFFER_WR_EN_LEN (1U)
+#define SDH_BUFFER_WR_EN_MSK (((1U << SDH_BUFFER_WR_EN_LEN) - 1) << SDH_BUFFER_WR_EN_POS)
+#define SDH_BUFFER_WR_EN_UMSK (~(((1U << SDH_BUFFER_WR_EN_LEN) - 1) << SDH_BUFFER_WR_EN_POS))
+#define SDH_BUFFER_RD_EN SDH_BUFFER_RD_EN
+#define SDH_BUFFER_RD_EN_POS (11U)
+#define SDH_BUFFER_RD_EN_LEN (1U)
+#define SDH_BUFFER_RD_EN_MSK (((1U << SDH_BUFFER_RD_EN_LEN) - 1) << SDH_BUFFER_RD_EN_POS)
+#define SDH_BUFFER_RD_EN_UMSK (~(((1U << SDH_BUFFER_RD_EN_LEN) - 1) << SDH_BUFFER_RD_EN_POS))
+
+/* 0x26 : Present State Register 2 */
+#define SDH_SD_PRESENT_STATE_2_OFFSET (0x26)
+#define SDH_CARD_INSERTED SDH_CARD_INSERTED
+#define SDH_CARD_INSERTED_POS (0U)
+#define SDH_CARD_INSERTED_LEN (1U)
+#define SDH_CARD_INSERTED_MSK (((1U << SDH_CARD_INSERTED_LEN) - 1) << SDH_CARD_INSERTED_POS)
+#define SDH_CARD_INSERTED_UMSK (~(((1U << SDH_CARD_INSERTED_LEN) - 1) << SDH_CARD_INSERTED_POS))
+#define SDH_CARD_STABLE SDH_CARD_STABLE
+#define SDH_CARD_STABLE_POS (1U)
+#define SDH_CARD_STABLE_LEN (1U)
+#define SDH_CARD_STABLE_MSK (((1U << SDH_CARD_STABLE_LEN) - 1) << SDH_CARD_STABLE_POS)
+#define SDH_CARD_STABLE_UMSK (~(((1U << SDH_CARD_STABLE_LEN) - 1) << SDH_CARD_STABLE_POS))
+#define SDH_CARD_DET SDH_CARD_DET
+#define SDH_CARD_DET_POS (2U)
+#define SDH_CARD_DET_LEN (1U)
+#define SDH_CARD_DET_MSK (((1U << SDH_CARD_DET_LEN) - 1) << SDH_CARD_DET_POS)
+#define SDH_CARD_DET_UMSK (~(((1U << SDH_CARD_DET_LEN) - 1) << SDH_CARD_DET_POS))
+#define SDH_WRITE_PROT SDH_WRITE_PROT
+#define SDH_WRITE_PROT_POS (3U)
+#define SDH_WRITE_PROT_LEN (1U)
+#define SDH_WRITE_PROT_MSK (((1U << SDH_WRITE_PROT_LEN) - 1) << SDH_WRITE_PROT_POS)
+#define SDH_WRITE_PROT_UMSK (~(((1U << SDH_WRITE_PROT_LEN) - 1) << SDH_WRITE_PROT_POS))
+#define SDH_DAT_LEVEL SDH_DAT_LEVEL
+#define SDH_DAT_LEVEL_POS (4U)
+#define SDH_DAT_LEVEL_LEN (4U)
+#define SDH_DAT_LEVEL_MSK (((1U << SDH_DAT_LEVEL_LEN) - 1) << SDH_DAT_LEVEL_POS)
+#define SDH_DAT_LEVEL_UMSK (~(((1U << SDH_DAT_LEVEL_LEN) - 1) << SDH_DAT_LEVEL_POS))
+#define SDH_CMD_LEVEL SDH_CMD_LEVEL
+#define SDH_CMD_LEVEL_POS (8U)
+#define SDH_CMD_LEVEL_LEN (1U)
+#define SDH_CMD_LEVEL_MSK (((1U << SDH_CMD_LEVEL_LEN) - 1) << SDH_CMD_LEVEL_POS)
+#define SDH_CMD_LEVEL_UMSK (~(((1U << SDH_CMD_LEVEL_LEN) - 1) << SDH_CMD_LEVEL_POS))
+
+/* 0x28 : Host Control Register */
+#define SDH_SD_HOST_CTRL_OFFSET (0x28)
+#define SDH_LED_CTRL SDH_LED_CTRL
+#define SDH_LED_CTRL_POS (0U)
+#define SDH_LED_CTRL_LEN (1U)
+#define SDH_LED_CTRL_MSK (((1U << SDH_LED_CTRL_LEN) - 1) << SDH_LED_CTRL_POS)
+#define SDH_LED_CTRL_UMSK (~(((1U << SDH_LED_CTRL_LEN) - 1) << SDH_LED_CTRL_POS))
+#define SDH_DATA_WIDTH SDH_DATA_WIDTH
+#define SDH_DATA_WIDTH_POS (1U)
+#define SDH_DATA_WIDTH_LEN (1U)
+#define SDH_DATA_WIDTH_MSK (((1U << SDH_DATA_WIDTH_LEN) - 1) << SDH_DATA_WIDTH_POS)
+#define SDH_DATA_WIDTH_UMSK (~(((1U << SDH_DATA_WIDTH_LEN) - 1) << SDH_DATA_WIDTH_POS))
+#define SDH_HI_SPEED_EN SDH_HI_SPEED_EN
+#define SDH_HI_SPEED_EN_POS (2U)
+#define SDH_HI_SPEED_EN_LEN (1U)
+#define SDH_HI_SPEED_EN_MSK (((1U << SDH_HI_SPEED_EN_LEN) - 1) << SDH_HI_SPEED_EN_POS)
+#define SDH_HI_SPEED_EN_UMSK (~(((1U << SDH_HI_SPEED_EN_LEN) - 1) << SDH_HI_SPEED_EN_POS))
+#define SDH_DMA_SEL SDH_DMA_SEL
+#define SDH_DMA_SEL_POS (3U)
+#define SDH_DMA_SEL_LEN (2U)
+#define SDH_DMA_SEL_MSK (((1U << SDH_DMA_SEL_LEN) - 1) << SDH_DMA_SEL_POS)
+#define SDH_DMA_SEL_UMSK (~(((1U << SDH_DMA_SEL_LEN) - 1) << SDH_DMA_SEL_POS))
+#define SDH_EX_DATA_WIDTH SDH_EX_DATA_WIDTH
+#define SDH_EX_DATA_WIDTH_POS (5U)
+#define SDH_EX_DATA_WIDTH_LEN (1U)
+#define SDH_EX_DATA_WIDTH_MSK (((1U << SDH_EX_DATA_WIDTH_LEN) - 1) << SDH_EX_DATA_WIDTH_POS)
+#define SDH_EX_DATA_WIDTH_UMSK (~(((1U << SDH_EX_DATA_WIDTH_LEN) - 1) << SDH_EX_DATA_WIDTH_POS))
+#define SDH_CARD_DET_L SDH_CARD_DET_L
+#define SDH_CARD_DET_L_POS (6U)
+#define SDH_CARD_DET_L_LEN (1U)
+#define SDH_CARD_DET_L_MSK (((1U << SDH_CARD_DET_L_LEN) - 1) << SDH_CARD_DET_L_POS)
+#define SDH_CARD_DET_L_UMSK (~(((1U << SDH_CARD_DET_L_LEN) - 1) << SDH_CARD_DET_L_POS))
+#define SDH_CARD_DET_S SDH_CARD_DET_S
+#define SDH_CARD_DET_S_POS (7U)
+#define SDH_CARD_DET_S_LEN (1U)
+#define SDH_CARD_DET_S_MSK (((1U << SDH_CARD_DET_S_LEN) - 1) << SDH_CARD_DET_S_POS)
+#define SDH_CARD_DET_S_UMSK (~(((1U << SDH_CARD_DET_S_LEN) - 1) << SDH_CARD_DET_S_POS))
+#define SDH_SD_BUS_POWER SDH_SD_BUS_POWER
+#define SDH_SD_BUS_POWER_POS (8U)
+#define SDH_SD_BUS_POWER_LEN (1U)
+#define SDH_SD_BUS_POWER_MSK (((1U << SDH_SD_BUS_POWER_LEN) - 1) << SDH_SD_BUS_POWER_POS)
+#define SDH_SD_BUS_POWER_UMSK (~(((1U << SDH_SD_BUS_POWER_LEN) - 1) << SDH_SD_BUS_POWER_POS))
+#define SDH_SD_BUS_VLT SDH_SD_BUS_VLT
+#define SDH_SD_BUS_VLT_POS (9U)
+#define SDH_SD_BUS_VLT_LEN (3U)
+#define SDH_SD_BUS_VLT_MSK (((1U << SDH_SD_BUS_VLT_LEN) - 1) << SDH_SD_BUS_VLT_POS)
+#define SDH_SD_BUS_VLT_UMSK (~(((1U << SDH_SD_BUS_VLT_LEN) - 1) << SDH_SD_BUS_VLT_POS))
+
+/* 0x2A : Block Gap Control Register */
+#define SDH_SD_BLOCK_GAP_CTRL_OFFSET (0x2A)
+#define SDH_STOP_AT_BLOCK_GAP_REQ SDH_STOP_AT_BLOCK_GAP_REQ
+#define SDH_STOP_AT_BLOCK_GAP_REQ_POS (0U)
+#define SDH_STOP_AT_BLOCK_GAP_REQ_LEN (1U)
+#define SDH_STOP_AT_BLOCK_GAP_REQ_MSK (((1U << SDH_STOP_AT_BLOCK_GAP_REQ_LEN) - 1) << SDH_STOP_AT_BLOCK_GAP_REQ_POS)
+#define SDH_STOP_AT_BLOCK_GAP_REQ_UMSK (~(((1U << SDH_STOP_AT_BLOCK_GAP_REQ_LEN) - 1) << SDH_STOP_AT_BLOCK_GAP_REQ_POS))
+#define SDH_CONT_REQ SDH_CONT_REQ
+#define SDH_CONT_REQ_POS (1U)
+#define SDH_CONT_REQ_LEN (1U)
+#define SDH_CONT_REQ_MSK (((1U << SDH_CONT_REQ_LEN) - 1) << SDH_CONT_REQ_POS)
+#define SDH_CONT_REQ_UMSK (~(((1U << SDH_CONT_REQ_LEN) - 1) << SDH_CONT_REQ_POS))
+#define SDH_RD_WAIT_CTL SDH_RD_WAIT_CTL
+#define SDH_RD_WAIT_CTL_POS (2U)
+#define SDH_RD_WAIT_CTL_LEN (1U)
+#define SDH_RD_WAIT_CTL_MSK (((1U << SDH_RD_WAIT_CTL_LEN) - 1) << SDH_RD_WAIT_CTL_POS)
+#define SDH_RD_WAIT_CTL_UMSK (~(((1U << SDH_RD_WAIT_CTL_LEN) - 1) << SDH_RD_WAIT_CTL_POS))
+#define SDH_INT_BLK_GAP SDH_INT_BLK_GAP
+#define SDH_INT_BLK_GAP_POS (3U)
+#define SDH_INT_BLK_GAP_LEN (1U)
+#define SDH_INT_BLK_GAP_MSK (((1U << SDH_INT_BLK_GAP_LEN) - 1) << SDH_INT_BLK_GAP_POS)
+#define SDH_INT_BLK_GAP_UMSK (~(((1U << SDH_INT_BLK_GAP_LEN) - 1) << SDH_INT_BLK_GAP_POS))
+#define SDH_W_CARD_INT SDH_W_CARD_INT
+#define SDH_W_CARD_INT_POS (8U)
+#define SDH_W_CARD_INT_LEN (1U)
+#define SDH_W_CARD_INT_MSK (((1U << SDH_W_CARD_INT_LEN) - 1) << SDH_W_CARD_INT_POS)
+#define SDH_W_CARD_INT_UMSK (~(((1U << SDH_W_CARD_INT_LEN) - 1) << SDH_W_CARD_INT_POS))
+#define SDH_W_INSERTION SDH_W_INSERTION
+#define SDH_W_INSERTION_POS (9U)
+#define SDH_W_INSERTION_LEN (1U)
+#define SDH_W_INSERTION_MSK (((1U << SDH_W_INSERTION_LEN) - 1) << SDH_W_INSERTION_POS)
+#define SDH_W_INSERTION_UMSK (~(((1U << SDH_W_INSERTION_LEN) - 1) << SDH_W_INSERTION_POS))
+#define SDH_W_REMOVAL SDH_W_REMOVAL
+#define SDH_W_REMOVAL_POS (10U)
+#define SDH_W_REMOVAL_LEN (1U)
+#define SDH_W_REMOVAL_MSK (((1U << SDH_W_REMOVAL_LEN) - 1) << SDH_W_REMOVAL_POS)
+#define SDH_W_REMOVAL_UMSK (~(((1U << SDH_W_REMOVAL_LEN) - 1) << SDH_W_REMOVAL_POS))
+
+/* 0x2C : Clock Control Register */
+#define SDH_SD_CLOCK_CTRL_OFFSET (0x2C)
+#define SDH_INT_CLK_EN SDH_INT_CLK_EN
+#define SDH_INT_CLK_EN_POS (0U)
+#define SDH_INT_CLK_EN_LEN (1U)
+#define SDH_INT_CLK_EN_MSK (((1U << SDH_INT_CLK_EN_LEN) - 1) << SDH_INT_CLK_EN_POS)
+#define SDH_INT_CLK_EN_UMSK (~(((1U << SDH_INT_CLK_EN_LEN) - 1) << SDH_INT_CLK_EN_POS))
+#define SDH_INT_CLK_STABLE SDH_INT_CLK_STABLE
+#define SDH_INT_CLK_STABLE_POS (1U)
+#define SDH_INT_CLK_STABLE_LEN (1U)
+#define SDH_INT_CLK_STABLE_MSK (((1U << SDH_INT_CLK_STABLE_LEN) - 1) << SDH_INT_CLK_STABLE_POS)
+#define SDH_INT_CLK_STABLE_UMSK (~(((1U << SDH_INT_CLK_STABLE_LEN) - 1) << SDH_INT_CLK_STABLE_POS))
+#define SDH_SD_CLK_EN SDH_SD_CLK_EN
+#define SDH_SD_CLK_EN_POS (2U)
+#define SDH_SD_CLK_EN_LEN (1U)
+#define SDH_SD_CLK_EN_MSK (((1U << SDH_SD_CLK_EN_LEN) - 1) << SDH_SD_CLK_EN_POS)
+#define SDH_SD_CLK_EN_UMSK (~(((1U << SDH_SD_CLK_EN_LEN) - 1) << SDH_SD_CLK_EN_POS))
+#define SDH_CLK_GEN_SEL SDH_CLK_GEN_SEL
+#define SDH_CLK_GEN_SEL_POS (5U)
+#define SDH_CLK_GEN_SEL_LEN (1U)
+#define SDH_CLK_GEN_SEL_MSK (((1U << SDH_CLK_GEN_SEL_LEN) - 1) << SDH_CLK_GEN_SEL_POS)
+#define SDH_CLK_GEN_SEL_UMSK (~(((1U << SDH_CLK_GEN_SEL_LEN) - 1) << SDH_CLK_GEN_SEL_POS))
+#define SDH_SD_FREQ_SEL_HI SDH_SD_FREQ_SEL_HI
+#define SDH_SD_FREQ_SEL_HI_POS (6U)
+#define SDH_SD_FREQ_SEL_HI_LEN (2U)
+#define SDH_SD_FREQ_SEL_HI_MSK (((1U << SDH_SD_FREQ_SEL_HI_LEN) - 1) << SDH_SD_FREQ_SEL_HI_POS)
+#define SDH_SD_FREQ_SEL_HI_UMSK (~(((1U << SDH_SD_FREQ_SEL_HI_LEN) - 1) << SDH_SD_FREQ_SEL_HI_POS))
+#define SDH_SD_FREQ_SEL_LO SDH_SD_FREQ_SEL_LO
+#define SDH_SD_FREQ_SEL_LO_POS (8U)
+#define SDH_SD_FREQ_SEL_LO_LEN (8U)
+#define SDH_SD_FREQ_SEL_LO_MSK (((1U << SDH_SD_FREQ_SEL_LO_LEN) - 1) << SDH_SD_FREQ_SEL_LO_POS)
+#define SDH_SD_FREQ_SEL_LO_UMSK (~(((1U << SDH_SD_FREQ_SEL_LO_LEN) - 1) << SDH_SD_FREQ_SEL_LO_POS))
+
+/* 0x2E : Timeout Control/Software Reset Register */
+#define SDH_SD_TIMEOUT_CTRL_SW_RESET_OFFSET (0x2E)
+#define SDH_TIMEOUT_VALUE SDH_TIMEOUT_VALUE
+#define SDH_TIMEOUT_VALUE_POS (0U)
+#define SDH_TIMEOUT_VALUE_LEN (4U)
+#define SDH_TIMEOUT_VALUE_MSK (((1U << SDH_TIMEOUT_VALUE_LEN) - 1) << SDH_TIMEOUT_VALUE_POS)
+#define SDH_TIMEOUT_VALUE_UMSK (~(((1U << SDH_TIMEOUT_VALUE_LEN) - 1) << SDH_TIMEOUT_VALUE_POS))
+#define SDH_SW_RST_ALL SDH_SW_RST_ALL
+#define SDH_SW_RST_ALL_POS (8U)
+#define SDH_SW_RST_ALL_LEN (1U)
+#define SDH_SW_RST_ALL_MSK (((1U << SDH_SW_RST_ALL_LEN) - 1) << SDH_SW_RST_ALL_POS)
+#define SDH_SW_RST_ALL_UMSK (~(((1U << SDH_SW_RST_ALL_LEN) - 1) << SDH_SW_RST_ALL_POS))
+#define SDH_SW_RST_CMD SDH_SW_RST_CMD
+#define SDH_SW_RST_CMD_POS (9U)
+#define SDH_SW_RST_CMD_LEN (1U)
+#define SDH_SW_RST_CMD_MSK (((1U << SDH_SW_RST_CMD_LEN) - 1) << SDH_SW_RST_CMD_POS)
+#define SDH_SW_RST_CMD_UMSK (~(((1U << SDH_SW_RST_CMD_LEN) - 1) << SDH_SW_RST_CMD_POS))
+#define SDH_SW_RST_DAT SDH_SW_RST_DAT
+#define SDH_SW_RST_DAT_POS (10U)
+#define SDH_SW_RST_DAT_LEN (1U)
+#define SDH_SW_RST_DAT_MSK (((1U << SDH_SW_RST_DAT_LEN) - 1) << SDH_SW_RST_DAT_POS)
+#define SDH_SW_RST_DAT_UMSK (~(((1U << SDH_SW_RST_DAT_LEN) - 1) << SDH_SW_RST_DAT_POS))
+
+/* 0x30 : Normal Interrupt Status Register */
+#define SDH_SD_NORMAL_INT_STATUS_OFFSET (0x30)
+#define SDH_CMD_COMPLETE SDH_CMD_COMPLETE
+#define SDH_CMD_COMPLETE_POS (0U)
+#define SDH_CMD_COMPLETE_LEN (1U)
+#define SDH_CMD_COMPLETE_MSK (((1U << SDH_CMD_COMPLETE_LEN) - 1) << SDH_CMD_COMPLETE_POS)
+#define SDH_CMD_COMPLETE_UMSK (~(((1U << SDH_CMD_COMPLETE_LEN) - 1) << SDH_CMD_COMPLETE_POS))
+#define SDH_XFER_COMPLETE SDH_XFER_COMPLETE
+#define SDH_XFER_COMPLETE_POS (1U)
+#define SDH_XFER_COMPLETE_LEN (1U)
+#define SDH_XFER_COMPLETE_MSK (((1U << SDH_XFER_COMPLETE_LEN) - 1) << SDH_XFER_COMPLETE_POS)
+#define SDH_XFER_COMPLETE_UMSK (~(((1U << SDH_XFER_COMPLETE_LEN) - 1) << SDH_XFER_COMPLETE_POS))
+#define SDH_BLOCK_GAP_EVT SDH_BLOCK_GAP_EVT
+#define SDH_BLOCK_GAP_EVT_POS (2U)
+#define SDH_BLOCK_GAP_EVT_LEN (1U)
+#define SDH_BLOCK_GAP_EVT_MSK (((1U << SDH_BLOCK_GAP_EVT_LEN) - 1) << SDH_BLOCK_GAP_EVT_POS)
+#define SDH_BLOCK_GAP_EVT_UMSK (~(((1U << SDH_BLOCK_GAP_EVT_LEN) - 1) << SDH_BLOCK_GAP_EVT_POS))
+#define SDH_DMA_INT SDH_DMA_INT
+#define SDH_DMA_INT_POS (3U)
+#define SDH_DMA_INT_LEN (1U)
+#define SDH_DMA_INT_MSK (((1U << SDH_DMA_INT_LEN) - 1) << SDH_DMA_INT_POS)
+#define SDH_DMA_INT_UMSK (~(((1U << SDH_DMA_INT_LEN) - 1) << SDH_DMA_INT_POS))
+#define SDH_TX_RDY SDH_TX_RDY
+#define SDH_TX_RDY_POS (4U)
+#define SDH_TX_RDY_LEN (1U)
+#define SDH_TX_RDY_MSK (((1U << SDH_TX_RDY_LEN) - 1) << SDH_TX_RDY_POS)
+#define SDH_TX_RDY_UMSK (~(((1U << SDH_TX_RDY_LEN) - 1) << SDH_TX_RDY_POS))
+#define SDH_RX_RDY SDH_RX_RDY
+#define SDH_RX_RDY_POS (5U)
+#define SDH_RX_RDY_LEN (1U)
+#define SDH_RX_RDY_MSK (((1U << SDH_RX_RDY_LEN) - 1) << SDH_RX_RDY_POS)
+#define SDH_RX_RDY_UMSK (~(((1U << SDH_RX_RDY_LEN) - 1) << SDH_RX_RDY_POS))
+#define SDH_CARD_INS_INT SDH_CARD_INS_INT
+#define SDH_CARD_INS_INT_POS (6U)
+#define SDH_CARD_INS_INT_LEN (1U)
+#define SDH_CARD_INS_INT_MSK (((1U << SDH_CARD_INS_INT_LEN) - 1) << SDH_CARD_INS_INT_POS)
+#define SDH_CARD_INS_INT_UMSK (~(((1U << SDH_CARD_INS_INT_LEN) - 1) << SDH_CARD_INS_INT_POS))
+#define SDH_CARD_REM_INT SDH_CARD_REM_INT
+#define SDH_CARD_REM_INT_POS (7U)
+#define SDH_CARD_REM_INT_LEN (1U)
+#define SDH_CARD_REM_INT_MSK (((1U << SDH_CARD_REM_INT_LEN) - 1) << SDH_CARD_REM_INT_POS)
+#define SDH_CARD_REM_INT_UMSK (~(((1U << SDH_CARD_REM_INT_LEN) - 1) << SDH_CARD_REM_INT_POS))
+#define SDH_CARD_INT SDH_CARD_INT
+#define SDH_CARD_INT_POS (8U)
+#define SDH_CARD_INT_LEN (1U)
+#define SDH_CARD_INT_MSK (((1U << SDH_CARD_INT_LEN) - 1) << SDH_CARD_INT_POS)
+#define SDH_CARD_INT_UMSK (~(((1U << SDH_CARD_INT_LEN) - 1) << SDH_CARD_INT_POS))
+#define SDH_INT_A SDH_INT_A
+#define SDH_INT_A_POS (9U)
+#define SDH_INT_A_LEN (1U)
+#define SDH_INT_A_MSK (((1U << SDH_INT_A_LEN) - 1) << SDH_INT_A_POS)
+#define SDH_INT_A_UMSK (~(((1U << SDH_INT_A_LEN) - 1) << SDH_INT_A_POS))
+#define SDH_INT_B SDH_INT_B
+#define SDH_INT_B_POS (10U)
+#define SDH_INT_B_LEN (1U)
+#define SDH_INT_B_MSK (((1U << SDH_INT_B_LEN) - 1) << SDH_INT_B_POS)
+#define SDH_INT_B_UMSK (~(((1U << SDH_INT_B_LEN) - 1) << SDH_INT_B_POS))
+#define SDH_INT_C SDH_INT_C
+#define SDH_INT_C_POS (11U)
+#define SDH_INT_C_LEN (1U)
+#define SDH_INT_C_MSK (((1U << SDH_INT_C_LEN) - 1) << SDH_INT_C_POS)
+#define SDH_INT_C_UMSK (~(((1U << SDH_INT_C_LEN) - 1) << SDH_INT_C_POS))
+#define SDH_RETUNING_INT SDH_RETUNING_INT
+#define SDH_RETUNING_INT_POS (12U)
+#define SDH_RETUNING_INT_LEN (1U)
+#define SDH_RETUNING_INT_MSK (((1U << SDH_RETUNING_INT_LEN) - 1) << SDH_RETUNING_INT_POS)
+#define SDH_RETUNING_INT_UMSK (~(((1U << SDH_RETUNING_INT_LEN) - 1) << SDH_RETUNING_INT_POS))
+#define SDH_ERR_INT SDH_ERR_INT
+#define SDH_ERR_INT_POS (15U)
+#define SDH_ERR_INT_LEN (1U)
+#define SDH_ERR_INT_MSK (((1U << SDH_ERR_INT_LEN) - 1) << SDH_ERR_INT_POS)
+#define SDH_ERR_INT_UMSK (~(((1U << SDH_ERR_INT_LEN) - 1) << SDH_ERR_INT_POS))
+
+/* 0x32 : Error Interrupt Status Register */
+#define SDH_SD_ERROR_INT_STATUS_OFFSET (0x32)
+#define SDH_CMD_TIMEOUT_ERR SDH_CMD_TIMEOUT_ERR
+#define SDH_CMD_TIMEOUT_ERR_POS (0U)
+#define SDH_CMD_TIMEOUT_ERR_LEN (1U)
+#define SDH_CMD_TIMEOUT_ERR_MSK (((1U << SDH_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_POS)
+#define SDH_CMD_TIMEOUT_ERR_UMSK (~(((1U << SDH_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_POS))
+#define SDH_CMD_CRC_ERR SDH_CMD_CRC_ERR
+#define SDH_CMD_CRC_ERR_POS (1U)
+#define SDH_CMD_CRC_ERR_LEN (1U)
+#define SDH_CMD_CRC_ERR_MSK (((1U << SDH_CMD_CRC_ERR_LEN) - 1) << SDH_CMD_CRC_ERR_POS)
+#define SDH_CMD_CRC_ERR_UMSK (~(((1U << SDH_CMD_CRC_ERR_LEN) - 1) << SDH_CMD_CRC_ERR_POS))
+#define SDH_CMD_END_BIT_ERR SDH_CMD_END_BIT_ERR
+#define SDH_CMD_END_BIT_ERR_POS (2U)
+#define SDH_CMD_END_BIT_ERR_LEN (1U)
+#define SDH_CMD_END_BIT_ERR_MSK (((1U << SDH_CMD_END_BIT_ERR_LEN) - 1) << SDH_CMD_END_BIT_ERR_POS)
+#define SDH_CMD_END_BIT_ERR_UMSK (~(((1U << SDH_CMD_END_BIT_ERR_LEN) - 1) << SDH_CMD_END_BIT_ERR_POS))
+#define SDH_CMD_INDEX_ERR SDH_CMD_INDEX_ERR
+#define SDH_CMD_INDEX_ERR_POS (3U)
+#define SDH_CMD_INDEX_ERR_LEN (1U)
+#define SDH_CMD_INDEX_ERR_MSK (((1U << SDH_CMD_INDEX_ERR_LEN) - 1) << SDH_CMD_INDEX_ERR_POS)
+#define SDH_CMD_INDEX_ERR_UMSK (~(((1U << SDH_CMD_INDEX_ERR_LEN) - 1) << SDH_CMD_INDEX_ERR_POS))
+#define SDH_DATA_TIMEOUT_ERR SDH_DATA_TIMEOUT_ERR
+#define SDH_DATA_TIMEOUT_ERR_POS (4U)
+#define SDH_DATA_TIMEOUT_ERR_LEN (1U)
+#define SDH_DATA_TIMEOUT_ERR_MSK (((1U << SDH_DATA_TIMEOUT_ERR_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_POS)
+#define SDH_DATA_TIMEOUT_ERR_UMSK (~(((1U << SDH_DATA_TIMEOUT_ERR_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_POS))
+#define SDH_RD_DATA_CRC_ERR SDH_RD_DATA_CRC_ERR
+#define SDH_RD_DATA_CRC_ERR_POS (5U)
+#define SDH_RD_DATA_CRC_ERR_LEN (1U)
+#define SDH_RD_DATA_CRC_ERR_MSK (((1U << SDH_RD_DATA_CRC_ERR_LEN) - 1) << SDH_RD_DATA_CRC_ERR_POS)
+#define SDH_RD_DATA_CRC_ERR_UMSK (~(((1U << SDH_RD_DATA_CRC_ERR_LEN) - 1) << SDH_RD_DATA_CRC_ERR_POS))
+#define SDH_RD_DATA_END_BIT_ERR SDH_RD_DATA_END_BIT_ERR
+#define SDH_RD_DATA_END_BIT_ERR_POS (6U)
+#define SDH_RD_DATA_END_BIT_ERR_LEN (1U)
+#define SDH_RD_DATA_END_BIT_ERR_MSK (((1U << SDH_RD_DATA_END_BIT_ERR_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_POS)
+#define SDH_RD_DATA_END_BIT_ERR_UMSK (~(((1U << SDH_RD_DATA_END_BIT_ERR_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_POS))
+#define SDH_CUR_LIMIT_ERR SDH_CUR_LIMIT_ERR
+#define SDH_CUR_LIMIT_ERR_POS (7U)
+#define SDH_CUR_LIMIT_ERR_LEN (1U)
+#define SDH_CUR_LIMIT_ERR_MSK (((1U << SDH_CUR_LIMIT_ERR_LEN) - 1) << SDH_CUR_LIMIT_ERR_POS)
+#define SDH_CUR_LIMIT_ERR_UMSK (~(((1U << SDH_CUR_LIMIT_ERR_LEN) - 1) << SDH_CUR_LIMIT_ERR_POS))
+#define SDH_AUTO_CMD12_ERR SDH_AUTO_CMD12_ERR
+#define SDH_AUTO_CMD12_ERR_POS (8U)
+#define SDH_AUTO_CMD12_ERR_LEN (1U)
+#define SDH_AUTO_CMD12_ERR_MSK (((1U << SDH_AUTO_CMD12_ERR_LEN) - 1) << SDH_AUTO_CMD12_ERR_POS)
+#define SDH_AUTO_CMD12_ERR_UMSK (~(((1U << SDH_AUTO_CMD12_ERR_LEN) - 1) << SDH_AUTO_CMD12_ERR_POS))
+#define SDH_ADMA_ERR SDH_ADMA_ERR
+#define SDH_ADMA_ERR_POS (9U)
+#define SDH_ADMA_ERR_LEN (1U)
+#define SDH_ADMA_ERR_MSK (((1U << SDH_ADMA_ERR_LEN) - 1) << SDH_ADMA_ERR_POS)
+#define SDH_ADMA_ERR_UMSK (~(((1U << SDH_ADMA_ERR_LEN) - 1) << SDH_ADMA_ERR_POS))
+#define SDH_TUNE_ERR SDH_TUNE_ERR
+#define SDH_TUNE_ERR_POS (10U)
+#define SDH_TUNE_ERR_LEN (1U)
+#define SDH_TUNE_ERR_MSK (((1U << SDH_TUNE_ERR_LEN) - 1) << SDH_TUNE_ERR_POS)
+#define SDH_TUNE_ERR_UMSK (~(((1U << SDH_TUNE_ERR_LEN) - 1) << SDH_TUNE_ERR_POS))
+#define SDH_SPI_ERR SDH_SPI_ERR
+#define SDH_SPI_ERR_POS (12U)
+#define SDH_SPI_ERR_LEN (1U)
+#define SDH_SPI_ERR_MSK (((1U << SDH_SPI_ERR_LEN) - 1) << SDH_SPI_ERR_POS)
+#define SDH_SPI_ERR_UMSK (~(((1U << SDH_SPI_ERR_LEN) - 1) << SDH_SPI_ERR_POS))
+#define SDH_AXI_RESP_ERR SDH_AXI_RESP_ERR
+#define SDH_AXI_RESP_ERR_POS (13U)
+#define SDH_AXI_RESP_ERR_LEN (1U)
+#define SDH_AXI_RESP_ERR_MSK (((1U << SDH_AXI_RESP_ERR_LEN) - 1) << SDH_AXI_RESP_ERR_POS)
+#define SDH_AXI_RESP_ERR_UMSK (~(((1U << SDH_AXI_RESP_ERR_LEN) - 1) << SDH_AXI_RESP_ERR_POS))
+#define SDH_CPL_TIMEOUT_ERR SDH_CPL_TIMEOUT_ERR
+#define SDH_CPL_TIMEOUT_ERR_POS (14U)
+#define SDH_CPL_TIMEOUT_ERR_LEN (1U)
+#define SDH_CPL_TIMEOUT_ERR_MSK (((1U << SDH_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_POS)
+#define SDH_CPL_TIMEOUT_ERR_UMSK (~(((1U << SDH_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_POS))
+#define SDH_CRC_STATUS_ERR SDH_CRC_STATUS_ERR
+#define SDH_CRC_STATUS_ERR_POS (15U)
+#define SDH_CRC_STATUS_ERR_LEN (1U)
+#define SDH_CRC_STATUS_ERR_MSK (((1U << SDH_CRC_STATUS_ERR_LEN) - 1) << SDH_CRC_STATUS_ERR_POS)
+#define SDH_CRC_STATUS_ERR_UMSK (~(((1U << SDH_CRC_STATUS_ERR_LEN) - 1) << SDH_CRC_STATUS_ERR_POS))
+
+/* 0x34 : Normal Interrupt Status Enable Register */
+#define SDH_SD_NORMAL_INT_STATUS_EN_OFFSET (0x34)
+#define SDH_CMD_COMPLETE_EN SDH_CMD_COMPLETE_EN
+#define SDH_CMD_COMPLETE_EN_POS (0U)
+#define SDH_CMD_COMPLETE_EN_LEN (1U)
+#define SDH_CMD_COMPLETE_EN_MSK (((1U << SDH_CMD_COMPLETE_EN_LEN) - 1) << SDH_CMD_COMPLETE_EN_POS)
+#define SDH_CMD_COMPLETE_EN_UMSK (~(((1U << SDH_CMD_COMPLETE_EN_LEN) - 1) << SDH_CMD_COMPLETE_EN_POS))
+#define SDH_XFER_COMPLETE_EN SDH_XFER_COMPLETE_EN
+#define SDH_XFER_COMPLETE_EN_POS (1U)
+#define SDH_XFER_COMPLETE_EN_LEN (1U)
+#define SDH_XFER_COMPLETE_EN_MSK (((1U << SDH_XFER_COMPLETE_EN_LEN) - 1) << SDH_XFER_COMPLETE_EN_POS)
+#define SDH_XFER_COMPLETE_EN_UMSK (~(((1U << SDH_XFER_COMPLETE_EN_LEN) - 1) << SDH_XFER_COMPLETE_EN_POS))
+#define SDH_BLOCK_GAP_EVT_EN SDH_BLOCK_GAP_EVT_EN
+#define SDH_BLOCK_GAP_EVT_EN_POS (2U)
+#define SDH_BLOCK_GAP_EVT_EN_LEN (1U)
+#define SDH_BLOCK_GAP_EVT_EN_MSK (((1U << SDH_BLOCK_GAP_EVT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_EN_POS)
+#define SDH_BLOCK_GAP_EVT_EN_UMSK (~(((1U << SDH_BLOCK_GAP_EVT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_EN_POS))
+#define SDH_DMA_INT_EN SDH_DMA_INT_EN
+#define SDH_DMA_INT_EN_POS (3U)
+#define SDH_DMA_INT_EN_LEN (1U)
+#define SDH_DMA_INT_EN_MSK (((1U << SDH_DMA_INT_EN_LEN) - 1) << SDH_DMA_INT_EN_POS)
+#define SDH_DMA_INT_EN_UMSK (~(((1U << SDH_DMA_INT_EN_LEN) - 1) << SDH_DMA_INT_EN_POS))
+#define SDH_TX_RDY_EN SDH_TX_RDY_EN
+#define SDH_TX_RDY_EN_POS (4U)
+#define SDH_TX_RDY_EN_LEN (1U)
+#define SDH_TX_RDY_EN_MSK (((1U << SDH_TX_RDY_EN_LEN) - 1) << SDH_TX_RDY_EN_POS)
+#define SDH_TX_RDY_EN_UMSK (~(((1U << SDH_TX_RDY_EN_LEN) - 1) << SDH_TX_RDY_EN_POS))
+#define SDH_RD_RDY_EN SDH_RD_RDY_EN
+#define SDH_RD_RDY_EN_POS (5U)
+#define SDH_RD_RDY_EN_LEN (1U)
+#define SDH_RD_RDY_EN_MSK (((1U << SDH_RD_RDY_EN_LEN) - 1) << SDH_RD_RDY_EN_POS)
+#define SDH_RD_RDY_EN_UMSK (~(((1U << SDH_RD_RDY_EN_LEN) - 1) << SDH_RD_RDY_EN_POS))
+#define SDH_CARD_INS_EN SDH_CARD_INS_EN
+#define SDH_CARD_INS_EN_POS (6U)
+#define SDH_CARD_INS_EN_LEN (1U)
+#define SDH_CARD_INS_EN_MSK (((1U << SDH_CARD_INS_EN_LEN) - 1) << SDH_CARD_INS_EN_POS)
+#define SDH_CARD_INS_EN_UMSK (~(((1U << SDH_CARD_INS_EN_LEN) - 1) << SDH_CARD_INS_EN_POS))
+#define SDH_CARD_REM_EN SDH_CARD_REM_EN
+#define SDH_CARD_REM_EN_POS (7U)
+#define SDH_CARD_REM_EN_LEN (1U)
+#define SDH_CARD_REM_EN_MSK (((1U << SDH_CARD_REM_EN_LEN) - 1) << SDH_CARD_REM_EN_POS)
+#define SDH_CARD_REM_EN_UMSK (~(((1U << SDH_CARD_REM_EN_LEN) - 1) << SDH_CARD_REM_EN_POS))
+#define SDH_CARD_INT_EN SDH_CARD_INT_EN
+#define SDH_CARD_INT_EN_POS (8U)
+#define SDH_CARD_INT_EN_LEN (1U)
+#define SDH_CARD_INT_EN_MSK (((1U << SDH_CARD_INT_EN_LEN) - 1) << SDH_CARD_INT_EN_POS)
+#define SDH_CARD_INT_EN_UMSK (~(((1U << SDH_CARD_INT_EN_LEN) - 1) << SDH_CARD_INT_EN_POS))
+#define SDH_INT_A_INT_EN SDH_INT_A_INT_EN
+#define SDH_INT_A_INT_EN_POS (9U)
+#define SDH_INT_A_INT_EN_LEN (1U)
+#define SDH_INT_A_INT_EN_MSK (((1U << SDH_INT_A_INT_EN_LEN) - 1) << SDH_INT_A_INT_EN_POS)
+#define SDH_INT_A_INT_EN_UMSK (~(((1U << SDH_INT_A_INT_EN_LEN) - 1) << SDH_INT_A_INT_EN_POS))
+#define SDH_INT_B_INT_EN SDH_INT_B_INT_EN
+#define SDH_INT_B_INT_EN_POS (10U)
+#define SDH_INT_B_INT_EN_LEN (1U)
+#define SDH_INT_B_INT_EN_MSK (((1U << SDH_INT_B_INT_EN_LEN) - 1) << SDH_INT_B_INT_EN_POS)
+#define SDH_INT_B_INT_EN_UMSK (~(((1U << SDH_INT_B_INT_EN_LEN) - 1) << SDH_INT_B_INT_EN_POS))
+#define SDH_INT_C_INT_EN SDH_INT_C_INT_EN
+#define SDH_INT_C_INT_EN_POS (11U)
+#define SDH_INT_C_INT_EN_LEN (1U)
+#define SDH_INT_C_INT_EN_MSK (((1U << SDH_INT_C_INT_EN_LEN) - 1) << SDH_INT_C_INT_EN_POS)
+#define SDH_INT_C_INT_EN_UMSK (~(((1U << SDH_INT_C_INT_EN_LEN) - 1) << SDH_INT_C_INT_EN_POS))
+#define SDH_RETUNE_INT_EN SDH_RETUNE_INT_EN
+#define SDH_RETUNE_INT_EN_POS (12U)
+#define SDH_RETUNE_INT_EN_LEN (1U)
+#define SDH_RETUNE_INT_EN_MSK (((1U << SDH_RETUNE_INT_EN_LEN) - 1) << SDH_RETUNE_INT_EN_POS)
+#define SDH_RETUNE_INT_EN_UMSK (~(((1U << SDH_RETUNE_INT_EN_LEN) - 1) << SDH_RETUNE_INT_EN_POS))
+
+/* 0x36 : Error Interrupt Status Enable Register */
+#define SDH_SD_ERROR_INT_STATUS_EN_OFFSET (0x36)
+#define SDH_CMD_TIMEOUT_ERR_EN SDH_CMD_TIMEOUT_ERR_EN
+#define SDH_CMD_TIMEOUT_ERR_EN_POS (0U)
+#define SDH_CMD_TIMEOUT_ERR_EN_LEN (1U)
+#define SDH_CMD_TIMEOUT_ERR_EN_MSK (((1U << SDH_CMD_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_EN_POS)
+#define SDH_CMD_TIMEOUT_ERR_EN_UMSK (~(((1U << SDH_CMD_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_EN_POS))
+#define SDH_CMD_CRC_ERR_EN SDH_CMD_CRC_ERR_EN
+#define SDH_CMD_CRC_ERR_EN_POS (1U)
+#define SDH_CMD_CRC_ERR_EN_LEN (1U)
+#define SDH_CMD_CRC_ERR_EN_MSK (((1U << SDH_CMD_CRC_ERR_EN_LEN) - 1) << SDH_CMD_CRC_ERR_EN_POS)
+#define SDH_CMD_CRC_ERR_EN_UMSK (~(((1U << SDH_CMD_CRC_ERR_EN_LEN) - 1) << SDH_CMD_CRC_ERR_EN_POS))
+#define SDH_CMD_END_BIT_ERR_EN SDH_CMD_END_BIT_ERR_EN
+#define SDH_CMD_END_BIT_ERR_EN_POS (2U)
+#define SDH_CMD_END_BIT_ERR_EN_LEN (1U)
+#define SDH_CMD_END_BIT_ERR_EN_MSK (((1U << SDH_CMD_END_BIT_ERR_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_EN_POS)
+#define SDH_CMD_END_BIT_ERR_EN_UMSK (~(((1U << SDH_CMD_END_BIT_ERR_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_EN_POS))
+#define SDH_CMD_INDEX_ERR_EN SDH_CMD_INDEX_ERR_EN
+#define SDH_CMD_INDEX_ERR_EN_POS (3U)
+#define SDH_CMD_INDEX_ERR_EN_LEN (1U)
+#define SDH_CMD_INDEX_ERR_EN_MSK (((1U << SDH_CMD_INDEX_ERR_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_EN_POS)
+#define SDH_CMD_INDEX_ERR_EN_UMSK (~(((1U << SDH_CMD_INDEX_ERR_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_EN_POS))
+#define SDH_DATA_TIMEOUT_ERR_EN SDH_DATA_TIMEOUT_ERR_EN
+#define SDH_DATA_TIMEOUT_ERR_EN_POS (4U)
+#define SDH_DATA_TIMEOUT_ERR_EN_LEN (1U)
+#define SDH_DATA_TIMEOUT_ERR_EN_MSK (((1U << SDH_DATA_TIMEOUT_ERR_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_EN_POS)
+#define SDH_DATA_TIMEOUT_ERR_EN_UMSK (~(((1U << SDH_DATA_TIMEOUT_ERR_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_EN_POS))
+#define SDH_RD_DATA_CRC_ERR_EN SDH_RD_DATA_CRC_ERR_EN
+#define SDH_RD_DATA_CRC_ERR_EN_POS (5U)
+#define SDH_RD_DATA_CRC_ERR_EN_LEN (1U)
+#define SDH_RD_DATA_CRC_ERR_EN_MSK (((1U << SDH_RD_DATA_CRC_ERR_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_EN_POS)
+#define SDH_RD_DATA_CRC_ERR_EN_UMSK (~(((1U << SDH_RD_DATA_CRC_ERR_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_EN_POS))
+#define SDH_RD_DATA_END_BIT_ERR_EN SDH_RD_DATA_END_BIT_ERR_EN
+#define SDH_RD_DATA_END_BIT_ERR_EN_POS (6U)
+#define SDH_RD_DATA_END_BIT_ERR_EN_LEN (1U)
+#define SDH_RD_DATA_END_BIT_ERR_EN_MSK (((1U << SDH_RD_DATA_END_BIT_ERR_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_EN_POS)
+#define SDH_RD_DATA_END_BIT_ERR_EN_UMSK (~(((1U << SDH_RD_DATA_END_BIT_ERR_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_EN_POS))
+#define SDH_CUR_LIM_ERR_EN SDH_CUR_LIM_ERR_EN
+#define SDH_CUR_LIM_ERR_EN_POS (7U)
+#define SDH_CUR_LIM_ERR_EN_LEN (1U)
+#define SDH_CUR_LIM_ERR_EN_MSK (((1U << SDH_CUR_LIM_ERR_EN_LEN) - 1) << SDH_CUR_LIM_ERR_EN_POS)
+#define SDH_CUR_LIM_ERR_EN_UMSK (~(((1U << SDH_CUR_LIM_ERR_EN_LEN) - 1) << SDH_CUR_LIM_ERR_EN_POS))
+#define SDH_AUTO_CMD12_ERR_EN SDH_AUTO_CMD12_ERR_EN
+#define SDH_AUTO_CMD12_ERR_EN_POS (8U)
+#define SDH_AUTO_CMD12_ERR_EN_LEN (1U)
+#define SDH_AUTO_CMD12_ERR_EN_MSK (((1U << SDH_AUTO_CMD12_ERR_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_EN_POS)
+#define SDH_AUTO_CMD12_ERR_EN_UMSK (~(((1U << SDH_AUTO_CMD12_ERR_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_EN_POS))
+#define SDH_ADMA_ERR_EN SDH_ADMA_ERR_EN
+#define SDH_ADMA_ERR_EN_POS (9U)
+#define SDH_ADMA_ERR_EN_LEN (1U)
+#define SDH_ADMA_ERR_EN_MSK (((1U << SDH_ADMA_ERR_EN_LEN) - 1) << SDH_ADMA_ERR_EN_POS)
+#define SDH_ADMA_ERR_EN_UMSK (~(((1U << SDH_ADMA_ERR_EN_LEN) - 1) << SDH_ADMA_ERR_EN_POS))
+#define SDH_TUNING_ERR_EN SDH_TUNING_ERR_EN
+#define SDH_TUNING_ERR_EN_POS (10U)
+#define SDH_TUNING_ERR_EN_LEN (1U)
+#define SDH_TUNING_ERR_EN_MSK (((1U << SDH_TUNING_ERR_EN_LEN) - 1) << SDH_TUNING_ERR_EN_POS)
+#define SDH_TUNING_ERR_EN_UMSK (~(((1U << SDH_TUNING_ERR_EN_LEN) - 1) << SDH_TUNING_ERR_EN_POS))
+#define SDH_SPI_ERR_EN SDH_SPI_ERR_EN
+#define SDH_SPI_ERR_EN_POS (12U)
+#define SDH_SPI_ERR_EN_LEN (1U)
+#define SDH_SPI_ERR_EN_MSK (((1U << SDH_SPI_ERR_EN_LEN) - 1) << SDH_SPI_ERR_EN_POS)
+#define SDH_SPI_ERR_EN_UMSK (~(((1U << SDH_SPI_ERR_EN_LEN) - 1) << SDH_SPI_ERR_EN_POS))
+#define SDH_AXI_RESP_ERR_EN SDH_AXI_RESP_ERR_EN
+#define SDH_AXI_RESP_ERR_EN_POS (13U)
+#define SDH_AXI_RESP_ERR_EN_LEN (1U)
+#define SDH_AXI_RESP_ERR_EN_MSK (((1U << SDH_AXI_RESP_ERR_EN_LEN) - 1) << SDH_AXI_RESP_ERR_EN_POS)
+#define SDH_AXI_RESP_ERR_EN_UMSK (~(((1U << SDH_AXI_RESP_ERR_EN_LEN) - 1) << SDH_AXI_RESP_ERR_EN_POS))
+#define SDH_CPL_TIMEOUT_ERR_EN SDH_CPL_TIMEOUT_ERR_EN
+#define SDH_CPL_TIMEOUT_ERR_EN_POS (14U)
+#define SDH_CPL_TIMEOUT_ERR_EN_LEN (1U)
+#define SDH_CPL_TIMEOUT_ERR_EN_MSK (((1U << SDH_CPL_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_EN_POS)
+#define SDH_CPL_TIMEOUT_ERR_EN_UMSK (~(((1U << SDH_CPL_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_EN_POS))
+#define SDH_CRC_STATUS_ERR_EN SDH_CRC_STATUS_ERR_EN
+#define SDH_CRC_STATUS_ERR_EN_POS (15U)
+#define SDH_CRC_STATUS_ERR_EN_LEN (1U)
+#define SDH_CRC_STATUS_ERR_EN_MSK (((1U << SDH_CRC_STATUS_ERR_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_EN_POS)
+#define SDH_CRC_STATUS_ERR_EN_UMSK (~(((1U << SDH_CRC_STATUS_ERR_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_EN_POS))
+
+/* 0x38 : Normal Interrupt Status Interrupt Enable Register */
+#define SDH_SD_NORMAL_INT_STATUS_INT_EN_OFFSET (0x38)
+#define SDH_CMD_COMPLETE_INT_EN SDH_CMD_COMPLETE_INT_EN
+#define SDH_CMD_COMPLETE_INT_EN_POS (0U)
+#define SDH_CMD_COMPLETE_INT_EN_LEN (1U)
+#define SDH_CMD_COMPLETE_INT_EN_MSK (((1U << SDH_CMD_COMPLETE_INT_EN_LEN) - 1) << SDH_CMD_COMPLETE_INT_EN_POS)
+#define SDH_CMD_COMPLETE_INT_EN_UMSK (~(((1U << SDH_CMD_COMPLETE_INT_EN_LEN) - 1) << SDH_CMD_COMPLETE_INT_EN_POS))
+#define SDH_XFER_COMPLETE_INT_EN SDH_XFER_COMPLETE_INT_EN
+#define SDH_XFER_COMPLETE_INT_EN_POS (1U)
+#define SDH_XFER_COMPLETE_INT_EN_LEN (1U)
+#define SDH_XFER_COMPLETE_INT_EN_MSK (((1U << SDH_XFER_COMPLETE_INT_EN_LEN) - 1) << SDH_XFER_COMPLETE_INT_EN_POS)
+#define SDH_XFER_COMPLETE_INT_EN_UMSK (~(((1U << SDH_XFER_COMPLETE_INT_EN_LEN) - 1) << SDH_XFER_COMPLETE_INT_EN_POS))
+#define SDH_BLOCK_GAP_EVT_INT_EN SDH_BLOCK_GAP_EVT_INT_EN
+#define SDH_BLOCK_GAP_EVT_INT_EN_POS (2U)
+#define SDH_BLOCK_GAP_EVT_INT_EN_LEN (1U)
+#define SDH_BLOCK_GAP_EVT_INT_EN_MSK (((1U << SDH_BLOCK_GAP_EVT_INT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_INT_EN_POS)
+#define SDH_BLOCK_GAP_EVT_INT_EN_UMSK (~(((1U << SDH_BLOCK_GAP_EVT_INT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_INT_EN_POS))
+#define SDH_DMA_INT_INT_EN SDH_DMA_INT_INT_EN
+#define SDH_DMA_INT_INT_EN_POS (3U)
+#define SDH_DMA_INT_INT_EN_LEN (1U)
+#define SDH_DMA_INT_INT_EN_MSK (((1U << SDH_DMA_INT_INT_EN_LEN) - 1) << SDH_DMA_INT_INT_EN_POS)
+#define SDH_DMA_INT_INT_EN_UMSK (~(((1U << SDH_DMA_INT_INT_EN_LEN) - 1) << SDH_DMA_INT_INT_EN_POS))
+#define SDH_TX_RDY_INT_EN SDH_TX_RDY_INT_EN
+#define SDH_TX_RDY_INT_EN_POS (4U)
+#define SDH_TX_RDY_INT_EN_LEN (1U)
+#define SDH_TX_RDY_INT_EN_MSK (((1U << SDH_TX_RDY_INT_EN_LEN) - 1) << SDH_TX_RDY_INT_EN_POS)
+#define SDH_TX_RDY_INT_EN_UMSK (~(((1U << SDH_TX_RDY_INT_EN_LEN) - 1) << SDH_TX_RDY_INT_EN_POS))
+#define SDH_RX_RDY_INT_EN SDH_RX_RDY_INT_EN
+#define SDH_RX_RDY_INT_EN_POS (5U)
+#define SDH_RX_RDY_INT_EN_LEN (1U)
+#define SDH_RX_RDY_INT_EN_MSK (((1U << SDH_RX_RDY_INT_EN_LEN) - 1) << SDH_RX_RDY_INT_EN_POS)
+#define SDH_RX_RDY_INT_EN_UMSK (~(((1U << SDH_RX_RDY_INT_EN_LEN) - 1) << SDH_RX_RDY_INT_EN_POS))
+#define SDH_CARD_INS_INT_EN SDH_CARD_INS_INT_EN
+#define SDH_CARD_INS_INT_EN_POS (6U)
+#define SDH_CARD_INS_INT_EN_LEN (1U)
+#define SDH_CARD_INS_INT_EN_MSK (((1U << SDH_CARD_INS_INT_EN_LEN) - 1) << SDH_CARD_INS_INT_EN_POS)
+#define SDH_CARD_INS_INT_EN_UMSK (~(((1U << SDH_CARD_INS_INT_EN_LEN) - 1) << SDH_CARD_INS_INT_EN_POS))
+#define SDH_CARD_REM_INT_EN SDH_CARD_REM_INT_EN
+#define SDH_CARD_REM_INT_EN_POS (7U)
+#define SDH_CARD_REM_INT_EN_LEN (1U)
+#define SDH_CARD_REM_INT_EN_MSK (((1U << SDH_CARD_REM_INT_EN_LEN) - 1) << SDH_CARD_REM_INT_EN_POS)
+#define SDH_CARD_REM_INT_EN_UMSK (~(((1U << SDH_CARD_REM_INT_EN_LEN) - 1) << SDH_CARD_REM_INT_EN_POS))
+#define SDH_CARD_INT_INT_EN SDH_CARD_INT_INT_EN
+#define SDH_CARD_INT_INT_EN_POS (8U)
+#define SDH_CARD_INT_INT_EN_LEN (1U)
+#define SDH_CARD_INT_INT_EN_MSK (((1U << SDH_CARD_INT_INT_EN_LEN) - 1) << SDH_CARD_INT_INT_EN_POS)
+#define SDH_CARD_INT_INT_EN_UMSK (~(((1U << SDH_CARD_INT_INT_EN_LEN) - 1) << SDH_CARD_INT_INT_EN_POS))
+#define SDH_INT_A_INT_INT_EN SDH_INT_A_INT_INT_EN
+#define SDH_INT_A_INT_INT_EN_POS (9U)
+#define SDH_INT_A_INT_INT_EN_LEN (1U)
+#define SDH_INT_A_INT_INT_EN_MSK (((1U << SDH_INT_A_INT_INT_EN_LEN) - 1) << SDH_INT_A_INT_INT_EN_POS)
+#define SDH_INT_A_INT_INT_EN_UMSK (~(((1U << SDH_INT_A_INT_INT_EN_LEN) - 1) << SDH_INT_A_INT_INT_EN_POS))
+#define SDH_INT_B_INT_INT_EN SDH_INT_B_INT_INT_EN
+#define SDH_INT_B_INT_INT_EN_POS (10U)
+#define SDH_INT_B_INT_INT_EN_LEN (1U)
+#define SDH_INT_B_INT_INT_EN_MSK (((1U << SDH_INT_B_INT_INT_EN_LEN) - 1) << SDH_INT_B_INT_INT_EN_POS)
+#define SDH_INT_B_INT_INT_EN_UMSK (~(((1U << SDH_INT_B_INT_INT_EN_LEN) - 1) << SDH_INT_B_INT_INT_EN_POS))
+#define SDH_INT_C_INT_INT_EN SDH_INT_C_INT_INT_EN
+#define SDH_INT_C_INT_INT_EN_POS (11U)
+#define SDH_INT_C_INT_INT_EN_LEN (1U)
+#define SDH_INT_C_INT_INT_EN_MSK (((1U << SDH_INT_C_INT_INT_EN_LEN) - 1) << SDH_INT_C_INT_INT_EN_POS)
+#define SDH_INT_C_INT_INT_EN_UMSK (~(((1U << SDH_INT_C_INT_INT_EN_LEN) - 1) << SDH_INT_C_INT_INT_EN_POS))
+#define SDH_RETUNE_INT_INT_EN SDH_RETUNE_INT_INT_EN
+#define SDH_RETUNE_INT_INT_EN_POS (12U)
+#define SDH_RETUNE_INT_INT_EN_LEN (1U)
+#define SDH_RETUNE_INT_INT_EN_MSK (((1U << SDH_RETUNE_INT_INT_EN_LEN) - 1) << SDH_RETUNE_INT_INT_EN_POS)
+#define SDH_RETUNE_INT_INT_EN_UMSK (~(((1U << SDH_RETUNE_INT_INT_EN_LEN) - 1) << SDH_RETUNE_INT_INT_EN_POS))
+
+/* 0x3A : Error Interrupt Status Interrupt Enable Register */
+#define SDH_SD_ERROR_INT_STATUS_INT_EN_OFFSET (0x3A)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN SDH_CMD_TIMEOUT_ERR_INT_EN
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_POS (0U)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_LEN (1U)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_MSK (((1U << SDH_CMD_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_INT_EN_POS)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_UMSK (~(((1U << SDH_CMD_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_INT_EN_POS))
+#define SDH_CMD_CRC_ERR_INT_EN SDH_CMD_CRC_ERR_INT_EN
+#define SDH_CMD_CRC_ERR_INT_EN_POS (1U)
+#define SDH_CMD_CRC_ERR_INT_EN_LEN (1U)
+#define SDH_CMD_CRC_ERR_INT_EN_MSK (((1U << SDH_CMD_CRC_ERR_INT_EN_LEN) - 1) << SDH_CMD_CRC_ERR_INT_EN_POS)
+#define SDH_CMD_CRC_ERR_INT_EN_UMSK (~(((1U << SDH_CMD_CRC_ERR_INT_EN_LEN) - 1) << SDH_CMD_CRC_ERR_INT_EN_POS))
+#define SDH_CMD_END_BIT_ERR_INT_EN SDH_CMD_END_BIT_ERR_INT_EN
+#define SDH_CMD_END_BIT_ERR_INT_EN_POS (2U)
+#define SDH_CMD_END_BIT_ERR_INT_EN_LEN (1U)
+#define SDH_CMD_END_BIT_ERR_INT_EN_MSK (((1U << SDH_CMD_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_INT_EN_POS)
+#define SDH_CMD_END_BIT_ERR_INT_EN_UMSK (~(((1U << SDH_CMD_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_INT_EN_POS))
+#define SDH_CMD_INDEX_ERR_INT_EN SDH_CMD_INDEX_ERR_INT_EN
+#define SDH_CMD_INDEX_ERR_INT_EN_POS (3U)
+#define SDH_CMD_INDEX_ERR_INT_EN_LEN (1U)
+#define SDH_CMD_INDEX_ERR_INT_EN_MSK (((1U << SDH_CMD_INDEX_ERR_INT_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_INT_EN_POS)
+#define SDH_CMD_INDEX_ERR_INT_EN_UMSK (~(((1U << SDH_CMD_INDEX_ERR_INT_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_INT_EN_POS))
+#define SDH_DATA_TIMEOUT_ERR_INT_EN SDH_DATA_TIMEOUT_ERR_INT_EN
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_POS (4U)
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_LEN (1U)
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_MSK (((1U << SDH_DATA_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_INT_EN_POS)
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_UMSK (~(((1U << SDH_DATA_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_INT_EN_POS))
+#define SDH_RD_DATA_CRC_ERR_INT_EN SDH_RD_DATA_CRC_ERR_INT_EN
+#define SDH_RD_DATA_CRC_ERR_INT_EN_POS (5U)
+#define SDH_RD_DATA_CRC_ERR_INT_EN_LEN (1U)
+#define SDH_RD_DATA_CRC_ERR_INT_EN_MSK (((1U << SDH_RD_DATA_CRC_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_INT_EN_POS)
+#define SDH_RD_DATA_CRC_ERR_INT_EN_UMSK (~(((1U << SDH_RD_DATA_CRC_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_INT_EN_POS))
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN SDH_RD_DATA_END_BIT_ERR_INT_EN
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_POS (6U)
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_LEN (1U)
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_MSK (((1U << SDH_RD_DATA_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_INT_EN_POS)
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_UMSK (~(((1U << SDH_RD_DATA_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_INT_EN_POS))
+#define SDH_CUR_LIM_ERR_INT_EN SDH_CUR_LIM_ERR_INT_EN
+#define SDH_CUR_LIM_ERR_INT_EN_POS (7U)
+#define SDH_CUR_LIM_ERR_INT_EN_LEN (1U)
+#define SDH_CUR_LIM_ERR_INT_EN_MSK (((1U << SDH_CUR_LIM_ERR_INT_EN_LEN) - 1) << SDH_CUR_LIM_ERR_INT_EN_POS)
+#define SDH_CUR_LIM_ERR_INT_EN_UMSK (~(((1U << SDH_CUR_LIM_ERR_INT_EN_LEN) - 1) << SDH_CUR_LIM_ERR_INT_EN_POS))
+#define SDH_AUTO_CMD12_ERR_INT_EN SDH_AUTO_CMD12_ERR_INT_EN
+#define SDH_AUTO_CMD12_ERR_INT_EN_POS (8U)
+#define SDH_AUTO_CMD12_ERR_INT_EN_LEN (1U)
+#define SDH_AUTO_CMD12_ERR_INT_EN_MSK (((1U << SDH_AUTO_CMD12_ERR_INT_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_INT_EN_POS)
+#define SDH_AUTO_CMD12_ERR_INT_EN_UMSK (~(((1U << SDH_AUTO_CMD12_ERR_INT_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_INT_EN_POS))
+#define SDH_ADMA_ERR_INT_EN SDH_ADMA_ERR_INT_EN
+#define SDH_ADMA_ERR_INT_EN_POS (9U)
+#define SDH_ADMA_ERR_INT_EN_LEN (1U)
+#define SDH_ADMA_ERR_INT_EN_MSK (((1U << SDH_ADMA_ERR_INT_EN_LEN) - 1) << SDH_ADMA_ERR_INT_EN_POS)
+#define SDH_ADMA_ERR_INT_EN_UMSK (~(((1U << SDH_ADMA_ERR_INT_EN_LEN) - 1) << SDH_ADMA_ERR_INT_EN_POS))
+#define SDH_TUNE_ERR_INT_EN SDH_TUNE_ERR_INT_EN
+#define SDH_TUNE_ERR_INT_EN_POS (10U)
+#define SDH_TUNE_ERR_INT_EN_LEN (1U)
+#define SDH_TUNE_ERR_INT_EN_MSK (((1U << SDH_TUNE_ERR_INT_EN_LEN) - 1) << SDH_TUNE_ERR_INT_EN_POS)
+#define SDH_TUNE_ERR_INT_EN_UMSK (~(((1U << SDH_TUNE_ERR_INT_EN_LEN) - 1) << SDH_TUNE_ERR_INT_EN_POS))
+#define SDH_SPI_ERR_INT_EN SDH_SPI_ERR_INT_EN
+#define SDH_SPI_ERR_INT_EN_POS (12U)
+#define SDH_SPI_ERR_INT_EN_LEN (1U)
+#define SDH_SPI_ERR_INT_EN_MSK (((1U << SDH_SPI_ERR_INT_EN_LEN) - 1) << SDH_SPI_ERR_INT_EN_POS)
+#define SDH_SPI_ERR_INT_EN_UMSK (~(((1U << SDH_SPI_ERR_INT_EN_LEN) - 1) << SDH_SPI_ERR_INT_EN_POS))
+#define SDH_AXI_RESP_ERR_INT_EN SDH_AXI_RESP_ERR_INT_EN
+#define SDH_AXI_RESP_ERR_INT_EN_POS (13U)
+#define SDH_AXI_RESP_ERR_INT_EN_LEN (1U)
+#define SDH_AXI_RESP_ERR_INT_EN_MSK (((1U << SDH_AXI_RESP_ERR_INT_EN_LEN) - 1) << SDH_AXI_RESP_ERR_INT_EN_POS)
+#define SDH_AXI_RESP_ERR_INT_EN_UMSK (~(((1U << SDH_AXI_RESP_ERR_INT_EN_LEN) - 1) << SDH_AXI_RESP_ERR_INT_EN_POS))
+#define SDH_CPL_TIMEOUT_ERR_INT_EN SDH_CPL_TIMEOUT_ERR_INT_EN
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_POS (14U)
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_LEN (1U)
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_MSK (((1U << SDH_CPL_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_INT_EN_POS)
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_UMSK (~(((1U << SDH_CPL_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_INT_EN_POS))
+#define SDH_CRC_STATUS_ERR_INT_EN SDH_CRC_STATUS_ERR_INT_EN
+#define SDH_CRC_STATUS_ERR_INT_EN_POS (15U)
+#define SDH_CRC_STATUS_ERR_INT_EN_LEN (1U)
+#define SDH_CRC_STATUS_ERR_INT_EN_MSK (((1U << SDH_CRC_STATUS_ERR_INT_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_INT_EN_POS)
+#define SDH_CRC_STATUS_ERR_INT_EN_UMSK (~(((1U << SDH_CRC_STATUS_ERR_INT_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_INT_EN_POS))
+
+/* 0x3C : Auto CMD12 Error Status Register */
+#define SDH_SD_AUTO_CMD12_ERROR_STATUS_OFFSET (0x3C)
+#define SDH_AUTO_CMD12_NOT_EXE SDH_AUTO_CMD12_NOT_EXE
+#define SDH_AUTO_CMD12_NOT_EXE_POS (0U)
+#define SDH_AUTO_CMD12_NOT_EXE_LEN (1U)
+#define SDH_AUTO_CMD12_NOT_EXE_MSK (((1U << SDH_AUTO_CMD12_NOT_EXE_LEN) - 1) << SDH_AUTO_CMD12_NOT_EXE_POS)
+#define SDH_AUTO_CMD12_NOT_EXE_UMSK (~(((1U << SDH_AUTO_CMD12_NOT_EXE_LEN) - 1) << SDH_AUTO_CMD12_NOT_EXE_POS))
+#define SDH_AUTO_CMD_TIMEOUT_ERR SDH_AUTO_CMD_TIMEOUT_ERR
+#define SDH_AUTO_CMD_TIMEOUT_ERR_POS (1U)
+#define SDH_AUTO_CMD_TIMEOUT_ERR_LEN (1U)
+#define SDH_AUTO_CMD_TIMEOUT_ERR_MSK (((1U << SDH_AUTO_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_AUTO_CMD_TIMEOUT_ERR_POS)
+#define SDH_AUTO_CMD_TIMEOUT_ERR_UMSK (~(((1U << SDH_AUTO_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_AUTO_CMD_TIMEOUT_ERR_POS))
+#define SDH_AUTO_CMD_CRC_ERR SDH_AUTO_CMD_CRC_ERR
+#define SDH_AUTO_CMD_CRC_ERR_POS (2U)
+#define SDH_AUTO_CMD_CRC_ERR_LEN (1U)
+#define SDH_AUTO_CMD_CRC_ERR_MSK (((1U << SDH_AUTO_CMD_CRC_ERR_LEN) - 1) << SDH_AUTO_CMD_CRC_ERR_POS)
+#define SDH_AUTO_CMD_CRC_ERR_UMSK (~(((1U << SDH_AUTO_CMD_CRC_ERR_LEN) - 1) << SDH_AUTO_CMD_CRC_ERR_POS))
+#define SDH_AUTO_CMD_END_BIT_ERR SDH_AUTO_CMD_END_BIT_ERR
+#define SDH_AUTO_CMD_END_BIT_ERR_POS (3U)
+#define SDH_AUTO_CMD_END_BIT_ERR_LEN (1U)
+#define SDH_AUTO_CMD_END_BIT_ERR_MSK (((1U << SDH_AUTO_CMD_END_BIT_ERR_LEN) - 1) << SDH_AUTO_CMD_END_BIT_ERR_POS)
+#define SDH_AUTO_CMD_END_BIT_ERR_UMSK (~(((1U << SDH_AUTO_CMD_END_BIT_ERR_LEN) - 1) << SDH_AUTO_CMD_END_BIT_ERR_POS))
+#define SDH_AUTO_CMD_INDEX_ERR SDH_AUTO_CMD_INDEX_ERR
+#define SDH_AUTO_CMD_INDEX_ERR_POS (4U)
+#define SDH_AUTO_CMD_INDEX_ERR_LEN (1U)
+#define SDH_AUTO_CMD_INDEX_ERR_MSK (((1U << SDH_AUTO_CMD_INDEX_ERR_LEN) - 1) << SDH_AUTO_CMD_INDEX_ERR_POS)
+#define SDH_AUTO_CMD_INDEX_ERR_UMSK (~(((1U << SDH_AUTO_CMD_INDEX_ERR_LEN) - 1) << SDH_AUTO_CMD_INDEX_ERR_POS))
+#define SDH_CMD_NOT_ISSUED SDH_CMD_NOT_ISSUED
+#define SDH_CMD_NOT_ISSUED_POS (7U)
+#define SDH_CMD_NOT_ISSUED_LEN (1U)
+#define SDH_CMD_NOT_ISSUED_MSK (((1U << SDH_CMD_NOT_ISSUED_LEN) - 1) << SDH_CMD_NOT_ISSUED_POS)
+#define SDH_CMD_NOT_ISSUED_UMSK (~(((1U << SDH_CMD_NOT_ISSUED_LEN) - 1) << SDH_CMD_NOT_ISSUED_POS))
+
+/* 0x3e : Host Control 2 Register */
+#define SDH_HOST_CTRL_2_OFFSET (0x3e)
+#define SDH_UHS_MODE_SEL SDH_UHS_MODE_SEL
+#define SDH_UHS_MODE_SEL_POS (0U)
+#define SDH_UHS_MODE_SEL_LEN (3U)
+#define SDH_UHS_MODE_SEL_MSK (((1U << SDH_UHS_MODE_SEL_LEN) - 1) << SDH_UHS_MODE_SEL_POS)
+#define SDH_UHS_MODE_SEL_UMSK (~(((1U << SDH_UHS_MODE_SEL_LEN) - 1) << SDH_UHS_MODE_SEL_POS))
+#define SDH_SDH_V18_EN SDH_SDH_V18_EN
+#define SDH_SDH_V18_EN_POS (3U)
+#define SDH_SDH_V18_EN_LEN (1U)
+#define SDH_SDH_V18_EN_MSK (((1U << SDH_SDH_V18_EN_LEN) - 1) << SDH_SDH_V18_EN_POS)
+#define SDH_SDH_V18_EN_UMSK (~(((1U << SDH_SDH_V18_EN_LEN) - 1) << SDH_SDH_V18_EN_POS))
+#define SDH_DRV_STRENGTH_SEL SDH_DRV_STRENGTH_SEL
+#define SDH_DRV_STRENGTH_SEL_POS (4U)
+#define SDH_DRV_STRENGTH_SEL_LEN (2U)
+#define SDH_DRV_STRENGTH_SEL_MSK (((1U << SDH_DRV_STRENGTH_SEL_LEN) - 1) << SDH_DRV_STRENGTH_SEL_POS)
+#define SDH_DRV_STRENGTH_SEL_UMSK (~(((1U << SDH_DRV_STRENGTH_SEL_LEN) - 1) << SDH_DRV_STRENGTH_SEL_POS))
+#define SDH_EXE_TUNING SDH_EXE_TUNING
+#define SDH_EXE_TUNING_POS (6U)
+#define SDH_EXE_TUNING_LEN (1U)
+#define SDH_EXE_TUNING_MSK (((1U << SDH_EXE_TUNING_LEN) - 1) << SDH_EXE_TUNING_POS)
+#define SDH_EXE_TUNING_UMSK (~(((1U << SDH_EXE_TUNING_LEN) - 1) << SDH_EXE_TUNING_POS))
+#define SDH_SAMPLING_CLK_SEL SDH_SAMPLING_CLK_SEL
+#define SDH_SAMPLING_CLK_SEL_POS (7U)
+#define SDH_SAMPLING_CLK_SEL_LEN (1U)
+#define SDH_SAMPLING_CLK_SEL_MSK (((1U << SDH_SAMPLING_CLK_SEL_LEN) - 1) << SDH_SAMPLING_CLK_SEL_POS)
+#define SDH_SAMPLING_CLK_SEL_UMSK (~(((1U << SDH_SAMPLING_CLK_SEL_LEN) - 1) << SDH_SAMPLING_CLK_SEL_POS))
+#define SDH_ASYNC_INT_EN SDH_ASYNC_INT_EN
+#define SDH_ASYNC_INT_EN_POS (14U)
+#define SDH_ASYNC_INT_EN_LEN (1U)
+#define SDH_ASYNC_INT_EN_MSK (((1U << SDH_ASYNC_INT_EN_LEN) - 1) << SDH_ASYNC_INT_EN_POS)
+#define SDH_ASYNC_INT_EN_UMSK (~(((1U << SDH_ASYNC_INT_EN_LEN) - 1) << SDH_ASYNC_INT_EN_POS))
+#define SDH_PRE_VAL_EN SDH_PRE_VAL_EN
+#define SDH_PRE_VAL_EN_POS (15U)
+#define SDH_PRE_VAL_EN_LEN (1U)
+#define SDH_PRE_VAL_EN_MSK (((1U << SDH_PRE_VAL_EN_LEN) - 1) << SDH_PRE_VAL_EN_POS)
+#define SDH_PRE_VAL_EN_UMSK (~(((1U << SDH_PRE_VAL_EN_LEN) - 1) << SDH_PRE_VAL_EN_POS))
+
+/* 0x40 : Capabilities Register 1 */
+#define SDH_SD_CAPABILITIES_1_OFFSET (0x40)
+#define SDH_TIMEOUT_FREQ SDH_TIMEOUT_FREQ
+#define SDH_TIMEOUT_FREQ_POS (0U)
+#define SDH_TIMEOUT_FREQ_LEN (6U)
+#define SDH_TIMEOUT_FREQ_MSK (((1U << SDH_TIMEOUT_FREQ_LEN) - 1) << SDH_TIMEOUT_FREQ_POS)
+#define SDH_TIMEOUT_FREQ_UMSK (~(((1U << SDH_TIMEOUT_FREQ_LEN) - 1) << SDH_TIMEOUT_FREQ_POS))
+#define SDH_TIMEOUT_UNIT SDH_TIMEOUT_UNIT
+#define SDH_TIMEOUT_UNIT_POS (7U)
+#define SDH_TIMEOUT_UNIT_LEN (1U)
+#define SDH_TIMEOUT_UNIT_MSK (((1U << SDH_TIMEOUT_UNIT_LEN) - 1) << SDH_TIMEOUT_UNIT_POS)
+#define SDH_TIMEOUT_UNIT_UMSK (~(((1U << SDH_TIMEOUT_UNIT_LEN) - 1) << SDH_TIMEOUT_UNIT_POS))
+#define SDH_BASE_FREQ SDH_BASE_FREQ
+#define SDH_BASE_FREQ_POS (8U)
+#define SDH_BASE_FREQ_LEN (8U)
+#define SDH_BASE_FREQ_MSK (((1U << SDH_BASE_FREQ_LEN) - 1) << SDH_BASE_FREQ_POS)
+#define SDH_BASE_FREQ_UMSK (~(((1U << SDH_BASE_FREQ_LEN) - 1) << SDH_BASE_FREQ_POS))
+
+/* 0x42 : Capabilities Register 2 */
+#define SDH_SD_CAPABILITIES_2_OFFSET (0x42)
+#define SDH_MAX_BLK_LEN SDH_MAX_BLK_LEN
+#define SDH_MAX_BLK_LEN_POS (0U)
+#define SDH_MAX_BLK_LEN_LEN (2U)
+#define SDH_MAX_BLK_LEN_MSK (((1U << SDH_MAX_BLK_LEN_LEN) - 1) << SDH_MAX_BLK_LEN_POS)
+#define SDH_MAX_BLK_LEN_UMSK (~(((1U << SDH_MAX_BLK_LEN_LEN) - 1) << SDH_MAX_BLK_LEN_POS))
+#define SDH_EX_DATA_WIDTH_SUPPORT SDH_EX_DATA_WIDTH_SUPPORT
+#define SDH_EX_DATA_WIDTH_SUPPORT_POS (2U)
+#define SDH_EX_DATA_WIDTH_SUPPORT_LEN (1U)
+#define SDH_EX_DATA_WIDTH_SUPPORT_MSK (((1U << SDH_EX_DATA_WIDTH_SUPPORT_LEN) - 1) << SDH_EX_DATA_WIDTH_SUPPORT_POS)
+#define SDH_EX_DATA_WIDTH_SUPPORT_UMSK (~(((1U << SDH_EX_DATA_WIDTH_SUPPORT_LEN) - 1) << SDH_EX_DATA_WIDTH_SUPPORT_POS))
+#define SDH_ADMA2_SUPPORT SDH_ADMA2_SUPPORT
+#define SDH_ADMA2_SUPPORT_POS (3U)
+#define SDH_ADMA2_SUPPORT_LEN (1U)
+#define SDH_ADMA2_SUPPORT_MSK (((1U << SDH_ADMA2_SUPPORT_LEN) - 1) << SDH_ADMA2_SUPPORT_POS)
+#define SDH_ADMA2_SUPPORT_UMSK (~(((1U << SDH_ADMA2_SUPPORT_LEN) - 1) << SDH_ADMA2_SUPPORT_POS))
+#define SDH_ADMA1_SUPPORT SDH_ADMA1_SUPPORT
+#define SDH_ADMA1_SUPPORT_POS (4U)
+#define SDH_ADMA1_SUPPORT_LEN (1U)
+#define SDH_ADMA1_SUPPORT_MSK (((1U << SDH_ADMA1_SUPPORT_LEN) - 1) << SDH_ADMA1_SUPPORT_POS)
+#define SDH_ADMA1_SUPPORT_UMSK (~(((1U << SDH_ADMA1_SUPPORT_LEN) - 1) << SDH_ADMA1_SUPPORT_POS))
+#define SDH_HI_SPEED_SUPPORT SDH_HI_SPEED_SUPPORT
+#define SDH_HI_SPEED_SUPPORT_POS (5U)
+#define SDH_HI_SPEED_SUPPORT_LEN (1U)
+#define SDH_HI_SPEED_SUPPORT_MSK (((1U << SDH_HI_SPEED_SUPPORT_LEN) - 1) << SDH_HI_SPEED_SUPPORT_POS)
+#define SDH_HI_SPEED_SUPPORT_UMSK (~(((1U << SDH_HI_SPEED_SUPPORT_LEN) - 1) << SDH_HI_SPEED_SUPPORT_POS))
+#define SDH_SDMA_SUPPORT SDH_SDMA_SUPPORT
+#define SDH_SDMA_SUPPORT_POS (6U)
+#define SDH_SDMA_SUPPORT_LEN (1U)
+#define SDH_SDMA_SUPPORT_MSK (((1U << SDH_SDMA_SUPPORT_LEN) - 1) << SDH_SDMA_SUPPORT_POS)
+#define SDH_SDMA_SUPPORT_UMSK (~(((1U << SDH_SDMA_SUPPORT_LEN) - 1) << SDH_SDMA_SUPPORT_POS))
+#define SDH_SUS_RES_SUPPORT SDH_SUS_RES_SUPPORT
+#define SDH_SUS_RES_SUPPORT_POS (7U)
+#define SDH_SUS_RES_SUPPORT_LEN (1U)
+#define SDH_SUS_RES_SUPPORT_MSK (((1U << SDH_SUS_RES_SUPPORT_LEN) - 1) << SDH_SUS_RES_SUPPORT_POS)
+#define SDH_SUS_RES_SUPPORT_UMSK (~(((1U << SDH_SUS_RES_SUPPORT_LEN) - 1) << SDH_SUS_RES_SUPPORT_POS))
+#define SDH_VLG_33_SUPPORT SDH_VLG_33_SUPPORT
+#define SDH_VLG_33_SUPPORT_POS (8U)
+#define SDH_VLG_33_SUPPORT_LEN (1U)
+#define SDH_VLG_33_SUPPORT_MSK (((1U << SDH_VLG_33_SUPPORT_LEN) - 1) << SDH_VLG_33_SUPPORT_POS)
+#define SDH_VLG_33_SUPPORT_UMSK (~(((1U << SDH_VLG_33_SUPPORT_LEN) - 1) << SDH_VLG_33_SUPPORT_POS))
+#define SDH_VLG_30_SUPPORT SDH_VLG_30_SUPPORT
+#define SDH_VLG_30_SUPPORT_POS (9U)
+#define SDH_VLG_30_SUPPORT_LEN (1U)
+#define SDH_VLG_30_SUPPORT_MSK (((1U << SDH_VLG_30_SUPPORT_LEN) - 1) << SDH_VLG_30_SUPPORT_POS)
+#define SDH_VLG_30_SUPPORT_UMSK (~(((1U << SDH_VLG_30_SUPPORT_LEN) - 1) << SDH_VLG_30_SUPPORT_POS))
+#define SDH_VLG_18_SUPPORT SDH_VLG_18_SUPPORT
+#define SDH_VLG_18_SUPPORT_POS (10U)
+#define SDH_VLG_18_SUPPORT_LEN (1U)
+#define SDH_VLG_18_SUPPORT_MSK (((1U << SDH_VLG_18_SUPPORT_LEN) - 1) << SDH_VLG_18_SUPPORT_POS)
+#define SDH_VLG_18_SUPPORT_UMSK (~(((1U << SDH_VLG_18_SUPPORT_LEN) - 1) << SDH_VLG_18_SUPPORT_POS))
+#define SDH_SYS_BUS_64_SUPPORT SDH_SYS_BUS_64_SUPPORT
+#define SDH_SYS_BUS_64_SUPPORT_POS (12U)
+#define SDH_SYS_BUS_64_SUPPORT_LEN (1U)
+#define SDH_SYS_BUS_64_SUPPORT_MSK (((1U << SDH_SYS_BUS_64_SUPPORT_LEN) - 1) << SDH_SYS_BUS_64_SUPPORT_POS)
+#define SDH_SYS_BUS_64_SUPPORT_UMSK (~(((1U << SDH_SYS_BUS_64_SUPPORT_LEN) - 1) << SDH_SYS_BUS_64_SUPPORT_POS))
+#define SDH_ASYNC_INT_SUPPORT SDH_ASYNC_INT_SUPPORT
+#define SDH_ASYNC_INT_SUPPORT_POS (13U)
+#define SDH_ASYNC_INT_SUPPORT_LEN (1U)
+#define SDH_ASYNC_INT_SUPPORT_MSK (((1U << SDH_ASYNC_INT_SUPPORT_LEN) - 1) << SDH_ASYNC_INT_SUPPORT_POS)
+#define SDH_ASYNC_INT_SUPPORT_UMSK (~(((1U << SDH_ASYNC_INT_SUPPORT_LEN) - 1) << SDH_ASYNC_INT_SUPPORT_POS))
+#define SDH_CFG_SLOT_TYPE SDH_CFG_SLOT_TYPE
+#define SDH_CFG_SLOT_TYPE_POS (14U)
+#define SDH_CFG_SLOT_TYPE_LEN (2U)
+#define SDH_CFG_SLOT_TYPE_MSK (((1U << SDH_CFG_SLOT_TYPE_LEN) - 1) << SDH_CFG_SLOT_TYPE_POS)
+#define SDH_CFG_SLOT_TYPE_UMSK (~(((1U << SDH_CFG_SLOT_TYPE_LEN) - 1) << SDH_CFG_SLOT_TYPE_POS))
+
+/* 0x44 : Capabilities Register 3 */
+#define SDH_SD_CAPABILITIES_3_OFFSET (0x44)
+#define SDH_SDR50_SUPPORT SDH_SDR50_SUPPORT
+#define SDH_SDR50_SUPPORT_POS (0U)
+#define SDH_SDR50_SUPPORT_LEN (1U)
+#define SDH_SDR50_SUPPORT_MSK (((1U << SDH_SDR50_SUPPORT_LEN) - 1) << SDH_SDR50_SUPPORT_POS)
+#define SDH_SDR50_SUPPORT_UMSK (~(((1U << SDH_SDR50_SUPPORT_LEN) - 1) << SDH_SDR50_SUPPORT_POS))
+#define SDH_SDR104_SUPPORT SDH_SDR104_SUPPORT
+#define SDH_SDR104_SUPPORT_POS (1U)
+#define SDH_SDR104_SUPPORT_LEN (1U)
+#define SDH_SDR104_SUPPORT_MSK (((1U << SDH_SDR104_SUPPORT_LEN) - 1) << SDH_SDR104_SUPPORT_POS)
+#define SDH_SDR104_SUPPORT_UMSK (~(((1U << SDH_SDR104_SUPPORT_LEN) - 1) << SDH_SDR104_SUPPORT_POS))
+#define SDH_DDR50_SUPPORT SDH_DDR50_SUPPORT
+#define SDH_DDR50_SUPPORT_POS (2U)
+#define SDH_DDR50_SUPPORT_LEN (1U)
+#define SDH_DDR50_SUPPORT_MSK (((1U << SDH_DDR50_SUPPORT_LEN) - 1) << SDH_DDR50_SUPPORT_POS)
+#define SDH_DDR50_SUPPORT_UMSK (~(((1U << SDH_DDR50_SUPPORT_LEN) - 1) << SDH_DDR50_SUPPORT_POS))
+#define SDH_DRV_TYPE_A SDH_DRV_TYPE_A
+#define SDH_DRV_TYPE_A_POS (4U)
+#define SDH_DRV_TYPE_A_LEN (1U)
+#define SDH_DRV_TYPE_A_MSK (((1U << SDH_DRV_TYPE_A_LEN) - 1) << SDH_DRV_TYPE_A_POS)
+#define SDH_DRV_TYPE_A_UMSK (~(((1U << SDH_DRV_TYPE_A_LEN) - 1) << SDH_DRV_TYPE_A_POS))
+#define SDH_DRV_TYPE_C SDH_DRV_TYPE_C
+#define SDH_DRV_TYPE_C_POS (5U)
+#define SDH_DRV_TYPE_C_LEN (1U)
+#define SDH_DRV_TYPE_C_MSK (((1U << SDH_DRV_TYPE_C_LEN) - 1) << SDH_DRV_TYPE_C_POS)
+#define SDH_DRV_TYPE_C_UMSK (~(((1U << SDH_DRV_TYPE_C_LEN) - 1) << SDH_DRV_TYPE_C_POS))
+#define SDH_DRV_TYPE_D SDH_DRV_TYPE_D
+#define SDH_DRV_TYPE_D_POS (6U)
+#define SDH_DRV_TYPE_D_LEN (1U)
+#define SDH_DRV_TYPE_D_MSK (((1U << SDH_DRV_TYPE_D_LEN) - 1) << SDH_DRV_TYPE_D_POS)
+#define SDH_DRV_TYPE_D_UMSK (~(((1U << SDH_DRV_TYPE_D_LEN) - 1) << SDH_DRV_TYPE_D_POS))
+#define SDH_TMR_RETUNE SDH_TMR_RETUNE
+#define SDH_TMR_RETUNE_POS (8U)
+#define SDH_TMR_RETUNE_LEN (4U)
+#define SDH_TMR_RETUNE_MSK (((1U << SDH_TMR_RETUNE_LEN) - 1) << SDH_TMR_RETUNE_POS)
+#define SDH_TMR_RETUNE_UMSK (~(((1U << SDH_TMR_RETUNE_LEN) - 1) << SDH_TMR_RETUNE_POS))
+#define SDH_SDR50_TUNE SDH_SDR50_TUNE
+#define SDH_SDR50_TUNE_POS (13U)
+#define SDH_SDR50_TUNE_LEN (1U)
+#define SDH_SDR50_TUNE_MSK (((1U << SDH_SDR50_TUNE_LEN) - 1) << SDH_SDR50_TUNE_POS)
+#define SDH_SDR50_TUNE_UMSK (~(((1U << SDH_SDR50_TUNE_LEN) - 1) << SDH_SDR50_TUNE_POS))
+#define SDH_RETUNE_MODES SDH_RETUNE_MODES
+#define SDH_RETUNE_MODES_POS (14U)
+#define SDH_RETUNE_MODES_LEN (2U)
+#define SDH_RETUNE_MODES_MSK (((1U << SDH_RETUNE_MODES_LEN) - 1) << SDH_RETUNE_MODES_POS)
+#define SDH_RETUNE_MODES_UMSK (~(((1U << SDH_RETUNE_MODES_LEN) - 1) << SDH_RETUNE_MODES_POS))
+
+/* 0x46 : Capabilities Register 4 */
+#define SDH_SD_CAPABILITIES_4_OFFSET (0x46)
+#define SDH_CLK_MULTIPLIER SDH_CLK_MULTIPLIER
+#define SDH_CLK_MULTIPLIER_POS (0U)
+#define SDH_CLK_MULTIPLIER_LEN (8U)
+#define SDH_CLK_MULTIPLIER_MSK (((1U << SDH_CLK_MULTIPLIER_LEN) - 1) << SDH_CLK_MULTIPLIER_POS)
+#define SDH_CLK_MULTIPLIER_UMSK (~(((1U << SDH_CLK_MULTIPLIER_LEN) - 1) << SDH_CLK_MULTIPLIER_POS))
+
+/* 0x48 : Maximum Current Register 1 */
+#define SDH_SD_MAX_CURRENT_1_OFFSET (0x48)
+#define SDH_MAX_CUR_33 SDH_MAX_CUR_33
+#define SDH_MAX_CUR_33_POS (0U)
+#define SDH_MAX_CUR_33_LEN (8U)
+#define SDH_MAX_CUR_33_MSK (((1U << SDH_MAX_CUR_33_LEN) - 1) << SDH_MAX_CUR_33_POS)
+#define SDH_MAX_CUR_33_UMSK (~(((1U << SDH_MAX_CUR_33_LEN) - 1) << SDH_MAX_CUR_33_POS))
+#define SDH_MAX_CUR_30 SDH_MAX_CUR_30
+#define SDH_MAX_CUR_30_POS (8U)
+#define SDH_MAX_CUR_30_LEN (8U)
+#define SDH_MAX_CUR_30_MSK (((1U << SDH_MAX_CUR_30_LEN) - 1) << SDH_MAX_CUR_30_POS)
+#define SDH_MAX_CUR_30_UMSK (~(((1U << SDH_MAX_CUR_30_LEN) - 1) << SDH_MAX_CUR_30_POS))
+
+/* 0x4A : Maximum Current Register 2 */
+#define SDH_SD_MAX_CURRENT_2_OFFSET (0x4A)
+#define SDH_MAX_CUR_18 SDH_MAX_CUR_18
+#define SDH_MAX_CUR_18_POS (0U)
+#define SDH_MAX_CUR_18_LEN (8U)
+#define SDH_MAX_CUR_18_MSK (((1U << SDH_MAX_CUR_18_LEN) - 1) << SDH_MAX_CUR_18_POS)
+#define SDH_MAX_CUR_18_UMSK (~(((1U << SDH_MAX_CUR_18_LEN) - 1) << SDH_MAX_CUR_18_POS))
+
+/* 0x4C : Maximum Current Register 3 */
+#define SDH_SD_MAX_CURRENT_3_OFFSET (0x4C)
+
+/* 0x4E : Maximum Current Register 4 */
+#define SDH_SD_MAX_CURRENT_4_OFFSET (0x4E)
+
+/* 0x50 : Force Event Auto cmd12 Error Register */
+#define SDH_SD_FORCE_EVENT_AUTO_CMD12_ERROR_OFFSET (0x50)
+#define SDH_F_ACMD12_NEXE_ERR SDH_F_ACMD12_NEXE_ERR
+#define SDH_F_ACMD12_NEXE_ERR_POS (0U)
+#define SDH_F_ACMD12_NEXE_ERR_LEN (1U)
+#define SDH_F_ACMD12_NEXE_ERR_MSK (((1U << SDH_F_ACMD12_NEXE_ERR_LEN) - 1) << SDH_F_ACMD12_NEXE_ERR_POS)
+#define SDH_F_ACMD12_NEXE_ERR_UMSK (~(((1U << SDH_F_ACMD12_NEXE_ERR_LEN) - 1) << SDH_F_ACMD12_NEXE_ERR_POS))
+#define SDH_F_ACMD_TO_ERR SDH_F_ACMD_TO_ERR
+#define SDH_F_ACMD_TO_ERR_POS (1U)
+#define SDH_F_ACMD_TO_ERR_LEN (1U)
+#define SDH_F_ACMD_TO_ERR_MSK (((1U << SDH_F_ACMD_TO_ERR_LEN) - 1) << SDH_F_ACMD_TO_ERR_POS)
+#define SDH_F_ACMD_TO_ERR_UMSK (~(((1U << SDH_F_ACMD_TO_ERR_LEN) - 1) << SDH_F_ACMD_TO_ERR_POS))
+#define SDH_F_ACMD_CRC_ERR SDH_F_ACMD_CRC_ERR
+#define SDH_F_ACMD_CRC_ERR_POS (2U)
+#define SDH_F_ACMD_CRC_ERR_LEN (1U)
+#define SDH_F_ACMD_CRC_ERR_MSK (((1U << SDH_F_ACMD_CRC_ERR_LEN) - 1) << SDH_F_ACMD_CRC_ERR_POS)
+#define SDH_F_ACMD_CRC_ERR_UMSK (~(((1U << SDH_F_ACMD_CRC_ERR_LEN) - 1) << SDH_F_ACMD_CRC_ERR_POS))
+#define SDH_F__ACMD_EBIT_ERR SDH_F__ACMD_EBIT_ERR
+#define SDH_F__ACMD_EBIT_ERR_POS (3U)
+#define SDH_F__ACMD_EBIT_ERR_LEN (1U)
+#define SDH_F__ACMD_EBIT_ERR_MSK (((1U << SDH_F__ACMD_EBIT_ERR_LEN) - 1) << SDH_F__ACMD_EBIT_ERR_POS)
+#define SDH_F__ACMD_EBIT_ERR_UMSK (~(((1U << SDH_F__ACMD_EBIT_ERR_LEN) - 1) << SDH_F__ACMD_EBIT_ERR_POS))
+#define SDH_F_ACMD_INDEX_ERR SDH_F_ACMD_INDEX_ERR
+#define SDH_F_ACMD_INDEX_ERR_POS (4U)
+#define SDH_F_ACMD_INDEX_ERR_LEN (1U)
+#define SDH_F_ACMD_INDEX_ERR_MSK (((1U << SDH_F_ACMD_INDEX_ERR_LEN) - 1) << SDH_F_ACMD_INDEX_ERR_POS)
+#define SDH_F_ACMD_INDEX_ERR_UMSK (~(((1U << SDH_F_ACMD_INDEX_ERR_LEN) - 1) << SDH_F_ACMD_INDEX_ERR_POS))
+#define SDH_F_ACMD12_ISSUE_ERR SDH_F_ACMD12_ISSUE_ERR
+#define SDH_F_ACMD12_ISSUE_ERR_POS (7U)
+#define SDH_F_ACMD12_ISSUE_ERR_LEN (1U)
+#define SDH_F_ACMD12_ISSUE_ERR_MSK (((1U << SDH_F_ACMD12_ISSUE_ERR_LEN) - 1) << SDH_F_ACMD12_ISSUE_ERR_POS)
+#define SDH_F_ACMD12_ISSUE_ERR_UMSK (~(((1U << SDH_F_ACMD12_ISSUE_ERR_LEN) - 1) << SDH_F_ACMD12_ISSUE_ERR_POS))
+
+/* 0x52 : Force Event for Error Status Register */
+#define SDH_SD_FORCE_EVENT_FOR_ERROR_STATUS_OFFSET (0x52)
+#define SDH_F_CMD_TO_ERR SDH_F_CMD_TO_ERR
+#define SDH_F_CMD_TO_ERR_POS (0U)
+#define SDH_F_CMD_TO_ERR_LEN (1U)
+#define SDH_F_CMD_TO_ERR_MSK (((1U << SDH_F_CMD_TO_ERR_LEN) - 1) << SDH_F_CMD_TO_ERR_POS)
+#define SDH_F_CMD_TO_ERR_UMSK (~(((1U << SDH_F_CMD_TO_ERR_LEN) - 1) << SDH_F_CMD_TO_ERR_POS))
+#define SDH_F_CMD_CRC_ERR SDH_F_CMD_CRC_ERR
+#define SDH_F_CMD_CRC_ERR_POS (1U)
+#define SDH_F_CMD_CRC_ERR_LEN (1U)
+#define SDH_F_CMD_CRC_ERR_MSK (((1U << SDH_F_CMD_CRC_ERR_LEN) - 1) << SDH_F_CMD_CRC_ERR_POS)
+#define SDH_F_CMD_CRC_ERR_UMSK (~(((1U << SDH_F_CMD_CRC_ERR_LEN) - 1) << SDH_F_CMD_CRC_ERR_POS))
+#define SDH_F_CMD_END_BIT_ERR SDH_F_CMD_END_BIT_ERR
+#define SDH_F_CMD_END_BIT_ERR_POS (2U)
+#define SDH_F_CMD_END_BIT_ERR_LEN (1U)
+#define SDH_F_CMD_END_BIT_ERR_MSK (((1U << SDH_F_CMD_END_BIT_ERR_LEN) - 1) << SDH_F_CMD_END_BIT_ERR_POS)
+#define SDH_F_CMD_END_BIT_ERR_UMSK (~(((1U << SDH_F_CMD_END_BIT_ERR_LEN) - 1) << SDH_F_CMD_END_BIT_ERR_POS))
+#define SDH_F_CMD_INDEX_ERR SDH_F_CMD_INDEX_ERR
+#define SDH_F_CMD_INDEX_ERR_POS (3U)
+#define SDH_F_CMD_INDEX_ERR_LEN (1U)
+#define SDH_F_CMD_INDEX_ERR_MSK (((1U << SDH_F_CMD_INDEX_ERR_LEN) - 1) << SDH_F_CMD_INDEX_ERR_POS)
+#define SDH_F_CMD_INDEX_ERR_UMSK (~(((1U << SDH_F_CMD_INDEX_ERR_LEN) - 1) << SDH_F_CMD_INDEX_ERR_POS))
+#define SDH_F_DAT_TO_ERR SDH_F_DAT_TO_ERR
+#define SDH_F_DAT_TO_ERR_POS (4U)
+#define SDH_F_DAT_TO_ERR_LEN (1U)
+#define SDH_F_DAT_TO_ERR_MSK (((1U << SDH_F_DAT_TO_ERR_LEN) - 1) << SDH_F_DAT_TO_ERR_POS)
+#define SDH_F_DAT_TO_ERR_UMSK (~(((1U << SDH_F_DAT_TO_ERR_LEN) - 1) << SDH_F_DAT_TO_ERR_POS))
+#define SDH_F_DAT_CRC_ERR SDH_F_DAT_CRC_ERR
+#define SDH_F_DAT_CRC_ERR_POS (5U)
+#define SDH_F_DAT_CRC_ERR_LEN (1U)
+#define SDH_F_DAT_CRC_ERR_MSK (((1U << SDH_F_DAT_CRC_ERR_LEN) - 1) << SDH_F_DAT_CRC_ERR_POS)
+#define SDH_F_DAT_CRC_ERR_UMSK (~(((1U << SDH_F_DAT_CRC_ERR_LEN) - 1) << SDH_F_DAT_CRC_ERR_POS))
+#define SDH_F_DAT_END_BIT_ERR SDH_F_DAT_END_BIT_ERR
+#define SDH_F_DAT_END_BIT_ERR_POS (6U)
+#define SDH_F_DAT_END_BIT_ERR_LEN (1U)
+#define SDH_F_DAT_END_BIT_ERR_MSK (((1U << SDH_F_DAT_END_BIT_ERR_LEN) - 1) << SDH_F_DAT_END_BIT_ERR_POS)
+#define SDH_F_DAT_END_BIT_ERR_UMSK (~(((1U << SDH_F_DAT_END_BIT_ERR_LEN) - 1) << SDH_F_DAT_END_BIT_ERR_POS))
+#define SDH_F_CURRENT_ERR SDH_F_CURRENT_ERR
+#define SDH_F_CURRENT_ERR_POS (7U)
+#define SDH_F_CURRENT_ERR_LEN (1U)
+#define SDH_F_CURRENT_ERR_MSK (((1U << SDH_F_CURRENT_ERR_LEN) - 1) << SDH_F_CURRENT_ERR_POS)
+#define SDH_F_CURRENT_ERR_UMSK (~(((1U << SDH_F_CURRENT_ERR_LEN) - 1) << SDH_F_CURRENT_ERR_POS))
+#define SDH_F_ACMD12_ERR SDH_F_ACMD12_ERR
+#define SDH_F_ACMD12_ERR_POS (8U)
+#define SDH_F_ACMD12_ERR_LEN (1U)
+#define SDH_F_ACMD12_ERR_MSK (((1U << SDH_F_ACMD12_ERR_LEN) - 1) << SDH_F_ACMD12_ERR_POS)
+#define SDH_F_ACMD12_ERR_UMSK (~(((1U << SDH_F_ACMD12_ERR_LEN) - 1) << SDH_F_ACMD12_ERR_POS))
+#define SDH_F_ADMA_ERR SDH_F_ADMA_ERR
+#define SDH_F_ADMA_ERR_POS (9U)
+#define SDH_F_ADMA_ERR_LEN (1U)
+#define SDH_F_ADMA_ERR_MSK (((1U << SDH_F_ADMA_ERR_LEN) - 1) << SDH_F_ADMA_ERR_POS)
+#define SDH_F_ADMA_ERR_UMSK (~(((1U << SDH_F_ADMA_ERR_LEN) - 1) << SDH_F_ADMA_ERR_POS))
+#define SDH_F_SPI_ERR SDH_F_SPI_ERR
+#define SDH_F_SPI_ERR_POS (12U)
+#define SDH_F_SPI_ERR_LEN (1U)
+#define SDH_F_SPI_ERR_MSK (((1U << SDH_F_SPI_ERR_LEN) - 1) << SDH_F_SPI_ERR_POS)
+#define SDH_F_SPI_ERR_UMSK (~(((1U << SDH_F_SPI_ERR_LEN) - 1) << SDH_F_SPI_ERR_POS))
+#define SDH_F_AXI_RESP_ERR SDH_F_AXI_RESP_ERR
+#define SDH_F_AXI_RESP_ERR_POS (13U)
+#define SDH_F_AXI_RESP_ERR_LEN (1U)
+#define SDH_F_AXI_RESP_ERR_MSK (((1U << SDH_F_AXI_RESP_ERR_LEN) - 1) << SDH_F_AXI_RESP_ERR_POS)
+#define SDH_F_AXI_RESP_ERR_UMSK (~(((1U << SDH_F_AXI_RESP_ERR_LEN) - 1) << SDH_F_AXI_RESP_ERR_POS))
+#define SDH_F_CPL_TIMEOUT_ERR SDH_F_CPL_TIMEOUT_ERR
+#define SDH_F_CPL_TIMEOUT_ERR_POS (14U)
+#define SDH_F_CPL_TIMEOUT_ERR_LEN (1U)
+#define SDH_F_CPL_TIMEOUT_ERR_MSK (((1U << SDH_F_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_F_CPL_TIMEOUT_ERR_POS)
+#define SDH_F_CPL_TIMEOUT_ERR_UMSK (~(((1U << SDH_F_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_F_CPL_TIMEOUT_ERR_POS))
+#define SDH_F_CRC_STATUS_ERR SDH_F_CRC_STATUS_ERR
+#define SDH_F_CRC_STATUS_ERR_POS (15U)
+#define SDH_F_CRC_STATUS_ERR_LEN (1U)
+#define SDH_F_CRC_STATUS_ERR_MSK (((1U << SDH_F_CRC_STATUS_ERR_LEN) - 1) << SDH_F_CRC_STATUS_ERR_POS)
+#define SDH_F_CRC_STATUS_ERR_UMSK (~(((1U << SDH_F_CRC_STATUS_ERR_LEN) - 1) << SDH_F_CRC_STATUS_ERR_POS))
+
+/* 0x54 : ADMA Error Status Register */
+#define SDH_SD_ADMA_ERROR_STATUS_OFFSET (0x54)
+#define SDH_ADMA_STATE SDH_ADMA_STATE
+#define SDH_ADMA_STATE_POS (0U)
+#define SDH_ADMA_STATE_LEN (2U)
+#define SDH_ADMA_STATE_MSK (((1U << SDH_ADMA_STATE_LEN) - 1) << SDH_ADMA_STATE_POS)
+#define SDH_ADMA_STATE_UMSK (~(((1U << SDH_ADMA_STATE_LEN) - 1) << SDH_ADMA_STATE_POS))
+#define SDH_ADMA_LEN_ERR SDH_ADMA_LEN_ERR
+#define SDH_ADMA_LEN_ERR_POS (2U)
+#define SDH_ADMA_LEN_ERR_LEN (1U)
+#define SDH_ADMA_LEN_ERR_MSK (((1U << SDH_ADMA_LEN_ERR_LEN) - 1) << SDH_ADMA_LEN_ERR_POS)
+#define SDH_ADMA_LEN_ERR_UMSK (~(((1U << SDH_ADMA_LEN_ERR_LEN) - 1) << SDH_ADMA_LEN_ERR_POS))
+
+/* 0x58 : ADMA System Address Register 1 */
+#define SDH_SD_ADMA_SYS_ADDR_1_OFFSET (0x58)
+#define SDH_ADMA_SYS_ADDR SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS (0U)
+#define SDH_ADMA_SYS_ADDR_LEN (16U)
+#define SDH_ADMA_SYS_ADDR_MSK (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x5A : ADMA System Address Register 2 */
+#define SDH_SD_ADMA_SYS_ADDR_2_OFFSET (0x5A)
+#define SDH_ADMA_SYS_ADDR SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS (0U)
+#define SDH_ADMA_SYS_ADDR_LEN (16U)
+#define SDH_ADMA_SYS_ADDR_MSK (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x5C : ADMA System Address Register 3 */
+#define SDH_SD_ADMA_SYS_ADDR_3_OFFSET (0x5C)
+#define SDH_ADMA_SYS_ADDR SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS (0U)
+#define SDH_ADMA_SYS_ADDR_LEN (16U)
+#define SDH_ADMA_SYS_ADDR_MSK (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x5E : ADMA System Address Register 4 */
+#define SDH_SD_ADMA_SYS_ADDR_4_OFFSET (0x5E)
+#define SDH_ADMA_SYS_ADDR SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS (0U)
+#define SDH_ADMA_SYS_ADDR_LEN (16U)
+#define SDH_ADMA_SYS_ADDR_MSK (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x60 : Preset Value Register for Initialization */
+#define SDH_PRESET_VALUE_FOR_INIT_OFFSET (0x60)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x62 : Preset Value Register for Default Speed */
+#define SDH_PRESET_VALUE_FOR_DS_OFFSET (0x62)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x64 : Preset Value Register for High Speed */
+#define SDH_PRESET_VALUE_FOR_HS_OFFSET (0x64)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x66 : Preset Value Register for SDR12 */
+#define SDH_PRESET_VALUE_FOR_SDR12_OFFSET (0x66)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x68 : Preset Value Register for SDR25 */
+#define SDH_PRESET_VALUE_FOR_SDR25_OFFSET (0x68)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x6a : Preset Value Register for SDR50 */
+#define SDH_PRESET_VALUE_FOR_SDR50_OFFSET (0x6a)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x6c : Preset Value Register for SDR104 */
+#define SDH_PRESET_VALUE_FOR_SDR104_OFFSET (0x6c)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x6e : Preset Value Register for DDR50 */
+#define SDH_PRESET_VALUE_FOR_DDR50_OFFSET (0x6e)
+#define SDH_SDCLK_FREQ_SEL_VAL SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0xe0 : Shared Bus Control Register */
+#define SDH_SHARED_BUS_CTRL_OFFSET (0xe0)
+#define SDH_NUM_CLK_PINS SDH_NUM_CLK_PINS
+#define SDH_NUM_CLK_PINS_POS (0U)
+#define SDH_NUM_CLK_PINS_LEN (3U)
+#define SDH_NUM_CLK_PINS_MSK (((1U << SDH_NUM_CLK_PINS_LEN) - 1) << SDH_NUM_CLK_PINS_POS)
+#define SDH_NUM_CLK_PINS_UMSK (~(((1U << SDH_NUM_CLK_PINS_LEN) - 1) << SDH_NUM_CLK_PINS_POS))
+#define SDH_NUM_INT_PINS SDH_NUM_INT_PINS
+#define SDH_NUM_INT_PINS_POS (4U)
+#define SDH_NUM_INT_PINS_LEN (2U)
+#define SDH_NUM_INT_PINS_MSK (((1U << SDH_NUM_INT_PINS_LEN) - 1) << SDH_NUM_INT_PINS_POS)
+#define SDH_NUM_INT_PINS_UMSK (~(((1U << SDH_NUM_INT_PINS_LEN) - 1) << SDH_NUM_INT_PINS_POS))
+#define SDH_BUS_WIDTH_PRESET SDH_BUS_WIDTH_PRESET
+#define SDH_BUS_WIDTH_PRESET_POS (8U)
+#define SDH_BUS_WIDTH_PRESET_LEN (7U)
+#define SDH_BUS_WIDTH_PRESET_MSK (((1U << SDH_BUS_WIDTH_PRESET_LEN) - 1) << SDH_BUS_WIDTH_PRESET_POS)
+#define SDH_BUS_WIDTH_PRESET_UMSK (~(((1U << SDH_BUS_WIDTH_PRESET_LEN) - 1) << SDH_BUS_WIDTH_PRESET_POS))
+#define SDH_CLK_PIN_SEL SDH_CLK_PIN_SEL
+#define SDH_CLK_PIN_SEL_POS (16U)
+#define SDH_CLK_PIN_SEL_LEN (3U)
+#define SDH_CLK_PIN_SEL_MSK (((1U << SDH_CLK_PIN_SEL_LEN) - 1) << SDH_CLK_PIN_SEL_POS)
+#define SDH_CLK_PIN_SEL_UMSK (~(((1U << SDH_CLK_PIN_SEL_LEN) - 1) << SDH_CLK_PIN_SEL_POS))
+#define SDH_INT_PIN_SEL SDH_INT_PIN_SEL
+#define SDH_INT_PIN_SEL_POS (20U)
+#define SDH_INT_PIN_SEL_LEN (3U)
+#define SDH_INT_PIN_SEL_MSK (((1U << SDH_INT_PIN_SEL_LEN) - 1) << SDH_INT_PIN_SEL_POS)
+#define SDH_INT_PIN_SEL_UMSK (~(((1U << SDH_INT_PIN_SEL_LEN) - 1) << SDH_INT_PIN_SEL_POS))
+#define SDH_BEND_PWR_CTRL SDH_BEND_PWR_CTRL
+#define SDH_BEND_PWR_CTRL_POS (24U)
+#define SDH_BEND_PWR_CTRL_LEN (7U)
+#define SDH_BEND_PWR_CTRL_MSK (((1U << SDH_BEND_PWR_CTRL_LEN) - 1) << SDH_BEND_PWR_CTRL_POS)
+#define SDH_BEND_PWR_CTRL_UMSK (~(((1U << SDH_BEND_PWR_CTRL_LEN) - 1) << SDH_BEND_PWR_CTRL_POS))
+
+/* 0xFC : Slot Interrupt Status Register */
+#define SDH_SD_SLOT_INT_STATUS_OFFSET (0xFC)
+#define SDH_SLOT_INT0 SDH_SLOT_INT0
+#define SDH_SLOT_INT0_POS (0U)
+#define SDH_SLOT_INT0_LEN (1U)
+#define SDH_SLOT_INT0_MSK (((1U << SDH_SLOT_INT0_LEN) - 1) << SDH_SLOT_INT0_POS)
+#define SDH_SLOT_INT0_UMSK (~(((1U << SDH_SLOT_INT0_LEN) - 1) << SDH_SLOT_INT0_POS))
+#define SDH_SLOT_INT1 SDH_SLOT_INT1
+#define SDH_SLOT_INT1_POS (1U)
+#define SDH_SLOT_INT1_LEN (1U)
+#define SDH_SLOT_INT1_MSK (((1U << SDH_SLOT_INT1_LEN) - 1) << SDH_SLOT_INT1_POS)
+#define SDH_SLOT_INT1_UMSK (~(((1U << SDH_SLOT_INT1_LEN) - 1) << SDH_SLOT_INT1_POS))
+
+/* 0xFE : Host Control Version Register */
+#define SDH_SD_HOST_CTRL_VER_OFFSET (0xFE)
+#define SDH_SD_VER SDH_SD_VER
+#define SDH_SD_VER_POS (0U)
+#define SDH_SD_VER_LEN (8U)
+#define SDH_SD_VER_MSK (((1U << SDH_SD_VER_LEN) - 1) << SDH_SD_VER_POS)
+#define SDH_SD_VER_UMSK (~(((1U << SDH_SD_VER_LEN) - 1) << SDH_SD_VER_POS))
+#define SDH_VENDOR_VER SDH_VENDOR_VER
+#define SDH_VENDOR_VER_POS (8U)
+#define SDH_VENDOR_VER_LEN (8U)
+#define SDH_VENDOR_VER_MSK (((1U << SDH_VENDOR_VER_LEN) - 1) << SDH_VENDOR_VER_POS)
+#define SDH_VENDOR_VER_UMSK (~(((1U << SDH_VENDOR_VER_LEN) - 1) << SDH_VENDOR_VER_POS))
+
+/* 0x100 : SD Extra Parameters Register */
+#define SDH_SD_CFG_FIFO_PARAM_OFFSET (0x100)
+#define SDH_BOOT_ACK SDH_BOOT_ACK
+#define SDH_BOOT_ACK_POS (3U)
+#define SDH_BOOT_ACK_LEN (1U)
+#define SDH_BOOT_ACK_MSK (((1U << SDH_BOOT_ACK_LEN) - 1) << SDH_BOOT_ACK_POS)
+#define SDH_BOOT_ACK_UMSK (~(((1U << SDH_BOOT_ACK_LEN) - 1) << SDH_BOOT_ACK_POS))
+#define SDH_SQU_EMPTY_CHK SDH_SQU_EMPTY_CHK
+#define SDH_SQU_EMPTY_CHK_POS (4U)
+#define SDH_SQU_EMPTY_CHK_LEN (1U)
+#define SDH_SQU_EMPTY_CHK_MSK (((1U << SDH_SQU_EMPTY_CHK_LEN) - 1) << SDH_SQU_EMPTY_CHK_POS)
+#define SDH_SQU_EMPTY_CHK_UMSK (~(((1U << SDH_SQU_EMPTY_CHK_LEN) - 1) << SDH_SQU_EMPTY_CHK_POS))
+#define SDH_SQU_FULL_CHK SDH_SQU_FULL_CHK
+#define SDH_SQU_FULL_CHK_POS (5U)
+#define SDH_SQU_FULL_CHK_LEN (1U)
+#define SDH_SQU_FULL_CHK_MSK (((1U << SDH_SQU_FULL_CHK_LEN) - 1) << SDH_SQU_FULL_CHK_POS)
+#define SDH_SQU_FULL_CHK_UMSK (~(((1U << SDH_SQU_FULL_CHK_LEN) - 1) << SDH_SQU_FULL_CHK_POS))
+#define SDH_GEN_PAD_CLK_ON SDH_GEN_PAD_CLK_ON
+#define SDH_GEN_PAD_CLK_ON_POS (6U)
+#define SDH_GEN_PAD_CLK_ON_LEN (1U)
+#define SDH_GEN_PAD_CLK_ON_MSK (((1U << SDH_GEN_PAD_CLK_ON_LEN) - 1) << SDH_GEN_PAD_CLK_ON_POS)
+#define SDH_GEN_PAD_CLK_ON_UMSK (~(((1U << SDH_GEN_PAD_CLK_ON_LEN) - 1) << SDH_GEN_PAD_CLK_ON_POS))
+#define SDH_GEN_PAD_CLK_CNT SDH_GEN_PAD_CLK_CNT
+#define SDH_GEN_PAD_CLK_CNT_POS (24U)
+#define SDH_GEN_PAD_CLK_CNT_LEN (8U)
+#define SDH_GEN_PAD_CLK_CNT_MSK (((1U << SDH_GEN_PAD_CLK_CNT_LEN) - 1) << SDH_GEN_PAD_CLK_CNT_POS)
+#define SDH_GEN_PAD_CLK_CNT_UMSK (~(((1U << SDH_GEN_PAD_CLK_CNT_LEN) - 1) << SDH_GEN_PAD_CLK_CNT_POS))
+
+/* 0x104 : FIFO Parameters Register */
+#define SDH_SD_FIFO_PARAM_OFFSET (0x104)
+#define SDH_RTC SDH_RTC
+#define SDH_RTC_POS (0U)
+#define SDH_RTC_LEN (2U)
+#define SDH_RTC_MSK (((1U << SDH_RTC_LEN) - 1) << SDH_RTC_POS)
+#define SDH_RTC_UMSK (~(((1U << SDH_RTC_LEN) - 1) << SDH_RTC_POS))
+#define SDH_WTC SDH_WTC
+#define SDH_WTC_POS (2U)
+#define SDH_WTC_LEN (2U)
+#define SDH_WTC_MSK (((1U << SDH_WTC_LEN) - 1) << SDH_WTC_POS)
+#define SDH_WTC_UMSK (~(((1U << SDH_WTC_LEN) - 1) << SDH_WTC_POS))
+#define SDH_FIFO_CLK SDH_FIFO_CLK
+#define SDH_FIFO_CLK_POS (4U)
+#define SDH_FIFO_CLK_LEN (1U)
+#define SDH_FIFO_CLK_MSK (((1U << SDH_FIFO_CLK_LEN) - 1) << SDH_FIFO_CLK_POS)
+#define SDH_FIFO_CLK_UMSK (~(((1U << SDH_FIFO_CLK_LEN) - 1) << SDH_FIFO_CLK_POS))
+#define SDH_FIFO_CS SDH_FIFO_CS
+#define SDH_FIFO_CS_POS (5U)
+#define SDH_FIFO_CS_LEN (1U)
+#define SDH_FIFO_CS_MSK (((1U << SDH_FIFO_CS_LEN) - 1) << SDH_FIFO_CS_POS)
+#define SDH_FIFO_CS_UMSK (~(((1U << SDH_FIFO_CS_LEN) - 1) << SDH_FIFO_CS_POS))
+#define SDH_PDWN SDH_PDWN
+#define SDH_PDWN_POS (6U)
+#define SDH_PDWN_LEN (1U)
+#define SDH_PDWN_MSK (((1U << SDH_PDWN_LEN) - 1) << SDH_PDWN_POS)
+#define SDH_PDWN_UMSK (~(((1U << SDH_PDWN_LEN) - 1) << SDH_PDWN_POS))
+#define SDH_USE_DAT3 SDH_USE_DAT3
+#define SDH_USE_DAT3_POS (7U)
+#define SDH_USE_DAT3_LEN (1U)
+#define SDH_USE_DAT3_MSK (((1U << SDH_USE_DAT3_LEN) - 1) << SDH_USE_DAT3_POS)
+#define SDH_USE_DAT3_UMSK (~(((1U << SDH_USE_DAT3_LEN) - 1) << SDH_USE_DAT3_POS))
+#define SDH_CLK_GATE_CTL SDH_CLK_GATE_CTL
+#define SDH_CLK_GATE_CTL_POS (8U)
+#define SDH_CLK_GATE_CTL_LEN (1U)
+#define SDH_CLK_GATE_CTL_MSK (((1U << SDH_CLK_GATE_CTL_LEN) - 1) << SDH_CLK_GATE_CTL_POS)
+#define SDH_CLK_GATE_CTL_UMSK (~(((1U << SDH_CLK_GATE_CTL_LEN) - 1) << SDH_CLK_GATE_CTL_POS))
+#define SDH_CLK_GATE_ON SDH_CLK_GATE_ON
+#define SDH_CLK_GATE_ON_POS (9U)
+#define SDH_CLK_GATE_ON_LEN (1U)
+#define SDH_CLK_GATE_ON_MSK (((1U << SDH_CLK_GATE_ON_LEN) - 1) << SDH_CLK_GATE_ON_POS)
+#define SDH_CLK_GATE_ON_UMSK (~(((1U << SDH_CLK_GATE_ON_LEN) - 1) << SDH_CLK_GATE_ON_POS))
+#define SDH_OVRRD_CLK_OEN SDH_OVRRD_CLK_OEN
+#define SDH_OVRRD_CLK_OEN_POS (11U)
+#define SDH_OVRRD_CLK_OEN_LEN (1U)
+#define SDH_OVRRD_CLK_OEN_MSK (((1U << SDH_OVRRD_CLK_OEN_LEN) - 1) << SDH_OVRRD_CLK_OEN_POS)
+#define SDH_OVRRD_CLK_OEN_UMSK (~(((1U << SDH_OVRRD_CLK_OEN_LEN) - 1) << SDH_OVRRD_CLK_OEN_POS))
+#define SDH_FORCE_CLK_ON SDH_FORCE_CLK_ON
+#define SDH_FORCE_CLK_ON_POS (12U)
+#define SDH_FORCE_CLK_ON_LEN (1U)
+#define SDH_FORCE_CLK_ON_MSK (((1U << SDH_FORCE_CLK_ON_LEN) - 1) << SDH_FORCE_CLK_ON_POS)
+#define SDH_FORCE_CLK_ON_UMSK (~(((1U << SDH_FORCE_CLK_ON_LEN) - 1) << SDH_FORCE_CLK_ON_POS))
+#define SDH_PDFVSSM SDH_PDFVSSM
+#define SDH_PDFVSSM_POS (13U)
+#define SDH_PDFVSSM_LEN (1U)
+#define SDH_PDFVSSM_MSK (((1U << SDH_PDFVSSM_LEN) - 1) << SDH_PDFVSSM_POS)
+#define SDH_PDFVSSM_UMSK (~(((1U << SDH_PDFVSSM_LEN) - 1) << SDH_PDFVSSM_POS))
+#define SDH_PDLVMC SDH_PDLVMC
+#define SDH_PDLVMC_POS (14U)
+#define SDH_PDLVMC_LEN (1U)
+#define SDH_PDLVMC_MSK (((1U << SDH_PDLVMC_LEN) - 1) << SDH_PDLVMC_POS)
+#define SDH_PDLVMC_UMSK (~(((1U << SDH_PDLVMC_LEN) - 1) << SDH_PDLVMC_POS))
+#define SDH_PRE_GATE_CLK_CNT SDH_PRE_GATE_CLK_CNT
+#define SDH_PRE_GATE_CLK_CNT_POS (16U)
+#define SDH_PRE_GATE_CLK_CNT_LEN (4U)
+#define SDH_PRE_GATE_CLK_CNT_MSK (((1U << SDH_PRE_GATE_CLK_CNT_LEN) - 1) << SDH_PRE_GATE_CLK_CNT_POS)
+#define SDH_PRE_GATE_CLK_CNT_UMSK (~(((1U << SDH_PRE_GATE_CLK_CNT_LEN) - 1) << SDH_PRE_GATE_CLK_CNT_POS))
+
+/* 0x108 : SPI Mode Register */
+#define SDH_SD_SPI_MODE_OFFSET (0x108)
+#define SDH_SPI_EN SDH_SPI_EN
+#define SDH_SPI_EN_POS (0U)
+#define SDH_SPI_EN_LEN (1U)
+#define SDH_SPI_EN_MSK (((1U << SDH_SPI_EN_LEN) - 1) << SDH_SPI_EN_POS)
+#define SDH_SPI_EN_UMSK (~(((1U << SDH_SPI_EN_LEN) - 1) << SDH_SPI_EN_POS))
+#define SDH_SPI_ERR_TOKEN SDH_SPI_ERR_TOKEN
+#define SDH_SPI_ERR_TOKEN_POS (8U)
+#define SDH_SPI_ERR_TOKEN_LEN (5U)
+#define SDH_SPI_ERR_TOKEN_MSK (((1U << SDH_SPI_ERR_TOKEN_LEN) - 1) << SDH_SPI_ERR_TOKEN_POS)
+#define SDH_SPI_ERR_TOKEN_UMSK (~(((1U << SDH_SPI_ERR_TOKEN_LEN) - 1) << SDH_SPI_ERR_TOKEN_POS))
+
+/* 0x10a : Clock and Burst Size Setup Register */
+#define SDH_SD_CLOCK_AND_BURST_SIZE_SETUP_OFFSET (0x10a)
+#define SDH_BRST_SIZE SDH_BRST_SIZE
+#define SDH_BRST_SIZE_POS (0U)
+#define SDH_BRST_SIZE_LEN (2U)
+#define SDH_BRST_SIZE_MSK (((1U << SDH_BRST_SIZE_LEN) - 1) << SDH_BRST_SIZE_POS)
+#define SDH_BRST_SIZE_UMSK (~(((1U << SDH_BRST_SIZE_LEN) - 1) << SDH_BRST_SIZE_POS))
+#define SDH_DMA_SIZE SDH_DMA_SIZE
+#define SDH_DMA_SIZE_POS (2U)
+#define SDH_DMA_SIZE_LEN (2U)
+#define SDH_DMA_SIZE_MSK (((1U << SDH_DMA_SIZE_LEN) - 1) << SDH_DMA_SIZE_POS)
+#define SDH_DMA_SIZE_UMSK (~(((1U << SDH_DMA_SIZE_LEN) - 1) << SDH_DMA_SIZE_POS))
+#define SDH_PRIORITY SDH_PRIORITY
+#define SDH_PRIORITY_POS (4U)
+#define SDH_PRIORITY_LEN (1U)
+#define SDH_PRIORITY_MSK (((1U << SDH_PRIORITY_LEN) - 1) << SDH_PRIORITY_POS)
+#define SDH_PRIORITY_UMSK (~(((1U << SDH_PRIORITY_LEN) - 1) << SDH_PRIORITY_POS))
+#define SDH_AXI_NON_POST_WR SDH_AXI_NON_POST_WR
+#define SDH_AXI_NON_POST_WR_POS (5U)
+#define SDH_AXI_NON_POST_WR_LEN (1U)
+#define SDH_AXI_NON_POST_WR_MSK (((1U << SDH_AXI_NON_POST_WR_LEN) - 1) << SDH_AXI_NON_POST_WR_POS)
+#define SDH_AXI_NON_POST_WR_UMSK (~(((1U << SDH_AXI_NON_POST_WR_LEN) - 1) << SDH_AXI_NON_POST_WR_POS))
+#define SDH_RD_ENDIAN SDH_RD_ENDIAN
+#define SDH_RD_ENDIAN_POS (6U)
+#define SDH_RD_ENDIAN_LEN (1U)
+#define SDH_RD_ENDIAN_MSK (((1U << SDH_RD_ENDIAN_LEN) - 1) << SDH_RD_ENDIAN_POS)
+#define SDH_RD_ENDIAN_UMSK (~(((1U << SDH_RD_ENDIAN_LEN) - 1) << SDH_RD_ENDIAN_POS))
+#define SDH_WR_ENDIAN SDH_WR_ENDIAN
+#define SDH_WR_ENDIAN_POS (7U)
+#define SDH_WR_ENDIAN_LEN (1U)
+#define SDH_WR_ENDIAN_MSK (((1U << SDH_WR_ENDIAN_LEN) - 1) << SDH_WR_ENDIAN_POS)
+#define SDH_WR_ENDIAN_UMSK (~(((1U << SDH_WR_ENDIAN_LEN) - 1) << SDH_WR_ENDIAN_POS))
+#define SDH_RD_OSTDG SDH_RD_OSTDG
+#define SDH_RD_OSTDG_POS (14U)
+#define SDH_RD_OSTDG_LEN (1U)
+#define SDH_RD_OSTDG_MSK (((1U << SDH_RD_OSTDG_LEN) - 1) << SDH_RD_OSTDG_POS)
+#define SDH_RD_OSTDG_UMSK (~(((1U << SDH_RD_OSTDG_LEN) - 1) << SDH_RD_OSTDG_POS))
+#define SDH_WR_OSTDG SDH_WR_OSTDG
+#define SDH_WR_OSTDG_POS (15U)
+#define SDH_WR_OSTDG_LEN (1U)
+#define SDH_WR_OSTDG_MSK (((1U << SDH_WR_OSTDG_LEN) - 1) << SDH_WR_OSTDG_POS)
+#define SDH_WR_OSTDG_UMSK (~(((1U << SDH_WR_OSTDG_LEN) - 1) << SDH_WR_OSTDG_POS))
+
+/* 0x10c : CE-ATA Register 1 */
+#define SDH_SD_CE_ATA_1_OFFSET (0x10c)
+#define SDH_CPL_TIMEOUT SDH_CPL_TIMEOUT
+#define SDH_CPL_TIMEOUT_POS (0U)
+#define SDH_CPL_TIMEOUT_LEN (14U)
+#define SDH_CPL_TIMEOUT_MSK (((1U << SDH_CPL_TIMEOUT_LEN) - 1) << SDH_CPL_TIMEOUT_POS)
+#define SDH_CPL_TIMEOUT_UMSK (~(((1U << SDH_CPL_TIMEOUT_LEN) - 1) << SDH_CPL_TIMEOUT_POS))
+
+/* 0x10e : CE-ATA Register 2 */
+#define SDH_SD_CE_ATA_2_OFFSET (0x10e)
+#define SDH_MISC_INT_INT_EN SDH_MISC_INT_INT_EN
+#define SDH_MISC_INT_INT_EN_POS (0U)
+#define SDH_MISC_INT_INT_EN_LEN (1U)
+#define SDH_MISC_INT_INT_EN_MSK (((1U << SDH_MISC_INT_INT_EN_LEN) - 1) << SDH_MISC_INT_INT_EN_POS)
+#define SDH_MISC_INT_INT_EN_UMSK (~(((1U << SDH_MISC_INT_INT_EN_LEN) - 1) << SDH_MISC_INT_INT_EN_POS))
+#define SDH_MISC_INT_EN SDH_MISC_INT_EN
+#define SDH_MISC_INT_EN_POS (1U)
+#define SDH_MISC_INT_EN_LEN (1U)
+#define SDH_MISC_INT_EN_MSK (((1U << SDH_MISC_INT_EN_LEN) - 1) << SDH_MISC_INT_EN_POS)
+#define SDH_MISC_INT_EN_UMSK (~(((1U << SDH_MISC_INT_EN_LEN) - 1) << SDH_MISC_INT_EN_POS))
+#define SDH_MISC_INT SDH_MISC_INT
+#define SDH_MISC_INT_POS (2U)
+#define SDH_MISC_INT_LEN (1U)
+#define SDH_MISC_INT_MSK (((1U << SDH_MISC_INT_LEN) - 1) << SDH_MISC_INT_POS)
+#define SDH_MISC_INT_UMSK (~(((1U << SDH_MISC_INT_LEN) - 1) << SDH_MISC_INT_POS))
+#define SDH_CPL_COMPLETE_INT_EN SDH_CPL_COMPLETE_INT_EN
+#define SDH_CPL_COMPLETE_INT_EN_POS (4U)
+#define SDH_CPL_COMPLETE_INT_EN_LEN (1U)
+#define SDH_CPL_COMPLETE_INT_EN_MSK (((1U << SDH_CPL_COMPLETE_INT_EN_LEN) - 1) << SDH_CPL_COMPLETE_INT_EN_POS)
+#define SDH_CPL_COMPLETE_INT_EN_UMSK (~(((1U << SDH_CPL_COMPLETE_INT_EN_LEN) - 1) << SDH_CPL_COMPLETE_INT_EN_POS))
+#define SDH_CPL_COMPLETE_EN SDH_CPL_COMPLETE_EN
+#define SDH_CPL_COMPLETE_EN_POS (5U)
+#define SDH_CPL_COMPLETE_EN_LEN (1U)
+#define SDH_CPL_COMPLETE_EN_MSK (((1U << SDH_CPL_COMPLETE_EN_LEN) - 1) << SDH_CPL_COMPLETE_EN_POS)
+#define SDH_CPL_COMPLETE_EN_UMSK (~(((1U << SDH_CPL_COMPLETE_EN_LEN) - 1) << SDH_CPL_COMPLETE_EN_POS))
+#define SDH_CPL_COMPLETE SDH_CPL_COMPLETE
+#define SDH_CPL_COMPLETE_POS (6U)
+#define SDH_CPL_COMPLETE_LEN (1U)
+#define SDH_CPL_COMPLETE_MSK (((1U << SDH_CPL_COMPLETE_LEN) - 1) << SDH_CPL_COMPLETE_POS)
+#define SDH_CPL_COMPLETE_UMSK (~(((1U << SDH_CPL_COMPLETE_LEN) - 1) << SDH_CPL_COMPLETE_POS))
+#define SDH_MMC_RESETN SDH_MMC_RESETN
+#define SDH_MMC_RESETN_POS (11U)
+#define SDH_MMC_RESETN_LEN (1U)
+#define SDH_MMC_RESETN_MSK (((1U << SDH_MMC_RESETN_LEN) - 1) << SDH_MMC_RESETN_POS)
+#define SDH_MMC_RESETN_UMSK (~(((1U << SDH_MMC_RESETN_LEN) - 1) << SDH_MMC_RESETN_POS))
+#define SDH_MMC_CARD SDH_MMC_CARD
+#define SDH_MMC_CARD_POS (12U)
+#define SDH_MMC_CARD_LEN (1U)
+#define SDH_MMC_CARD_MSK (((1U << SDH_MMC_CARD_LEN) - 1) << SDH_MMC_CARD_POS)
+#define SDH_MMC_CARD_UMSK (~(((1U << SDH_MMC_CARD_LEN) - 1) << SDH_MMC_CARD_POS))
+#define SDH_CEATA_CARD SDH_CEATA_CARD
+#define SDH_CEATA_CARD_POS (13U)
+#define SDH_CEATA_CARD_LEN (1U)
+#define SDH_CEATA_CARD_MSK (((1U << SDH_CEATA_CARD_LEN) - 1) << SDH_CEATA_CARD_POS)
+#define SDH_CEATA_CARD_UMSK (~(((1U << SDH_CEATA_CARD_LEN) - 1) << SDH_CEATA_CARD_POS))
+#define SDH_SND_CPL SDH_SND_CPL
+#define SDH_SND_CPL_POS (14U)
+#define SDH_SND_CPL_LEN (1U)
+#define SDH_SND_CPL_MSK (((1U << SDH_SND_CPL_LEN) - 1) << SDH_SND_CPL_POS)
+#define SDH_SND_CPL_UMSK (~(((1U << SDH_SND_CPL_LEN) - 1) << SDH_SND_CPL_POS))
+#define SDH_CHK_CPL SDH_CHK_CPL
+#define SDH_CHK_CPL_POS (15U)
+#define SDH_CHK_CPL_LEN (1U)
+#define SDH_CHK_CPL_MSK (((1U << SDH_CHK_CPL_LEN) - 1) << SDH_CHK_CPL_POS)
+#define SDH_CHK_CPL_UMSK (~(((1U << SDH_CHK_CPL_LEN) - 1) << SDH_CHK_CPL_POS))
+
+/* 0x110 : PAD I/O Setup Register */
+#define SDH_SD_PAD_IO_SETUP_OFFSET (0x110)
+#define SDH_ASYNC_IO_EN SDH_ASYNC_IO_EN
+#define SDH_ASYNC_IO_EN_POS (0U)
+#define SDH_ASYNC_IO_EN_LEN (1U)
+#define SDH_ASYNC_IO_EN_MSK (((1U << SDH_ASYNC_IO_EN_LEN) - 1) << SDH_ASYNC_IO_EN_POS)
+#define SDH_ASYNC_IO_EN_UMSK (~(((1U << SDH_ASYNC_IO_EN_LEN) - 1) << SDH_ASYNC_IO_EN_POS))
+#define SDH_INAND_SEL SDH_INAND_SEL
+#define SDH_INAND_SEL_POS (1U)
+#define SDH_INAND_SEL_LEN (1U)
+#define SDH_INAND_SEL_MSK (((1U << SDH_INAND_SEL_LEN) - 1) << SDH_INAND_SEL_POS)
+#define SDH_INAND_SEL_UMSK (~(((1U << SDH_INAND_SEL_LEN) - 1) << SDH_INAND_SEL_POS))
+#define SDH_ECO_REG SDH_ECO_REG
+#define SDH_ECO_REG_POS (16U)
+#define SDH_ECO_REG_LEN (8U)
+#define SDH_ECO_REG_MSK (((1U << SDH_ECO_REG_LEN) - 1) << SDH_ECO_REG_POS)
+#define SDH_ECO_REG_UMSK (~(((1U << SDH_ECO_REG_LEN) - 1) << SDH_ECO_REG_POS))
+
+/* 0x114 : RX Configuration Register */
+#define SDH_RX_CFG_REG_OFFSET (0x114)
+#define SDH_SDCLK_SEL0 SDH_SDCLK_SEL0
+#define SDH_SDCLK_SEL0_POS (0U)
+#define SDH_SDCLK_SEL0_LEN (2U)
+#define SDH_SDCLK_SEL0_MSK (((1U << SDH_SDCLK_SEL0_LEN) - 1) << SDH_SDCLK_SEL0_POS)
+#define SDH_SDCLK_SEL0_UMSK (~(((1U << SDH_SDCLK_SEL0_LEN) - 1) << SDH_SDCLK_SEL0_POS))
+#define SDH_SDCLK_SEL1 SDH_SDCLK_SEL1
+#define SDH_SDCLK_SEL1_POS (2U)
+#define SDH_SDCLK_SEL1_LEN (2U)
+#define SDH_SDCLK_SEL1_MSK (((1U << SDH_SDCLK_SEL1_LEN) - 1) << SDH_SDCLK_SEL1_POS)
+#define SDH_SDCLK_SEL1_UMSK (~(((1U << SDH_SDCLK_SEL1_LEN) - 1) << SDH_SDCLK_SEL1_POS))
+#define SDH_SDCLK_DELAY SDH_SDCLK_DELAY
+#define SDH_SDCLK_DELAY_POS (8U)
+#define SDH_SDCLK_DELAY_LEN (10U)
+#define SDH_SDCLK_DELAY_MSK (((1U << SDH_SDCLK_DELAY_LEN) - 1) << SDH_SDCLK_DELAY_POS)
+#define SDH_SDCLK_DELAY_UMSK (~(((1U << SDH_SDCLK_DELAY_LEN) - 1) << SDH_SDCLK_DELAY_POS))
+#define SDH_TUNING_DLY_INC SDH_TUNING_DLY_INC
+#define SDH_TUNING_DLY_INC_POS (18U)
+#define SDH_TUNING_DLY_INC_LEN (10U)
+#define SDH_TUNING_DLY_INC_MSK (((1U << SDH_TUNING_DLY_INC_LEN) - 1) << SDH_TUNING_DLY_INC_POS)
+#define SDH_TUNING_DLY_INC_UMSK (~(((1U << SDH_TUNING_DLY_INC_LEN) - 1) << SDH_TUNING_DLY_INC_POS))
+
+/* 0x118 : TX Configuration Register */
+#define SDH_TX_CFG_REG_OFFSET (0x118)
+#define SDH_TX_HOLD_DELAY0 SDH_TX_HOLD_DELAY0
+#define SDH_TX_HOLD_DELAY0_POS (0U)
+#define SDH_TX_HOLD_DELAY0_LEN (10U)
+#define SDH_TX_HOLD_DELAY0_MSK (((1U << SDH_TX_HOLD_DELAY0_LEN) - 1) << SDH_TX_HOLD_DELAY0_POS)
+#define SDH_TX_HOLD_DELAY0_UMSK (~(((1U << SDH_TX_HOLD_DELAY0_LEN) - 1) << SDH_TX_HOLD_DELAY0_POS))
+#define SDH_TX_HOLD_DELAY1 SDH_TX_HOLD_DELAY1
+#define SDH_TX_HOLD_DELAY1_POS (16U)
+#define SDH_TX_HOLD_DELAY1_LEN (10U)
+#define SDH_TX_HOLD_DELAY1_MSK (((1U << SDH_TX_HOLD_DELAY1_LEN) - 1) << SDH_TX_HOLD_DELAY1_POS)
+#define SDH_TX_HOLD_DELAY1_UMSK (~(((1U << SDH_TX_HOLD_DELAY1_LEN) - 1) << SDH_TX_HOLD_DELAY1_POS))
+#define SDH_TX_INT_CLK_SEL SDH_TX_INT_CLK_SEL
+#define SDH_TX_INT_CLK_SEL_POS (30U)
+#define SDH_TX_INT_CLK_SEL_LEN (1U)
+#define SDH_TX_INT_CLK_SEL_MSK (((1U << SDH_TX_INT_CLK_SEL_LEN) - 1) << SDH_TX_INT_CLK_SEL_POS)
+#define SDH_TX_INT_CLK_SEL_UMSK (~(((1U << SDH_TX_INT_CLK_SEL_LEN) - 1) << SDH_TX_INT_CLK_SEL_POS))
+#define SDH_TX_MUX_SEL SDH_TX_MUX_SEL
+#define SDH_TX_MUX_SEL_POS (31U)
+#define SDH_TX_MUX_SEL_LEN (1U)
+#define SDH_TX_MUX_SEL_MSK (((1U << SDH_TX_MUX_SEL_LEN) - 1) << SDH_TX_MUX_SEL_POS)
+#define SDH_TX_MUX_SEL_UMSK (~(((1U << SDH_TX_MUX_SEL_LEN) - 1) << SDH_TX_MUX_SEL_POS))
+
+/* 0x11c : TUNING CONFIG Register */
+#define SDH_TUNING_CFG_REG_OFFSET (0x11c)
+#define SDH_TUNING_TT_CNT SDH_TUNING_TT_CNT
+#define SDH_TUNING_TT_CNT_POS (0U)
+#define SDH_TUNING_TT_CNT_LEN (8U)
+#define SDH_TUNING_TT_CNT_MSK (((1U << SDH_TUNING_TT_CNT_LEN) - 1) << SDH_TUNING_TT_CNT_POS)
+#define SDH_TUNING_TT_CNT_UMSK (~(((1U << SDH_TUNING_TT_CNT_LEN) - 1) << SDH_TUNING_TT_CNT_POS))
+#define SDH_TUNING_WD_CNT SDH_TUNING_WD_CNT
+#define SDH_TUNING_WD_CNT_POS (8U)
+#define SDH_TUNING_WD_CNT_LEN (6U)
+#define SDH_TUNING_WD_CNT_MSK (((1U << SDH_TUNING_WD_CNT_LEN) - 1) << SDH_TUNING_WD_CNT_POS)
+#define SDH_TUNING_WD_CNT_UMSK (~(((1U << SDH_TUNING_WD_CNT_LEN) - 1) << SDH_TUNING_WD_CNT_POS))
+#define SDH_TUNING_CLK_DLY SDH_TUNING_CLK_DLY
+#define SDH_TUNING_CLK_DLY_POS (14U)
+#define SDH_TUNING_CLK_DLY_LEN (10U)
+#define SDH_TUNING_CLK_DLY_MSK (((1U << SDH_TUNING_CLK_DLY_LEN) - 1) << SDH_TUNING_CLK_DLY_POS)
+#define SDH_TUNING_CLK_DLY_UMSK (~(((1U << SDH_TUNING_CLK_DLY_LEN) - 1) << SDH_TUNING_CLK_DLY_POS))
+#define SDH_TUNING_SUCCESS_CNT SDH_TUNING_SUCCESS_CNT
+#define SDH_TUNING_SUCCESS_CNT_POS (24U)
+#define SDH_TUNING_SUCCESS_CNT_LEN (6U)
+#define SDH_TUNING_SUCCESS_CNT_MSK (((1U << SDH_TUNING_SUCCESS_CNT_LEN) - 1) << SDH_TUNING_SUCCESS_CNT_POS)
+#define SDH_TUNING_SUCCESS_CNT_UMSK (~(((1U << SDH_TUNING_SUCCESS_CNT_LEN) - 1) << SDH_TUNING_SUCCESS_CNT_POS))
+
+struct sdh_reg {
+ /* 0x00 : System Address Low Register */
+ union {
+ struct
+ {
+ uint16_t DMA_ADDR_L : 16; /* [15: 0], RW, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_SYS_ADDR_LOW;
+
+ /* 0x02 : System Address High Register */
+ union {
+ struct
+ {
+ uint16_t DMA_ADDR_H : 16; /* [15: 0], RW, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_SYS_ADDR_HIGH;
+
+ /* 0x04 : Block Size Register */
+ union {
+ struct
+ {
+ uint16_t BLOCK_SIZE : 12; /* [11: 0], RW, 0x000 */
+ uint16_t HOST_DMA_BDRY : 3; /* [14:12], RW, 0x0 */
+ uint16_t Reserved_15 : 1; /* [ 15], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_BLOCK_SIZE;
+
+ /* 0x06 : Block Count Register */
+ union {
+ struct
+ {
+ uint16_t BLOCK_COUNT : 16; /* [15: 0], RW, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_BLOCK_COUNT;
+
+ /* 0x08 : Argument Low Register */
+ union {
+ struct
+ {
+ uint16_t ARG_L : 16; /* [15: 0], RW , 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ARG_LOW;
+
+ /* 0x0A : Argument High Register */
+ union {
+ struct
+ {
+ uint16_t ARG_H : 16; /* [15: 0], RW, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ARG_HIGH;
+
+ /* 0x0C : Transfer Mode Register */
+ union {
+ struct
+ {
+ uint16_t DMA_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t BLK_CNT_EN : 1; /* [ 1], RW, 0x0 */
+ uint16_t AUTO_CMD_EN : 2; /* [ 3: 2], RW, 0x0 */
+ uint16_t TO_HOST_DIR : 1; /* [ 4], RW, 0x0 */
+ uint16_t MULTI_BLK_SEL : 1; /* [ 5], RW, 0x0 */
+ uint16_t Reserved_15_6 : 10; /* [15: 6], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_TRANSFER_MODE;
+
+ /* 0x0E : Command Register */
+ union {
+ struct
+ {
+ uint16_t RESP_TYPE : 2; /* [ 1: 0], RW, 0x0 */
+ uint16_t Reserved_2 : 1; /* [ 2], RSVD, 0x0 */
+ uint16_t CMD_CRC_CHK_EN : 1; /* [ 3], RW, 0x0 */
+ uint16_t CMD_INDEX_CHK_EN : 1; /* [ 4], RW, 0x0 */
+ uint16_t DATA_PRESENT : 1; /* [ 5], RW, 0x0 */
+ uint16_t CMD_TYPE : 2; /* [ 7: 6], RW, 0x0 */
+ uint16_t CMD_INDEX : 6; /* [13: 8], RW, 0x00 */
+ uint16_t Reserved_15_14 : 2; /* [15:14], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CMD;
+
+ /* 0x10 : Response Register 0 */
+ union {
+ struct
+ {
+ uint16_t RESP0 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_0;
+
+ /* 0x12 : Response Register 1 */
+ union {
+ struct
+ {
+ uint16_t RESP1 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_1;
+
+ /* 0x14 : Response Register 2 */
+ union {
+ struct
+ {
+ uint16_t RESP2 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_2;
+
+ /* 0x16 : Response Register 3 */
+ union {
+ struct
+ {
+ uint16_t RESP3 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_3;
+
+ /* 0x18 : Response Register 4 */
+ union {
+ struct
+ {
+ uint16_t RESP4 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_4;
+
+ /* 0x1A : Response Register 5 */
+ union {
+ struct
+ {
+ uint16_t RESP5 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_5;
+
+ /* 0x1C : Response Register 6 */
+ union {
+ struct
+ {
+ uint16_t RESP6 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_6;
+
+ /* 0x1E : Response Register 7 */
+ union {
+ struct
+ {
+ uint16_t RESP7 : 16; /* [15: 0], RO, 0x0000 */
+ } BF;
+ uint16_t SHORT;
+ } SD_RESP_7;
+
+ /* 0x20 : Buffer Data Port 0 Register */
+ union {
+ struct
+ {
+ uint16_t CPU_DATA0 : 16; /* [15: 0], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_BUFFER_DATA_PORT_0;
+
+ /* 0x22 : Buffer Data Port 1 Register */
+ union {
+ struct
+ {
+ uint16_t CPU_DATA1 : 16; /* [15: 0], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_BUFFER_DATA_PORT_1;
+
+ /* 0x24 : Present State Register 1 */
+ union {
+ struct
+ {
+ uint16_t CMD_INHIBIT_CMD : 1; /* [ 0], RO, 0x0 */
+ uint16_t CMD_INHIBIT_DAT : 1; /* [ 1], RO, 0x0 */
+ uint16_t _DAT_ACTIVE : 1; /* [ 2], RO, 0x0 */
+ uint16_t RETUNING_REQ : 1; /* [ 3], RO, 0x0 */
+ uint16_t Reserved_7_4 : 4; /* [ 7: 4], RSVD, 0x0 */
+ uint16_t TX_ACTIVE : 1; /* [ 8], RO, 0x0 */
+ uint16_t RX_ACTIVE : 1; /* [ 9], RO, 0x0 */
+ uint16_t BUFFER_WR_EN : 1; /* [ 10], RO, 0x1 */
+ uint16_t BUFFER_RD_EN : 1; /* [ 11], RO, 0x0 */
+ uint16_t Reserved_15_12 : 4; /* [15:12], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_PRESENT_STATE_1;
+
+ /* 0x26 : Present State Register 2 */
+ union {
+ struct
+ {
+ uint16_t CARD_INSERTED : 1; /* [ 0], RO, 0x0 */
+ uint16_t CARD_STABLE : 1; /* [ 1], RO, 0x0 */
+ uint16_t CARD_DET : 1; /* [ 2], RO, 0x0 */
+ uint16_t WRITE_PROT : 1; /* [ 3], RO, 0x0 */
+ uint16_t DAT_LEVEL : 4; /* [ 7: 4], RO, 0xF */
+ uint16_t CMD_LEVEL : 1; /* [ 8], RO, 0x1 */
+ uint16_t Reserved_15_9 : 7; /* [15: 9], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_PRESENT_STATE_2;
+
+ /* 0x28 : Host Control Register */
+ union {
+ struct
+ {
+ uint16_t LED_CTRL : 1; /* [ 0], RW, 0x0 */
+ uint16_t DATA_WIDTH : 1; /* [ 1], RW, 0x0 */
+ uint16_t HI_SPEED_EN : 1; /* [ 2], RW, 0x0 */
+ uint16_t DMA_SEL : 2; /* [ 4: 3], RW, 0x0 */
+ uint16_t EX_DATA_WIDTH : 1; /* [ 5], RW, 0x0 */
+ uint16_t CARD_DET_L : 1; /* [ 6], RW, 0x0 */
+ uint16_t CARD_DET_S : 1; /* [ 7], RW, 0x0 */
+ uint16_t SD_BUS_POWER : 1; /* [ 8], RW, 0x0 */
+ uint16_t SD_BUS_VLT : 3; /* [11: 9], RW, 0x0 */
+ uint16_t Reserved_15_12 : 4; /* [15:12], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_HOST_CTRL;
+
+ /* 0x2A : Block Gap Control Register */
+ union {
+ struct
+ {
+ uint16_t STOP_AT_BLOCK_GAP_REQ : 1; /* [ 0], RW, 0x0 */
+ uint16_t CONT_REQ : 1; /* [ 1], RWAC, 0x0 */
+ uint16_t RD_WAIT_CTL : 1; /* [ 2], RW, 0x0 */
+ uint16_t INT_BLK_GAP : 1; /* [ 3], RW, 0x0 */
+ uint16_t Reserved_7_4 : 4; /* [ 7: 4], RSVD, 0x0 */
+ uint16_t W_CARD_INT : 1; /* [ 8], RW, 0x0 */
+ uint16_t W_INSERTION : 1; /* [ 9], RW, 0x0 */
+ uint16_t W_REMOVAL : 1; /* [ 10], RW, 0x0 */
+ uint16_t Reserved_15_11 : 5; /* [15:11], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_BLOCK_GAP_CTRL;
+
+ /* 0x2C : Clock Control Register */
+ union {
+ struct
+ {
+ uint16_t INT_CLK_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t INT_CLK_STABLE : 1; /* [ 1], RO, 0x0 */
+ uint16_t SD_CLK_EN : 1; /* [ 2], RW, 0x0 */
+ uint16_t Reserved_4_3 : 2; /* [ 4: 3], RSVD, 0x0 */
+ uint16_t CLK_GEN_SEL : 1; /* [ 5], RW, 0x0 */
+ uint16_t SD_FREQ_SEL_HI : 2; /* [ 7: 6], RW, 0x0 */
+ uint16_t SD_FREQ_SEL_LO : 8; /* [15: 8], RW, 0x00 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CLOCK_CTRL;
+
+ /* 0x2E : Timeout Control/Software Reset Register */
+ union {
+ struct
+ {
+ uint16_t TIMEOUT_VALUE : 4; /* [ 3: 0], RW, 0x0 */
+ uint16_t Reserved_7_4 : 4; /* [ 7: 4], RSVD, 0x0 */
+ uint16_t SW_RST_ALL : 1; /* [ 8], RWAC, 0x0 */
+ uint16_t SW_RST_CMD : 1; /* [ 9], RWAC, 0x0 */
+ uint16_t SW_RST_DAT : 1; /* [ 10], RWAC, 0x0 */
+ uint16_t Reserved_15_11 : 5; /* [15:11], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_TIMEOUT_CTRL_SW_RESET;
+
+ /* 0x30 : Normal Interrupt Status Register */
+ union {
+ struct
+ {
+ uint16_t CMD_COMPLETE : 1; /* [ 0], RW1C, 0x0 */
+ uint16_t XFER_COMPLETE : 1; /* [ 1], RW1C, 0x0 */
+ uint16_t BLOCK_GAP_EVT : 1; /* [ 2], RW1C, 0x0 */
+ uint16_t DMA_INT : 1; /* [ 3], RW1C, 0x0 */
+ uint16_t TX_RDY : 1; /* [ 4], RW1C, 0x1 */
+ uint16_t RX_RDY : 1; /* [ 5], RW1C, 0x0 */
+ uint16_t CARD_INS_INT : 1; /* [ 6], RW1C, 0x0 */
+ uint16_t CARD_REM_INT : 1; /* [ 7], RW1C, 0x0 */
+ uint16_t CARD_INT : 1; /* [ 8], RO, 0x0 */
+ uint16_t INT_A : 1; /* [ 9], RW1C, 0x0 */
+ uint16_t INT_B : 1; /* [ 10], RW1C, 0x0 */
+ uint16_t INT_C : 1; /* [ 11], RW1C, 0x0 */
+ uint16_t RETUNING_INT : 1; /* [ 12], RW1C, 0x0 */
+ uint16_t Reserved_14_13 : 2; /* [14:13], RSVD, 0x0 */
+ uint16_t ERR_INT : 1; /* [ 15], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_NORMAL_INT_STATUS;
+
+ /* 0x32 : Error Interrupt Status Register */
+ union {
+ struct
+ {
+ uint16_t CMD_TIMEOUT_ERR : 1; /* [ 0], RW1C, 0x0 */
+ uint16_t CMD_CRC_ERR : 1; /* [ 1], RW1C, 0x0 */
+ uint16_t CMD_END_BIT_ERR : 1; /* [ 2], RW1C, 0x0 */
+ uint16_t CMD_INDEX_ERR : 1; /* [ 3], RW1C, 0x0 */
+ uint16_t DATA_TIMEOUT_ERR : 1; /* [ 4], RW1C, 0x0 */
+ uint16_t RD_DATA_CRC_ERR : 1; /* [ 5], RW1C, 0x0 */
+ uint16_t RD_DATA_END_BIT_ERR : 1; /* [ 6], RW1C, 0x0 */
+ uint16_t CUR_LIMIT_ERR : 1; /* [ 7], RW1C, 0x0 */
+ uint16_t AUTO_CMD12_ERR : 1; /* [ 8], RW1C, 0x0 */
+ uint16_t ADMA_ERR : 1; /* [ 9], RW1C, 0x0 */
+ uint16_t TUNE_ERR : 1; /* [ 10], RW1C, 0x0 */
+ uint16_t Reserved_11 : 1; /* [ 11], RSVD, 0x0 */
+ uint16_t SPI_ERR : 1; /* [ 12], RW1C, 0x0 */
+ uint16_t AXI_RESP_ERR : 1; /* [ 13], RW1C, 0x0 */
+ uint16_t CPL_TIMEOUT_ERR : 1; /* [ 14], RW1C, 0x0 */
+ uint16_t CRC_STATUS_ERR : 1; /* [ 15], RW1C, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ERROR_INT_STATUS;
+
+ /* 0x34 : Normal Interrupt Status Enable Register */
+ union {
+ struct
+ {
+ uint16_t CMD_COMPLETE_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t XFER_COMPLETE_EN : 1; /* [ 1], RW, 0x0 */
+ uint16_t BLOCK_GAP_EVT_EN : 1; /* [ 2], RW, 0x0 */
+ uint16_t DMA_INT_EN : 1; /* [ 3], RW, 0x0 */
+ uint16_t TX_RDY_EN : 1; /* [ 4], RW, 0x0 */
+ uint16_t RD_RDY_EN : 1; /* [ 5], RW, 0x0 */
+ uint16_t CARD_INS_EN : 1; /* [ 6], RW, 0x0 */
+ uint16_t CARD_REM_EN : 1; /* [ 7], RW, 0x0 */
+ uint16_t CARD_INT_EN : 1; /* [ 8], RW, 0x0 */
+ uint16_t INT_A_INT_EN : 1; /* [ 9], RW, 0x0 */
+ uint16_t INT_B_INT_EN : 1; /* [ 10], RW, 0x0 */
+ uint16_t INT_C_INT_EN : 1; /* [ 11], RW, 0x0 */
+ uint16_t RETUNE_INT_EN : 1; /* [ 12], RW, 0x0 */
+ uint16_t Reserved_15_13 : 3; /* [15:13], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_NORMAL_INT_STATUS_EN;
+
+ /* 0x36 : Error Interrupt Status Enable Register */
+ union {
+ struct
+ {
+ uint16_t CMD_TIMEOUT_ERR_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t CMD_CRC_ERR_EN : 1; /* [ 1], RW, 0x0 */
+ uint16_t CMD_END_BIT_ERR_EN : 1; /* [ 2], RW, 0x0 */
+ uint16_t CMD_INDEX_ERR_EN : 1; /* [ 3], RW, 0x0 */
+ uint16_t DATA_TIMEOUT_ERR_EN : 1; /* [ 4], RW, 0x0 */
+ uint16_t RD_DATA_CRC_ERR_EN : 1; /* [ 5], RW, 0x0 */
+ uint16_t RD_DATA_END_BIT_ERR_EN : 1; /* [ 6], RW, 0x0 */
+ uint16_t CUR_LIM_ERR_EN : 1; /* [ 7], RW, 0x0 */
+ uint16_t AUTO_CMD12_ERR_EN : 1; /* [ 8], RW, 0x0 */
+ uint16_t ADMA_ERR_EN : 1; /* [ 9], RW, 0x0 */
+ uint16_t TUNING_ERR_EN : 1; /* [ 10], RW, 0x0 */
+ uint16_t Reserved_11 : 1; /* [ 11], RSVD, 0x0 */
+ uint16_t SPI_ERR_EN : 1; /* [ 12], RW, 0x0 */
+ uint16_t AXI_RESP_ERR_EN : 1; /* [ 13], RW, 0x0 */
+ uint16_t CPL_TIMEOUT_ERR_EN : 1; /* [ 14], RW, 0x0 */
+ uint16_t CRC_STATUS_ERR_EN : 1; /* [ 15], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ERROR_INT_STATUS_EN;
+
+ /* 0x38 : Normal Interrupt Status Interrupt Enable Register */
+ union {
+ struct
+ {
+ uint16_t CMD_COMPLETE_INT_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t XFER_COMPLETE_INT_EN : 1; /* [ 1], RW, 0x0 */
+ uint16_t BLOCK_GAP_EVT_INT_EN : 1; /* [ 2], RW, 0x0 */
+ uint16_t DMA_INT_INT_EN : 1; /* [ 3], RW, 0x0 */
+ uint16_t TX_RDY_INT_EN : 1; /* [ 4], RW, 0x0 */
+ uint16_t RX_RDY_INT_EN : 1; /* [ 5], RW, 0x0 */
+ uint16_t CARD_INS_INT_EN : 1; /* [ 6], RW, 0x0 */
+ uint16_t CARD_REM_INT_EN : 1; /* [ 7], RW, 0x0 */
+ uint16_t CARD_INT_INT_EN : 1; /* [ 8], RW, 0x0 */
+ uint16_t INT_A_INT_INT_EN : 1; /* [ 9], RW, 0x0 */
+ uint16_t INT_B_INT_INT_EN : 1; /* [ 10], RW, 0x0 */
+ uint16_t INT_C_INT_INT_EN : 1; /* [ 11], RW, 0x0 */
+ uint16_t RETUNE_INT_INT_EN : 1; /* [ 12], RW, 0x0 */
+ uint16_t Reserved_15_13 : 3; /* [15:13], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_NORMAL_INT_STATUS_INT_EN;
+
+ /* 0x3A : Error Interrupt Status Interrupt Enable Register */
+ union {
+ struct
+ {
+ uint16_t CMD_TIMEOUT_ERR_INT_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t CMD_CRC_ERR_INT_EN : 1; /* [ 1], RW, 0x0 */
+ uint16_t CMD_END_BIT_ERR_INT_EN : 1; /* [ 2], RW, 0x0 */
+ uint16_t CMD_INDEX_ERR_INT_EN : 1; /* [ 3], RW, 0x0 */
+ uint16_t DATA_TIMEOUT_ERR_INT_EN : 1; /* [ 4], RW, 0x0 */
+ uint16_t RD_DATA_CRC_ERR_INT_EN : 1; /* [ 5], RW, 0x0 */
+ uint16_t RD_DATA_END_BIT_ERR_INT_EN : 1; /* [ 6], RW, 0x0 */
+ uint16_t CUR_LIM_ERR_INT_EN : 1; /* [ 7], RW, 0x0 */
+ uint16_t AUTO_CMD12_ERR_INT_EN : 1; /* [ 8], RW, 0x0 */
+ uint16_t ADMA_ERR_INT_EN : 1; /* [ 9], RW, 0x0 */
+ uint16_t TUNE_ERR_INT_EN : 1; /* [ 10], RW, 0x0 */
+ uint16_t Reserved_11 : 1; /* [ 11], RSVD, 0x0 */
+ uint16_t SPI_ERR_INT_EN : 1; /* [ 12], RW, 0x0 */
+ uint16_t AXI_RESP_ERR_INT_EN : 1; /* [ 13], RW, 0x0 */
+ uint16_t CPL_TIMEOUT_ERR_INT_EN : 1; /* [ 14], RW, 0x0 */
+ uint16_t CRC_STATUS_ERR_INT_EN : 1; /* [ 15], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ERROR_INT_STATUS_INT_EN;
+
+ /* 0x3C : Auto CMD12 Error Status Register */
+ union {
+ struct
+ {
+ uint16_t AUTO_CMD12_NOT_EXE : 1; /* [ 0], RW1C, 0x0 */
+ uint16_t AUTO_CMD_TIMEOUT_ERR : 1; /* [ 1], RW1C, 0x0 */
+ uint16_t AUTO_CMD_CRC_ERR : 1; /* [ 2], RW1C, 0x0 */
+ uint16_t AUTO_CMD_END_BIT_ERR : 1; /* [ 3], RW1C, 0x0 */
+ uint16_t AUTO_CMD_INDEX_ERR : 1; /* [ 4], RW1C, 0x0 */
+ uint16_t Reserved_6_5 : 2; /* [ 6: 5], RSVD, 0x0 */
+ uint16_t CMD_NOT_ISSUED : 1; /* [ 7], ROC, 0x0 */
+ uint16_t Reserved_15_8 : 8; /* [15: 8], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_AUTO_CMD12_ERROR_STATUS;
+
+ /* 0x3e : Host Control 2 Register */
+ union {
+ struct
+ {
+ uint16_t UHS_MODE_SEL : 3; /* [ 2: 0], RW, 0x0 */
+ uint16_t SDH_V18_EN : 1; /* [ 3], RW, 0x0 */
+ uint16_t DRV_STRENGTH_SEL : 2; /* [ 5: 4], RW, 0x0 */
+ uint16_t EXE_TUNING : 1; /* [ 6], RWAC, 0x0 */
+ uint16_t SAMPLING_CLK_SEL : 1; /* [ 7], RW, 0x0 */
+ uint16_t Reserved_13_8 : 6; /* [13: 8], RSVD, 0x0 */
+ uint16_t ASYNC_INT_EN : 1; /* [ 14], RW, 0x1 */
+ uint16_t PRE_VAL_EN : 1; /* [ 15], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } HOST_CTRL_2;
+
+ /* 0x40 : Capabilities Register 1 */
+ union {
+ struct
+ {
+ uint16_t TIMEOUT_FREQ : 6; /* [ 5: 0], RO, 0x00 */
+ uint16_t Reserved_6 : 1; /* [ 6], RSVD, 0x0 */
+ uint16_t TIMEOUT_UNIT : 1; /* [ 7], RO, 0x1 */
+ uint16_t BASE_FREQ : 8; /* [15: 8], RO, 0x00 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CAPABILITIES_1;
+
+ /* 0x42 : Capabilities Register 2 */
+ union {
+ struct
+ {
+ uint16_t MAX_BLK_LEN : 2; /* [ 1: 0], RO, 0x0 */
+ uint16_t EX_DATA_WIDTH_SUPPORT : 1; /* [ 2], RO, 0x1 */
+ uint16_t ADMA2_SUPPORT : 1; /* [ 3], RO, 0x1 */
+ uint16_t ADMA1_SUPPORT : 1; /* [ 4], RO, 0x1 */
+ uint16_t HI_SPEED_SUPPORT : 1; /* [ 5], RO, 0x1 */
+ uint16_t SDMA_SUPPORT : 1; /* [ 6], RO, 0x1 */
+ uint16_t SUS_RES_SUPPORT : 1; /* [ 7], RO, 0x1 */
+ uint16_t VLG_33_SUPPORT : 1; /* [ 8], RO, 0x1 */
+ uint16_t VLG_30_SUPPORT : 1; /* [ 9], RO, 0x0 */
+ uint16_t VLG_18_SUPPORT : 1; /* [ 10], RO, 0x1 */
+ uint16_t Reserved_11 : 1; /* [ 11], RSVD, 0x0 */
+ uint16_t SYS_BUS_64_SUPPORT : 1; /* [ 12], RO, 0x0 */
+ uint16_t ASYNC_INT_SUPPORT : 1; /* [ 13], RO, 0x1 */
+ uint16_t CFG_SLOT_TYPE : 2; /* [15:14], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CAPABILITIES_2;
+
+ /* 0x44 : Capabilities Register 3 */
+ union {
+ struct
+ {
+ uint16_t SDR50_SUPPORT : 1; /* [ 0], RO, 0x1 */
+ uint16_t SDR104_SUPPORT : 1; /* [ 1], RO, 0x1 */
+ uint16_t DDR50_SUPPORT : 1; /* [ 2], RO, 0x1 */
+ uint16_t Reserved_3 : 1; /* [ 3], RSVD, 0x0 */
+ uint16_t DRV_TYPE_A : 1; /* [ 4], RO, 0x1 */
+ uint16_t DRV_TYPE_C : 1; /* [ 5], RO, 0x1 */
+ uint16_t DRV_TYPE_D : 1; /* [ 6], RO, 0x1 */
+ uint16_t Reserved_7 : 1; /* [ 7], RSVD, 0x0 */
+ uint16_t TMR_RETUNE : 4; /* [11: 8], RO, 0xf */
+ uint16_t Reserved_12 : 1; /* [ 12], RSVD, 0x0 */
+ uint16_t SDR50_TUNE : 1; /* [ 13], RO, 0x1 */
+ uint16_t RETUNE_MODES : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CAPABILITIES_3;
+
+ /* 0x46 : Capabilities Register 4 */
+ union {
+ struct
+ {
+ uint16_t clk_multiplier : 8; /* [ 7: 0], RO, 0x0 */
+ uint16_t Reserved_15_8 : 8; /* [15: 8], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CAPABILITIES_4;
+
+ /* 0x48 : Maximum Current Register 1 */
+ union {
+ struct
+ {
+ uint16_t MAX_CUR_33 : 8; /* [ 7: 0], RO, 0x0 */
+ uint16_t MAX_CUR_30 : 8; /* [15: 8], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_MAX_CURRENT_1;
+
+ /* 0x4A : Maximum Current Register 2 */
+ union {
+ struct
+ {
+ uint16_t MAX_CUR_18 : 8; /* [ 7: 0], RO, 0x0 */
+ uint16_t Reserved_15_8 : 8; /* [15: 8], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_MAX_CURRENT_2;
+
+ /* 0x4C : Maximum Current Register 3 */
+ union {
+ struct
+ {
+ uint16_t Reserved_15_0 : 16; /* [15: 0], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_MAX_CURRENT_3;
+
+ /* 0x4E : Maximum Current Register 4 */
+ union {
+ struct
+ {
+ uint16_t Reserved_15_0 : 16; /* [15: 0], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_MAX_CURRENT_4;
+
+ /* 0x50 : Force Event Auto cmd12 Error Register */
+ union {
+ struct
+ {
+ uint16_t F_ACMD12_NEXE_ERR : 1; /* [ 0], WO, 0x0 */
+ uint16_t F_ACMD_TO_ERR : 1; /* [ 1], WO, 0x0 */
+ uint16_t F_ACMD_CRC_ERR : 1; /* [ 2], WO, 0x0 */
+ uint16_t F__ACMD_EBIT_ERR : 1; /* [ 3], WO, 0x0 */
+ uint16_t F_ACMD_INDEX_ERR : 1; /* [ 4], WO, 0x0 */
+ uint16_t Reserved_6_5 : 2; /* [ 6: 5], RSVD, 0x0 */
+ uint16_t F_ACMD12_ISSUE_ERR : 1; /* [ 7], WO, 0x0 */
+ uint16_t Reserved_15_8 : 8; /* [15: 8], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_FORCE_EVENT_AUTO_CMD12_ERROR;
+
+ /* 0x52 : Force Event for Error Status Register */
+ union {
+ struct
+ {
+ uint16_t F_CMD_TO_ERR : 1; /* [ 0], WO, 0x0 */
+ uint16_t F_CMD_CRC_ERR : 1; /* [ 1], WO, 0x0 */
+ uint16_t F_CMD_END_BIT_ERR : 1; /* [ 2], WO, 0x0 */
+ uint16_t F_CMD_INDEX_ERR : 1; /* [ 3], WO, 0x0 */
+ uint16_t F_DAT_TO_ERR : 1; /* [ 4], WO, 0x0 */
+ uint16_t F_DAT_CRC_ERR : 1; /* [ 5], WO, 0x0 */
+ uint16_t F_DAT_END_BIT_ERR : 1; /* [ 6], WO, 0x0 */
+ uint16_t F_CURRENT_ERR : 1; /* [ 7], WO, 0x0 */
+ uint16_t F_ACMD12_ERR : 1; /* [ 8], WO, 0x0 */
+ uint16_t F_ADMA_ERR : 1; /* [ 9], WO, 0x0 */
+ uint16_t Reserved_11_10 : 2; /* [11:10], RSVD, 0x0 */
+ uint16_t F_SPI_ERR : 1; /* [ 12], WO, 0x0 */
+ uint16_t F_AXI_RESP_ERR : 1; /* [ 13], WO, 0x0 */
+ uint16_t F_CPL_TIMEOUT_ERR : 1; /* [ 14], WO, 0x0 */
+ uint16_t F_CRC_STATUS_ERR : 1; /* [ 15], WO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_FORCE_EVENT_FOR_ERROR_STATUS;
+
+ /* 0x54 : ADMA Error Status Register */
+ union {
+ struct
+ {
+ uint16_t ADMA_STATE : 2; /* [ 1: 0], RW, 0x0 */
+ uint16_t ADMA_LEN_ERR : 1; /* [ 2], RW, 0x0 */
+ uint16_t Reserved_15_3 : 13; /* [15: 3], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ADMA_ERROR_STATUS;
+
+ /* 0x56 reserved */
+ uint8_t RESERVED0x56[2];
+
+ /* 0x58 : ADMA System Address Register 1 */
+ union {
+ struct
+ {
+ uint16_t ADMA_SYS_ADDR : 16; /* [15: 0], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ADMA_SYS_ADDR_1;
+
+ /* 0x5A : ADMA System Address Register 2 */
+ union {
+ struct
+ {
+ uint16_t ADMA_SYS_ADDR : 16; /* [15: 0], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ADMA_SYS_ADDR_2;
+
+ /* 0x5C : ADMA System Address Register 3 */
+ union {
+ struct
+ {
+ uint16_t ADMA_SYS_ADDR : 16; /* [15: 0], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ADMA_SYS_ADDR_3;
+
+ /* 0x5E : ADMA System Address Register 4 */
+ union {
+ struct
+ {
+ uint16_t ADMA_SYS_ADDR : 16; /* [15: 0], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_ADMA_SYS_ADDR_4;
+
+ /* 0x60 : Preset Value Register for Initialization */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x100 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_INIT;
+
+ /* 0x62 : Preset Value Register for Default Speed */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x004 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_DS;
+
+ /* 0x64 : Preset Value Register for High Speed */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x002 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_HS;
+
+ /* 0x66 : Preset Value Register for SDR12 */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x004 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_SDR12;
+
+ /* 0x68 : Preset Value Register for SDR25 */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x002 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_SDR25;
+
+ /* 0x6a : Preset Value Register for SDR50 */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x001 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_SDR50;
+
+ /* 0x6c : Preset Value Register for SDR104 */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x0 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_SDR104;
+
+ /* 0x6e : Preset Value Register for DDR50 */
+ union {
+ struct
+ {
+ uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0], RO, 0x002 */
+ uint16_t CLKGEN_SEL_VAL : 1; /* [ 10], RO, 0x0 */
+ uint16_t Reserved_13_11 : 3; /* [13:11], RSVD, 0x0 */
+ uint16_t DRV_STRENGTH_VAL : 2; /* [15:14], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } PRESET_VALUE_FOR_DDR50;
+
+ /* 0x70 reserved */
+ uint8_t RESERVED0x70[112];
+
+ /* 0xe0 : Shared Bus Control Register */
+ union {
+ struct
+ {
+ uint32_t NUM_CLK_PINS : 3; /* [ 2: 0], RO, 0x0 */
+ uint32_t Reserved_3 : 1; /* [ 3], RSVD, 0x0 */
+ uint32_t NUM_INT_PINS : 2; /* [ 5: 4], RO, 0x0 */
+ uint32_t Reserved_7_6 : 2; /* [ 7: 6], RSVD, 0x0 */
+ uint32_t BUS_WIDTH_PRESET : 7; /* [14: 8], RO, 0x0 */
+ uint32_t Reserved_15 : 1; /* [ 15], RSVD, 0x0 */
+ uint32_t CLK_PIN_SEL : 3; /* [18:16], RW, 0x0 */
+ uint32_t Reserved_19 : 1; /* [ 19], RSVD, 0x0 */
+ uint32_t INT_PIN_SEL : 3; /* [22:20], RW, 0x0 */
+ uint32_t Reserved_23 : 1; /* [ 23], RSVD, 0x0 */
+ uint32_t BEND_PWR_CTRL : 7; /* [30:24], RW, 0x0 */
+ uint32_t Reserved_31 : 1; /* [ 31], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } SHARED_BUS_CTRL;
+
+ /* 0xe4 reserved */
+ uint8_t RESERVED0xe4[24];
+
+ /* 0xFC : Slot Interrupt Status Register */
+ union {
+ struct
+ {
+ uint16_t SLOT_INT0 : 1; /* [ 0], RO, 0x0 */
+ uint16_t SLOT_INT1 : 1; /* [ 1], RO, 0x0 */
+ uint16_t Reserved_15_2 : 14; /* [15: 2], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_SLOT_INT_STATUS;
+
+ /* 0xFE : Host Control Version Register */
+ union {
+ struct
+ {
+ uint16_t SD_VER : 8; /* [ 7: 0], RO, 0x2 */
+ uint16_t VENDOR_VER : 8; /* [15: 8], RO, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_HOST_CTRL_VER;
+
+ /* 0x100 : SD Extra Parameters Register */
+ union {
+ struct
+ {
+ uint32_t Reserved_0 : 1; /* [ 0], RSVD, 0x0 */
+ uint32_t Reserved_2_1 : 2; /* [ 2: 1], RSVD, 0x0 */
+ uint32_t BOOT_ACK : 1; /* [ 3], RW, 0x0 */
+ uint32_t SQU_EMPTY_CHK : 1; /* [ 4], RW, 0x0 */
+ uint32_t SQU_FULL_CHK : 1; /* [ 5], RW, 0x0 */
+ uint32_t GEN_PAD_CLK_ON : 1; /* [ 6], RWAC, 0x0 */
+ uint32_t Reserved_23_7 : 17; /* [23: 7], RSVD, 0x0 */
+ uint32_t GEN_PAD_CLK_CNT : 8; /* [31:24], RW, 0x4a */
+ } BF;
+ uint32_t WORD;
+ } SD_CFG_FIFO_PARAM;
+
+ /* 0x104 : FIFO Parameters Register */
+ union {
+ struct
+ {
+ uint32_t RTC : 2; /* [ 1: 0], RW, 0x1 */
+ uint32_t WTC : 2; /* [ 3: 2], RW, 0x1 */
+ uint32_t FIFO_CLK : 1; /* [ 4], RW, 0x0 */
+ uint32_t FIFO_CS : 1; /* [ 5], RW, 0x0 */
+ uint32_t PDWN : 1; /* [ 6], RW, 0x0 */
+ uint32_t use_dat3 : 1; /* [ 7], RW, 0x0 */
+ uint32_t CLK_GATE_CTL : 1; /* [ 8], RW, 0x0 */
+ uint32_t CLK_GATE_ON : 1; /* [ 9], RW, 0x0 */
+ uint32_t Reserved_10 : 1; /* [ 10], RSVD, 0x0 */
+ uint32_t OVRRD_CLK_OEN : 1; /* [ 11], RW, 0x0 */
+ uint32_t FORCE_CLK_ON : 1; /* [ 12], RW, 0x0 */
+ uint32_t PDFVSSM : 1; /* [ 13], RW, 0x0 */
+ uint32_t PDLVMC : 1; /* [ 14], RW, 0x0 */
+ uint32_t Reserved_15 : 1; /* [ 15], RSVD, 0x0 */
+ uint32_t PRE_GATE_CLK_CNT : 4; /* [19:16], RW, 0x7 */
+ uint32_t Reserved_31_20 : 12; /* [31:20], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } SD_FIFO_PARAM;
+
+ /* 0x108 : SPI Mode Register */
+ union {
+ struct
+ {
+ uint16_t SPI_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t Reserved_7_1 : 7; /* [ 7: 1], RSVD, 0x0 */
+ uint16_t SPI_ERR_TOKEN : 5; /* [12: 8], RW, 0x0 */
+ uint16_t Reserved_15_13 : 3; /* [15:13], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_SPI_MODE;
+
+ /* 0x10a : Clock and Burst Size Setup Register */
+ union {
+ struct
+ {
+ uint16_t BRST_SIZE : 2; /* [ 1: 0], RW, 0x2 */
+ uint16_t DMA_SIZE : 2; /* [ 3: 2], RW, 0x3 */
+ uint16_t priority : 1; /* [ 4], RW, 0x0 */
+ uint16_t AXI_NON_POST_WR : 1; /* [ 5], RW, 0x0 */
+ uint16_t RD_ENDIAN : 1; /* [ 6], RW, 0x1 */
+ uint16_t WR_ENDIAN : 1; /* [ 7], RW, 0x1 */
+ uint16_t Reserved_13_8 : 6; /* [13: 8], RSVD, 0x0 */
+ uint16_t RD_OSTDG : 1; /* [ 14], RW, 0x0 */
+ uint16_t WR_OSTDG : 1; /* [ 15], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CLOCK_AND_BURST_SIZE_SETUP;
+
+ /* 0x10c : CE-ATA Register 1 */
+ union {
+ struct
+ {
+ uint16_t CPL_TIMEOUT : 14; /* [13: 0], RW, 0x3FFF */
+ uint16_t Reserved_15_14 : 2; /* [15:14], RSVD, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CE_ATA_1;
+
+ /* 0x10e : CE-ATA Register 2 */
+ union {
+ struct
+ {
+ uint16_t MISC_INT_INT_EN : 1; /* [ 0], RW, 0x0 */
+ uint16_t MISC_INT_EN : 1; /* [ 1], RW, 0x0 */
+ uint16_t MISC_INT : 1; /* [ 2], RW1C, 0x0 */
+ uint16_t Reserved_3 : 1; /* [ 3], RSVD, 0x0 */
+ uint16_t CPL_COMPLETE_INT_EN : 1; /* [ 4], RW, 0x0 */
+ uint16_t CPL_COMPLETE_EN : 1; /* [ 5], RW, 0x0 */
+ uint16_t CPL_COMPLETE : 1; /* [ 6], RW1C, 0x0 */
+ uint16_t Reserved_10_7 : 4; /* [10: 7], RSVD, 0x0 */
+ uint16_t MMC_RESETN : 1; /* [ 11], RW, 0x1 */
+ uint16_t MMC_CARD : 1; /* [ 12], RW, 0x0 */
+ uint16_t CEATA_CARD : 1; /* [ 13], RW, 0x0 */
+ uint16_t SND_CPL : 1; /* [ 14], RW, 0x0 */
+ uint16_t CHK_CPL : 1; /* [ 15], RW, 0x0 */
+ } BF;
+ uint16_t SHORT;
+ } SD_CE_ATA_2;
+
+ /* 0x110 : PAD I/O Setup Register */
+ union {
+ struct
+ {
+ uint32_t ASYNC_IO_EN : 1; /* [ 0], RW, 0x0 */
+ uint32_t INAND_SEL : 1; /* [ 1], RW, 0x1 */
+ uint32_t Reserved_15_2 : 14; /* [15: 2], RSVD, 0x0 */
+ uint32_t ECO_REG : 8; /* [23:16], RW, 0x0 */
+ uint32_t Reserved_31_24 : 8; /* [31:24], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } SD_PAD_IO_SETUP;
+
+ /* 0x114 : RX Configuration Register */
+ union {
+ struct
+ {
+ uint32_t SDCLK_SEL0 : 2; /* [ 1: 0], RW, 0x0 */
+ uint32_t SDCLK_SEL1 : 2; /* [ 3: 2], RW, 0x0 */
+ uint32_t Reserved_7_4 : 4; /* [ 7: 4], RSVD, 0x0 */
+ uint32_t SDCLK_DELAY : 10; /* [17: 8], RW, 0x0 */
+ uint32_t TUNING_DLY_INC : 10; /* [27:18], RW, 0x0 */
+ uint32_t Reserved_31_28 : 4; /* [31:28], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } RX_CFG_REG;
+
+ /* 0x118 : TX Configuration Register */
+ union {
+ struct
+ {
+ uint32_t TX_HOLD_DELAY0 : 10; /* [ 9: 0], RW, 0x70 */
+ uint32_t Reserved_15_10 : 6; /* [15:10], RSVD, 0x0 */
+ uint32_t TX_HOLD_DELAY1 : 10; /* [25:16], RW, 0x29 */
+ uint32_t Reserved_29_26 : 4; /* [29:26], RSVD, 0x0 */
+ uint32_t TX_INT_CLK_SEL : 1; /* [ 30], RW, 0x0 */
+ uint32_t TX_MUX_SEL : 1; /* [ 31], RW, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } TX_CFG_REG;
+
+ /* 0x11c : TUNING CONFIG Register */
+ union {
+ struct
+ {
+ uint32_t TUNING_TT_CNT : 8; /* [ 7: 0], RW, 0x27 */
+ uint32_t TUNING_WD_CNT : 6; /* [13: 8], RW, 0x0a */
+ uint32_t TUNING_CLK_DLY : 10; /* [23:14], RO, 0x0 */
+ uint32_t
+ TUNING_SUCCESS_CNT : 6; /* [29:24], RO, 0x0 */
+ uint32_t Reserved_31_30 : 2; /* [31:30], RSVD, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } TUNING_CFG_REG;
+};
+
+typedef volatile struct sdh_reg sdh_reg_t;
+
+#endif /* __SDH_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/sf_ctrl_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/sf_ctrl_reg.h
new file mode 100644
index 00000000..b9d49c88
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/sf_ctrl_reg.h
@@ -0,0 +1,3359 @@
+/**
+ ******************************************************************************
+ * @file sf_ctrl_reg.h
+ * @version V1.0
+ * @date 2021-07-13
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __SF_CTRL_REG_H__
+#define __SF_CTRL_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : sf_ctrl_0 */
+#define SF_CTRL_0_OFFSET (0x0)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL SF_CTRL_SF_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS (2U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN (1U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_GATE_EN SF_CTRL_SF_CLK_OUT_GATE_EN
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS (3U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN (1U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS))
+#define SF_CTRL_SF_CLK_OUT_INV_SEL SF_CTRL_SF_CLK_OUT_INV_SEL
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS (4U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN (1U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF_IF_READ_DLY_N SF_CTRL_SF_IF_READ_DLY_N
+#define SF_CTRL_SF_IF_READ_DLY_N_POS (8U)
+#define SF_CTRL_SF_IF_READ_DLY_N_LEN (3U)
+#define SF_CTRL_SF_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)
+#define SF_CTRL_SF_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS))
+#define SF_CTRL_SF_IF_READ_DLY_EN SF_CTRL_SF_IF_READ_DLY_EN
+#define SF_CTRL_SF_IF_READ_DLY_EN_POS (11U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_LEN (1U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)
+#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS))
+#define SF_CTRL_SF_IF_INT SF_CTRL_SF_IF_INT
+#define SF_CTRL_SF_IF_INT_POS (16U)
+#define SF_CTRL_SF_IF_INT_LEN (1U)
+#define SF_CTRL_SF_IF_INT_MSK (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)
+#define SF_CTRL_SF_IF_INT_UMSK (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS))
+#define SF_CTRL_SF_IF_INT_CLR SF_CTRL_SF_IF_INT_CLR
+#define SF_CTRL_SF_IF_INT_CLR_POS (17U)
+#define SF_CTRL_SF_IF_INT_CLR_LEN (1U)
+#define SF_CTRL_SF_IF_INT_CLR_MSK (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)
+#define SF_CTRL_SF_IF_INT_CLR_UMSK (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS))
+#define SF_CTRL_SF_IF_INT_SET SF_CTRL_SF_IF_INT_SET
+#define SF_CTRL_SF_IF_INT_SET_POS (18U)
+#define SF_CTRL_SF_IF_INT_SET_LEN (1U)
+#define SF_CTRL_SF_IF_INT_SET_MSK (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)
+#define SF_CTRL_SF_IF_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS))
+#define SF_CTRL_SF_IF_32B_ADR_EN SF_CTRL_SF_IF_32B_ADR_EN
+#define SF_CTRL_SF_IF_32B_ADR_EN_POS (19U)
+#define SF_CTRL_SF_IF_32B_ADR_EN_LEN (1U)
+#define SF_CTRL_SF_IF_32B_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_32B_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_32B_ADR_EN_POS)
+#define SF_CTRL_SF_IF_32B_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_32B_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_32B_ADR_EN_POS))
+#define SF_CTRL_SF_AES_DOUT_ENDIAN SF_CTRL_SF_AES_DOUT_ENDIAN
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS (20U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN (1U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS))
+#define SF_CTRL_SF_AES_DIN_ENDIAN SF_CTRL_SF_AES_DIN_ENDIAN
+#define SF_CTRL_SF_AES_DIN_ENDIAN_POS (21U)
+#define SF_CTRL_SF_AES_DIN_ENDIAN_LEN (1U)
+#define SF_CTRL_SF_AES_DIN_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_DIN_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DIN_ENDIAN_POS)
+#define SF_CTRL_SF_AES_DIN_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_DIN_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DIN_ENDIAN_POS))
+#define SF_CTRL_SF_AES_KEY_ENDIAN SF_CTRL_SF_AES_KEY_ENDIAN
+#define SF_CTRL_SF_AES_KEY_ENDIAN_POS (22U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN (1U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS))
+#define SF_CTRL_SF_AES_IV_ENDIAN SF_CTRL_SF_AES_IV_ENDIAN
+#define SF_CTRL_SF_AES_IV_ENDIAN_POS (23U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_LEN (1U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)
+#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS))
+#define SF_CTRL_SF_ID SF_CTRL_SF_ID
+#define SF_CTRL_SF_ID_POS (24U)
+#define SF_CTRL_SF_ID_LEN (8U)
+#define SF_CTRL_SF_ID_MSK (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)
+#define SF_CTRL_SF_ID_UMSK (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS))
+
+/* 0x4 : sf_ctrl_1 */
+#define SF_CTRL_1_OFFSET (0x4)
+#define SF_CTRL_SF_IF_SR_PAT_MASK SF_CTRL_SF_IF_SR_PAT_MASK
+#define SF_CTRL_SF_IF_SR_PAT_MASK_POS (0U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS))
+#define SF_CTRL_SF_IF_SR_PAT SF_CTRL_SF_IF_SR_PAT
+#define SF_CTRL_SF_IF_SR_PAT_POS (8U)
+#define SF_CTRL_SF_IF_SR_PAT_LEN (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)
+#define SF_CTRL_SF_IF_SR_PAT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS))
+#define SF_CTRL_SF_IF_SR_INT SF_CTRL_SF_IF_SR_INT
+#define SF_CTRL_SF_IF_SR_INT_POS (16U)
+#define SF_CTRL_SF_IF_SR_INT_LEN (1U)
+#define SF_CTRL_SF_IF_SR_INT_MSK (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)
+#define SF_CTRL_SF_IF_SR_INT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS))
+#define SF_CTRL_SF_IF_SR_INT_EN SF_CTRL_SF_IF_SR_INT_EN
+#define SF_CTRL_SF_IF_SR_INT_EN_POS (17U)
+#define SF_CTRL_SF_IF_SR_INT_EN_LEN (1U)
+#define SF_CTRL_SF_IF_SR_INT_EN_MSK (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)
+#define SF_CTRL_SF_IF_SR_INT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS))
+#define SF_CTRL_SF_IF_SR_INT_SET SF_CTRL_SF_IF_SR_INT_SET
+#define SF_CTRL_SF_IF_SR_INT_SET_POS (18U)
+#define SF_CTRL_SF_IF_SR_INT_SET_LEN (1U)
+#define SF_CTRL_SF_IF_SR_INT_SET_MSK (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)
+#define SF_CTRL_SF_IF_SR_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS))
+#define SF_CTRL_SF_IF_0_ACK_LAT SF_CTRL_SF_IF_0_ACK_LAT
+#define SF_CTRL_SF_IF_0_ACK_LAT_POS (20U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_LEN (3U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS))
+#define SF_CTRL_SF_AHB2SIF_DISWRAP SF_CTRL_SF_AHB2SIF_DISWRAP
+#define SF_CTRL_SF_AHB2SIF_DISWRAP_POS (23U)
+#define SF_CTRL_SF_AHB2SIF_DISWRAP_LEN (1U)
+#define SF_CTRL_SF_AHB2SIF_DISWRAP_MSK (((1U << SF_CTRL_SF_AHB2SIF_DISWRAP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_DISWRAP_POS)
+#define SF_CTRL_SF_AHB2SIF_DISWRAP_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_DISWRAP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_DISWRAP_POS))
+#define SF_CTRL_SF_IF_REG_HOLD SF_CTRL_SF_IF_REG_HOLD
+#define SF_CTRL_SF_IF_REG_HOLD_POS (24U)
+#define SF_CTRL_SF_IF_REG_HOLD_LEN (1U)
+#define SF_CTRL_SF_IF_REG_HOLD_MSK (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)
+#define SF_CTRL_SF_IF_REG_HOLD_UMSK (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS))
+#define SF_CTRL_SF_IF_REG_WP SF_CTRL_SF_IF_REG_WP
+#define SF_CTRL_SF_IF_REG_WP_POS (25U)
+#define SF_CTRL_SF_IF_REG_WP_LEN (1U)
+#define SF_CTRL_SF_IF_REG_WP_MSK (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)
+#define SF_CTRL_SF_IF_REG_WP_UMSK (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS))
+#define SF_CTRL_SF_AHB2SIF_STOPPED SF_CTRL_SF_AHB2SIF_STOPPED
+#define SF_CTRL_SF_AHB2SIF_STOPPED_POS (26U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN (1U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS))
+#define SF_CTRL_SF_AHB2SIF_STOP SF_CTRL_SF_AHB2SIF_STOP
+#define SF_CTRL_SF_AHB2SIF_STOP_POS (27U)
+#define SF_CTRL_SF_AHB2SIF_STOP_LEN (1U)
+#define SF_CTRL_SF_AHB2SIF_STOP_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)
+#define SF_CTRL_SF_AHB2SIF_STOP_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS))
+#define SF_CTRL_SF_IF_FN_SEL SF_CTRL_SF_IF_FN_SEL
+#define SF_CTRL_SF_IF_FN_SEL_POS (28U)
+#define SF_CTRL_SF_IF_FN_SEL_LEN (1U)
+#define SF_CTRL_SF_IF_FN_SEL_MSK (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)
+#define SF_CTRL_SF_IF_FN_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS))
+#define SF_CTRL_SF_IF_EN SF_CTRL_SF_IF_EN
+#define SF_CTRL_SF_IF_EN_POS (29U)
+#define SF_CTRL_SF_IF_EN_LEN (1U)
+#define SF_CTRL_SF_IF_EN_MSK (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)
+#define SF_CTRL_SF_IF_EN_UMSK (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS))
+#define SF_CTRL_SF_AHB2SIF_EN SF_CTRL_SF_AHB2SIF_EN
+#define SF_CTRL_SF_AHB2SIF_EN_POS (30U)
+#define SF_CTRL_SF_AHB2SIF_EN_LEN (1U)
+#define SF_CTRL_SF_AHB2SIF_EN_MSK (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)
+#define SF_CTRL_SF_AHB2SIF_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS))
+#define SF_CTRL_SF_AHB2SRAM_EN SF_CTRL_SF_AHB2SRAM_EN
+#define SF_CTRL_SF_AHB2SRAM_EN_POS (31U)
+#define SF_CTRL_SF_AHB2SRAM_EN_LEN (1U)
+#define SF_CTRL_SF_AHB2SRAM_EN_MSK (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)
+#define SF_CTRL_SF_AHB2SRAM_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS))
+
+/* 0x8 : sf_if_sahb_0 */
+#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8)
+#define SF_CTRL_SF_IF_BUSY SF_CTRL_SF_IF_BUSY
+#define SF_CTRL_SF_IF_BUSY_POS (0U)
+#define SF_CTRL_SF_IF_BUSY_LEN (1U)
+#define SF_CTRL_SF_IF_BUSY_MSK (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)
+#define SF_CTRL_SF_IF_BUSY_UMSK (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS))
+#define SF_CTRL_SF_IF_0_TRIG SF_CTRL_SF_IF_0_TRIG
+#define SF_CTRL_SF_IF_0_TRIG_POS (1U)
+#define SF_CTRL_SF_IF_0_TRIG_LEN (1U)
+#define SF_CTRL_SF_IF_0_TRIG_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)
+#define SF_CTRL_SF_IF_0_TRIG_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS))
+#define SF_CTRL_SF_IF_0_DAT_BYTE SF_CTRL_SF_IF_0_DAT_BYTE
+#define SF_CTRL_SF_IF_0_DAT_BYTE_POS (2U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN (10U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DMY_BYTE SF_CTRL_SF_IF_0_DMY_BYTE
+#define SF_CTRL_SF_IF_0_DMY_BYTE_POS (12U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN (5U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_0_ADR_BYTE SF_CTRL_SF_IF_0_ADR_BYTE
+#define SF_CTRL_SF_IF_0_ADR_BYTE_POS (17U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_0_CMD_BYTE SF_CTRL_SF_IF_0_CMD_BYTE
+#define SF_CTRL_SF_IF_0_CMD_BYTE_POS (20U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DAT_RW SF_CTRL_SF_IF_0_DAT_RW
+#define SF_CTRL_SF_IF_0_DAT_RW_POS (23U)
+#define SF_CTRL_SF_IF_0_DAT_RW_LEN (1U)
+#define SF_CTRL_SF_IF_0_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)
+#define SF_CTRL_SF_IF_0_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS))
+#define SF_CTRL_SF_IF_0_DAT_EN SF_CTRL_SF_IF_0_DAT_EN
+#define SF_CTRL_SF_IF_0_DAT_EN_POS (24U)
+#define SF_CTRL_SF_IF_0_DAT_EN_LEN (1U)
+#define SF_CTRL_SF_IF_0_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)
+#define SF_CTRL_SF_IF_0_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS))
+#define SF_CTRL_SF_IF_0_DMY_EN SF_CTRL_SF_IF_0_DMY_EN
+#define SF_CTRL_SF_IF_0_DMY_EN_POS (25U)
+#define SF_CTRL_SF_IF_0_DMY_EN_LEN (1U)
+#define SF_CTRL_SF_IF_0_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)
+#define SF_CTRL_SF_IF_0_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS))
+#define SF_CTRL_SF_IF_0_ADR_EN SF_CTRL_SF_IF_0_ADR_EN
+#define SF_CTRL_SF_IF_0_ADR_EN_POS (26U)
+#define SF_CTRL_SF_IF_0_ADR_EN_LEN (1U)
+#define SF_CTRL_SF_IF_0_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)
+#define SF_CTRL_SF_IF_0_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS))
+#define SF_CTRL_SF_IF_0_CMD_EN SF_CTRL_SF_IF_0_CMD_EN
+#define SF_CTRL_SF_IF_0_CMD_EN_POS (27U)
+#define SF_CTRL_SF_IF_0_CMD_EN_LEN (1U)
+#define SF_CTRL_SF_IF_0_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)
+#define SF_CTRL_SF_IF_0_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS))
+#define SF_CTRL_SF_IF_0_SPI_MODE SF_CTRL_SF_IF_0_SPI_MODE
+#define SF_CTRL_SF_IF_0_SPI_MODE_POS (28U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_LEN (3U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN SF_CTRL_SF_IF_0_QPI_MODE_EN
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS (31U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN (1U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS))
+
+/* 0xC : sf_if_sahb_1 */
+#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0 SF_CTRL_SF_IF_0_CMD_BUF_0
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS))
+
+/* 0x10 : sf_if_sahb_2 */
+#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1 SF_CTRL_SF_IF_0_CMD_BUF_1
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS))
+
+/* 0x14 : sf_if_iahb_0 */
+#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14)
+#define SF_CTRL_SF_IF_1_DMY_BYTE SF_CTRL_SF_IF_1_DMY_BYTE
+#define SF_CTRL_SF_IF_1_DMY_BYTE_POS (12U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN (5U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_1_ADR_BYTE SF_CTRL_SF_IF_1_ADR_BYTE
+#define SF_CTRL_SF_IF_1_ADR_BYTE_POS (17U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_1_CMD_BYTE SF_CTRL_SF_IF_1_CMD_BYTE
+#define SF_CTRL_SF_IF_1_CMD_BYTE_POS (20U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_1_DAT_RW SF_CTRL_SF_IF_1_DAT_RW
+#define SF_CTRL_SF_IF_1_DAT_RW_POS (23U)
+#define SF_CTRL_SF_IF_1_DAT_RW_LEN (1U)
+#define SF_CTRL_SF_IF_1_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)
+#define SF_CTRL_SF_IF_1_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS))
+#define SF_CTRL_SF_IF_1_DAT_EN SF_CTRL_SF_IF_1_DAT_EN
+#define SF_CTRL_SF_IF_1_DAT_EN_POS (24U)
+#define SF_CTRL_SF_IF_1_DAT_EN_LEN (1U)
+#define SF_CTRL_SF_IF_1_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)
+#define SF_CTRL_SF_IF_1_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS))
+#define SF_CTRL_SF_IF_1_DMY_EN SF_CTRL_SF_IF_1_DMY_EN
+#define SF_CTRL_SF_IF_1_DMY_EN_POS (25U)
+#define SF_CTRL_SF_IF_1_DMY_EN_LEN (1U)
+#define SF_CTRL_SF_IF_1_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)
+#define SF_CTRL_SF_IF_1_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS))
+#define SF_CTRL_SF_IF_1_ADR_EN SF_CTRL_SF_IF_1_ADR_EN
+#define SF_CTRL_SF_IF_1_ADR_EN_POS (26U)
+#define SF_CTRL_SF_IF_1_ADR_EN_LEN (1U)
+#define SF_CTRL_SF_IF_1_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)
+#define SF_CTRL_SF_IF_1_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS))
+#define SF_CTRL_SF_IF_1_CMD_EN SF_CTRL_SF_IF_1_CMD_EN
+#define SF_CTRL_SF_IF_1_CMD_EN_POS (27U)
+#define SF_CTRL_SF_IF_1_CMD_EN_LEN (1U)
+#define SF_CTRL_SF_IF_1_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)
+#define SF_CTRL_SF_IF_1_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS))
+#define SF_CTRL_SF_IF_1_SPI_MODE SF_CTRL_SF_IF_1_SPI_MODE
+#define SF_CTRL_SF_IF_1_SPI_MODE_POS (28U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_LEN (3U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN SF_CTRL_SF_IF_1_QPI_MODE_EN
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS (31U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN (1U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS))
+
+/* 0x18 : sf_if_iahb_1 */
+#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0 SF_CTRL_SF_IF_1_CMD_BUF_0
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS))
+
+/* 0x1C : sf_if_iahb_2 */
+#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1 SF_CTRL_SF_IF_1_CMD_BUF_1
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS))
+
+/* 0x20 : sf_if_status_0 */
+#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)
+#define SF_CTRL_SF_IF_STATUS_0 SF_CTRL_SF_IF_STATUS_0
+#define SF_CTRL_SF_IF_STATUS_0_POS (0U)
+#define SF_CTRL_SF_IF_STATUS_0_LEN (32U)
+#define SF_CTRL_SF_IF_STATUS_0_MSK (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)
+#define SF_CTRL_SF_IF_STATUS_0_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS))
+
+/* 0x24 : sf_if_status_1 */
+#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)
+#define SF_CTRL_SF_IF_STATUS_1 SF_CTRL_SF_IF_STATUS_1
+#define SF_CTRL_SF_IF_STATUS_1_POS (0U)
+#define SF_CTRL_SF_IF_STATUS_1_LEN (32U)
+#define SF_CTRL_SF_IF_STATUS_1_MSK (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)
+#define SF_CTRL_SF_IF_STATUS_1_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS))
+
+/* 0x28 : sf_aes */
+#define SF_CTRL_SF_AES_OFFSET (0x28)
+#define SF_CTRL_SF_AES_EN SF_CTRL_SF_AES_EN
+#define SF_CTRL_SF_AES_EN_POS (0U)
+#define SF_CTRL_SF_AES_EN_LEN (1U)
+#define SF_CTRL_SF_AES_EN_MSK (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)
+#define SF_CTRL_SF_AES_EN_UMSK (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS))
+#define SF_CTRL_SF_AES_MODE SF_CTRL_SF_AES_MODE
+#define SF_CTRL_SF_AES_MODE_POS (1U)
+#define SF_CTRL_SF_AES_MODE_LEN (2U)
+#define SF_CTRL_SF_AES_MODE_MSK (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)
+#define SF_CTRL_SF_AES_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS))
+#define SF_CTRL_SF_AES_BLK_MODE SF_CTRL_SF_AES_BLK_MODE
+#define SF_CTRL_SF_AES_BLK_MODE_POS (3U)
+#define SF_CTRL_SF_AES_BLK_MODE_LEN (1U)
+#define SF_CTRL_SF_AES_BLK_MODE_MSK (((1U << SF_CTRL_SF_AES_BLK_MODE_LEN) - 1) << SF_CTRL_SF_AES_BLK_MODE_POS)
+#define SF_CTRL_SF_AES_BLK_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_BLK_MODE_LEN) - 1) << SF_CTRL_SF_AES_BLK_MODE_POS))
+#define SF_CTRL_SF_AES_XTS_KEY_OPT SF_CTRL_SF_AES_XTS_KEY_OPT
+#define SF_CTRL_SF_AES_XTS_KEY_OPT_POS (4U)
+#define SF_CTRL_SF_AES_XTS_KEY_OPT_LEN (1U)
+#define SF_CTRL_SF_AES_XTS_KEY_OPT_MSK (((1U << SF_CTRL_SF_AES_XTS_KEY_OPT_LEN) - 1) << SF_CTRL_SF_AES_XTS_KEY_OPT_POS)
+#define SF_CTRL_SF_AES_XTS_KEY_OPT_UMSK (~(((1U << SF_CTRL_SF_AES_XTS_KEY_OPT_LEN) - 1) << SF_CTRL_SF_AES_XTS_KEY_OPT_POS))
+#define SF_CTRL_SF_AES_STATUS SF_CTRL_SF_AES_STATUS
+#define SF_CTRL_SF_AES_STATUS_POS (5U)
+#define SF_CTRL_SF_AES_STATUS_LEN (27U)
+#define SF_CTRL_SF_AES_STATUS_MSK (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)
+#define SF_CTRL_SF_AES_STATUS_UMSK (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS))
+
+/* 0x2C : sf_ahb2sif_status */
+#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)
+#define SF_CTRL_SF_AHB2SIF_STATUS SF_CTRL_SF_AHB2SIF_STATUS
+#define SF_CTRL_SF_AHB2SIF_STATUS_POS (0U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_LEN (32U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_MSK (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)
+#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS))
+
+/* 0x30 : sf_if_io_dly_0 */
+#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30)
+#define SF_CTRL_SF_CS_DLY_SEL SF_CTRL_SF_CS_DLY_SEL
+#define SF_CTRL_SF_CS_DLY_SEL_POS (0U)
+#define SF_CTRL_SF_CS_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)
+#define SF_CTRL_SF_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS))
+#define SF_CTRL_SF_CS2_DLY_SEL SF_CTRL_SF_CS2_DLY_SEL
+#define SF_CTRL_SF_CS2_DLY_SEL_POS (2U)
+#define SF_CTRL_SF_CS2_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL SF_CTRL_SF_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS (8U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_OE_DLY_SEL SF_CTRL_SF_DQS_OE_DLY_SEL
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS (26U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DI_DLY_SEL SF_CTRL_SF_DQS_DI_DLY_SEL
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS (28U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DO_DLY_SEL SF_CTRL_SF_DQS_DO_DLY_SEL
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS (30U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS))
+
+/* 0x34 : sf_if_io_dly_1 */
+#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL SF_CTRL_SF_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL SF_CTRL_SF_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL SF_CTRL_SF_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS))
+
+/* 0x38 : sf_if_io_dly_2 */
+#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL SF_CTRL_SF_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL SF_CTRL_SF_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL SF_CTRL_SF_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS))
+
+/* 0x3C : sf_if_io_dly_3 */
+#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL SF_CTRL_SF_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL SF_CTRL_SF_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL SF_CTRL_SF_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS))
+
+/* 0x40 : sf_if_io_dly_4 */
+#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL SF_CTRL_SF_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL SF_CTRL_SF_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL SF_CTRL_SF_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS))
+
+/* 0x44 : sf_reserved */
+#define SF_CTRL_SF_RESERVED_OFFSET (0x44)
+#define SF_CTRL_SF_RESERVED SF_CTRL_SF_RESERVED
+#define SF_CTRL_SF_RESERVED_POS (0U)
+#define SF_CTRL_SF_RESERVED_LEN (32U)
+#define SF_CTRL_SF_RESERVED_MSK (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)
+#define SF_CTRL_SF_RESERVED_UMSK (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS))
+
+/* 0x48 : sf2_if_io_dly_0 */
+#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48)
+#define SF_CTRL_SF2_CS_DLY_SEL SF_CTRL_SF2_CS_DLY_SEL
+#define SF_CTRL_SF2_CS_DLY_SEL_POS (0U)
+#define SF_CTRL_SF2_CS_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)
+#define SF_CTRL_SF2_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS))
+#define SF_CTRL_SF2_CS2_DLY_SEL SF_CTRL_SF2_CS2_DLY_SEL
+#define SF_CTRL_SF2_CS2_DLY_SEL_POS (2U)
+#define SF_CTRL_SF2_CS2_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF2_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL SF_CTRL_SF2_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS (8U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL SF_CTRL_SF2_DQS_OE_DLY_SEL
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS (26U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL SF_CTRL_SF2_DQS_DI_DLY_SEL
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS (28U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL SF_CTRL_SF2_DQS_DO_DLY_SEL
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS (30U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS))
+
+/* 0x4C : sf2_if_io_dly_1 */
+#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL SF_CTRL_SF2_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL SF_CTRL_SF2_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL SF_CTRL_SF2_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS))
+
+/* 0x50 : sf2_if_io_dly_2 */
+#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL SF_CTRL_SF2_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL SF_CTRL_SF2_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL SF_CTRL_SF2_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS))
+
+/* 0x54 : sf2_if_io_dly_3 */
+#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL SF_CTRL_SF2_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL SF_CTRL_SF2_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL SF_CTRL_SF2_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS))
+
+/* 0x58 : sf2_if_io_dly_4 */
+#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL SF_CTRL_SF2_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL SF_CTRL_SF2_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL SF_CTRL_SF2_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS))
+
+/* 0x5C : sf3_if_io_dly_0 */
+#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C)
+#define SF_CTRL_SF3_CS_DLY_SEL SF_CTRL_SF3_CS_DLY_SEL
+#define SF_CTRL_SF3_CS_DLY_SEL_POS (0U)
+#define SF_CTRL_SF3_CS_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)
+#define SF_CTRL_SF3_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS))
+#define SF_CTRL_SF3_CS2_DLY_SEL SF_CTRL_SF3_CS2_DLY_SEL
+#define SF_CTRL_SF3_CS2_DLY_SEL_POS (2U)
+#define SF_CTRL_SF3_CS2_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF3_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL SF_CTRL_SF3_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS (8U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL SF_CTRL_SF3_DQS_OE_DLY_SEL
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS (26U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL SF_CTRL_SF3_DQS_DI_DLY_SEL
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS (28U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL SF_CTRL_SF3_DQS_DO_DLY_SEL
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS (30U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS))
+
+/* 0x60 : sf3_if_io_dly_1 */
+#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL SF_CTRL_SF3_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL SF_CTRL_SF3_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL SF_CTRL_SF3_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS))
+
+/* 0x64 : sf3_if_io_dly_2 */
+#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL SF_CTRL_SF3_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL SF_CTRL_SF3_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL SF_CTRL_SF3_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS))
+
+/* 0x68 : sf3_if_io_dly_3 */
+#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL SF_CTRL_SF3_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL SF_CTRL_SF3_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL SF_CTRL_SF3_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS))
+
+/* 0x6C : sf3_if_io_dly_4 */
+#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL SF_CTRL_SF3_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL SF_CTRL_SF3_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL SF_CTRL_SF3_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS))
+
+/* 0x70 : sf_ctrl_2 */
+#define SF_CTRL_2_OFFSET (0x70)
+#define SF_CTRL_SF_IF_PAD_SEL SF_CTRL_SF_IF_PAD_SEL
+#define SF_CTRL_SF_IF_PAD_SEL_POS (0U)
+#define SF_CTRL_SF_IF_PAD_SEL_LEN (2U)
+#define SF_CTRL_SF_IF_PAD_SEL_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS))
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK SF_CTRL_SF_IF_PAD_SEL_LOCK
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS (3U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN (1U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS))
+#define SF_CTRL_SF_IF_DTR_EN SF_CTRL_SF_IF_DTR_EN
+#define SF_CTRL_SF_IF_DTR_EN_POS (4U)
+#define SF_CTRL_SF_IF_DTR_EN_LEN (1U)
+#define SF_CTRL_SF_IF_DTR_EN_MSK (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)
+#define SF_CTRL_SF_IF_DTR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS))
+#define SF_CTRL_SF_IF_DQS_EN SF_CTRL_SF_IF_DQS_EN
+#define SF_CTRL_SF_IF_DQS_EN_POS (5U)
+#define SF_CTRL_SF_IF_DQS_EN_LEN (1U)
+#define SF_CTRL_SF_IF_DQS_EN_MSK (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)
+#define SF_CTRL_SF_IF_DQS_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS))
+#define SF_CTRL_SF_IF_TRIG_WR_PROT SF_CTRL_SF_IF_TRIG_WR_PROT
+#define SF_CTRL_SF_IF_TRIG_WR_PROT_POS (6U)
+#define SF_CTRL_SF_IF_TRIG_WR_PROT_LEN (1U)
+#define SF_CTRL_SF_IF_TRIG_WR_PROT_MSK (((1U << SF_CTRL_SF_IF_TRIG_WR_PROT_LEN) - 1) << SF_CTRL_SF_IF_TRIG_WR_PROT_POS)
+#define SF_CTRL_SF_IF_TRIG_WR_PROT_UMSK (~(((1U << SF_CTRL_SF_IF_TRIG_WR_PROT_LEN) - 1) << SF_CTRL_SF_IF_TRIG_WR_PROT_POS))
+#define SF_CTRL_SF_ID_OFFSET_LOCK SF_CTRL_SF_ID_OFFSET_LOCK
+#define SF_CTRL_SF_ID_OFFSET_LOCK_POS (7U)
+#define SF_CTRL_SF_ID_OFFSET_LOCK_LEN (1U)
+#define SF_CTRL_SF_ID_OFFSET_LOCK_MSK (((1U << SF_CTRL_SF_ID_OFFSET_LOCK_LEN) - 1) << SF_CTRL_SF_ID_OFFSET_LOCK_POS)
+#define SF_CTRL_SF_ID_OFFSET_LOCK_UMSK (~(((1U << SF_CTRL_SF_ID_OFFSET_LOCK_LEN) - 1) << SF_CTRL_SF_ID_OFFSET_LOCK_POS))
+#define SF_CTRL_SF_AHB2SIF_REMAP_LOCK SF_CTRL_SF_AHB2SIF_REMAP_LOCK
+#define SF_CTRL_SF_AHB2SIF_REMAP_LOCK_POS (25U)
+#define SF_CTRL_SF_AHB2SIF_REMAP_LOCK_LEN (1U)
+#define SF_CTRL_SF_AHB2SIF_REMAP_LOCK_MSK (((1U << SF_CTRL_SF_AHB2SIF_REMAP_LOCK_LEN) - 1) << SF_CTRL_SF_AHB2SIF_REMAP_LOCK_POS)
+#define SF_CTRL_SF_AHB2SIF_REMAP_LOCK_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_REMAP_LOCK_LEN) - 1) << SF_CTRL_SF_AHB2SIF_REMAP_LOCK_POS))
+#define SF_CTRL_SF_AHB2SIF_REMAP SF_CTRL_SF_AHB2SIF_REMAP
+#define SF_CTRL_SF_AHB2SIF_REMAP_POS (26U)
+#define SF_CTRL_SF_AHB2SIF_REMAP_LEN (2U)
+#define SF_CTRL_SF_AHB2SIF_REMAP_MSK (((1U << SF_CTRL_SF_AHB2SIF_REMAP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_REMAP_POS)
+#define SF_CTRL_SF_AHB2SIF_REMAP_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_REMAP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_REMAP_POS))
+#define SF_CTRL_SF_IF_BK_SWAP SF_CTRL_SF_IF_BK_SWAP
+#define SF_CTRL_SF_IF_BK_SWAP_POS (28U)
+#define SF_CTRL_SF_IF_BK_SWAP_LEN (1U)
+#define SF_CTRL_SF_IF_BK_SWAP_MSK (((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS)
+#define SF_CTRL_SF_IF_BK_SWAP_UMSK (~(((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS))
+#define SF_CTRL_SF_IF_BK2_MODE SF_CTRL_SF_IF_BK2_MODE
+#define SF_CTRL_SF_IF_BK2_MODE_POS (29U)
+#define SF_CTRL_SF_IF_BK2_MODE_LEN (1U)
+#define SF_CTRL_SF_IF_BK2_MODE_MSK (((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS)
+#define SF_CTRL_SF_IF_BK2_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS))
+#define SF_CTRL_SF_IF_BK2_EN SF_CTRL_SF_IF_BK2_EN
+#define SF_CTRL_SF_IF_BK2_EN_POS (30U)
+#define SF_CTRL_SF_IF_BK2_EN_LEN (1U)
+#define SF_CTRL_SF_IF_BK2_EN_MSK (((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS)
+#define SF_CTRL_SF_IF_BK2_EN_UMSK (~(((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS))
+#define SF_CTRL_SF_IF_0_BK_SEL SF_CTRL_SF_IF_0_BK_SEL
+#define SF_CTRL_SF_IF_0_BK_SEL_POS (31U)
+#define SF_CTRL_SF_IF_0_BK_SEL_LEN (1U)
+#define SF_CTRL_SF_IF_0_BK_SEL_MSK (((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS)
+#define SF_CTRL_SF_IF_0_BK_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS))
+
+/* 0x74 : sf_ctrl_3 */
+#define SF_CTRL_3_OFFSET (0x74)
+#define SF_CTRL_SF_CMDS_2_WRAP_LEN SF_CTRL_SF_CMDS_2_WRAP_LEN
+#define SF_CTRL_SF_CMDS_2_WRAP_LEN_POS (0U)
+#define SF_CTRL_SF_CMDS_2_WRAP_LEN_LEN (4U)
+#define SF_CTRL_SF_CMDS_2_WRAP_LEN_MSK (((1U << SF_CTRL_SF_CMDS_2_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_LEN_POS)
+#define SF_CTRL_SF_CMDS_2_WRAP_LEN_UMSK (~(((1U << SF_CTRL_SF_CMDS_2_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_LEN_POS))
+#define SF_CTRL_SF_CMDS_2_EN SF_CTRL_SF_CMDS_2_EN
+#define SF_CTRL_SF_CMDS_2_EN_POS (4U)
+#define SF_CTRL_SF_CMDS_2_EN_LEN (1U)
+#define SF_CTRL_SF_CMDS_2_EN_MSK (((1U << SF_CTRL_SF_CMDS_2_EN_LEN) - 1) << SF_CTRL_SF_CMDS_2_EN_POS)
+#define SF_CTRL_SF_CMDS_2_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_2_EN_LEN) - 1) << SF_CTRL_SF_CMDS_2_EN_POS))
+#define SF_CTRL_SF_CMDS_2_BT_DLY SF_CTRL_SF_CMDS_2_BT_DLY
+#define SF_CTRL_SF_CMDS_2_BT_DLY_POS (5U)
+#define SF_CTRL_SF_CMDS_2_BT_DLY_LEN (3U)
+#define SF_CTRL_SF_CMDS_2_BT_DLY_MSK (((1U << SF_CTRL_SF_CMDS_2_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_2_BT_DLY_POS)
+#define SF_CTRL_SF_CMDS_2_BT_DLY_UMSK (~(((1U << SF_CTRL_SF_CMDS_2_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_2_BT_DLY_POS))
+#define SF_CTRL_SF_CMDS_2_BT_EN SF_CTRL_SF_CMDS_2_BT_EN
+#define SF_CTRL_SF_CMDS_2_BT_EN_POS (8U)
+#define SF_CTRL_SF_CMDS_2_BT_EN_LEN (1U)
+#define SF_CTRL_SF_CMDS_2_BT_EN_MSK (((1U << SF_CTRL_SF_CMDS_2_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_2_BT_EN_POS)
+#define SF_CTRL_SF_CMDS_2_BT_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_2_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_2_BT_EN_POS))
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_INI SF_CTRL_SF_CMDS_2_WRAP_Q_INI
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_INI_POS (9U)
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_INI_LEN (1U)
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_INI_MSK (((1U << SF_CTRL_SF_CMDS_2_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_Q_INI_POS)
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_2_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_Q_INI_POS))
+#define SF_CTRL_SF_CMDS_2_WRAP_MODE SF_CTRL_SF_CMDS_2_WRAP_MODE
+#define SF_CTRL_SF_CMDS_2_WRAP_MODE_POS (10U)
+#define SF_CTRL_SF_CMDS_2_WRAP_MODE_LEN (2U)
+#define SF_CTRL_SF_CMDS_2_WRAP_MODE_MSK (((1U << SF_CTRL_SF_CMDS_2_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_MODE_POS)
+#define SF_CTRL_SF_CMDS_2_WRAP_MODE_UMSK (~(((1U << SF_CTRL_SF_CMDS_2_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_MODE_POS))
+#define SF_CTRL_SF_CMDS_2_WRAP_Q SF_CTRL_SF_CMDS_2_WRAP_Q
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_POS (12U)
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_LEN (1U)
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_MSK (((1U << SF_CTRL_SF_CMDS_2_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_Q_POS)
+#define SF_CTRL_SF_CMDS_2_WRAP_Q_UMSK (~(((1U << SF_CTRL_SF_CMDS_2_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_2_WRAP_Q_POS))
+#define SF_CTRL_SF_CMDS_1_WRAP_LEN SF_CTRL_SF_CMDS_1_WRAP_LEN
+#define SF_CTRL_SF_CMDS_1_WRAP_LEN_POS (13U)
+#define SF_CTRL_SF_CMDS_1_WRAP_LEN_LEN (4U)
+#define SF_CTRL_SF_CMDS_1_WRAP_LEN_MSK (((1U << SF_CTRL_SF_CMDS_1_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_1_WRAP_LEN_POS)
+#define SF_CTRL_SF_CMDS_1_WRAP_LEN_UMSK (~(((1U << SF_CTRL_SF_CMDS_1_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_1_WRAP_LEN_POS))
+#define SF_CTRL_SF_CMDS_1_EN SF_CTRL_SF_CMDS_1_EN
+#define SF_CTRL_SF_CMDS_1_EN_POS (17U)
+#define SF_CTRL_SF_CMDS_1_EN_LEN (1U)
+#define SF_CTRL_SF_CMDS_1_EN_MSK (((1U << SF_CTRL_SF_CMDS_1_EN_LEN) - 1) << SF_CTRL_SF_CMDS_1_EN_POS)
+#define SF_CTRL_SF_CMDS_1_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_1_EN_LEN) - 1) << SF_CTRL_SF_CMDS_1_EN_POS))
+#define SF_CTRL_SF_CMDS_1_WRAP_MODE SF_CTRL_SF_CMDS_1_WRAP_MODE
+#define SF_CTRL_SF_CMDS_1_WRAP_MODE_POS (18U)
+#define SF_CTRL_SF_CMDS_1_WRAP_MODE_LEN (2U)
+#define SF_CTRL_SF_CMDS_1_WRAP_MODE_MSK (((1U << SF_CTRL_SF_CMDS_1_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_1_WRAP_MODE_POS)
+#define SF_CTRL_SF_CMDS_1_WRAP_MODE_UMSK (~(((1U << SF_CTRL_SF_CMDS_1_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_1_WRAP_MODE_POS))
+#define SF_CTRL_SF_CMDS_CORE_EN SF_CTRL_SF_CMDS_CORE_EN
+#define SF_CTRL_SF_CMDS_CORE_EN_POS (20U)
+#define SF_CTRL_SF_CMDS_CORE_EN_LEN (1U)
+#define SF_CTRL_SF_CMDS_CORE_EN_MSK (((1U << SF_CTRL_SF_CMDS_CORE_EN_LEN) - 1) << SF_CTRL_SF_CMDS_CORE_EN_POS)
+#define SF_CTRL_SF_CMDS_CORE_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_CORE_EN_LEN) - 1) << SF_CTRL_SF_CMDS_CORE_EN_POS))
+#define SF_CTRL_SF_IF_1_ACK_LAT SF_CTRL_SF_IF_1_ACK_LAT
+#define SF_CTRL_SF_IF_1_ACK_LAT_POS (29U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_LEN (3U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS))
+
+/* 0x78 : sf_if_iahb_3 */
+#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78)
+#define SF_CTRL_SF_IF_2_DMY_BYTE SF_CTRL_SF_IF_2_DMY_BYTE
+#define SF_CTRL_SF_IF_2_DMY_BYTE_POS (12U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN (5U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_2_ADR_BYTE SF_CTRL_SF_IF_2_ADR_BYTE
+#define SF_CTRL_SF_IF_2_ADR_BYTE_POS (17U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_2_CMD_BYTE SF_CTRL_SF_IF_2_CMD_BYTE
+#define SF_CTRL_SF_IF_2_CMD_BYTE_POS (20U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_2_DAT_RW SF_CTRL_SF_IF_2_DAT_RW
+#define SF_CTRL_SF_IF_2_DAT_RW_POS (23U)
+#define SF_CTRL_SF_IF_2_DAT_RW_LEN (1U)
+#define SF_CTRL_SF_IF_2_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)
+#define SF_CTRL_SF_IF_2_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS))
+#define SF_CTRL_SF_IF_2_DAT_EN SF_CTRL_SF_IF_2_DAT_EN
+#define SF_CTRL_SF_IF_2_DAT_EN_POS (24U)
+#define SF_CTRL_SF_IF_2_DAT_EN_LEN (1U)
+#define SF_CTRL_SF_IF_2_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)
+#define SF_CTRL_SF_IF_2_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS))
+#define SF_CTRL_SF_IF_2_DMY_EN SF_CTRL_SF_IF_2_DMY_EN
+#define SF_CTRL_SF_IF_2_DMY_EN_POS (25U)
+#define SF_CTRL_SF_IF_2_DMY_EN_LEN (1U)
+#define SF_CTRL_SF_IF_2_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)
+#define SF_CTRL_SF_IF_2_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS))
+#define SF_CTRL_SF_IF_2_ADR_EN SF_CTRL_SF_IF_2_ADR_EN
+#define SF_CTRL_SF_IF_2_ADR_EN_POS (26U)
+#define SF_CTRL_SF_IF_2_ADR_EN_LEN (1U)
+#define SF_CTRL_SF_IF_2_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)
+#define SF_CTRL_SF_IF_2_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS))
+#define SF_CTRL_SF_IF_2_CMD_EN SF_CTRL_SF_IF_2_CMD_EN
+#define SF_CTRL_SF_IF_2_CMD_EN_POS (27U)
+#define SF_CTRL_SF_IF_2_CMD_EN_LEN (1U)
+#define SF_CTRL_SF_IF_2_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)
+#define SF_CTRL_SF_IF_2_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS))
+#define SF_CTRL_SF_IF_2_SPI_MODE SF_CTRL_SF_IF_2_SPI_MODE
+#define SF_CTRL_SF_IF_2_SPI_MODE_POS (28U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_LEN (3U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN SF_CTRL_SF_IF_2_QPI_MODE_EN
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS (31U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN (1U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS))
+
+/* 0x7C : sf_if_iahb_4 */
+#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0 SF_CTRL_SF_IF_2_CMD_BUF_0
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS))
+
+/* 0x80 : sf_if_iahb_5 */
+#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1 SF_CTRL_SF_IF_2_CMD_BUF_1
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS))
+
+/* 0x84 : sf_if_iahb_6 */
+#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84)
+#define SF_CTRL_SF_IF_3_ADR_BYTE SF_CTRL_SF_IF_3_ADR_BYTE
+#define SF_CTRL_SF_IF_3_ADR_BYTE_POS (17U)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_3_CMD_BYTE SF_CTRL_SF_IF_3_CMD_BYTE
+#define SF_CTRL_SF_IF_3_CMD_BYTE_POS (20U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_3_ADR_EN SF_CTRL_SF_IF_3_ADR_EN
+#define SF_CTRL_SF_IF_3_ADR_EN_POS (26U)
+#define SF_CTRL_SF_IF_3_ADR_EN_LEN (1U)
+#define SF_CTRL_SF_IF_3_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS)
+#define SF_CTRL_SF_IF_3_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS))
+#define SF_CTRL_SF_IF_3_CMD_EN SF_CTRL_SF_IF_3_CMD_EN
+#define SF_CTRL_SF_IF_3_CMD_EN_POS (27U)
+#define SF_CTRL_SF_IF_3_CMD_EN_LEN (1U)
+#define SF_CTRL_SF_IF_3_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS)
+#define SF_CTRL_SF_IF_3_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS))
+#define SF_CTRL_SF_IF_3_SPI_MODE SF_CTRL_SF_IF_3_SPI_MODE
+#define SF_CTRL_SF_IF_3_SPI_MODE_POS (28U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_LEN (3U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN SF_CTRL_SF_IF_3_QPI_MODE_EN
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS (31U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN (1U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS))
+
+/* 0x88 : sf_if_iahb_7 */
+#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0 SF_CTRL_SF_IF_3_CMD_BUF_0
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS (0U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN (32U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS))
+
+/* 0x8C : sf_if_iahb_8 */
+#define SF_CTRL_SF_IF_IAHB_8_OFFSET (0x8C)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1 SF_CTRL_SF_IF_3_CMD_BUF_1
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_POS (0U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_LEN (32U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS))
+
+/* 0x90 : sf_if_iahb_9 */
+#define SF_CTRL_SF_IF_IAHB_9_OFFSET (0x90)
+#define SF_CTRL_SF_IF_4_DMY_BYTE SF_CTRL_SF_IF_4_DMY_BYTE
+#define SF_CTRL_SF_IF_4_DMY_BYTE_POS (12U)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_LEN (5U)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_4_ADR_BYTE SF_CTRL_SF_IF_4_ADR_BYTE
+#define SF_CTRL_SF_IF_4_ADR_BYTE_POS (17U)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_4_CMD_BYTE SF_CTRL_SF_IF_4_CMD_BYTE
+#define SF_CTRL_SF_IF_4_CMD_BYTE_POS (20U)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_4_DAT_RW SF_CTRL_SF_IF_4_DAT_RW
+#define SF_CTRL_SF_IF_4_DAT_RW_POS (23U)
+#define SF_CTRL_SF_IF_4_DAT_RW_LEN (1U)
+#define SF_CTRL_SF_IF_4_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS)
+#define SF_CTRL_SF_IF_4_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS))
+#define SF_CTRL_SF_IF_4_DAT_EN SF_CTRL_SF_IF_4_DAT_EN
+#define SF_CTRL_SF_IF_4_DAT_EN_POS (24U)
+#define SF_CTRL_SF_IF_4_DAT_EN_LEN (1U)
+#define SF_CTRL_SF_IF_4_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS)
+#define SF_CTRL_SF_IF_4_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS))
+#define SF_CTRL_SF_IF_4_DMY_EN SF_CTRL_SF_IF_4_DMY_EN
+#define SF_CTRL_SF_IF_4_DMY_EN_POS (25U)
+#define SF_CTRL_SF_IF_4_DMY_EN_LEN (1U)
+#define SF_CTRL_SF_IF_4_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS)
+#define SF_CTRL_SF_IF_4_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS))
+#define SF_CTRL_SF_IF_4_ADR_EN SF_CTRL_SF_IF_4_ADR_EN
+#define SF_CTRL_SF_IF_4_ADR_EN_POS (26U)
+#define SF_CTRL_SF_IF_4_ADR_EN_LEN (1U)
+#define SF_CTRL_SF_IF_4_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS)
+#define SF_CTRL_SF_IF_4_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS))
+#define SF_CTRL_SF_IF_4_CMD_EN SF_CTRL_SF_IF_4_CMD_EN
+#define SF_CTRL_SF_IF_4_CMD_EN_POS (27U)
+#define SF_CTRL_SF_IF_4_CMD_EN_LEN (1U)
+#define SF_CTRL_SF_IF_4_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS)
+#define SF_CTRL_SF_IF_4_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS))
+#define SF_CTRL_SF_IF_4_SPI_MODE SF_CTRL_SF_IF_4_SPI_MODE
+#define SF_CTRL_SF_IF_4_SPI_MODE_POS (28U)
+#define SF_CTRL_SF_IF_4_SPI_MODE_LEN (3U)
+#define SF_CTRL_SF_IF_4_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_4_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN SF_CTRL_SF_IF_4_QPI_MODE_EN
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_POS (31U)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN (1U)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS))
+
+/* 0x94 : sf_if_iahb_10 */
+#define SF_CTRL_SF_IF_IAHB_10_OFFSET (0x94)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0 SF_CTRL_SF_IF_4_CMD_BUF_0
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_POS (0U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_LEN (32U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS))
+
+/* 0x98 : sf_if_iahb_11 */
+#define SF_CTRL_SF_IF_IAHB_11_OFFSET (0x98)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1 SF_CTRL_SF_IF_4_CMD_BUF_1
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_POS (0U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_LEN (32U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS))
+
+/* 0x9C : sf_if_iahb_12 */
+#define SF_CTRL_SF_IF_IAHB_12_OFFSET (0x9C)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL SF_CTRL_SF2_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS (2U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN (1U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS))
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC SF_CTRL_SF2_CLK_SF_RX_INV_SRC
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS (3U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN (1U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_MSK (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS))
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL SF_CTRL_SF2_CLK_OUT_INV_SEL
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_POS (4U)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN (1U)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL SF_CTRL_SF3_CLK_OUT_INV_SEL
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_POS (5U)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN (1U)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_N SF_CTRL_SF2_IF_READ_DLY_N
+#define SF_CTRL_SF2_IF_READ_DLY_N_POS (8U)
+#define SF_CTRL_SF2_IF_READ_DLY_N_LEN (3U)
+#define SF_CTRL_SF2_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_EN SF_CTRL_SF2_IF_READ_DLY_EN
+#define SF_CTRL_SF2_IF_READ_DLY_EN_POS (11U)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_LEN (1U)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_SRC SF_CTRL_SF2_IF_READ_DLY_SRC
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_POS (12U)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_LEN (1U)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS))
+
+/* 0xA0 : sf_id0_offset */
+#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0xA0)
+#define SF_CTRL_SF_ID0_OFFSET SF_CTRL_SF_ID0_OFFSET
+#define SF_CTRL_SF_ID0_OFFSET_POS (0U)
+#define SF_CTRL_SF_ID0_OFFSET_LEN (28U)
+#define SF_CTRL_SF_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)
+#define SF_CTRL_SF_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS))
+
+/* 0xA4 : sf_id1_offset */
+#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0xA4)
+#define SF_CTRL_SF_ID1_OFFSET SF_CTRL_SF_ID1_OFFSET
+#define SF_CTRL_SF_ID1_OFFSET_POS (0U)
+#define SF_CTRL_SF_ID1_OFFSET_LEN (28U)
+#define SF_CTRL_SF_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)
+#define SF_CTRL_SF_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS))
+
+/* 0xA8 : sf_bk2_id0_offset */
+#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0xA8)
+#define SF_CTRL_SF_BK2_ID0_OFFSET SF_CTRL_SF_BK2_ID0_OFFSET
+#define SF_CTRL_SF_BK2_ID0_OFFSET_POS (0U)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_LEN (28U)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS))
+
+/* 0xAC : sf_bk2_id1_offset */
+#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0xAC)
+#define SF_CTRL_SF_BK2_ID1_OFFSET SF_CTRL_SF_BK2_ID1_OFFSET
+#define SF_CTRL_SF_BK2_ID1_OFFSET_POS (0U)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_LEN (28U)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS))
+
+/* 0xB0 : sf_dbg */
+#define SF_CTRL_SF_DBG_OFFSET (0xB0)
+#define SF_CTRL_SF_AUTOLOAD_ST SF_CTRL_SF_AUTOLOAD_ST
+#define SF_CTRL_SF_AUTOLOAD_ST_POS (0U)
+#define SF_CTRL_SF_AUTOLOAD_ST_LEN (5U)
+#define SF_CTRL_SF_AUTOLOAD_ST_MSK (((1U << SF_CTRL_SF_AUTOLOAD_ST_LEN) - 1) << SF_CTRL_SF_AUTOLOAD_ST_POS)
+#define SF_CTRL_SF_AUTOLOAD_ST_UMSK (~(((1U << SF_CTRL_SF_AUTOLOAD_ST_LEN) - 1) << SF_CTRL_SF_AUTOLOAD_ST_POS))
+#define SF_CTRL_SF_AUTOLOAD_ST_DONE SF_CTRL_SF_AUTOLOAD_ST_DONE
+#define SF_CTRL_SF_AUTOLOAD_ST_DONE_POS (5U)
+#define SF_CTRL_SF_AUTOLOAD_ST_DONE_LEN (1U)
+#define SF_CTRL_SF_AUTOLOAD_ST_DONE_MSK (((1U << SF_CTRL_SF_AUTOLOAD_ST_DONE_LEN) - 1) << SF_CTRL_SF_AUTOLOAD_ST_DONE_POS)
+#define SF_CTRL_SF_AUTOLOAD_ST_DONE_UMSK (~(((1U << SF_CTRL_SF_AUTOLOAD_ST_DONE_LEN) - 1) << SF_CTRL_SF_AUTOLOAD_ST_DONE_POS))
+
+/* 0xC0 : sf_if2_ctrl_0 */
+#define SF_CTRL_SF_IF2_CTRL_0_OFFSET (0xC0)
+#define SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL
+#define SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_POS (2U)
+#define SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_LEN (1U)
+#define SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL_POS))
+#define SF_CTRL_SF_IF2_READ_DLY_N SF_CTRL_SF_IF2_READ_DLY_N
+#define SF_CTRL_SF_IF2_READ_DLY_N_POS (8U)
+#define SF_CTRL_SF_IF2_READ_DLY_N_LEN (3U)
+#define SF_CTRL_SF_IF2_READ_DLY_N_MSK (((1U << SF_CTRL_SF_IF2_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF2_READ_DLY_N_POS)
+#define SF_CTRL_SF_IF2_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF_IF2_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF2_READ_DLY_N_POS))
+#define SF_CTRL_SF_IF2_READ_DLY_EN SF_CTRL_SF_IF2_READ_DLY_EN
+#define SF_CTRL_SF_IF2_READ_DLY_EN_POS (11U)
+#define SF_CTRL_SF_IF2_READ_DLY_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_READ_DLY_EN_MSK (((1U << SF_CTRL_SF_IF2_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF2_READ_DLY_EN_POS)
+#define SF_CTRL_SF_IF2_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF2_READ_DLY_EN_POS))
+#define SF_CTRL_SF_IF2_INT SF_CTRL_SF_IF2_INT
+#define SF_CTRL_SF_IF2_INT_POS (16U)
+#define SF_CTRL_SF_IF2_INT_LEN (1U)
+#define SF_CTRL_SF_IF2_INT_MSK (((1U << SF_CTRL_SF_IF2_INT_LEN) - 1) << SF_CTRL_SF_IF2_INT_POS)
+#define SF_CTRL_SF_IF2_INT_UMSK (~(((1U << SF_CTRL_SF_IF2_INT_LEN) - 1) << SF_CTRL_SF_IF2_INT_POS))
+#define SF_CTRL_SF_IF2_INT_CLR SF_CTRL_SF_IF2_INT_CLR
+#define SF_CTRL_SF_IF2_INT_CLR_POS (17U)
+#define SF_CTRL_SF_IF2_INT_CLR_LEN (1U)
+#define SF_CTRL_SF_IF2_INT_CLR_MSK (((1U << SF_CTRL_SF_IF2_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF2_INT_CLR_POS)
+#define SF_CTRL_SF_IF2_INT_CLR_UMSK (~(((1U << SF_CTRL_SF_IF2_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF2_INT_CLR_POS))
+#define SF_CTRL_SF_IF2_INT_SET SF_CTRL_SF_IF2_INT_SET
+#define SF_CTRL_SF_IF2_INT_SET_POS (18U)
+#define SF_CTRL_SF_IF2_INT_SET_LEN (1U)
+#define SF_CTRL_SF_IF2_INT_SET_MSK (((1U << SF_CTRL_SF_IF2_INT_SET_LEN) - 1) << SF_CTRL_SF_IF2_INT_SET_POS)
+#define SF_CTRL_SF_IF2_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF2_INT_SET_LEN) - 1) << SF_CTRL_SF_IF2_INT_SET_POS))
+#define SF_CTRL_SF_IF2_REPLACE_SF1 SF_CTRL_SF_IF2_REPLACE_SF1
+#define SF_CTRL_SF_IF2_REPLACE_SF1_POS (23U)
+#define SF_CTRL_SF_IF2_REPLACE_SF1_LEN (1U)
+#define SF_CTRL_SF_IF2_REPLACE_SF1_MSK (((1U << SF_CTRL_SF_IF2_REPLACE_SF1_LEN) - 1) << SF_CTRL_SF_IF2_REPLACE_SF1_POS)
+#define SF_CTRL_SF_IF2_REPLACE_SF1_UMSK (~(((1U << SF_CTRL_SF_IF2_REPLACE_SF1_LEN) - 1) << SF_CTRL_SF_IF2_REPLACE_SF1_POS))
+#define SF_CTRL_SF_IF2_REPLACE_SF2 SF_CTRL_SF_IF2_REPLACE_SF2
+#define SF_CTRL_SF_IF2_REPLACE_SF2_POS (24U)
+#define SF_CTRL_SF_IF2_REPLACE_SF2_LEN (1U)
+#define SF_CTRL_SF_IF2_REPLACE_SF2_MSK (((1U << SF_CTRL_SF_IF2_REPLACE_SF2_LEN) - 1) << SF_CTRL_SF_IF2_REPLACE_SF2_POS)
+#define SF_CTRL_SF_IF2_REPLACE_SF2_UMSK (~(((1U << SF_CTRL_SF_IF2_REPLACE_SF2_LEN) - 1) << SF_CTRL_SF_IF2_REPLACE_SF2_POS))
+#define SF_CTRL_SF_IF2_REPLACE_SF3 SF_CTRL_SF_IF2_REPLACE_SF3
+#define SF_CTRL_SF_IF2_REPLACE_SF3_POS (25U)
+#define SF_CTRL_SF_IF2_REPLACE_SF3_LEN (1U)
+#define SF_CTRL_SF_IF2_REPLACE_SF3_MSK (((1U << SF_CTRL_SF_IF2_REPLACE_SF3_LEN) - 1) << SF_CTRL_SF_IF2_REPLACE_SF3_POS)
+#define SF_CTRL_SF_IF2_REPLACE_SF3_UMSK (~(((1U << SF_CTRL_SF_IF2_REPLACE_SF3_LEN) - 1) << SF_CTRL_SF_IF2_REPLACE_SF3_POS))
+#define SF_CTRL_SF_IF2_PAD_SEL SF_CTRL_SF_IF2_PAD_SEL
+#define SF_CTRL_SF_IF2_PAD_SEL_POS (26U)
+#define SF_CTRL_SF_IF2_PAD_SEL_LEN (2U)
+#define SF_CTRL_SF_IF2_PAD_SEL_MSK (((1U << SF_CTRL_SF_IF2_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF2_PAD_SEL_POS)
+#define SF_CTRL_SF_IF2_PAD_SEL_UMSK (~(((1U << SF_CTRL_SF_IF2_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF2_PAD_SEL_POS))
+#define SF_CTRL_SF_IF2_BK_SWAP SF_CTRL_SF_IF2_BK_SWAP
+#define SF_CTRL_SF_IF2_BK_SWAP_POS (28U)
+#define SF_CTRL_SF_IF2_BK_SWAP_LEN (1U)
+#define SF_CTRL_SF_IF2_BK_SWAP_MSK (((1U << SF_CTRL_SF_IF2_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF2_BK_SWAP_POS)
+#define SF_CTRL_SF_IF2_BK_SWAP_UMSK (~(((1U << SF_CTRL_SF_IF2_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF2_BK_SWAP_POS))
+#define SF_CTRL_SF_IF2_BK2_MODE SF_CTRL_SF_IF2_BK2_MODE
+#define SF_CTRL_SF_IF2_BK2_MODE_POS (29U)
+#define SF_CTRL_SF_IF2_BK2_MODE_LEN (1U)
+#define SF_CTRL_SF_IF2_BK2_MODE_MSK (((1U << SF_CTRL_SF_IF2_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF2_BK2_MODE_POS)
+#define SF_CTRL_SF_IF2_BK2_MODE_UMSK (~(((1U << SF_CTRL_SF_IF2_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF2_BK2_MODE_POS))
+#define SF_CTRL_SF_IF2_BK2_EN SF_CTRL_SF_IF2_BK2_EN
+#define SF_CTRL_SF_IF2_BK2_EN_POS (30U)
+#define SF_CTRL_SF_IF2_BK2_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_BK2_EN_MSK (((1U << SF_CTRL_SF_IF2_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF2_BK2_EN_POS)
+#define SF_CTRL_SF_IF2_BK2_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF2_BK2_EN_POS))
+#define SF_CTRL_SF_IF2_BK_SEL SF_CTRL_SF_IF2_BK_SEL
+#define SF_CTRL_SF_IF2_BK_SEL_POS (31U)
+#define SF_CTRL_SF_IF2_BK_SEL_LEN (1U)
+#define SF_CTRL_SF_IF2_BK_SEL_MSK (((1U << SF_CTRL_SF_IF2_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF2_BK_SEL_POS)
+#define SF_CTRL_SF_IF2_BK_SEL_UMSK (~(((1U << SF_CTRL_SF_IF2_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF2_BK_SEL_POS))
+
+/* 0xC4 : sf_if2_ctrl_1 */
+#define SF_CTRL_SF_IF2_CTRL_1_OFFSET (0xC4)
+#define SF_CTRL_SF_IF2_SR_PAT_MASK SF_CTRL_SF_IF2_SR_PAT_MASK
+#define SF_CTRL_SF_IF2_SR_PAT_MASK_POS (0U)
+#define SF_CTRL_SF_IF2_SR_PAT_MASK_LEN (8U)
+#define SF_CTRL_SF_IF2_SR_PAT_MASK_MSK (((1U << SF_CTRL_SF_IF2_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF2_SR_PAT_MASK_POS)
+#define SF_CTRL_SF_IF2_SR_PAT_MASK_UMSK (~(((1U << SF_CTRL_SF_IF2_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF2_SR_PAT_MASK_POS))
+#define SF_CTRL_SF_IF2_SR_PAT SF_CTRL_SF_IF2_SR_PAT
+#define SF_CTRL_SF_IF2_SR_PAT_POS (8U)
+#define SF_CTRL_SF_IF2_SR_PAT_LEN (8U)
+#define SF_CTRL_SF_IF2_SR_PAT_MSK (((1U << SF_CTRL_SF_IF2_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF2_SR_PAT_POS)
+#define SF_CTRL_SF_IF2_SR_PAT_UMSK (~(((1U << SF_CTRL_SF_IF2_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF2_SR_PAT_POS))
+#define SF_CTRL_SF_IF2_SR_INT SF_CTRL_SF_IF2_SR_INT
+#define SF_CTRL_SF_IF2_SR_INT_POS (16U)
+#define SF_CTRL_SF_IF2_SR_INT_LEN (1U)
+#define SF_CTRL_SF_IF2_SR_INT_MSK (((1U << SF_CTRL_SF_IF2_SR_INT_LEN) - 1) << SF_CTRL_SF_IF2_SR_INT_POS)
+#define SF_CTRL_SF_IF2_SR_INT_UMSK (~(((1U << SF_CTRL_SF_IF2_SR_INT_LEN) - 1) << SF_CTRL_SF_IF2_SR_INT_POS))
+#define SF_CTRL_SF_IF2_SR_INT_EN SF_CTRL_SF_IF2_SR_INT_EN
+#define SF_CTRL_SF_IF2_SR_INT_EN_POS (17U)
+#define SF_CTRL_SF_IF2_SR_INT_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_SR_INT_EN_MSK (((1U << SF_CTRL_SF_IF2_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF2_SR_INT_EN_POS)
+#define SF_CTRL_SF_IF2_SR_INT_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF2_SR_INT_EN_POS))
+#define SF_CTRL_SF_IF2_SR_INT_SET SF_CTRL_SF_IF2_SR_INT_SET
+#define SF_CTRL_SF_IF2_SR_INT_SET_POS (18U)
+#define SF_CTRL_SF_IF2_SR_INT_SET_LEN (1U)
+#define SF_CTRL_SF_IF2_SR_INT_SET_MSK (((1U << SF_CTRL_SF_IF2_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF2_SR_INT_SET_POS)
+#define SF_CTRL_SF_IF2_SR_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF2_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF2_SR_INT_SET_POS))
+#define SF_CTRL_SF_IF2_ACK_LAT SF_CTRL_SF_IF2_ACK_LAT
+#define SF_CTRL_SF_IF2_ACK_LAT_POS (20U)
+#define SF_CTRL_SF_IF2_ACK_LAT_LEN (3U)
+#define SF_CTRL_SF_IF2_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF2_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF2_ACK_LAT_POS)
+#define SF_CTRL_SF_IF2_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF2_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF2_ACK_LAT_POS))
+#define SF_CTRL_SF_IF2_REG_HOLD SF_CTRL_SF_IF2_REG_HOLD
+#define SF_CTRL_SF_IF2_REG_HOLD_POS (24U)
+#define SF_CTRL_SF_IF2_REG_HOLD_LEN (1U)
+#define SF_CTRL_SF_IF2_REG_HOLD_MSK (((1U << SF_CTRL_SF_IF2_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF2_REG_HOLD_POS)
+#define SF_CTRL_SF_IF2_REG_HOLD_UMSK (~(((1U << SF_CTRL_SF_IF2_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF2_REG_HOLD_POS))
+#define SF_CTRL_SF_IF2_REG_WP SF_CTRL_SF_IF2_REG_WP
+#define SF_CTRL_SF_IF2_REG_WP_POS (25U)
+#define SF_CTRL_SF_IF2_REG_WP_LEN (1U)
+#define SF_CTRL_SF_IF2_REG_WP_MSK (((1U << SF_CTRL_SF_IF2_REG_WP_LEN) - 1) << SF_CTRL_SF_IF2_REG_WP_POS)
+#define SF_CTRL_SF_IF2_REG_WP_UMSK (~(((1U << SF_CTRL_SF_IF2_REG_WP_LEN) - 1) << SF_CTRL_SF_IF2_REG_WP_POS))
+#define SF_CTRL_SF_IF2_FN_SEL SF_CTRL_SF_IF2_FN_SEL
+#define SF_CTRL_SF_IF2_FN_SEL_POS (28U)
+#define SF_CTRL_SF_IF2_FN_SEL_LEN (1U)
+#define SF_CTRL_SF_IF2_FN_SEL_MSK (((1U << SF_CTRL_SF_IF2_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF2_FN_SEL_POS)
+#define SF_CTRL_SF_IF2_FN_SEL_UMSK (~(((1U << SF_CTRL_SF_IF2_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF2_FN_SEL_POS))
+#define SF_CTRL_SF_IF2_EN SF_CTRL_SF_IF2_EN
+#define SF_CTRL_SF_IF2_EN_POS (29U)
+#define SF_CTRL_SF_IF2_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_EN_MSK (((1U << SF_CTRL_SF_IF2_EN_LEN) - 1) << SF_CTRL_SF_IF2_EN_POS)
+#define SF_CTRL_SF_IF2_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_EN_LEN) - 1) << SF_CTRL_SF_IF2_EN_POS))
+
+/* 0xC8 : sf_if2_sahb_0 */
+#define SF_CTRL_SF_IF2_SAHB_0_OFFSET (0xC8)
+#define SF_CTRL_SF_IF2_BUSY SF_CTRL_SF_IF2_BUSY
+#define SF_CTRL_SF_IF2_BUSY_POS (0U)
+#define SF_CTRL_SF_IF2_BUSY_LEN (1U)
+#define SF_CTRL_SF_IF2_BUSY_MSK (((1U << SF_CTRL_SF_IF2_BUSY_LEN) - 1) << SF_CTRL_SF_IF2_BUSY_POS)
+#define SF_CTRL_SF_IF2_BUSY_UMSK (~(((1U << SF_CTRL_SF_IF2_BUSY_LEN) - 1) << SF_CTRL_SF_IF2_BUSY_POS))
+#define SF_CTRL_SF_IF2_0_TRIG SF_CTRL_SF_IF2_0_TRIG
+#define SF_CTRL_SF_IF2_0_TRIG_POS (1U)
+#define SF_CTRL_SF_IF2_0_TRIG_LEN (1U)
+#define SF_CTRL_SF_IF2_0_TRIG_MSK (((1U << SF_CTRL_SF_IF2_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF2_0_TRIG_POS)
+#define SF_CTRL_SF_IF2_0_TRIG_UMSK (~(((1U << SF_CTRL_SF_IF2_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF2_0_TRIG_POS))
+#define SF_CTRL_SF_IF2_0_DAT_BYTE SF_CTRL_SF_IF2_0_DAT_BYTE
+#define SF_CTRL_SF_IF2_0_DAT_BYTE_POS (2U)
+#define SF_CTRL_SF_IF2_0_DAT_BYTE_LEN (10U)
+#define SF_CTRL_SF_IF2_0_DAT_BYTE_MSK (((1U << SF_CTRL_SF_IF2_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_DAT_BYTE_POS)
+#define SF_CTRL_SF_IF2_0_DAT_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF2_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_DAT_BYTE_POS))
+#define SF_CTRL_SF_IF2_0_DMY_BYTE SF_CTRL_SF_IF2_0_DMY_BYTE
+#define SF_CTRL_SF_IF2_0_DMY_BYTE_POS (12U)
+#define SF_CTRL_SF_IF2_0_DMY_BYTE_LEN (5U)
+#define SF_CTRL_SF_IF2_0_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF2_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF2_0_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF2_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF2_0_ADR_BYTE SF_CTRL_SF_IF2_0_ADR_BYTE
+#define SF_CTRL_SF_IF2_0_ADR_BYTE_POS (17U)
+#define SF_CTRL_SF_IF2_0_ADR_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF2_0_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF2_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF2_0_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF2_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF2_0_CMD_BYTE SF_CTRL_SF_IF2_0_CMD_BYTE
+#define SF_CTRL_SF_IF2_0_CMD_BYTE_POS (20U)
+#define SF_CTRL_SF_IF2_0_CMD_BYTE_LEN (3U)
+#define SF_CTRL_SF_IF2_0_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF2_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF2_0_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF2_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF2_0_DAT_RW SF_CTRL_SF_IF2_0_DAT_RW
+#define SF_CTRL_SF_IF2_0_DAT_RW_POS (23U)
+#define SF_CTRL_SF_IF2_0_DAT_RW_LEN (1U)
+#define SF_CTRL_SF_IF2_0_DAT_RW_MSK (((1U << SF_CTRL_SF_IF2_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF2_0_DAT_RW_POS)
+#define SF_CTRL_SF_IF2_0_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF2_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF2_0_DAT_RW_POS))
+#define SF_CTRL_SF_IF2_0_DAT_EN SF_CTRL_SF_IF2_0_DAT_EN
+#define SF_CTRL_SF_IF2_0_DAT_EN_POS (24U)
+#define SF_CTRL_SF_IF2_0_DAT_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_0_DAT_EN_MSK (((1U << SF_CTRL_SF_IF2_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_DAT_EN_POS)
+#define SF_CTRL_SF_IF2_0_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_DAT_EN_POS))
+#define SF_CTRL_SF_IF2_0_DMY_EN SF_CTRL_SF_IF2_0_DMY_EN
+#define SF_CTRL_SF_IF2_0_DMY_EN_POS (25U)
+#define SF_CTRL_SF_IF2_0_DMY_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_0_DMY_EN_MSK (((1U << SF_CTRL_SF_IF2_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_DMY_EN_POS)
+#define SF_CTRL_SF_IF2_0_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_DMY_EN_POS))
+#define SF_CTRL_SF_IF2_0_ADR_EN SF_CTRL_SF_IF2_0_ADR_EN
+#define SF_CTRL_SF_IF2_0_ADR_EN_POS (26U)
+#define SF_CTRL_SF_IF2_0_ADR_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_0_ADR_EN_MSK (((1U << SF_CTRL_SF_IF2_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_ADR_EN_POS)
+#define SF_CTRL_SF_IF2_0_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_ADR_EN_POS))
+#define SF_CTRL_SF_IF2_0_CMD_EN SF_CTRL_SF_IF2_0_CMD_EN
+#define SF_CTRL_SF_IF2_0_CMD_EN_POS (27U)
+#define SF_CTRL_SF_IF2_0_CMD_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_0_CMD_EN_MSK (((1U << SF_CTRL_SF_IF2_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_EN_POS)
+#define SF_CTRL_SF_IF2_0_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_EN_POS))
+#define SF_CTRL_SF_IF2_0_SPI_MODE SF_CTRL_SF_IF2_0_SPI_MODE
+#define SF_CTRL_SF_IF2_0_SPI_MODE_POS (28U)
+#define SF_CTRL_SF_IF2_0_SPI_MODE_LEN (3U)
+#define SF_CTRL_SF_IF2_0_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF2_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF2_0_SPI_MODE_POS)
+#define SF_CTRL_SF_IF2_0_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF2_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF2_0_SPI_MODE_POS))
+#define SF_CTRL_SF_IF2_0_QPI_MODE_EN SF_CTRL_SF_IF2_0_QPI_MODE_EN
+#define SF_CTRL_SF_IF2_0_QPI_MODE_EN_POS (31U)
+#define SF_CTRL_SF_IF2_0_QPI_MODE_EN_LEN (1U)
+#define SF_CTRL_SF_IF2_0_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF2_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF2_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF2_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF2_0_QPI_MODE_EN_POS))
+
+/* 0xCC : sf_if2_sahb_1 */
+#define SF_CTRL_SF_IF2_SAHB_1_OFFSET (0xCC)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_0 SF_CTRL_SF_IF2_0_CMD_BUF_0
+#define SF_CTRL_SF_IF2_0_CMD_BUF_0_POS (0U)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_0_LEN (32U)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF2_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF2_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_BUF_0_POS))
+
+/* 0xD0 : sf_if2_sahb_2 */
+#define SF_CTRL_SF_IF2_SAHB_2_OFFSET (0xD0)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_1 SF_CTRL_SF_IF2_0_CMD_BUF_1
+#define SF_CTRL_SF_IF2_0_CMD_BUF_1_POS (0U)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_1_LEN (32U)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF2_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF2_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF2_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF2_0_CMD_BUF_1_POS))
+
+/* 0x100 : sf_ctrl_prot_en_rd */
+#define SF_CTRL_PROT_EN_RD_OFFSET (0x100)
+#define SF_CTRL_ID0_EN_RD SF_CTRL_ID0_EN_RD
+#define SF_CTRL_ID0_EN_RD_POS (1U)
+#define SF_CTRL_ID0_EN_RD_LEN (1U)
+#define SF_CTRL_ID0_EN_RD_MSK (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)
+#define SF_CTRL_ID0_EN_RD_UMSK (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS))
+#define SF_CTRL_ID1_EN_RD SF_CTRL_ID1_EN_RD
+#define SF_CTRL_ID1_EN_RD_POS (2U)
+#define SF_CTRL_ID1_EN_RD_LEN (1U)
+#define SF_CTRL_ID1_EN_RD_MSK (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)
+#define SF_CTRL_ID1_EN_RD_UMSK (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS))
+#define SF_CTRL_SF_SEC_TZSID_LOCK SF_CTRL_SF_SEC_TZSID_LOCK
+#define SF_CTRL_SF_SEC_TZSID_LOCK_POS (28U)
+#define SF_CTRL_SF_SEC_TZSID_LOCK_LEN (1U)
+#define SF_CTRL_SF_SEC_TZSID_LOCK_MSK (((1U << SF_CTRL_SF_SEC_TZSID_LOCK_LEN) - 1) << SF_CTRL_SF_SEC_TZSID_LOCK_POS)
+#define SF_CTRL_SF_SEC_TZSID_LOCK_UMSK (~(((1U << SF_CTRL_SF_SEC_TZSID_LOCK_LEN) - 1) << SF_CTRL_SF_SEC_TZSID_LOCK_POS))
+#define SF_CTRL_SF_IF2_0_TRIG_WR_LOCK SF_CTRL_SF_IF2_0_TRIG_WR_LOCK
+#define SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_POS (29U)
+#define SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_LEN (1U)
+#define SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_MSK (((1U << SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_POS)
+#define SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF2_0_TRIG_WR_LOCK_POS))
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK SF_CTRL_SF_IF_0_TRIG_WR_LOCK
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS (30U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN (1U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS))
+#define SF_CTRL_SF_DBG_DIS SF_CTRL_SF_DBG_DIS
+#define SF_CTRL_SF_DBG_DIS_POS (31U)
+#define SF_CTRL_SF_DBG_DIS_LEN (1U)
+#define SF_CTRL_SF_DBG_DIS_MSK (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)
+#define SF_CTRL_SF_DBG_DIS_UMSK (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS))
+
+/* 0x104 : sf_ctrl_prot_en */
+#define SF_CTRL_PROT_EN_OFFSET (0x104)
+#define SF_CTRL_ID0_EN SF_CTRL_ID0_EN
+#define SF_CTRL_ID0_EN_POS (1U)
+#define SF_CTRL_ID0_EN_LEN (1U)
+#define SF_CTRL_ID0_EN_MSK (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)
+#define SF_CTRL_ID0_EN_UMSK (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS))
+#define SF_CTRL_ID1_EN SF_CTRL_ID1_EN
+#define SF_CTRL_ID1_EN_POS (2U)
+#define SF_CTRL_ID1_EN_LEN (1U)
+#define SF_CTRL_ID1_EN_MSK (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)
+#define SF_CTRL_ID1_EN_UMSK (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS))
+
+/* 0x200 : sf_aes_key_r0_0 */
+#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)
+#define SF_CTRL_SF_AES_KEY_R0_0 SF_CTRL_SF_AES_KEY_R0_0
+#define SF_CTRL_SF_AES_KEY_R0_0_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_0_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)
+#define SF_CTRL_SF_AES_KEY_R0_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS))
+
+/* 0x204 : sf_aes_key_r0_1 */
+#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)
+#define SF_CTRL_SF_AES_KEY_R0_1 SF_CTRL_SF_AES_KEY_R0_1
+#define SF_CTRL_SF_AES_KEY_R0_1_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_1_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)
+#define SF_CTRL_SF_AES_KEY_R0_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS))
+
+/* 0x208 : sf_aes_key_r0_2 */
+#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)
+#define SF_CTRL_SF_AES_KEY_R0_2 SF_CTRL_SF_AES_KEY_R0_2
+#define SF_CTRL_SF_AES_KEY_R0_2_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_2_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)
+#define SF_CTRL_SF_AES_KEY_R0_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS))
+
+/* 0x20C : sf_aes_key_r0_3 */
+#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)
+#define SF_CTRL_SF_AES_KEY_R0_3 SF_CTRL_SF_AES_KEY_R0_3
+#define SF_CTRL_SF_AES_KEY_R0_3_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_3_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)
+#define SF_CTRL_SF_AES_KEY_R0_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS))
+
+/* 0x210 : sf_aes_key_r0_4 */
+#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)
+#define SF_CTRL_SF_AES_KEY_R0_4 SF_CTRL_SF_AES_KEY_R0_4
+#define SF_CTRL_SF_AES_KEY_R0_4_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_4_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)
+#define SF_CTRL_SF_AES_KEY_R0_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS))
+
+/* 0x214 : sf_aes_key_r0_5 */
+#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)
+#define SF_CTRL_SF_AES_KEY_R0_5 SF_CTRL_SF_AES_KEY_R0_5
+#define SF_CTRL_SF_AES_KEY_R0_5_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_5_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)
+#define SF_CTRL_SF_AES_KEY_R0_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS))
+
+/* 0x218 : sf_aes_key_r0_6 */
+#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)
+#define SF_CTRL_SF_AES_KEY_R0_6 SF_CTRL_SF_AES_KEY_R0_6
+#define SF_CTRL_SF_AES_KEY_R0_6_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_6_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)
+#define SF_CTRL_SF_AES_KEY_R0_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS))
+
+/* 0x21C : sf_aes_key_r0_7 */
+#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)
+#define SF_CTRL_SF_AES_KEY_R0_7 SF_CTRL_SF_AES_KEY_R0_7
+#define SF_CTRL_SF_AES_KEY_R0_7_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R0_7_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R0_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)
+#define SF_CTRL_SF_AES_KEY_R0_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS))
+
+/* 0x220 : sf_aes_iv_r0_w0 */
+#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)
+#define SF_CTRL_SF_AES_IV_R0_W0 SF_CTRL_SF_AES_IV_R0_W0
+#define SF_CTRL_SF_AES_IV_R0_W0_POS (0U)
+#define SF_CTRL_SF_AES_IV_R0_W0_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R0_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)
+#define SF_CTRL_SF_AES_IV_R0_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS))
+
+/* 0x224 : sf_aes_iv_r0_w1 */
+#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)
+#define SF_CTRL_SF_AES_IV_R0_W1 SF_CTRL_SF_AES_IV_R0_W1
+#define SF_CTRL_SF_AES_IV_R0_W1_POS (0U)
+#define SF_CTRL_SF_AES_IV_R0_W1_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R0_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)
+#define SF_CTRL_SF_AES_IV_R0_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS))
+
+/* 0x228 : sf_aes_iv_r0_w2 */
+#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)
+#define SF_CTRL_SF_AES_IV_R0_W2 SF_CTRL_SF_AES_IV_R0_W2
+#define SF_CTRL_SF_AES_IV_R0_W2_POS (0U)
+#define SF_CTRL_SF_AES_IV_R0_W2_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R0_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)
+#define SF_CTRL_SF_AES_IV_R0_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS))
+
+/* 0x22C : sf_aes_iv_r0_w3 */
+#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)
+#define SF_CTRL_SF_AES_IV_R0_W3 SF_CTRL_SF_AES_IV_R0_W3
+#define SF_CTRL_SF_AES_IV_R0_W3_POS (0U)
+#define SF_CTRL_SF_AES_IV_R0_W3_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R0_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)
+#define SF_CTRL_SF_AES_IV_R0_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS))
+
+/* 0x230 : sf_aes_r0_start */
+#define SF_CTRL_SF_AES_R0_START_OFFSET (0x230)
+#define SF_CTRL_SF_AES_REGION_R0_START SF_CTRL_SF_AES_REGION_R0_START
+#define SF_CTRL_SF_AES_REGION_R0_START_POS (0U)
+#define SF_CTRL_SF_AES_REGION_R0_START_LEN (19U)
+#define SF_CTRL_SF_AES_REGION_R0_START_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)
+#define SF_CTRL_SF_AES_REGION_R0_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS))
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS (29U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN (1U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_EN SF_CTRL_SF_AES_REGION_R0_EN
+#define SF_CTRL_SF_AES_REGION_R0_EN_POS (30U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_LEN (1U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_LOCK SF_CTRL_SF_AES_REGION_R0_LOCK
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS (31U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN (1U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS))
+
+/* 0x234 : sf_aes_r0_end */
+#define SF_CTRL_SF_AES_R0_END_OFFSET (0x234)
+#define SF_CTRL_SF_AES_REGION_R0_END SF_CTRL_SF_AES_REGION_R0_END
+#define SF_CTRL_SF_AES_REGION_R0_END_POS (0U)
+#define SF_CTRL_SF_AES_REGION_R0_END_LEN (19U)
+#define SF_CTRL_SF_AES_REGION_R0_END_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)
+#define SF_CTRL_SF_AES_REGION_R0_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS))
+
+/* 0x280 : sf_aes_key_r1_0 */
+#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x280)
+#define SF_CTRL_SF_AES_KEY_R1_0 SF_CTRL_SF_AES_KEY_R1_0
+#define SF_CTRL_SF_AES_KEY_R1_0_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_0_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)
+#define SF_CTRL_SF_AES_KEY_R1_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS))
+
+/* 0x284 : sf_aes_key_r1_1 */
+#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x284)
+#define SF_CTRL_SF_AES_KEY_R1_1 SF_CTRL_SF_AES_KEY_R1_1
+#define SF_CTRL_SF_AES_KEY_R1_1_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_1_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)
+#define SF_CTRL_SF_AES_KEY_R1_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS))
+
+/* 0x288 : sf_aes_key_r1_2 */
+#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x288)
+#define SF_CTRL_SF_AES_KEY_R1_2 SF_CTRL_SF_AES_KEY_R1_2
+#define SF_CTRL_SF_AES_KEY_R1_2_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_2_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)
+#define SF_CTRL_SF_AES_KEY_R1_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS))
+
+/* 0x28C : sf_aes_key_r1_3 */
+#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x28C)
+#define SF_CTRL_SF_AES_KEY_R1_3 SF_CTRL_SF_AES_KEY_R1_3
+#define SF_CTRL_SF_AES_KEY_R1_3_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_3_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)
+#define SF_CTRL_SF_AES_KEY_R1_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS))
+
+/* 0x290 : sf_aes_key_r1_4 */
+#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x290)
+#define SF_CTRL_SF_AES_KEY_R1_4 SF_CTRL_SF_AES_KEY_R1_4
+#define SF_CTRL_SF_AES_KEY_R1_4_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_4_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)
+#define SF_CTRL_SF_AES_KEY_R1_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS))
+
+/* 0x294 : sf_aes_key_r1_5 */
+#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x294)
+#define SF_CTRL_SF_AES_KEY_R1_5 SF_CTRL_SF_AES_KEY_R1_5
+#define SF_CTRL_SF_AES_KEY_R1_5_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_5_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)
+#define SF_CTRL_SF_AES_KEY_R1_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS))
+
+/* 0x298 : sf_aes_key_r1_6 */
+#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x298)
+#define SF_CTRL_SF_AES_KEY_R1_6 SF_CTRL_SF_AES_KEY_R1_6
+#define SF_CTRL_SF_AES_KEY_R1_6_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_6_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)
+#define SF_CTRL_SF_AES_KEY_R1_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS))
+
+/* 0x29C : sf_aes_key_r1_7 */
+#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x29C)
+#define SF_CTRL_SF_AES_KEY_R1_7 SF_CTRL_SF_AES_KEY_R1_7
+#define SF_CTRL_SF_AES_KEY_R1_7_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R1_7_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R1_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)
+#define SF_CTRL_SF_AES_KEY_R1_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS))
+
+/* 0x2A0 : sf_aes_iv_r1_w0 */
+#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x2A0)
+#define SF_CTRL_SF_AES_IV_R1_W0 SF_CTRL_SF_AES_IV_R1_W0
+#define SF_CTRL_SF_AES_IV_R1_W0_POS (0U)
+#define SF_CTRL_SF_AES_IV_R1_W0_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R1_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)
+#define SF_CTRL_SF_AES_IV_R1_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS))
+
+/* 0x2A4 : sf_aes_iv_r1_w1 */
+#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x2A4)
+#define SF_CTRL_SF_AES_IV_R1_W1 SF_CTRL_SF_AES_IV_R1_W1
+#define SF_CTRL_SF_AES_IV_R1_W1_POS (0U)
+#define SF_CTRL_SF_AES_IV_R1_W1_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R1_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)
+#define SF_CTRL_SF_AES_IV_R1_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS))
+
+/* 0x2A8 : sf_aes_iv_r1_w2 */
+#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x2A8)
+#define SF_CTRL_SF_AES_IV_R1_W2 SF_CTRL_SF_AES_IV_R1_W2
+#define SF_CTRL_SF_AES_IV_R1_W2_POS (0U)
+#define SF_CTRL_SF_AES_IV_R1_W2_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R1_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)
+#define SF_CTRL_SF_AES_IV_R1_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS))
+
+/* 0x2AC : sf_aes_iv_r1_w3 */
+#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x2AC)
+#define SF_CTRL_SF_AES_IV_R1_W3 SF_CTRL_SF_AES_IV_R1_W3
+#define SF_CTRL_SF_AES_IV_R1_W3_POS (0U)
+#define SF_CTRL_SF_AES_IV_R1_W3_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R1_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)
+#define SF_CTRL_SF_AES_IV_R1_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS))
+
+/* 0x2B0 : sf_aes_r1_start */
+#define SF_CTRL_SF_AES_R1_START_OFFSET (0x2B0)
+#define SF_CTRL_SF_AES_R1_START SF_CTRL_SF_AES_R1_START
+#define SF_CTRL_SF_AES_R1_START_POS (0U)
+#define SF_CTRL_SF_AES_R1_START_LEN (19U)
+#define SF_CTRL_SF_AES_R1_START_MSK (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)
+#define SF_CTRL_SF_AES_R1_START_UMSK (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS))
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN SF_CTRL_SF_AES_R1_HW_KEY_EN
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS (29U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN (1U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R1_EN SF_CTRL_SF_AES_R1_EN
+#define SF_CTRL_SF_AES_R1_EN_POS (30U)
+#define SF_CTRL_SF_AES_R1_EN_LEN (1U)
+#define SF_CTRL_SF_AES_R1_EN_MSK (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)
+#define SF_CTRL_SF_AES_R1_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS))
+#define SF_CTRL_SF_AES_R1_LOCK SF_CTRL_SF_AES_R1_LOCK
+#define SF_CTRL_SF_AES_R1_LOCK_POS (31U)
+#define SF_CTRL_SF_AES_R1_LOCK_LEN (1U)
+#define SF_CTRL_SF_AES_R1_LOCK_MSK (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)
+#define SF_CTRL_SF_AES_R1_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS))
+
+/* 0x2B4 : sf_aes_r1_end */
+#define SF_CTRL_SF_AES_R1_END_OFFSET (0x2B4)
+#define SF_CTRL_SF_AES_R1_END SF_CTRL_SF_AES_R1_END
+#define SF_CTRL_SF_AES_R1_END_POS (0U)
+#define SF_CTRL_SF_AES_R1_END_LEN (19U)
+#define SF_CTRL_SF_AES_R1_END_MSK (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)
+#define SF_CTRL_SF_AES_R1_END_UMSK (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS))
+
+/* 0x300 : sf_aes_key_r2_0 */
+#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x300)
+#define SF_CTRL_SF_AES_KEY_R2_0 SF_CTRL_SF_AES_KEY_R2_0
+#define SF_CTRL_SF_AES_KEY_R2_0_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_0_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)
+#define SF_CTRL_SF_AES_KEY_R2_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS))
+
+/* 0x304 : sf_aes_key_r2_1 */
+#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x304)
+#define SF_CTRL_SF_AES_KEY_R2_1 SF_CTRL_SF_AES_KEY_R2_1
+#define SF_CTRL_SF_AES_KEY_R2_1_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_1_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)
+#define SF_CTRL_SF_AES_KEY_R2_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS))
+
+/* 0x308 : sf_aes_key_r2_2 */
+#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x308)
+#define SF_CTRL_SF_AES_KEY_R2_2 SF_CTRL_SF_AES_KEY_R2_2
+#define SF_CTRL_SF_AES_KEY_R2_2_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_2_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)
+#define SF_CTRL_SF_AES_KEY_R2_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS))
+
+/* 0x30C : sf_aes_key_r2_3 */
+#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x30C)
+#define SF_CTRL_SF_AES_KEY_R2_3 SF_CTRL_SF_AES_KEY_R2_3
+#define SF_CTRL_SF_AES_KEY_R2_3_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_3_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)
+#define SF_CTRL_SF_AES_KEY_R2_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS))
+
+/* 0x310 : sf_aes_key_r2_4 */
+#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x310)
+#define SF_CTRL_SF_AES_KEY_R2_4 SF_CTRL_SF_AES_KEY_R2_4
+#define SF_CTRL_SF_AES_KEY_R2_4_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_4_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)
+#define SF_CTRL_SF_AES_KEY_R2_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS))
+
+/* 0x314 : sf_aes_key_r2_5 */
+#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x314)
+#define SF_CTRL_SF_AES_KEY_R2_5 SF_CTRL_SF_AES_KEY_R2_5
+#define SF_CTRL_SF_AES_KEY_R2_5_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_5_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)
+#define SF_CTRL_SF_AES_KEY_R2_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS))
+
+/* 0x318 : sf_aes_key_r2_6 */
+#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x318)
+#define SF_CTRL_SF_AES_KEY_R2_6 SF_CTRL_SF_AES_KEY_R2_6
+#define SF_CTRL_SF_AES_KEY_R2_6_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_6_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)
+#define SF_CTRL_SF_AES_KEY_R2_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS))
+
+/* 0x31C : sf_aes_key_r2_7 */
+#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x31C)
+#define SF_CTRL_SF_AES_KEY_R2_7 SF_CTRL_SF_AES_KEY_R2_7
+#define SF_CTRL_SF_AES_KEY_R2_7_POS (0U)
+#define SF_CTRL_SF_AES_KEY_R2_7_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_R2_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)
+#define SF_CTRL_SF_AES_KEY_R2_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS))
+
+/* 0x320 : sf_aes_iv_r2_w0 */
+#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x320)
+#define SF_CTRL_SF_AES_IV_R2_W0 SF_CTRL_SF_AES_IV_R2_W0
+#define SF_CTRL_SF_AES_IV_R2_W0_POS (0U)
+#define SF_CTRL_SF_AES_IV_R2_W0_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R2_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)
+#define SF_CTRL_SF_AES_IV_R2_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS))
+
+/* 0x324 : sf_aes_iv_r2_w1 */
+#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x324)
+#define SF_CTRL_SF_AES_IV_R2_W1 SF_CTRL_SF_AES_IV_R2_W1
+#define SF_CTRL_SF_AES_IV_R2_W1_POS (0U)
+#define SF_CTRL_SF_AES_IV_R2_W1_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R2_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)
+#define SF_CTRL_SF_AES_IV_R2_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS))
+
+/* 0x328 : sf_aes_iv_r2_w2 */
+#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x328)
+#define SF_CTRL_SF_AES_IV_R2_W2 SF_CTRL_SF_AES_IV_R2_W2
+#define SF_CTRL_SF_AES_IV_R2_W2_POS (0U)
+#define SF_CTRL_SF_AES_IV_R2_W2_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R2_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)
+#define SF_CTRL_SF_AES_IV_R2_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS))
+
+/* 0x32C : sf_aes_iv_r2_w3 */
+#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x32C)
+#define SF_CTRL_SF_AES_IV_R2_W3 SF_CTRL_SF_AES_IV_R2_W3
+#define SF_CTRL_SF_AES_IV_R2_W3_POS (0U)
+#define SF_CTRL_SF_AES_IV_R2_W3_LEN (32U)
+#define SF_CTRL_SF_AES_IV_R2_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)
+#define SF_CTRL_SF_AES_IV_R2_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS))
+
+/* 0x330 : sf_aes_r2_start */
+#define SF_CTRL_SF_AES_R2_START_OFFSET (0x330)
+#define SF_CTRL_SF_AES_R2_START SF_CTRL_SF_AES_R2_START
+#define SF_CTRL_SF_AES_R2_START_POS (0U)
+#define SF_CTRL_SF_AES_R2_START_LEN (19U)
+#define SF_CTRL_SF_AES_R2_START_MSK (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)
+#define SF_CTRL_SF_AES_R2_START_UMSK (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS))
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN SF_CTRL_SF_AES_R2_HW_KEY_EN
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS (29U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN (1U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R2_EN SF_CTRL_SF_AES_R2_EN
+#define SF_CTRL_SF_AES_R2_EN_POS (30U)
+#define SF_CTRL_SF_AES_R2_EN_LEN (1U)
+#define SF_CTRL_SF_AES_R2_EN_MSK (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)
+#define SF_CTRL_SF_AES_R2_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS))
+#define SF_CTRL_SF_AES_R2_LOCK SF_CTRL_SF_AES_R2_LOCK
+#define SF_CTRL_SF_AES_R2_LOCK_POS (31U)
+#define SF_CTRL_SF_AES_R2_LOCK_LEN (1U)
+#define SF_CTRL_SF_AES_R2_LOCK_MSK (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)
+#define SF_CTRL_SF_AES_R2_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS))
+
+/* 0x334 : sf_aes_r2_end */
+#define SF_CTRL_SF_AES_R2_END_OFFSET (0x334)
+#define SF_CTRL_SF_AES_R2_END SF_CTRL_SF_AES_R2_END
+#define SF_CTRL_SF_AES_R2_END_POS (0U)
+#define SF_CTRL_SF_AES_R2_END_LEN (19U)
+#define SF_CTRL_SF_AES_R2_END_MSK (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)
+#define SF_CTRL_SF_AES_R2_END_UMSK (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS))
+
+struct sf_ctrl_reg {
+ /* 0x0 : sf_ctrl_0 */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t sf_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x1 */
+ uint32_t sf_clk_out_gate_en : 1; /* [ 3], r/w, 0x1 */
+ uint32_t sf_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t sf_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */
+ uint32_t sf_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t sf_if_int : 1; /* [ 16], r, 0x0 */
+ uint32_t sf_if_int_clr : 1; /* [ 17], r/w, 0x1 */
+ uint32_t sf_if_int_set : 1; /* [ 18], r/w, 0x0 */
+ uint32_t sf_if_32b_adr_en : 1; /* [ 19], r/w, 0x0 */
+ uint32_t sf_aes_dout_endian : 1; /* [ 20], r/w, 0x1 */
+ uint32_t sf_aes_din_endian : 1; /* [ 21], r/w, 0x1 */
+ uint32_t sf_aes_key_endian : 1; /* [ 22], r/w, 0x1 */
+ uint32_t sf_aes_iv_endian : 1; /* [ 23], r/w, 0x1 */
+ uint32_t sf_id : 8; /* [31:24], r/w, 0x1a */
+ } BF;
+ uint32_t WORD;
+ } sf_ctrl_0;
+
+ /* 0x4 : sf_ctrl_1 */
+ union {
+ struct {
+ uint32_t sf_if_sr_pat_mask : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t sf_if_sr_pat : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t sf_if_sr_int : 1; /* [ 16], r, 0x0 */
+ uint32_t sf_if_sr_int_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t sf_if_sr_int_set : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t sf_if_0_ack_lat : 3; /* [22:20], r/w, 0x6 */
+ uint32_t sf_ahb2sif_diswrap : 1; /* [ 23], r/w, 0x0 */
+ uint32_t sf_if_reg_hold : 1; /* [ 24], r/w, 0x1 */
+ uint32_t sf_if_reg_wp : 1; /* [ 25], r/w, 0x1 */
+ uint32_t sf_ahb2sif_stopped : 1; /* [ 26], r, 0x0 */
+ uint32_t sf_ahb2sif_stop : 1; /* [ 27], r/w, 0x0 */
+ uint32_t sf_if_fn_sel : 1; /* [ 28], r/w, 0x1 */
+ uint32_t sf_if_en : 1; /* [ 29], r/w, 0x1 */
+ uint32_t sf_ahb2sif_en : 1; /* [ 30], r/w, 0x1 */
+ uint32_t sf_ahb2sram_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } sf_ctrl_1;
+
+ /* 0x8 : sf_if_sahb_0 */
+ union {
+ struct {
+ uint32_t sf_if_busy : 1; /* [ 0], r, 0x0 */
+ uint32_t sf_if_0_trig : 1; /* [ 1], r/w, 0x0 */
+ uint32_t sf_if_0_dat_byte : 10; /* [11: 2], r/w, 0xff */
+ uint32_t sf_if_0_dmy_byte : 5; /* [16:12], r/w, 0x0 */
+ uint32_t sf_if_0_adr_byte : 3; /* [19:17], r/w, 0x2 */
+ uint32_t sf_if_0_cmd_byte : 3; /* [22:20], r/w, 0x0 */
+ uint32_t sf_if_0_dat_rw : 1; /* [ 23], r/w, 0x0 */
+ uint32_t sf_if_0_dat_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t sf_if_0_dmy_en : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sf_if_0_adr_en : 1; /* [ 26], r/w, 0x1 */
+ uint32_t sf_if_0_cmd_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t sf_if_0_spi_mode : 3; /* [30:28], r/w, 0x0 */
+ uint32_t sf_if_0_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_sahb_0;
+
+ /* 0xC : sf_if_sahb_1 */
+ union {
+ struct {
+ uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_sahb_1;
+
+ /* 0x10 : sf_if_sahb_2 */
+ union {
+ struct {
+ uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_sahb_2;
+
+ /* 0x14 : sf_if_iahb_0 */
+ union {
+ struct {
+ uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
+ uint32_t sf_if_1_dmy_byte : 5; /* [16:12], r/w, 0x0 */
+ uint32_t sf_if_1_adr_byte : 3; /* [19:17], r/w, 0x2 */
+ uint32_t sf_if_1_cmd_byte : 3; /* [22:20], r/w, 0x0 */
+ uint32_t sf_if_1_dat_rw : 1; /* [ 23], r/w, 0x0 */
+ uint32_t sf_if_1_dat_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t sf_if_1_dmy_en : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sf_if_1_adr_en : 1; /* [ 26], r/w, 0x1 */
+ uint32_t sf_if_1_cmd_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t sf_if_1_spi_mode : 3; /* [30:28], r/w, 0x0 */
+ uint32_t sf_if_1_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_0;
+
+ /* 0x18 : sf_if_iahb_1 */
+ union {
+ struct {
+ uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_1;
+
+ /* 0x1C : sf_if_iahb_2 */
+ union {
+ struct {
+ uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_2;
+
+ /* 0x20 : sf_if_status_0 */
+ union {
+ struct {
+ uint32_t sf_if_status_0 : 32; /* [31: 0], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_status_0;
+
+ /* 0x24 : sf_if_status_1 */
+ union {
+ struct {
+ uint32_t sf_if_status_1 : 32; /* [31: 0], r, 0x20000000 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_status_1;
+
+ /* 0x28 : sf_aes */
+ union {
+ struct {
+ uint32_t sf_aes_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t sf_aes_mode : 2; /* [ 2: 1], r/w, 0x0 */
+ uint32_t sf_aes_blk_mode : 1; /* [ 3], r/w, 0x0 */
+ uint32_t sf_aes_xts_key_opt : 1; /* [ 4], r/w, 0x0 */
+ uint32_t sf_aes_status : 27; /* [31: 5], r, 0x2 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes;
+
+ /* 0x2C : sf_ahb2sif_status */
+ union {
+ struct {
+ uint32_t sf_ahb2sif_status : 32; /* [31: 0], r, 0x1010003 */
+ } BF;
+ uint32_t WORD;
+ } sf_ahb2sif_status;
+
+ /* 0x30 : sf_if_io_dly_0 */
+ union {
+ struct {
+ uint32_t sf_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t sf_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t sf_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */
+ uint32_t sf_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */
+ uint32_t sf_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t sf_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_io_dly_0;
+
+ /* 0x34 : sf_if_io_dly_1 */
+ union {
+ struct {
+ uint32_t sf_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_io_dly_1;
+
+ /* 0x38 : sf_if_io_dly_2 */
+ union {
+ struct {
+ uint32_t sf_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_io_dly_2;
+
+ /* 0x3C : sf_if_io_dly_3 */
+ union {
+ struct {
+ uint32_t sf_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_io_dly_3;
+
+ /* 0x40 : sf_if_io_dly_4 */
+ union {
+ struct {
+ uint32_t sf_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_io_dly_4;
+
+ /* 0x44 : sf_reserved */
+ union {
+ struct {
+ uint32_t sf_reserved : 32; /* [31: 0], r/w, 0xffff */
+ } BF;
+ uint32_t WORD;
+ } sf_reserved;
+
+ /* 0x48 : sf2_if_io_dly_0 */
+ union {
+ struct {
+ uint32_t sf2_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t sf2_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t sf2_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */
+ uint32_t sf2_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */
+ uint32_t sf2_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t sf2_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf2_if_io_dly_0;
+
+ /* 0x4C : sf2_if_io_dly_1 */
+ union {
+ struct {
+ uint32_t sf2_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf2_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf2_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf2_if_io_dly_1;
+
+ /* 0x50 : sf2_if_io_dly_2 */
+ union {
+ struct {
+ uint32_t sf2_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf2_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf2_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf2_if_io_dly_2;
+
+ /* 0x54 : sf2_if_io_dly_3 */
+ union {
+ struct {
+ uint32_t sf2_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf2_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf2_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf2_if_io_dly_3;
+
+ /* 0x58 : sf2_if_io_dly_4 */
+ union {
+ struct {
+ uint32_t sf2_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf2_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf2_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf2_if_io_dly_4;
+
+ /* 0x5C : sf3_if_io_dly_0 */
+ union {
+ struct {
+ uint32_t sf3_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t sf3_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t sf3_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */
+ uint32_t sf3_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */
+ uint32_t sf3_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t sf3_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf3_if_io_dly_0;
+
+ /* 0x60 : sf3_if_io_dly_1 */
+ union {
+ struct {
+ uint32_t sf3_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf3_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf3_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf3_if_io_dly_1;
+
+ /* 0x64 : sf3_if_io_dly_2 */
+ union {
+ struct {
+ uint32_t sf3_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf3_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf3_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf3_if_io_dly_2;
+
+ /* 0x68 : sf3_if_io_dly_3 */
+ union {
+ struct {
+ uint32_t sf3_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf3_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf3_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf3_if_io_dly_3;
+
+ /* 0x6C : sf3_if_io_dly_4 */
+ union {
+ struct {
+ uint32_t sf3_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t sf3_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t sf3_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf3_if_io_dly_4;
+
+ /* 0x70 : sf_ctrl_2 */
+ union {
+ struct {
+ uint32_t sf_if_pad_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */
+ uint32_t sf_if_pad_sel_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t sf_if_dtr_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t sf_if_dqs_en : 1; /* [ 5], r/w, 0x0 */
+ uint32_t sf_if_trig_wr_prot : 1; /* [ 6], r/w, 0x0 */
+ uint32_t sf_id_offset_lock : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reserved_8_24 : 17; /* [24: 8], rsvd, 0x0 */
+ uint32_t sf_ahb2sif_remap_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sf_ahb2sif_remap : 2; /* [27:26], r/w, 0x0 */
+ uint32_t sf_if_bk_swap : 1; /* [ 28], r/w, 0x0 */
+ uint32_t sf_if_bk2_mode : 1; /* [ 29], r/w, 0x0 */
+ uint32_t sf_if_bk2_en : 1; /* [ 30], r/w, 0x0 */
+ uint32_t sf_if_0_bk_sel : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_ctrl_2;
+
+ /* 0x74 : sf_ctrl_3 */
+ union {
+ struct {
+ uint32_t sf_cmds_2_wrap_len : 4; /* [ 3: 0], r/w, 0x6 */
+ uint32_t sf_cmds_2_en : 1; /* [ 4], r/w, 0x1 */
+ uint32_t sf_cmds_2_bt_dly : 3; /* [ 7: 5], r/w, 0x2 */
+ uint32_t sf_cmds_2_bt_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t sf_cmds_2_wrap_q_ini : 1; /* [ 9], r/w, 0x0 */
+ uint32_t sf_cmds_2_wrap_mode : 2; /* [11:10], r/w, 0x0 */
+ uint32_t sf_cmds_2_wrap_q : 1; /* [ 12], r, 0x0 */
+ uint32_t sf_cmds_1_wrap_len : 4; /* [16:13], r/w, 0x6 */
+ uint32_t sf_cmds_1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t sf_cmds_1_wrap_mode : 2; /* [19:18], r/w, 0x0 */
+ uint32_t sf_cmds_core_en : 1; /* [ 20], r/w, 0x1 */
+ uint32_t reserved_21_28 : 8; /* [28:21], rsvd, 0x0 */
+ uint32_t sf_if_1_ack_lat : 3; /* [31:29], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } sf_ctrl_3;
+
+ /* 0x78 : sf_if_iahb_3 */
+ union {
+ struct {
+ uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
+ uint32_t sf_if_2_dmy_byte : 5; /* [16:12], r/w, 0x0 */
+ uint32_t sf_if_2_adr_byte : 3; /* [19:17], r/w, 0x2 */
+ uint32_t sf_if_2_cmd_byte : 3; /* [22:20], r/w, 0x0 */
+ uint32_t sf_if_2_dat_rw : 1; /* [ 23], r/w, 0x1 */
+ uint32_t sf_if_2_dat_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t sf_if_2_dmy_en : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sf_if_2_adr_en : 1; /* [ 26], r/w, 0x1 */
+ uint32_t sf_if_2_cmd_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t sf_if_2_spi_mode : 3; /* [30:28], r/w, 0x0 */
+ uint32_t sf_if_2_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_3;
+
+ /* 0x7C : sf_if_iahb_4 */
+ union {
+ struct {
+ uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0], r/w, 0x38000000 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_4;
+
+ /* 0x80 : sf_if_iahb_5 */
+ union {
+ struct {
+ uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_5;
+
+ /* 0x84 : sf_if_iahb_6 */
+ union {
+ struct {
+ uint32_t reserved_0_16 : 17; /* [16: 0], rsvd, 0x0 */
+ uint32_t sf_if_3_adr_byte : 3; /* [19:17], r/w, 0x0 */
+ uint32_t sf_if_3_cmd_byte : 3; /* [22:20], r/w, 0x0 */
+ uint32_t reserved_23_25 : 3; /* [25:23], rsvd, 0x0 */
+ uint32_t sf_if_3_adr_en : 1; /* [ 26], r/w, 0x0 */
+ uint32_t sf_if_3_cmd_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t sf_if_3_spi_mode : 3; /* [30:28], r/w, 0x0 */
+ uint32_t sf_if_3_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_6;
+
+ /* 0x88 : sf_if_iahb_7 */
+ union {
+ struct {
+ uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0], r/w, 0xc0000000L */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_7;
+
+ /* 0x8C : sf_if_iahb_8 */
+ union {
+ struct {
+ uint32_t sf_if_3_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_8;
+
+ /* 0x90 : sf_if_iahb_9 */
+ union {
+ struct {
+ uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
+ uint32_t sf_if_4_dmy_byte : 5; /* [16:12], r/w, 0x2 */
+ uint32_t sf_if_4_adr_byte : 3; /* [19:17], r/w, 0x2 */
+ uint32_t sf_if_4_cmd_byte : 3; /* [22:20], r/w, 0x0 */
+ uint32_t sf_if_4_dat_rw : 1; /* [ 23], r/w, 0x0 */
+ uint32_t sf_if_4_dat_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t sf_if_4_dmy_en : 1; /* [ 25], r/w, 0x1 */
+ uint32_t sf_if_4_adr_en : 1; /* [ 26], r/w, 0x1 */
+ uint32_t sf_if_4_cmd_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t sf_if_4_spi_mode : 3; /* [30:28], r/w, 0x0 */
+ uint32_t sf_if_4_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_9;
+
+ /* 0x94 : sf_if_iahb_10 */
+ union {
+ struct {
+ uint32_t sf_if_4_cmd_buf_0 : 32; /* [31: 0], r/w, 0xeb000000L */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_10;
+
+ /* 0x98 : sf_if_iahb_11 */
+ union {
+ struct {
+ uint32_t sf_if_4_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_11;
+
+ /* 0x9C : sf_if_iahb_12 */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t sf2_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t sf2_clk_sf_rx_inv_src : 1; /* [ 3], r/w, 0x0 */
+ uint32_t sf2_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */
+ uint32_t sf3_clk_out_inv_sel : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t sf2_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */
+ uint32_t sf2_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */
+ uint32_t sf2_if_read_dly_src : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if_iahb_12;
+
+ /* 0xA0 : sf_id0_offset */
+ union {
+ struct {
+ uint32_t sf_id0_offset : 28; /* [27: 0], r/w, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_id0_offset;
+
+ /* 0xA4 : sf_id1_offset */
+ union {
+ struct {
+ uint32_t sf_id1_offset : 28; /* [27: 0], r/w, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_id1_offset;
+
+ /* 0xA8 : sf_bk2_id0_offset */
+ union {
+ struct {
+ uint32_t sf_bk2_id0_offset : 28; /* [27: 0], r/w, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_bk2_id0_offset;
+
+ /* 0xAC : sf_bk2_id1_offset */
+ union {
+ struct {
+ uint32_t sf_bk2_id1_offset : 28; /* [27: 0], r/w, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_bk2_id1_offset;
+
+ /* 0xB0 : sf_dbg */
+ union {
+ struct {
+ uint32_t sf_autoload_st : 5; /* [ 4: 0], r, 0x1 */
+ uint32_t sf_autoload_st_done : 1; /* [ 5], r, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_dbg;
+
+ /* 0xb4 reserved */
+ uint8_t RESERVED0xb4[12];
+
+ /* 0xC0 : sf_if2_ctrl_0 */
+ union {
+ struct {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t sf_clk_sf_if2_rx_inv_sel : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
+ uint32_t sf_if2_read_dly_n : 3; /* [10: 8], r/w, 0x0 */
+ uint32_t sf_if2_read_dly_en : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t sf_if2_int : 1; /* [ 16], r, 0x0 */
+ uint32_t sf_if2_int_clr : 1; /* [ 17], r/w, 0x1 */
+ uint32_t sf_if2_int_set : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_22 : 4; /* [22:19], rsvd, 0x0 */
+ uint32_t sf_if2_replace_sf1 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t sf_if2_replace_sf2 : 1; /* [ 24], r/w, 0x0 */
+ uint32_t sf_if2_replace_sf3 : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sf_if2_pad_sel : 2; /* [27:26], r/w, 0x0 */
+ uint32_t sf_if2_bk_swap : 1; /* [ 28], r/w, 0x0 */
+ uint32_t sf_if2_bk2_mode : 1; /* [ 29], r/w, 0x0 */
+ uint32_t sf_if2_bk2_en : 1; /* [ 30], r/w, 0x0 */
+ uint32_t sf_if2_bk_sel : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if2_ctrl_0;
+
+ /* 0xC4 : sf_if2_ctrl_1 */
+ union {
+ struct {
+ uint32_t sf_if2_sr_pat_mask : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t sf_if2_sr_pat : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t sf_if2_sr_int : 1; /* [ 16], r, 0x0 */
+ uint32_t sf_if2_sr_int_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t sf_if2_sr_int_set : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t sf_if2_ack_lat : 3; /* [22:20], r/w, 0x6 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t sf_if2_reg_hold : 1; /* [ 24], r/w, 0x1 */
+ uint32_t sf_if2_reg_wp : 1; /* [ 25], r/w, 0x1 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t sf_if2_fn_sel : 1; /* [ 28], r/w, 0x0 */
+ uint32_t sf_if2_en : 1; /* [ 29], r/w, 0x1 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if2_ctrl_1;
+
+ /* 0xC8 : sf_if2_sahb_0 */
+ union {
+ struct {
+ uint32_t sf_if2_busy : 1; /* [ 0], r, 0x0 */
+ uint32_t sf_if2_0_trig : 1; /* [ 1], r/w, 0x0 */
+ uint32_t sf_if2_0_dat_byte : 10; /* [11: 2], r/w, 0xff */
+ uint32_t sf_if2_0_dmy_byte : 5; /* [16:12], r/w, 0x0 */
+ uint32_t sf_if2_0_adr_byte : 3; /* [19:17], r/w, 0x2 */
+ uint32_t sf_if2_0_cmd_byte : 3; /* [22:20], r/w, 0x0 */
+ uint32_t sf_if2_0_dat_rw : 1; /* [ 23], r/w, 0x0 */
+ uint32_t sf_if2_0_dat_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t sf_if2_0_dmy_en : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sf_if2_0_adr_en : 1; /* [ 26], r/w, 0x1 */
+ uint32_t sf_if2_0_cmd_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t sf_if2_0_spi_mode : 3; /* [30:28], r/w, 0x0 */
+ uint32_t sf_if2_0_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if2_sahb_0;
+
+ /* 0xCC : sf_if2_sahb_1 */
+ union {
+ struct {
+ uint32_t sf_if2_0_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */
+ } BF;
+ uint32_t WORD;
+ } sf_if2_sahb_1;
+
+ /* 0xD0 : sf_if2_sahb_2 */
+ union {
+ struct {
+ uint32_t sf_if2_0_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_if2_sahb_2;
+
+ /* 0xd4 reserved */
+ uint8_t RESERVED0xd4[44];
+
+ /* 0x100 : sf_ctrl_prot_en_rd */
+ union {
+ struct {
+ uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
+ uint32_t sf_ctrl_id0_en_rd : 1; /* [ 1], r, 0x1 */
+ uint32_t sf_ctrl_id1_en_rd : 1; /* [ 2], r, 0x1 */
+ uint32_t reserved_3_27 : 25; /* [27: 3], rsvd, 0x0 */
+ uint32_t sf_sec_tzsid_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t sf_if2_0_trig_wr_lock : 1; /* [ 29], r, 0x0 */
+ uint32_t sf_if_0_trig_wr_lock : 1; /* [ 30], r, 0x0 */
+ uint32_t sf_dbg_dis : 1; /* [ 31], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_ctrl_prot_en_rd;
+
+ /* 0x104 : sf_ctrl_prot_en */
+ union {
+ struct {
+ uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
+ uint32_t sf_ctrl_id0_en : 1; /* [ 1], r/w, 0x1 */
+ uint32_t sf_ctrl_id1_en : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_ctrl_prot_en;
+
+ /* 0x108 reserved */
+ uint8_t RESERVED0x108[248];
+
+ /* 0x200 : sf_aes_key_r0_0 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_0;
+
+ /* 0x204 : sf_aes_key_r0_1 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_1;
+
+ /* 0x208 : sf_aes_key_r0_2 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_2;
+
+ /* 0x20C : sf_aes_key_r0_3 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_3;
+
+ /* 0x210 : sf_aes_key_r0_4 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_4 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_4;
+
+ /* 0x214 : sf_aes_key_r0_5 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_5 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_5;
+
+ /* 0x218 : sf_aes_key_r0_6 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_6 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_6;
+
+ /* 0x21C : sf_aes_key_r0_7 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r0_7 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r0_7;
+
+ /* 0x220 : sf_aes_iv_r0_w0 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r0_w0;
+
+ /* 0x224 : sf_aes_iv_r0_w1 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r0_w1;
+
+ /* 0x228 : sf_aes_iv_r0_w2 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r0_w2;
+
+ /* 0x22C : sf_aes_iv_r0_w3 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r0_w3;
+
+ /* 0x230 : sf_aes_r0_start */
+ union {
+ struct {
+ uint32_t sf_aes_region_r0_start : 19; /* [18: 0], r/w, 0x0 */
+ uint32_t reserved_19_28 : 10; /* [28:19], rsvd, 0x0 */
+ uint32_t sf_aes_region_r0_hw_key_en : 1; /* [ 29], r/w, 0x0 */
+ uint32_t sf_aes_region_r0_en : 1; /* [ 30], r/w, 0x0 */
+ uint32_t sf_aes_region_r0_lock : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_r0_start;
+
+ /* 0x234 : sf_aes_r0_end */
+ union {
+ struct {
+ uint32_t sf_aes_region_r0_end : 19; /* [18: 0], r/w, 0x3fff */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_r0_end;
+
+ /* 0x238 reserved */
+ uint8_t RESERVED0x238[72];
+
+ /* 0x280 : sf_aes_key_r1_0 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_0;
+
+ /* 0x284 : sf_aes_key_r1_1 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_1;
+
+ /* 0x288 : sf_aes_key_r1_2 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_2;
+
+ /* 0x28C : sf_aes_key_r1_3 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_3;
+
+ /* 0x290 : sf_aes_key_r1_4 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_4 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_4;
+
+ /* 0x294 : sf_aes_key_r1_5 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_5 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_5;
+
+ /* 0x298 : sf_aes_key_r1_6 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_6 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_6;
+
+ /* 0x29C : sf_aes_key_r1_7 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r1_7 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r1_7;
+
+ /* 0x2A0 : sf_aes_iv_r1_w0 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r1_w0;
+
+ /* 0x2A4 : sf_aes_iv_r1_w1 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r1_w1;
+
+ /* 0x2A8 : sf_aes_iv_r1_w2 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r1_w2;
+
+ /* 0x2AC : sf_aes_iv_r1_w3 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r1_w3;
+
+ /* 0x2B0 : sf_aes_r1_start */
+ union {
+ struct {
+ uint32_t sf_aes_r1_start : 19; /* [18: 0], r/w, 0x0 */
+ uint32_t reserved_19_28 : 10; /* [28:19], rsvd, 0x0 */
+ uint32_t sf_aes_r1_hw_key_en : 1; /* [ 29], r/w, 0x0 */
+ uint32_t sf_aes_r1_en : 1; /* [ 30], r/w, 0x0 */
+ uint32_t sf_aes_r1_lock : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_r1_start;
+
+ /* 0x2B4 : sf_aes_r1_end */
+ union {
+ struct {
+ uint32_t sf_aes_r1_end : 19; /* [18: 0], r/w, 0x3fff */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_r1_end;
+
+ /* 0x2b8 reserved */
+ uint8_t RESERVED0x2b8[72];
+
+ /* 0x300 : sf_aes_key_r2_0 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_0;
+
+ /* 0x304 : sf_aes_key_r2_1 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_1;
+
+ /* 0x308 : sf_aes_key_r2_2 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_2;
+
+ /* 0x30C : sf_aes_key_r2_3 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_3;
+
+ /* 0x310 : sf_aes_key_r2_4 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_4 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_4;
+
+ /* 0x314 : sf_aes_key_r2_5 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_5 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_5;
+
+ /* 0x318 : sf_aes_key_r2_6 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_6 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_6;
+
+ /* 0x31C : sf_aes_key_r2_7 */
+ union {
+ struct {
+ uint32_t sf_aes_key_r2_7 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_r2_7;
+
+ /* 0x320 : sf_aes_iv_r2_w0 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r2_w0;
+
+ /* 0x324 : sf_aes_iv_r2_w1 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r2_w1;
+
+ /* 0x328 : sf_aes_iv_r2_w2 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r2_w2;
+
+ /* 0x32C : sf_aes_iv_r2_w3 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_r2_w3;
+
+ /* 0x330 : sf_aes_r2_start */
+ union {
+ struct {
+ uint32_t sf_aes_r2_start : 19; /* [18: 0], r/w, 0x0 */
+ uint32_t reserved_19_28 : 10; /* [28:19], rsvd, 0x0 */
+ uint32_t sf_aes_r2_hw_key_en : 1; /* [ 29], r/w, 0x0 */
+ uint32_t sf_aes_r2_en : 1; /* [ 30], r/w, 0x0 */
+ uint32_t sf_aes_r2_lock : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_r2_start;
+
+ /* 0x334 : sf_aes_r2_end */
+ union {
+ struct {
+ uint32_t sf_aes_r2_end : 19; /* [18: 0], r/w, 0x3fff */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_r2_end;
+};
+
+typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : sf_if_sahb_0 */
+#define SF_CTRL_IF_SAHB_0_OFFSET (0x0)
+#define SF_CTRL_IF_BUSY SF_CTRL_IF_BUSY
+#define SF_CTRL_IF_BUSY_POS (0U)
+#define SF_CTRL_IF_BUSY_LEN (1U)
+#define SF_CTRL_IF_BUSY_MSK (((1U << SF_CTRL_IF_BUSY_LEN) - 1) << SF_CTRL_IF_BUSY_POS)
+#define SF_CTRL_IF_BUSY_UMSK (~(((1U << SF_CTRL_IF_BUSY_LEN) - 1) << SF_CTRL_IF_BUSY_POS))
+#define SF_CTRL_IF_0_TRIG SF_CTRL_IF_0_TRIG
+#define SF_CTRL_IF_0_TRIG_POS (1U)
+#define SF_CTRL_IF_0_TRIG_LEN (1U)
+#define SF_CTRL_IF_0_TRIG_MSK (((1U << SF_CTRL_IF_0_TRIG_LEN) - 1) << SF_CTRL_IF_0_TRIG_POS)
+#define SF_CTRL_IF_0_TRIG_UMSK (~(((1U << SF_CTRL_IF_0_TRIG_LEN) - 1) << SF_CTRL_IF_0_TRIG_POS))
+#define SF_CTRL_IF_0_DAT_BYTE SF_CTRL_IF_0_DAT_BYTE
+#define SF_CTRL_IF_0_DAT_BYTE_POS (2U)
+#define SF_CTRL_IF_0_DAT_BYTE_LEN (10U)
+#define SF_CTRL_IF_0_DAT_BYTE_MSK (((1U << SF_CTRL_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_IF_0_DAT_BYTE_POS)
+#define SF_CTRL_IF_0_DAT_BYTE_UMSK (~(((1U << SF_CTRL_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_IF_0_DAT_BYTE_POS))
+#define SF_CTRL_IF_0_DMY_BYTE SF_CTRL_IF_0_DMY_BYTE
+#define SF_CTRL_IF_0_DMY_BYTE_POS (12U)
+#define SF_CTRL_IF_0_DMY_BYTE_LEN (5U)
+#define SF_CTRL_IF_0_DMY_BYTE_MSK (((1U << SF_CTRL_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_IF_0_DMY_BYTE_POS)
+#define SF_CTRL_IF_0_DMY_BYTE_UMSK (~(((1U << SF_CTRL_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_IF_0_DMY_BYTE_POS))
+#define SF_CTRL_IF_0_ADR_BYTE SF_CTRL_IF_0_ADR_BYTE
+#define SF_CTRL_IF_0_ADR_BYTE_POS (17U)
+#define SF_CTRL_IF_0_ADR_BYTE_LEN (3U)
+#define SF_CTRL_IF_0_ADR_BYTE_MSK (((1U << SF_CTRL_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_IF_0_ADR_BYTE_POS)
+#define SF_CTRL_IF_0_ADR_BYTE_UMSK (~(((1U << SF_CTRL_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_IF_0_ADR_BYTE_POS))
+#define SF_CTRL_IF_0_CMD_BYTE SF_CTRL_IF_0_CMD_BYTE
+#define SF_CTRL_IF_0_CMD_BYTE_POS (20U)
+#define SF_CTRL_IF_0_CMD_BYTE_LEN (3U)
+#define SF_CTRL_IF_0_CMD_BYTE_MSK (((1U << SF_CTRL_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_IF_0_CMD_BYTE_POS)
+#define SF_CTRL_IF_0_CMD_BYTE_UMSK (~(((1U << SF_CTRL_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_IF_0_CMD_BYTE_POS))
+#define SF_CTRL_IF_0_DAT_RW SF_CTRL_IF_0_DAT_RW
+#define SF_CTRL_IF_0_DAT_RW_POS (23U)
+#define SF_CTRL_IF_0_DAT_RW_LEN (1U)
+#define SF_CTRL_IF_0_DAT_RW_MSK (((1U << SF_CTRL_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_IF_0_DAT_RW_POS)
+#define SF_CTRL_IF_0_DAT_RW_UMSK (~(((1U << SF_CTRL_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_IF_0_DAT_RW_POS))
+#define SF_CTRL_IF_0_DAT_EN SF_CTRL_IF_0_DAT_EN
+#define SF_CTRL_IF_0_DAT_EN_POS (24U)
+#define SF_CTRL_IF_0_DAT_EN_LEN (1U)
+#define SF_CTRL_IF_0_DAT_EN_MSK (((1U << SF_CTRL_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_IF_0_DAT_EN_POS)
+#define SF_CTRL_IF_0_DAT_EN_UMSK (~(((1U << SF_CTRL_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_IF_0_DAT_EN_POS))
+#define SF_CTRL_IF_0_DMY_EN SF_CTRL_IF_0_DMY_EN
+#define SF_CTRL_IF_0_DMY_EN_POS (25U)
+#define SF_CTRL_IF_0_DMY_EN_LEN (1U)
+#define SF_CTRL_IF_0_DMY_EN_MSK (((1U << SF_CTRL_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_IF_0_DMY_EN_POS)
+#define SF_CTRL_IF_0_DMY_EN_UMSK (~(((1U << SF_CTRL_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_IF_0_DMY_EN_POS))
+#define SF_CTRL_IF_0_ADR_EN SF_CTRL_IF_0_ADR_EN
+#define SF_CTRL_IF_0_ADR_EN_POS (26U)
+#define SF_CTRL_IF_0_ADR_EN_LEN (1U)
+#define SF_CTRL_IF_0_ADR_EN_MSK (((1U << SF_CTRL_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_IF_0_ADR_EN_POS)
+#define SF_CTRL_IF_0_ADR_EN_UMSK (~(((1U << SF_CTRL_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_IF_0_ADR_EN_POS))
+#define SF_CTRL_IF_0_CMD_EN SF_CTRL_IF_0_CMD_EN
+#define SF_CTRL_IF_0_CMD_EN_POS (27U)
+#define SF_CTRL_IF_0_CMD_EN_LEN (1U)
+#define SF_CTRL_IF_0_CMD_EN_MSK (((1U << SF_CTRL_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_IF_0_CMD_EN_POS)
+#define SF_CTRL_IF_0_CMD_EN_UMSK (~(((1U << SF_CTRL_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_IF_0_CMD_EN_POS))
+#define SF_CTRL_IF_0_SPI_MODE SF_CTRL_IF_0_SPI_MODE
+#define SF_CTRL_IF_0_SPI_MODE_POS (28U)
+#define SF_CTRL_IF_0_SPI_MODE_LEN (3U)
+#define SF_CTRL_IF_0_SPI_MODE_MSK (((1U << SF_CTRL_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_IF_0_SPI_MODE_POS)
+#define SF_CTRL_IF_0_SPI_MODE_UMSK (~(((1U << SF_CTRL_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_IF_0_SPI_MODE_POS))
+#define SF_CTRL_IF_0_QPI_MODE_EN SF_CTRL_IF_0_QPI_MODE_EN
+#define SF_CTRL_IF_0_QPI_MODE_EN_POS (31U)
+#define SF_CTRL_IF_0_QPI_MODE_EN_LEN (1U)
+#define SF_CTRL_IF_0_QPI_MODE_EN_MSK (((1U << SF_CTRL_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_IF_0_QPI_MODE_EN_POS)
+#define SF_CTRL_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_IF_0_QPI_MODE_EN_POS))
+
+/* 0x4 : sf_if_sahb_1 */
+#define SF_CTRL_IF_SAHB_1_OFFSET (0x4)
+#define SF_CTRL_IF_0_CMD_BUF_0 SF_CTRL_IF_0_CMD_BUF_0
+#define SF_CTRL_IF_0_CMD_BUF_0_POS (0U)
+#define SF_CTRL_IF_0_CMD_BUF_0_LEN (32U)
+#define SF_CTRL_IF_0_CMD_BUF_0_MSK (((1U << SF_CTRL_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_IF_0_CMD_BUF_0_POS)
+#define SF_CTRL_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_IF_0_CMD_BUF_0_POS))
+
+/* 0x8 : sf_if_sahb_2 */
+#define SF_CTRL_IF_SAHB_2_OFFSET (0x8)
+#define SF_CTRL_IF_0_CMD_BUF_1 SF_CTRL_IF_0_CMD_BUF_1
+#define SF_CTRL_IF_0_CMD_BUF_1_POS (0U)
+#define SF_CTRL_IF_0_CMD_BUF_1_LEN (32U)
+#define SF_CTRL_IF_0_CMD_BUF_1_MSK (((1U << SF_CTRL_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_IF_0_CMD_BUF_1_POS)
+#define SF_CTRL_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_IF_0_CMD_BUF_1_POS))
+
+struct sf_if_sahb_0_reg {
+ /* 0x0 : sf_if_sahb_0 */
+ union {
+ struct {
+ uint32_t if_busy : 1; /* [ 0], r, 0x0 */
+ uint32_t if_0_trig : 1; /* [ 1], r/w, 0x0 */
+ uint32_t if_0_dat_byte : 10; /* [11: 2], r/w, 0xff */
+ uint32_t if_0_dmy_byte : 5; /* [16:12], r/w, 0x0 */
+ uint32_t if_0_adr_byte : 3; /* [19:17], r/w, 0x2 */
+ uint32_t if_0_cmd_byte : 3; /* [22:20], r/w, 0x0 */
+ uint32_t if_0_dat_rw : 1; /* [ 23], r/w, 0x0 */
+ uint32_t if_0_dat_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t if_0_dmy_en : 1; /* [ 25], r/w, 0x0 */
+ uint32_t if_0_adr_en : 1; /* [ 26], r/w, 0x1 */
+ uint32_t if_0_cmd_en : 1; /* [ 27], r/w, 0x1 */
+ uint32_t if_0_spi_mode : 3; /* [30:28], r/w, 0x0 */
+ uint32_t if_0_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } if_sahb_0;
+
+ /* 0x4 : sf_if_sahb_1 */
+ union {
+ struct {
+ uint32_t if_0_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */
+ } BF;
+ uint32_t WORD;
+ } if_sahb_1;
+
+ /* 0x8 : sf_if_sahb_2 */
+ union {
+ struct {
+ uint32_t if_0_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } if_sahb_2;
+};
+
+typedef volatile struct sf_if_sahb_0_reg sf_if_sahb_0_reg_t;
+
+#define SF_CTRL_IF1_SAHB_OFFSET 0x8
+#define SF_CTRL_IF2_SAHB_OFFSET 0xC8
+
+/*Following is reg patch*/
+
+/* 0x0 : if_io_dly_0 */
+#define SF_CTRL_IO_DLY_0_OFFSET (0x0)
+#define SF_CTRL_CS_DLY_SEL SF_CTRL_CS_DLY_SEL
+#define SF_CTRL_CS_DLY_SEL_POS (0U)
+#define SF_CTRL_CS_DLY_SEL_LEN (2U)
+#define SF_CTRL_CS_DLY_SEL_MSK (((1U << SF_CTRL_CS_DLY_SEL_LEN) - 1) << SF_CTRL_CS_DLY_SEL_POS)
+#define SF_CTRL_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_CS_DLY_SEL_LEN) - 1) << SF_CTRL_CS_DLY_SEL_POS))
+#define SF_CTRL_CS2_DLY_SEL SF_CTRL_CS2_DLY_SEL
+#define SF_CTRL_CS2_DLY_SEL_POS (2U)
+#define SF_CTRL_CS2_DLY_SEL_LEN (2U)
+#define SF_CTRL_CS2_DLY_SEL_MSK (((1U << SF_CTRL_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_CS2_DLY_SEL_POS)
+#define SF_CTRL_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_CS2_DLY_SEL_POS))
+#define SF_CTRL_CLK_OUT_DLY_SEL SF_CTRL_CLK_OUT_DLY_SEL
+#define SF_CTRL_CLK_OUT_DLY_SEL_POS (8U)
+#define SF_CTRL_CLK_OUT_DLY_SEL_LEN (2U)
+#define SF_CTRL_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_DQS_OE_DLY_SEL SF_CTRL_DQS_OE_DLY_SEL
+#define SF_CTRL_DQS_OE_DLY_SEL_POS (26U)
+#define SF_CTRL_DQS_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_DQS_DI_DLY_SEL SF_CTRL_DQS_DI_DLY_SEL
+#define SF_CTRL_DQS_DI_DLY_SEL_POS (28U)
+#define SF_CTRL_DQS_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_DQS_DO_DLY_SEL SF_CTRL_DQS_DO_DLY_SEL
+#define SF_CTRL_DQS_DO_DLY_SEL_POS (30U)
+#define SF_CTRL_DQS_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_DQS_DO_DLY_SEL_POS))
+
+/* 0x4 : if_io_dly_1 */
+#define SF_CTRL_IO_DLY_1_OFFSET (0x4)
+#define SF_CTRL_IO_0_OE_DLY_SEL SF_CTRL_IO_0_OE_DLY_SEL
+#define SF_CTRL_IO_0_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_IO_0_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_IO_0_DI_DLY_SEL SF_CTRL_IO_0_DI_DLY_SEL
+#define SF_CTRL_IO_0_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_IO_0_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_IO_0_DO_DLY_SEL SF_CTRL_IO_0_DO_DLY_SEL
+#define SF_CTRL_IO_0_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_IO_0_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_0_DO_DLY_SEL_POS))
+
+/* 0x8 : if_io_dly_2 */
+#define SF_CTRL_IO_DLY_2_OFFSET (0x8)
+#define SF_CTRL_IO_1_OE_DLY_SEL SF_CTRL_IO_1_OE_DLY_SEL
+#define SF_CTRL_IO_1_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_IO_1_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_IO_1_DI_DLY_SEL SF_CTRL_IO_1_DI_DLY_SEL
+#define SF_CTRL_IO_1_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_IO_1_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_IO_1_DO_DLY_SEL SF_CTRL_IO_1_DO_DLY_SEL
+#define SF_CTRL_IO_1_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_IO_1_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_1_DO_DLY_SEL_POS))
+
+/* 0xc : if_io_dly_3 */
+#define SF_CTRL_IO_DLY_3_OFFSET (0xc)
+#define SF_CTRL_IO_2_OE_DLY_SEL SF_CTRL_IO_2_OE_DLY_SEL
+#define SF_CTRL_IO_2_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_IO_2_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_IO_2_DI_DLY_SEL SF_CTRL_IO_2_DI_DLY_SEL
+#define SF_CTRL_IO_2_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_IO_2_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_IO_2_DO_DLY_SEL SF_CTRL_IO_2_DO_DLY_SEL
+#define SF_CTRL_IO_2_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_IO_2_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_2_DO_DLY_SEL_POS))
+
+/* 0x10 : if_io_dly_4 */
+#define SF_CTRL_IO_DLY_4_OFFSET (0x10)
+#define SF_CTRL_IO_3_OE_DLY_SEL SF_CTRL_IO_3_OE_DLY_SEL
+#define SF_CTRL_IO_3_OE_DLY_SEL_POS (0U)
+#define SF_CTRL_IO_3_OE_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_IO_3_DI_DLY_SEL SF_CTRL_IO_3_DI_DLY_SEL
+#define SF_CTRL_IO_3_DI_DLY_SEL_POS (8U)
+#define SF_CTRL_IO_3_DI_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_IO_3_DO_DLY_SEL SF_CTRL_IO_3_DO_DLY_SEL
+#define SF_CTRL_IO_3_DO_DLY_SEL_POS (16U)
+#define SF_CTRL_IO_3_DO_DLY_SEL_LEN (2U)
+#define SF_CTRL_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_IO_3_DO_DLY_SEL_POS))
+
+struct sf_if_io_dly_0_reg {
+ /* 0x0 : if_io_dly_0 */
+ union {
+ struct {
+ uint32_t cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
+ uint32_t clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */
+ uint32_t dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */
+ uint32_t dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */
+ uint32_t dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } io_dly_0;
+
+ /* 0x4 : if_io_dly_1 */
+ union {
+ struct {
+ uint32_t io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } io_dly_1;
+
+ /* 0x8 : if_io_dly_2 */
+ union {
+ struct {
+ uint32_t io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } io_dly_2;
+
+ /* 0xc : if_io_dly_3 */
+ union {
+ struct {
+ uint32_t io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } io_dly_3;
+
+ /* 0x10 : if_io_dly_4 */
+ union {
+ struct {
+ uint32_t io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
+ uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } io_dly_4;
+};
+
+typedef volatile struct sf_if_io_dly_0_reg sf_if_io_dly_0_reg_t;
+
+#define SF_CTRL_IF_IO_DLY_1_OFFSET 0x30
+#define SF_CTRL_IF_IO_DLY_2_OFFSET 0x48
+#define SF_CTRL_IF_IO_DLY_3_OFFSET 0x5C
+
+/*Following is reg patch*/
+
+/* 0x0 : sf_aes_key_0 */
+#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0)
+#define SF_CTRL_SF_AES_KEY_0 SF_CTRL_SF_AES_KEY_0
+#define SF_CTRL_SF_AES_KEY_0_POS (0U)
+#define SF_CTRL_SF_AES_KEY_0_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_0_MSK (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)
+#define SF_CTRL_SF_AES_KEY_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS))
+
+/* 0x4 : sf_aes_key_1 */
+#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4)
+#define SF_CTRL_SF_AES_KEY_1 SF_CTRL_SF_AES_KEY_1
+#define SF_CTRL_SF_AES_KEY_1_POS (0U)
+#define SF_CTRL_SF_AES_KEY_1_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_1_MSK (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)
+#define SF_CTRL_SF_AES_KEY_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS))
+
+/* 0x8 : sf_aes_key_2 */
+#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8)
+#define SF_CTRL_SF_AES_KEY_2 SF_CTRL_SF_AES_KEY_2
+#define SF_CTRL_SF_AES_KEY_2_POS (0U)
+#define SF_CTRL_SF_AES_KEY_2_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_2_MSK (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)
+#define SF_CTRL_SF_AES_KEY_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS))
+
+/* 0xc : sf_aes_key_3 */
+#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc)
+#define SF_CTRL_SF_AES_KEY_3 SF_CTRL_SF_AES_KEY_3
+#define SF_CTRL_SF_AES_KEY_3_POS (0U)
+#define SF_CTRL_SF_AES_KEY_3_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_3_MSK (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)
+#define SF_CTRL_SF_AES_KEY_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS))
+
+/* 0x10 : sf_aes_key_4 */
+#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10)
+#define SF_CTRL_SF_AES_KEY_4 SF_CTRL_SF_AES_KEY_4
+#define SF_CTRL_SF_AES_KEY_4_POS (0U)
+#define SF_CTRL_SF_AES_KEY_4_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_4_MSK (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)
+#define SF_CTRL_SF_AES_KEY_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS))
+
+/* 0x14 : sf_aes_key_5 */
+#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14)
+#define SF_CTRL_SF_AES_KEY_5 SF_CTRL_SF_AES_KEY_5
+#define SF_CTRL_SF_AES_KEY_5_POS (0U)
+#define SF_CTRL_SF_AES_KEY_5_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_5_MSK (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)
+#define SF_CTRL_SF_AES_KEY_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS))
+
+/* 0x18 : sf_aes_key_6 */
+#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18)
+#define SF_CTRL_SF_AES_KEY_6 SF_CTRL_SF_AES_KEY_6
+#define SF_CTRL_SF_AES_KEY_6_POS (0U)
+#define SF_CTRL_SF_AES_KEY_6_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_6_MSK (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)
+#define SF_CTRL_SF_AES_KEY_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS))
+
+/* 0x1c : sf_aes_key_7 */
+#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c)
+#define SF_CTRL_SF_AES_KEY_7 SF_CTRL_SF_AES_KEY_7
+#define SF_CTRL_SF_AES_KEY_7_POS (0U)
+#define SF_CTRL_SF_AES_KEY_7_LEN (32U)
+#define SF_CTRL_SF_AES_KEY_7_MSK (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)
+#define SF_CTRL_SF_AES_KEY_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS))
+
+/* 0x20 : sf_aes_iv_w0 */
+#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20)
+#define SF_CTRL_SF_AES_IV_W0 SF_CTRL_SF_AES_IV_W0
+#define SF_CTRL_SF_AES_IV_W0_POS (0U)
+#define SF_CTRL_SF_AES_IV_W0_LEN (32U)
+#define SF_CTRL_SF_AES_IV_W0_MSK (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)
+#define SF_CTRL_SF_AES_IV_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS))
+
+/* 0x24 : sf_aes_iv_w1 */
+#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24)
+#define SF_CTRL_SF_AES_IV_W1 SF_CTRL_SF_AES_IV_W1
+#define SF_CTRL_SF_AES_IV_W1_POS (0U)
+#define SF_CTRL_SF_AES_IV_W1_LEN (32U)
+#define SF_CTRL_SF_AES_IV_W1_MSK (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)
+#define SF_CTRL_SF_AES_IV_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS))
+
+/* 0x28 : sf_aes_iv_w2 */
+#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28)
+#define SF_CTRL_SF_AES_IV_W2 SF_CTRL_SF_AES_IV_W2
+#define SF_CTRL_SF_AES_IV_W2_POS (0U)
+#define SF_CTRL_SF_AES_IV_W2_LEN (32U)
+#define SF_CTRL_SF_AES_IV_W2_MSK (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)
+#define SF_CTRL_SF_AES_IV_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS))
+
+/* 0x2c : sf_aes_iv_w3 */
+#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c)
+#define SF_CTRL_SF_AES_IV_W3 SF_CTRL_SF_AES_IV_W3
+#define SF_CTRL_SF_AES_IV_W3_POS (0U)
+#define SF_CTRL_SF_AES_IV_W3_LEN (32U)
+#define SF_CTRL_SF_AES_IV_W3_MSK (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)
+#define SF_CTRL_SF_AES_IV_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS))
+
+/* 0x30 : sf_aes_start */
+#define SF_CTRL_SF_AES_START_OFFSET (0x30)
+#define SF_CTRL_SF_AES_REGION_START SF_CTRL_SF_AES_REGION_START
+#define SF_CTRL_SF_AES_REGION_START_POS (0U)
+#define SF_CTRL_SF_AES_REGION_START_LEN (19U)
+#define SF_CTRL_SF_AES_REGION_START_MSK (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)
+#define SF_CTRL_SF_AES_REGION_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS))
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN SF_CTRL_SF_AES_REGION_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS (29U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN (1U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_EN SF_CTRL_SF_AES_REGION_EN
+#define SF_CTRL_SF_AES_REGION_EN_POS (30U)
+#define SF_CTRL_SF_AES_REGION_EN_LEN (1U)
+#define SF_CTRL_SF_AES_REGION_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)
+#define SF_CTRL_SF_AES_REGION_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS))
+#define SF_CTRL_SF_AES_REGION_LOCK SF_CTRL_SF_AES_REGION_LOCK
+#define SF_CTRL_SF_AES_REGION_LOCK_POS (31U)
+#define SF_CTRL_SF_AES_REGION_LOCK_LEN (1U)
+#define SF_CTRL_SF_AES_REGION_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS))
+
+/* 0x34 : sf_aes_end */
+#define SF_CTRL_SF_AES_END_OFFSET (0x34)
+#define SF_CTRL_SF_AES_REGION_END SF_CTRL_SF_AES_REGION_END
+#define SF_CTRL_SF_AES_REGION_END_POS (0U)
+#define SF_CTRL_SF_AES_REGION_END_LEN (19U)
+#define SF_CTRL_SF_AES_REGION_END_MSK (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)
+#define SF_CTRL_SF_AES_REGION_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS))
+
+struct sf_ctrl_aes_region_reg {
+ /* 0x0 : sf_aes_key_0 */
+ union {
+ struct {
+ uint32_t sf_aes_key_0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_0;
+
+ /* 0x4 : sf_aes_key_1 */
+ union {
+ struct {
+ uint32_t sf_aes_key_1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_1;
+
+ /* 0x8 : sf_aes_key_2 */
+ union {
+ struct {
+ uint32_t sf_aes_key_2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_2;
+
+ /* 0xc : sf_aes_key_3 */
+ union {
+ struct {
+ uint32_t sf_aes_key_3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_3;
+
+ /* 0x10 : sf_aes_key_4 */
+ union {
+ struct {
+ uint32_t sf_aes_key_4 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_4;
+
+ /* 0x14 : sf_aes_key_5 */
+ union {
+ struct {
+ uint32_t sf_aes_key_5 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_5;
+
+ /* 0x18 : sf_aes_key_6 */
+ union {
+ struct {
+ uint32_t sf_aes_key_6 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_6;
+
+ /* 0x1c : sf_aes_key_7 */
+ union {
+ struct {
+ uint32_t sf_aes_key_7 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_key_7;
+
+ /* 0x20 : sf_aes_iv_w0 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_w0 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_w0;
+
+ /* 0x24 : sf_aes_iv_w1 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_w1 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_w1;
+
+ /* 0x28 : sf_aes_iv_w2 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_w2 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_w2;
+
+ /* 0x2c : sf_aes_iv_w3 */
+ union {
+ struct {
+ uint32_t sf_aes_iv_w3 : 32; /* [31: 0], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_iv_w3;
+
+ /* 0x30 : sf_aes_start */
+ union {
+ struct {
+ uint32_t sf_aes_region_start : 19; /* [18: 0], r/w, 0x0 */
+ uint32_t reserved_19_28 : 10; /* [28:19], rsvd, 0x0 */
+ uint32_t sf_aes_region_hw_key_en : 1; /* [ 29], r/w, 0x0 */
+ uint32_t sf_aes_region_en : 1; /* [ 30], r/w, 0x0 */
+ uint32_t sf_aes_region_lock : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_start;
+
+ /* 0x34 : sf_aes_end */
+ union {
+ struct {
+ uint32_t sf_aes_region_end : 19; /* [18: 0], r/w, 0x3fff */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } sf_aes_end;
+};
+
+typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t;
+
+#define SF_CTRL_AES_REGION_OFFSET 0x200
+
+#endif /* __SF_CTRL_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/tzc_nsec_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/tzc_nsec_reg.h
new file mode 100644
index 00000000..2cc613fd
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/tzc_nsec_reg.h
@@ -0,0 +1,3803 @@
+/**
+ ******************************************************************************
+ * @file tzc_nsec_reg.h
+ * @version V1.0
+ * @date 2021-09-10
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __TZC_NSEC_REG_H__
+#define __TZC_NSEC_REG_H__
+
+#include "bl808.h"
+
+/* 0x40 : tzc_rom_tzsrg_ctrl */
+#define TZC_NSEC_TZC_ROM_TZSRG_CTRL_OFFSET (0x40)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_EN TZC_NSEC_TZC_ROM_TZSRG_R0_EN
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_EN TZC_NSEC_TZC_ROM_TZSRG_R1_EN
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_EN TZC_NSEC_TZC_ROM_TZSRG_R2_EN
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_LOCK_POS))
+#define TZC_NSEC_TZC_SBOOT_DONE TZC_NSEC_TZC_SBOOT_DONE
+#define TZC_NSEC_TZC_SBOOT_DONE_POS (28U)
+#define TZC_NSEC_TZC_SBOOT_DONE_LEN (4U)
+#define TZC_NSEC_TZC_SBOOT_DONE_MSK (((1U << TZC_NSEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_NSEC_TZC_SBOOT_DONE_POS)
+#define TZC_NSEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_NSEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_NSEC_TZC_SBOOT_DONE_POS))
+
+/* 0x44 : tzc_rom_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_OFFSET (0x44)
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x48 : tzc_rom_tzsrg_r0 */
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_OFFSET (0x48)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_END TZC_NSEC_TZC_ROM_TZSRG_R0_END
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_END_LEN (10U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_START TZC_NSEC_TZC_ROM_TZSRG_R0_START
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_START_LEN (10U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R0_START_POS))
+
+/* 0x4C : tzc_rom_tzsrg_r1 */
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_OFFSET (0x4C)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_END TZC_NSEC_TZC_ROM_TZSRG_R1_END
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_END_LEN (10U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_START TZC_NSEC_TZC_ROM_TZSRG_R1_START
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_START_LEN (10U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R1_START_POS))
+
+/* 0x50 : tzc_rom_tzsrg_r2 */
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_OFFSET (0x50)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_END TZC_NSEC_TZC_ROM_TZSRG_R2_END
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_END_LEN (10U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_START TZC_NSEC_TZC_ROM_TZSRG_R2_START
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_START_LEN (10U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_ROM_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_ROM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_ROM_TZSRG_R2_START_POS))
+
+/* 0x54 : tzc_rom_tzsrg_r3 */
+#define TZC_NSEC_TZC_ROM_TZSRG_R3_OFFSET (0x54)
+
+/* 0x100 : tzc_bmx_tzmid */
+#define TZC_NSEC_TZC_BMX_TZMID_OFFSET (0x100)
+#define TZC_NSEC_TZC_PICO_TZMID TZC_NSEC_TZC_PICO_TZMID
+#define TZC_NSEC_TZC_PICO_TZMID_POS (0U)
+#define TZC_NSEC_TZC_PICO_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_PICO_TZMID_MSK (((1U << TZC_NSEC_TZC_PICO_TZMID_LEN) - 1) << TZC_NSEC_TZC_PICO_TZMID_POS)
+#define TZC_NSEC_TZC_PICO_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_PICO_TZMID_LEN) - 1) << TZC_NSEC_TZC_PICO_TZMID_POS))
+#define TZC_NSEC_TZC_MM_TZMID TZC_NSEC_TZC_MM_TZMID
+#define TZC_NSEC_TZC_MM_TZMID_POS (1U)
+#define TZC_NSEC_TZC_MM_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_MM_TZMID_MSK (((1U << TZC_NSEC_TZC_MM_TZMID_LEN) - 1) << TZC_NSEC_TZC_MM_TZMID_POS)
+#define TZC_NSEC_TZC_MM_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_MM_TZMID_LEN) - 1) << TZC_NSEC_TZC_MM_TZMID_POS))
+#define TZC_NSEC_TZC_USB_TZMID TZC_NSEC_TZC_USB_TZMID
+#define TZC_NSEC_TZC_USB_TZMID_POS (2U)
+#define TZC_NSEC_TZC_USB_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_USB_TZMID_MSK (((1U << TZC_NSEC_TZC_USB_TZMID_LEN) - 1) << TZC_NSEC_TZC_USB_TZMID_POS)
+#define TZC_NSEC_TZC_USB_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_USB_TZMID_LEN) - 1) << TZC_NSEC_TZC_USB_TZMID_POS))
+#define TZC_NSEC_TZC_WIFI_TZMID TZC_NSEC_TZC_WIFI_TZMID
+#define TZC_NSEC_TZC_WIFI_TZMID_POS (3U)
+#define TZC_NSEC_TZC_WIFI_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_WIFI_TZMID_MSK (((1U << TZC_NSEC_TZC_WIFI_TZMID_LEN) - 1) << TZC_NSEC_TZC_WIFI_TZMID_POS)
+#define TZC_NSEC_TZC_WIFI_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_WIFI_TZMID_LEN) - 1) << TZC_NSEC_TZC_WIFI_TZMID_POS))
+#define TZC_NSEC_TZC_CCI_TZMID TZC_NSEC_TZC_CCI_TZMID
+#define TZC_NSEC_TZC_CCI_TZMID_POS (4U)
+#define TZC_NSEC_TZC_CCI_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_CCI_TZMID_MSK (((1U << TZC_NSEC_TZC_CCI_TZMID_LEN) - 1) << TZC_NSEC_TZC_CCI_TZMID_POS)
+#define TZC_NSEC_TZC_CCI_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_CCI_TZMID_LEN) - 1) << TZC_NSEC_TZC_CCI_TZMID_POS))
+#define TZC_NSEC_TZC_SDHM_TZMID TZC_NSEC_TZC_SDHM_TZMID
+#define TZC_NSEC_TZC_SDHM_TZMID_POS (5U)
+#define TZC_NSEC_TZC_SDHM_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_SDHM_TZMID_MSK (((1U << TZC_NSEC_TZC_SDHM_TZMID_LEN) - 1) << TZC_NSEC_TZC_SDHM_TZMID_POS)
+#define TZC_NSEC_TZC_SDHM_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_SDHM_TZMID_LEN) - 1) << TZC_NSEC_TZC_SDHM_TZMID_POS))
+#define TZC_NSEC_TZC_EMACA_TZMID TZC_NSEC_TZC_EMACA_TZMID
+#define TZC_NSEC_TZC_EMACA_TZMID_POS (6U)
+#define TZC_NSEC_TZC_EMACA_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_EMACA_TZMID_MSK (((1U << TZC_NSEC_TZC_EMACA_TZMID_LEN) - 1) << TZC_NSEC_TZC_EMACA_TZMID_POS)
+#define TZC_NSEC_TZC_EMACA_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_EMACA_TZMID_LEN) - 1) << TZC_NSEC_TZC_EMACA_TZMID_POS))
+#define TZC_NSEC_TZC_CPU_TZMID TZC_NSEC_TZC_CPU_TZMID
+#define TZC_NSEC_TZC_CPU_TZMID_POS (7U)
+#define TZC_NSEC_TZC_CPU_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_CPU_TZMID_MSK (((1U << TZC_NSEC_TZC_CPU_TZMID_LEN) - 1) << TZC_NSEC_TZC_CPU_TZMID_POS)
+#define TZC_NSEC_TZC_CPU_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_CPU_TZMID_LEN) - 1) << TZC_NSEC_TZC_CPU_TZMID_POS))
+#define TZC_NSEC_TZC_DMA_TZMID TZC_NSEC_TZC_DMA_TZMID
+#define TZC_NSEC_TZC_DMA_TZMID_POS (8U)
+#define TZC_NSEC_TZC_DMA_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_DMA_TZMID_MSK (((1U << TZC_NSEC_TZC_DMA_TZMID_LEN) - 1) << TZC_NSEC_TZC_DMA_TZMID_POS)
+#define TZC_NSEC_TZC_DMA_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_DMA_TZMID_LEN) - 1) << TZC_NSEC_TZC_DMA_TZMID_POS))
+#define TZC_NSEC_TZC_DMA2_TZMID TZC_NSEC_TZC_DMA2_TZMID
+#define TZC_NSEC_TZC_DMA2_TZMID_POS (9U)
+#define TZC_NSEC_TZC_DMA2_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_DMA2_TZMID_MSK (((1U << TZC_NSEC_TZC_DMA2_TZMID_LEN) - 1) << TZC_NSEC_TZC_DMA2_TZMID_POS)
+#define TZC_NSEC_TZC_DMA2_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_DMA2_TZMID_LEN) - 1) << TZC_NSEC_TZC_DMA2_TZMID_POS))
+#define TZC_NSEC_TZC_LZ4_TZMID TZC_NSEC_TZC_LZ4_TZMID
+#define TZC_NSEC_TZC_LZ4_TZMID_POS (10U)
+#define TZC_NSEC_TZC_LZ4_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_LZ4_TZMID_MSK (((1U << TZC_NSEC_TZC_LZ4_TZMID_LEN) - 1) << TZC_NSEC_TZC_LZ4_TZMID_POS)
+#define TZC_NSEC_TZC_LZ4_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_LZ4_TZMID_LEN) - 1) << TZC_NSEC_TZC_LZ4_TZMID_POS))
+#define TZC_NSEC_TZC_PICO_TZMID_SEL TZC_NSEC_TZC_PICO_TZMID_SEL
+#define TZC_NSEC_TZC_PICO_TZMID_SEL_POS (16U)
+#define TZC_NSEC_TZC_PICO_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_PICO_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_PICO_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_PICO_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_PICO_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_PICO_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_PICO_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_MM_TZMID_SEL TZC_NSEC_TZC_MM_TZMID_SEL
+#define TZC_NSEC_TZC_MM_TZMID_SEL_POS (17U)
+#define TZC_NSEC_TZC_MM_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_MM_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_MM_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_MM_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_MM_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_MM_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_MM_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_USB_TZMID_SEL TZC_NSEC_TZC_USB_TZMID_SEL
+#define TZC_NSEC_TZC_USB_TZMID_SEL_POS (18U)
+#define TZC_NSEC_TZC_USB_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_USB_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_USB_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_USB_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_USB_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_USB_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_USB_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_WIFI_TZMID_SEL TZC_NSEC_TZC_WIFI_TZMID_SEL
+#define TZC_NSEC_TZC_WIFI_TZMID_SEL_POS (19U)
+#define TZC_NSEC_TZC_WIFI_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_WIFI_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_WIFI_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_WIFI_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_WIFI_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_WIFI_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_WIFI_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_CCI_TZMID_SEL TZC_NSEC_TZC_CCI_TZMID_SEL
+#define TZC_NSEC_TZC_CCI_TZMID_SEL_POS (20U)
+#define TZC_NSEC_TZC_CCI_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_CCI_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_CCI_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CCI_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_CCI_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_CCI_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CCI_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_SDHM_TZMID_SEL TZC_NSEC_TZC_SDHM_TZMID_SEL
+#define TZC_NSEC_TZC_SDHM_TZMID_SEL_POS (21U)
+#define TZC_NSEC_TZC_SDHM_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_SDHM_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_SDHM_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_SDHM_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_SDHM_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_SDHM_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_SDHM_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_EMACA_TZMID_SEL TZC_NSEC_TZC_EMACA_TZMID_SEL
+#define TZC_NSEC_TZC_EMACA_TZMID_SEL_POS (22U)
+#define TZC_NSEC_TZC_EMACA_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_EMACA_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_EMACA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_EMACA_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_EMACA_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_EMACA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_EMACA_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_CPU_TZMID_SEL TZC_NSEC_TZC_CPU_TZMID_SEL
+#define TZC_NSEC_TZC_CPU_TZMID_SEL_POS (23U)
+#define TZC_NSEC_TZC_CPU_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_CPU_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_CPU_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CPU_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_CPU_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_CPU_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CPU_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_DMA_TZMID_SEL TZC_NSEC_TZC_DMA_TZMID_SEL
+#define TZC_NSEC_TZC_DMA_TZMID_SEL_POS (24U)
+#define TZC_NSEC_TZC_DMA_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_DMA_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_DMA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_DMA_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_DMA_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_DMA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_DMA_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_DMA2_TZMID_SEL TZC_NSEC_TZC_DMA2_TZMID_SEL
+#define TZC_NSEC_TZC_DMA2_TZMID_SEL_POS (25U)
+#define TZC_NSEC_TZC_DMA2_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_DMA2_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_DMA2_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_DMA2_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_DMA2_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_DMA2_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_DMA2_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_LZ4_TZMID_SEL TZC_NSEC_TZC_LZ4_TZMID_SEL
+#define TZC_NSEC_TZC_LZ4_TZMID_SEL_POS (26U)
+#define TZC_NSEC_TZC_LZ4_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_LZ4_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_LZ4_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_LZ4_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_LZ4_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_LZ4_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_LZ4_TZMID_SEL_POS))
+
+/* 0x104 : tzc_bmx_tzmid_lock */
+#define TZC_NSEC_TZC_BMX_TZMID_LOCK_OFFSET (0x104)
+#define TZC_NSEC_TZC_PICO_TZMID_LOCK TZC_NSEC_TZC_PICO_TZMID_LOCK
+#define TZC_NSEC_TZC_PICO_TZMID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_PICO_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PICO_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_PICO_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_PICO_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_PICO_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PICO_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_PICO_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_MM_TZMID_LOCK TZC_NSEC_TZC_MM_TZMID_LOCK
+#define TZC_NSEC_TZC_MM_TZMID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_MM_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_USB_TZMID_LOCK TZC_NSEC_TZC_USB_TZMID_LOCK
+#define TZC_NSEC_TZC_USB_TZMID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_USB_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_USB_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_USB_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_USB_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_USB_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_USB_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_USB_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_WIFI_TZMID_LOCK TZC_NSEC_TZC_WIFI_TZMID_LOCK
+#define TZC_NSEC_TZC_WIFI_TZMID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_WIFI_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_WIFI_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_WIFI_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_WIFI_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_WIFI_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_WIFI_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_WIFI_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_CCI_TZMID_LOCK TZC_NSEC_TZC_CCI_TZMID_LOCK
+#define TZC_NSEC_TZC_CCI_TZMID_LOCK_POS (4U)
+#define TZC_NSEC_TZC_CCI_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CCI_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_CCI_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CCI_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_CCI_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CCI_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CCI_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_SDHM_TZMID_LOCK TZC_NSEC_TZC_SDHM_TZMID_LOCK
+#define TZC_NSEC_TZC_SDHM_TZMID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_SDHM_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SDHM_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_SDHM_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SDHM_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_SDHM_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SDHM_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SDHM_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_EMACA_TZMID_LOCK TZC_NSEC_TZC_EMACA_TZMID_LOCK
+#define TZC_NSEC_TZC_EMACA_TZMID_LOCK_POS (6U)
+#define TZC_NSEC_TZC_EMACA_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_EMACA_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_EMACA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_EMACA_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_EMACA_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_EMACA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_EMACA_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_CPU_TZMID_LOCK TZC_NSEC_TZC_CPU_TZMID_LOCK
+#define TZC_NSEC_TZC_CPU_TZMID_LOCK_POS (7U)
+#define TZC_NSEC_TZC_CPU_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CPU_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_CPU_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CPU_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_CPU_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CPU_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CPU_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_DMA_TZMID_LOCK TZC_NSEC_TZC_DMA_TZMID_LOCK
+#define TZC_NSEC_TZC_DMA_TZMID_LOCK_POS (8U)
+#define TZC_NSEC_TZC_DMA_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_DMA_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_DMA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DMA_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_DMA_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_DMA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DMA_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_DMA2_TZMID_LOCK TZC_NSEC_TZC_DMA2_TZMID_LOCK
+#define TZC_NSEC_TZC_DMA2_TZMID_LOCK_POS (9U)
+#define TZC_NSEC_TZC_DMA2_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_DMA2_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_DMA2_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DMA2_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_DMA2_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_DMA2_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DMA2_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_LZ4_TZMID_LOCK TZC_NSEC_TZC_LZ4_TZMID_LOCK
+#define TZC_NSEC_TZC_LZ4_TZMID_LOCK_POS (10U)
+#define TZC_NSEC_TZC_LZ4_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_LZ4_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_LZ4_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_LZ4_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_LZ4_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_LZ4_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_LZ4_TZMID_LOCK_POS))
+
+/* 0x108 : tzc_bmx_s0 */
+#define TZC_NSEC_TZC_BMX_S0_OFFSET (0x108)
+#define TZC_NSEC_TZC_BMX_MM_TZSID_EN TZC_NSEC_TZC_BMX_MM_TZSID_EN
+#define TZC_NSEC_TZC_BMX_MM_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_BMX_MM_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_MM_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_MM_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_MM_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_MM_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_MM_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_MM_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_EN TZC_NSEC_TZC_BMX_DMA_TZSID_EN
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_DMA_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_DMA_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_EN TZC_NSEC_TZC_BMX_DMA2_TZSID_EN
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA2_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_EN TZC_NSEC_TZC_BMX_PWR_TZSID_EN
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_PWR_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_PWR_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_PWR_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_PWR_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_EN TZC_NSEC_TZC_BMX_SDH_TZSID_EN
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_SDH_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_SDH_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_SDH_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_SDH_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_EN TZC_NSEC_TZC_BMX_EMAC_TZSID_EN
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_EMAC_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_MM_TZSID_LOCK TZC_NSEC_TZC_BMX_MM_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_POS (16U)
+#define TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_MM_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_POS (17U)
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_POS (18U)
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_DMA2_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_POS (19U)
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_PWR_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_POS (20U)
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_SDH_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_POS (21U)
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_EMAC_TZSID_LOCK_POS))
+
+/* 0x10C : tzc_bmx_s1 */
+#define TZC_NSEC_TZC_BMX_S1_OFFSET (0x10C)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_EN TZC_NSEC_TZC_BMX_S10_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S10_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S10_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S10_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S11_TZSID_EN TZC_NSEC_TZC_BMX_S11_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S11_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_BMX_S11_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S11_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S11_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S11_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S11_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S12_TZSID_EN TZC_NSEC_TZC_BMX_S12_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S12_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_BMX_S12_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S12_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S12_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S12_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S12_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S13_TZSID_EN TZC_NSEC_TZC_BMX_S13_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S13_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_BMX_S13_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S13_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S13_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S13_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S13_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S14_TZSID_EN TZC_NSEC_TZC_BMX_S14_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S14_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_BMX_S14_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S14_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S14_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S14_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S14_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S15_TZSID_EN TZC_NSEC_TZC_BMX_S15_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S15_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_BMX_S15_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S15_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S15_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S15_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S15_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S16_TZSID_EN TZC_NSEC_TZC_BMX_S16_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S16_TZSID_EN_POS (12U)
+#define TZC_NSEC_TZC_BMX_S16_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S16_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S16_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S16_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S16_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S17_TZSID_EN TZC_NSEC_TZC_BMX_S17_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S17_TZSID_EN_POS (14U)
+#define TZC_NSEC_TZC_BMX_S17_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S17_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S17_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S17_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S17_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S18_TZSID_EN TZC_NSEC_TZC_BMX_S18_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S18_TZSID_EN_POS (16U)
+#define TZC_NSEC_TZC_BMX_S18_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S18_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S18_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S18_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S18_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S19_TZSID_EN TZC_NSEC_TZC_BMX_S19_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S19_TZSID_EN_POS (18U)
+#define TZC_NSEC_TZC_BMX_S19_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S19_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S19_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S19_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S19_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_EN TZC_NSEC_TZC_BMX_S1A_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_EN_POS (20U)
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1A_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1A_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_EN TZC_NSEC_TZC_BMX_S1B_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_EN_POS (22U)
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1B_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1B_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_EN TZC_NSEC_TZC_BMX_S1C_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_EN_POS (24U)
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1C_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1C_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_EN TZC_NSEC_TZC_BMX_S1D_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_EN_POS (26U)
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1D_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1D_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_EN TZC_NSEC_TZC_BMX_S1E_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_EN_POS (28U)
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1E_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1E_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_EN TZC_NSEC_TZC_BMX_S1F_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_EN_POS (30U)
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1F_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S1F_TZSID_EN_POS))
+
+/* 0x110 : tzc_bmx_s2 */
+#define TZC_NSEC_TZC_BMX_S2_OFFSET (0x110)
+#define TZC_NSEC_TZC_BMX_S20_TZSID_EN TZC_NSEC_TZC_BMX_S20_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S20_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_BMX_S20_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S20_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S20_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S20_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S20_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S20_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S20_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S21_TZSID_EN TZC_NSEC_TZC_BMX_S21_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S21_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_BMX_S21_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S21_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S21_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S21_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S21_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S21_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S21_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S22_TZSID_EN TZC_NSEC_TZC_BMX_S22_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S22_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_BMX_S22_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S22_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S22_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S22_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S22_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S22_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S22_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S23_TZSID_EN TZC_NSEC_TZC_BMX_S23_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S23_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_BMX_S23_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S23_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S23_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S23_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S23_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S23_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S23_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S24_TZSID_EN TZC_NSEC_TZC_BMX_S24_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S24_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_BMX_S24_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S24_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S24_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S24_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S24_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S24_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S24_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S25_TZSID_EN TZC_NSEC_TZC_BMX_S25_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S25_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_BMX_S25_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S25_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S25_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S25_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S25_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S25_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S25_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S26_TZSID_EN TZC_NSEC_TZC_BMX_S26_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S26_TZSID_EN_POS (12U)
+#define TZC_NSEC_TZC_BMX_S26_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S26_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S26_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S26_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S26_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S26_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S26_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S27_TZSID_EN TZC_NSEC_TZC_BMX_S27_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S27_TZSID_EN_POS (14U)
+#define TZC_NSEC_TZC_BMX_S27_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S27_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S27_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S27_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S27_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S27_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S27_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S28_TZSID_EN TZC_NSEC_TZC_BMX_S28_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S28_TZSID_EN_POS (16U)
+#define TZC_NSEC_TZC_BMX_S28_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S28_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S28_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S28_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S28_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S28_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S28_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S29_TZSID_EN TZC_NSEC_TZC_BMX_S29_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S29_TZSID_EN_POS (18U)
+#define TZC_NSEC_TZC_BMX_S29_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S29_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S29_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S29_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S29_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S29_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S29_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_EN TZC_NSEC_TZC_BMX_S2A_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_EN_POS (20U)
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S2A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2A_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2A_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_EN TZC_NSEC_TZC_BMX_S2B_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_EN_POS (22U)
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S2B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2B_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2B_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_EN TZC_NSEC_TZC_BMX_S2C_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_EN_POS (24U)
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S2C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2C_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2C_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_EN TZC_NSEC_TZC_BMX_S2D_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_EN_POS (26U)
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S2D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2D_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2D_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_EN TZC_NSEC_TZC_BMX_S2E_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_EN_POS (28U)
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S2E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2E_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2E_TZSID_EN_POS))
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_EN TZC_NSEC_TZC_BMX_S2F_TZSID_EN
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_EN_POS (30U)
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_BMX_S2F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2F_TZSID_EN_POS)
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_BMX_S2F_TZSID_EN_POS))
+
+/* 0x114 : tzc_bmx_s_lock */
+#define TZC_NSEC_TZC_BMX_S_LOCK_OFFSET (0x114)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_LOCK TZC_NSEC_TZC_BMX_S10_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S10_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S11_TZSID_LOCK TZC_NSEC_TZC_BMX_S11_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S11_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S12_TZSID_LOCK TZC_NSEC_TZC_BMX_S12_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S12_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S13_TZSID_LOCK TZC_NSEC_TZC_BMX_S13_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S13_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S14_TZSID_LOCK TZC_NSEC_TZC_BMX_S14_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_POS (4U)
+#define TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S14_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S15_TZSID_LOCK TZC_NSEC_TZC_BMX_S15_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S15_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S16_TZSID_LOCK TZC_NSEC_TZC_BMX_S16_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_POS (6U)
+#define TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S16_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S17_TZSID_LOCK TZC_NSEC_TZC_BMX_S17_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_POS (7U)
+#define TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S17_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S18_TZSID_LOCK TZC_NSEC_TZC_BMX_S18_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_POS (8U)
+#define TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S18_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S19_TZSID_LOCK TZC_NSEC_TZC_BMX_S19_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_POS (9U)
+#define TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S19_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_POS (10U)
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1A_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_POS (11U)
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1B_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_POS (12U)
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1C_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_POS (13U)
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1D_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_POS (14U)
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1E_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_POS (15U)
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S1F_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S20_TZSID_LOCK TZC_NSEC_TZC_BMX_S20_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_POS (16U)
+#define TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S20_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S21_TZSID_LOCK TZC_NSEC_TZC_BMX_S21_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_POS (17U)
+#define TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S21_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S22_TZSID_LOCK TZC_NSEC_TZC_BMX_S22_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_POS (18U)
+#define TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S22_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S23_TZSID_LOCK TZC_NSEC_TZC_BMX_S23_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_POS (19U)
+#define TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S23_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S24_TZSID_LOCK TZC_NSEC_TZC_BMX_S24_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_POS (20U)
+#define TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S24_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S25_TZSID_LOCK TZC_NSEC_TZC_BMX_S25_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_POS (21U)
+#define TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S25_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S26_TZSID_LOCK TZC_NSEC_TZC_BMX_S26_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_POS (22U)
+#define TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S26_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S27_TZSID_LOCK TZC_NSEC_TZC_BMX_S27_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_POS (23U)
+#define TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S27_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S28_TZSID_LOCK TZC_NSEC_TZC_BMX_S28_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_POS (24U)
+#define TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S28_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S29_TZSID_LOCK TZC_NSEC_TZC_BMX_S29_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_POS (25U)
+#define TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S29_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_POS (26U)
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2A_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_POS (27U)
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2B_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_POS (28U)
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2C_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_POS (29U)
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2D_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_POS (30U)
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2E_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_POS (31U)
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BMX_S2F_TZSID_LOCK_POS))
+
+/* 0x140 : tzc_ocram_tzsrg_ctrl */
+#define TZC_NSEC_TZC_OCRAM_TZSRG_CTRL_OFFSET (0x140)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_POS (8U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_POS (12U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_RX_ID_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_POS (19U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_RX_EN_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_POS (20U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_POS (21U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_POS (22U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_LOCK_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_POS (23U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_RX_LOCK_POS))
+
+/* 0x144 : tzc_ocram_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_OFFSET (0x144)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x148 : tzc_ocram_tzsrg_r0 */
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_OFFSET (0x148)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_END TZC_NSEC_TZC_OCRAM_TZSRG_R0_END
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_START TZC_NSEC_TZC_OCRAM_TZSRG_R0_START
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R0_START_POS))
+
+/* 0x14C : tzc_ocram_tzsrg_r1 */
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_OFFSET (0x14C)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_END TZC_NSEC_TZC_OCRAM_TZSRG_R1_END
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_START TZC_NSEC_TZC_OCRAM_TZSRG_R1_START
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R1_START_POS))
+
+/* 0x150 : tzc_ocram_tzsrg_r2 */
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_OFFSET (0x150)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_END TZC_NSEC_TZC_OCRAM_TZSRG_R2_END
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_START TZC_NSEC_TZC_OCRAM_TZSRG_R2_START
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_OCRAM_TZSRG_R2_START_POS))
+
+/* 0x154 : tzc_ocram_tzsrg_r3 */
+#define TZC_NSEC_TZC_OCRAM_TZSRG_R3_OFFSET (0x154)
+
+/* 0x180 : tzc_wram_tzsrg_ctrl */
+#define TZC_NSEC_TZC_WRAM_TZSRG_CTRL_OFFSET (0x180)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_POS (8U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_POS (12U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_RX_ID_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_EN TZC_NSEC_TZC_WRAM_TZSRG_R0_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_EN TZC_NSEC_TZC_WRAM_TZSRG_R1_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_EN TZC_NSEC_TZC_WRAM_TZSRG_R2_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_EN TZC_NSEC_TZC_WRAM_TZSRG_RX_EN
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_POS (19U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_RX_EN_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_POS (20U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_POS (21U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_POS (22U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_LOCK_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_POS (23U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_RX_LOCK_POS))
+
+/* 0x184 : tzc_wram_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_OFFSET (0x184)
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x188 : tzc_wram_tzsrg_r0 */
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_OFFSET (0x188)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_END TZC_NSEC_TZC_WRAM_TZSRG_R0_END
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_START TZC_NSEC_TZC_WRAM_TZSRG_R0_START
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R0_START_POS))
+
+/* 0x18C : tzc_wram_tzsrg_r1 */
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_OFFSET (0x18C)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_END TZC_NSEC_TZC_WRAM_TZSRG_R1_END
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_START TZC_NSEC_TZC_WRAM_TZSRG_R1_START
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R1_START_POS))
+
+/* 0x190 : tzc_wram_tzsrg_r2 */
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_OFFSET (0x190)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_END TZC_NSEC_TZC_WRAM_TZSRG_R2_END
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_START TZC_NSEC_TZC_WRAM_TZSRG_R2_START
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_WRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_WRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_WRAM_TZSRG_R2_START_POS))
+
+/* 0x194 : tzc_wram_tzsrg_r3 */
+#define TZC_NSEC_TZC_WRAM_TZSRG_R3_OFFSET (0x194)
+
+/* 0x198 : tzc_wifi_dbg */
+#define TZC_NSEC_TZC_WIFI_DBG_OFFSET (0x198)
+#define TZC_NSEC_TZC_MAC_DBG_DIS TZC_NSEC_TZC_MAC_DBG_DIS
+#define TZC_NSEC_TZC_MAC_DBG_DIS_POS (0U)
+#define TZC_NSEC_TZC_MAC_DBG_DIS_LEN (1U)
+#define TZC_NSEC_TZC_MAC_DBG_DIS_MSK (((1U << TZC_NSEC_TZC_MAC_DBG_DIS_LEN) - 1) << TZC_NSEC_TZC_MAC_DBG_DIS_POS)
+#define TZC_NSEC_TZC_MAC_DBG_DIS_UMSK (~(((1U << TZC_NSEC_TZC_MAC_DBG_DIS_LEN) - 1) << TZC_NSEC_TZC_MAC_DBG_DIS_POS))
+
+/* 0x240 : tzc_pdm_ctrl */
+#define TZC_NSEC_TZC_PDM_CTRL_OFFSET (0x240)
+
+/* 0x244 : tzc_uart_ctrl */
+#define TZC_NSEC_TZC_UART_CTRL_OFFSET (0x244)
+
+/* 0x248 : tzc_i2c_ctrl */
+#define TZC_NSEC_TZC_I2C_CTRL_OFFSET (0x248)
+
+/* 0x24C : tzc_timer_ctrl */
+#define TZC_NSEC_TZC_TIMER_CTRL_OFFSET (0x24C)
+
+/* 0x250 : tzc_i2s_ctrl */
+#define TZC_NSEC_TZC_I2S_CTRL_OFFSET (0x250)
+
+/* 0x280 : tzc_sf_tzsrg_ctrl */
+#define TZC_NSEC_TZC_SF_TZSRG_CTRL_OFFSET (0x280)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_POS (8U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_POS (12U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_ID_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN
+#define TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_POS (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_LEN (4U)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_RX_ID_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R0_EN TZC_NSEC_TZC_SF_TZSRG_R0_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R0_EN_POS (20U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R1_EN TZC_NSEC_TZC_SF_TZSRG_R1_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R1_EN_POS (21U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R2_EN TZC_NSEC_TZC_SF_TZSRG_R2_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R2_EN_POS (22U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R3_EN TZC_NSEC_TZC_SF_TZSRG_R3_EN
+#define TZC_NSEC_TZC_SF_TZSRG_R3_EN_POS (23U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_EN_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R3_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R3_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_RX_EN TZC_NSEC_TZC_SF_TZSRG_RX_EN
+#define TZC_NSEC_TZC_SF_TZSRG_RX_EN_POS (24U)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_EN_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_EN_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_RX_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_RX_EN_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_RX_EN_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_RX_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R0_LOCK TZC_NSEC_TZC_SF_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_POS (25U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R1_LOCK TZC_NSEC_TZC_SF_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_POS (26U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R2_LOCK TZC_NSEC_TZC_SF_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_POS (27U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_LOCK_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R3_LOCK TZC_NSEC_TZC_SF_TZSRG_R3_LOCK
+#define TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_POS (28U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_LOCK_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_RX_LOCK TZC_NSEC_TZC_SF_TZSRG_RX_LOCK
+#define TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_POS (29U)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_RX_LOCK_POS))
+
+/* 0x284 : tzc_sf_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_OFFSET (0x284)
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK TZC_NSEC_TZC_SF_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LEN (19U)
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_POS (31U)
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x288 : tzc_sf_tzsrg_r0 */
+#define TZC_NSEC_TZC_SF_TZSRG_R0_OFFSET (0x288)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END TZC_NSEC_TZC_SF_TZSRG_R0_END
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START TZC_NSEC_TZC_SF_TZSRG_R0_START
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_START_POS))
+
+/* 0x28C : tzc_sf_tzsrg_r1 */
+#define TZC_NSEC_TZC_SF_TZSRG_R1_OFFSET (0x28C)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END TZC_NSEC_TZC_SF_TZSRG_R1_END
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START TZC_NSEC_TZC_SF_TZSRG_R1_START
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_START_POS))
+
+/* 0x290 : tzc_sf_tzsrg_r2 */
+#define TZC_NSEC_TZC_SF_TZSRG_R2_OFFSET (0x290)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END TZC_NSEC_TZC_SF_TZSRG_R2_END
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START TZC_NSEC_TZC_SF_TZSRG_R2_START
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_START_POS))
+
+/* 0x294 : tzc_sf_tzsrg_r3 */
+#define TZC_NSEC_TZC_SF_TZSRG_R3_OFFSET (0x294)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END TZC_NSEC_TZC_SF_TZSRG_R3_END
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_POS (0U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R3_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_END_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R3_END_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_END_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START TZC_NSEC_TZC_SF_TZSRG_R3_START
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_POS (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_LEN (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R3_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_START_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R3_START_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_START_POS))
+
+/* 0x298 : tzc_sf_tzsrg_msb */
+#define TZC_NSEC_TZC_SF_TZSRG_MSB_OFFSET (0x298)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_POS (0U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_END_MSB_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_POS (4U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R0_START_MSB_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_POS (8U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_END_MSB_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_POS (12U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R1_START_MSB_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_POS (16U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_END_MSB_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_POS (20U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R2_START_MSB_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_POS (24U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_END_MSB_POS))
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_POS (28U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_LEN (3U)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_MSK (((1U << TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_POS)
+#define TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_LEN) - 1) << TZC_NSEC_TZC_SF_TZSRG_R3_START_MSB_POS))
+
+/* 0x300 : tzc_mm_bmx_tzmid */
+#define TZC_NSEC_TZC_MM_BMX_TZMID_OFFSET (0x300)
+#define TZC_NSEC_TZC_MMCPU_TZMID TZC_NSEC_TZC_MMCPU_TZMID
+#define TZC_NSEC_TZC_MMCPU_TZMID_POS (0U)
+#define TZC_NSEC_TZC_MMCPU_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_MMCPU_TZMID_MSK (((1U << TZC_NSEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_NSEC_TZC_MMCPU_TZMID_POS)
+#define TZC_NSEC_TZC_MMCPU_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_NSEC_TZC_MMCPU_TZMID_POS))
+#define TZC_NSEC_TZC_BLAI_TZMID TZC_NSEC_TZC_BLAI_TZMID
+#define TZC_NSEC_TZC_BLAI_TZMID_POS (1U)
+#define TZC_NSEC_TZC_BLAI_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_BLAI_TZMID_MSK (((1U << TZC_NSEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_NSEC_TZC_BLAI_TZMID_POS)
+#define TZC_NSEC_TZC_BLAI_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_NSEC_TZC_BLAI_TZMID_POS))
+#define TZC_NSEC_TZC_CODEC_TZMID TZC_NSEC_TZC_CODEC_TZMID
+#define TZC_NSEC_TZC_CODEC_TZMID_POS (2U)
+#define TZC_NSEC_TZC_CODEC_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_TZMID_MSK (((1U << TZC_NSEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_POS)
+#define TZC_NSEC_TZC_CODEC_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_POS))
+#define TZC_NSEC_TZC_SUBSYS_TZMID TZC_NSEC_TZC_SUBSYS_TZMID
+#define TZC_NSEC_TZC_SUBSYS_TZMID_POS (3U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_MSK (((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_POS)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_POS))
+#define TZC_NSEC_TZC_X2DDMA_TZMID TZC_NSEC_TZC_X2DDMA_TZMID
+#define TZC_NSEC_TZC_X2DDMA_TZMID_POS (4U)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_MSK (((1U << TZC_NSEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_NSEC_TZC_X2DDMA_TZMID_POS)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_NSEC_TZC_X2DDMA_TZMID_POS))
+#define TZC_NSEC_TZC_XDMA_TZMID TZC_NSEC_TZC_XDMA_TZMID
+#define TZC_NSEC_TZC_XDMA_TZMID_POS (5U)
+#define TZC_NSEC_TZC_XDMA_TZMID_LEN (1U)
+#define TZC_NSEC_TZC_XDMA_TZMID_MSK (((1U << TZC_NSEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_NSEC_TZC_XDMA_TZMID_POS)
+#define TZC_NSEC_TZC_XDMA_TZMID_UMSK (~(((1U << TZC_NSEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_NSEC_TZC_XDMA_TZMID_POS))
+#define TZC_NSEC_TZC_MMCPU_TZMID_SEL TZC_NSEC_TZC_MMCPU_TZMID_SEL
+#define TZC_NSEC_TZC_MMCPU_TZMID_SEL_POS (16U)
+#define TZC_NSEC_TZC_MMCPU_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_MMCPU_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_MMCPU_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_MMCPU_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_MMCPU_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_BLAI_TZMID_SEL TZC_NSEC_TZC_BLAI_TZMID_SEL
+#define TZC_NSEC_TZC_BLAI_TZMID_SEL_POS (17U)
+#define TZC_NSEC_TZC_BLAI_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_BLAI_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_BLAI_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_BLAI_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_BLAI_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_CODEC_TZMID_SEL TZC_NSEC_TZC_CODEC_TZMID_SEL
+#define TZC_NSEC_TZC_CODEC_TZMID_SEL_POS (18U)
+#define TZC_NSEC_TZC_CODEC_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_CODEC_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL TZC_NSEC_TZC_SUBSYS_TZMID_SEL
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_POS (19U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_X2DDMA_TZMID_SEL TZC_NSEC_TZC_X2DDMA_TZMID_SEL
+#define TZC_NSEC_TZC_X2DDMA_TZMID_SEL_POS (20U)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_X2DDMA_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_X2DDMA_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_XDMA_TZMID_SEL TZC_NSEC_TZC_XDMA_TZMID_SEL
+#define TZC_NSEC_TZC_XDMA_TZMID_SEL_POS (21U)
+#define TZC_NSEC_TZC_XDMA_TZMID_SEL_LEN (1U)
+#define TZC_NSEC_TZC_XDMA_TZMID_SEL_MSK (((1U << TZC_NSEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_XDMA_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_XDMA_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_XDMA_TZMID_SEL_POS))
+
+/* 0x304 : tzc_mm_bmx_tzmid_lock */
+#define TZC_NSEC_TZC_MM_BMX_TZMID_LOCK_OFFSET (0x304)
+#define TZC_NSEC_TZC_MMCPU_TZMID_LOCK TZC_NSEC_TZC_MMCPU_TZMID_LOCK
+#define TZC_NSEC_TZC_MMCPU_TZMID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_MMCPU_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMCPU_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMCPU_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_MMCPU_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMCPU_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_BLAI_TZMID_LOCK TZC_NSEC_TZC_BLAI_TZMID_LOCK
+#define TZC_NSEC_TZC_BLAI_TZMID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_BLAI_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_BLAI_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BLAI_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_BLAI_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_BLAI_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_TZMID_LOCK TZC_NSEC_TZC_CODEC_TZMID_LOCK
+#define TZC_NSEC_TZC_CODEC_TZMID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_CODEC_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK TZC_NSEC_TZC_SUBSYS_TZMID_LOCK
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK TZC_NSEC_TZC_X2DDMA_TZMID_LOCK
+#define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_POS (4U)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_XDMA_TZMID_LOCK TZC_NSEC_TZC_XDMA_TZMID_LOCK
+#define TZC_NSEC_TZC_XDMA_TZMID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_XDMA_TZMID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_XDMA_TZMID_LOCK_MSK (((1U << TZC_NSEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_XDMA_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_XDMA_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_XDMA_TZMID_LOCK_POS))
+
+/* 0x308 : tzc_mm_bmx_s0 */
+#define TZC_NSEC_TZC_MM_BMX_S0_OFFSET (0x308)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_EN TZC_NSEC_TZC_MMPERI_S10_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S10_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_EN TZC_NSEC_TZC_MMPERI_S11_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S11_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_EN TZC_NSEC_TZC_MMPERI_S12_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S12_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_EN TZC_NSEC_TZC_MMPERI_S13_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S13_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_EN TZC_NSEC_TZC_MMPERI_S14_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S14_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_EN TZC_NSEC_TZC_MMPERI_S15_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S15_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_EN TZC_NSEC_TZC_MMPERI_S16_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_POS (12U)
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S16_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_EN TZC_NSEC_TZC_MMPERI_S17_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_POS (14U)
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S17_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_EN TZC_NSEC_TZC_MMPERI_S18_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_POS (16U)
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S18_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_EN TZC_NSEC_TZC_MMPERI_S19_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_POS (18U)
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S19_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_POS (20U)
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1A_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_POS (22U)
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1B_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_POS (24U)
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1C_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_POS (26U)
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1D_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_POS (28U)
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1E_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_POS (30U)
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_POS))
+
+/* 0x30C : tzc_mm_bmx_s1 */
+#define TZC_NSEC_TZC_MM_BMX_S1_OFFSET (0x30C)
+#define TZC_NSEC_TZC_S10_TZSID_EN TZC_NSEC_TZC_S10_TZSID_EN
+#define TZC_NSEC_TZC_S10_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_S10_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S10_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S10_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S11_TZSID_EN TZC_NSEC_TZC_S11_TZSID_EN
+#define TZC_NSEC_TZC_S11_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_S11_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S11_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S11_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S12_TZSID_EN TZC_NSEC_TZC_S12_TZSID_EN
+#define TZC_NSEC_TZC_S12_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_S12_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S12_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S12_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S13_TZSID_EN TZC_NSEC_TZC_S13_TZSID_EN
+#define TZC_NSEC_TZC_S13_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_S13_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S13_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S13_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S14_TZSID_EN TZC_NSEC_TZC_S14_TZSID_EN
+#define TZC_NSEC_TZC_S14_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_S14_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S14_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S14_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S15_TZSID_EN TZC_NSEC_TZC_S15_TZSID_EN
+#define TZC_NSEC_TZC_S15_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_S15_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S15_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S15_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S16_TZSID_EN TZC_NSEC_TZC_S16_TZSID_EN
+#define TZC_NSEC_TZC_S16_TZSID_EN_POS (12U)
+#define TZC_NSEC_TZC_S16_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S16_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S16_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S17_TZSID_EN TZC_NSEC_TZC_S17_TZSID_EN
+#define TZC_NSEC_TZC_S17_TZSID_EN_POS (14U)
+#define TZC_NSEC_TZC_S17_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S17_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S17_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S18_TZSID_EN TZC_NSEC_TZC_S18_TZSID_EN
+#define TZC_NSEC_TZC_S18_TZSID_EN_POS (16U)
+#define TZC_NSEC_TZC_S18_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S18_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S18_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S19_TZSID_EN TZC_NSEC_TZC_S19_TZSID_EN
+#define TZC_NSEC_TZC_S19_TZSID_EN_POS (18U)
+#define TZC_NSEC_TZC_S19_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S19_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S19_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1A_TZSID_EN TZC_NSEC_TZC_S1A_TZSID_EN
+#define TZC_NSEC_TZC_S1A_TZSID_EN_POS (20U)
+#define TZC_NSEC_TZC_S1A_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S1A_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1A_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1B_TZSID_EN TZC_NSEC_TZC_S1B_TZSID_EN
+#define TZC_NSEC_TZC_S1B_TZSID_EN_POS (22U)
+#define TZC_NSEC_TZC_S1B_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S1B_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1B_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1C_TZSID_EN TZC_NSEC_TZC_S1C_TZSID_EN
+#define TZC_NSEC_TZC_S1C_TZSID_EN_POS (24U)
+#define TZC_NSEC_TZC_S1C_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S1C_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1C_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1D_TZSID_EN TZC_NSEC_TZC_S1D_TZSID_EN
+#define TZC_NSEC_TZC_S1D_TZSID_EN_POS (26U)
+#define TZC_NSEC_TZC_S1D_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S1D_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1D_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1E_TZSID_EN TZC_NSEC_TZC_S1E_TZSID_EN
+#define TZC_NSEC_TZC_S1E_TZSID_EN_POS (28U)
+#define TZC_NSEC_TZC_S1E_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S1E_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1E_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1F_TZSID_EN TZC_NSEC_TZC_S1F_TZSID_EN
+#define TZC_NSEC_TZC_S1F_TZSID_EN_POS (30U)
+#define TZC_NSEC_TZC_S1F_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_S1F_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_EN_POS))
+
+/* 0x310 : tzc_mm_bmx_s2 */
+#define TZC_NSEC_TZC_MM_BMX_S2_OFFSET (0x310)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_EN TZC_NSEC_TZC_CODEC_S10_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S10_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S10_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_EN TZC_NSEC_TZC_CODEC_S11_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S11_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S11_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_EN TZC_NSEC_TZC_CODEC_S12_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S12_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S12_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_EN TZC_NSEC_TZC_CODEC_S13_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S13_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S13_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_EN TZC_NSEC_TZC_CODEC_S14_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S14_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S14_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_EN TZC_NSEC_TZC_CODEC_S15_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S15_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S15_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_EN TZC_NSEC_TZC_CODEC_S16_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_EN_POS (12U)
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S16_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S16_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_EN TZC_NSEC_TZC_CODEC_S17_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_EN_POS (14U)
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S17_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S17_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_EN TZC_NSEC_TZC_CODEC_S18_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_EN_POS (16U)
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S18_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S18_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_EN TZC_NSEC_TZC_CODEC_S19_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_EN_POS (18U)
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S19_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S19_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_EN TZC_NSEC_TZC_CODEC_S1A_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_POS (20U)
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1A_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_EN TZC_NSEC_TZC_CODEC_S1B_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_POS (22U)
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1B_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_EN TZC_NSEC_TZC_CODEC_S1C_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_POS (24U)
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1C_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_EN TZC_NSEC_TZC_CODEC_S1D_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_POS (26U)
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1D_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_EN TZC_NSEC_TZC_CODEC_S1E_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_POS (28U)
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1E_TZSID_EN_POS))
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_EN TZC_NSEC_TZC_CODEC_S1F_TZSID_EN
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_POS (30U)
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_POS)
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1F_TZSID_EN_POS))
+
+/* 0x314 : tzc_mm_bmx_s_lock0 */
+#define TZC_NSEC_TZC_MM_BMX_S_LOCK0_OFFSET (0x314)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S10_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S11_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S12_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S13_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_POS (4U)
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S14_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S15_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_POS (6U)
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S16_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_POS (7U)
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S17_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_POS (8U)
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S18_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_POS (9U)
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S19_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_POS (10U)
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1A_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_POS (11U)
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1B_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_POS (12U)
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1C_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_POS (13U)
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1D_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_POS (14U)
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1E_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_POS (15U)
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1F_TZSID_LOCK_POS))
+
+/* 0x318 : tzc_mm_bmx_s_lock1 */
+#define TZC_NSEC_TZC_MM_BMX_S_LOCK1_OFFSET (0x318)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S10_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S11_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S12_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S13_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_POS (4U)
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S14_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S15_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_POS (6U)
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S16_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_POS (7U)
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S17_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_POS (8U)
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S18_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_POS (9U)
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S19_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_POS (10U)
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1A_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_POS (11U)
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1B_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_POS (12U)
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1C_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_POS (13U)
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1D_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_POS (14U)
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1E_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_POS (15U)
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S10_TZSID_LOCK TZC_NSEC_TZC_S10_TZSID_LOCK
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_POS (16U)
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S11_TZSID_LOCK TZC_NSEC_TZC_S11_TZSID_LOCK
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_POS (17U)
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S12_TZSID_LOCK TZC_NSEC_TZC_S12_TZSID_LOCK
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_POS (18U)
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S13_TZSID_LOCK TZC_NSEC_TZC_S13_TZSID_LOCK
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_POS (19U)
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S14_TZSID_LOCK TZC_NSEC_TZC_S14_TZSID_LOCK
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_POS (20U)
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S15_TZSID_LOCK TZC_NSEC_TZC_S15_TZSID_LOCK
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_POS (21U)
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S16_TZSID_LOCK TZC_NSEC_TZC_S16_TZSID_LOCK
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_POS (22U)
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S17_TZSID_LOCK TZC_NSEC_TZC_S17_TZSID_LOCK
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_POS (23U)
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S18_TZSID_LOCK TZC_NSEC_TZC_S18_TZSID_LOCK
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_POS (24U)
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S19_TZSID_LOCK TZC_NSEC_TZC_S19_TZSID_LOCK
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_POS (25U)
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK TZC_NSEC_TZC_S1A_TZSID_LOCK
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_POS (26U)
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK TZC_NSEC_TZC_S1B_TZSID_LOCK
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_POS (27U)
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK TZC_NSEC_TZC_S1C_TZSID_LOCK
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_POS (28U)
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK TZC_NSEC_TZC_S1D_TZSID_LOCK
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_POS (29U)
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK TZC_NSEC_TZC_S1E_TZSID_LOCK
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_POS (30U)
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK TZC_NSEC_TZC_S1F_TZSID_LOCK
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_POS (31U)
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_LOCK_POS))
+
+/* 0x340 : tzc_l2sram_tzsrg_ctrl */
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_CTRL_OFFSET (0x340)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_LOCK_POS))
+
+/* 0x344 : tzc_l2sram_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_OFFSET (0x344)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x348 : tzc_l2sram_tzsrg_r0 */
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_OFFSET (0x348)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R0_START_POS))
+
+/* 0x34C : tzc_l2sram_tzsrg_r1 */
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_OFFSET (0x34C)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R1_START_POS))
+
+/* 0x350 : tzc_l2sram_tzsrg_r2 */
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_OFFSET (0x350)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_L2SRAM_TZSRG_R2_START_POS))
+
+/* 0x354 : tzc_l2sram_tzsrg_r3 */
+#define TZC_NSEC_TZC_L2SRAM_TZSRG_R3_OFFSET (0x354)
+
+/* 0x360 : tzc_vram_tzsrg_ctrl */
+#define TZC_NSEC_TZC_VRAM_TZSRG_CTRL_OFFSET (0x360)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_EN TZC_NSEC_TZC_VRAM_TZSRG_R0_EN
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_EN TZC_NSEC_TZC_VRAM_TZSRG_R1_EN
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_EN TZC_NSEC_TZC_VRAM_TZSRG_R2_EN
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_LOCK_POS))
+
+/* 0x364 : tzc_vram_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_OFFSET (0x364)
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x368 : tzc_vram_tzsrg_r0 */
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_OFFSET (0x368)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_END TZC_NSEC_TZC_VRAM_TZSRG_R0_END
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_START TZC_NSEC_TZC_VRAM_TZSRG_R0_START
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R0_START_POS))
+
+/* 0x36C : tzc_vram_tzsrg_r1 */
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_OFFSET (0x36C)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_END TZC_NSEC_TZC_VRAM_TZSRG_R1_END
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_START TZC_NSEC_TZC_VRAM_TZSRG_R1_START
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R1_START_POS))
+
+/* 0x370 : tzc_vram_tzsrg_r2 */
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_OFFSET (0x370)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_END TZC_NSEC_TZC_VRAM_TZSRG_R2_END
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_START TZC_NSEC_TZC_VRAM_TZSRG_R2_START
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_VRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_VRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_VRAM_TZSRG_R2_START_POS))
+
+/* 0x374 : tzc_vram_tzsrg_r3 */
+#define TZC_NSEC_TZC_VRAM_TZSRG_R3_OFFSET (0x374)
+
+/* 0x380 : tzc_psrama_tzsrg_ctrl */
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_CTRL_OFFSET (0x380)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_POS (24U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_POS (25U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_POS (26U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_LOCK_POS))
+
+/* 0x384 : tzc_psrama_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_OFFSET (0x384)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x388 : tzc_psrama_tzsrg_r0 */
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_OFFSET (0x388)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R0_START_POS))
+
+/* 0x38C : tzc_psrama_tzsrg_r1 */
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_OFFSET (0x38C)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R1_START_POS))
+
+/* 0x390 : tzc_psrama_tzsrg_r2 */
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_OFFSET (0x390)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMA_TZSRG_R2_START_POS))
+
+/* 0x394 : tzc_psrama_tzsrg_r3 */
+#define TZC_NSEC_TZC_PSRAMA_TZSRG_R3_OFFSET (0x394)
+
+/* 0x3a0 : tzc_psramb_tzsrg_ctrl */
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_CTRL_OFFSET (0x3a0)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_POS (24U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_POS (25U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_POS (26U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_LOCK_POS))
+
+/* 0x3A4 : tzc_psramb_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_OFFSET (0x3A4)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x3A8 : tzc_psramb_tzsrg_r0 */
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_OFFSET (0x3A8)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R0_START_POS))
+
+/* 0x3AC : tzc_psramb_tzsrg_r1 */
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_OFFSET (0x3AC)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R1_START_POS))
+
+/* 0x3B0 : tzc_psramb_tzsrg_r2 */
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_OFFSET (0x3B0)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_LEN (16U)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_PSRAMB_TZSRG_R2_START_POS))
+
+/* 0x3B4 : tzc_psramb_tzsrg_r3 */
+#define TZC_NSEC_TZC_PSRAMB_TZSRG_R3_OFFSET (0x3B4)
+
+/* 0x3c0 : tzc_xram_tzsrg_ctrl */
+#define TZC_NSEC_TZC_XRAM_TZSRG_CTRL_OFFSET (0x3c0)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_EN TZC_NSEC_TZC_XRAM_TZSRG_R0_EN
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_EN_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_EN TZC_NSEC_TZC_XRAM_TZSRG_R1_EN
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_EN_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_EN TZC_NSEC_TZC_XRAM_TZSRG_R2_EN
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_EN_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_LOCK_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_LOCK_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_LOCK_POS))
+
+/* 0x3C4 : tzc_xram_tzsrg_adr_mask */
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_OFFSET (0x3C4)
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x3C8 : tzc_xram_tzsrg_r0 */
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_OFFSET (0x3C8)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_END TZC_NSEC_TZC_XRAM_TZSRG_R0_END
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_END_POS (0U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_END_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_END_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_END_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_END_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_START TZC_NSEC_TZC_XRAM_TZSRG_R0_START
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_START_POS (16U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_START_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_START_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R0_START_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R0_START_POS))
+
+/* 0x3CC : tzc_xram_tzsrg_r1 */
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_OFFSET (0x3CC)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_END TZC_NSEC_TZC_XRAM_TZSRG_R1_END
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_END_POS (0U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_END_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_END_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_END_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_END_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_START TZC_NSEC_TZC_XRAM_TZSRG_R1_START
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_START_POS (16U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_START_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_START_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R1_START_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R1_START_POS))
+
+/* 0x3D0 : tzc_xram_tzsrg_r2 */
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_OFFSET (0x3D0)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_END TZC_NSEC_TZC_XRAM_TZSRG_R2_END
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_END_POS (0U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_END_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_END_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_END_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_END_POS))
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_START TZC_NSEC_TZC_XRAM_TZSRG_R2_START
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_START_POS (16U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_START_MSK (((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_START_POS)
+#define TZC_NSEC_TZC_XRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_NSEC_TZC_XRAM_TZSRG_R2_START_LEN) - 1) << TZC_NSEC_TZC_XRAM_TZSRG_R2_START_POS))
+
+/* 0x3D4 : tzc_xram_tzsrg_r3 */
+#define TZC_NSEC_TZC_XRAM_TZSRG_R3_OFFSET (0x3D4)
+
+/* 0xF00 : tzc_glb_ctrl_0 */
+#define TZC_NSEC_TZC_GLB_CTRL_0_OFFSET (0xF00)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_EN TZC_NSEC_TZC_GLB_MISC_TZSID_EN
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_MISC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_MISC_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_MISC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_MISC_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_EN TZC_NSEC_TZC_GLB_SRAM_TZSID_EN
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_SRAM_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_EN TZC_NSEC_TZC_GLB_SWRST_TZSID_EN
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_POS (12U)
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_SWRST_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_EN TZC_NSEC_TZC_GLB_BMX_TZSID_EN
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_EN_POS (14U)
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_BMX_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_BMX_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_BMX_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_BMX_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_EN TZC_NSEC_TZC_GLB_DBG_TZSID_EN
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_EN_POS (16U)
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_DBG_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_DBG_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_DBG_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_DBG_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_EN TZC_NSEC_TZC_GLB_MBIST_TZSID_EN
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_POS (18U)
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_MBIST_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_EN TZC_NSEC_TZC_GLB_CLK_TZSID_EN
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_EN_POS (20U)
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_CLK_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_CLK_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_CLK_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_CLK_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_INT_TZSID_EN TZC_NSEC_TZC_GLB_INT_TZSID_EN
+#define TZC_NSEC_TZC_GLB_INT_TZSID_EN_POS (22U)
+#define TZC_NSEC_TZC_GLB_INT_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_INT_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_INT_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_INT_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_INT_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_INT_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_INT_TZSID_EN_POS))
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_EN TZC_NSEC_TZC_GLB_PWR_TZSID_EN
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_EN_POS (24U)
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_GLB_PWR_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_PWR_TZSID_EN_POS)
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_GLB_PWR_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_GLB_PWR_TZSID_EN_POS))
+
+/* 0xF04 : tzc_glb_ctrl_1 */
+#define TZC_NSEC_TZC_GLB_CTRL_1_OFFSET (0xF04)
+
+/* 0xF08 : tzc_glb_ctrl_2 */
+#define TZC_NSEC_TZC_GLB_CTRL_2_OFFSET (0xF08)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_PWRON_RST_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU_RESET_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_SYS_RESET_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_POS (4U)
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_MISC_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_SRAM_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_POS (6U)
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_SWRST_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_POS (7U)
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_BMX_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_POS (8U)
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_DBG_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_POS (9U)
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_MBIST_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_POS (10U)
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_CLK_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_INT_TZSID_LOCK TZC_NSEC_TZC_GLB_INT_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_POS (11U)
+#define TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_INT_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_POS (12U)
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_GLB_PWR_TZSID_LOCK_POS))
+
+/* 0xF20 : tzc_mm_ctrl_0 */
+#define TZC_NSEC_TZC_MM_CTRL_0_OFFSET (0xF20)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_EN TZC_NSEC_TZC_MM_CPU0_TZSID_EN
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MM_CPU0_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MM_CPU0_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_EN TZC_NSEC_TZC_MM_SRAM_TZSID_EN
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MM_SRAM_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_SRAM_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MM_SRAM_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_SRAM_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_EN TZC_NSEC_TZC_MM_SWRST_TZSID_EN
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_EN_POS (12U)
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MM_SWRST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_SWRST_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MM_SWRST_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_SWRST_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MM_CLK_TZSID_EN TZC_NSEC_TZC_MM_CLK_TZSID_EN
+#define TZC_NSEC_TZC_MM_CLK_TZSID_EN_POS (20U)
+#define TZC_NSEC_TZC_MM_CLK_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_MM_CLK_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_MM_CLK_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_CLK_TZSID_EN_POS)
+#define TZC_NSEC_TZC_MM_CLK_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MM_CLK_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MM_CLK_TZSID_EN_POS))
+
+/* 0xF24 : tzc_mm_ctrl_1 */
+#define TZC_NSEC_TZC_MM_CTRL_1_OFFSET (0xF24)
+
+/* 0xF28 : tzc_mm_ctrl_2 */
+#define TZC_NSEC_TZC_MM_CTRL_2_OFFSET (0xF28)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_PWRON_RST_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_RESET_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_SYS_RESET_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_CPU0_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_SRAM_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_POS (6U)
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_SWRST_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_MM_CLK_TZSID_LOCK TZC_NSEC_TZC_MM_CLK_TZSID_LOCK
+#define TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_POS (10U)
+#define TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_MM_CLK_TZSID_LOCK_POS))
+
+/* 0xF40 : tzc_se_ctrl_0 */
+#define TZC_NSEC_TZC_SE_CTRL_0_OFFSET (0xF40)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_EN TZC_NSEC_TZC_SE_SHA_TZSID_EN
+#define TZC_NSEC_TZC_SE_SHA_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SE_SHA_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_SHA_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SE_SHA_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_SHA_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SE_AES_TZSID_EN TZC_NSEC_TZC_SE_AES_TZSID_EN
+#define TZC_NSEC_TZC_SE_AES_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_SE_AES_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SE_AES_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SE_AES_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_AES_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SE_AES_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SE_AES_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_AES_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_EN TZC_NSEC_TZC_SE_TRNG_TZSID_EN
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_EN_POS (4U)
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SE_TRNG_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_TRNG_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SE_TRNG_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_TRNG_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SE_PKA_TZSID_EN TZC_NSEC_TZC_SE_PKA_TZSID_EN
+#define TZC_NSEC_TZC_SE_PKA_TZSID_EN_POS (6U)
+#define TZC_NSEC_TZC_SE_PKA_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SE_PKA_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SE_PKA_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_PKA_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SE_PKA_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SE_PKA_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_PKA_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SE_CDET_TZSID_EN TZC_NSEC_TZC_SE_CDET_TZSID_EN
+#define TZC_NSEC_TZC_SE_CDET_TZSID_EN_POS (8U)
+#define TZC_NSEC_TZC_SE_CDET_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SE_CDET_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SE_CDET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_CDET_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SE_CDET_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SE_CDET_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_CDET_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_EN TZC_NSEC_TZC_SE_GMAC_TZSID_EN
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_EN_POS (10U)
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SE_GMAC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_GMAC_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SE_GMAC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SE_GMAC_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SE_TZSID_CRMD TZC_NSEC_TZC_SE_TZSID_CRMD
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_POS (12U)
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_LEN (1U)
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_MSK (((1U << TZC_NSEC_TZC_SE_TZSID_CRMD_LEN) - 1) << TZC_NSEC_TZC_SE_TZSID_CRMD_POS)
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_UMSK (~(((1U << TZC_NSEC_TZC_SE_TZSID_CRMD_LEN) - 1) << TZC_NSEC_TZC_SE_TZSID_CRMD_POS))
+#define TZC_NSEC_TZC_SE_WDT_DLY TZC_NSEC_TZC_SE_WDT_DLY
+#define TZC_NSEC_TZC_SE_WDT_DLY_POS (16U)
+#define TZC_NSEC_TZC_SE_WDT_DLY_LEN (16U)
+#define TZC_NSEC_TZC_SE_WDT_DLY_MSK (((1U << TZC_NSEC_TZC_SE_WDT_DLY_LEN) - 1) << TZC_NSEC_TZC_SE_WDT_DLY_POS)
+#define TZC_NSEC_TZC_SE_WDT_DLY_UMSK (~(((1U << TZC_NSEC_TZC_SE_WDT_DLY_LEN) - 1) << TZC_NSEC_TZC_SE_WDT_DLY_POS))
+
+/* 0xF44 : tzc_se_ctrl_1 */
+#define TZC_NSEC_TZC_SE_CTRL_1_OFFSET (0xF44)
+#define TZC_NSEC_TZC_SF_CR_TZSID_EN TZC_NSEC_TZC_SF_CR_TZSID_EN
+#define TZC_NSEC_TZC_SF_CR_TZSID_EN_POS (0U)
+#define TZC_NSEC_TZC_SF_CR_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SF_CR_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SF_CR_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_CR_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SF_CR_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_CR_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_CR_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SF_SEC_TZSID_EN TZC_NSEC_TZC_SF_SEC_TZSID_EN
+#define TZC_NSEC_TZC_SF_SEC_TZSID_EN_POS (2U)
+#define TZC_NSEC_TZC_SF_SEC_TZSID_EN_LEN (2U)
+#define TZC_NSEC_TZC_SF_SEC_TZSID_EN_MSK (((1U << TZC_NSEC_TZC_SF_SEC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_SEC_TZSID_EN_POS)
+#define TZC_NSEC_TZC_SF_SEC_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_SF_SEC_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_SF_SEC_TZSID_EN_POS))
+#define TZC_NSEC_TZC_SF_TZSID_CRMD TZC_NSEC_TZC_SF_TZSID_CRMD
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_POS (4U)
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_MSK (((1U << TZC_NSEC_TZC_SF_TZSID_CRMD_LEN) - 1) << TZC_NSEC_TZC_SF_TZSID_CRMD_POS)
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSID_CRMD_LEN) - 1) << TZC_NSEC_TZC_SF_TZSID_CRMD_POS))
+
+/* 0xF48 : tzc_se_ctrl_2 */
+#define TZC_NSEC_TZC_SE_CTRL_2_OFFSET (0xF48)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_LOCK TZC_NSEC_TZC_SE_SHA_TZSID_LOCK
+#define TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_POS (0U)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_SHA_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SE_AES_TZSID_LOCK TZC_NSEC_TZC_SE_AES_TZSID_LOCK
+#define TZC_NSEC_TZC_SE_AES_TZSID_LOCK_POS (1U)
+#define TZC_NSEC_TZC_SE_AES_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SE_AES_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SE_AES_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_AES_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SE_AES_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SE_AES_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_AES_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_POS (2U)
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_TRNG_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SE_PKA_TZSID_LOCK TZC_NSEC_TZC_SE_PKA_TZSID_LOCK
+#define TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_POS (3U)
+#define TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_PKA_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SE_CDET_TZSID_LOCK TZC_NSEC_TZC_SE_CDET_TZSID_LOCK
+#define TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_POS (4U)
+#define TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_CDET_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_POS (5U)
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_GMAC_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_POS (6U)
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_MSK (((1U << TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_POS)
+#define TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_LEN) - 1) << TZC_NSEC_TZC_SE_TZSID_CRMD_LOCK_POS))
+#define TZC_NSEC_TZC_SF_CR_TZSID_LOCK TZC_NSEC_TZC_SF_CR_TZSID_LOCK
+#define TZC_NSEC_TZC_SF_CR_TZSID_LOCK_POS (16U)
+#define TZC_NSEC_TZC_SF_CR_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_CR_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_CR_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_CR_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SF_CR_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_CR_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_CR_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SF_SEC_TZSID_LOCK TZC_NSEC_TZC_SF_SEC_TZSID_LOCK
+#define TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_POS (17U)
+#define TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_SEC_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_POS (18U)
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_LEN (1U)
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_MSK (((1U << TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_POS)
+#define TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_LEN) - 1) << TZC_NSEC_TZC_SF_TZSID_CRMD_LOCK_POS))
+
+struct tzc_nsec_reg {
+ /* 0x0 reserved */
+ uint8_t RESERVED0x0[64];
+
+ /* 0x40 : tzc_rom_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r0_id_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_rom_tzsrg_r1_id_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_rom_tzsrg_r2_id_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_rom_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_rom_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r0_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_rom_tzsrg_r1_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_rom_tzsrg_r2_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t tzc_sboot_done : 4; /* [31:28], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_ctrl;
+
+ /* 0x44 : tzc_rom_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_adr_mask : 10; /* [ 9: 0], r, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_adr_mask;
+
+ /* 0x48 : tzc_rom_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r0_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r0_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r0;
+
+ /* 0x4C : tzc_rom_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r1_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r1_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r1;
+
+ /* 0x50 : tzc_rom_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r2_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r2_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r2;
+
+ /* 0x54 : tzc_rom_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r3;
+
+ /* 0x58 reserved */
+ uint8_t RESERVED0x58[168];
+
+ /* 0x100 : tzc_bmx_tzmid */
+ union {
+ struct {
+ uint32_t tzc_pico_tzmid : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_mm_tzmid : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_usb_tzmid : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_wifi_tzmid : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_cci_tzmid : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_sdhm_tzmid : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_emacA_tzmid : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_cpu_tzmid : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_dma_tzmid : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_dma2_tzmid : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_lz4_tzmid : 1; /* [ 10], r, 0x0 */
+ uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
+ uint32_t tzc_pico_tzmid_sel : 1; /* [ 16], r, 0x1 */
+ uint32_t tzc_mm_tzmid_sel : 1; /* [ 17], r, 0x1 */
+ uint32_t tzc_usb_tzmid_sel : 1; /* [ 18], r, 0x1 */
+ uint32_t tzc_wifi_tzmid_sel : 1; /* [ 19], r, 0x1 */
+ uint32_t tzc_cci_tzmid_sel : 1; /* [ 20], r, 0x1 */
+ uint32_t tzc_sdhm_tzmid_sel : 1; /* [ 21], r, 0x1 */
+ uint32_t tzc_emacA_tzmid_sel : 1; /* [ 22], r, 0x1 */
+ uint32_t tzc_cpu_tzmid_sel : 1; /* [ 23], r, 0x1 */
+ uint32_t tzc_dma_tzmid_sel : 1; /* [ 24], r, 0x1 */
+ uint32_t tzc_dma2_tzmid_sel : 1; /* [ 25], r, 0x1 */
+ uint32_t tzc_lz4_tzmid_sel : 1; /* [ 26], r, 0x1 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_tzmid;
+
+ /* 0x104 : tzc_bmx_tzmid_lock */
+ union {
+ struct {
+ uint32_t tzc_pico_tzmid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_mm_tzmid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_usb_tzmid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_wifi_tzmid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_cci_tzmid_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_sdhm_tzmid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_emacA_tzmid_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_cpu_tzmid_lock : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_dma_tzmid_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_dma2_tzmid_lock : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_lz4_tzmid_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_tzmid_lock;
+
+ /* 0x108 : tzc_bmx_s0 */
+ union {
+ struct {
+ uint32_t tzc_bmx_mm_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_bmx_dma_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_bmx_dma2_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_bmx_pwr_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_bmx_sdh_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_bmx_emac_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t tzc_bmx_mm_tzsid_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_bmx_dma_tzsid_lock : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_bmx_dma2_tzsid_lock : 1; /* [ 18], r, 0x0 */
+ uint32_t tzc_bmx_pwr_tzsid_lock : 1; /* [ 19], r, 0x0 */
+ uint32_t tzc_bmx_sdh_tzsid_lock : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_bmx_emac_tzsid_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s0;
+
+ /* 0x10C : tzc_bmx_s1 */
+ union {
+ struct {
+ uint32_t tzc_bmx_s10_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_bmx_s11_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_bmx_s12_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_bmx_s13_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_bmx_s14_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_bmx_s15_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_bmx_s16_tzsid_en : 2; /* [13:12], r, 0x3 */
+ uint32_t tzc_bmx_s17_tzsid_en : 2; /* [15:14], r, 0x3 */
+ uint32_t tzc_bmx_s18_tzsid_en : 2; /* [17:16], r, 0x3 */
+ uint32_t tzc_bmx_s19_tzsid_en : 2; /* [19:18], r, 0x3 */
+ uint32_t tzc_bmx_s1a_tzsid_en : 2; /* [21:20], r, 0x3 */
+ uint32_t tzc_bmx_s1b_tzsid_en : 2; /* [23:22], r, 0x3 */
+ uint32_t tzc_bmx_s1c_tzsid_en : 2; /* [25:24], r, 0x3 */
+ uint32_t tzc_bmx_s1d_tzsid_en : 2; /* [27:26], r, 0x3 */
+ uint32_t tzc_bmx_s1e_tzsid_en : 2; /* [29:28], r, 0x3 */
+ uint32_t tzc_bmx_s1f_tzsid_en : 2; /* [31:30], r, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s1;
+
+ /* 0x110 : tzc_bmx_s2 */
+ union {
+ struct {
+ uint32_t tzc_bmx_s20_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_bmx_s21_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_bmx_s22_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_bmx_s23_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_bmx_s24_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_bmx_s25_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_bmx_s26_tzsid_en : 2; /* [13:12], r, 0x3 */
+ uint32_t tzc_bmx_s27_tzsid_en : 2; /* [15:14], r, 0x3 */
+ uint32_t tzc_bmx_s28_tzsid_en : 2; /* [17:16], r, 0x3 */
+ uint32_t tzc_bmx_s29_tzsid_en : 2; /* [19:18], r, 0x3 */
+ uint32_t tzc_bmx_s2a_tzsid_en : 2; /* [21:20], r, 0x3 */
+ uint32_t tzc_bmx_s2b_tzsid_en : 2; /* [23:22], r, 0x3 */
+ uint32_t tzc_bmx_s2c_tzsid_en : 2; /* [25:24], r, 0x3 */
+ uint32_t tzc_bmx_s2d_tzsid_en : 2; /* [27:26], r, 0x3 */
+ uint32_t tzc_bmx_s2e_tzsid_en : 2; /* [29:28], r, 0x3 */
+ uint32_t tzc_bmx_s2f_tzsid_en : 2; /* [31:30], r, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s2;
+
+ /* 0x114 : tzc_bmx_s_lock */
+ union {
+ struct {
+ uint32_t tzc_bmx_s10_tzsid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_bmx_s11_tzsid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_bmx_s12_tzsid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_bmx_s13_tzsid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_bmx_s14_tzsid_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_bmx_s15_tzsid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_bmx_s16_tzsid_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_bmx_s17_tzsid_lock : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_bmx_s18_tzsid_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_bmx_s19_tzsid_lock : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_bmx_s1a_tzsid_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t tzc_bmx_s1b_tzsid_lock : 1; /* [ 11], r, 0x0 */
+ uint32_t tzc_bmx_s1c_tzsid_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t tzc_bmx_s1d_tzsid_lock : 1; /* [ 13], r, 0x0 */
+ uint32_t tzc_bmx_s1e_tzsid_lock : 1; /* [ 14], r, 0x0 */
+ uint32_t tzc_bmx_s1f_tzsid_lock : 1; /* [ 15], r, 0x0 */
+ uint32_t tzc_bmx_s20_tzsid_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_bmx_s21_tzsid_lock : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_bmx_s22_tzsid_lock : 1; /* [ 18], r, 0x0 */
+ uint32_t tzc_bmx_s23_tzsid_lock : 1; /* [ 19], r, 0x0 */
+ uint32_t tzc_bmx_s24_tzsid_lock : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_bmx_s25_tzsid_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_bmx_s26_tzsid_lock : 1; /* [ 22], r, 0x0 */
+ uint32_t tzc_bmx_s27_tzsid_lock : 1; /* [ 23], r, 0x0 */
+ uint32_t tzc_bmx_s28_tzsid_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_bmx_s29_tzsid_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_bmx_s2a_tzsid_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t tzc_bmx_s2b_tzsid_lock : 1; /* [ 27], r, 0x0 */
+ uint32_t tzc_bmx_s2c_tzsid_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t tzc_bmx_s2d_tzsid_lock : 1; /* [ 29], r, 0x0 */
+ uint32_t tzc_bmx_s2e_tzsid_lock : 1; /* [ 30], r, 0x0 */
+ uint32_t tzc_bmx_s2f_tzsid_lock : 1; /* [ 31], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s_lock;
+
+ /* 0x118 reserved */
+ uint8_t RESERVED0x118[40];
+
+ /* 0x140 : tzc_ocram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r0_id_en : 4; /* [ 3: 0], r, 0xf */
+ uint32_t tzc_ocram_tzsrg_r1_id_en : 4; /* [ 7: 4], r, 0xf */
+ uint32_t tzc_ocram_tzsrg_r2_id_en : 4; /* [11: 8], r, 0xf */
+ uint32_t tzc_ocram_tzsrg_rx_id_en : 4; /* [15:12], r, 0xf */
+ uint32_t tzc_ocram_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t tzc_ocram_tzsrg_rx_en : 1; /* [ 19], r, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r0_lock : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r1_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r2_lock : 1; /* [ 22], r, 0x0 */
+ uint32_t tzc_ocram_tzsrg_rx_lock : 1; /* [ 23], r, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_ctrl;
+
+ /* 0x144 : tzc_ocram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_adr_mask : 10; /* [ 9: 0], r, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_adr_mask;
+
+ /* 0x148 : tzc_ocram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r0_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r0_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r0;
+
+ /* 0x14C : tzc_ocram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r1_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r1_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r1;
+
+ /* 0x150 : tzc_ocram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r2_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r2_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r2;
+
+ /* 0x154 : tzc_ocram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r3;
+
+ /* 0x158 reserved */
+ uint8_t RESERVED0x158[40];
+
+ /* 0x180 : tzc_wram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r0_id_en : 4; /* [ 3: 0], r, 0xf */
+ uint32_t tzc_wram_tzsrg_r1_id_en : 4; /* [ 7: 4], r, 0xf */
+ uint32_t tzc_wram_tzsrg_r2_id_en : 4; /* [11: 8], r, 0xf */
+ uint32_t tzc_wram_tzsrg_rx_id_en : 4; /* [15:12], r, 0xf */
+ uint32_t tzc_wram_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_wram_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_wram_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t tzc_wram_tzsrg_rx_en : 1; /* [ 19], r, 0x0 */
+ uint32_t tzc_wram_tzsrg_r0_lock : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_wram_tzsrg_r1_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_wram_tzsrg_r2_lock : 1; /* [ 22], r, 0x0 */
+ uint32_t tzc_wram_tzsrg_rx_lock : 1; /* [ 23], r, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_ctrl;
+
+ /* 0x184 : tzc_wram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_adr_mask : 10; /* [ 9: 0], r, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_adr_mask;
+
+ /* 0x188 : tzc_wram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r0_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_r0_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r0;
+
+ /* 0x18C : tzc_wram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r1_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_r1_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r1;
+
+ /* 0x190 : tzc_wram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r2_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_r2_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r2;
+
+ /* 0x194 : tzc_wram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r3;
+
+ /* 0x198 : tzc_wifi_dbg */
+ union {
+ struct {
+ uint32_t tzc_mac_dbg_dis : 1; /* [ 0], r, 0x1 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wifi_dbg;
+
+ /* 0x19c reserved */
+ uint8_t RESERVED0x19c[164];
+
+ /* 0x240 : tzc_pdm_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_pdm_ctrl;
+
+ /* 0x244 : tzc_uart_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_uart_ctrl;
+
+ /* 0x248 : tzc_i2c_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_i2c_ctrl;
+
+ /* 0x24C : tzc_timer_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_timer_ctrl;
+
+ /* 0x250 : tzc_i2s_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_i2s_ctrl;
+
+ /* 0x254 reserved */
+ uint8_t RESERVED0x254[44];
+
+ /* 0x280 : tzc_sf_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r0_id_en : 4; /* [ 3: 0], r, 0xf */
+ uint32_t tzc_sf_tzsrg_r1_id_en : 4; /* [ 7: 4], r, 0xf */
+ uint32_t tzc_sf_tzsrg_r2_id_en : 4; /* [11: 8], r, 0xf */
+ uint32_t tzc_sf_tzsrg_r3_id_en : 4; /* [15:12], r, 0xf */
+ uint32_t tzc_sf_tzsrg_rx_id_en : 4; /* [19:16], r, 0xf */
+ uint32_t tzc_sf_tzsrg_r0_en : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_en : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_en : 1; /* [ 22], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_en : 1; /* [ 23], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_rx_en : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_r0_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_lock : 1; /* [ 27], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t tzc_sf_tzsrg_rx_lock : 1; /* [ 29], r, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_ctrl;
+
+ /* 0x284 : tzc_sf_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_adr_mask : 19; /* [18: 0], r, 0x0 */
+ uint32_t reserved_19_30 : 12; /* [30:19], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_adr_mask_lock : 1; /* [ 31], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_adr_mask;
+
+ /* 0x288 : tzc_sf_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r0_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_sf_tzsrg_r0_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r0;
+
+ /* 0x28C : tzc_sf_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r1_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_sf_tzsrg_r1_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r1;
+
+ /* 0x290 : tzc_sf_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r2_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_sf_tzsrg_r2_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r2;
+
+ /* 0x294 : tzc_sf_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r3_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_sf_tzsrg_r3_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r3;
+
+ /* 0x298 : tzc_sf_tzsrg_msb */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r0_end_msb : 3; /* [ 2: 0], r, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r0_start_msb : 3; /* [ 6: 4], r, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_end_msb : 3; /* [10: 8], r, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_start_msb : 3; /* [14:12], r, 0x0 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_end_msb : 3; /* [18:16], r, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_start_msb : 3; /* [22:20], r, 0x0 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_end_msb : 3; /* [26:24], r, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_start_msb : 3; /* [30:28], r, 0x0 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_msb;
+
+ /* 0x29c reserved */
+ uint8_t RESERVED0x29c[100];
+
+ /* 0x300 : tzc_mm_bmx_tzmid */
+ union {
+ struct {
+ uint32_t tzc_mmcpu_tzmid : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_blai_tzmid : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_codec_tzmid : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_subsys_tzmid : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_x2ddma_tzmid : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_xdma_tzmid : 1; /* [ 5], r, 0x0 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_mmcpu_tzmid_sel : 1; /* [ 16], r, 0x1 */
+ uint32_t tzc_blai_tzmid_sel : 1; /* [ 17], r, 0x1 */
+ uint32_t tzc_codec_tzmid_sel : 1; /* [ 18], r, 0x1 */
+ uint32_t tzc_subsys_tzmid_sel : 1; /* [ 19], r, 0x1 */
+ uint32_t tzc_x2ddma_tzmid_sel : 1; /* [ 20], r, 0x1 */
+ uint32_t tzc_xdma_tzmid_sel : 1; /* [ 21], r, 0x1 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_tzmid;
+
+ /* 0x304 : tzc_mm_bmx_tzmid_lock */
+ union {
+ struct {
+ uint32_t tzc_mmcpu_tzmid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_blai_tzmid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_codec_tzmid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_subsys_tzmid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_x2ddma_tzmid_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_xdma_tzmid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_tzmid_lock;
+
+ /* 0x308 : tzc_mm_bmx_s0 */
+ union {
+ struct {
+ uint32_t tzc_mmperi_s10_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_mmperi_s11_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_mmperi_s12_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_mmperi_s13_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_mmperi_s14_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_mmperi_s15_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_mmperi_s16_tzsid_en : 2; /* [13:12], r, 0x3 */
+ uint32_t tzc_mmperi_s17_tzsid_en : 2; /* [15:14], r, 0x3 */
+ uint32_t tzc_mmperi_s18_tzsid_en : 2; /* [17:16], r, 0x3 */
+ uint32_t tzc_mmperi_s19_tzsid_en : 2; /* [19:18], r, 0x3 */
+ uint32_t tzc_mmperi_s1a_tzsid_en : 2; /* [21:20], r, 0x3 */
+ uint32_t tzc_mmperi_s1b_tzsid_en : 2; /* [23:22], r, 0x3 */
+ uint32_t tzc_mmperi_s1c_tzsid_en : 2; /* [25:24], r, 0x3 */
+ uint32_t tzc_mmperi_s1d_tzsid_en : 2; /* [27:26], r, 0x3 */
+ uint32_t tzc_mmperi_s1e_tzsid_en : 2; /* [29:28], r, 0x3 */
+ uint32_t tzc_mmperi_s1f_tzsid_en : 2; /* [31:30], r, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s0;
+
+ /* 0x30C : tzc_mm_bmx_s1 */
+ union {
+ struct {
+ uint32_t tzc_s10_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_s11_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_s12_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_s13_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_s14_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_s15_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_s16_tzsid_en : 2; /* [13:12], r, 0x3 */
+ uint32_t tzc_s17_tzsid_en : 2; /* [15:14], r, 0x3 */
+ uint32_t tzc_s18_tzsid_en : 2; /* [17:16], r, 0x3 */
+ uint32_t tzc_s19_tzsid_en : 2; /* [19:18], r, 0x3 */
+ uint32_t tzc_s1a_tzsid_en : 2; /* [21:20], r, 0x3 */
+ uint32_t tzc_s1b_tzsid_en : 2; /* [23:22], r, 0x3 */
+ uint32_t tzc_s1c_tzsid_en : 2; /* [25:24], r, 0x3 */
+ uint32_t tzc_s1d_tzsid_en : 2; /* [27:26], r, 0x3 */
+ uint32_t tzc_s1e_tzsid_en : 2; /* [29:28], r, 0x3 */
+ uint32_t tzc_s1f_tzsid_en : 2; /* [31:30], r, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s1;
+
+ /* 0x310 : tzc_mm_bmx_s2 */
+ union {
+ struct {
+ uint32_t tzc_codec_s10_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_codec_s11_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_codec_s12_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_codec_s13_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_codec_s14_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_codec_s15_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_codec_s16_tzsid_en : 2; /* [13:12], r, 0x3 */
+ uint32_t tzc_codec_s17_tzsid_en : 2; /* [15:14], r, 0x3 */
+ uint32_t tzc_codec_s18_tzsid_en : 2; /* [17:16], r, 0x3 */
+ uint32_t tzc_codec_s19_tzsid_en : 2; /* [19:18], r, 0x3 */
+ uint32_t tzc_codec_s1a_tzsid_en : 2; /* [21:20], r, 0x3 */
+ uint32_t tzc_codec_s1b_tzsid_en : 2; /* [23:22], r, 0x3 */
+ uint32_t tzc_codec_s1c_tzsid_en : 2; /* [25:24], r, 0x3 */
+ uint32_t tzc_codec_s1d_tzsid_en : 2; /* [27:26], r, 0x3 */
+ uint32_t tzc_codec_s1e_tzsid_en : 2; /* [29:28], r, 0x3 */
+ uint32_t tzc_codec_s1f_tzsid_en : 2; /* [31:30], r, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s2;
+
+ /* 0x314 : tzc_mm_bmx_s_lock0 */
+ union {
+ struct {
+ uint32_t tzc_mmperi_s10_tzsid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_mmperi_s11_tzsid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_mmperi_s12_tzsid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_mmperi_s13_tzsid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_mmperi_s14_tzsid_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_mmperi_s15_tzsid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_mmperi_s16_tzsid_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_mmperi_s17_tzsid_lock : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_mmperi_s18_tzsid_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_mmperi_s19_tzsid_lock : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_mmperi_s1a_tzsid_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t tzc_mmperi_s1b_tzsid_lock : 1; /* [ 11], r, 0x0 */
+ uint32_t tzc_mmperi_s1c_tzsid_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t tzc_mmperi_s1d_tzsid_lock : 1; /* [ 13], r, 0x0 */
+ uint32_t tzc_mmperi_s1e_tzsid_lock : 1; /* [ 14], r, 0x0 */
+ uint32_t tzc_mmperi_s1f_tzsid_lock : 1; /* [ 15], r, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s_lock0;
+
+ /* 0x318 : tzc_mm_bmx_s_lock1 */
+ union {
+ struct {
+ uint32_t tzc_codec_s10_tzsid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_codec_s11_tzsid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_codec_s12_tzsid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_codec_s13_tzsid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_codec_s14_tzsid_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_codec_s15_tzsid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_codec_s16_tzsid_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_codec_s17_tzsid_lock : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_codec_s18_tzsid_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_codec_s19_tzsid_lock : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_codec_s1a_tzsid_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t tzc_codec_s1b_tzsid_lock : 1; /* [ 11], r, 0x0 */
+ uint32_t tzc_codec_s1c_tzsid_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t tzc_codec_s1d_tzsid_lock : 1; /* [ 13], r, 0x0 */
+ uint32_t tzc_codec_s1e_tzsid_lock : 1; /* [ 14], r, 0x0 */
+ uint32_t tzc_codec_s1f_tzsid_lock : 1; /* [ 15], r, 0x0 */
+ uint32_t tzc_s10_tzsid_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_s11_tzsid_lock : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_s12_tzsid_lock : 1; /* [ 18], r, 0x0 */
+ uint32_t tzc_s13_tzsid_lock : 1; /* [ 19], r, 0x0 */
+ uint32_t tzc_s14_tzsid_lock : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_s15_tzsid_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_s16_tzsid_lock : 1; /* [ 22], r, 0x0 */
+ uint32_t tzc_s17_tzsid_lock : 1; /* [ 23], r, 0x0 */
+ uint32_t tzc_s18_tzsid_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_s19_tzsid_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_s1a_tzsid_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t tzc_s1b_tzsid_lock : 1; /* [ 27], r, 0x0 */
+ uint32_t tzc_s1c_tzsid_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t tzc_s1d_tzsid_lock : 1; /* [ 29], r, 0x0 */
+ uint32_t tzc_s1e_tzsid_lock : 1; /* [ 30], r, 0x0 */
+ uint32_t tzc_s1f_tzsid_lock : 1; /* [ 31], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s_lock1;
+
+ /* 0x31c reserved */
+ uint8_t RESERVED0x31c[36];
+
+ /* 0x340 : tzc_l2sram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r0_id_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_l2sram_tzsrg_r1_id_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_l2sram_tzsrg_r2_id_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r0_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r1_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r2_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_ctrl;
+
+ /* 0x344 : tzc_l2sram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_adr_mask : 10; /* [ 9: 0], r, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_adr_mask;
+
+ /* 0x348 : tzc_l2sram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r0_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r0_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r0;
+
+ /* 0x34C : tzc_l2sram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r1_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r1_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r1;
+
+ /* 0x350 : tzc_l2sram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r2_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r2_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r2;
+
+ /* 0x354 : tzc_l2sram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r3;
+
+ /* 0x358 reserved */
+ uint8_t RESERVED0x358[8];
+
+ /* 0x360 : tzc_vram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r0_id_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_vram_tzsrg_r1_id_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_vram_tzsrg_r2_id_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_vram_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_vram_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r0_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_vram_tzsrg_r1_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_vram_tzsrg_r2_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_ctrl;
+
+ /* 0x364 : tzc_vram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_adr_mask : 10; /* [ 9: 0], r, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_adr_mask;
+
+ /* 0x368 : tzc_vram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r0_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r0_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r0;
+
+ /* 0x36C : tzc_vram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r1_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r1_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r1;
+
+ /* 0x370 : tzc_vram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r2_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r2_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r2;
+
+ /* 0x374 : tzc_vram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r3;
+
+ /* 0x378 reserved */
+ uint8_t RESERVED0x378[8];
+
+ /* 0x380 : tzc_psrama_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r0_id_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_psrama_tzsrg_r1_id_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_psrama_tzsrg_r2_id_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r0_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r1_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r2_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_ctrl;
+
+ /* 0x384 : tzc_psrama_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_adr_mask : 16; /* [15: 0], r, 0x0 */
+ uint32_t tzc_psrama_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_adr_mask;
+
+ /* 0x388 : tzc_psrama_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r0_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_psrama_tzsrg_r0_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r0;
+
+ /* 0x38C : tzc_psrama_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r1_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_psrama_tzsrg_r1_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r1;
+
+ /* 0x390 : tzc_psrama_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r2_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_psrama_tzsrg_r2_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r2;
+
+ /* 0x394 : tzc_psrama_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r3;
+
+ /* 0x398 reserved */
+ uint8_t RESERVED0x398[8];
+
+ /* 0x3a0 : tzc_psramb_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r0_id_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_psramb_tzsrg_r1_id_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_psramb_tzsrg_r2_id_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r0_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r1_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r2_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_ctrl;
+
+ /* 0x3A4 : tzc_psramb_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_adr_mask : 16; /* [15: 0], r, 0x0 */
+ uint32_t tzc_psramb_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_adr_mask;
+
+ /* 0x3A8 : tzc_psramb_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r0_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_psramb_tzsrg_r0_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r0;
+
+ /* 0x3AC : tzc_psramb_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r1_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_psramb_tzsrg_r1_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r1;
+
+ /* 0x3B0 : tzc_psramb_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r2_end : 16; /* [15: 0], r, 0xffff */
+ uint32_t tzc_psramb_tzsrg_r2_start : 16; /* [31:16], r, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r2;
+
+ /* 0x3B4 : tzc_psramb_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r3;
+
+ /* 0x3b8 reserved */
+ uint8_t RESERVED0x3b8[8];
+
+ /* 0x3c0 : tzc_xram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r0_id_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_xram_tzsrg_r1_id_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_xram_tzsrg_r2_id_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r0_en : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_xram_tzsrg_r1_en : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_xram_tzsrg_r2_en : 1; /* [ 18], r, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r0_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_xram_tzsrg_r1_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_xram_tzsrg_r2_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_ctrl;
+
+ /* 0x3C4 : tzc_xram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_adr_mask : 10; /* [ 9: 0], r, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_adr_mask_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_adr_mask;
+
+ /* 0x3C8 : tzc_xram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r0_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r0_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r0;
+
+ /* 0x3CC : tzc_xram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r1_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r1_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r1;
+
+ /* 0x3D0 : tzc_xram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r2_end : 10; /* [ 9: 0], r, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r2_start : 10; /* [25:16], r, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r2;
+
+ /* 0x3D4 : tzc_xram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r3;
+
+ /* 0x3d8 reserved */
+ uint8_t RESERVED0x3d8[2856];
+
+ /* 0xF00 : tzc_glb_ctrl_0 */
+ union {
+ struct {
+ uint32_t tzc_glb_pwron_rst_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_glb_cpu_reset_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_glb_sys_reset_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_glb_cpu2_reset_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_glb_misc_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_glb_sram_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_glb_swrst_tzsid_en : 2; /* [13:12], r, 0x3 */
+ uint32_t tzc_glb_bmx_tzsid_en : 2; /* [15:14], r, 0x3 */
+ uint32_t tzc_glb_dbg_tzsid_en : 2; /* [17:16], r, 0x3 */
+ uint32_t tzc_glb_mbist_tzsid_en : 2; /* [19:18], r, 0x3 */
+ uint32_t tzc_glb_clk_tzsid_en : 2; /* [21:20], r, 0x3 */
+ uint32_t tzc_glb_int_tzsid_en : 2; /* [23:22], r, 0x3 */
+ uint32_t tzc_glb_pwr_tzsid_en : 2; /* [25:24], r, 0x3 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_glb_ctrl_0;
+
+ /* 0xF04 : tzc_glb_ctrl_1 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_glb_ctrl_1;
+
+ /* 0xF08 : tzc_glb_ctrl_2 */
+ union {
+ struct {
+ uint32_t tzc_glb_pwron_rst_tzsid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_glb_cpu_reset_tzsid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_glb_sys_reset_tzsid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_glb_cpu2_reset_tzsid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_glb_misc_tzsid_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_glb_sram_tzsid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_glb_swrst_tzsid_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_glb_bmx_tzsid_lock : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_glb_dbg_tzsid_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_glb_mbist_tzsid_lock : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_glb_clk_tzsid_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t tzc_glb_int_tzsid_lock : 1; /* [ 11], r, 0x0 */
+ uint32_t tzc_glb_pwr_tzsid_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_glb_ctrl_2;
+
+ /* 0xf0c reserved */
+ uint8_t RESERVED0xf0c[20];
+
+ /* 0xF20 : tzc_mm_ctrl_0 */
+ union {
+ struct {
+ uint32_t tzc_mm_pwron_rst_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_mm_cpu0_reset_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_mm_sys_reset_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_mm_cpu0_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */
+ uint32_t tzc_mm_sram_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_mm_swrst_tzsid_en : 2; /* [13:12], r, 0x3 */
+ uint32_t reserved_14_19 : 6; /* [19:14], rsvd, 0x0 */
+ uint32_t tzc_mm_clk_tzsid_en : 2; /* [21:20], r, 0x3 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_ctrl_0;
+
+ /* 0xF24 : tzc_mm_ctrl_1 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_ctrl_1;
+
+ /* 0xF28 : tzc_mm_ctrl_2 */
+ union {
+ struct {
+ uint32_t tzc_mm_pwron_rst_tzsid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_mm_cpu0_reset_tzsid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_mm_sys_reset_tzsid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_mm_cpu0_tzsid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t reserved_4 : 1; /* [ 4], rsvd, 0x0 */
+ uint32_t tzc_mm_sram_tzsid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_mm_swrst_tzsid_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t reserved_7_9 : 3; /* [ 9: 7], rsvd, 0x0 */
+ uint32_t tzc_mm_clk_tzsid_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_ctrl_2;
+
+ /* 0xf2c reserved */
+ uint8_t RESERVED0xf2c[20];
+
+ /* 0xF40 : tzc_se_ctrl_0 */
+ union {
+ struct {
+ uint32_t tzc_se_sha_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_se_aes_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_se_trng_tzsid_en : 2; /* [ 5: 4], r, 0x3 */
+ uint32_t tzc_se_pka_tzsid_en : 2; /* [ 7: 6], r, 0x3 */
+ uint32_t tzc_se_cdet_tzsid_en : 2; /* [ 9: 8], r, 0x3 */
+ uint32_t tzc_se_gmac_tzsid_en : 2; /* [11:10], r, 0x3 */
+ uint32_t tzc_se_tzsid_crmd : 1; /* [ 12], r, 0x0 */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t tzc_se_wdt_dly : 16; /* [31:16], r, 0x5 */
+ } BF;
+ uint32_t WORD;
+ } tzc_se_ctrl_0;
+
+ /* 0xF44 : tzc_se_ctrl_1 */
+ union {
+ struct {
+ uint32_t tzc_sf_cr_tzsid_en : 2; /* [ 1: 0], r, 0x3 */
+ uint32_t tzc_sf_sec_tzsid_en : 2; /* [ 3: 2], r, 0x3 */
+ uint32_t tzc_sf_tzsid_crmd : 1; /* [ 4], r, 0x0 */
+ uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_se_ctrl_1;
+
+ /* 0xF48 : tzc_se_ctrl_2 */
+ union {
+ struct {
+ uint32_t tzc_se_sha_tzsid_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_se_aes_tzsid_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_se_trng_tzsid_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_se_pka_tzsid_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_se_cdet_tzsid_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_se_gmac_tzsid_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_se_tzsid_crmd_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t reserved_7_15 : 9; /* [15: 7], rsvd, 0x0 */
+ uint32_t tzc_sf_cr_tzsid_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_sf_sec_tzsid_lock : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_sf_tzsid_crmd_lock : 1; /* [ 18], r, 0x0 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_se_ctrl_2;
+};
+
+typedef volatile struct tzc_nsec_reg tzc_nsec_reg_t;
+
+#endif /* __TZC_NSEC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/tzc_sec_reg.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/tzc_sec_reg.h
new file mode 100644
index 00000000..bdce232e
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware/tzc_sec_reg.h
@@ -0,0 +1,3803 @@
+/**
+ ******************************************************************************
+ * @file tzc_sec_reg.h
+ * @version V1.0
+ * @date 2021-07-20
+ * @brief This file is the description of.IP register
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __TZC_SEC_REG_H__
+#define __TZC_SEC_REG_H__
+
+#include "bl808.h"
+
+/* 0x40 : tzc_rom_tzsrg_ctrl */
+#define TZC_SEC_TZC_ROM_TZSRG_CTRL_OFFSET (0x40)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R0_EN TZC_SEC_TZC_ROM_TZSRG_R0_EN
+#define TZC_SEC_TZC_ROM_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R1_EN TZC_SEC_TZC_ROM_TZSRG_R1_EN
+#define TZC_SEC_TZC_ROM_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R2_EN TZC_SEC_TZC_ROM_TZSRG_R2_EN
+#define TZC_SEC_TZC_ROM_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R0_LOCK TZC_SEC_TZC_ROM_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R1_LOCK TZC_SEC_TZC_ROM_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R2_LOCK TZC_SEC_TZC_ROM_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_LOCK_POS))
+#define TZC_SEC_TZC_SBOOT_DONE TZC_SEC_TZC_SBOOT_DONE
+#define TZC_SEC_TZC_SBOOT_DONE_POS (28U)
+#define TZC_SEC_TZC_SBOOT_DONE_LEN (4U)
+#define TZC_SEC_TZC_SBOOT_DONE_MSK (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)
+#define TZC_SEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS))
+
+/* 0x44 : tzc_rom_tzsrg_adr_mask */
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_OFFSET (0x44)
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK TZC_SEC_TZC_ROM_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x48 : tzc_rom_tzsrg_r0 */
+#define TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET (0x48)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_END TZC_SEC_TZC_ROM_TZSRG_R0_END
+#define TZC_SEC_TZC_ROM_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_END_LEN (10U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R0_START TZC_SEC_TZC_ROM_TZSRG_R0_START
+#define TZC_SEC_TZC_ROM_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_START_LEN (10U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R0_START_POS))
+
+/* 0x4C : tzc_rom_tzsrg_r1 */
+#define TZC_SEC_TZC_ROM_TZSRG_R1_OFFSET (0x4C)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_END TZC_SEC_TZC_ROM_TZSRG_R1_END
+#define TZC_SEC_TZC_ROM_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_END_LEN (10U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R1_START TZC_SEC_TZC_ROM_TZSRG_R1_START
+#define TZC_SEC_TZC_ROM_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_START_LEN (10U)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R1_START_POS))
+
+/* 0x50 : tzc_rom_tzsrg_r2 */
+#define TZC_SEC_TZC_ROM_TZSRG_R2_OFFSET (0x50)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_END TZC_SEC_TZC_ROM_TZSRG_R2_END
+#define TZC_SEC_TZC_ROM_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_END_LEN (10U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_ROM_TZSRG_R2_START TZC_SEC_TZC_ROM_TZSRG_R2_START
+#define TZC_SEC_TZC_ROM_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_START_LEN (10U)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_ROM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_ROM_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_ROM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_ROM_TZSRG_R2_START_POS))
+
+/* 0x54 : tzc_rom_tzsrg_r3 */
+#define TZC_SEC_TZC_ROM_TZSRG_R3_OFFSET (0x54)
+
+/* 0x100 : tzc_bmx_tzmid */
+#define TZC_SEC_TZC_BMX_TZMID_OFFSET (0x100)
+#define TZC_SEC_TZC_PICO_TZMID TZC_SEC_TZC_PICO_TZMID
+#define TZC_SEC_TZC_PICO_TZMID_POS (0U)
+#define TZC_SEC_TZC_PICO_TZMID_LEN (1U)
+#define TZC_SEC_TZC_PICO_TZMID_MSK (((1U << TZC_SEC_TZC_PICO_TZMID_LEN) - 1) << TZC_SEC_TZC_PICO_TZMID_POS)
+#define TZC_SEC_TZC_PICO_TZMID_UMSK (~(((1U << TZC_SEC_TZC_PICO_TZMID_LEN) - 1) << TZC_SEC_TZC_PICO_TZMID_POS))
+#define TZC_SEC_TZC_MM_TZMID TZC_SEC_TZC_MM_TZMID
+#define TZC_SEC_TZC_MM_TZMID_POS (1U)
+#define TZC_SEC_TZC_MM_TZMID_LEN (1U)
+#define TZC_SEC_TZC_MM_TZMID_MSK (((1U << TZC_SEC_TZC_MM_TZMID_LEN) - 1) << TZC_SEC_TZC_MM_TZMID_POS)
+#define TZC_SEC_TZC_MM_TZMID_UMSK (~(((1U << TZC_SEC_TZC_MM_TZMID_LEN) - 1) << TZC_SEC_TZC_MM_TZMID_POS))
+#define TZC_SEC_TZC_USB_TZMID TZC_SEC_TZC_USB_TZMID
+#define TZC_SEC_TZC_USB_TZMID_POS (2U)
+#define TZC_SEC_TZC_USB_TZMID_LEN (1U)
+#define TZC_SEC_TZC_USB_TZMID_MSK (((1U << TZC_SEC_TZC_USB_TZMID_LEN) - 1) << TZC_SEC_TZC_USB_TZMID_POS)
+#define TZC_SEC_TZC_USB_TZMID_UMSK (~(((1U << TZC_SEC_TZC_USB_TZMID_LEN) - 1) << TZC_SEC_TZC_USB_TZMID_POS))
+#define TZC_SEC_TZC_WIFI_TZMID TZC_SEC_TZC_WIFI_TZMID
+#define TZC_SEC_TZC_WIFI_TZMID_POS (3U)
+#define TZC_SEC_TZC_WIFI_TZMID_LEN (1U)
+#define TZC_SEC_TZC_WIFI_TZMID_MSK (((1U << TZC_SEC_TZC_WIFI_TZMID_LEN) - 1) << TZC_SEC_TZC_WIFI_TZMID_POS)
+#define TZC_SEC_TZC_WIFI_TZMID_UMSK (~(((1U << TZC_SEC_TZC_WIFI_TZMID_LEN) - 1) << TZC_SEC_TZC_WIFI_TZMID_POS))
+#define TZC_SEC_TZC_CCI_TZMID TZC_SEC_TZC_CCI_TZMID
+#define TZC_SEC_TZC_CCI_TZMID_POS (4U)
+#define TZC_SEC_TZC_CCI_TZMID_LEN (1U)
+#define TZC_SEC_TZC_CCI_TZMID_MSK (((1U << TZC_SEC_TZC_CCI_TZMID_LEN) - 1) << TZC_SEC_TZC_CCI_TZMID_POS)
+#define TZC_SEC_TZC_CCI_TZMID_UMSK (~(((1U << TZC_SEC_TZC_CCI_TZMID_LEN) - 1) << TZC_SEC_TZC_CCI_TZMID_POS))
+#define TZC_SEC_TZC_SDHM_TZMID TZC_SEC_TZC_SDHM_TZMID
+#define TZC_SEC_TZC_SDHM_TZMID_POS (5U)
+#define TZC_SEC_TZC_SDHM_TZMID_LEN (1U)
+#define TZC_SEC_TZC_SDHM_TZMID_MSK (((1U << TZC_SEC_TZC_SDHM_TZMID_LEN) - 1) << TZC_SEC_TZC_SDHM_TZMID_POS)
+#define TZC_SEC_TZC_SDHM_TZMID_UMSK (~(((1U << TZC_SEC_TZC_SDHM_TZMID_LEN) - 1) << TZC_SEC_TZC_SDHM_TZMID_POS))
+#define TZC_SEC_TZC_EMACA_TZMID TZC_SEC_TZC_EMACA_TZMID
+#define TZC_SEC_TZC_EMACA_TZMID_POS (6U)
+#define TZC_SEC_TZC_EMACA_TZMID_LEN (1U)
+#define TZC_SEC_TZC_EMACA_TZMID_MSK (((1U << TZC_SEC_TZC_EMACA_TZMID_LEN) - 1) << TZC_SEC_TZC_EMACA_TZMID_POS)
+#define TZC_SEC_TZC_EMACA_TZMID_UMSK (~(((1U << TZC_SEC_TZC_EMACA_TZMID_LEN) - 1) << TZC_SEC_TZC_EMACA_TZMID_POS))
+#define TZC_SEC_TZC_CPU_TZMID TZC_SEC_TZC_CPU_TZMID
+#define TZC_SEC_TZC_CPU_TZMID_POS (7U)
+#define TZC_SEC_TZC_CPU_TZMID_LEN (1U)
+#define TZC_SEC_TZC_CPU_TZMID_MSK (((1U << TZC_SEC_TZC_CPU_TZMID_LEN) - 1) << TZC_SEC_TZC_CPU_TZMID_POS)
+#define TZC_SEC_TZC_CPU_TZMID_UMSK (~(((1U << TZC_SEC_TZC_CPU_TZMID_LEN) - 1) << TZC_SEC_TZC_CPU_TZMID_POS))
+#define TZC_SEC_TZC_DMA_TZMID TZC_SEC_TZC_DMA_TZMID
+#define TZC_SEC_TZC_DMA_TZMID_POS (8U)
+#define TZC_SEC_TZC_DMA_TZMID_LEN (1U)
+#define TZC_SEC_TZC_DMA_TZMID_MSK (((1U << TZC_SEC_TZC_DMA_TZMID_LEN) - 1) << TZC_SEC_TZC_DMA_TZMID_POS)
+#define TZC_SEC_TZC_DMA_TZMID_UMSK (~(((1U << TZC_SEC_TZC_DMA_TZMID_LEN) - 1) << TZC_SEC_TZC_DMA_TZMID_POS))
+#define TZC_SEC_TZC_DMA2_TZMID TZC_SEC_TZC_DMA2_TZMID
+#define TZC_SEC_TZC_DMA2_TZMID_POS (9U)
+#define TZC_SEC_TZC_DMA2_TZMID_LEN (1U)
+#define TZC_SEC_TZC_DMA2_TZMID_MSK (((1U << TZC_SEC_TZC_DMA2_TZMID_LEN) - 1) << TZC_SEC_TZC_DMA2_TZMID_POS)
+#define TZC_SEC_TZC_DMA2_TZMID_UMSK (~(((1U << TZC_SEC_TZC_DMA2_TZMID_LEN) - 1) << TZC_SEC_TZC_DMA2_TZMID_POS))
+#define TZC_SEC_TZC_LZ4_TZMID TZC_SEC_TZC_LZ4_TZMID
+#define TZC_SEC_TZC_LZ4_TZMID_POS (10U)
+#define TZC_SEC_TZC_LZ4_TZMID_LEN (1U)
+#define TZC_SEC_TZC_LZ4_TZMID_MSK (((1U << TZC_SEC_TZC_LZ4_TZMID_LEN) - 1) << TZC_SEC_TZC_LZ4_TZMID_POS)
+#define TZC_SEC_TZC_LZ4_TZMID_UMSK (~(((1U << TZC_SEC_TZC_LZ4_TZMID_LEN) - 1) << TZC_SEC_TZC_LZ4_TZMID_POS))
+#define TZC_SEC_TZC_PICO_TZMID_SEL TZC_SEC_TZC_PICO_TZMID_SEL
+#define TZC_SEC_TZC_PICO_TZMID_SEL_POS (16U)
+#define TZC_SEC_TZC_PICO_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_PICO_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_PICO_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_PICO_TZMID_SEL_POS)
+#define TZC_SEC_TZC_PICO_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_PICO_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_PICO_TZMID_SEL_POS))
+#define TZC_SEC_TZC_MM_TZMID_SEL TZC_SEC_TZC_MM_TZMID_SEL
+#define TZC_SEC_TZC_MM_TZMID_SEL_POS (17U)
+#define TZC_SEC_TZC_MM_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_MM_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_MM_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MM_TZMID_SEL_POS)
+#define TZC_SEC_TZC_MM_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_MM_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MM_TZMID_SEL_POS))
+#define TZC_SEC_TZC_USB_TZMID_SEL TZC_SEC_TZC_USB_TZMID_SEL
+#define TZC_SEC_TZC_USB_TZMID_SEL_POS (18U)
+#define TZC_SEC_TZC_USB_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_USB_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_USB_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_USB_TZMID_SEL_POS)
+#define TZC_SEC_TZC_USB_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_USB_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_USB_TZMID_SEL_POS))
+#define TZC_SEC_TZC_WIFI_TZMID_SEL TZC_SEC_TZC_WIFI_TZMID_SEL
+#define TZC_SEC_TZC_WIFI_TZMID_SEL_POS (19U)
+#define TZC_SEC_TZC_WIFI_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_WIFI_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_WIFI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_WIFI_TZMID_SEL_POS)
+#define TZC_SEC_TZC_WIFI_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_WIFI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_WIFI_TZMID_SEL_POS))
+#define TZC_SEC_TZC_CCI_TZMID_SEL TZC_SEC_TZC_CCI_TZMID_SEL
+#define TZC_SEC_TZC_CCI_TZMID_SEL_POS (20U)
+#define TZC_SEC_TZC_CCI_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_CCI_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_CCI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CCI_TZMID_SEL_POS)
+#define TZC_SEC_TZC_CCI_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_CCI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CCI_TZMID_SEL_POS))
+#define TZC_SEC_TZC_SDHM_TZMID_SEL TZC_SEC_TZC_SDHM_TZMID_SEL
+#define TZC_SEC_TZC_SDHM_TZMID_SEL_POS (21U)
+#define TZC_SEC_TZC_SDHM_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_SDHM_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_SDHM_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_SDHM_TZMID_SEL_POS)
+#define TZC_SEC_TZC_SDHM_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_SDHM_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_SDHM_TZMID_SEL_POS))
+#define TZC_SEC_TZC_EMACA_TZMID_SEL TZC_SEC_TZC_EMACA_TZMID_SEL
+#define TZC_SEC_TZC_EMACA_TZMID_SEL_POS (22U)
+#define TZC_SEC_TZC_EMACA_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_EMACA_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_EMACA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_EMACA_TZMID_SEL_POS)
+#define TZC_SEC_TZC_EMACA_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_EMACA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_EMACA_TZMID_SEL_POS))
+#define TZC_SEC_TZC_CPU_TZMID_SEL TZC_SEC_TZC_CPU_TZMID_SEL
+#define TZC_SEC_TZC_CPU_TZMID_SEL_POS (23U)
+#define TZC_SEC_TZC_CPU_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_CPU_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_CPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CPU_TZMID_SEL_POS)
+#define TZC_SEC_TZC_CPU_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_CPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CPU_TZMID_SEL_POS))
+#define TZC_SEC_TZC_DMA_TZMID_SEL TZC_SEC_TZC_DMA_TZMID_SEL
+#define TZC_SEC_TZC_DMA_TZMID_SEL_POS (24U)
+#define TZC_SEC_TZC_DMA_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_DMA_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_DMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_DMA_TZMID_SEL_POS)
+#define TZC_SEC_TZC_DMA_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_DMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_DMA_TZMID_SEL_POS))
+#define TZC_SEC_TZC_DMA2_TZMID_SEL TZC_SEC_TZC_DMA2_TZMID_SEL
+#define TZC_SEC_TZC_DMA2_TZMID_SEL_POS (25U)
+#define TZC_SEC_TZC_DMA2_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_DMA2_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_DMA2_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_DMA2_TZMID_SEL_POS)
+#define TZC_SEC_TZC_DMA2_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_DMA2_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_DMA2_TZMID_SEL_POS))
+#define TZC_SEC_TZC_LZ4_TZMID_SEL TZC_SEC_TZC_LZ4_TZMID_SEL
+#define TZC_SEC_TZC_LZ4_TZMID_SEL_POS (26U)
+#define TZC_SEC_TZC_LZ4_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_LZ4_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_LZ4_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_LZ4_TZMID_SEL_POS)
+#define TZC_SEC_TZC_LZ4_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_LZ4_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_LZ4_TZMID_SEL_POS))
+
+/* 0x104 : tzc_bmx_tzmid_lock */
+#define TZC_SEC_TZC_BMX_TZMID_LOCK_OFFSET (0x104)
+#define TZC_SEC_TZC_PICO_TZMID_LOCK TZC_SEC_TZC_PICO_TZMID_LOCK
+#define TZC_SEC_TZC_PICO_TZMID_LOCK_POS (0U)
+#define TZC_SEC_TZC_PICO_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PICO_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_PICO_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_PICO_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_PICO_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PICO_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_PICO_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_MM_TZMID_LOCK TZC_SEC_TZC_MM_TZMID_LOCK
+#define TZC_SEC_TZC_MM_TZMID_LOCK_POS (1U)
+#define TZC_SEC_TZC_MM_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_MM_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_USB_TZMID_LOCK TZC_SEC_TZC_USB_TZMID_LOCK
+#define TZC_SEC_TZC_USB_TZMID_LOCK_POS (2U)
+#define TZC_SEC_TZC_USB_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_USB_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_USB_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_USB_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_USB_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_USB_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_USB_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_WIFI_TZMID_LOCK TZC_SEC_TZC_WIFI_TZMID_LOCK
+#define TZC_SEC_TZC_WIFI_TZMID_LOCK_POS (3U)
+#define TZC_SEC_TZC_WIFI_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_WIFI_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_WIFI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_WIFI_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_WIFI_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_WIFI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_WIFI_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_CCI_TZMID_LOCK TZC_SEC_TZC_CCI_TZMID_LOCK
+#define TZC_SEC_TZC_CCI_TZMID_LOCK_POS (4U)
+#define TZC_SEC_TZC_CCI_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CCI_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_CCI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CCI_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_CCI_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CCI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CCI_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_SDHM_TZMID_LOCK TZC_SEC_TZC_SDHM_TZMID_LOCK
+#define TZC_SEC_TZC_SDHM_TZMID_LOCK_POS (5U)
+#define TZC_SEC_TZC_SDHM_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SDHM_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_SDHM_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_SDHM_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_SDHM_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SDHM_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_SDHM_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_EMACA_TZMID_LOCK TZC_SEC_TZC_EMACA_TZMID_LOCK
+#define TZC_SEC_TZC_EMACA_TZMID_LOCK_POS (6U)
+#define TZC_SEC_TZC_EMACA_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_EMACA_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_EMACA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_EMACA_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_EMACA_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_EMACA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_EMACA_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_CPU_TZMID_LOCK TZC_SEC_TZC_CPU_TZMID_LOCK
+#define TZC_SEC_TZC_CPU_TZMID_LOCK_POS (7U)
+#define TZC_SEC_TZC_CPU_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CPU_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_CPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CPU_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_CPU_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CPU_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_DMA_TZMID_LOCK TZC_SEC_TZC_DMA_TZMID_LOCK
+#define TZC_SEC_TZC_DMA_TZMID_LOCK_POS (8U)
+#define TZC_SEC_TZC_DMA_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_DMA_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_DMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_DMA_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_DMA_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_DMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_DMA_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_DMA2_TZMID_LOCK TZC_SEC_TZC_DMA2_TZMID_LOCK
+#define TZC_SEC_TZC_DMA2_TZMID_LOCK_POS (9U)
+#define TZC_SEC_TZC_DMA2_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_DMA2_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_DMA2_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_DMA2_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_DMA2_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_DMA2_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_DMA2_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_LZ4_TZMID_LOCK TZC_SEC_TZC_LZ4_TZMID_LOCK
+#define TZC_SEC_TZC_LZ4_TZMID_LOCK_POS (10U)
+#define TZC_SEC_TZC_LZ4_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_LZ4_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_LZ4_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_LZ4_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_LZ4_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_LZ4_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_LZ4_TZMID_LOCK_POS))
+
+/* 0x108 : tzc_bmx_s0 */
+#define TZC_SEC_TZC_BMX_S0_OFFSET (0x108)
+#define TZC_SEC_TZC_BMX_MM_TZSID_EN TZC_SEC_TZC_BMX_MM_TZSID_EN
+#define TZC_SEC_TZC_BMX_MM_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_BMX_MM_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_MM_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_MM_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_MM_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_MM_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_MM_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_MM_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_DMA_TZSID_EN TZC_SEC_TZC_BMX_DMA_TZSID_EN
+#define TZC_SEC_TZC_BMX_DMA_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_BMX_DMA_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_DMA_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_DMA_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_DMA_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_DMA_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_DMA_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_DMA_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_EN TZC_SEC_TZC_BMX_DMA2_TZSID_EN
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_DMA2_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_DMA2_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_DMA2_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_DMA2_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_PWR_TZSID_EN TZC_SEC_TZC_BMX_PWR_TZSID_EN
+#define TZC_SEC_TZC_BMX_PWR_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_BMX_PWR_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_PWR_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_PWR_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_PWR_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_PWR_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_PWR_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_PWR_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_SDH_TZSID_EN TZC_SEC_TZC_BMX_SDH_TZSID_EN
+#define TZC_SEC_TZC_BMX_SDH_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_BMX_SDH_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_SDH_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_SDH_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_SDH_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_SDH_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_SDH_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_SDH_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_EN TZC_SEC_TZC_BMX_EMAC_TZSID_EN
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_EMAC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_EMAC_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_EMAC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_EMAC_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_MM_TZSID_LOCK TZC_SEC_TZC_BMX_MM_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_MM_TZSID_LOCK_POS (16U)
+#define TZC_SEC_TZC_BMX_MM_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_MM_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_MM_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_MM_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_MM_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_MM_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_MM_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_DMA_TZSID_LOCK TZC_SEC_TZC_BMX_DMA_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_POS (17U)
+#define TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_DMA_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_POS (18U)
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_DMA2_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_PWR_TZSID_LOCK TZC_SEC_TZC_BMX_PWR_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_POS (19U)
+#define TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_PWR_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_SDH_TZSID_LOCK TZC_SEC_TZC_BMX_SDH_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_POS (20U)
+#define TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_SDH_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_POS (21U)
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_EMAC_TZSID_LOCK_POS))
+
+/* 0x10C : tzc_bmx_s1 */
+#define TZC_SEC_TZC_BMX_S1_OFFSET (0x10C)
+#define TZC_SEC_TZC_BMX_S10_TZSID_EN TZC_SEC_TZC_BMX_S10_TZSID_EN
+#define TZC_SEC_TZC_BMX_S10_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_BMX_S10_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S10_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S10_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S10_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S10_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S11_TZSID_EN TZC_SEC_TZC_BMX_S11_TZSID_EN
+#define TZC_SEC_TZC_BMX_S11_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_BMX_S11_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S11_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S11_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S11_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S11_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S12_TZSID_EN TZC_SEC_TZC_BMX_S12_TZSID_EN
+#define TZC_SEC_TZC_BMX_S12_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_BMX_S12_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S12_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S12_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S12_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S12_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S13_TZSID_EN TZC_SEC_TZC_BMX_S13_TZSID_EN
+#define TZC_SEC_TZC_BMX_S13_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_BMX_S13_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S13_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S13_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S13_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S13_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S14_TZSID_EN TZC_SEC_TZC_BMX_S14_TZSID_EN
+#define TZC_SEC_TZC_BMX_S14_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_BMX_S14_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S14_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S14_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S14_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S14_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S15_TZSID_EN TZC_SEC_TZC_BMX_S15_TZSID_EN
+#define TZC_SEC_TZC_BMX_S15_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_BMX_S15_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S15_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S15_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S15_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S15_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S16_TZSID_EN TZC_SEC_TZC_BMX_S16_TZSID_EN
+#define TZC_SEC_TZC_BMX_S16_TZSID_EN_POS (12U)
+#define TZC_SEC_TZC_BMX_S16_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S16_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S16_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S16_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S16_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S17_TZSID_EN TZC_SEC_TZC_BMX_S17_TZSID_EN
+#define TZC_SEC_TZC_BMX_S17_TZSID_EN_POS (14U)
+#define TZC_SEC_TZC_BMX_S17_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S17_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S17_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S17_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S17_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S18_TZSID_EN TZC_SEC_TZC_BMX_S18_TZSID_EN
+#define TZC_SEC_TZC_BMX_S18_TZSID_EN_POS (16U)
+#define TZC_SEC_TZC_BMX_S18_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S18_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S18_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S18_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S18_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S19_TZSID_EN TZC_SEC_TZC_BMX_S19_TZSID_EN
+#define TZC_SEC_TZC_BMX_S19_TZSID_EN_POS (18U)
+#define TZC_SEC_TZC_BMX_S19_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S19_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S19_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S19_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S19_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S1A_TZSID_EN TZC_SEC_TZC_BMX_S1A_TZSID_EN
+#define TZC_SEC_TZC_BMX_S1A_TZSID_EN_POS (20U)
+#define TZC_SEC_TZC_BMX_S1A_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S1A_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1A_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S1A_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1A_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S1B_TZSID_EN TZC_SEC_TZC_BMX_S1B_TZSID_EN
+#define TZC_SEC_TZC_BMX_S1B_TZSID_EN_POS (22U)
+#define TZC_SEC_TZC_BMX_S1B_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S1B_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1B_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S1B_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1B_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S1C_TZSID_EN TZC_SEC_TZC_BMX_S1C_TZSID_EN
+#define TZC_SEC_TZC_BMX_S1C_TZSID_EN_POS (24U)
+#define TZC_SEC_TZC_BMX_S1C_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S1C_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1C_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S1C_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1C_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S1D_TZSID_EN TZC_SEC_TZC_BMX_S1D_TZSID_EN
+#define TZC_SEC_TZC_BMX_S1D_TZSID_EN_POS (26U)
+#define TZC_SEC_TZC_BMX_S1D_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S1D_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1D_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S1D_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1D_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S1E_TZSID_EN TZC_SEC_TZC_BMX_S1E_TZSID_EN
+#define TZC_SEC_TZC_BMX_S1E_TZSID_EN_POS (28U)
+#define TZC_SEC_TZC_BMX_S1E_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S1E_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1E_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S1E_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1E_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S1F_TZSID_EN TZC_SEC_TZC_BMX_S1F_TZSID_EN
+#define TZC_SEC_TZC_BMX_S1F_TZSID_EN_POS (30U)
+#define TZC_SEC_TZC_BMX_S1F_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S1F_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1F_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S1F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S1F_TZSID_EN_POS))
+
+/* 0x110 : tzc_bmx_s2 */
+#define TZC_SEC_TZC_BMX_S2_OFFSET (0x110)
+#define TZC_SEC_TZC_BMX_S20_TZSID_EN TZC_SEC_TZC_BMX_S20_TZSID_EN
+#define TZC_SEC_TZC_BMX_S20_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_BMX_S20_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S20_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S20_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S20_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S20_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S20_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S20_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S21_TZSID_EN TZC_SEC_TZC_BMX_S21_TZSID_EN
+#define TZC_SEC_TZC_BMX_S21_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_BMX_S21_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S21_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S21_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S21_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S21_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S21_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S21_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S22_TZSID_EN TZC_SEC_TZC_BMX_S22_TZSID_EN
+#define TZC_SEC_TZC_BMX_S22_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_BMX_S22_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S22_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S22_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S22_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S22_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S22_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S22_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S23_TZSID_EN TZC_SEC_TZC_BMX_S23_TZSID_EN
+#define TZC_SEC_TZC_BMX_S23_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_BMX_S23_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S23_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S23_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S23_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S23_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S23_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S23_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S24_TZSID_EN TZC_SEC_TZC_BMX_S24_TZSID_EN
+#define TZC_SEC_TZC_BMX_S24_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_BMX_S24_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S24_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S24_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S24_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S24_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S24_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S24_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S25_TZSID_EN TZC_SEC_TZC_BMX_S25_TZSID_EN
+#define TZC_SEC_TZC_BMX_S25_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_BMX_S25_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S25_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S25_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S25_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S25_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S25_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S25_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S26_TZSID_EN TZC_SEC_TZC_BMX_S26_TZSID_EN
+#define TZC_SEC_TZC_BMX_S26_TZSID_EN_POS (12U)
+#define TZC_SEC_TZC_BMX_S26_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S26_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S26_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S26_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S26_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S26_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S26_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S27_TZSID_EN TZC_SEC_TZC_BMX_S27_TZSID_EN
+#define TZC_SEC_TZC_BMX_S27_TZSID_EN_POS (14U)
+#define TZC_SEC_TZC_BMX_S27_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S27_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S27_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S27_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S27_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S27_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S27_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S28_TZSID_EN TZC_SEC_TZC_BMX_S28_TZSID_EN
+#define TZC_SEC_TZC_BMX_S28_TZSID_EN_POS (16U)
+#define TZC_SEC_TZC_BMX_S28_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S28_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S28_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S28_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S28_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S28_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S28_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S29_TZSID_EN TZC_SEC_TZC_BMX_S29_TZSID_EN
+#define TZC_SEC_TZC_BMX_S29_TZSID_EN_POS (18U)
+#define TZC_SEC_TZC_BMX_S29_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S29_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S29_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S29_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S29_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S29_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S29_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S2A_TZSID_EN TZC_SEC_TZC_BMX_S2A_TZSID_EN
+#define TZC_SEC_TZC_BMX_S2A_TZSID_EN_POS (20U)
+#define TZC_SEC_TZC_BMX_S2A_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S2A_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S2A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2A_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S2A_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2A_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S2B_TZSID_EN TZC_SEC_TZC_BMX_S2B_TZSID_EN
+#define TZC_SEC_TZC_BMX_S2B_TZSID_EN_POS (22U)
+#define TZC_SEC_TZC_BMX_S2B_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S2B_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S2B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2B_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S2B_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2B_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S2C_TZSID_EN TZC_SEC_TZC_BMX_S2C_TZSID_EN
+#define TZC_SEC_TZC_BMX_S2C_TZSID_EN_POS (24U)
+#define TZC_SEC_TZC_BMX_S2C_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S2C_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S2C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2C_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S2C_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2C_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S2D_TZSID_EN TZC_SEC_TZC_BMX_S2D_TZSID_EN
+#define TZC_SEC_TZC_BMX_S2D_TZSID_EN_POS (26U)
+#define TZC_SEC_TZC_BMX_S2D_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S2D_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S2D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2D_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S2D_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2D_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S2E_TZSID_EN TZC_SEC_TZC_BMX_S2E_TZSID_EN
+#define TZC_SEC_TZC_BMX_S2E_TZSID_EN_POS (28U)
+#define TZC_SEC_TZC_BMX_S2E_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S2E_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S2E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2E_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S2E_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2E_TZSID_EN_POS))
+#define TZC_SEC_TZC_BMX_S2F_TZSID_EN TZC_SEC_TZC_BMX_S2F_TZSID_EN
+#define TZC_SEC_TZC_BMX_S2F_TZSID_EN_POS (30U)
+#define TZC_SEC_TZC_BMX_S2F_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_BMX_S2F_TZSID_EN_MSK (((1U << TZC_SEC_TZC_BMX_S2F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2F_TZSID_EN_POS)
+#define TZC_SEC_TZC_BMX_S2F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_BMX_S2F_TZSID_EN_POS))
+
+/* 0x114 : tzc_bmx_s_lock */
+#define TZC_SEC_TZC_BMX_S_LOCK_OFFSET (0x114)
+#define TZC_SEC_TZC_BMX_S10_TZSID_LOCK TZC_SEC_TZC_BMX_S10_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S10_TZSID_LOCK_POS (0U)
+#define TZC_SEC_TZC_BMX_S10_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S10_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S10_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S10_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S10_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S11_TZSID_LOCK TZC_SEC_TZC_BMX_S11_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S11_TZSID_LOCK_POS (1U)
+#define TZC_SEC_TZC_BMX_S11_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S11_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S11_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S11_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S11_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S12_TZSID_LOCK TZC_SEC_TZC_BMX_S12_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S12_TZSID_LOCK_POS (2U)
+#define TZC_SEC_TZC_BMX_S12_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S12_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S12_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S12_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S12_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S13_TZSID_LOCK TZC_SEC_TZC_BMX_S13_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S13_TZSID_LOCK_POS (3U)
+#define TZC_SEC_TZC_BMX_S13_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S13_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S13_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S13_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S13_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S14_TZSID_LOCK TZC_SEC_TZC_BMX_S14_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S14_TZSID_LOCK_POS (4U)
+#define TZC_SEC_TZC_BMX_S14_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S14_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S14_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S14_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S14_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S15_TZSID_LOCK TZC_SEC_TZC_BMX_S15_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S15_TZSID_LOCK_POS (5U)
+#define TZC_SEC_TZC_BMX_S15_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S15_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S15_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S15_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S15_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S16_TZSID_LOCK TZC_SEC_TZC_BMX_S16_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S16_TZSID_LOCK_POS (6U)
+#define TZC_SEC_TZC_BMX_S16_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S16_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S16_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S16_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S16_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S17_TZSID_LOCK TZC_SEC_TZC_BMX_S17_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S17_TZSID_LOCK_POS (7U)
+#define TZC_SEC_TZC_BMX_S17_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S17_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S17_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S17_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S17_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S18_TZSID_LOCK TZC_SEC_TZC_BMX_S18_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S18_TZSID_LOCK_POS (8U)
+#define TZC_SEC_TZC_BMX_S18_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S18_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S18_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S18_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S18_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S19_TZSID_LOCK TZC_SEC_TZC_BMX_S19_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S19_TZSID_LOCK_POS (9U)
+#define TZC_SEC_TZC_BMX_S19_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S19_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S19_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S19_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S19_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S1A_TZSID_LOCK TZC_SEC_TZC_BMX_S1A_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_POS (10U)
+#define TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1A_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S1B_TZSID_LOCK TZC_SEC_TZC_BMX_S1B_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_POS (11U)
+#define TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1B_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S1C_TZSID_LOCK TZC_SEC_TZC_BMX_S1C_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_POS (12U)
+#define TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1C_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S1D_TZSID_LOCK TZC_SEC_TZC_BMX_S1D_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_POS (13U)
+#define TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1D_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S1E_TZSID_LOCK TZC_SEC_TZC_BMX_S1E_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_POS (14U)
+#define TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1E_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S1F_TZSID_LOCK TZC_SEC_TZC_BMX_S1F_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_POS (15U)
+#define TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S1F_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S20_TZSID_LOCK TZC_SEC_TZC_BMX_S20_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S20_TZSID_LOCK_POS (16U)
+#define TZC_SEC_TZC_BMX_S20_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S20_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S20_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S20_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S20_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S20_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S20_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S21_TZSID_LOCK TZC_SEC_TZC_BMX_S21_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S21_TZSID_LOCK_POS (17U)
+#define TZC_SEC_TZC_BMX_S21_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S21_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S21_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S21_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S21_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S21_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S21_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S22_TZSID_LOCK TZC_SEC_TZC_BMX_S22_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S22_TZSID_LOCK_POS (18U)
+#define TZC_SEC_TZC_BMX_S22_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S22_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S22_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S22_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S22_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S22_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S22_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S23_TZSID_LOCK TZC_SEC_TZC_BMX_S23_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S23_TZSID_LOCK_POS (19U)
+#define TZC_SEC_TZC_BMX_S23_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S23_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S23_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S23_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S23_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S23_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S23_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S24_TZSID_LOCK TZC_SEC_TZC_BMX_S24_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S24_TZSID_LOCK_POS (20U)
+#define TZC_SEC_TZC_BMX_S24_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S24_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S24_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S24_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S24_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S24_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S24_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S25_TZSID_LOCK TZC_SEC_TZC_BMX_S25_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S25_TZSID_LOCK_POS (21U)
+#define TZC_SEC_TZC_BMX_S25_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S25_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S25_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S25_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S25_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S25_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S25_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S26_TZSID_LOCK TZC_SEC_TZC_BMX_S26_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S26_TZSID_LOCK_POS (22U)
+#define TZC_SEC_TZC_BMX_S26_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S26_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S26_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S26_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S26_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S26_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S26_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S27_TZSID_LOCK TZC_SEC_TZC_BMX_S27_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S27_TZSID_LOCK_POS (23U)
+#define TZC_SEC_TZC_BMX_S27_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S27_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S27_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S27_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S27_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S27_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S27_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S28_TZSID_LOCK TZC_SEC_TZC_BMX_S28_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S28_TZSID_LOCK_POS (24U)
+#define TZC_SEC_TZC_BMX_S28_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S28_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S28_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S28_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S28_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S28_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S28_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S29_TZSID_LOCK TZC_SEC_TZC_BMX_S29_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S29_TZSID_LOCK_POS (25U)
+#define TZC_SEC_TZC_BMX_S29_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S29_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S29_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S29_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S29_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S29_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S29_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S2A_TZSID_LOCK TZC_SEC_TZC_BMX_S2A_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_POS (26U)
+#define TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2A_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S2B_TZSID_LOCK TZC_SEC_TZC_BMX_S2B_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_POS (27U)
+#define TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2B_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S2C_TZSID_LOCK TZC_SEC_TZC_BMX_S2C_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_POS (28U)
+#define TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2C_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S2D_TZSID_LOCK TZC_SEC_TZC_BMX_S2D_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_POS (29U)
+#define TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2D_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S2E_TZSID_LOCK TZC_SEC_TZC_BMX_S2E_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_POS (30U)
+#define TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2E_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_BMX_S2F_TZSID_LOCK TZC_SEC_TZC_BMX_S2F_TZSID_LOCK
+#define TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_POS (31U)
+#define TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_BMX_S2F_TZSID_LOCK_POS))
+
+/* 0x140 : tzc_ocram_tzsrg_ctrl */
+#define TZC_SEC_TZC_OCRAM_TZSRG_CTRL_OFFSET (0x140)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_POS (4U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_POS (8U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_POS (12U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_RX_ID_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_EN TZC_SEC_TZC_OCRAM_TZSRG_R0_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_EN TZC_SEC_TZC_OCRAM_TZSRG_R1_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_EN TZC_SEC_TZC_OCRAM_TZSRG_R2_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_EN TZC_SEC_TZC_OCRAM_TZSRG_RX_EN
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_POS (19U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_RX_EN_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_POS (20U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_POS (21U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_POS (22U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_LOCK_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_POS (23U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_RX_LOCK_POS))
+
+/* 0x144 : tzc_ocram_tzsrg_adr_mask */
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_OFFSET (0x144)
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x148 : tzc_ocram_tzsrg_r0 */
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_OFFSET (0x148)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_END TZC_SEC_TZC_OCRAM_TZSRG_R0_END
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_START TZC_SEC_TZC_OCRAM_TZSRG_R0_START
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R0_START_POS))
+
+/* 0x14C : tzc_ocram_tzsrg_r1 */
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_OFFSET (0x14C)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_END TZC_SEC_TZC_OCRAM_TZSRG_R1_END
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_START TZC_SEC_TZC_OCRAM_TZSRG_R1_START
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R1_START_POS))
+
+/* 0x150 : tzc_ocram_tzsrg_r2 */
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_OFFSET (0x150)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_END TZC_SEC_TZC_OCRAM_TZSRG_R2_END
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_START TZC_SEC_TZC_OCRAM_TZSRG_R2_START
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_OCRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_OCRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_OCRAM_TZSRG_R2_START_POS))
+
+/* 0x154 : tzc_ocram_tzsrg_r3 */
+#define TZC_SEC_TZC_OCRAM_TZSRG_R3_OFFSET (0x154)
+
+/* 0x180 : tzc_wram_tzsrg_ctrl */
+#define TZC_SEC_TZC_WRAM_TZSRG_CTRL_OFFSET (0x180)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_POS (4U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_POS (8U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_POS (12U)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_RX_ID_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_EN TZC_SEC_TZC_WRAM_TZSRG_R0_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_EN TZC_SEC_TZC_WRAM_TZSRG_R1_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_EN TZC_SEC_TZC_WRAM_TZSRG_R2_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_EN TZC_SEC_TZC_WRAM_TZSRG_RX_EN
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_EN_POS (19U)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_EN_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_EN_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_RX_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_RX_EN_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_EN_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_RX_EN_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_RX_EN_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_POS (20U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_POS (21U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_POS (22U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_LOCK_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_POS (23U)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_RX_LOCK_POS))
+
+/* 0x184 : tzc_wram_tzsrg_adr_mask */
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_OFFSET (0x184)
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x188 : tzc_wram_tzsrg_r0 */
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_OFFSET (0x188)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_END TZC_SEC_TZC_WRAM_TZSRG_R0_END
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_START TZC_SEC_TZC_WRAM_TZSRG_R0_START
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R0_START_POS))
+
+/* 0x18C : tzc_wram_tzsrg_r1 */
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_OFFSET (0x18C)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_END TZC_SEC_TZC_WRAM_TZSRG_R1_END
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_START TZC_SEC_TZC_WRAM_TZSRG_R1_START
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R1_START_POS))
+
+/* 0x190 : tzc_wram_tzsrg_r2 */
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_OFFSET (0x190)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_END TZC_SEC_TZC_WRAM_TZSRG_R2_END
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_START TZC_SEC_TZC_WRAM_TZSRG_R2_START
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_WRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_WRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_WRAM_TZSRG_R2_START_POS))
+
+/* 0x194 : tzc_wram_tzsrg_r3 */
+#define TZC_SEC_TZC_WRAM_TZSRG_R3_OFFSET (0x194)
+
+/* 0x198 : tzc_wifi_dbg */
+#define TZC_SEC_TZC_WIFI_DBG_OFFSET (0x198)
+#define TZC_SEC_TZC_MAC_DBG_DIS TZC_SEC_TZC_MAC_DBG_DIS
+#define TZC_SEC_TZC_MAC_DBG_DIS_POS (0U)
+#define TZC_SEC_TZC_MAC_DBG_DIS_LEN (1U)
+#define TZC_SEC_TZC_MAC_DBG_DIS_MSK (((1U << TZC_SEC_TZC_MAC_DBG_DIS_LEN) - 1) << TZC_SEC_TZC_MAC_DBG_DIS_POS)
+#define TZC_SEC_TZC_MAC_DBG_DIS_UMSK (~(((1U << TZC_SEC_TZC_MAC_DBG_DIS_LEN) - 1) << TZC_SEC_TZC_MAC_DBG_DIS_POS))
+
+/* 0x240 : tzc_pdm_ctrl */
+#define TZC_SEC_TZC_PDM_CTRL_OFFSET (0x240)
+
+/* 0x244 : tzc_uart_ctrl */
+#define TZC_SEC_TZC_UART_CTRL_OFFSET (0x244)
+
+/* 0x248 : tzc_i2c_ctrl */
+#define TZC_SEC_TZC_I2C_CTRL_OFFSET (0x248)
+
+/* 0x24C : tzc_timer_ctrl */
+#define TZC_SEC_TZC_TIMER_CTRL_OFFSET (0x24C)
+
+/* 0x250 : tzc_i2s_ctrl */
+#define TZC_SEC_TZC_I2S_CTRL_OFFSET (0x250)
+
+/* 0x280 : tzc_sf_tzsrg_ctrl */
+#define TZC_SEC_TZC_SF_TZSRG_CTRL_OFFSET (0x280)
+#define TZC_SEC_TZC_SF_TZSRG_R0_ID_EN TZC_SEC_TZC_SF_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R1_ID_EN TZC_SEC_TZC_SF_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_POS (4U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R2_ID_EN TZC_SEC_TZC_SF_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_POS (8U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R3_ID_EN TZC_SEC_TZC_SF_TZSRG_R3_ID_EN
+#define TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_POS (12U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_ID_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_RX_ID_EN TZC_SEC_TZC_SF_TZSRG_RX_ID_EN
+#define TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_POS (16U)
+#define TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_LEN (4U)
+#define TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_RX_ID_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R0_EN TZC_SEC_TZC_SF_TZSRG_R0_EN
+#define TZC_SEC_TZC_SF_TZSRG_R0_EN_POS (20U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R1_EN TZC_SEC_TZC_SF_TZSRG_R1_EN
+#define TZC_SEC_TZC_SF_TZSRG_R1_EN_POS (21U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R2_EN TZC_SEC_TZC_SF_TZSRG_R2_EN
+#define TZC_SEC_TZC_SF_TZSRG_R2_EN_POS (22U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R3_EN TZC_SEC_TZC_SF_TZSRG_R3_EN
+#define TZC_SEC_TZC_SF_TZSRG_R3_EN_POS (23U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_EN_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R3_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R3_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_RX_EN TZC_SEC_TZC_SF_TZSRG_RX_EN
+#define TZC_SEC_TZC_SF_TZSRG_RX_EN_POS (24U)
+#define TZC_SEC_TZC_SF_TZSRG_RX_EN_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_RX_EN_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_RX_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_RX_EN_POS)
+#define TZC_SEC_TZC_SF_TZSRG_RX_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_RX_EN_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_RX_EN_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R0_LOCK TZC_SEC_TZC_SF_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_SF_TZSRG_R0_LOCK_POS (25U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R1_LOCK TZC_SEC_TZC_SF_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_SF_TZSRG_R1_LOCK_POS (26U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R2_LOCK TZC_SEC_TZC_SF_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_SF_TZSRG_R2_LOCK_POS (27U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_LOCK_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R3_LOCK TZC_SEC_TZC_SF_TZSRG_R3_LOCK
+#define TZC_SEC_TZC_SF_TZSRG_R3_LOCK_POS (28U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_LOCK_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R3_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_LOCK_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R3_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_LOCK_POS))
+#define TZC_SEC_TZC_SF_TZSRG_RX_LOCK TZC_SEC_TZC_SF_TZSRG_RX_LOCK
+#define TZC_SEC_TZC_SF_TZSRG_RX_LOCK_POS (29U)
+#define TZC_SEC_TZC_SF_TZSRG_RX_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_RX_LOCK_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_RX_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_RX_LOCK_POS)
+#define TZC_SEC_TZC_SF_TZSRG_RX_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_RX_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_RX_LOCK_POS))
+
+/* 0x284 : tzc_sf_tzsrg_adr_mask */
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_OFFSET (0x284)
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK TZC_SEC_TZC_SF_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LEN (19U)
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_POS (31U)
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x288 : tzc_sf_tzsrg_r0 */
+#define TZC_SEC_TZC_SF_TZSRG_R0_OFFSET (0x288)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END TZC_SEC_TZC_SF_TZSRG_R0_END
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R0_START TZC_SEC_TZC_SF_TZSRG_R0_START
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_START_POS))
+
+/* 0x28C : tzc_sf_tzsrg_r1 */
+#define TZC_SEC_TZC_SF_TZSRG_R1_OFFSET (0x28C)
+#define TZC_SEC_TZC_SF_TZSRG_R1_END TZC_SEC_TZC_SF_TZSRG_R1_END
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R1_START TZC_SEC_TZC_SF_TZSRG_R1_START
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_START_POS))
+
+/* 0x290 : tzc_sf_tzsrg_r2 */
+#define TZC_SEC_TZC_SF_TZSRG_R2_OFFSET (0x290)
+#define TZC_SEC_TZC_SF_TZSRG_R2_END TZC_SEC_TZC_SF_TZSRG_R2_END
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R2_START TZC_SEC_TZC_SF_TZSRG_R2_START
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_START_POS))
+
+/* 0x294 : tzc_sf_tzsrg_r3 */
+#define TZC_SEC_TZC_SF_TZSRG_R3_OFFSET (0x294)
+#define TZC_SEC_TZC_SF_TZSRG_R3_END TZC_SEC_TZC_SF_TZSRG_R3_END
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_POS (0U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R3_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_END_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_END_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_END_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R3_START TZC_SEC_TZC_SF_TZSRG_R3_START
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_POS (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_LEN (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R3_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_START_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_START_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_START_POS))
+
+/* 0x298 : tzc_sf_tzsrg_msb */
+#define TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET (0x298)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_MSB TZC_SEC_TZC_SF_TZSRG_R0_END_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_POS (0U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_END_MSB_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_MSB TZC_SEC_TZC_SF_TZSRG_R0_START_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_POS (4U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R0_START_MSB_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_MSB TZC_SEC_TZC_SF_TZSRG_R1_END_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_POS (8U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_END_MSB_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_MSB TZC_SEC_TZC_SF_TZSRG_R1_START_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_POS (12U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R1_START_MSB_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_MSB TZC_SEC_TZC_SF_TZSRG_R2_END_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_POS (16U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_END_MSB_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_MSB TZC_SEC_TZC_SF_TZSRG_R2_START_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_POS (20U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R2_START_MSB_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_MSB TZC_SEC_TZC_SF_TZSRG_R3_END_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_POS (24U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_END_MSB_POS))
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_MSB TZC_SEC_TZC_SF_TZSRG_R3_START_MSB
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_POS (28U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_LEN (3U)
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_MSK (((1U << TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_POS)
+#define TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_POS))
+
+/* 0x300 : tzc_mm_bmx_tzmid */
+#define TZC_SEC_TZC_MM_BMX_TZMID_OFFSET (0x300)
+#define TZC_SEC_TZC_MMCPU_TZMID TZC_SEC_TZC_MMCPU_TZMID
+#define TZC_SEC_TZC_MMCPU_TZMID_POS (0U)
+#define TZC_SEC_TZC_MMCPU_TZMID_LEN (1U)
+#define TZC_SEC_TZC_MMCPU_TZMID_MSK (((1U << TZC_SEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_POS)
+#define TZC_SEC_TZC_MMCPU_TZMID_UMSK (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_POS))
+#define TZC_SEC_TZC_BLAI_TZMID TZC_SEC_TZC_BLAI_TZMID
+#define TZC_SEC_TZC_BLAI_TZMID_POS (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_LEN (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_MSK (((1U << TZC_SEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_POS)
+#define TZC_SEC_TZC_BLAI_TZMID_UMSK (~(((1U << TZC_SEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_POS))
+#define TZC_SEC_TZC_CODEC_TZMID TZC_SEC_TZC_CODEC_TZMID
+#define TZC_SEC_TZC_CODEC_TZMID_POS (2U)
+#define TZC_SEC_TZC_CODEC_TZMID_LEN (1U)
+#define TZC_SEC_TZC_CODEC_TZMID_MSK (((1U << TZC_SEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_POS)
+#define TZC_SEC_TZC_CODEC_TZMID_UMSK (~(((1U << TZC_SEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_POS))
+#define TZC_SEC_TZC_SUBSYS_TZMID TZC_SEC_TZC_SUBSYS_TZMID
+#define TZC_SEC_TZC_SUBSYS_TZMID_POS (3U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LEN (1U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_MSK (((1U << TZC_SEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_POS)
+#define TZC_SEC_TZC_SUBSYS_TZMID_UMSK (~(((1U << TZC_SEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_POS))
+#define TZC_SEC_TZC_X2DDMA_TZMID TZC_SEC_TZC_X2DDMA_TZMID
+#define TZC_SEC_TZC_X2DDMA_TZMID_POS (4U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LEN (1U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_MSK (((1U << TZC_SEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_POS)
+#define TZC_SEC_TZC_X2DDMA_TZMID_UMSK (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_POS))
+#define TZC_SEC_TZC_XDMA_TZMID TZC_SEC_TZC_XDMA_TZMID
+#define TZC_SEC_TZC_XDMA_TZMID_POS (5U)
+#define TZC_SEC_TZC_XDMA_TZMID_LEN (1U)
+#define TZC_SEC_TZC_XDMA_TZMID_MSK (((1U << TZC_SEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_POS)
+#define TZC_SEC_TZC_XDMA_TZMID_UMSK (~(((1U << TZC_SEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_POS))
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL TZC_SEC_TZC_MMCPU_TZMID_SEL
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_POS (16U)
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_SEL_POS)
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_SEL_POS))
+#define TZC_SEC_TZC_BLAI_TZMID_SEL TZC_SEC_TZC_BLAI_TZMID_SEL
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_POS (17U)
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_SEL_POS)
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_SEL_POS))
+#define TZC_SEC_TZC_CODEC_TZMID_SEL TZC_SEC_TZC_CODEC_TZMID_SEL
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_POS (18U)
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_SEL_POS)
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_SEL_POS))
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL TZC_SEC_TZC_SUBSYS_TZMID_SEL
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_POS (19U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_SEL_POS)
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_SEL_POS))
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL TZC_SEC_TZC_X2DDMA_TZMID_SEL
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS (20U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS)
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS))
+#define TZC_SEC_TZC_XDMA_TZMID_SEL TZC_SEC_TZC_XDMA_TZMID_SEL
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_POS (21U)
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_LEN (1U)
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_MSK (((1U << TZC_SEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_SEL_POS)
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_SEL_POS))
+
+/* 0x304 : tzc_mm_bmx_tzmid_lock */
+#define TZC_SEC_TZC_MM_BMX_TZMID_LOCK_OFFSET (0x304)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK TZC_SEC_TZC_MMCPU_TZMID_LOCK
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS (0U)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK TZC_SEC_TZC_BLAI_TZMID_LOCK
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_POS (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK TZC_SEC_TZC_CODEC_TZMID_LOCK
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_POS (2U)
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK TZC_SEC_TZC_SUBSYS_TZMID_LOCK
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_POS (3U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK TZC_SEC_TZC_X2DDMA_TZMID_LOCK
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS (4U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK TZC_SEC_TZC_XDMA_TZMID_LOCK
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_POS (5U)
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_MSK (((1U << TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_LOCK_POS))
+
+/* 0x308 : tzc_mm_bmx_s0 */
+#define TZC_SEC_TZC_MM_BMX_S0_OFFSET (0x308)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_EN TZC_SEC_TZC_MMPERI_S10_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S10_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S10_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_EN TZC_SEC_TZC_MMPERI_S11_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S11_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S11_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_EN TZC_SEC_TZC_MMPERI_S12_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S12_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S12_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_EN TZC_SEC_TZC_MMPERI_S13_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S13_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S13_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_EN TZC_SEC_TZC_MMPERI_S14_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S14_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S14_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_EN TZC_SEC_TZC_MMPERI_S15_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S15_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S15_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_EN TZC_SEC_TZC_MMPERI_S16_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_EN_POS (12U)
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S16_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S16_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_EN TZC_SEC_TZC_MMPERI_S17_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_EN_POS (14U)
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S17_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S17_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_EN TZC_SEC_TZC_MMPERI_S18_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_EN_POS (16U)
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S18_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S18_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_EN TZC_SEC_TZC_MMPERI_S19_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_EN_POS (18U)
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S19_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S19_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_EN TZC_SEC_TZC_MMPERI_S1A_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_POS (20U)
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1A_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_EN TZC_SEC_TZC_MMPERI_S1B_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_POS (22U)
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1B_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_EN TZC_SEC_TZC_MMPERI_S1C_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_POS (24U)
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1C_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_EN TZC_SEC_TZC_MMPERI_S1D_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_POS (26U)
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1D_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_EN TZC_SEC_TZC_MMPERI_S1E_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_POS (28U)
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1E_TZSID_EN_POS))
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_EN TZC_SEC_TZC_MMPERI_S1F_TZSID_EN
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_POS (30U)
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_POS)
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_POS))
+
+/* 0x30C : tzc_mm_bmx_s1 */
+#define TZC_SEC_TZC_MM_BMX_S1_OFFSET (0x30C)
+#define TZC_SEC_TZC_S10_TZSID_EN TZC_SEC_TZC_S10_TZSID_EN
+#define TZC_SEC_TZC_S10_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_S10_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S10_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_EN_POS)
+#define TZC_SEC_TZC_S10_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_EN_POS))
+#define TZC_SEC_TZC_S11_TZSID_EN TZC_SEC_TZC_S11_TZSID_EN
+#define TZC_SEC_TZC_S11_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_S11_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S11_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_EN_POS)
+#define TZC_SEC_TZC_S11_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_EN_POS))
+#define TZC_SEC_TZC_S12_TZSID_EN TZC_SEC_TZC_S12_TZSID_EN
+#define TZC_SEC_TZC_S12_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_S12_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S12_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_EN_POS)
+#define TZC_SEC_TZC_S12_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_EN_POS))
+#define TZC_SEC_TZC_S13_TZSID_EN TZC_SEC_TZC_S13_TZSID_EN
+#define TZC_SEC_TZC_S13_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_S13_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S13_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_EN_POS)
+#define TZC_SEC_TZC_S13_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_EN_POS))
+#define TZC_SEC_TZC_S14_TZSID_EN TZC_SEC_TZC_S14_TZSID_EN
+#define TZC_SEC_TZC_S14_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_S14_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S14_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_EN_POS)
+#define TZC_SEC_TZC_S14_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_EN_POS))
+#define TZC_SEC_TZC_S15_TZSID_EN TZC_SEC_TZC_S15_TZSID_EN
+#define TZC_SEC_TZC_S15_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_S15_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S15_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_EN_POS)
+#define TZC_SEC_TZC_S15_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_EN_POS))
+#define TZC_SEC_TZC_S16_TZSID_EN TZC_SEC_TZC_S16_TZSID_EN
+#define TZC_SEC_TZC_S16_TZSID_EN_POS (12U)
+#define TZC_SEC_TZC_S16_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S16_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_EN_POS)
+#define TZC_SEC_TZC_S16_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_EN_POS))
+#define TZC_SEC_TZC_S17_TZSID_EN TZC_SEC_TZC_S17_TZSID_EN
+#define TZC_SEC_TZC_S17_TZSID_EN_POS (14U)
+#define TZC_SEC_TZC_S17_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S17_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_EN_POS)
+#define TZC_SEC_TZC_S17_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_EN_POS))
+#define TZC_SEC_TZC_S18_TZSID_EN TZC_SEC_TZC_S18_TZSID_EN
+#define TZC_SEC_TZC_S18_TZSID_EN_POS (16U)
+#define TZC_SEC_TZC_S18_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S18_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_EN_POS)
+#define TZC_SEC_TZC_S18_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_EN_POS))
+#define TZC_SEC_TZC_S19_TZSID_EN TZC_SEC_TZC_S19_TZSID_EN
+#define TZC_SEC_TZC_S19_TZSID_EN_POS (18U)
+#define TZC_SEC_TZC_S19_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S19_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_EN_POS)
+#define TZC_SEC_TZC_S19_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1A_TZSID_EN TZC_SEC_TZC_S1A_TZSID_EN
+#define TZC_SEC_TZC_S1A_TZSID_EN_POS (20U)
+#define TZC_SEC_TZC_S1A_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S1A_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1A_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1B_TZSID_EN TZC_SEC_TZC_S1B_TZSID_EN
+#define TZC_SEC_TZC_S1B_TZSID_EN_POS (22U)
+#define TZC_SEC_TZC_S1B_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S1B_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1B_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1C_TZSID_EN TZC_SEC_TZC_S1C_TZSID_EN
+#define TZC_SEC_TZC_S1C_TZSID_EN_POS (24U)
+#define TZC_SEC_TZC_S1C_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S1C_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1C_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1D_TZSID_EN TZC_SEC_TZC_S1D_TZSID_EN
+#define TZC_SEC_TZC_S1D_TZSID_EN_POS (26U)
+#define TZC_SEC_TZC_S1D_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S1D_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1D_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1E_TZSID_EN TZC_SEC_TZC_S1E_TZSID_EN
+#define TZC_SEC_TZC_S1E_TZSID_EN_POS (28U)
+#define TZC_SEC_TZC_S1E_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S1E_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1E_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1F_TZSID_EN TZC_SEC_TZC_S1F_TZSID_EN
+#define TZC_SEC_TZC_S1F_TZSID_EN_POS (30U)
+#define TZC_SEC_TZC_S1F_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_S1F_TZSID_EN_MSK (((1U << TZC_SEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_EN_POS))
+
+/* 0x310 : tzc_mm_bmx_s2 */
+#define TZC_SEC_TZC_MM_BMX_S2_OFFSET (0x310)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_EN TZC_SEC_TZC_CODEC_S10_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S10_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S10_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S10_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S11_TZSID_EN TZC_SEC_TZC_CODEC_S11_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S11_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_CODEC_S11_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S11_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S11_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S11_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S11_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S12_TZSID_EN TZC_SEC_TZC_CODEC_S12_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S12_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_CODEC_S12_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S12_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S12_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S12_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S12_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S13_TZSID_EN TZC_SEC_TZC_CODEC_S13_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S13_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_CODEC_S13_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S13_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S13_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S13_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S13_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S14_TZSID_EN TZC_SEC_TZC_CODEC_S14_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S14_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_CODEC_S14_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S14_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S14_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S14_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S14_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S15_TZSID_EN TZC_SEC_TZC_CODEC_S15_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S15_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_CODEC_S15_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S15_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S15_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S15_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S15_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S16_TZSID_EN TZC_SEC_TZC_CODEC_S16_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S16_TZSID_EN_POS (12U)
+#define TZC_SEC_TZC_CODEC_S16_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S16_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S16_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S16_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S16_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S17_TZSID_EN TZC_SEC_TZC_CODEC_S17_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S17_TZSID_EN_POS (14U)
+#define TZC_SEC_TZC_CODEC_S17_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S17_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S17_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S17_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S17_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S18_TZSID_EN TZC_SEC_TZC_CODEC_S18_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S18_TZSID_EN_POS (16U)
+#define TZC_SEC_TZC_CODEC_S18_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S18_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S18_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S18_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S18_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S19_TZSID_EN TZC_SEC_TZC_CODEC_S19_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S19_TZSID_EN_POS (18U)
+#define TZC_SEC_TZC_CODEC_S19_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S19_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S19_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S19_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S19_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_EN TZC_SEC_TZC_CODEC_S1A_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_EN_POS (20U)
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1A_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1A_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_EN TZC_SEC_TZC_CODEC_S1B_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_EN_POS (22U)
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1B_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1B_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_EN TZC_SEC_TZC_CODEC_S1C_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_EN_POS (24U)
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1C_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1C_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_EN TZC_SEC_TZC_CODEC_S1D_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_EN_POS (26U)
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1D_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1D_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_EN TZC_SEC_TZC_CODEC_S1E_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_EN_POS (28U)
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1E_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1E_TZSID_EN_POS))
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_EN TZC_SEC_TZC_CODEC_S1F_TZSID_EN
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_EN_POS (30U)
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_EN_MSK (((1U << TZC_SEC_TZC_CODEC_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1F_TZSID_EN_POS)
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_CODEC_S1F_TZSID_EN_POS))
+
+/* 0x314 : tzc_mm_bmx_s_lock0 */
+#define TZC_SEC_TZC_MM_BMX_S_LOCK0_OFFSET (0x314)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_POS (0U)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S10_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_POS (1U)
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S11_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_POS (2U)
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S12_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_POS (3U)
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S13_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_POS (4U)
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S14_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_POS (5U)
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S15_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_POS (6U)
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S16_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_POS (7U)
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S17_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_POS (8U)
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S18_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_POS (9U)
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S19_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_POS (10U)
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1A_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_POS (11U)
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1B_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_POS (12U)
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1C_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_POS (13U)
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1D_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_POS (14U)
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1E_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_POS (15U)
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1F_TZSID_LOCK_POS))
+
+/* 0x318 : tzc_mm_bmx_s_lock1 */
+#define TZC_SEC_TZC_MM_BMX_S_LOCK1_OFFSET (0x318)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_LOCK TZC_SEC_TZC_CODEC_S10_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_POS (0U)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S10_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S11_TZSID_LOCK TZC_SEC_TZC_CODEC_S11_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_POS (1U)
+#define TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S11_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S12_TZSID_LOCK TZC_SEC_TZC_CODEC_S12_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_POS (2U)
+#define TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S12_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S13_TZSID_LOCK TZC_SEC_TZC_CODEC_S13_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_POS (3U)
+#define TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S13_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S14_TZSID_LOCK TZC_SEC_TZC_CODEC_S14_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_POS (4U)
+#define TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S14_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S15_TZSID_LOCK TZC_SEC_TZC_CODEC_S15_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_POS (5U)
+#define TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S15_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S16_TZSID_LOCK TZC_SEC_TZC_CODEC_S16_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_POS (6U)
+#define TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S16_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S17_TZSID_LOCK TZC_SEC_TZC_CODEC_S17_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_POS (7U)
+#define TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S17_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S18_TZSID_LOCK TZC_SEC_TZC_CODEC_S18_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_POS (8U)
+#define TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S18_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S19_TZSID_LOCK TZC_SEC_TZC_CODEC_S19_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_POS (9U)
+#define TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S19_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_POS (10U)
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1A_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_POS (11U)
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1B_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_POS (12U)
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1C_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_POS (13U)
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1D_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_POS (14U)
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1E_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_POS (15U)
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S10_TZSID_LOCK TZC_SEC_TZC_S10_TZSID_LOCK
+#define TZC_SEC_TZC_S10_TZSID_LOCK_POS (16U)
+#define TZC_SEC_TZC_S10_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S10_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S10_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S11_TZSID_LOCK TZC_SEC_TZC_S11_TZSID_LOCK
+#define TZC_SEC_TZC_S11_TZSID_LOCK_POS (17U)
+#define TZC_SEC_TZC_S11_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S11_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S11_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S12_TZSID_LOCK TZC_SEC_TZC_S12_TZSID_LOCK
+#define TZC_SEC_TZC_S12_TZSID_LOCK_POS (18U)
+#define TZC_SEC_TZC_S12_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S12_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S12_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S13_TZSID_LOCK TZC_SEC_TZC_S13_TZSID_LOCK
+#define TZC_SEC_TZC_S13_TZSID_LOCK_POS (19U)
+#define TZC_SEC_TZC_S13_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S13_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S13_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S14_TZSID_LOCK TZC_SEC_TZC_S14_TZSID_LOCK
+#define TZC_SEC_TZC_S14_TZSID_LOCK_POS (20U)
+#define TZC_SEC_TZC_S14_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S14_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S14_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S15_TZSID_LOCK TZC_SEC_TZC_S15_TZSID_LOCK
+#define TZC_SEC_TZC_S15_TZSID_LOCK_POS (21U)
+#define TZC_SEC_TZC_S15_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S15_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S15_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S16_TZSID_LOCK TZC_SEC_TZC_S16_TZSID_LOCK
+#define TZC_SEC_TZC_S16_TZSID_LOCK_POS (22U)
+#define TZC_SEC_TZC_S16_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S16_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S16_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S17_TZSID_LOCK TZC_SEC_TZC_S17_TZSID_LOCK
+#define TZC_SEC_TZC_S17_TZSID_LOCK_POS (23U)
+#define TZC_SEC_TZC_S17_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S17_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S17_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S18_TZSID_LOCK TZC_SEC_TZC_S18_TZSID_LOCK
+#define TZC_SEC_TZC_S18_TZSID_LOCK_POS (24U)
+#define TZC_SEC_TZC_S18_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S18_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S18_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S19_TZSID_LOCK TZC_SEC_TZC_S19_TZSID_LOCK
+#define TZC_SEC_TZC_S19_TZSID_LOCK_POS (25U)
+#define TZC_SEC_TZC_S19_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S19_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S19_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1A_TZSID_LOCK TZC_SEC_TZC_S1A_TZSID_LOCK
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_POS (26U)
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1B_TZSID_LOCK TZC_SEC_TZC_S1B_TZSID_LOCK
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_POS (27U)
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1C_TZSID_LOCK TZC_SEC_TZC_S1C_TZSID_LOCK
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_POS (28U)
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1D_TZSID_LOCK TZC_SEC_TZC_S1D_TZSID_LOCK
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_POS (29U)
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1E_TZSID_LOCK TZC_SEC_TZC_S1E_TZSID_LOCK
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_POS (30U)
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1F_TZSID_LOCK TZC_SEC_TZC_S1F_TZSID_LOCK
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_POS (31U)
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_LOCK_POS))
+
+/* 0x340 : tzc_l2sram_tzsrg_ctrl */
+#define TZC_SEC_TZC_L2SRAM_TZSRG_CTRL_OFFSET (0x340)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_LOCK_POS))
+
+/* 0x344 : tzc_l2sram_tzsrg_adr_mask */
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_OFFSET (0x344)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x348 : tzc_l2sram_tzsrg_r0 */
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_OFFSET (0x348)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_END TZC_SEC_TZC_L2SRAM_TZSRG_R0_END
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_START TZC_SEC_TZC_L2SRAM_TZSRG_R0_START
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R0_START_POS))
+
+/* 0x34C : tzc_l2sram_tzsrg_r1 */
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_OFFSET (0x34C)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_END TZC_SEC_TZC_L2SRAM_TZSRG_R1_END
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_START TZC_SEC_TZC_L2SRAM_TZSRG_R1_START
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R1_START_POS))
+
+/* 0x350 : tzc_l2sram_tzsrg_r2 */
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_OFFSET (0x350)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_END TZC_SEC_TZC_L2SRAM_TZSRG_R2_END
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_START TZC_SEC_TZC_L2SRAM_TZSRG_R2_START
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_L2SRAM_TZSRG_R2_START_POS))
+
+/* 0x354 : tzc_l2sram_tzsrg_r3 */
+#define TZC_SEC_TZC_L2SRAM_TZSRG_R3_OFFSET (0x354)
+
+/* 0x360 : tzc_vram_tzsrg_ctrl */
+#define TZC_SEC_TZC_VRAM_TZSRG_CTRL_OFFSET (0x360)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_EN TZC_SEC_TZC_VRAM_TZSRG_R0_EN
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_EN TZC_SEC_TZC_VRAM_TZSRG_R1_EN
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_EN TZC_SEC_TZC_VRAM_TZSRG_R2_EN
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_LOCK_POS))
+
+/* 0x364 : tzc_vram_tzsrg_adr_mask */
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_OFFSET (0x364)
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x368 : tzc_vram_tzsrg_r0 */
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_OFFSET (0x368)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_END TZC_SEC_TZC_VRAM_TZSRG_R0_END
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_START TZC_SEC_TZC_VRAM_TZSRG_R0_START
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R0_START_POS))
+
+/* 0x36C : tzc_vram_tzsrg_r1 */
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_OFFSET (0x36C)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_END TZC_SEC_TZC_VRAM_TZSRG_R1_END
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_START TZC_SEC_TZC_VRAM_TZSRG_R1_START
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R1_START_POS))
+
+/* 0x370 : tzc_vram_tzsrg_r2 */
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_OFFSET (0x370)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_END TZC_SEC_TZC_VRAM_TZSRG_R2_END
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_START TZC_SEC_TZC_VRAM_TZSRG_R2_START
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_VRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_VRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_VRAM_TZSRG_R2_START_POS))
+
+/* 0x374 : tzc_vram_tzsrg_r3 */
+#define TZC_SEC_TZC_VRAM_TZSRG_R3_OFFSET (0x374)
+
+/* 0x380 : tzc_psrama_tzsrg_ctrl */
+#define TZC_SEC_TZC_PSRAMA_TZSRG_CTRL_OFFSET (0x380)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_POS (24U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_POS (25U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_POS (26U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_LOCK_POS))
+
+/* 0x384 : tzc_psrama_tzsrg_adr_mask */
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_OFFSET (0x384)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LEN (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x388 : tzc_psrama_tzsrg_r0 */
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_OFFSET (0x388)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_END TZC_SEC_TZC_PSRAMA_TZSRG_R0_END
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_LEN (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_START TZC_SEC_TZC_PSRAMA_TZSRG_R0_START
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_LEN (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R0_START_POS))
+
+/* 0x38C : tzc_psrama_tzsrg_r1 */
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_OFFSET (0x38C)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_END TZC_SEC_TZC_PSRAMA_TZSRG_R1_END
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_LEN (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_START TZC_SEC_TZC_PSRAMA_TZSRG_R1_START
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_LEN (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R1_START_POS))
+
+/* 0x390 : tzc_psrama_tzsrg_r2 */
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_OFFSET (0x390)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_END TZC_SEC_TZC_PSRAMA_TZSRG_R2_END
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_LEN (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_START TZC_SEC_TZC_PSRAMA_TZSRG_R2_START
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_LEN (16U)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_PSRAMA_TZSRG_R2_START_POS))
+
+/* 0x394 : tzc_psrama_tzsrg_r3 */
+#define TZC_SEC_TZC_PSRAMA_TZSRG_R3_OFFSET (0x394)
+
+/* 0x3a0 : tzc_psramb_tzsrg_ctrl */
+#define TZC_SEC_TZC_PSRAMB_TZSRG_CTRL_OFFSET (0x3a0)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_POS (24U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_POS (25U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_POS (26U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_LOCK_POS))
+
+/* 0x3A4 : tzc_psramb_tzsrg_adr_mask */
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_OFFSET (0x3A4)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LEN (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x3A8 : tzc_psramb_tzsrg_r0 */
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET (0x3A8)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_END TZC_SEC_TZC_PSRAMB_TZSRG_R0_END
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_LEN (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_START TZC_SEC_TZC_PSRAMB_TZSRG_R0_START
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_LEN (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R0_START_POS))
+
+/* 0x3AC : tzc_psramb_tzsrg_r1 */
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_OFFSET (0x3AC)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_END TZC_SEC_TZC_PSRAMB_TZSRG_R1_END
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_LEN (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_START TZC_SEC_TZC_PSRAMB_TZSRG_R1_START
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_LEN (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R1_START_POS))
+
+/* 0x3B0 : tzc_psramb_tzsrg_r2 */
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_OFFSET (0x3B0)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_END TZC_SEC_TZC_PSRAMB_TZSRG_R2_END
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_LEN (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_START TZC_SEC_TZC_PSRAMB_TZSRG_R2_START
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_LEN (16U)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_PSRAMB_TZSRG_R2_START_POS))
+
+/* 0x3B4 : tzc_psramb_tzsrg_r3 */
+#define TZC_SEC_TZC_PSRAMB_TZSRG_R3_OFFSET (0x3B4)
+
+/* 0x3c0 : tzc_xram_tzsrg_ctrl */
+#define TZC_SEC_TZC_XRAM_TZSRG_CTRL_OFFSET (0x3c0)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_POS (0U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_ID_EN_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_POS (2U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_ID_EN_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_POS (4U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_LEN (2U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_ID_EN_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_EN TZC_SEC_TZC_XRAM_TZSRG_R0_EN
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_EN_POS (16U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_EN_LEN (1U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_EN_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_EN_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_EN_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_EN TZC_SEC_TZC_XRAM_TZSRG_R1_EN
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_EN_POS (17U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_EN_LEN (1U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_EN_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_EN_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_EN_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_EN TZC_SEC_TZC_XRAM_TZSRG_R2_EN
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_EN_POS (18U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_EN_LEN (1U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_EN_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_EN_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_EN_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_EN_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_EN_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_POS (24U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_LEN (1U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_LOCK_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_POS (25U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_LEN (1U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_LOCK_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_POS (26U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_LEN (1U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_LOCK_POS))
+
+/* 0x3C4 : tzc_xram_tzsrg_adr_mask */
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_OFFSET (0x3C4)
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_POS (0U)
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LEN (10U)
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_POS (16U)
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_LEN (1U)
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_ADR_MASK_LOCK_POS))
+
+/* 0x3C8 : tzc_xram_tzsrg_r0 */
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_OFFSET (0x3C8)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_END TZC_SEC_TZC_XRAM_TZSRG_R0_END
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_END_POS (0U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_END_LEN (10U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_END_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_END_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_END_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_END_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_END_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_START TZC_SEC_TZC_XRAM_TZSRG_R0_START
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_START_POS (16U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_START_LEN (10U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_START_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_START_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R0_START_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R0_START_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R0_START_POS))
+
+/* 0x3CC : tzc_xram_tzsrg_r1 */
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_OFFSET (0x3CC)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_END TZC_SEC_TZC_XRAM_TZSRG_R1_END
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_END_POS (0U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_END_LEN (10U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_END_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_END_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_END_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_END_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_END_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_START TZC_SEC_TZC_XRAM_TZSRG_R1_START
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_START_POS (16U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_START_LEN (10U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_START_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_START_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R1_START_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R1_START_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R1_START_POS))
+
+/* 0x3D0 : tzc_xram_tzsrg_r2 */
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_OFFSET (0x3D0)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_END TZC_SEC_TZC_XRAM_TZSRG_R2_END
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_END_POS (0U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_END_LEN (10U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_END_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_END_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_END_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_END_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_END_POS))
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_START TZC_SEC_TZC_XRAM_TZSRG_R2_START
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_START_POS (16U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_START_LEN (10U)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_START_MSK (((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_START_POS)
+#define TZC_SEC_TZC_XRAM_TZSRG_R2_START_UMSK (~(((1U << TZC_SEC_TZC_XRAM_TZSRG_R2_START_LEN) - 1) << TZC_SEC_TZC_XRAM_TZSRG_R2_START_POS))
+
+/* 0x3D4 : tzc_xram_tzsrg_r3 */
+#define TZC_SEC_TZC_XRAM_TZSRG_R3_OFFSET (0x3D4)
+
+/* 0xF00 : tzc_glb_ctrl_0 */
+#define TZC_SEC_TZC_GLB_CTRL_0_OFFSET (0xF00)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_MISC_TZSID_EN TZC_SEC_TZC_GLB_MISC_TZSID_EN
+#define TZC_SEC_TZC_GLB_MISC_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_GLB_MISC_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_MISC_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_MISC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_MISC_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_MISC_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_MISC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_MISC_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_EN TZC_SEC_TZC_GLB_SRAM_TZSID_EN
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_SRAM_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_SRAM_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_SRAM_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_SRAM_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_EN TZC_SEC_TZC_GLB_SWRST_TZSID_EN
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_EN_POS (12U)
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_SWRST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_SWRST_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_SWRST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_SWRST_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_BMX_TZSID_EN TZC_SEC_TZC_GLB_BMX_TZSID_EN
+#define TZC_SEC_TZC_GLB_BMX_TZSID_EN_POS (14U)
+#define TZC_SEC_TZC_GLB_BMX_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_BMX_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_BMX_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_BMX_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_BMX_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_BMX_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_BMX_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_DBG_TZSID_EN TZC_SEC_TZC_GLB_DBG_TZSID_EN
+#define TZC_SEC_TZC_GLB_DBG_TZSID_EN_POS (16U)
+#define TZC_SEC_TZC_GLB_DBG_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_DBG_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_DBG_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_DBG_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_DBG_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_DBG_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_DBG_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_EN TZC_SEC_TZC_GLB_MBIST_TZSID_EN
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_EN_POS (18U)
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_MBIST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_MBIST_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_MBIST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_MBIST_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_CLK_TZSID_EN TZC_SEC_TZC_GLB_CLK_TZSID_EN
+#define TZC_SEC_TZC_GLB_CLK_TZSID_EN_POS (20U)
+#define TZC_SEC_TZC_GLB_CLK_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_CLK_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_CLK_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_CLK_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_CLK_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_CLK_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_CLK_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_INT_TZSID_EN TZC_SEC_TZC_GLB_INT_TZSID_EN
+#define TZC_SEC_TZC_GLB_INT_TZSID_EN_POS (22U)
+#define TZC_SEC_TZC_GLB_INT_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_INT_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_INT_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_INT_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_INT_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_INT_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_INT_TZSID_EN_POS))
+#define TZC_SEC_TZC_GLB_PWR_TZSID_EN TZC_SEC_TZC_GLB_PWR_TZSID_EN
+#define TZC_SEC_TZC_GLB_PWR_TZSID_EN_POS (24U)
+#define TZC_SEC_TZC_GLB_PWR_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_GLB_PWR_TZSID_EN_MSK (((1U << TZC_SEC_TZC_GLB_PWR_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_PWR_TZSID_EN_POS)
+#define TZC_SEC_TZC_GLB_PWR_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_GLB_PWR_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_GLB_PWR_TZSID_EN_POS))
+
+/* 0xF04 : tzc_glb_ctrl_1 */
+#define TZC_SEC_TZC_GLB_CTRL_1_OFFSET (0xF04)
+
+/* 0xF08 : tzc_glb_ctrl_2 */
+#define TZC_SEC_TZC_GLB_CTRL_2_OFFSET (0xF08)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_POS (0U)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_PWRON_RST_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_POS (1U)
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_CPU_RESET_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_POS (2U)
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_SYS_RESET_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_POS (3U)
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_CPU2_RESET_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_MISC_TZSID_LOCK TZC_SEC_TZC_GLB_MISC_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_POS (4U)
+#define TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_MISC_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_POS (5U)
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_SRAM_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_POS (6U)
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_SWRST_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_BMX_TZSID_LOCK TZC_SEC_TZC_GLB_BMX_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_POS (7U)
+#define TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_BMX_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_DBG_TZSID_LOCK TZC_SEC_TZC_GLB_DBG_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_POS (8U)
+#define TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_DBG_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_POS (9U)
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_MBIST_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_CLK_TZSID_LOCK TZC_SEC_TZC_GLB_CLK_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_POS (10U)
+#define TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_CLK_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_INT_TZSID_LOCK TZC_SEC_TZC_GLB_INT_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_INT_TZSID_LOCK_POS (11U)
+#define TZC_SEC_TZC_GLB_INT_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_INT_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_INT_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_INT_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_INT_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_INT_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_INT_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_GLB_PWR_TZSID_LOCK TZC_SEC_TZC_GLB_PWR_TZSID_LOCK
+#define TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_POS (12U)
+#define TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_GLB_PWR_TZSID_LOCK_POS))
+
+/* 0xF20 : tzc_mm_ctrl_0 */
+#define TZC_SEC_TZC_MM_CTRL_0_OFFSET (0xF20)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_POS)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_PWRON_RST_TZSID_EN_POS))
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_POS)
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_EN_POS))
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_POS)
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_SYS_RESET_TZSID_EN_POS))
+#define TZC_SEC_TZC_MM_CPU0_TZSID_EN TZC_SEC_TZC_MM_CPU0_TZSID_EN
+#define TZC_SEC_TZC_MM_CPU0_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_MM_CPU0_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MM_CPU0_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MM_CPU0_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_TZSID_EN_POS)
+#define TZC_SEC_TZC_MM_CPU0_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MM_CPU0_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_TZSID_EN_POS))
+#define TZC_SEC_TZC_MM_SRAM_TZSID_EN TZC_SEC_TZC_MM_SRAM_TZSID_EN
+#define TZC_SEC_TZC_MM_SRAM_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_MM_SRAM_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MM_SRAM_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MM_SRAM_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_SRAM_TZSID_EN_POS)
+#define TZC_SEC_TZC_MM_SRAM_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MM_SRAM_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_SRAM_TZSID_EN_POS))
+#define TZC_SEC_TZC_MM_SWRST_TZSID_EN TZC_SEC_TZC_MM_SWRST_TZSID_EN
+#define TZC_SEC_TZC_MM_SWRST_TZSID_EN_POS (12U)
+#define TZC_SEC_TZC_MM_SWRST_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MM_SWRST_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MM_SWRST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_SWRST_TZSID_EN_POS)
+#define TZC_SEC_TZC_MM_SWRST_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MM_SWRST_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_SWRST_TZSID_EN_POS))
+#define TZC_SEC_TZC_MM_CLK_TZSID_EN TZC_SEC_TZC_MM_CLK_TZSID_EN
+#define TZC_SEC_TZC_MM_CLK_TZSID_EN_POS (20U)
+#define TZC_SEC_TZC_MM_CLK_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_MM_CLK_TZSID_EN_MSK (((1U << TZC_SEC_TZC_MM_CLK_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_CLK_TZSID_EN_POS)
+#define TZC_SEC_TZC_MM_CLK_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MM_CLK_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MM_CLK_TZSID_EN_POS))
+
+/* 0xF24 : tzc_mm_ctrl_1 */
+#define TZC_SEC_TZC_MM_CTRL_1_OFFSET (0xF24)
+
+/* 0xF28 : tzc_mm_ctrl_2 */
+#define TZC_SEC_TZC_MM_CTRL_2_OFFSET (0xF28)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_POS (0U)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_PWRON_RST_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_POS (1U)
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_RESET_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_POS (2U)
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_SYS_RESET_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MM_CPU0_TZSID_LOCK TZC_SEC_TZC_MM_CPU0_TZSID_LOCK
+#define TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_POS (3U)
+#define TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_CPU0_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MM_SRAM_TZSID_LOCK TZC_SEC_TZC_MM_SRAM_TZSID_LOCK
+#define TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_POS (5U)
+#define TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_SRAM_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MM_SWRST_TZSID_LOCK TZC_SEC_TZC_MM_SWRST_TZSID_LOCK
+#define TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_POS (6U)
+#define TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_SWRST_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_MM_CLK_TZSID_LOCK TZC_SEC_TZC_MM_CLK_TZSID_LOCK
+#define TZC_SEC_TZC_MM_CLK_TZSID_LOCK_POS (10U)
+#define TZC_SEC_TZC_MM_CLK_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_MM_CLK_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_MM_CLK_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_CLK_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_MM_CLK_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_MM_CLK_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_MM_CLK_TZSID_LOCK_POS))
+
+/* 0xF40 : tzc_se_ctrl_0 */
+#define TZC_SEC_TZC_SE_CTRL_0_OFFSET (0xF40)
+#define TZC_SEC_TZC_SE_SHA_TZSID_EN TZC_SEC_TZC_SE_SHA_TZSID_EN
+#define TZC_SEC_TZC_SE_SHA_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_SE_SHA_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SE_SHA_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SE_SHA_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_SHA_TZSID_EN_POS)
+#define TZC_SEC_TZC_SE_SHA_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SE_SHA_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_SHA_TZSID_EN_POS))
+#define TZC_SEC_TZC_SE_AES_TZSID_EN TZC_SEC_TZC_SE_AES_TZSID_EN
+#define TZC_SEC_TZC_SE_AES_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_SE_AES_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SE_AES_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SE_AES_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_AES_TZSID_EN_POS)
+#define TZC_SEC_TZC_SE_AES_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SE_AES_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_AES_TZSID_EN_POS))
+#define TZC_SEC_TZC_SE_TRNG_TZSID_EN TZC_SEC_TZC_SE_TRNG_TZSID_EN
+#define TZC_SEC_TZC_SE_TRNG_TZSID_EN_POS (4U)
+#define TZC_SEC_TZC_SE_TRNG_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SE_TRNG_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SE_TRNG_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_TRNG_TZSID_EN_POS)
+#define TZC_SEC_TZC_SE_TRNG_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SE_TRNG_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_TRNG_TZSID_EN_POS))
+#define TZC_SEC_TZC_SE_PKA_TZSID_EN TZC_SEC_TZC_SE_PKA_TZSID_EN
+#define TZC_SEC_TZC_SE_PKA_TZSID_EN_POS (6U)
+#define TZC_SEC_TZC_SE_PKA_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SE_PKA_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SE_PKA_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_PKA_TZSID_EN_POS)
+#define TZC_SEC_TZC_SE_PKA_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SE_PKA_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_PKA_TZSID_EN_POS))
+#define TZC_SEC_TZC_SE_CDET_TZSID_EN TZC_SEC_TZC_SE_CDET_TZSID_EN
+#define TZC_SEC_TZC_SE_CDET_TZSID_EN_POS (8U)
+#define TZC_SEC_TZC_SE_CDET_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SE_CDET_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SE_CDET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_CDET_TZSID_EN_POS)
+#define TZC_SEC_TZC_SE_CDET_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SE_CDET_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_CDET_TZSID_EN_POS))
+#define TZC_SEC_TZC_SE_GMAC_TZSID_EN TZC_SEC_TZC_SE_GMAC_TZSID_EN
+#define TZC_SEC_TZC_SE_GMAC_TZSID_EN_POS (10U)
+#define TZC_SEC_TZC_SE_GMAC_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SE_GMAC_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SE_GMAC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_GMAC_TZSID_EN_POS)
+#define TZC_SEC_TZC_SE_GMAC_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SE_GMAC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SE_GMAC_TZSID_EN_POS))
+#define TZC_SEC_TZC_SE_TZSID_CRMD TZC_SEC_TZC_SE_TZSID_CRMD
+#define TZC_SEC_TZC_SE_TZSID_CRMD_POS (12U)
+#define TZC_SEC_TZC_SE_TZSID_CRMD_LEN (1U)
+#define TZC_SEC_TZC_SE_TZSID_CRMD_MSK (((1U << TZC_SEC_TZC_SE_TZSID_CRMD_LEN) - 1) << TZC_SEC_TZC_SE_TZSID_CRMD_POS)
+#define TZC_SEC_TZC_SE_TZSID_CRMD_UMSK (~(((1U << TZC_SEC_TZC_SE_TZSID_CRMD_LEN) - 1) << TZC_SEC_TZC_SE_TZSID_CRMD_POS))
+#define TZC_SEC_TZC_SE_WDT_DLY TZC_SEC_TZC_SE_WDT_DLY
+#define TZC_SEC_TZC_SE_WDT_DLY_POS (16U)
+#define TZC_SEC_TZC_SE_WDT_DLY_LEN (16U)
+#define TZC_SEC_TZC_SE_WDT_DLY_MSK (((1U << TZC_SEC_TZC_SE_WDT_DLY_LEN) - 1) << TZC_SEC_TZC_SE_WDT_DLY_POS)
+#define TZC_SEC_TZC_SE_WDT_DLY_UMSK (~(((1U << TZC_SEC_TZC_SE_WDT_DLY_LEN) - 1) << TZC_SEC_TZC_SE_WDT_DLY_POS))
+
+/* 0xF44 : tzc_se_ctrl_1 */
+#define TZC_SEC_TZC_SE_CTRL_1_OFFSET (0xF44)
+#define TZC_SEC_TZC_SF_CR_TZSID_EN TZC_SEC_TZC_SF_CR_TZSID_EN
+#define TZC_SEC_TZC_SF_CR_TZSID_EN_POS (0U)
+#define TZC_SEC_TZC_SF_CR_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SF_CR_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SF_CR_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SF_CR_TZSID_EN_POS)
+#define TZC_SEC_TZC_SF_CR_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_CR_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SF_CR_TZSID_EN_POS))
+#define TZC_SEC_TZC_SF_SEC_TZSID_EN TZC_SEC_TZC_SF_SEC_TZSID_EN
+#define TZC_SEC_TZC_SF_SEC_TZSID_EN_POS (2U)
+#define TZC_SEC_TZC_SF_SEC_TZSID_EN_LEN (2U)
+#define TZC_SEC_TZC_SF_SEC_TZSID_EN_MSK (((1U << TZC_SEC_TZC_SF_SEC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SF_SEC_TZSID_EN_POS)
+#define TZC_SEC_TZC_SF_SEC_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_SF_SEC_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_SF_SEC_TZSID_EN_POS))
+#define TZC_SEC_TZC_SF_TZSID_CRMD TZC_SEC_TZC_SF_TZSID_CRMD
+#define TZC_SEC_TZC_SF_TZSID_CRMD_POS (4U)
+#define TZC_SEC_TZC_SF_TZSID_CRMD_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSID_CRMD_MSK (((1U << TZC_SEC_TZC_SF_TZSID_CRMD_LEN) - 1) << TZC_SEC_TZC_SF_TZSID_CRMD_POS)
+#define TZC_SEC_TZC_SF_TZSID_CRMD_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSID_CRMD_LEN) - 1) << TZC_SEC_TZC_SF_TZSID_CRMD_POS))
+
+/* 0xF48 : tzc_se_ctrl_2 */
+#define TZC_SEC_TZC_SE_CTRL_2_OFFSET (0xF48)
+#define TZC_SEC_TZC_SE_SHA_TZSID_LOCK TZC_SEC_TZC_SE_SHA_TZSID_LOCK
+#define TZC_SEC_TZC_SE_SHA_TZSID_LOCK_POS (0U)
+#define TZC_SEC_TZC_SE_SHA_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SE_SHA_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SE_SHA_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_SHA_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SE_SHA_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SE_SHA_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_SHA_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SE_AES_TZSID_LOCK TZC_SEC_TZC_SE_AES_TZSID_LOCK
+#define TZC_SEC_TZC_SE_AES_TZSID_LOCK_POS (1U)
+#define TZC_SEC_TZC_SE_AES_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SE_AES_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SE_AES_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_AES_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SE_AES_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SE_AES_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_AES_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SE_TRNG_TZSID_LOCK TZC_SEC_TZC_SE_TRNG_TZSID_LOCK
+#define TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_POS (2U)
+#define TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_TRNG_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SE_PKA_TZSID_LOCK TZC_SEC_TZC_SE_PKA_TZSID_LOCK
+#define TZC_SEC_TZC_SE_PKA_TZSID_LOCK_POS (3U)
+#define TZC_SEC_TZC_SE_PKA_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SE_PKA_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SE_PKA_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_PKA_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SE_PKA_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SE_PKA_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_PKA_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SE_CDET_TZSID_LOCK TZC_SEC_TZC_SE_CDET_TZSID_LOCK
+#define TZC_SEC_TZC_SE_CDET_TZSID_LOCK_POS (4U)
+#define TZC_SEC_TZC_SE_CDET_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SE_CDET_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SE_CDET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_CDET_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SE_CDET_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SE_CDET_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_CDET_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SE_GMAC_TZSID_LOCK TZC_SEC_TZC_SE_GMAC_TZSID_LOCK
+#define TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_POS (5U)
+#define TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_GMAC_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SE_TZSID_CRMD_LOCK TZC_SEC_TZC_SE_TZSID_CRMD_LOCK
+#define TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_POS (6U)
+#define TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_MSK (((1U << TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_POS)
+#define TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_LEN) - 1) << TZC_SEC_TZC_SE_TZSID_CRMD_LOCK_POS))
+#define TZC_SEC_TZC_SF_CR_TZSID_LOCK TZC_SEC_TZC_SF_CR_TZSID_LOCK
+#define TZC_SEC_TZC_SF_CR_TZSID_LOCK_POS (16U)
+#define TZC_SEC_TZC_SF_CR_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_CR_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SF_CR_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_CR_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SF_CR_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_CR_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_CR_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SF_SEC_TZSID_LOCK TZC_SEC_TZC_SF_SEC_TZSID_LOCK
+#define TZC_SEC_TZC_SF_SEC_TZSID_LOCK_POS (17U)
+#define TZC_SEC_TZC_SF_SEC_TZSID_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_SEC_TZSID_LOCK_MSK (((1U << TZC_SEC_TZC_SF_SEC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_SEC_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_SF_SEC_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_SEC_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_SEC_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_SF_TZSID_CRMD_LOCK TZC_SEC_TZC_SF_TZSID_CRMD_LOCK
+#define TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_POS (18U)
+#define TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_LEN (1U)
+#define TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_MSK (((1U << TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_POS)
+#define TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_LEN) - 1) << TZC_SEC_TZC_SF_TZSID_CRMD_LOCK_POS))
+
+struct tzc_sec_reg {
+ /* 0x0 reserved */
+ uint8_t RESERVED0x0[64];
+
+ /* 0x40 : tzc_rom_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r0_id_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_rom_tzsrg_r1_id_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_rom_tzsrg_r2_id_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_rom_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_rom_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r0_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_rom_tzsrg_r1_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_rom_tzsrg_r2_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t tzc_sboot_done : 4; /* [31:28], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_ctrl;
+
+ /* 0x44 : tzc_rom_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_adr_mask : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_adr_mask;
+
+ /* 0x48 : tzc_rom_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r0_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r0_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r0;
+
+ /* 0x4C : tzc_rom_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r1_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r1_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r1;
+
+ /* 0x50 : tzc_rom_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_rom_tzsrg_r2_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_rom_tzsrg_r2_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r2;
+
+ /* 0x54 : tzc_rom_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_rom_tzsrg_r3;
+
+ /* 0x58 reserved */
+ uint8_t RESERVED0x58[168];
+
+ /* 0x100 : tzc_bmx_tzmid */
+ union {
+ struct {
+ uint32_t tzc_pico_tzmid : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_mm_tzmid : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_usb_tzmid : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_wifi_tzmid : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_cci_tzmid : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_sdhm_tzmid : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_emacA_tzmid : 1; /* [ 6], r/w, 0x0 */
+ uint32_t tzc_cpu_tzmid : 1; /* [ 7], r/w, 0x0 */
+ uint32_t tzc_dma_tzmid : 1; /* [ 8], r/w, 0x0 */
+ uint32_t tzc_dma2_tzmid : 1; /* [ 9], r/w, 0x0 */
+ uint32_t tzc_lz4_tzmid : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
+ uint32_t tzc_pico_tzmid_sel : 1; /* [ 16], r/w, 0x1 */
+ uint32_t tzc_mm_tzmid_sel : 1; /* [ 17], r/w, 0x1 */
+ uint32_t tzc_usb_tzmid_sel : 1; /* [ 18], r/w, 0x1 */
+ uint32_t tzc_wifi_tzmid_sel : 1; /* [ 19], r/w, 0x1 */
+ uint32_t tzc_cci_tzmid_sel : 1; /* [ 20], r/w, 0x1 */
+ uint32_t tzc_sdhm_tzmid_sel : 1; /* [ 21], r/w, 0x1 */
+ uint32_t tzc_emacA_tzmid_sel : 1; /* [ 22], r/w, 0x1 */
+ uint32_t tzc_cpu_tzmid_sel : 1; /* [ 23], r/w, 0x1 */
+ uint32_t tzc_dma_tzmid_sel : 1; /* [ 24], r/w, 0x1 */
+ uint32_t tzc_dma2_tzmid_sel : 1; /* [ 25], r/w, 0x1 */
+ uint32_t tzc_lz4_tzmid_sel : 1; /* [ 26], r/w, 0x1 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_tzmid;
+
+ /* 0x104 : tzc_bmx_tzmid_lock */
+ union {
+ struct {
+ uint32_t tzc_pico_tzmid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_mm_tzmid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_usb_tzmid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_wifi_tzmid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_cci_tzmid_lock : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_sdhm_tzmid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_emacA_tzmid_lock : 1; /* [ 6], r/w, 0x0 */
+ uint32_t tzc_cpu_tzmid_lock : 1; /* [ 7], r/w, 0x0 */
+ uint32_t tzc_dma_tzmid_lock : 1; /* [ 8], r/w, 0x0 */
+ uint32_t tzc_dma2_tzmid_lock : 1; /* [ 9], r/w, 0x0 */
+ uint32_t tzc_lz4_tzmid_lock : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_tzmid_lock;
+
+ /* 0x108 : tzc_bmx_s0 */
+ union {
+ struct {
+ uint32_t tzc_bmx_mm_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_bmx_dma_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_bmx_dma2_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_bmx_pwr_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_bmx_sdh_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_bmx_emac_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t tzc_bmx_mm_tzsid_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_bmx_dma_tzsid_lock : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_bmx_dma2_tzsid_lock : 1; /* [ 18], r/w, 0x0 */
+ uint32_t tzc_bmx_pwr_tzsid_lock : 1; /* [ 19], r/w, 0x0 */
+ uint32_t tzc_bmx_sdh_tzsid_lock : 1; /* [ 20], r/w, 0x0 */
+ uint32_t tzc_bmx_emac_tzsid_lock : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s0;
+
+ /* 0x10C : tzc_bmx_s1 */
+ union {
+ struct {
+ uint32_t tzc_bmx_s10_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_bmx_s11_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_bmx_s12_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_bmx_s13_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_bmx_s14_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_bmx_s15_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_bmx_s16_tzsid_en : 2; /* [13:12], r/w, 0x3 */
+ uint32_t tzc_bmx_s17_tzsid_en : 2; /* [15:14], r/w, 0x3 */
+ uint32_t tzc_bmx_s18_tzsid_en : 2; /* [17:16], r/w, 0x3 */
+ uint32_t tzc_bmx_s19_tzsid_en : 2; /* [19:18], r/w, 0x3 */
+ uint32_t tzc_bmx_s1a_tzsid_en : 2; /* [21:20], r/w, 0x3 */
+ uint32_t tzc_bmx_s1b_tzsid_en : 2; /* [23:22], r/w, 0x3 */
+ uint32_t tzc_bmx_s1c_tzsid_en : 2; /* [25:24], r/w, 0x3 */
+ uint32_t tzc_bmx_s1d_tzsid_en : 2; /* [27:26], r/w, 0x3 */
+ uint32_t tzc_bmx_s1e_tzsid_en : 2; /* [29:28], r/w, 0x3 */
+ uint32_t tzc_bmx_s1f_tzsid_en : 2; /* [31:30], r/w, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s1;
+
+ /* 0x110 : tzc_bmx_s2 */
+ union {
+ struct {
+ uint32_t tzc_bmx_s20_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_bmx_s21_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_bmx_s22_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_bmx_s23_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_bmx_s24_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_bmx_s25_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_bmx_s26_tzsid_en : 2; /* [13:12], r/w, 0x3 */
+ uint32_t tzc_bmx_s27_tzsid_en : 2; /* [15:14], r/w, 0x3 */
+ uint32_t tzc_bmx_s28_tzsid_en : 2; /* [17:16], r/w, 0x3 */
+ uint32_t tzc_bmx_s29_tzsid_en : 2; /* [19:18], r/w, 0x3 */
+ uint32_t tzc_bmx_s2a_tzsid_en : 2; /* [21:20], r/w, 0x3 */
+ uint32_t tzc_bmx_s2b_tzsid_en : 2; /* [23:22], r/w, 0x3 */
+ uint32_t tzc_bmx_s2c_tzsid_en : 2; /* [25:24], r/w, 0x3 */
+ uint32_t tzc_bmx_s2d_tzsid_en : 2; /* [27:26], r/w, 0x3 */
+ uint32_t tzc_bmx_s2e_tzsid_en : 2; /* [29:28], r/w, 0x3 */
+ uint32_t tzc_bmx_s2f_tzsid_en : 2; /* [31:30], r/w, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s2;
+
+ /* 0x114 : tzc_bmx_s_lock */
+ union {
+ struct {
+ uint32_t tzc_bmx_s10_tzsid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_bmx_s11_tzsid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_bmx_s12_tzsid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_bmx_s13_tzsid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_bmx_s14_tzsid_lock : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_bmx_s15_tzsid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_bmx_s16_tzsid_lock : 1; /* [ 6], r/w, 0x0 */
+ uint32_t tzc_bmx_s17_tzsid_lock : 1; /* [ 7], r/w, 0x0 */
+ uint32_t tzc_bmx_s18_tzsid_lock : 1; /* [ 8], r/w, 0x0 */
+ uint32_t tzc_bmx_s19_tzsid_lock : 1; /* [ 9], r/w, 0x0 */
+ uint32_t tzc_bmx_s1a_tzsid_lock : 1; /* [ 10], r/w, 0x0 */
+ uint32_t tzc_bmx_s1b_tzsid_lock : 1; /* [ 11], r/w, 0x0 */
+ uint32_t tzc_bmx_s1c_tzsid_lock : 1; /* [ 12], r/w, 0x0 */
+ uint32_t tzc_bmx_s1d_tzsid_lock : 1; /* [ 13], r/w, 0x0 */
+ uint32_t tzc_bmx_s1e_tzsid_lock : 1; /* [ 14], r/w, 0x0 */
+ uint32_t tzc_bmx_s1f_tzsid_lock : 1; /* [ 15], r/w, 0x0 */
+ uint32_t tzc_bmx_s20_tzsid_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_bmx_s21_tzsid_lock : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_bmx_s22_tzsid_lock : 1; /* [ 18], r/w, 0x0 */
+ uint32_t tzc_bmx_s23_tzsid_lock : 1; /* [ 19], r/w, 0x0 */
+ uint32_t tzc_bmx_s24_tzsid_lock : 1; /* [ 20], r/w, 0x0 */
+ uint32_t tzc_bmx_s25_tzsid_lock : 1; /* [ 21], r/w, 0x0 */
+ uint32_t tzc_bmx_s26_tzsid_lock : 1; /* [ 22], r/w, 0x0 */
+ uint32_t tzc_bmx_s27_tzsid_lock : 1; /* [ 23], r/w, 0x0 */
+ uint32_t tzc_bmx_s28_tzsid_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_bmx_s29_tzsid_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_bmx_s2a_tzsid_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t tzc_bmx_s2b_tzsid_lock : 1; /* [ 27], r/w, 0x0 */
+ uint32_t tzc_bmx_s2c_tzsid_lock : 1; /* [ 28], r/w, 0x0 */
+ uint32_t tzc_bmx_s2d_tzsid_lock : 1; /* [ 29], r/w, 0x0 */
+ uint32_t tzc_bmx_s2e_tzsid_lock : 1; /* [ 30], r/w, 0x0 */
+ uint32_t tzc_bmx_s2f_tzsid_lock : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_bmx_s_lock;
+
+ /* 0x118 reserved */
+ uint8_t RESERVED0x118[40];
+
+ /* 0x140 : tzc_ocram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r0_id_en : 4; /* [ 3: 0], r/w, 0xf */
+ uint32_t tzc_ocram_tzsrg_r1_id_en : 4; /* [ 7: 4], r/w, 0xf */
+ uint32_t tzc_ocram_tzsrg_r2_id_en : 4; /* [11: 8], r/w, 0xf */
+ uint32_t tzc_ocram_tzsrg_rx_id_en : 4; /* [15:12], r/w, 0xf */
+ uint32_t tzc_ocram_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t tzc_ocram_tzsrg_rx_en : 1; /* [ 19], r/w, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r0_lock : 1; /* [ 20], r/w, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r1_lock : 1; /* [ 21], r/w, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r2_lock : 1; /* [ 22], r/w, 0x0 */
+ uint32_t tzc_ocram_tzsrg_rx_lock : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_ctrl;
+
+ /* 0x144 : tzc_ocram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_adr_mask : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_adr_mask;
+
+ /* 0x148 : tzc_ocram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r0_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r0_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r0;
+
+ /* 0x14C : tzc_ocram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r1_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r1_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r1;
+
+ /* 0x150 : tzc_ocram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_ocram_tzsrg_r2_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_ocram_tzsrg_r2_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r2;
+
+ /* 0x154 : tzc_ocram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_ocram_tzsrg_r3;
+
+ /* 0x158 reserved */
+ uint8_t RESERVED0x158[40];
+
+ /* 0x180 : tzc_wram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r0_id_en : 4; /* [ 3: 0], r/w, 0xf */
+ uint32_t tzc_wram_tzsrg_r1_id_en : 4; /* [ 7: 4], r/w, 0xf */
+ uint32_t tzc_wram_tzsrg_r2_id_en : 4; /* [11: 8], r/w, 0xf */
+ uint32_t tzc_wram_tzsrg_rx_id_en : 4; /* [15:12], r/w, 0xf */
+ uint32_t tzc_wram_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_wram_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_wram_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t tzc_wram_tzsrg_rx_en : 1; /* [ 19], r/w, 0x0 */
+ uint32_t tzc_wram_tzsrg_r0_lock : 1; /* [ 20], r/w, 0x0 */
+ uint32_t tzc_wram_tzsrg_r1_lock : 1; /* [ 21], r/w, 0x0 */
+ uint32_t tzc_wram_tzsrg_r2_lock : 1; /* [ 22], r/w, 0x0 */
+ uint32_t tzc_wram_tzsrg_rx_lock : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_ctrl;
+
+ /* 0x184 : tzc_wram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_adr_mask : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_adr_mask;
+
+ /* 0x188 : tzc_wram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r0_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_r0_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r0;
+
+ /* 0x18C : tzc_wram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r1_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_r1_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r1;
+
+ /* 0x190 : tzc_wram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_wram_tzsrg_r2_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_wram_tzsrg_r2_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r2;
+
+ /* 0x194 : tzc_wram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wram_tzsrg_r3;
+
+ /* 0x198 : tzc_wifi_dbg */
+ union {
+ struct {
+ uint32_t tzc_mac_dbg_dis : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_wifi_dbg;
+
+ /* 0x19c reserved */
+ uint8_t RESERVED0x19c[164];
+
+ /* 0x240 : tzc_pdm_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_pdm_ctrl;
+
+ /* 0x244 : tzc_uart_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_uart_ctrl;
+
+ /* 0x248 : tzc_i2c_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_i2c_ctrl;
+
+ /* 0x24C : tzc_timer_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_timer_ctrl;
+
+ /* 0x250 : tzc_i2s_ctrl */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_i2s_ctrl;
+
+ /* 0x254 reserved */
+ uint8_t RESERVED0x254[44];
+
+ /* 0x280 : tzc_sf_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r0_id_en : 4; /* [ 3: 0], r/w, 0xf */
+ uint32_t tzc_sf_tzsrg_r1_id_en : 4; /* [ 7: 4], r/w, 0xf */
+ uint32_t tzc_sf_tzsrg_r2_id_en : 4; /* [11: 8], r/w, 0xf */
+ uint32_t tzc_sf_tzsrg_r3_id_en : 4; /* [15:12], r/w, 0xf */
+ uint32_t tzc_sf_tzsrg_rx_id_en : 4; /* [19:16], r/w, 0xf */
+ uint32_t tzc_sf_tzsrg_r0_en : 1; /* [ 20], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_en : 1; /* [ 21], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_en : 1; /* [ 22], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_en : 1; /* [ 23], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_rx_en : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_r0_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_lock : 1; /* [ 27], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_lock : 1; /* [ 28], r/w, 0x0 */
+ uint32_t tzc_sf_tzsrg_rx_lock : 1; /* [ 29], r/w, 0x0 */
+ uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_ctrl;
+
+ /* 0x284 : tzc_sf_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_adr_mask : 19; /* [18: 0], r/w, 0x0 */
+ uint32_t reserved_19_30 : 12; /* [30:19], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_adr_mask_lock : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_adr_mask;
+
+ /* 0x288 : tzc_sf_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r0_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_sf_tzsrg_r0_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r0;
+
+ /* 0x28C : tzc_sf_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r1_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_sf_tzsrg_r1_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r1;
+
+ /* 0x290 : tzc_sf_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r2_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_sf_tzsrg_r2_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r2;
+
+ /* 0x294 : tzc_sf_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r3_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_sf_tzsrg_r3_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_r3;
+
+ /* 0x298 : tzc_sf_tzsrg_msb */
+ union {
+ struct {
+ uint32_t tzc_sf_tzsrg_r0_end_msb : 3; /* [ 2: 0], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r0_start_msb : 3; /* [ 6: 4], r/w, 0x0 */
+ uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_end_msb : 3; /* [10: 8], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r1_start_msb : 3; /* [14:12], r/w, 0x0 */
+ uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_end_msb : 3; /* [18:16], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r2_start_msb : 3; /* [22:20], r/w, 0x0 */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_end_msb : 3; /* [26:24], r/w, 0x0 */
+ uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
+ uint32_t tzc_sf_tzsrg_r3_start_msb : 3; /* [30:28], r/w, 0x0 */
+ uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_sf_tzsrg_msb;
+
+ /* 0x29c reserved */
+ uint8_t RESERVED0x29c[100];
+
+ /* 0x300 : tzc_mm_bmx_tzmid */
+ union {
+ struct {
+ uint32_t tzc_mmcpu_tzmid : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_blai_tzmid : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_codec_tzmid : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_subsys_tzmid : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_x2ddma_tzmid : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_xdma_tzmid : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_mmcpu_tzmid_sel : 1; /* [ 16], r/w, 0x1 */
+ uint32_t tzc_blai_tzmid_sel : 1; /* [ 17], r/w, 0x1 */
+ uint32_t tzc_codec_tzmid_sel : 1; /* [ 18], r/w, 0x1 */
+ uint32_t tzc_subsys_tzmid_sel : 1; /* [ 19], r/w, 0x1 */
+ uint32_t tzc_x2ddma_tzmid_sel : 1; /* [ 20], r/w, 0x1 */
+ uint32_t tzc_xdma_tzmid_sel : 1; /* [ 21], r/w, 0x1 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_tzmid;
+
+ /* 0x304 : tzc_mm_bmx_tzmid_lock */
+ union {
+ struct {
+ uint32_t tzc_mmcpu_tzmid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_blai_tzmid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_codec_tzmid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_subsys_tzmid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_x2ddma_tzmid_lock : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_xdma_tzmid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_tzmid_lock;
+
+ /* 0x308 : tzc_mm_bmx_s0 */
+ union {
+ struct {
+ uint32_t tzc_mmperi_s10_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_mmperi_s11_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_mmperi_s12_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_mmperi_s13_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_mmperi_s14_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_mmperi_s15_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_mmperi_s16_tzsid_en : 2; /* [13:12], r/w, 0x3 */
+ uint32_t tzc_mmperi_s17_tzsid_en : 2; /* [15:14], r/w, 0x3 */
+ uint32_t tzc_mmperi_s18_tzsid_en : 2; /* [17:16], r/w, 0x3 */
+ uint32_t tzc_mmperi_s19_tzsid_en : 2; /* [19:18], r/w, 0x3 */
+ uint32_t tzc_mmperi_s1a_tzsid_en : 2; /* [21:20], r/w, 0x3 */
+ uint32_t tzc_mmperi_s1b_tzsid_en : 2; /* [23:22], r/w, 0x3 */
+ uint32_t tzc_mmperi_s1c_tzsid_en : 2; /* [25:24], r/w, 0x3 */
+ uint32_t tzc_mmperi_s1d_tzsid_en : 2; /* [27:26], r/w, 0x3 */
+ uint32_t tzc_mmperi_s1e_tzsid_en : 2; /* [29:28], r/w, 0x3 */
+ uint32_t tzc_mmperi_s1f_tzsid_en : 2; /* [31:30], r/w, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s0;
+
+ /* 0x30C : tzc_mm_bmx_s1 */
+ union {
+ struct {
+ uint32_t tzc_s10_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_s11_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_s12_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_s13_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_s14_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_s15_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_s16_tzsid_en : 2; /* [13:12], r/w, 0x3 */
+ uint32_t tzc_s17_tzsid_en : 2; /* [15:14], r/w, 0x3 */
+ uint32_t tzc_s18_tzsid_en : 2; /* [17:16], r/w, 0x3 */
+ uint32_t tzc_s19_tzsid_en : 2; /* [19:18], r/w, 0x3 */
+ uint32_t tzc_s1a_tzsid_en : 2; /* [21:20], r/w, 0x3 */
+ uint32_t tzc_s1b_tzsid_en : 2; /* [23:22], r/w, 0x3 */
+ uint32_t tzc_s1c_tzsid_en : 2; /* [25:24], r/w, 0x3 */
+ uint32_t tzc_s1d_tzsid_en : 2; /* [27:26], r/w, 0x3 */
+ uint32_t tzc_s1e_tzsid_en : 2; /* [29:28], r/w, 0x3 */
+ uint32_t tzc_s1f_tzsid_en : 2; /* [31:30], r/w, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s1;
+
+ /* 0x310 : tzc_mm_bmx_s2 */
+ union {
+ struct {
+ uint32_t tzc_codec_s10_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_codec_s11_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_codec_s12_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_codec_s13_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_codec_s14_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_codec_s15_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_codec_s16_tzsid_en : 2; /* [13:12], r/w, 0x3 */
+ uint32_t tzc_codec_s17_tzsid_en : 2; /* [15:14], r/w, 0x3 */
+ uint32_t tzc_codec_s18_tzsid_en : 2; /* [17:16], r/w, 0x3 */
+ uint32_t tzc_codec_s19_tzsid_en : 2; /* [19:18], r/w, 0x3 */
+ uint32_t tzc_codec_s1a_tzsid_en : 2; /* [21:20], r/w, 0x3 */
+ uint32_t tzc_codec_s1b_tzsid_en : 2; /* [23:22], r/w, 0x3 */
+ uint32_t tzc_codec_s1c_tzsid_en : 2; /* [25:24], r/w, 0x3 */
+ uint32_t tzc_codec_s1d_tzsid_en : 2; /* [27:26], r/w, 0x3 */
+ uint32_t tzc_codec_s1e_tzsid_en : 2; /* [29:28], r/w, 0x3 */
+ uint32_t tzc_codec_s1f_tzsid_en : 2; /* [31:30], r/w, 0x3 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s2;
+
+ /* 0x314 : tzc_mm_bmx_s_lock0 */
+ union {
+ struct {
+ uint32_t tzc_mmperi_s10_tzsid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_mmperi_s11_tzsid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_mmperi_s12_tzsid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_mmperi_s13_tzsid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_mmperi_s14_tzsid_lock : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_mmperi_s15_tzsid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_mmperi_s16_tzsid_lock : 1; /* [ 6], r/w, 0x0 */
+ uint32_t tzc_mmperi_s17_tzsid_lock : 1; /* [ 7], r/w, 0x0 */
+ uint32_t tzc_mmperi_s18_tzsid_lock : 1; /* [ 8], r/w, 0x0 */
+ uint32_t tzc_mmperi_s19_tzsid_lock : 1; /* [ 9], r/w, 0x0 */
+ uint32_t tzc_mmperi_s1a_tzsid_lock : 1; /* [ 10], r/w, 0x0 */
+ uint32_t tzc_mmperi_s1b_tzsid_lock : 1; /* [ 11], r/w, 0x0 */
+ uint32_t tzc_mmperi_s1c_tzsid_lock : 1; /* [ 12], r/w, 0x0 */
+ uint32_t tzc_mmperi_s1d_tzsid_lock : 1; /* [ 13], r/w, 0x0 */
+ uint32_t tzc_mmperi_s1e_tzsid_lock : 1; /* [ 14], r/w, 0x0 */
+ uint32_t tzc_mmperi_s1f_tzsid_lock : 1; /* [ 15], r/w, 0x0 */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s_lock0;
+
+ /* 0x318 : tzc_mm_bmx_s_lock1 */
+ union {
+ struct {
+ uint32_t tzc_codec_s10_tzsid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_codec_s11_tzsid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_codec_s12_tzsid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_codec_s13_tzsid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_codec_s14_tzsid_lock : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_codec_s15_tzsid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_codec_s16_tzsid_lock : 1; /* [ 6], r/w, 0x0 */
+ uint32_t tzc_codec_s17_tzsid_lock : 1; /* [ 7], r/w, 0x0 */
+ uint32_t tzc_codec_s18_tzsid_lock : 1; /* [ 8], r/w, 0x0 */
+ uint32_t tzc_codec_s19_tzsid_lock : 1; /* [ 9], r/w, 0x0 */
+ uint32_t tzc_codec_s1a_tzsid_lock : 1; /* [ 10], r/w, 0x0 */
+ uint32_t tzc_codec_s1b_tzsid_lock : 1; /* [ 11], r/w, 0x0 */
+ uint32_t tzc_codec_s1c_tzsid_lock : 1; /* [ 12], r/w, 0x0 */
+ uint32_t tzc_codec_s1d_tzsid_lock : 1; /* [ 13], r/w, 0x0 */
+ uint32_t tzc_codec_s1e_tzsid_lock : 1; /* [ 14], r/w, 0x0 */
+ uint32_t tzc_codec_s1f_tzsid_lock : 1; /* [ 15], r/w, 0x0 */
+ uint32_t tzc_s10_tzsid_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_s11_tzsid_lock : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_s12_tzsid_lock : 1; /* [ 18], r/w, 0x0 */
+ uint32_t tzc_s13_tzsid_lock : 1; /* [ 19], r/w, 0x0 */
+ uint32_t tzc_s14_tzsid_lock : 1; /* [ 20], r/w, 0x0 */
+ uint32_t tzc_s15_tzsid_lock : 1; /* [ 21], r/w, 0x0 */
+ uint32_t tzc_s16_tzsid_lock : 1; /* [ 22], r/w, 0x0 */
+ uint32_t tzc_s17_tzsid_lock : 1; /* [ 23], r/w, 0x0 */
+ uint32_t tzc_s18_tzsid_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_s19_tzsid_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_s1a_tzsid_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t tzc_s1b_tzsid_lock : 1; /* [ 27], r/w, 0x0 */
+ uint32_t tzc_s1c_tzsid_lock : 1; /* [ 28], r/w, 0x0 */
+ uint32_t tzc_s1d_tzsid_lock : 1; /* [ 29], r/w, 0x0 */
+ uint32_t tzc_s1e_tzsid_lock : 1; /* [ 30], r/w, 0x0 */
+ uint32_t tzc_s1f_tzsid_lock : 1; /* [ 31], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_bmx_s_lock1;
+
+ /* 0x31c reserved */
+ uint8_t RESERVED0x31c[36];
+
+ /* 0x340 : tzc_l2sram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r0_id_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_l2sram_tzsrg_r1_id_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_l2sram_tzsrg_r2_id_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r0_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r1_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r2_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_ctrl;
+
+ /* 0x344 : tzc_l2sram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_adr_mask : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_adr_mask;
+
+ /* 0x348 : tzc_l2sram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r0_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r0_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r0;
+
+ /* 0x34C : tzc_l2sram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r1_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r1_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r1;
+
+ /* 0x350 : tzc_l2sram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_l2sram_tzsrg_r2_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_l2sram_tzsrg_r2_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r2;
+
+ /* 0x354 : tzc_l2sram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_l2sram_tzsrg_r3;
+
+ /* 0x358 reserved */
+ uint8_t RESERVED0x358[8];
+
+ /* 0x360 : tzc_vram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r0_id_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_vram_tzsrg_r1_id_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_vram_tzsrg_r2_id_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_vram_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_vram_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r0_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_vram_tzsrg_r1_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_vram_tzsrg_r2_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_ctrl;
+
+ /* 0x364 : tzc_vram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_adr_mask : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_adr_mask;
+
+ /* 0x368 : tzc_vram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r0_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r0_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r0;
+
+ /* 0x36C : tzc_vram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r1_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r1_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r1;
+
+ /* 0x370 : tzc_vram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_vram_tzsrg_r2_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_vram_tzsrg_r2_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r2;
+
+ /* 0x374 : tzc_vram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_vram_tzsrg_r3;
+
+ /* 0x378 reserved */
+ uint8_t RESERVED0x378[8];
+
+ /* 0x380 : tzc_psrama_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r0_id_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_psrama_tzsrg_r1_id_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_psrama_tzsrg_r2_id_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r0_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r1_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_psrama_tzsrg_r2_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_ctrl;
+
+ /* 0x384 : tzc_psrama_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_adr_mask : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t tzc_psrama_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_adr_mask;
+
+ /* 0x388 : tzc_psrama_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r0_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_psrama_tzsrg_r0_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r0;
+
+ /* 0x38C : tzc_psrama_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r1_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_psrama_tzsrg_r1_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r1;
+
+ /* 0x390 : tzc_psrama_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_psrama_tzsrg_r2_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_psrama_tzsrg_r2_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r2;
+
+ /* 0x394 : tzc_psrama_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psrama_tzsrg_r3;
+
+ /* 0x398 reserved */
+ uint8_t RESERVED0x398[8];
+
+ /* 0x3a0 : tzc_psramb_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r0_id_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_psramb_tzsrg_r1_id_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_psramb_tzsrg_r2_id_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r0_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r1_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_psramb_tzsrg_r2_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_ctrl;
+
+ /* 0x3A4 : tzc_psramb_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_adr_mask : 16; /* [15: 0], r/w, 0x0 */
+ uint32_t tzc_psramb_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_adr_mask;
+
+ /* 0x3A8 : tzc_psramb_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r0_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_psramb_tzsrg_r0_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r0;
+
+ /* 0x3AC : tzc_psramb_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r1_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_psramb_tzsrg_r1_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r1;
+
+ /* 0x3B0 : tzc_psramb_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_psramb_tzsrg_r2_end : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t tzc_psramb_tzsrg_r2_start : 16; /* [31:16], r/w, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r2;
+
+ /* 0x3B4 : tzc_psramb_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_psramb_tzsrg_r3;
+
+ /* 0x3b8 reserved */
+ uint8_t RESERVED0x3b8[8];
+
+ /* 0x3c0 : tzc_xram_tzsrg_ctrl */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r0_id_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_xram_tzsrg_r1_id_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_xram_tzsrg_r2_id_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r0_en : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_xram_tzsrg_r1_en : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_xram_tzsrg_r2_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r0_lock : 1; /* [ 24], r/w, 0x0 */
+ uint32_t tzc_xram_tzsrg_r1_lock : 1; /* [ 25], r/w, 0x0 */
+ uint32_t tzc_xram_tzsrg_r2_lock : 1; /* [ 26], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_ctrl;
+
+ /* 0x3C4 : tzc_xram_tzsrg_adr_mask */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_adr_mask : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_adr_mask_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_adr_mask;
+
+ /* 0x3C8 : tzc_xram_tzsrg_r0 */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r0_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r0_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r0;
+
+ /* 0x3CC : tzc_xram_tzsrg_r1 */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r1_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r1_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r1;
+
+ /* 0x3D0 : tzc_xram_tzsrg_r2 */
+ union {
+ struct {
+ uint32_t tzc_xram_tzsrg_r2_end : 10; /* [ 9: 0], r/w, 0x3ff */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t tzc_xram_tzsrg_r2_start : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r2;
+
+ /* 0x3D4 : tzc_xram_tzsrg_r3 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_xram_tzsrg_r3;
+
+ /* 0x3d8 reserved */
+ uint8_t RESERVED0x3d8[2856];
+
+ /* 0xF00 : tzc_glb_ctrl_0 */
+ union {
+ struct {
+ uint32_t tzc_glb_pwron_rst_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_glb_cpu_reset_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_glb_sys_reset_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_glb_cpu2_reset_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_glb_misc_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_glb_sram_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_glb_swrst_tzsid_en : 2; /* [13:12], r/w, 0x3 */
+ uint32_t tzc_glb_bmx_tzsid_en : 2; /* [15:14], r/w, 0x3 */
+ uint32_t tzc_glb_dbg_tzsid_en : 2; /* [17:16], r/w, 0x3 */
+ uint32_t tzc_glb_mbist_tzsid_en : 2; /* [19:18], r/w, 0x3 */
+ uint32_t tzc_glb_clk_tzsid_en : 2; /* [21:20], r/w, 0x3 */
+ uint32_t tzc_glb_int_tzsid_en : 2; /* [23:22], r/w, 0x3 */
+ uint32_t tzc_glb_pwr_tzsid_en : 2; /* [25:24], r/w, 0x3 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_glb_ctrl_0;
+
+ /* 0xF04 : tzc_glb_ctrl_1 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_glb_ctrl_1;
+
+ /* 0xF08 : tzc_glb_ctrl_2 */
+ union {
+ struct {
+ uint32_t tzc_glb_pwron_rst_tzsid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_glb_cpu_reset_tzsid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_glb_sys_reset_tzsid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_glb_cpu2_reset_tzsid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_glb_misc_tzsid_lock : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_glb_sram_tzsid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_glb_swrst_tzsid_lock : 1; /* [ 6], r/w, 0x0 */
+ uint32_t tzc_glb_bmx_tzsid_lock : 1; /* [ 7], r/w, 0x0 */
+ uint32_t tzc_glb_dbg_tzsid_lock : 1; /* [ 8], r/w, 0x0 */
+ uint32_t tzc_glb_mbist_tzsid_lock : 1; /* [ 9], r/w, 0x0 */
+ uint32_t tzc_glb_clk_tzsid_lock : 1; /* [ 10], r/w, 0x0 */
+ uint32_t tzc_glb_int_tzsid_lock : 1; /* [ 11], r/w, 0x0 */
+ uint32_t tzc_glb_pwr_tzsid_lock : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_glb_ctrl_2;
+
+ /* 0xf0c reserved */
+ uint8_t RESERVED0xf0c[20];
+
+ /* 0xF20 : tzc_mm_ctrl_0 */
+ union {
+ struct {
+ uint32_t tzc_mm_pwron_rst_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_mm_cpu0_reset_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_mm_sys_reset_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_mm_cpu0_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */
+ uint32_t tzc_mm_sram_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_mm_swrst_tzsid_en : 2; /* [13:12], r/w, 0x3 */
+ uint32_t reserved_14_19 : 6; /* [19:14], rsvd, 0x0 */
+ uint32_t tzc_mm_clk_tzsid_en : 2; /* [21:20], r/w, 0x3 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_ctrl_0;
+
+ /* 0xF24 : tzc_mm_ctrl_1 */
+ union {
+ struct {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_ctrl_1;
+
+ /* 0xF28 : tzc_mm_ctrl_2 */
+ union {
+ struct {
+ uint32_t tzc_mm_pwron_rst_tzsid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_mm_cpu0_reset_tzsid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_mm_sys_reset_tzsid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_mm_cpu0_tzsid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reserved_4 : 1; /* [ 4], rsvd, 0x0 */
+ uint32_t tzc_mm_sram_tzsid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_mm_swrst_tzsid_lock : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7_9 : 3; /* [ 9: 7], rsvd, 0x0 */
+ uint32_t tzc_mm_clk_tzsid_lock : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_mm_ctrl_2;
+
+ /* 0xf2c reserved */
+ uint8_t RESERVED0xf2c[20];
+
+ /* 0xF40 : tzc_se_ctrl_0 */
+ union {
+ struct {
+ uint32_t tzc_se_sha_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_se_aes_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_se_trng_tzsid_en : 2; /* [ 5: 4], r/w, 0x3 */
+ uint32_t tzc_se_pka_tzsid_en : 2; /* [ 7: 6], r/w, 0x3 */
+ uint32_t tzc_se_cdet_tzsid_en : 2; /* [ 9: 8], r/w, 0x3 */
+ uint32_t tzc_se_gmac_tzsid_en : 2; /* [11:10], r/w, 0x3 */
+ uint32_t tzc_se_tzsid_crmd : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
+ uint32_t tzc_se_wdt_dly : 16; /* [31:16], r/w, 0x5 */
+ } BF;
+ uint32_t WORD;
+ } tzc_se_ctrl_0;
+
+ /* 0xF44 : tzc_se_ctrl_1 */
+ union {
+ struct {
+ uint32_t tzc_sf_cr_tzsid_en : 2; /* [ 1: 0], r/w, 0x3 */
+ uint32_t tzc_sf_sec_tzsid_en : 2; /* [ 3: 2], r/w, 0x3 */
+ uint32_t tzc_sf_tzsid_crmd : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_se_ctrl_1;
+
+ /* 0xF48 : tzc_se_ctrl_2 */
+ union {
+ struct {
+ uint32_t tzc_se_sha_tzsid_lock : 1; /* [ 0], r/w, 0x0 */
+ uint32_t tzc_se_aes_tzsid_lock : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tzc_se_trng_tzsid_lock : 1; /* [ 2], r/w, 0x0 */
+ uint32_t tzc_se_pka_tzsid_lock : 1; /* [ 3], r/w, 0x0 */
+ uint32_t tzc_se_cdet_tzsid_lock : 1; /* [ 4], r/w, 0x0 */
+ uint32_t tzc_se_gmac_tzsid_lock : 1; /* [ 5], r/w, 0x0 */
+ uint32_t tzc_se_tzsid_crmd_lock : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reserved_7_15 : 9; /* [15: 7], rsvd, 0x0 */
+ uint32_t tzc_sf_cr_tzsid_lock : 1; /* [ 16], r/w, 0x0 */
+ uint32_t tzc_sf_sec_tzsid_lock : 1; /* [ 17], r/w, 0x0 */
+ uint32_t tzc_sf_tzsid_crmd_lock : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
+ } BF;
+ uint32_t WORD;
+ } tzc_se_ctrl_2;
+};
+
+typedef volatile struct tzc_sec_reg tzc_sec_reg_t;
+
+#endif /* __TZC_SEC_REG_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/port/bl808_clock.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/port/bl808_clock.c
new file mode 100644
index 00000000..7927058b
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/port/bl808_clock.c
@@ -0,0 +1,21 @@
+#include "bflb_clock.h"
+#include "bl808_clock.h"
+
+uint32_t bflb_clk_get_system_clock(uint8_t type)
+{
+ return 0;
+}
+
+uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
+{
+ if (type == BFLB_DEVICE_TYPE_UART) {
+ return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0);
+ } else if (type == BFLB_DEVICE_TYPE_SPI) {
+ return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0);
+ } else if (type == BFLB_DEVICE_TYPE_I2C) {
+ return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2C0);
+ } else if (type == BFLB_DEVICE_TYPE_SDH) {
+ return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SDH);
+ }
+ return 0;
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_aon.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_aon.c
new file mode 100644
index 00000000..d7cd0f7d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_aon.c
@@ -0,0 +1,537 @@
+/**
+ ******************************************************************************
+ * @file bl808_aon.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808_aon.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup AON
+ * @{
+ */
+
+/** @defgroup AON_Private_Macros
+ * @{
+ */
+#define AON_CLK_SET_DUMMY_WAIT \
+ { \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ }
+
+/*@} end of group AON_Private_Macros */
+
+/** @defgroup AON_Private_Types
+ * @{
+ */
+
+/*@} end of group AON_Private_Types */
+
+/** @defgroup AON_Private_Variables
+ * @{
+ */
+
+/*@} end of group AON_Private_Variables */
+
+/** @defgroup AON_Global_Variables
+ * @{
+ */
+
+/*@} end of group AON_Global_Variables */
+
+/** @defgroup AON_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group AON_Private_Fun_Declaration */
+
+/** @defgroup AON_Private_Functions
+ * @{
+ */
+
+/*@} end of group AON_Private_Functions */
+
+/** @defgroup AON_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Power on MXX band gap
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* Power up RF for PLL to work */
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ arch_delay_us(55);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power off MXX band gap
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* Power OFF */
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power on XTAL
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t timeOut = 0;
+
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ /* Polling for ready */
+ do {
+ arch_delay_us(10);
+ timeOut++;
+ tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
+ } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
+
+ if (timeOut >= 120) {
+ return TIMEOUT;
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set XTAL cap code
+ *
+ * @param capIn: Cap code in
+ * @param capOut: Cap code out
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
+ BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+ arch_delay_us(100);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get XTAL cap code
+ *
+ * @param None
+ *
+ * @return Cap code
+ *
+*******************************************************************************/
+uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
+}
+
+/****************************************************************************/ /**
+ * @brief Power off XTAL
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power on bandgap system
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* power up RF for PLL to work */
+ tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+ BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+ arch_delay_us(55);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power off bandgap system
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* power up RF for PLL to work */
+ tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+ BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+ arch_delay_us(55);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief trim dcdc11 vout
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_DCDC11_Vout(void)
+{
+ Efuse_Ana_DCDC11_Trim_Type trim;
+ uint32_t tmpVal = 0;
+
+ EF_Ctrl_Read_DCDC11_Trim(&trim);
+ if (trim.trimDcdc11VoutAonEn) {
+ if (trim.trimDcdc11VoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimDcdc11VoutAon, 4)) {
+ tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_TRIM_AON, trim.trimDcdc11VoutAon);
+ BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
+ return SUCCESS;
+ }
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief trim dcdc18 vout
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_DCDC18_Vout(void)
+{
+ Efuse_Ana_DCDC18_Trim_Type trim;
+ uint32_t tmpVal = 0;
+
+ EF_Ctrl_Read_DCDC18_Trim(&trim);
+ if (trim.trimDcdc18VoutAonEn) {
+ if (trim.trimDcdc18VoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimDcdc18VoutAon, 4)) {
+ tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_TRIM_AON, trim.trimDcdc18VoutAon);
+ BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);
+ return SUCCESS;
+ }
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief trim usb20 rcal vout
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_USB20_RCAL(void)
+{
+ Efuse_Ana_USB20RCAL_Trim_Type trim;
+ uint32_t tmpVal = 0;
+
+ //EF_Ctrl_Read_USB20RCAL_Trim(&trim); //FixZc
+ if (trim.trimUsb20rcalAonEn) {
+ if (trim.trimUsb20rcalAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimUsb20rcalAon, 6)) {
+ tmpVal = BL_RD_REG(AON_BASE, AON_PSW_IRRCV);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_USB20_RCAL_CODE_AON, trim.trimUsb20rcalAon);
+ BL_WR_REG(AON_BASE, AON_PSW_IRRCV, tmpVal);
+ return SUCCESS;
+ }
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief Power on LDO15_RF
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* ldo15rf power on */
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ arch_delay_us(90);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power off LDO15_RF
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* ldo15rf power off */
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief power on source follow regular
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* power on sfreg */
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ arch_delay_us(10);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief power off source follow regular
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* power off sfreg */
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power off the power can be shut down in PDS0
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* power off sfreg */
+ tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
+ BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ /* gating Clock */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+ tmpVal = tmpVal & (~(1 << 6));
+ tmpVal = tmpVal & (~(1 << 7));
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power on the power powered down in PDS0
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ arch_delay_us(20);
+
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ arch_delay_us(60);
+
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+ arch_delay_us(20);
+
+ /* power on wb */
+ tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
+ BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+ /* ungating Clock */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+ tmpVal = tmpVal | ((1 << 6));
+ tmpVal = tmpVal | ((1 << 7));
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief AON set DCDC11_Top voltage out
+ *
+ * @param dcdcLevel: DCDC11_Top volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_AON_DCDC_LEVEL_TYPE(dcdcLevel));
+
+ tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_SEL_AON, dcdcLevel);
+ BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
+
+ return SUCCESS;
+}
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_clock.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_clock.c
new file mode 100644
index 00000000..46b94265
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_clock.c
@@ -0,0 +1,2299 @@
+/**
+ ******************************************************************************
+ * @file bl808_clock.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808_clock.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup CLOCK
+ * @{
+ */
+
+/** @defgroup CLOCK_Private_Macros
+ * @{
+ */
+
+/*@} end of group CLOCK_Private_Macros */
+
+/** @defgroup CLOCK_Private_Types
+ * @{
+ */
+
+/*@} end of group CLOCK_Private_Types */
+
+/** @defgroup CLOCK_Private_Variables
+ * @{
+ */
+
+/*@} end of group CLOCK_Private_Variables */
+
+/** @defgroup CLOCK_Global_Variables
+ * @{
+ */
+
+/*@} end of group CLOCK_Global_Variables */
+
+/** @defgroup CLOCK_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group CLOCK_Private_Fun_Declaration */
+
+/** @defgroup CLOCK_Private_Functions
+ * @{
+ */
+
+/*@} end of group CLOCK_Private_Functions */
+
+/** @defgroup CLOCK_Public_Functions
+ * @{
+ */
+
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut)
+{
+ uint8_t xtalType = 0;
+ uint32_t tmpVal = 0;
+ uint32_t vcoFreq = 0;
+ uint32_t calculationDiv = (1 << 19);
+
+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG6), GLB_WIFIPLL_SDMIN);
+
+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+ switch (xtalType) {
+ /* Calculation method:* wifipll_sdmin / calculationDiv * xtal_freq * 1000 * 1000 / cpupll_refdiv_ratio */
+ case GLB_XTAL_NONE:
+ return (0);
+ case GLB_XTAL_24M:
+ /* 960000000 */
+ vcoFreq = tmpVal / calculationDiv * 24 * 1000 * 1000;
+ break;
+ case GLB_XTAL_32M:
+ /* 960000000 */
+ vcoFreq = tmpVal / calculationDiv * 32 * 1000 * (1000 / 2);
+ break;
+ case GLB_XTAL_38P4M:
+ /* 960000000 */
+ vcoFreq = tmpVal / calculationDiv * 384 * 100 * (1000 / 2);
+ break;
+ case GLB_XTAL_40M:
+ /* 960000000 */
+ vcoFreq = tmpVal / calculationDiv * 40 * 1000 * (1000 / 2);
+ break;
+ case GLB_XTAL_26M:
+ /* 959920000 */
+ vcoFreq = 200 * tmpVal / calculationDiv * 26 * 5000;
+ break;
+ case GLB_XTAL_RC32M:
+ /* 960000000 */
+ vcoFreq = tmpVal / calculationDiv * 32 * 1000 * (1000 / 2);
+ break;
+ default:
+ return (0);
+ }
+ } else {
+ return (0);
+ }
+
+ if ((vcoFreq >= 955000000) && (vcoFreq <= 965000000)) {
+ /* vcoFreq:959920000~960000000 */
+ return (pllOut);
+ } else {
+ return (0);
+ }
+}
+
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t pllOut)
+{
+ uint8_t xtalType = 0;
+ uint32_t tmpVal = 0;
+ uint32_t vcoFreq = 0;
+ uint32_t calculationDiv = (1 << 11);
+
+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_CPU_PLL_CFG6), CCI_CPUPLL_SDMIN);
+
+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+ switch (xtalType) {
+ /* Calculation method:xtal_freq * 1000 * cpupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */
+ case GLB_XTAL_NONE:
+ return (0);
+ case GLB_XTAL_24M:
+ /* 480000000;399996000;379998000 */
+ vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);
+ break;
+ case GLB_XTAL_32M:
+ /* 480000000;400000000;380000000 */
+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ case GLB_XTAL_38P4M:
+ /* 480000000;399998250;379996750 */
+ vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ case GLB_XTAL_40M:
+ /* 480000000;400000000;380000000 */
+ vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ case GLB_XTAL_26M:
+ /* 479997000;399997500;379996000 */
+ vcoFreq = 26 * 1000 * tmpVal / calculationDiv * (1000 / 2);
+ break;
+ case GLB_XTAL_RC32M:
+ /* 480000000;400000000;380000000 */
+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ default:
+ return (0);
+ }
+ } else {
+ return (0);
+ }
+
+ if ((vcoFreq >= 475000000) && (vcoFreq <= 485000000)) {
+ /* vcoFreq:479997000~480000000 */
+ return (pllOut / 100 * 120);
+ } else if ((vcoFreq >= 395000000 && vcoFreq <= 405000000)) {
+ /* vcoFreq:399996000~400000000 */
+ return (pllOut);
+ } else if ((vcoFreq >= 375000000 && vcoFreq <= 385000000)) {
+ /* vcoFreq:379996000~380000000 */
+ return (pllOut / 100 * 95);
+ } else {
+ return (0);
+ }
+}
+
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clockAupllType)
+{
+ uint8_t xtalType = 0;
+ uint32_t tmpVal = 0;
+ uint32_t vcoFreq = 0;
+ uint32_t calculationDiv = (1 << 11);
+
+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG6), CCI_AUPLL_SDMIN);
+
+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+ switch (xtalType) {
+ /* Calculation method:xtal_freq * 1000 * aupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */
+ case GLB_XTAL_NONE:
+ return (0);
+ case GLB_XTAL_24M:
+ /* 442365000;451582000 */
+ vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);
+ break;
+ case GLB_XTAL_32M:
+ /* 442367000;451582000 */
+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ case GLB_XTAL_38P4M:
+ /* 442364000;451579500; */
+ vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ case GLB_XTAL_40M:
+ /* 442368000;451582000 */
+ vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ case GLB_XTAL_26M:
+ /* 442368000;451578500 */
+ vcoFreq = 26 * 1000 * tmpVal / calculationDiv * (1000 / 2);
+ break;
+ case GLB_XTAL_RC32M:
+ /* 442367000;451582000 */
+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+ break;
+ default:
+ return (0);
+ }
+ } else {
+ return (0);
+ }
+
+ if ((vcoFreq >= 451000000) && (vcoFreq <= 452000000)) {
+ /* vcoFreq:451578500~451582000 */
+ vcoFreq = 451584000;
+ } else if ((vcoFreq >= 442000000) && (vcoFreq <= 443000000)) {
+ /* vcoFreq:442364000~442368000 */
+ vcoFreq = 442368000;
+ } else {
+ return (0);
+ }
+
+ switch (clockAupllType) {
+ case CLOCK_AUPLL_DIV1:
+ return (vcoFreq);
+ case CLOCK_AUPLL_DIV2:
+ return (vcoFreq / 2);
+ case CLOCK_AUPLL_DIV2P5:
+ return (vcoFreq * 2 / 5);
+ case CLOCK_AUPLL_DIV3:
+ return (vcoFreq / 3);
+ case CLOCK_AUPLL_DIV4:
+ return (vcoFreq / 4);
+ case CLOCK_AUPLL_DIV5:
+ return (vcoFreq / 5);
+ case CLOCK_AUPLL_DIV6:
+ return (vcoFreq / 6);
+ case CLOCK_AUPLL_DIV10:
+ return (vcoFreq / 10);
+ case CLOCK_AUPLL_DIV15:
+ return (vcoFreq / 15);
+ default:
+ return (0);
+ }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output()
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG1), CCI_AUPLL_POSTDIV);
+
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1) / tmpVal;
+}
+
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
+{
+ uint8_t xtalType = 0;
+ uint32_t tmpVal = 0;
+ uint32_t vcoFreq = 0;
+ uint32_t calculationDiv = (1 << 11);
+
+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG6), GLB_MIPIPLL_SDMIN);
+
+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+ switch (xtalType) {
+ /* Calculation method:xtal_freq * 1000 or 500 * mipipll_sdmin / calculationDiv * 1000 or 2000 / cpupll_refdiv_ratio */
+ case GLB_XTAL_NONE:
+ return (0);
+ case GLB_XTAL_24M:
+ /* 1500000000 */
+ vcoFreq = 24 * 1000 * tmpVal / calculationDiv * 1000;
+ break;
+ case GLB_XTAL_32M:
+ /* 1500000000 */
+ vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);
+ break;
+ case GLB_XTAL_38P4M:
+ /* 1500000000 */
+ vcoFreq = 384 * 50 * tmpVal / calculationDiv * (2000 / 2);
+ break;
+ case GLB_XTAL_40M:
+ /* 1500000000 */
+ vcoFreq = 40 * 500 * tmpVal / calculationDiv * (2000 / 2);
+ break;
+ case GLB_XTAL_26M:
+ /* 1499989000 */
+ vcoFreq = 26 * 1000 * tmpVal / calculationDiv * 1000;
+ break;
+ case GLB_XTAL_RC32M:
+ /* 1500000000 */
+ vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);
+ break;
+ default:
+ return (0);
+ }
+ } else {
+ return (0);
+ }
+
+ if ((vcoFreq >= 1490000000) && (vcoFreq <= 1510000000)) {
+ /* vcoFreq:1499989000~1500000000 */
+ return (1500000000);
+ } else {
+ return (0);
+ }
+}
+
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
+{
+ uint8_t xtalType = 0;
+ uint32_t tmpVal = 0;
+ uint32_t vcoFreq = 0;
+ uint32_t calculationDiv = (1 << 11);
+
+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG6), GLB_UHSPLL_SDMIN);
+
+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+ switch (xtalType) {
+ /* Calculation method:xtal_freq * 500 or 250 * uhspll_sdmin / calculationDiv * 2000 or 4000 / cpupll_refdiv_ratio */
+ case GLB_XTAL_NONE:
+ return (0);
+ case GLB_XTAL_24M:
+ /* 2299992000;2199996000;2100000000;1999992000;1599996000;1500000000;1399992000;1065996000;799992000;666996000;399996000 */
+ vcoFreq = 24 * 500 * tmpVal / calculationDiv * 2000;
+ break;
+ case GLB_XTAL_32M:
+ /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */
+ vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);
+ break;
+ case GLB_XTAL_38P4M:
+ /* 2299996000;2199992000;2100000000;1999996000;1599992000;1500000000;1399996000;1065992000;799996000;666992000;399992000 */
+ vcoFreq = 384 * 25 * tmpVal / calculationDiv * (4000 / 2);
+ break;
+ case GLB_XTAL_40M:
+ /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1065996000;800000000;666992000;400000000 */
+ vcoFreq = 40 * 250 * tmpVal / calculationDiv * (4000 / 2);
+ break;
+ case GLB_XTAL_26M:
+ /* 2299996000;2199996000;2099994000;1999994000;1599990000;1499988000;1399988000;1066000000;799994000;666998000;399990000 */
+ vcoFreq = 26 * 500 * tmpVal / calculationDiv * 2000;
+ break;
+ case GLB_XTAL_RC32M:
+ /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */
+ vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);
+ break;
+ default:
+ return (0);
+ }
+ } else {
+ return (0);
+ }
+
+ if ((vcoFreq >= 2295000000) && (vcoFreq <= 2305000000)) {
+ /* vcoFreq:2299992000~2300000000 */
+ return (2300000000);
+ } else if ((vcoFreq >= 2195000000) && (vcoFreq <= 2205000000)) {
+ /* vcoFreq:2199992000~2200000000 */
+ return (2200000000);
+ } else if ((vcoFreq >= 2095000000) && (vcoFreq <= 2105000000)) {
+ /* vcoFreq:2099994000~2100000000 */
+ return (2100000000);
+ } else if ((vcoFreq >= 1995000000 && vcoFreq <= 2005000000)) {
+ /* vcoFreq:1999992000~2000000000 */
+ return (2000000000);
+ } else if ((vcoFreq >= 1595000000 && vcoFreq <= 1605000000)) {
+ /* vcoFreq:1599990000~1600000000 */
+ return (1600000000);
+ } else if ((vcoFreq >= 1495000000 && vcoFreq <= 1505000000)) {
+ /* vcoFreq:1499988000~1500000000 */
+ return (1500000000);
+ } else if ((vcoFreq >= 1395000000 && vcoFreq <= 1405000000)) {
+ /* vcoFreq:1399988000~1400000000 */
+ return (1400000000);
+ } else if ((vcoFreq >= 1064000000 && vcoFreq <= 1068000000)) {
+ /* vcoFreq:1065992000~1066000000 */
+ return (1066000000);
+ } else if ((vcoFreq >= 799000000 && vcoFreq <= 801000000)) {
+ /* vcoFreq:799992000~800000000 */
+ return (800000000);
+ } else if ((vcoFreq >= 666000000 && vcoFreq <= 668000000)) {
+ /* vcoFreq:666992000~667000000 */
+ return (667000000);
+ } else if ((vcoFreq >= 399000000 && vcoFreq <= 401000000)) {
+ /* vcoFreq:399990000~400000000 */
+ return (400000000);
+ } else {
+ return (0);
+ }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Get_WIFI_PLL_Output(uint32_t pllOut)
+{
+ return Clock_Get_WIFI_PLL_Output(pllOut);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_WIFI_PLL_Output(uint32_t pllOut)
+{
+ return Clock_Get_WIFI_PLL_Output(pllOut);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_CPU_PLL_Output(uint32_t pllOut)
+{
+ return Clock_Get_CPU_PLL_Output(pllOut);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
+{
+ uint8_t xtalType = 0;
+
+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+ switch (xtalType) {
+ case GLB_XTAL_NONE:
+ return 0;
+ case GLB_XTAL_24M:
+ return 24 * 1000 * 1000;
+ case GLB_XTAL_32M:
+ return 32 * 1000 * 1000;
+ case GLB_XTAL_38P4M:
+ return 38.4 * 1000 * 1000;
+ case GLB_XTAL_40M:
+ return 40 * 1000 * 1000;
+ case GLB_XTAL_26M:
+ return 26 * 1000 * 1000;
+ case GLB_XTAL_RC32M:
+ return 32 * 1000 * 1000;
+ default:
+ return 0;
+ }
+ } else {
+ return 40 * 1000 * 1000;
+ }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* rc32m */
+ return (32 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* xtal */
+ return Clock_Xtal_Output();
+ } else {
+ return 0;
+ }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
+{
+ uint32_t tmpVal;
+ uint32_t div = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV);
+
+ if (sel == 0) {
+ /* src32K */
+ return (32 * 1000);
+ } else if (sel == 1) {
+ /* xtal 32K */
+ return (32 * 1000);
+ } else {
+ return Clock_Xtal_Output() / (div + 1);
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm wifi pll 320m */
+ return Clock_DSP_Get_WIFI_PLL_Output(320 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* mm aupll div1 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm wifi pll 240m */
+ return Clock_DSP_Get_WIFI_PLL_Output(240 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* mm aupll div2 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm wifi pll 160m */
+ return Clock_DSP_Get_WIFI_PLL_Output(160 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* cpu pll 160m */
+ return Clock_Get_CPU_PLL_Output(160 * 1000 * 1000);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* wifi pll 160m */
+ return Clock_Get_WIFI_PLL_Output(160 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* top cpu pll 160m */
+ return Clock_Get_CPU_PLL_Output(160 * 1000 * 1000);
+ } else if (sel == 2) {
+ /* top aupll div2 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);
+ } else if (sel == 3) {
+ /* aupll div2p5 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2P5);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* wifi pll 80m */
+ return Clock_Get_WIFI_PLL_Output(80 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* top cpu pll 80m */
+ return Clock_Get_CPU_PLL_Output(80 * 1000 * 1000);
+ } else if (sel == 2) {
+ /* aupll div5 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
+ } else if (sel == 3) {
+ /* aupll div6 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV6);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* cpu pll 400m */
+ return Clock_Get_CPU_PLL_Output(400 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* aupll div1 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
+ } else if (sel == 2) {
+ /* wifi pll 240m */
+ return Clock_Get_WIFI_PLL_Output(240 * 1000 * 1000);
+ } else if (sel == 3) {
+ /* wifi pll 320m */
+ return Clock_Get_WIFI_PLL_Output(320 * 1000 * 1000);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+ return (tmpVal & 0x1);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+ return ((tmpVal >> 1) & 0x1);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
+{
+ uint32_t tmpVal;
+
+ if (sel == 0) {
+ /* xclk */
+ return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+ } else if (sel == 1) {
+ /* pll */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+ sel = BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL);
+ return Clock_MCU_Clk_Mux_Output(sel);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* rc32m */
+ return (32 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* xtal */
+ return Clock_Xtal_Output();
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm mux 240m */
+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());
+ } else if (sel == 1) {
+ /* mm mux 320m */
+ return Clock_DSP_320M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_320M_Sel_Val());
+ } else if (sel == 2 || sel == 3) {
+ /* cpu pll 400m */
+ return Clock_Get_CPU_PLL_Output(400 * 1000 * 1000);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint8_t sel)
+{
+ uint32_t tmpVal;
+
+ if (sel == 0) {
+ /* xclk */
+ return Clock_DSP_XClk_Mux_Output(Clock_Get_DSP_XClk_Sel_Val());
+ } else if (sel == 1) {
+ /* pll */
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ sel = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL);
+ return Clock_DSP_Clk_Mux_Output(sel);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_MM_BCLK_Mux_Output(uint8_t sel)
+{
+ if (sel == 0 || sel == 1) {
+ /* mm xclk */
+ return Clock_DSP_XClk_Mux_Output(Clock_Get_DSP_XClk_Sel_Val());
+ } else if (sel == 2) {
+ /* mm mux 160m */
+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());
+ } else if (sel == 3) {
+ /* mm mux 240m */
+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());
+ } else {
+ return 0;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Get System Clock
+ *
+ * @param type: System clock type
+ *
+ * @return System clock value
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type)
+{
+ uint32_t clock = 0;
+ uint32_t div = 0;
+
+ switch (type) {
+ case BL_SYSTEM_CLOCK_MCU_XCLK:
+ /*!< mcu xclk clock */
+ return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+ case BL_SYSTEM_CLOCK_MCU_ROOT_CLK:
+ /*!< mcu root clock */
+ return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+
+ case BL_SYSTEM_CLOCK_MCU_CLK:
+ /*!< mcu fast clock/cpu clock */
+ clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+ div = Clock_Get_MCU_HClk_Div_Val();
+ return clock / (div + 1);
+
+ case BL_SYSTEM_CLOCK_MCU_BCLK:
+ ATTR_FALLTHROUGH();
+
+ case BL_SYSTEM_CLOCK_MCU_PBCLK:
+ /*!< mcu peri bus clock */
+ clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+ div = Clock_Get_Peri_BClk_Div_Val();
+ return clock / (div + 1);
+
+ case BL_SYSTEM_CLOCK_DSP_XCLK:
+ /*!< dsp xclk clock */
+ return Clock_DSP_XClk_Mux_Output(Clock_Get_DSP_XClk_Sel_Val());
+
+ case BL_SYSTEM_CLOCK_DSP_ROOT_CLK:
+ /*!< dsp root clock */
+ return Clock_DSP_Root_Clk_Mux_Output(Clock_Get_DSP_Root_Clk_Sel_Val());
+
+ case BL_SYSTEM_CLOCK_DSP_CLK:
+ /*!< dsp fast clock/cpu clock */
+ clock = Clock_DSP_Root_Clk_Mux_Output(Clock_Get_DSP_Root_Clk_Sel_Val());
+ div = Clock_Get_DSP_HClk_Div_Val();
+ return clock / (div + 1);
+
+ case BL_SYSTEM_CLOCK_DSP_BCLK:
+ /*!< dsp bus clock */
+ clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);
+ div = Clock_Get_DSP_BClk_Div_Val();
+ return clock / (div + 1);
+
+ case BL_SYSTEM_CLOCK_DSP_PBCLK:
+ /*!< DSP mm bus clock */
+ clock = Clock_DSP_MM_BCLK_Mux_Output(Clock_Get_DSP_MM_Bclk_Sel_Val());
+ div = Clock_Get_MM_BClk_Div_Val();
+ return clock / (div + 1);
+
+ case BL_SYSTEM_CLOCK_LP_CLK:
+ /*!< lp clock */
+ clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+ div = Clock_Get_LP_Clk_Div_Val();
+ return clock / (div + 1);
+
+ case BL_SYSTEM_CLOCK_F32K:
+ /*!< f32k clock */
+ return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+
+ case BL_SYSTEM_CLOCK_XTAL:
+ /*!< xtal clock */
+ return Clock_Xtal_Output();
+
+ default:
+ return 0;
+ }
+}
+
+static inline uint32_t Clock_EMI_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mcu pbclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+ } else if (sel == 1 || sel == 5) {
+ /* emi aupll div1 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
+ } else if (sel == 2 || sel == 6) {
+ /* emi wifi pll 320m */
+ return Clock_EMI_Get_WIFI_PLL_Output(320 * 1000 * 1000);
+ } else if (sel == 3 || sel == 7) {
+ /* emi cpu pll 400m */
+ return Clock_EMI_Get_CPU_PLL_Output(400 * 1000 * 1000);
+ } else if (sel == 4) {
+ /* emi cpu pll 200m */
+ return Clock_EMI_Get_CPU_PLL_Output(200 * 1000 * 1000);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_EMI_Clk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_EMI_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL);
+}
+
+static inline uint32_t Clock_Get_EMI_Clk(void)
+{
+ uint32_t div = 0;
+
+ div = Clock_Get_EMI_Clk_Div_Val();
+
+ return Clock_EMI_Clk_Mux_Output(Clock_Get_EMI_Clk_Sel_Val()) / (div + 1);
+}
+
+static inline uint32_t Clock_PARAMB_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* emi cpu pll 400m */
+ return Clock_EMI_Get_CPU_PLL_Output(400 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* emi wifi pll 320m */
+ return Clock_EMI_Get_WIFI_PLL_Output(320 * 1000 * 1000);
+ } else if (sel == 2 || sel == 3) {
+ /* mm aupll div1 clk */
+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_PSRAMB_Clk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_PSRAMB_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL);
+}
+
+static inline uint32_t Clock_Get_PSRAMB_Clk(void)
+{
+ uint32_t div = 0;
+
+ div = Clock_Get_PSRAMB_Clk_Div_Val();
+
+ return Clock_PARAMB_Clk_Mux_Output(Clock_Get_PSRAMB_Clk_Sel_Val()) / (div + 1);
+}
+
+static inline uint32_t Clock_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm mux 160m */
+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());
+ } else if (sel == 1) {
+ /* mm mux 240m */
+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());
+ } else if (sel == 2) {
+ /* cpu pll 400m */
+ return Clock_Get_CPU_PLL_Output(400 * 1000 * 1000);
+ } else if (sel == 3) {
+ /* mm xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);
+ ;
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_Clk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_SEL);
+}
+
+static inline uint32_t Clock_Get_Clk(void)
+{
+ uint32_t div = 0;
+
+ div = Clock_Get_Clk_Div_Val();
+
+ return Clock_Clk_Mux_Output(Clock_Get_Clk_Sel_Val()) / (div + 1);
+}
+
+static inline uint32_t Clock_H264_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm mux 160m */
+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());
+ } else if (sel == 1) {
+ /* mm mux 240m */
+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());
+ } else if (sel == 2 || sel == 3) {
+ /* mm mux 320m */
+ return Clock_DSP_320M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_320M_Sel_Val());
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_H264_Clk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_H264_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL);
+}
+
+static inline uint32_t Clock_Get_H264_Clk(void)
+{
+ uint32_t div = 0;
+
+ div = Clock_Get_H264_Clk_Div_Val();
+
+ return Clock_H264_Clk_Mux_Output(Clock_Get_H264_Clk_Sel_Val()) / (div + 1);
+}
+
+static inline uint32_t Clock_BLAI_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm mux 160m */
+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());
+ } else if (sel == 1) {
+ /* mm mux 240m */
+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());
+ } else if (sel == 2 || sel == 3) {
+ /* mm mux 320m */
+ return Clock_DSP_320M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_320M_Sel_Val());
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_BLAI_Clk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_BLAI_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL);
+}
+
+static inline uint32_t Clock_Get_BLAI_Clk(void)
+{
+ uint32_t div = 0;
+
+ div = Clock_Get_BLAI_Clk_Div_Val();
+
+ return Clock_BLAI_Clk_Mux_Output(Clock_Get_BLAI_Clk_Sel_Val()) / (div + 1);
+}
+
+static inline uint8_t Clock_Get_MIPI_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO);
+}
+
+static inline uint32_t Clock_MIPI_Clk_Mux_Output(void)
+{
+ return Clock_Get_MIPI_PLL_Output();
+}
+
+static inline uint32_t Clock_Display_Clk_Mux_Output(uint8_t sel)
+{
+ uint32_t div = 0;
+
+ if (sel == 0) {
+ /* displ pll clk */
+ div = Clock_Get_MIPI_Div_Val();
+ return Clock_MIPI_Clk_Mux_Output() / div;
+ } else if (sel == 1) {
+ /* mm xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_Display_Clk_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_Display_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL);
+}
+
+static inline uint32_t Clock_Get_Display_Clk(void)
+{
+ uint32_t div = 0;
+
+ div = Clock_Get_Display_Clk_Div_Val();
+
+ return Clock_Display_Clk_Mux_Output(Clock_Get_Display_Clk_Sel_Val()) / (div + 1);
+}
+
+static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mcu pbclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+ } else if (sel == 1) {
+ /* mux 160Mkz */
+ return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+ } else {
+ /* xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
+ }
+}
+
+static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+
+ return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL));
+}
+
+static inline uint8_t Clock_Get_UART_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
+}
+
+static inline uint32_t Clock_DSP_UART_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm pbclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK);
+ } else if (sel == 1) {
+ /* mm mux 160m */
+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());
+ } else if (sel == 2 || sel == 3) {
+ /* mm xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_DSP_UART_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_DSP_UART0_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_DSP_UART1_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV);
+}
+
+static inline uint32_t Clock_PKA_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mcu pbclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+ } else if (sel == 1) {
+ /* mux 160m */
+ return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_PKA_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL);
+}
+
+static inline uint32_t Clock_IR_Clk_Mux_Output(void)
+{
+ /* xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
+}
+
+static inline uint8_t Clock_Get_IR_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
+}
+
+static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* wifi pll 120m */
+ return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* xtal */
+ return Clock_Xtal_Output();
+ } else if (sel == 2) {
+ /* wifi pll 120m */
+ return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);
+ } else {
+ /* cpu pll 100m */
+ return Clock_Get_CPU_PLL_Output(100 * 1000 * 1000);
+ }
+}
+
+static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* sf sel2 */
+ return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val());
+ } else if (sel == 1) {
+ /* mux 80m */
+ return Clock_80M_Clk_Mux_Output(Clock_Get_Muxpll_80M_Sel_Val());
+ } else if (sel == 2) {
+ /* mcu pbclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+ } else {
+ /* wifi 96m */
+ return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
+ }
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SF_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);
+}
+
+static inline uint32_t Clock_SPI_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mux 160Mkz */
+ return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+ } else {
+ /* xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
+ }
+}
+
+static inline uint8_t Clock_Get_SPI_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SPI_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
+}
+
+static inline uint32_t Clock_DSP_SPI_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm mux 160m */
+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());
+ } else if (sel == 1) {
+ /* mm xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_DSP_SPI_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_DSP_SPI_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV);
+}
+
+static inline uint32_t Clock_I2C_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mcu pbclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+ } else if (sel == 1) {
+ /* xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_I2C_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_I2C_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
+}
+
+static inline uint32_t Clock_DSP_I2C_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* mm pbclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK);
+ } else {
+ /* mm xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);
+ }
+}
+
+static inline uint8_t Clock_Get_DSP_I2C_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_DSP_I2C0_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_DSP_I2C1_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* audio pll clk */
+ return Clock_Get_Audio_PLL_Output();
+ } else {
+ /* xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
+ }
+}
+
+static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_GPADC_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
+{
+ uint32_t div = 0;
+
+ if (sel == 1) {
+ /* f32k bclk */
+ return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+ } else {
+ div = Clock_Get_GPADC_Div_Val();
+ return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1);
+ }
+}
+
+static inline uint32_t Clock_PDM_Clk_Mux_Output(void)
+{
+ /* audio pll clk */
+ return Clock_Get_Audio_PLL_Output();
+}
+
+static inline uint8_t Clock_Get_PDM_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV);
+}
+
+static inline uint32_t Clock_I2S_Clk_Mux_Output(void)
+{
+ /* audio pll clk */
+ return Clock_Get_Audio_PLL_Output();
+}
+
+static inline uint8_t Clock_Get_I2S_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV);
+}
+
+static inline uint32_t Clock_ADC_Clk_Mux_Output(void)
+{
+ /* audio pll clk */
+ return Clock_Get_Audio_PLL_Output();
+}
+
+static inline uint8_t Clock_Get_ADC_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS);
+}
+
+static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* wifi pll 32m */
+ return Clock_Get_WIFI_PLL_Output(32 * 1000 * 1000);
+ } else if (sel == 1) {
+ /* xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
+ } else {
+ /* audio pll clk */
+ return Clock_Get_Audio_PLL_Output();
+ }
+}
+
+static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
+}
+
+static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
+}
+
+static inline uint32_t Clock_DAC_Clk_Mux_Output(void)
+{
+ /* audio pll clk */
+ return Clock_Get_Audio_PLL_Output();
+}
+
+static inline uint8_t Clock_Get_DAC_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV);
+}
+
+static inline uint32_t Clock_SDH_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* wifi pll 96m */
+ return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
+ } else {
+ /* cpu pll 100m */
+ return Clock_Get_CPU_PLL_Output(100 * 1000 * 1000);
+ }
+}
+
+static inline uint8_t Clock_Get_SDH_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SDH_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV);
+}
+
+static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel)
+{
+ if (sel == 0) {
+ /* xclk */
+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
+ } else if (sel == 1) {
+ /* wifi pull 960m */
+ return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
+ } else if (sel == 2 || sel == 3) {
+ /* cpu pll 100m */
+ return Clock_Get_CPU_PLL_Output(100 * 1000 * 1000);
+ } else {
+ return 0;
+ }
+}
+
+static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
+}
+
+static inline uint8_t Clock_Get_CAM_Div_Val(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
+}
+
+/****************************************************************************/ /**
+
+ * @brief Get Audio ADC Clock
+ *
+ * @return Audio ADC clock value
+ *
+*******************************************************************************/
+static inline uint32_t Clock_Audio_ADC_Clock_Get(void)
+{
+ uint32_t clock = 0;
+ uint32_t div = 0;
+
+ clock = Clock_ADC_Clk_Mux_Output();
+ div = Clock_Get_ADC_Div_Val();
+
+ return clock / (div + 1);
+}
+
+/****************************************************************************/ /**
+
+ * @brief Get Audio DAC Clock
+ *
+ * @return Audio DAC clock value
+ *
+*******************************************************************************/
+static inline uint32_t Clock_Audio_DAC_Clock_Get(void)
+{
+ uint32_t clock = 0;
+ uint32_t div = 0;
+
+ clock = Clock_DAC_Clk_Mux_Output();
+ div = Clock_Get_DAC_Div_Val();
+
+ return clock / (div + 1);
+}
+
+/****************************************************************************/ /**
+
+ * @brief Get Peripheral1 Clock
+ *
+ * @param type: Peripheral1 clock type
+ *
+ * @return Peripheral1 clock value
+ *
+*******************************************************************************/
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
+{
+ uint32_t clock = 0;
+ uint32_t div = 0;
+
+ switch (type) {
+ /*!< uart0 clock */
+ case BL_PERIPHERAL_CLOCK_UART0:
+ ATTR_FALLTHROUGH();
+
+ /*!< uart1 clock */
+ case BL_PERIPHERAL_CLOCK_UART1:
+ ATTR_FALLTHROUGH();
+
+ /*!< uart2 clock */
+ case BL_PERIPHERAL_CLOCK_UART2:
+ clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val());
+ div = Clock_Get_UART_Div_Val();
+ return clock / (div + 1);
+
+ /*!< uart3 clock */
+ case BL_PERIPHERAL_CLOCK_UART3:
+ clock = Clock_DSP_UART_Clk_Mux_Output(Clock_Get_DSP_UART_Clk_Sel_Val());
+ div = Clock_Get_DSP_UART0_Div_Val();
+ return clock / (div + 1);
+
+#ifndef CONFIG_SUPPORT_UART_CLOCK_GET_ONLY
+ /*!< spi0 clock */
+ case BL_PERIPHERAL_CLOCK_SPI0:
+ clock = Clock_SPI_Clk_Mux_Output(Clock_Get_SPI_Clk_Sel_Val());
+ div = Clock_Get_SPI_Div_Val();
+ return clock / (div + 1);
+
+ /*!< spi1 clock */
+ case BL_PERIPHERAL_CLOCK_SPI1:
+ clock = Clock_DSP_SPI_Clk_Mux_Output(Clock_Get_DSP_SPI_Clk_Sel_Val());
+ div = Clock_Get_DSP_SPI_Div_Val();
+ return clock / (div + 1);
+
+ /*!< i2c0 clock */
+ case BL_PERIPHERAL_CLOCK_I2C0:
+ ATTR_FALLTHROUGH();
+
+ /*!< i2c1 clock */
+ case BL_PERIPHERAL_CLOCK_I2C1:
+ clock = Clock_I2C_Clk_Mux_Output(Clock_Get_I2C_Clk_Sel_Val());
+ div = Clock_Get_I2C_Div_Val();
+ return clock / (div + 1);
+
+ /*!< i2c2 clock */
+ case BL_PERIPHERAL_CLOCK_I2C2:
+ clock = Clock_DSP_I2C_Clk_Mux_Output(Clock_Get_DSP_I2C_Clk_Sel_Val());
+ div = Clock_Get_DSP_I2C0_Div_Val();
+ return clock / (div + 1);
+
+ /*!< i2c3 clock */
+ case BL_PERIPHERAL_CLOCK_I2C3:
+ clock = Clock_DSP_I2C_Clk_Mux_Output(Clock_Get_DSP_I2C_Clk_Sel_Val());
+ div = Clock_Get_DSP_I2C1_Div_Val();
+ return clock / (div + 1);
+
+ /*!< PSRAMA clock */
+ case BL_PERIPHERAL_CLOCK_PSRAMA:
+ return Clock_Get_UHS_PLL_Output();
+
+ /*!< PSRAMB clock */
+ case BL_PERIPHERAL_CLOCK_PSRAMB:
+ return Clock_Get_PSRAMB_Clk();
+
+ /*!< FLASH clock */
+ case BL_PERIPHERAL_CLOCK_FLASH:
+ clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val());
+ div = Clock_Get_SF_Div_Val();
+ return clock / (div + 1);
+
+ /*!< I2S clock */
+ case BL_PERIPHERAL_CLOCK_I2S:
+ clock = Clock_I2S_Clk_Mux_Output();
+ div = Clock_Get_I2S_Div_Val();
+ return clock / (div + 1);
+
+ /*!< BLAI clock */
+ case BL_PERIPHERAL_CLOCK_BLAI:
+ return Clock_Get_BLAI_Clk();
+
+ /*!< DISPLAY clock */
+ case BL_PERIPHERAL_CLOCK_DISPLAY:
+ return Clock_Get_Display_Clk();
+
+ /*!< IR clock */
+ case BL_PERIPHERAL_CLOCK_IR:
+ clock = Clock_IR_Clk_Mux_Output();
+ div = Clock_Get_IR_Div_Val();
+ return clock / (div + 1);
+
+ /*!< PDM clock */
+ case BL_PERIPHERAL_CLOCK_PDM:
+ clock = Clock_PDM_Clk_Mux_Output();
+ div = Clock_Get_PDM_Div_Val();
+ return clock / (div + 1);
+
+ /*!< ADC clock */
+ case BL_PERIPHERAL_CLOCK_ADC:
+ return Clock_Audio_ADC_Clock_Get();
+
+ /*!< DAC clock */
+ case BL_PERIPHERAL_CLOCK_DAC:
+ return Clock_Audio_DAC_Clock_Get();
+
+ /*!< GPADC clock */
+ case BL_PERIPHERAL_CLOCK_GPADC:
+ return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val());
+
+ /*!< GPDAC clock */
+ case BL_PERIPHERAL_CLOCK_GPDAC:
+ clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val());
+ div = Clock_Get_GPDAC_Div_Val();
+ return clock / (div + 1);
+
+ /*!< CAM clock */
+ case BL_PERIPHERAL_CLOCK_CAM:
+ clock = Clock_CAM_Clk_Mux_Output(Clock_Get_CAM_Clk_Sel_Val());
+ div = Clock_Get_CAM_Div_Val();
+ return clock / (div + 1);
+
+ /*!< SDH clock */
+ case BL_PERIPHERAL_CLOCK_SDH:
+ clock = Clock_SDH_Clk_Mux_Output(Clock_Get_SDH_Clk_Sel_Val());
+ div = Clock_Get_SDH_Div_Val();
+ return clock / (div + 1);
+
+ /*!< PKA clock */
+ case BL_PERIPHERAL_CLOCK_PKA:
+ return Clock_PKA_Clk_Mux_Output(Clock_Get_PKA_Clk_Sel_Val());
+
+ /*!< EMI clock */
+ case BL_PERIPHERAL_CLOCK_EMI:
+ return Clock_Get_EMI_Clk();
+
+ /*!< H264 clock */
+ case BL_PERIPHERAL_CLOCK_H264:
+ return Clock_Get_H264_Clk();
+
+ /*!< DSP Sub clock */
+ case BL_PERIPHERAL_CLOCK_SUB:
+ return Clock_Get_Clk();
+#endif
+ default:
+ return 0;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief get system core clock
+ *
+ * @param None
+ *
+ * @return system core clock value
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION SystemCoreClockGet(void)
+{
+ uint32_t clockVal = 0;
+
+ switch (GLB_Get_Core_Type()) {
+ case GLB_CORE_ID_M0:
+ clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+ break;
+ case GLB_CORE_ID_D0:
+ clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);
+ break;
+ case GLB_CORE_ID_LP:
+ clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);
+ break;
+ default:
+ clockVal = 0;
+ break;
+ }
+ clockVal = clockVal ? clockVal : (32 * 1000 * 1000);
+
+ return clockVal;
+}
+
+/****************************************************************************/ /**
+ * @brief mcu rtc reset
+ *
+ * @param rstEn: hold reset or not
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_RST(uint8_t rstEn)
+{
+ uint32_t tmpVal = 0;
+ uint32_t address = 0;
+
+ switch (GLB_Get_Core_Type()) {
+ case GLB_CORE_ID_M0:
+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+ break;
+ case GLB_CORE_ID_D0:
+ address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET;
+ break;
+ case GLB_CORE_ID_LP:
+ address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET;
+ break;
+ default:
+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+ break;
+ }
+
+ /* set reset */
+ /* MCU RTC_RST is [30] */
+ /* DSP RTC_RST is [30] */
+ /* LP RTC_RST is [30] */
+ tmpVal = BL_RD_WORD(address);
+ if (rstEn) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
+ }
+ BL_WR_WORD(address, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief mcu rtc reset
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_Reset_MTimer(void)
+{
+ CPU_Set_MTimer_RST(1);
+ CPU_Set_MTimer_RST(0);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set mcu rtc clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_CLK(uint8_t enable, uint16_t div)
+{
+ uint32_t tmpVal = 0;
+ uint32_t address = 0;
+
+ CHECK_PARAM((div <= 0x3FF));
+
+ switch (GLB_Get_Core_Type()) {
+ case GLB_CORE_ID_M0:
+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+ break;
+ case GLB_CORE_ID_D0:
+ address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET;
+ break;
+ case GLB_CORE_ID_LP:
+ address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET;
+ break;
+ default:
+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+ break;
+ }
+
+ /* disable rtc first */
+ /* MCU RTC_EN is [31] */
+ /* DSP RTC_EN is [31] */
+ /* LP RTC_EN is [31] */
+ tmpVal = BL_RD_WORD(address);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+ BL_WR_WORD(address, tmpVal);
+
+ /* set div */
+ /* MCU RTC_DIV is [9:0] */
+ /* DSP RTC_DIV is [9:0] */
+ /* LP RTC_DIV is [9:0] */
+ tmpVal = BL_RD_WORD(address);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div);
+ BL_WR_WORD(address, tmpVal);
+
+ /* enable or not */
+ /* MCU RTC_EN is [31] */
+ /* DSP RTC_EN is [31] */
+ /* LP RTC_EN is [31] */
+ tmpVal = BL_RD_WORD(address);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+ }
+ BL_WR_WORD(address, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get cpu rtc source clock
+ *
+ * @param None
+ *
+ * @return cpu rtc source clock
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Source_Clock(void)
+{
+ uint32_t coreFreq = 0;
+
+ /* get cpu core clock */
+ switch (GLB_Get_Core_Type()) {
+ case GLB_CORE_ID_M0:
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+ break;
+ case GLB_CORE_ID_D0:
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);
+ break;
+ case GLB_CORE_ID_LP:
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);
+ break;
+ default:
+ coreFreq = 0;
+ break;
+ }
+ coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
+
+ return coreFreq;
+}
+
+/****************************************************************************/ /**
+ * @brief get mcu rtc clock
+ *
+ * @param None
+ *
+ * @return mcu rtc counter clock
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Clock(void)
+{
+ uint32_t coreFreq = 0;
+ uint32_t address = 0;
+ uint32_t div = 0;
+
+ /* get cpu core clock */
+ /* get mtimer clock div */
+ switch (GLB_Get_Core_Type()) {
+ case GLB_CORE_ID_M0:
+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+ break;
+ case GLB_CORE_ID_D0:
+ address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET;
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);
+ break;
+ case GLB_CORE_ID_LP:
+ address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET;
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);
+ break;
+ default:
+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+ coreFreq = 0;
+ break;
+ }
+ /* MCU RTC_DIV is [9:0] */
+ /* DSP RTC_DIV is [9:0] */
+ /* LP RTC_DIV is [9:0] */
+ div = BL_GET_REG_BITS_VAL(BL_RD_WORD(address), MCU_MISC_REG_MCU_RTC_DIV);
+ div += 1;
+ coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
+ coreFreq = coreFreq / div; /* mtimer clock = cpu clock / mtimer div */
+
+ return coreFreq;
+}
+
+/****************************************************************************/ /**
+ * @brief get mcu rtc counter
+ *
+ * @param None
+ *
+ * @return mcu rtc counter
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Counter(void)
+{
+#if (__riscv_xlen == 64)
+ return (uint64_t)csi_coret_get_value();
+#else
+ volatile uint32_t tmpValLow, tmpValHigh, tmpValHigh1;
+ uint32_t cnt = 0;
+
+ do {
+ tmpValHigh = csi_coret_get_valueh();
+ tmpValLow = csi_coret_get_value();
+ tmpValHigh1 = csi_coret_get_valueh();
+ cnt++;
+ if (cnt > 5000) {
+ break;
+ }
+ } while (tmpValHigh != tmpValHigh1);
+
+ return (uint64_t)(((uint64_t)tmpValHigh << 32) + tmpValLow);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief get mcu cycle
+ *
+ * @param None
+ *
+ * @return mcu cycle
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_CPU_Cycle(void)
+{
+#if (__riscv_xlen == 64)
+ return (uint64_t)__get_MCYCLE();
+#else
+ volatile uint32_t tmpValLow, tmpValHigh, tmpValHigh1;
+ uint32_t cnt = 0;
+
+ do {
+ tmpValHigh = __get_MCYCLEH();
+ tmpValLow = __get_MCYCLE();
+ tmpValHigh1 = __get_MCYCLEH();
+ cnt++;
+ if (cnt > 5000) {
+ break;
+ }
+ } while (tmpValHigh != tmpValHigh1);
+
+ return (uint64_t)(((uint64_t)tmpValHigh << 32) + tmpValLow);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief get mcu rtc counter in us
+ *
+ * @param None
+ *
+ * @return mcu rtc counter in us
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_US(void)
+{
+ uint32_t clk = SystemCoreClockGet();
+ uint64_t mtimer_counter = CPU_Get_MTimer_Counter();
+
+ if (mtimer_counter < 10) {
+ mtimer_counter = CPU_Get_CPU_Cycle();
+ return (uint32_t)mtimer_counter / (clk / 1000000);
+ }
+
+ if (clk > 1000 * 1000) {
+ /* system_clock > 1MHz ==> mtimer_clock is 1MHz */
+ /* return mtimer_count after mtimer_init_1MHz */
+ return CPU_Get_MTimer_Counter();
+ } else {
+ /* system_clock < 1MHz ==> mtimer_clock is 1KHz */
+ /* return mtimer_count*1000 after mtimer_init_1KHz */
+ return CPU_Get_MTimer_Counter() * 1000;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief get mcu rtc counter in ms
+ *
+ * @param None
+ *
+ * @return mcu rtc counter in ms
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_MS(void)
+{
+ uint32_t clk = SystemCoreClockGet();
+ uint64_t mtimer_counter = CPU_Get_MTimer_Counter();
+
+ if (mtimer_counter < 10) {
+ mtimer_counter = CPU_Get_CPU_Cycle();
+ return (uint32_t)mtimer_counter / (clk / 1000);
+ }
+
+ if (clk > 1000 * 1000) {
+ /* system_clock > 1MHz ==> mtimer_clock is 1MHz */
+ /* return mtimer_count/1000 after mtimer_init_1MHz */
+ mtimer_counter = CPU_Get_MTimer_Counter();
+#ifndef CONFIG_SUPPORT_U32_DIV_ONLY
+ return mtimer_counter / 1000;
+#else
+ if (mtimer_counter < (1 << 30)) {
+ return (uint32_t)mtimer_counter / 1000;
+ } else {
+ //return CPU_Get_MTimer_Counter()/1000;
+ return (mtimer_counter >> 10) + (mtimer_counter >> 15) - (mtimer_counter >> 17) + (mtimer_counter >> 21);
+ }
+#endif
+ } else {
+ /* system_clock < 1MHz ==> mtimer_clock is 1KHz */
+ /* return mtimer_count after mtimer_init_1KHz */
+ return CPU_Get_MTimer_Counter();
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief mcu timer delay us
+ *
+ * @param cnt: us
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_US(uint32_t cnt)
+{
+ volatile uint64_t us1 = 0;
+ volatile uint64_t us2 = 0;
+
+ us1 = CPU_Get_MTimer_US();
+ do {
+ us2 = CPU_Get_MTimer_US();
+ } while (((us2 - us1) < (uint64_t)(cnt)));
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief mcu timer delay ms
+ *
+ * @param cnt: ms
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_MS(uint32_t cnt)
+{
+ volatile uint64_t ms1 = 0;
+ volatile uint64_t ms2 = 0;
+
+ ms1 = CPU_Get_MTimer_MS();
+ do {
+ ms2 = CPU_Get_MTimer_MS();
+ } while (((ms2 - ms1) < (uint64_t)(cnt)));
+
+ return SUCCESS;
+}
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_common.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_common.c
new file mode 100644
index 00000000..995a7b80
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_common.c
@@ -0,0 +1,406 @@
+#include "bl808_common.h"
+#include "bl808_glb.h"
+#include "bl808_clock.h"
+
+/** @addtogroup BL808_Periph_Driver
+ * @{
+ */
+
+/** @defgroup DRIVER_COMMON DRIVER_COMMON
+ * @brief Digger driver common functions
+ * @{
+ */
+
+/** @defgroup DRIVER_Private_Type
+ * @{
+ */
+
+/*@} end of group DRIVER_Private_Type*/
+
+/** @defgroup DRIVER_Private_Defines
+ * @{
+ */
+
+/*@} end of group DRIVER_Private_Defines */
+
+/** @defgroup DRIVER_Private_Variables
+ * @{
+ */
+
+/*@} end of group DRIVER_Private_Variables */
+
+/** @defgroup DRIVER_Global_Variables
+ * @{
+ */
+
+/*@} end of group DRIVER_Global_Variables */
+
+/** @defgroup DRIVER_Private_FunctionDeclaration
+ * @{
+ */
+
+/*@} end of group DRIVER_Private_FunctionDeclaration */
+
+/** @defgroup DRIVER_Private_Functions
+ * @{
+ */
+
+/*@} end of group DRIVER_Private_Functions */
+
+/** @defgroup DRIVER_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief delay us
+ *
+ * @param[in] core: systemcoreclock
+ *
+ * @param[in] cnt: delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+#ifdef ARCH_RISCV
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)
+{
+ volatile uint32_t divVal = loopT;
+ volatile uint32_t speed = 0;
+ volatile uint32_t cycNum = 0;
+
+ /* 1M=100K*10, so multiple is 10 */
+ /* loop function take 4 instructions, so instructionNum is 4 */
+ /* divVal = multiple*instructionNum */
+
+ if (core >= 1 * 1000 * 1000) {
+ /* CPU clock >= 1MHz */
+ speed = core / (100 * 1000);
+ cycNum = speed * cnt;
+ cycNum = cycNum / 10;
+ cycNum = cycNum / divVal;
+ /* cycNum >= 0 */
+ } else {
+ /* CPU clock < 1MHz */
+ speed = core / 1000;
+ cycNum = speed * cnt;
+ cycNum = cycNum / 1000;
+ cycNum = cycNum / divVal;
+ /* cycNum >= 0 */
+ }
+
+ if (!cycNum) {
+ return;
+ }
+
+ __asm__ __volatile__(
+ "mv a4,%0\n\t"
+ "li a5,0x0\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".align 4\n\t"
+ "1 :\n"
+ "beq a5,a4,2f\n\t"
+ "addi a5,a5,0x1\n\t"
+ "lui a3,0xF0000\n\t"
+ "lw a3,0(a3)\n\t"
+ "j 1b\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "2 :\n\t"
+ "nop\n"
+ : /* output */
+ : "r"(cycNum) /* input */
+ : "a3", "a4", "a5" /* destruct description */
+ );
+}
+#endif
+#endif
+
+/****************************************************************************/ /**
+ * @brief delay us
+ *
+ * @param[in] cnt: delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+const uint32_t ATTR_TCM_CONST_SECTION m0Cyc00[] = {46,46,66,69};
+const uint32_t ATTR_TCM_CONST_SECTION m0Cyc10[] = {10,10,66,69};
+const uint32_t ATTR_TCM_CONST_SECTION m0Cyc11[] = {10,10,66,69};
+const uint32_t ATTR_TCM_CONST_SECTION d0Cyc00[] = { 5, 5,62,34};
+const uint32_t ATTR_TCM_CONST_SECTION d0Cyc11[] = { 5, 5,13,13};
+const uint32_t ATTR_TCM_CONST_SECTION lpCyc00[] = { 6, 6,55,85};
+__WEAK
+void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)
+{
+ GLB_CORE_ID_Type coreID;
+ uint32_t coreFreq;
+ uint32_t loopTick = 5;
+ const uint32_t *pCyc = NULL;
+ uint32_t iCacheEn = 1;
+ uint32_t dCacheEn = 1;
+
+ /* requirement: icache enable && dcache enable */
+ /* otherwise the latency depends on the code address */
+
+ coreID = GLB_Get_Core_Type();
+
+ if(GLB_CORE_ID_M0 == coreID){
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+#ifdef __RV32
+ iCacheEn = (__get_MHCR() & CLIC_INTIE_IE_Msk) >> CLIC_INTIE_IE_Pos;
+ dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;
+#endif
+ if(iCacheEn && dCacheEn){
+ pCyc = m0Cyc11;
+ }else if(iCacheEn && !dCacheEn){
+ pCyc = m0Cyc10;
+ }else if(!iCacheEn && !dCacheEn){
+ pCyc = m0Cyc00;
+ }else{
+ pCyc = m0Cyc11;
+ }
+ }else if(GLB_CORE_ID_D0 == coreID){
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);
+#ifdef __RV64
+ iCacheEn = (__get_MHCR() & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos;
+ dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;
+#endif
+ if(iCacheEn && dCacheEn){
+ pCyc = d0Cyc11;
+ }else if(!iCacheEn && !dCacheEn){
+ pCyc = d0Cyc00;
+ }else{
+ pCyc = d0Cyc11;
+ }
+ }else if(GLB_CORE_ID_LP == coreID){
+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);
+ pCyc = lpCyc00;
+ }else{
+ coreFreq = 32 * 1000 * 1000;
+ pCyc = lpCyc00;
+ }
+
+ switch(((uint32_t)(uintptr_t)&ASM_Delay_Us)>>24){
+ case 0x22:
+ loopTick = pCyc[0];
+ break;
+ case 0x62:
+ loopTick = pCyc[0];
+ break;
+ case 0x3F:
+ loopTick = pCyc[2];
+ break;
+ case 0x3E:
+ loopTick = pCyc[3];
+ break;
+ default :
+ break;
+ }
+
+ coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
+
+ ASM_Delay_Us(coreFreq, cnt, loopTick);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief delay ms
+ *
+ * @param[in] cnt: delay cnt ms
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt)
+{
+ uint32_t i = 0;
+ uint32_t count = 0;
+
+ if (cnt >= 1024) {
+ /* delay (n*1024) ms */
+ for (i = 0; i < (cnt / 1024); i++) {
+ arch_delay_us(1024 * 1000);
+ }
+ }
+
+ count = cnt & 0x3FF;
+
+ if (count) {
+ /* delay (1-1023)ms */
+ arch_delay_us(count * 1000);
+ }
+}
+#endif
+
+#ifdef DEBUG
+/*******************************************************************************
+* @brief Reports the name of the source file and the source line number
+* where the CHECK_PARAM error has occurred.
+
+* @param file: Pointer to the source file name
+* @param line: assert_param error line source number
+
+* @return None
+*******************************************************************************/
+void ATTR_TCM_SECTION check_failed(uint8_t *file, uint32_t line)
+{
+ /* Infinite loop */
+ while (1)
+ ;
+}
+#endif /* DEBUG */
+
+/****************************************************************************/ /**
+ * @brief MM_Sys All interrupt handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#if defined(CPU_M0) || defined(CPU_LP)
+#ifndef BFLB_USE_HAL_DRIVER
+void AWB2_IRQHandler(void);
+void UART4_IRQHandler(void);
+void UART3_IRQHandler(void);
+void I2C2_IRQHandler(void);
+void I2C3_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void AE_IRQHandler(void);
+void AWB0_IRQHandler(void);
+void SEOF0_IRQHandler(void);
+void SEOF1_IRQHandler(void);
+void SEOF2_IRQHandler(void);
+void CAM0_IRQHandler(void);
+void CAM1_IRQHandler(void);
+void CAM2_IRQHandler(void);
+void CAM3_IRQHandler(void);
+void MJPEG_IRQHandler(void);
+void DMA2_INT0_IRQHandler(void);
+void DMA2_INT1_IRQHandler(void);
+void DMA2_INT2_IRQHandler(void);
+void DMA2_INT3_IRQHandler(void);
+void DMA2_INT4_IRQHandler(void);
+void DMA2_INT5_IRQHandler(void);
+void DMA2_INT6_IRQHandler(void);
+void DMA2_INT7_IRQHandler(void);
+void IPC_D0_IRQHandler(void);
+void MJDEC_IRQHandler(void);
+void CAM4_IRQHandler(void);
+void CAM5_IRQHandler(void);
+void CAM6_IRQHandler(void);
+void CAM7_IRQHandler(void);
+void DMA2D_INT0_IRQHandler(void);
+void DMA2D_INT1_IRQHandler(void);
+void Display_IRQHandler(void);
+void PWM_IRQHandler(void);
+void SEOF3_IRQHandler(void);
+void DBI_IRQHandler(void);
+void WDR_IRQHandler(void);
+void OSD_PB_IRQHandler(void);
+void AWB1_IRQHandler(void);
+void DSI_IRQHandler(void);
+void AE_HIST_IRQHandler(void);
+void TIMER1_CH0_IRQHandler(void);
+void TIMER1_CH1_IRQHandler(void);
+void TIMER1_WDT_IRQHandler(void);
+void AUDIO_IRQHandler(void);
+
+
+
+void C906_ALL_IRQHandler(void)
+{
+ AWB2_IRQHandler();
+ UART4_IRQHandler();
+ UART3_IRQHandler();
+ I2C2_IRQHandler();
+ I2C3_IRQHandler();
+ SPI1_IRQHandler();
+ AE_IRQHandler();
+ AWB0_IRQHandler();
+ SEOF0_IRQHandler();
+ SEOF1_IRQHandler();
+ SEOF2_IRQHandler();
+ CAM0_IRQHandler();
+ CAM1_IRQHandler();
+ CAM2_IRQHandler();
+ CAM3_IRQHandler();
+ MJPEG_IRQHandler();
+ DMA2_INT0_IRQHandler();
+ DMA2_INT1_IRQHandler();
+ DMA2_INT2_IRQHandler();
+ DMA2_INT3_IRQHandler();
+ DMA2_INT4_IRQHandler();
+ DMA2_INT5_IRQHandler();
+ DMA2_INT6_IRQHandler();
+ DMA2_INT7_IRQHandler();
+ IPC_D0_IRQHandler();
+ MJDEC_IRQHandler();
+ CAM4_IRQHandler();
+ CAM5_IRQHandler();
+ CAM6_IRQHandler();
+ CAM7_IRQHandler();
+ DMA2D_INT0_IRQHandler();
+ DMA2D_INT1_IRQHandler();
+ Display_IRQHandler();
+ PWM_IRQHandler();
+ SEOF3_IRQHandler();
+ DBI_IRQHandler();
+ WDR_IRQHandler();
+ OSD_PB_IRQHandler();
+ AWB1_IRQHandler();
+ DSI_IRQHandler();
+ AE_HIST_IRQHandler();
+ TIMER1_CH0_IRQHandler();
+ TIMER1_CH1_IRQHandler();
+ TIMER1_WDT_IRQHandler();
+ AUDIO_IRQHandler();
+}
+#endif
+#endif
+
+/****************************************************************************/ /**
+ * @brief Enable MM_Sys All interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#if defined(CPU_M0) || defined(CPU_LP)
+void C906_All_Int_Enable(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(MM_ALL_IRQn, C906_ALL_IRQHandler);
+#endif
+ CPU_Interrupt_Enable(MM_ALL_IRQn);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Dsiable MM_Sys All interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#if defined(CPU_M0) || defined(CPU_LP)
+void C906_All_Int_Disable(void)
+{
+ CPU_Interrupt_Disable(MM_ALL_IRQn);
+}
+#endif
+
+/*@} end of group DRIVER_Public_Functions */
+
+/*@} end of group DRIVER_COMMON */
+
+/*@} end of group BL808_Periph_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_ef_cfg.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_ef_cfg.c
new file mode 100644
index 00000000..b4559f93
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_ef_cfg.c
@@ -0,0 +1,434 @@
+/**
+ ******************************************************************************
+ * @file bl808_ef_cfg.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "bl808_ef_cfg.h"
+#include "hardware/ef_data_0_reg.h"
+#include "hardware/ef_data_1_reg.h"
+
+extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+
+static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
+ {
+ .name = "rc32m",
+ .en_addr = 0x78 * 8 + 1,
+ .parity_addr = 0x78 * 8 + 0,
+ .value_addr = 0x7C * 8 + 4,
+ .value_len = 8,
+ },
+ {
+ .name = "rc32k",
+ .en_addr = 0xEC * 8 + 19,
+ .parity_addr = 0xEC * 8 + 18,
+ .value_addr = 0xEC * 8 + 8,
+ .value_len = 10,
+ },
+ {
+ .name = "gpadc_gain",
+ .en_addr = 0xF0 * 8 + 27,
+ .parity_addr = 0xF0 * 8 + 26,
+ .value_addr = 0xF0 * 8 + 14,
+ .value_len = 12,
+ },
+ {
+ .name = "tsen",
+ .en_addr = 0xF0 * 8 + 13,
+ .parity_addr = 0xF0 * 8 + 12,
+ .value_addr = 0xF0 * 8 + 0,
+ .value_len = 12,
+ },
+ {
+ .name = "usb20",
+ .en_addr = 0xF8 * 8 + 15,
+ .parity_addr = 0xF8 * 8 + 14,
+ .value_addr = 0xF8 * 8 + 8,
+ .value_len = 6,
+ },
+ {
+ .name = "dcdc11_trim",
+ .en_addr = 0x78 * 8 + 31,
+ .parity_addr = 0x78 * 8 + 30,
+ .value_addr = 0x78 * 8 + 26,
+ .value_len = 4,
+ },
+ {
+ .name = "dcdc18_trim",
+ .en_addr = 0x78 * 8 + 25,
+ .parity_addr = 0x78 * 8 + 24,
+ .value_addr = 0x78 * 8 + 20,
+ .value_len = 4,
+ },
+ {
+ .name = "ldo28cis_trim",
+ .en_addr = 0x78 * 8 + 13,
+ .parity_addr = 0x78 * 8 + 12,
+ .value_addr = 0x78 * 8 + 8,
+ .value_len = 4,
+ },
+ {
+ .name = "ldo15cis_trim",
+ .en_addr = 0x78 * 8 + 13,
+ .parity_addr = 0x78 * 8 + 12,
+ .value_addr = 0x78 * 8 + 8,
+ .value_len = 4,
+ },
+ {
+ .name = "ldo18flash_trim",
+ .en_addr = 0xEC * 8 + 31,
+ .parity_addr = 0xEC * 8 + 30,
+ .value_addr = 0xEC * 8 + 26,
+ .value_len = 4,
+ },
+ {
+ .name = "ldo12uhs_trim",
+ .en_addr = 0xEC * 8 + 25,
+ .parity_addr = 0xEC * 8 + 24,
+ .value_addr = 0xEC * 8 + 20,
+ .value_len = 4,
+ },
+};
+
+/****************************************************************************/ /**
+ * @brief Efuse get trim list
+ *
+ * @param trim_list: Trim list pointer
+ *
+ * @return Trim list count
+ *
+*******************************************************************************/
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
+{
+ *ptrim_list = &trim_list[0];
+ return sizeof(trim_list) / sizeof(trim_list[0]);
+}
+
+/****************************************************************************/ /**
+ * @brief Efuse read device info
+ *
+ * @param deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
+{
+ uint32_t tmpval;
+
+ //tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, 1);
+
+ deviceInfo->chipInfo = (tmpval >> 29) & 0x7;
+ deviceInfo->memoryInfo = (tmpval >> 27) & 0x3;
+ deviceInfo->psramInfo = (tmpval >> 25) & 0x3;
+ deviceInfo->deviceInfo = (tmpval >> 22) & 0x7;
+
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+
+ deviceInfo->psramInfo |= ((tmpval >> 20) & 0x1) << 2;
+}
+
+void bflb_efuse_get_chipid(uint8_t chipid[8])
+{
+ bflb_efuse_read_mac_address_opt(0, chipid, 1);
+ chipid[6] = 0;
+ chipid[7] = 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Whether MAC address slot is empty
+ *
+ * @param slot: MAC address slot
+ * @param reload: whether reload to check
+ *
+ * @return 0 for all slots full,1 for others
+ *
+*******************************************************************************/
+uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
+{
+ uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
+ uint32_t part1Empty = 0, part2Empty = 0;
+
+ if (slot == 0) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
+ } else if (slot == 1) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmp1, 1, reload);
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmp2, 1, reload);
+ } else if (slot == 2) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmp1, 1, reload);
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmp2, 1, reload);
+ }
+
+ part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
+ part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
+
+ return (part1Empty && part2Empty);
+}
+
+/****************************************************************************/ /**
+ * @brief Efuse write optional MAC address
+ *
+ * @param slot: MAC address slot
+ * @param mac[6]: MAC address buffer
+ * @param program: Whether program
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
+{
+ uint8_t *maclow = (uint8_t *)mac;
+ uint8_t *machigh = (uint8_t *)(mac + 4);
+ uint32_t tmpval;
+ uint32_t i = 0, cnt;
+
+ if (slot >= 3) {
+ return -1;
+ }
+
+ /* Change to local order */
+ for (i = 0; i < 3; i++) {
+ tmpval = mac[i];
+ mac[i] = mac[5 - i];
+ mac[5 - i] = tmpval;
+ }
+
+ /* The low 32 bits */
+ tmpval = BL_RDWD_FRM_BYTEP(maclow);
+
+ if (slot == 0) {
+ bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
+ } else if (slot == 1) {
+ bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmpval, 1, program);
+ } else if (slot == 2) {
+ bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, program);
+ }
+
+ /* The high 16 bits */
+ tmpval = machigh[0] + (machigh[1] << 8);
+ cnt = 0;
+
+ for (i = 0; i < 6; i++) {
+ cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+ }
+
+ tmpval |= ((cnt & 0x3f) << 16);
+
+ if (slot == 0) {
+ bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
+ } else if (slot == 1) {
+ bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmpval, 1, program);
+ } else if (slot == 2) {
+ bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, program);
+ }
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Efuse read optional MAC address
+ *
+ * @param slot: MAC address slot
+ * @param mac[6]: MAC address buffer
+ * @param reload: Whether reload
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
+{
+ uint8_t *maclow = (uint8_t *)mac;
+ uint8_t *machigh = (uint8_t *)(mac + 4);
+ uint32_t tmpval = 0;
+ uint32_t i = 0;
+ uint32_t cnt = 0;
+
+ if (slot >= 3) {
+ return -1;
+ }
+
+ if (slot == 0) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
+ } else if (slot == 1) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmpval, 1, reload);
+ } else if (slot == 2) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, reload);
+ }
+
+ BL_WRWD_TO_BYTEP(maclow, tmpval);
+
+ if (slot == 0) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
+ } else if (slot == 1) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmpval, 1, reload);
+ } else if (slot == 2) {
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, reload);
+ }
+
+ machigh[0] = tmpval & 0xff;
+ machigh[1] = (tmpval >> 8) & 0xff;
+
+ /* Check parity */
+ for (i = 0; i < 6; i++) {
+ cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+ }
+
+ if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) {
+ /* Change to network order */
+ for (i = 0; i < 3; i++) {
+ tmpval = mac[i];
+ mac[i] = mac[5 - i];
+ mac[5 - i] = tmpval;
+ }
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+float bflb_efuse_get_adc_trim(void)
+{
+ bflb_ef_ctrl_com_trim_t trim;
+ uint32_t tmp;
+
+ float coe = 1.0;
+
+ bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
+
+ if (trim.en) {
+ if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+ tmp = trim.value;
+
+ if (tmp & 0x800) {
+ tmp = ~tmp;
+ tmp += 1;
+ tmp = tmp & 0xfff;
+ coe = (1.0 + ((float)tmp / 2048.0));
+ } else {
+ coe = (1.0 - ((float)tmp / 2048.0));
+ }
+ }
+ }
+
+ return coe;
+}
+
+uint32_t bflb_efuse_get_adc_tsen_trim(void)
+{
+ bflb_ef_ctrl_com_trim_t trim;
+
+ bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
+ if (trim.en) {
+ if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+ return trim.value;
+ }
+ }
+
+ return 2042;
+}
+
+void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
+{
+ uint32_t tmpval = 0;
+
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+ *sign = ((tmpval & EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) & 0x01;
+ *aes = ((tmpval & EF_DATA_0_EF_SF_AES_MODE_MSK) >> EF_DATA_0_EF_SF_AES_MODE_POS);
+}
+
+void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+ if ((index <= 3) || (index == 11)) {
+ index = ((index == 11) ? 5 : index);
+ /* Every key is 4 words len*/
+ bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+ } else if ((index < 11) && (index > 3)) {
+ index = index - 4;
+ /* Every key is 4 words len*/
+ bflb_ef_ctrl_write_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
+ }
+}
+
+void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+ if ((index <= 3) || (index == 11)) {
+ index = ((index == 11) ? 5 : index);
+ /* Every key is 4 words len*/
+ bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+ } else if ((index < 11) && (index > 3)) {
+ index = index - 4;
+ /* Every key is 4 words len*/
+ bflb_ef_ctrl_read_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
+ }
+}
+
+void bflb_efuse_lock_aes_key_write(uint8_t index)
+{
+ uint32_t lock = 0;
+
+ if ((index <= 3) || (index == 11)) {
+ index = ((index == 11) ? 8 : index);
+ lock |= (1 << (index + 17));
+ bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)&lock, 1, 1);
+ } else if ((index < 11) && (index > 3)) {
+ index = index - 4;
+ lock |= (1 << (index + 15));
+ bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)&lock, 1, 1);
+ }
+}
+
+void bflb_efuse_lock_aes_key_read(uint8_t index)
+{
+ uint32_t lock = 0;
+
+ if ((index <= 3) || (index == 11)) {
+ index = ((index == 11) ? 4 : index);
+ lock |= (1 << (index + 27));
+ bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
+ } else if ((index < 11) && (index > 3)) {
+ index = index - 4;
+ lock |= (1 << (index + 25));
+ bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
+ }
+}
+
+void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
+{
+ bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
+}
+
+void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
+{
+ bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_glb.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_glb.c
new file mode 100644
index 00000000..239ba7d1
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_glb.c
@@ -0,0 +1,6096 @@
+/**
+ ******************************************************************************
+ * @file bl808_glb_pll.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808_clock.h"
+#include "bl808_glb.h"
+#include "bl808_aon.h"
+#include "bl808_hbn.h"
+#include "bl808_pds.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup GLB
+ * @{
+ */
+
+/** @defgroup GLB_Private_Macros
+ * @{
+ */
+#define GLB_CLK_SET_DUMMY_WAIT \
+ { \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ }
+#define GLB_CLK_SET_DUMMY_TIMEOUT (0xFF)
+#define GLB_FREQ_RC32M (32000000)
+
+/*@} end of group GLB_Private_Macros */
+
+/** @defgroup GLB_Private_Types
+ * @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };
+#endif
+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit);
+
+/*@} end of group GLB_Private_Types */
+
+/** @defgroup GLB_Private_Variables
+ * @{
+ */
+
+/* WiFi PLL Config*/
+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */
+ .clkpllIcp1u = 0, /*!< pll_icp_1u */
+ .clkpllIcp5u = 2, /*!< pll_icp_5u */
+ .clkpllRz = 3, /*!< pll_rz */
+ .clkpllCz = 1, /*!< pll_cz */
+ .clkpllC3 = 2, /*!< pll_c3 */
+ .clkpllR4Short = 1, /*!< pll_r4_short */
+ .clkpllC4En = 0, /*!< pll_r4_en */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */
+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */
+};
+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */
+ .clkpllIcp1u = 0, /*!< pll_icp_1u */
+ .clkpllIcp5u = 2, /*!< pll_icp_5u */
+ .clkpllRz = 3, /*!< pll_rz */
+ .clkpllCz = 1, /*!< pll_cz */
+ .clkpllC3 = 2, /*!< pll_c3 */
+ .clkpllR4Short = 1, /*!< pll_r4_short */
+ .clkpllC4En = 0, /*!< pll_r4_en */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */
+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */
+};
+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */
+ .clkpllIcp1u = 1, /*!< pll_icp_1u */
+ .clkpllIcp5u = 0, /*!< pll_icp_5u */
+ .clkpllRz = 5, /*!< pll_rz */
+ .clkpllCz = 2, /*!< pll_cz */
+ .clkpllC3 = 2, /*!< pll_c3 */
+ .clkpllR4Short = 0, /*!< pll_r4_short */
+ .clkpllC4En = 1, /*!< pll_r4_en */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */
+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */
+};
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */
+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */
+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */
+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */
+ { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */
+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */
+};
+
+/* Audio PLL Config*/
+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */
+ .clkpllIcp1u = 1, /*!< pll_icp_1u */
+ .clkpllIcp5u = 0, /*!< pll_icp_5u */
+ .clkpllRz = 5, /*!< pll_rz */
+ .clkpllCz = 2, /*!< pll_cz */
+ .clkpllC3 = 2, /*!< pll_c3 */
+ .clkpllR4Short = 0, /*!< pll_r4_short */
+ .clkpllC4En = 1, /*!< pll_r4_en */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */
+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */
+};
+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */
+ .clkpllIcp1u = 1, /*!< pll_icp_1u */
+ .clkpllIcp5u = 0, /*!< pll_icp_5u */
+ .clkpllRz = 5, /*!< pll_rz */
+ .clkpllCz = 2, /*!< pll_cz */
+ .clkpllC3 = 2, /*!< pll_c3 */
+ .clkpllR4Short = 0, /*!< pll_r4_short */
+ .clkpllC4En = 1, /*!< pll_r4_en */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */
+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */
+};
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */
+ { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */
+};
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */
+ { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */
+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */
+};
+
+/* CPU PLL Config*/
+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */
+ .clkpllIcp1u = 1, /*!< pll_icp_1u */
+ .clkpllIcp5u = 0, /*!< pll_icp_5u */
+ .clkpllRz = 5, /*!< pll_rz */
+ .clkpllCz = 2, /*!< pll_cz */
+ .clkpllC3 = 2, /*!< pll_c3 */
+ .clkpllR4Short = 0, /*!< pll_r4_short */
+ .clkpllC4En = 1, /*!< pll_r4_en */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */
+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */
+};
+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */
+ .clkpllIcp1u = 1, /*!< pll_icp_1u */
+ .clkpllIcp5u = 0, /*!< pll_icp_5u */
+ .clkpllRz = 5, /*!< pll_rz */
+ .clkpllCz = 2, /*!< pll_cz */
+ .clkpllC3 = 2, /*!< pll_c3 */
+ .clkpllR4Short = 0, /*!< pll_r4_short */
+ .clkpllC4En = 1, /*!< pll_r4_en */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */
+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */
+};
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */
+ { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */
+};
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */
+ { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */
+};
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_440M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &cpuPllBasicCfg_24M_26M, 0x12555 }, /*!< XTAL is 24M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1B800 }, /*!< XTAL is 32M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x16EAA }, /*!< XTAL is 38.4M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x16000 }, /*!< XTAL is 40M */
+ { &cpuPllBasicCfg_24M_26M, 0x10EC4 }, /*!< XTAL is 26M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1B800 }, /*!< XTAL is RC32M */
+};
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */
+ { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */
+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */
+};
+
+/* MIPI PLL Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &mipiPllBasicCfg_24M, 0x3E800 }, /*!< XTAL is 24M */
+ { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is 32M */
+ { &mipiPllBasicCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */
+ { &mipiPllBasicCfg_40M, 0x38400 }, /*!< XTAL is 40M */
+ { &mipiPllBasicCfg_26M, 0x39B13 }, /*!< XTAL is 26M */
+ { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 2100 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */
+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */
+ { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */
+ { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */
+ { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */
+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 1400 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll1400MCfg_24M, 0x3A555 }, /*!< XTAL is 24M */
+ { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is 32M */
+ { &uhsPll1400MCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */
+ { &uhsPll1400MCfg_40M, 0x34800 }, /*!< XTAL is 40M */
+ { &uhsPll1400MCfg_26M, 0x35D89 }, /*!< XTAL is 26M */
+ { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 1500 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll1500MCfg_24M, 0x3E800 }, /*!< XTAL is 24M */
+ { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is 32M */
+ { &uhsPll1500MCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */
+ { &uhsPll1500MCfg_40M, 0x38400 }, /*!< XTAL is 40M */
+ { &uhsPll1500MCfg_26M, 0x39B13 }, /*!< XTAL is 26M */
+ { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 1600 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */
+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */
+ { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */
+ { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */
+ { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */
+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 400 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll400BasicCfg_24M, 0x19000 }, /*!< XTAL is 24M */
+ { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */
+ { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */
+ { &uhsPll400BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */
+ { &uhsPll400BasicCfg_26M, 0x1713B }, /*!< XTAL is 26M */
+ { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 667 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = {
+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll667BasicCfg_24M, 0x29B00 }, /*!< XTAL is 24M */
+ { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is 32M */
+ { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */
+ { &uhsPll667BasicCfg_40M, 0x21599 }, /*!< XTAL is 40M */
+ { &uhsPll667BasicCfg_26M, 0x267B1 }, /*!< XTAL is 26M */
+ { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 800 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll800BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */
+ { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is 32M */
+ { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */
+ { &uhsPll800BasicCfg_40M, 0x1E000 }, /*!< XTAL is 40M */
+ { &uhsPll800BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */
+ { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 1066 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = {
+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll1066BasicCfg_24M, 0x2C6AA }, /*!< XTAL is 24M */
+ { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is 32M */
+ { &uhsPll1066BasicCfg_38P4M, 0x29A40 }, /*!< XTAL is 38.4M */
+ { &uhsPll1066BasicCfg_40M, 0x27F99 }, /*!< XTAL is 40M */
+ { &uhsPll1066BasicCfg_26M, 0x29000 }, /*!< XTAL is 26M */
+ { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is RC32M */
+};
+
+/* uhs PLL 2000 Config*/
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = {
+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
+};
+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */
+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */
+ { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */
+ { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */
+ { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */
+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */
+};
+
+/*@} end of group GLB_Private_Variables */
+
+/** @defgroup GLB_Global_Variables
+ * @{
+ */
+
+/*@} end of group GLB_Global_Variables */
+
+/** @defgroup GLB_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group GLB_Private_Fun_Declaration */
+
+/** @defgroup GLB_Private_Functions
+ * @{
+ */
+
+/*@} end of group GLB_Private_Functions */
+
+/** @defgroup GLB_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief set mcu muxpll 160M selection
+ *
+ * @param clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_160M_Sel(GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get mcu muxpll 160M selection
+ *
+ * @param None
+ *
+ * @return 160M mux select value
+ *
+*******************************************************************************/
+GLB_MCU_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_160M_Sel(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ return (GLB_MCU_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief set top muxpll 80M selection
+ *
+ * @param clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_80M_Sel(GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get mcu muxpll 80M selection
+ *
+ * @param None
+ *
+ * @return 80M mux select value
+ *
+*******************************************************************************/
+GLB_MCU_MUXPLL_80M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_80M_Sel(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ return (GLB_MCU_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief set dsp muxpll 320M selection
+ *
+ * @param clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get dsp muxpll 320M selection
+ *
+ * @param None
+ *
+ * @return dsp 320M mux select value
+ *
+*******************************************************************************/
+GLB_DSP_MUXPLL_320M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_320M_Sel(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ return (GLB_DSP_MUXPLL_320M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief set dsp muxpll 240M selection
+ *
+ * @param clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get dsp muxpll 240M selection
+ *
+ * @param None
+ *
+ * @return dsp 240M mux select value
+ *
+*******************************************************************************/
+GLB_DSP_MUXPLL_240M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_240M_Sel(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ return (GLB_DSP_MUXPLL_240M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief set dsp muxpll 160M selection
+ *
+ * @param clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get dsp muxpll 160M selection
+ *
+ * @param None
+ *
+ * @return dsp 160M mux select value
+ *
+*******************************************************************************/
+GLB_DSP_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_160M_Sel(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+ return (GLB_DSP_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief power on all PLL clock
+ *
+ * @param xtalType: XTAL frequency type
+ * @param pllType: only power on xtal
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type pllType)
+{
+ uint32_t tmpVal;
+ GLB_CORE_ID_Type coreType;
+ HBN_MCU_XCLK_Type mcuXclkSel;
+ HBN_MCU_ROOT_CLK_Type mcuRootClkSel;
+ GLB_DSP_XCLK_Type dspXclkSel;
+ GLB_DSP_ROOT_CLK_Type dspRootClkSel;
+ volatile GLB_PLL_REF_CLK_Type refClk;
+
+ CHECK_PARAM(IS_GLB_XTAL_TYPE(xtalType));
+ CHECK_PARAM((pllType < (GLB_PLL_UHSPLL * 2)));
+
+ if (xtalType == GLB_XTAL_NONE) {
+ return ERROR;
+ }
+
+ if (xtalType != GLB_XTAL_RC32M) {
+ /* power on xtal first */
+ AON_Power_On_XTAL();
+ }
+
+ coreType = GLB_Get_Core_Type();
+ if ((GLB_CORE_ID_D0 == coreType)) {
+ /* D0 */
+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */
+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();
+ dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel();
+ if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) {
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ }
+ GLB_Set_DSP_System_CLK_Div(0, 0);
+ } else {
+ /* M0 or LP or invalid(use M0 instead) */
+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */
+ mcuXclkSel = HBN_Get_MCU_XCLK_Sel();
+ mcuRootClkSel = HBN_Get_MCU_Root_CLK_Sel();
+ if ((mcuXclkSel != HBN_MCU_XCLK_RC32M) || (mcuRootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ }
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+ }
+
+ HBN_Set_Xtal_Type(xtalType);
+
+ if (GLB_PLL_NONE == pllType) {
+ GLB_CLK_SET_DUMMY_WAIT;
+ return SUCCESS;
+ }
+
+ if (xtalType == GLB_XTAL_RC32M) {
+ refClk = GLB_PLL_REFCLK_RC32M;
+ } else {
+ refClk = GLB_PLL_REFCLK_XTAL;
+ }
+
+ /* power on wifipll */
+ if (pllType & GLB_PLL_WIFIPLL) {
+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);
+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);
+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &wifiPllCfg_960M[xtalType], 0);
+ }
+
+ /* power on aupll */
+ if (pllType & GLB_PLL_AUPLL) {
+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);
+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);
+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &audioPllCfg_442P368M[xtalType], 0);
+ }
+
+ /* power on cpupll */
+ if (pllType & GLB_PLL_CPUPLL) {
+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);
+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);
+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &cpuPllCfg_380M[xtalType], 0);
+ }
+
+ /* power on mipipll */
+ if (pllType & GLB_PLL_MIPIPLL) {
+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);
+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);
+ GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &mipiPllCfg_1500M[xtalType], 0);
+ }
+
+ /* power on uhspll */
+ if (pllType & GLB_PLL_UHSPLL) {
+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);
+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);
+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &uhsPllCfg_2100M[xtalType], 0);
+ }
+
+ arch_delay_us(75);
+
+ if (xtalType != GLB_XTAL_RC32M) {
+ /* if power on xtal, always set xclk from xtal */
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);
+ }
+
+ /* enable all PLL clock output */
+ /* GLB reg_pll_en = 1, cannot be zero */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
+ /* MM_GLB reg_pll_en = 1, cannot be zero */
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_PLL_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB power off wifi audio cpu PLL
+ *
+ * @param pllType: PLL XTAL type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_Type pllType)
+{
+ uint32_t REG_PLL_BASE_ADDRESS = 0;
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));
+
+ switch (pllType) {
+ case GLB_WAC_PLL_WIFIPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
+ break;
+ case GLB_WAC_PLL_AUPLL:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+ break;
+ case GLB_WAC_PLL_CPUPLL:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;
+ break;
+ default:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+ break;
+ }
+
+ /* cfg0 : pu_aupll=0 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* cfg0 : pu_aupll_sfreg=0 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB wifi audio cpu PLL ref clock select
+ *
+ * @param pllType: PLL XTAL type
+ * @param refClk: PLL ref clock select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)
+{
+ uint32_t REG_PLL_BASE_ADDRESS = 0;
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));
+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));
+
+ switch (pllType) {
+ case GLB_WAC_PLL_WIFIPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
+ break;
+ case GLB_WAC_PLL_AUPLL:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+ break;
+ case GLB_WAC_PLL_CPUPLL:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;
+ break;
+ default:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+ break;
+ }
+
+ /* xxxpll_refclk_sel */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+ if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) {
+ /* wifipll_refclk_sel different from other's pll, 1 means xtal */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1);
+ } else {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);
+ }
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB power on PLL
+ *
+ * @param pllType: PLL XTAL type
+ * @param cfg: GLB PLL configuration
+ * @param waitStable: wait PLL clock stable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable)
+{
+ uint32_t REG_PLL_BASE_ADDRESS = 0;
+ uint32_t tmpVal = 0;
+
+ /* unknown */
+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));
+
+ switch (pllType) {
+ case GLB_WAC_PLL_WIFIPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
+ break;
+ case GLB_WAC_PLL_AUPLL:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+ break;
+ case GLB_WAC_PLL_CPUPLL:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;
+ break;
+ default:
+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+ break;
+ }
+
+ /* Step1:config parameter */
+ /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+ /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);
+
+ /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);
+
+ /* cfg4:Set aupll_sel_sample_clk */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);
+
+ /* cfg5:Set aupll_vco_speed */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);
+
+ /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);
+ if (GLB_WAC_PLL_WIFIPLL == pllType) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin);
+ } else {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);
+ }
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);
+
+ /* Step2:config pu */
+ /* cfg0 : pu_aupll_sfreg=1 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* delay > 2us */
+ arch_delay_us(3);
+
+ /* cfg0 : pu_wifipll=1 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* delay > 2us */
+ arch_delay_us(3);
+
+ /* toggle sdm_reset (pulse 0 > 1us) */
+ /* cfg0 : aupll_sdm_reset */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* Step3:reset pll */
+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */
+ if (GLB_WAC_PLL_AUPLL == pllType) {
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+ if ((cfg->clkpllSdmin == 0x12D0E) || (cfg->clkpllSdmin == 0x1C395) || (cfg->clkpllSdmin == 0x17851) || (cfg->clkpllSdmin == 0x16944) || (cfg->clkpllSdmin == 0x115E5)) {
+ /* 451.548 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14);
+ } else {
+ /* 442.368 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12);
+ }
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+ }
+
+ /* Step4:enable output clock */
+ /* wifipll : cfg5, wifipll_vco_div3_en=1 */
+ if (GLB_WAC_PLL_WIFIPLL == pllType) {
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);
+ }
+ /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);
+ if (GLB_WAC_PLL_WIFIPLL == pllType) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1);
+ }
+ /* cfg8 : wifipll/aupll/cpupll clock enable */
+ switch (pllType) {
+ case GLB_WAC_PLL_WIFIPLL:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10);
+ break;
+ case GLB_WAC_PLL_AUPLL:
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6);
+ break;
+ case GLB_WAC_PLL_CPUPLL:
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4);
+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5);
+ break;
+ default:
+ break;
+ }
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);
+
+ if (waitStable) {
+ /* Wait 1.5*30us */
+ arch_delay_us(45);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB enable or disable USB clock
+ *
+ * @param enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable)
+{
+ uint32_t tmpVal = 0;
+
+ /* pu_usbpll_mmdiv */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);
+ }
+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+
+ /* toggle usbpll_rstb */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);
+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB);
+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);
+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB power off mipi uhs PLL
+ *
+ * @param pllType: PLL XTAL type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType)
+{
+ uint32_t REG_PLL_BASE_ADDRESS = 0;
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_Power_Off_MU_TYPE(pllType));
+
+ switch (pllType) {
+ case GLB_MU_PLL_MIPIPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
+ break;
+ case GLB_MU_PLL_UHSPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;
+ break;
+ default:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
+ break;
+ }
+
+ /* cfg0 : pu_aupll=0 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* cfg0 : pu_aupll_sfreg=0 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB mipi uhs PLL ref clock select
+ *
+ * @param pllType: PLL XTAL type
+ * @param refClk: PLL ref clock select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)
+{
+ uint32_t REG_PLL_BASE_ADDRESS = 0;
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));
+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));
+
+ switch (pllType) {
+ case GLB_MU_PLL_MIPIPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
+ break;
+ case GLB_MU_PLL_UHSPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;
+ break;
+ default:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
+ break;
+ }
+
+ /* xxxpll_refclk_sel */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB power on PLL
+ *
+ * @param pllType: PLL XTAL type
+ * @param cfg: GLB PLL configuration
+ * @param waitStable: wait PLL stable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable)
+{
+ uint32_t REG_PLL_BASE_ADDRESS = 0;
+ uint32_t tmpVal = 0;
+
+ /* unknown */
+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));
+
+ switch (pllType) {
+ case GLB_MU_PLL_MIPIPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
+ break;
+ case GLB_MU_PLL_UHSPLL:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;
+ break;
+ default:
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
+ break;
+ }
+
+ /* Step1:config parameter */
+ /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+ /* cfg4:Set aupll_sel_sample_clk */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);
+
+ /* cfg5:Set aupll_vco_speed */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);
+
+ /* cfg1: uhspll_even_div_en and uhspll_even_div_ratio */
+ if (GLB_MU_PLL_UHSPLL == pllType) {
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_EN, cfg->basicCfg->clkpllEvenDivEn);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_RATIO, cfg->basicCfg->clkpllEvenDivRatio);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+ }
+
+ /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);
+
+ /* Step2:config pu */
+ /* cfg0 : pu_aupll_sfreg=1 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* delay > 2us */
+ arch_delay_us(3);
+
+ /* cfg0 : pu_wifipll=1 */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* delay > 2us */
+ arch_delay_us(3);
+
+ /* toggle sdm_reset (pulse 0 > 1us) */
+ /* cfg0 : aupll_sdm_reset */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ /* Step3:reset pll */
+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+ if (waitStable) {
+ /* Wait 1.5*30us */
+ arch_delay_us(45);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB set display clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param srcClk: source clock type
+ * @param evenDiv: divider in even number
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv)
+{
+ uint32_t tmpVal = 0;
+ uint32_t evenNum = 0;
+
+ CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk));
+ CHECK_PARAM((evenDiv <= 0x7F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);
+
+ if ((evenDiv >= 8) && (evenDiv <= 126)) {
+ evenNum = evenDiv & ~(1 << 0);
+ } else {
+ evenNum = evenDiv;
+ }
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB enable or disable ethernet clock
+ *
+ * @param enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_EMAC_CLK(uint8_t enable)
+{
+ uint32_t tmpVal = 0;
+
+ /* uhspll_even_div_en */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG1);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_UHS_PLL_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GLB output ethernet MAC clock via GPIO
+ *
+ * @param gpio: gpio number,which can be 6/14/22/30
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Output_EMAC_CLK(uint8_t gpio)
+{
+ uint32_t regAddr = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpio << 2);
+ uint32_t regVal = 0x00040F03;
+
+ if ((gpio != GLB_GPIO_PIN_6) &&
+ (gpio != GLB_GPIO_PIN_14) &&
+ (gpio != GLB_GPIO_PIN_12) &&
+ (gpio != GLB_GPIO_PIN_30)) {
+ return ERROR;
+ }
+ /* set gpio in debug function */
+ BL_WR_WORD(regAddr, regVal);
+
+ /* select signal */
+ BL_WR_WORD(0x200002E0 + ((gpio - 6) / 8) * 4, 0x80000010);
+
+ /* output */
+ BL_WR_WORD(0x200002F0, 0x01);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set System clock divider
+ *
+ * @param mcuClkDiv: HCLK divider
+ * @param mcuPBclkDiv: BCLK divider
+ * @param lpClkDiv: LP clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv)
+{
+ uint32_t tmpVal;
+ uint32_t timeout = 1024;
+ HBN_MCU_XCLK_Type xclkSel;
+ HBN_MCU_ROOT_CLK_Type rootClkSel;
+
+ /* get root clock */
+ xclkSel = HBN_Get_MCU_XCLK_Sel();
+ rootClkSel = HBN_Get_MCU_Root_CLK_Sel();
+
+ if ((xclkSel != HBN_MCU_XCLK_RC32M) || (rootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ }
+
+ /* config hclk_div=mcuClkDiv */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, mcuClkDiv);
+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
+
+ /* config bclk_div=mcuPBclkDiv */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, mcuPBclkDiv);
+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
+ /* bclk act pulse */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV_ACT_PULSE, 1);
+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal);
+
+ timeout = 1024;
+ do {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE);
+ } while ((--timeout) && (!tmpVal));
+ if (!timeout) {
+ return ERROR;
+ }
+
+ /* config lp clock div=lpClkDiv */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, lpClkDiv);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal);
+ /* bclk act pulse */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PICO_CLK_DIV_ACT_PULSE, 1);
+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal);
+
+ timeout = 1024;
+ do {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_PICO_CLK_PROT_DONE);
+ } while ((--timeout) && (!tmpVal));
+ if (!timeout) {
+ return ERROR;
+ }
+
+ /* recover root clock */
+ HBN_Set_MCU_XCLK_Sel(xclkSel);
+ HBN_Set_MCU_Root_CLK_Sel(rootClkSel);
+
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get System clock divider
+ *
+ * @param mcuClkDiv: HCLK divider
+ * @param mcuPBclkDiv: BCLK divider
+ * @param lpClkDiv: LP clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv)
+{
+ *mcuClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV);
+ *mcuPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV);
+ *lpClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7), PDS_REG_PICO_DIV);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set mcu System clock
+ *
+ * @param clkFreq: mcu system clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq)
+{
+ uint32_t tmpVal;
+ HBN_MCU_XCLK_Type mcuXclkSel;
+
+ CHECK_PARAM(IS_GLB_MCU_SYS_CLK_TYPE(clkFreq));
+
+ /* get xclk&&rootclk clock */
+ mcuXclkSel = HBN_Get_MCU_XCLK_Sel();
+
+ /* change root clock to rc32m */
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+
+ /* select pll output clock before select root clock */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+ switch (clkFreq) {
+ case GLB_MCU_SYS_CLK_CPUPLL_400M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 0);
+ break;
+ case GLB_MCU_SYS_CLK_WIFIPLL_240M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 2);
+ break;
+ case GLB_MCU_SYS_CLK_WIFIPLL_320M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 3);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);
+
+ /* select root clock */
+ switch (clkFreq) {
+ case GLB_MCU_SYS_CLK_RC32M:
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ break;
+ case GLB_MCU_SYS_CLK_XTAL:
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ break;
+ case GLB_MCU_SYS_CLK_CPUPLL_400M:
+ /* For high speed, set DIV first */
+ GLB_Set_MCU_System_CLK_Div(1, 2, 1);
+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */
+ /* MCU_MISC_IROM_2T_Access_Set(0); */
+ /* unuseful for mcu, useful for dsp, just for safe */
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);
+ /* recover xclk */
+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);
+ break;
+ case GLB_MCU_SYS_CLK_WIFIPLL_240M:
+ /* For high speed, set DIV first */
+ GLB_Set_MCU_System_CLK_Div(0, 2, 1);
+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */
+ /* MCU_MISC_IROM_2T_Access_Set(0); */
+ /* unuseful for mcu, useful for dsp, just for safe */
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);
+ /* recover xclk */
+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);
+ break;
+ case GLB_MCU_SYS_CLK_WIFIPLL_320M:
+ /* overclock, not recommended */
+ /* For high speed, set DIV first */
+ GLB_Set_MCU_System_CLK_Div(0, 3, 1);
+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */
+ /* MCU_MISC_IROM_2T_Access_Set(0); */
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);
+ /* recover xclk */
+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);
+ break;
+ default:
+ break;
+ }
+
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief select DSP0 DSP1 clock div
+ *
+ * @param dspClkDiv: mm glb cpu div
+ * @param dspBclkDiv: mm glb bclk2x div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK_Div(uint8_t dspClkDiv, uint8_t dspBclkDiv)
+{
+ uint32_t tmpVal = 0;
+ uint32_t timeout = 1024;
+ GLB_DSP_XCLK_Type dspXclkSel;
+ GLB_DSP_ROOT_CLK_Type dspRootClkSel;
+
+ /* get root clock */
+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();
+ dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel();
+
+ /* change root clock to rc32m */
+ if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) {
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ }
+
+ /* set div */
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV, dspBclkDiv);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV, dspClkDiv);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV_ACT_PULSE, 1);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ do {
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_STS_BCLK2X_PROT_DONE);
+ } while ((--timeout) && (!tmpVal));
+ if (!timeout) {
+ return ERROR;
+ }
+
+ /* recover root clock */
+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);
+ GLB_Set_DSP_ROOT_CLK_Sel(dspRootClkSel);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get DSP0 DSP1 clock div
+ *
+ * @param dspClkDiv: mm glb cpu div
+ * @param dspBclkDiv: mm glb bclk2x div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_System_CLK_Div(uint8_t *dspClkDiv, uint8_t *dspBclkDiv)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+ *dspBclkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV);
+ *dspClkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set dsp System clock
+ *
+ * @param clkFreq: dsp system clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_Type clkFreq)
+{
+ GLB_DSP_XCLK_Type dspXclkSel;
+
+ CHECK_PARAM(IS_GLB_DSP_SYS_CLK_TYPE(clkFreq));
+
+ /* get root clock */
+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();
+
+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ GLB_Set_DSP_System_CLK_Div(0, 0);
+
+ /* select pll output clock before select root clock */
+ if (GLB_DSP_SYS_CLK_MM_WIFIPLL_240M == clkFreq) {
+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_240M);
+ } else if (GLB_DSP_SYS_CLK_MM_WIFIPLL_320M == clkFreq) {
+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_320M);
+ } else if (GLB_DSP_SYS_CLK_CPUPLL_400M == clkFreq) {
+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_CPUPLL_400M);
+ }
+
+ /* select root clock */
+ switch (clkFreq) {
+ case GLB_DSP_SYS_CLK_RC32M:
+ GLB_Set_DSP_System_CLK_Div(0, 0);
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ break;
+ case GLB_DSP_SYS_CLK_XTAL:
+ GLB_Set_DSP_System_CLK_Div(0, 0);
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ break;
+ case GLB_DSP_SYS_CLK_MM_WIFIPLL_240M:
+ GLB_Set_DSP_System_CLK_Div(0, 1);
+ GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);
+ /* recover xclk */
+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);
+ break;
+ case GLB_DSP_SYS_CLK_MM_WIFIPLL_320M:
+ GLB_Set_DSP_System_CLK_Div(0, 1);
+ GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_320M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);
+ /* recover xclk */
+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);
+ break;
+ case GLB_DSP_SYS_CLK_CPUPLL_400M:
+ GLB_Set_DSP_System_CLK_Div(0, 1);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);
+ /* recover xclk */
+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);
+ break;
+ default:
+ break;
+ }
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief select DSP0 pbus clock div
+ *
+ * @param dspBclkDiv: mm glb bclk2x div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK_Div(uint8_t dspPBclkDiv)
+{
+ uint32_t tmpVal = 0;
+
+ /* set div */
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV, dspPBclkDiv);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get DSP0 pbus clock div
+ *
+ * @param dspBclkDiv: mm glb bclk2x div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBCLK_Div(uint8_t *dspPBclkDiv)
+{
+ *dspPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU), MM_GLB_REG_BCLK1X_DIV);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set dsp pbus clock
+ *
+ * @param pbClkSel: dsp pbus clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_Type pbClkSel)
+{
+ CHECK_PARAM(IS_GLB_DSP_SYS_PBCLK_TYPE(pbClkSel));
+
+ GLB_Set_DSP_PBCLK_Div(0);
+
+ /* select pbroot clock */
+ switch (pbClkSel) {
+ case GLB_DSP_SYS_PBCLK_RC32M:
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_PBCLK_Div(0);
+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK);
+ break;
+ case GLB_DSP_SYS_PBCLK_XTAL:
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);
+ GLB_Set_DSP_PBCLK_Div(0);
+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK);
+ break;
+ case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M:
+ GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_160M);
+ GLB_Set_DSP_PBCLK_Div(0);
+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M);
+ break;
+ case GLB_DSP_SYS_PBCLK_CPUPLL_160M:
+ GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_CPUPLL_160M);
+ GLB_Set_DSP_PBCLK_Div(0);
+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M);
+ break;
+ case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M:
+ GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M);
+ GLB_Set_DSP_PBCLK_Div(1);
+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M);
+ break;
+ default:
+ break;
+ }
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief DSP0 clock enable
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Enable(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief DSP0 clock disable
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Disable(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get xclk clock source Select
+ *
+ * @param None
+ *
+ * @return xclk clock type selection
+ *
+*******************************************************************************/
+GLB_DSP_XCLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_XCLK_Sel(void)
+{
+ return (GLB_DSP_XCLK_Type)(BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU), MM_GLB_REG_XCLK_CLK_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief Select xclk clock source
+ *
+ * @param xclk: xclk clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_Type xclk)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_DSP_XCLK_TYPE(xclk));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL, xclk);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get DSP root clock
+ *
+ * @param None
+ *
+ * @return mm glb root clock type
+ *
+*******************************************************************************/
+GLB_DSP_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_ROOT_CLK_Sel(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t rootclk = 0;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ rootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL);
+ if (0 == rootclk) {
+ /* xclk */
+ return GLB_DSP_ROOT_CLK_XCLK;
+ } else {
+ /* pll */
+ return GLB_DSP_ROOT_CLK_PLL;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief select DSP root clock
+ *
+ * @param rootClk: mm glb root clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_Type rootClk)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_DSP_ROOT_CLK_TYPE(rootClk));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ switch (rootClk) {
+ case GLB_DSP_ROOT_CLK_XCLK:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 0);
+ break;
+ case GLB_DSP_ROOT_CLK_PLL:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 1);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief select DSP muxpll clock
+ *
+ * @param pllClk: mm glb pll clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_Type pllClk)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_PLL_CLK_TYPE(pllClk));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ switch (pllClk) {
+ case GLB_DSP_PLL_CLK_MUXPLL_240M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 0);
+ break;
+ case GLB_DSP_PLL_CLK_MUXPLL_320M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 1);
+ break;
+ case GLB_DSP_PLL_CLK_CPUPLL_400M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 2);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get DSP pbroot clock
+ *
+ * @param None
+ *
+ * @return mm DSP pbroot clock type
+ *
+*******************************************************************************/
+GLB_DSP_PBROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBROOT_CLK_Sel(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t pbrootclk = 0;
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ pbrootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL);
+ switch (pbrootclk) {
+ case 0:
+ return GLB_DSP_PBROOT_CLK_MM_XCLK;
+ case 1:
+ return GLB_DSP_PBROOT_CLK_MM_XCLK;
+ case 2:
+ return GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M;
+ case 3:
+ return GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M;
+ default:
+ return GLB_DSP_PBROOT_CLK_MM_XCLK;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief select DSP pbroot clock
+ *
+ * @param pbrootClk: mm DSP pbroot clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_Type pbrootClk)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_DSP_PBROOT_CLK_TYPE(pbrootClk));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ switch (pbrootClk) {
+ case GLB_DSP_PBROOT_CLK_MM_XCLK:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 0);
+ break;
+ case GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 2);
+ break;
+ case GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 3);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+ GLB_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get core type
+ *
+ * @param None
+ *
+ * @return core type
+ *
+*******************************************************************************/
+GLB_CORE_ID_Type ATTR_CLOCK_SECTION GLB_Get_Core_Type(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_WORD(CORE_ID_ADDRESS);
+
+ switch (tmpVal) {
+ case CORE_ID_M0:
+ return GLB_CORE_ID_M0;
+ case CORE_ID_D0:
+ return GLB_CORE_ID_D0;
+ case CORE_ID_LP:
+ return GLB_CORE_ID_LP;
+ default:
+ return GLB_CORE_ID_INVALID;
+ }
+
+ return GLB_CORE_ID_INVALID;
+}
+
+/****************************************************************************/ /**
+ * @brief hold cpu
+ *
+ * @param coreID: core type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Halt_CPU(GLB_CORE_ID_Type coreID)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));
+
+ switch (coreID) {
+ case GLB_CORE_ID_M0:
+ PDS_Set_MCU0_Clock_Disable();
+ arch_delay_us(1);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ break;
+ case GLB_CORE_ID_D0:
+ GLB_DSP0_Clock_Disable();
+ arch_delay_us(1);
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+ break;
+ case GLB_CORE_ID_LP:
+ PDS_Set_LP_Clock_Disable();
+ arch_delay_us(1);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ break;
+ default:
+ return ERROR;
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief release cpu
+ *
+ * @param coreID: core type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Release_CPU(GLB_CORE_ID_Type coreID)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));
+
+ switch (coreID) {
+ case GLB_CORE_ID_M0:
+ PDS_Set_MCU0_Clock_Enable();
+ arch_delay_us(1);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ break;
+ case GLB_CORE_ID_D0:
+ GLB_DSP0_Clock_Enable();
+ arch_delay_us(1);
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+ break;
+ case GLB_CORE_ID_LP:
+ PDS_Set_LP_Clock_Enable();
+ arch_delay_us(1);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ break;
+ default:
+ return ERROR;
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set CPU reset address
+ *
+ * @param coreID: core type
+ * @param addr: reset address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr)
+{
+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));
+
+ switch (coreID) {
+ case GLB_CORE_ID_M0:
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr);
+ break;
+ case GLB_CORE_ID_D0:
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU0_BOOT, addr);
+ break;
+ case GLB_CORE_ID_LP:
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr);
+ break;
+ default:
+ return ERROR;
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief DSP get MCU interrupt status
+ *
+ * @param intType: MCU interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_DSP_Get_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType)
+{
+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG16) & (1 << intType)) ? SET : RESET;
+ } else {
+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG17) & (1 << (intType - 32))) ? SET : RESET;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief DSP set MCU interrupt mask
+ *
+ * @param intType: MCU interrupt type
+ * @param intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_DSP_Set_MCU_IntMask(GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG18);
+ if (UNMASK != intMask) {
+ tmpVal |= (1 << intType);
+ } else {
+ tmpVal &= ~(1 << intType);
+ }
+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG18, tmpVal);
+ } else {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG19);
+ if (UNMASK != intMask) {
+ tmpVal |= (1 << (intType - 32));
+ } else {
+ tmpVal &= ~(1 << (intType - 32));
+ }
+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG19, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief DSP clear MCU interrupt status
+ *
+ * @param intType: MCU interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_DSP_Clr_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG20);
+ tmpVal |= (1 << intType);
+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG20, tmpVal);
+ } else {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG21);
+ tmpVal |= (1 << (intType - 32));
+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG21, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief DSP set LP interrupt enable
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param intType: LP interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_DSP_Set_LP_IntEn(uint8_t enable, GLB_LP_ALL_INT_Type intType)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG22);
+ if (enable) {
+ tmpVal |= (1 << intType);
+ } else {
+ tmpVal &= ~(1 << intType);
+ }
+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG22, tmpVal);
+ } else {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG23);
+ if (enable) {
+ tmpVal |= (1 << (intType - 32));
+ } else {
+ tmpVal &= ~(1 << (intType - 32));
+ }
+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG23, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief DSP get LP interrupt status
+ *
+ * @param intType: LP interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_DSP_Get_LP_IntStatus(GLB_LP_ALL_INT_Type intType)
+{
+ CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG24) & (1 << intType)) ? SET : RESET;
+ } else {
+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG25) & (1 << (intType - 32))) ? SET : RESET;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief MCU get DSP interrupt status
+ *
+ * @param intType: DSP interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_MCU_Get_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType)
+{
+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA0) & (1 << intType)) ? SET : RESET;
+ } else {
+ return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA1) & (1 << (intType - 32))) ? SET : RESET;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief MCU set DSP interrupt mask
+ *
+ * @param intType: DSP interrupt type
+ * @param intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_MCU_Set_DSP_IntMask(GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0);
+ if (UNMASK != intMask) {
+ tmpVal |= (1 << intType);
+ } else {
+ tmpVal &= ~(1 << intType);
+ }
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0, tmpVal);
+ } else {
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1);
+ if (UNMASK != intMask) {
+ tmpVal |= (1 << (intType - 32));
+ } else {
+ tmpVal &= ~(1 << (intType - 32));
+ }
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief MCU clear DSP interrupt status
+ *
+ * @param intType: DSP interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_MCU_Clr_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));
+
+ if (intType < 32) {
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0);
+ tmpVal |= (1 << intType);
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0, tmpVal);
+ } else {
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1);
+ tmpVal |= (1 << (intType - 32));
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set MTimer clock
+ *
+ * @param enable: enable or disable
+ * @param clkSel: clock selection
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_EMI_CLK(uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_EMI_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x3));
+
+ /* disable EMI clock first */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);
+ switch (clkSel) {
+ case GLB_EMI_CLK_MCU_PBCLK:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 0);
+ break;
+ case GLB_EMI_CLK_CPUPLL_200M_CLK:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 4);
+ break;
+ case GLB_EMI_CLK_WIFIPLL_320M_CLK:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 2);
+ break;
+ case GLB_EMI_CLK_CPUPLL_400M_CLK:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 3);
+ break;
+ default:
+ break;
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Clr_EMI_Reset_Gate(void)
+{
+ uint32_t tmpVal;
+
+ /* clear EMI swrst bit */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S1_EXT_EMI_MISC);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal);
+
+ /* set EMI cgen bit */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S1_EXT_EMI_MISC);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set MTimer clock
+ *
+ * @param enable: enable or disable MTimer clock
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MCU_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM((div <= 0x3FF));
+
+ /* disable MTimer clock first */
+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);
+
+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);
+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);
+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);
+
+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+ }
+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set MTimer clock
+ *
+ * @param enable: enable or disable MTimer clock
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM((div <= 0x3FF));
+
+ /* disable MTimer clock first */
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_C906_RTC_DIV, div);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);
+ }
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set ADC clock
+ *
+ * @param enable: enable frequency divider or not
+ * @param clkSel: ADC clock selection
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x3F));
+
+ /* disable ADC clock first */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set DMA clock
+ *
+ * @param enable: Enable or disable
+ * @param clk: DMA clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ CHECK_PARAM(IS_GLB_DMA_CLK_ID_TYPE(clk));
+
+ if (clk >= GLB_DMA1_CLK_CH0) {
+ /* DMA1 */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG1);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN);
+ if (enable) {
+ tmpVal2 |= (1 << (clk - GLB_DMA1_CLK_CH0));
+ } else {
+ tmpVal2 &= (~(1 << (clk - GLB_DMA1_CLK_CH0)));
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN, tmpVal2);
+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG1, tmpVal);
+ } else {
+ /* DMA0 */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG0);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);
+ if (enable) {
+ tmpVal2 |= (1 << clk);
+ } else {
+ tmpVal2 &= (~(1 << clk));
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);
+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG0, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set peripheral DMA cn
+ *
+ * @param peri: peripheral
+ * @param cn: cn
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_PERI_DMA_TYPE(peri));
+ CHECK_PARAM(IS_GLB_PERI_DMA_CN_SEL_TYPE(cn));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG2);
+ switch (cn) {
+ case GLB_PERI_DMA_CN_SEL_DMA0:
+ tmpVal &= ~(1 << peri);
+ break;
+ case GLB_PERI_DMA_CN_SEL_DMA1:
+ tmpVal |= (1 << peri);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set IR clock divider
+ *
+ * @param enable: enable or disable IR clock
+ * @param clkSel: IR clock type
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x3F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select ir rx gpio (gpio11~gpio13)
+ *
+ * @param gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)
+{
+ uint32_t tmpVal = 0;
+
+ /* Select gpio between gpio9 and gpio23 */
+ if (gpio > 8 && gpio < 24) {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 8);
+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);
+ }
+
+ /* Close ir rx */
+ if (gpio == 0) {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0);
+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable ir led driver
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Enable(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* Enable led driver */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Disable ir led driver
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Disable(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* Disable led driver */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set UART2 IO selection
+ *
+ * @param ioType: UART2 IO selection type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_Type ioType)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_UART2_IO_SEL_TYPE(ioType));
+
+ /* Set uart2 io selection */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART2_IO_SEL, ioType);
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set UART clock
+ *
+ * @param enable: Enable or disable UART clock
+ * @param clkSel: UART clock type
+ * @param div: UART clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((div <= 0x7));
+ CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+ /* disable UART clock first */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);
+
+ /* Set div */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);
+
+ /* Select clock source for uart */
+ HBN_Set_UART_CLK_Sel(clkSel);
+
+ /* Set enable or disable */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select UART signal function
+ *
+ * @param sig: UART signal
+ * @param fun: UART function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)
+{
+ uint32_t sig_pos = 0;
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));
+ CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));
+
+ if (sig < GLB_UART_SIG_8) {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG1);
+ sig_pos = (sig * 4);
+ /* Clear original val */
+ tmpVal &= (~(0xf << sig_pos));
+ /* Set new value */
+ tmpVal |= (fun << sig_pos);
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG1, tmpVal);
+ } else {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG2);
+ sig_pos = ((sig - 8) * 4);
+ /* Clear original val */
+ tmpVal &= (~(0xf << sig_pos));
+ /* Set new value */
+ tmpVal |= (fun << sig_pos);
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG2, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set sflash clock
+ *
+ * @param enable: enable or disable sflash clock
+ * @param clkSel: sflash clock type
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x7));
+
+ /* disable SFLASH clock first */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);
+
+ if (clkSel == GLB_SFLASH_CLK_100M_CPUPLL) {
+ GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_CPUPLL_100M);
+ }
+
+ /* clock divider */
+ /* Select flash clock, all Flash CLKs are divied by PLL_480M */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);
+ switch (clkSel) {
+ case GLB_SFLASH_CLK_120M_WIFIPLL:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);
+ break;
+ case GLB_SFLASH_CLK_XTAL:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);
+ break;
+ case GLB_SFLASH_CLK_100M_CPUPLL:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);
+ break;
+ case GLB_SFLASH_CLK_80M_MUXPLL:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);
+ break;
+ case GLB_SFLASH_CLK_BCLK:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);
+ break;
+ case GLB_SFLASH_CLK_96M_WIFIPLL:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);
+
+ /* enable or disable flash clock */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set I2C clock
+ *
+ * @param enable: Enable or disable I2C clock
+ * @param clkSel: clock selection
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_I2C_CLK_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set I2S clock
+ *
+ * @param refClkEn: ref clock ENABLE or DISABLE
+ * @param refClkDiv: divider
+ * @param inRef: di ref clock
+ * @param outRef: do ref clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((refClkDiv <= 0x3F));
+ CHECK_PARAM(IS_GLB_I2S_DI_REF_CLK_TYPE(inRef));
+ CHECK_PARAM(IS_GLB_I2S_DO_REF_CLK_TYPE(outRef));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DO_REF_CLK_SEL, outRef);
+ if (refClkEn) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DI_REF_CLK_SEL, inRef);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV, refClkDiv);
+ BL_WR_REG(GLB_BASE, GLB_I2S_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set SPI clock
+ *
+ * @param enable: Enable or disable SPI clock
+ * @param clkSel: clock selection
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_SPI_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x1F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set PWM1 clock
+ *
+ * @param ioSel: io select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_PWM1_IO_SEL_TYPE(ioSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM1_IO_SEL, ioSel);
+ BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set PWM2 clock
+ *
+ * @param ioSel: io select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PWM2_IO_Sel(GLB_PWM2_IO_SEL_Type ioSel)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_PWM2_IO_SEL_TYPE(ioSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM2_IO_SEL, ioSel);
+ BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set PDM clock
+ *
+ * @param ioSel: io select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PDM_IO_Sel(GLB_PDM_IO_SEL_Type ioSel)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_PDM_IO_SEL_TYPE(ioSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM_IO_SEL, ioSel);
+ BL_WR_REG(GLB_BASE, GLB_PDM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief select DIG clock source
+ *
+ * @param clkSel: DIG clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)
+{
+ uint32_t tmpVal;
+ uint32_t dig512kEn;
+ uint32_t dig32kEn;
+
+ CHECK_PARAM(IS_GLB_DIG_CLK_TYPE(clkSel));
+
+ /* disable DIG512K and DIG32K clock first */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);
+ dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ /* repristinate DIG512K and DIG32K clock */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set DIG 512K clock
+ *
+ * @param enable: enable or disable DIG 512K clock
+ * @param compensationEn: enable or disable DIG 512K clock compensation
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensationEn, uint8_t div)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM((div <= 0x7F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ if (compensationEn) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set DIG 32K clock
+ *
+ * @param enable: enable or disable DIG 32K clock
+ * @param compensationEn: enable or disable DIG 32K clock compensation
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM((div <= 0x7FF));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ if (compensationEn) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief platform wakeup becomes one of pds_wakeup source
+ *
+ * @param enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
+ }
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief mcu gpio timer clock select
+ *
+ * @param gpioPin: gpio pin number
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+ switch (gpioPin & 0x3) {
+ case 0: /* inout_sig_0 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 0);
+ break;
+ case 1: /* inout_sig_1 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 1);
+ break;
+ case 2: /* inout_sig_2 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 2);
+ break;
+ case 3: /* inout_sig_3 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 3);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief dsp gpio timer clock select
+ *
+ * @param gpioPin: gpio pin number
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Sel_DSP_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+ switch (gpioPin & 0x3) {
+ case 0: /* inout_sig_0 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 0);
+ break;
+ case 1: /* inout_sig_1 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 1);
+ break;
+ case 2: /* inout_sig_2 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 2);
+ break;
+ case 3: /* inout_sig_3 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 3);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief chip clock out0 select
+ *
+ * @param clkOutType: chip clock out0 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+ /* set clk out0 output enable */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief chip clock out1 select
+ *
+ * @param clkOutType: chip clock out1 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+ /* set clk out1 output enable */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief chip clock out2 select
+ *
+ * @param clkOutType: chip clock out2 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+ /* set clk out2 output enable */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief chip clock out3 select
+ *
+ * @param clkOutType: chip clock out3 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+ /* set clk out3 output enable */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief csi dsi clock select
+ *
+ * @param csiClkSel: csi clock select
+ * @param dsiClkSel: dsi clock select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_CSI_DSI_CLK_Sel(GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CSI_TXCLKESC_SEL, csiClkSel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DSI_TXCLKESC_SEL, dsiClkSel);
+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief BMX init
+ *
+ * @param BmxCfg: BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((BmxCfg->timeoutEn) <= 0x1F);
+ CHECK_PARAM(IS_BMX_ARB_TYPE(BmxCfg->arbMod));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_ARB_MODE, BmxCfg->arbMod);
+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(BMX_MCU_TO_IRQn, BMX_TO_IRQHandler);
+#endif
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get BMX TO status
+ *
+ * @param None
+ *
+ * @return BMX TO status
+ *
+*******************************************************************************/
+uint8_t GLB_Get_BMX_TO_Status(void)
+{
+ return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_BMX_CFG0), GLB_STS_BMX_TIMEOUT_STS);
+}
+
+/****************************************************************************/ /**
+ * @brief clear BMX TO status
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Clr_BMX_TO_Status(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);
+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);
+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);
+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief BMX timeout interrupt callback install
+ *
+ * @param intType: BMX timeout interrupt type
+ * @param cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+ CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));
+
+ glbBmxToIntCbfArra[intType] = cbFun;
+
+ return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief BMX Time Out interrupt IRQ handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_TO_IRQHandler(void)
+{
+ BMX_TO_INT_Type intType;
+
+ for (intType = 0; intType < BMX_TO_INT_ALL; intType++) {
+ if (glbBmxToIntCbfArra[intType] != NULL) {
+ glbBmxToIntCbfArra[intType]();
+ }
+ }
+ GLB_Clr_BMX_TO_Status();
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief set audio auto clock
+ *
+ * @param divEn: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ if (divEn) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set audio ADC clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((div <= 0x3F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set audio DAC clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_DAC_CLK(uint8_t enable, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((div <= 0x3F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set audio PDM clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_PDM_CLK(uint8_t enable, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((div <= 0x3F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set audio PDM clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PADC_CLK(uint8_t enable, uint16_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((div <= 0x3F));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PADC_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief invert eth rx clock
+ *
+ * @param enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+ }
+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief invert eth tx clock
+ *
+ * @param enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+ }
+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief invert eth ref clock
+ *
+ * @param enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+ }
+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set eth ref clock select
+ *
+ * @param clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_ETH_REF_CLK_OUT_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set CAM clock
+ *
+ * @param enable: Enable or disable CAM clock
+ * @param clkSel: CAM clock type
+ * @param div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x3));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set SDH clock
+ *
+ * @param enable: Enable or disable
+ * @param clkSel: SDH clock type
+ * @param div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_SDH_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x7));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL, clkSel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+ }
+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief swap UART gpio pins sig function
+ *
+ * @param group: UART swap set group
+ * @param swap: swap or no swap
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap)
+{
+ uint32_t tmpVal = 0;
+ uint32_t tmpVal2 = 0;
+
+ CHECK_PARAM(IS_GLB_UART_SIG_SWAP_GRP_TYPE(group));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET);
+ if (swap) {
+ tmpVal2 |= (1 << group);
+ } else {
+ tmpVal2 &= ~(1 << group);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, tmpVal2);
+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief swap DSP SPI0 MOSI with MISO
+ *
+ * @param newState: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_SWAP, newState);
+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select DSP SPI_0 act mode
+ *
+ * @param mod: SPI work mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_MASTER_MODE, mod);
+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set L2SRAM
+ *
+ * @param h2pfSramRel: make pfh_64k0,pfh_64k1,pfh_64k0 writable
+ * @param vramSramRel: make l2_vram writable
+ * @param subSramRel: make sub_32k0,sub_32k1 writable
+ * @param blaiSramRel: make blai_64k0,blai_64k1 writable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t subSramRel, uint8_t blaiSramRel)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_H2PF_SRAM_REL, h2pfSramRel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_VRAM_SRAM_REL, vramSramRel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SUB_SRAM_REL, subSramRel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_BLAI_SRAM_REL, blaiSramRel);
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL, tmpVal);
+
+ /* Make the above settings effective */
+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SYSRAM_SET, 1);
+ BL_WR_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select DSP SPI_0 act mode
+ *
+ * @param mod: SPI work mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);
+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select SPI_0 act mode
+ *
+ * @param mod: SPI work mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);
+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set flash io parameter
+ *
+ * @param selEmbedded: Select embedded flash pin
+ * @param swap: Select embedded flash swap io0 with io3
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+ if (selEmbedded) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
+ if (swap) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+ }
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+ }
+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+ if (selEmbedded) {
+ GLB_Embedded_Flash_Pad_Enable();
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief software reset
+ *
+ * @param swrst: reset num
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst)
+{
+ uint32_t tmpVal = 0;
+ uint32_t bit = 0;
+ uint32_t regAddr = 0;
+
+ CHECK_PARAM(IS_GLB_AHB_MCU_SW_TYPE(swrst));
+
+ if (swrst < 32) {
+ bit = swrst;
+ regAddr = GLB_BASE + GLB_SWRST_CFG0_OFFSET;
+ } else if (swrst < 64) {
+ bit = swrst - 32;
+ regAddr = GLB_BASE + GLB_SWRST_CFG1_OFFSET;
+ } else if (swrst < 96) {
+ bit = swrst - 64;
+ regAddr = GLB_BASE + GLB_SWRST_CFG2_OFFSET;
+ }
+
+ tmpVal = BL_RD_WORD(regAddr);
+ tmpVal &= ~(1 << bit);
+ BL_WR_WORD(regAddr, tmpVal);
+ BL_DRV_DUMMY;
+ tmpVal = BL_RD_WORD(regAddr);
+ tmpVal |= (1 << bit);
+ BL_WR_WORD(regAddr, tmpVal);
+ BL_DRV_DUMMY;
+ tmpVal = BL_RD_WORD(regAddr);
+ tmpVal &= ~(1 << bit);
+ BL_WR_WORD(regAddr, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief software reset
+ *
+ * @param swrst: reset num
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst)
+{
+ uint32_t tmpVal = 0;
+ uint32_t bit = 0;
+ uint32_t regAddr = 0;
+
+ CHECK_PARAM(IS_GLB_AHB_DSP_SW_TYPE(swrst));
+
+ if (swrst < 32) {
+ bit = swrst;
+ regAddr = MM_GLB_BASE + MM_GLB_MM_SW_SYS_RESET_OFFSET;
+ } else if (swrst < 64) {
+ bit = swrst - 32;
+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_MM_PERI_OFFSET;
+ } else if (swrst < 96) {
+ bit = swrst - 64;
+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_SUB_OFFSET;
+ } else if (swrst < 128) {
+ bit = swrst - 96;
+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_CODEC_SUB_OFFSET;
+ } else if (swrst < 160) {
+ bit = swrst - 128;
+ regAddr = MM_GLB_BASE + MM_GLB_IMAGE_SENSOR_CTRL_OFFSET;
+ }
+
+ tmpVal = BL_RD_WORD(regAddr);
+ tmpVal &= ~(1 << bit);
+ BL_WR_WORD(regAddr, tmpVal);
+ BL_DRV_DUMMY;
+ tmpVal = BL_RD_WORD(regAddr);
+ tmpVal |= (1 << bit);
+ BL_WR_WORD(regAddr, tmpVal);
+ BL_DRV_DUMMY;
+ tmpVal = BL_RD_WORD(regAddr);
+ tmpVal &= ~(1 << bit);
+ BL_WR_WORD(regAddr, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief dis reset
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param disrst: disrst macro
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Disrst_Set(uint8_t enable, GLB_DISRST_Type disrst)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DISRST_TYPE(disrst));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG3);
+ if (enable) {
+ tmpVal |= (1 << disrst);
+ } else {
+ tmpVal &= ~(1 << disrst);
+ }
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get first 1 from u64, then clear it
+ *
+ * @param val: target value
+ * @param bit: first 1 in bit
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit)
+{
+ if (!*val) {
+ return ERROR;
+ }
+
+ for (uint8_t i = 0; i < 64; i++) {
+ if ((*val) & ((uint64_t)1 << i)) {
+ *bit = i;
+ (*val) &= ~((uint64_t)1 << i);
+ break;
+ }
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief hold IPs clock
+ *
+ * @param ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips)
+{
+ /* api request from cjy */
+
+ uint32_t tmpValCfg0 = 0;
+ uint32_t tmpValCfg1 = 0;
+ uint32_t tmpValCfg2 = 0;
+ uint32_t bitfield = 0;
+
+ tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+ tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+ while (ips) {
+ if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+ switch (bitfield) {
+ case GLB_AHB_CLOCK_IP_CPU:
+ tmpValCfg0 &= ~(1 << 0);
+ break;
+ case GLB_AHB_CLOCK_IP_SDU:
+ tmpValCfg0 &= ~(1 << 1);
+ break;
+ case GLB_AHB_CLOCK_IP_SEC:
+ tmpValCfg0 &= ~(1 << 2);
+ tmpValCfg1 &= ~(1 << 3);
+ tmpValCfg1 &= ~(1 << 4);
+ break;
+ case GLB_AHB_CLOCK_IP_DMA_0:
+ tmpValCfg0 &= ~(1 << 3);
+ tmpValCfg1 &= ~(1 << 12);
+ break;
+ case GLB_AHB_CLOCK_IP_DMA_1:
+ tmpValCfg0 &= ~(1 << 3);
+ break;
+ case GLB_AHB_CLOCK_IP_DMA_2:
+ tmpValCfg0 &= ~(1 << 3);
+ tmpValCfg2 &= ~(1 << 24);
+ break;
+ case GLB_AHB_CLOCK_IP_CCI:
+ tmpValCfg0 &= ~(1 << 4);
+ break;
+ case GLB_AHB_CLOCK_IP_RF_TOP:
+ tmpValCfg1 &= ~(1 << 1);
+ break;
+ case GLB_AHB_CLOCK_IP_GPIP:
+ tmpValCfg1 &= ~(1 << 2);
+ break;
+ case GLB_AHB_CLOCK_IP_TZC:
+ tmpValCfg1 &= ~(1 << 5);
+ break;
+ case GLB_AHB_CLOCK_IP_EF_CTRL:
+ tmpValCfg1 &= ~(1 << 7);
+ break;
+ case GLB_AHB_CLOCK_IP_SF_CTRL:
+ tmpValCfg1 &= ~(1 << 11);
+ break;
+ case GLB_AHB_CLOCK_IP_EMAC:
+ tmpValCfg2 &= ~(1 << 19);
+ tmpValCfg2 &= ~(1 << 23);
+ break;
+ case GLB_AHB_CLOCK_IP_UART0:
+ tmpValCfg1 &= ~(1 << 16);
+ break;
+ case GLB_AHB_CLOCK_IP_UART1:
+ tmpValCfg1 &= ~(1 << 17);
+ break;
+ case GLB_AHB_CLOCK_IP_UART2:
+ tmpValCfg1 &= ~(1 << 26);
+ break;
+ case GLB_AHB_CLOCK_IP_UART3:
+ break;
+ case GLB_AHB_CLOCK_IP_SPI:
+ tmpValCfg1 &= ~(1 << 18);
+ break;
+ case GLB_AHB_CLOCK_IP_I2C:
+ tmpValCfg1 &= ~(1 << 19);
+ break;
+ case GLB_AHB_CLOCK_IP_PWM:
+ tmpValCfg1 &= ~(1 << 20);
+ break;
+ case GLB_AHB_CLOCK_IP_TIMER:
+ tmpValCfg1 &= ~(1 << 21);
+ break;
+ case GLB_AHB_CLOCK_IP_IR:
+ tmpValCfg1 &= ~(1 << 22);
+ break;
+ case GLB_AHB_CLOCK_IP_CHECKSUM:
+ tmpValCfg1 &= ~(1 << 23);
+ break;
+ case GLB_AHB_CLOCK_IP_QDEC:
+ break;
+ case GLB_AHB_CLOCK_IP_KYS:
+ break;
+ case GLB_AHB_CLOCK_IP_I2S:
+ tmpValCfg1 &= ~(1 << 27);
+ break;
+ case GLB_AHB_CLOCK_IP_USB11:
+ break;
+ case GLB_AHB_CLOCK_IP_CAM:
+ break;
+ case GLB_AHB_CLOCK_IP_MJPEG:
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+ tmpValCfg2 &= ~(1 << 8);
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+ tmpValCfg2 &= ~(1 << 9);
+ break;
+ case GLB_AHB_CLOCK_IP_ZB_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+ tmpValCfg2 &= ~(1 << 4);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+ tmpValCfg2 &= ~(1 << 10);
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_EMI_MISC:
+ tmpValCfg2 &= ~(1 << 16);
+ break;
+ case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+ tmpValCfg2 &= ~(1 << 17);
+ break;
+ case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+ tmpValCfg2 &= ~(1 << 18);
+ break;
+ case GLB_AHB_CLOCK_IP_USB20:
+ tmpValCfg1 &= ~(1 << 13);
+ break;
+ case GLB_AHB_CLOCK_IP_MIX2:
+ tmpValCfg2 &= ~(1 << 20);
+ break;
+ case GLB_AHB_CLOCK_IP_AUDIO:
+ tmpValCfg2 &= ~(1 << 21);
+ break;
+ case GLB_AHB_CLOCK_IP_SDH:
+ tmpValCfg2 &= ~(1 << 22);
+ break;
+ case GLB_AHB_CLOCK_IP_ZB2_NORMAL:
+ tmpValCfg2 &= ~(1 << 11);
+ break;
+ case GLB_AHB_CLOCK_IP_ZB2_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_I2C1:
+ tmpValCfg1 &= ~(1 << 25);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_PHY:
+ tmpValCfg0 &= ~(1 << 7);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:
+ tmpValCfg0 &= ~(1 << 6);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:
+ tmpValCfg0 &= ~(1 << 5);
+ break;
+ case GLB_AHB_CLOCK_IP_LZ4:
+ tmpValCfg1 &= ~(1 << 29);
+ break;
+ case GLB_AHB_CLOCK_IP_AUPDM:
+ tmpValCfg1 &= ~(1 << 28);
+ break;
+ case GLB_AHB_CLOCK_IP_GAUGE:
+ tmpValCfg1 &= ~(1 << 0);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief release IPs clock
+ *
+ * @param ips: GLB_AHB_CLOCK_xxx | GLB_AHB_CLOCK_xxx | ...... (not GLB_AHB_CLOCK_IP_xxx)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)
+{
+ /* api request from cjy */
+
+ uint32_t tmpValCfg0 = 0;
+ uint32_t tmpValCfg1 = 0;
+ uint32_t tmpValCfg2 = 0;
+ uint32_t bitfield = 0;
+
+ tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+ tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+ while (ips) {
+ if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+ switch (bitfield) {
+ case GLB_AHB_CLOCK_IP_CPU:
+ tmpValCfg0 |= (1 << 0);
+ break;
+ case GLB_AHB_CLOCK_IP_SDU:
+ tmpValCfg0 |= (1 << 1);
+ break;
+ case GLB_AHB_CLOCK_IP_SEC:
+ tmpValCfg0 |= (1 << 2);
+ tmpValCfg1 |= (1 << 3);
+ tmpValCfg1 |= (1 << 4);
+ break;
+ case GLB_AHB_CLOCK_IP_DMA_0:
+ tmpValCfg0 |= (1 << 3);
+ tmpValCfg1 |= (1 << 12);
+ break;
+ case GLB_AHB_CLOCK_IP_DMA_1:
+ tmpValCfg0 |= (1 << 3);
+ break;
+ case GLB_AHB_CLOCK_IP_DMA_2:
+ tmpValCfg0 |= (1 << 3);
+ tmpValCfg2 |= (1 << 24);
+ break;
+ case GLB_AHB_CLOCK_IP_CCI:
+ tmpValCfg0 |= (1 << 4);
+ break;
+ case GLB_AHB_CLOCK_IP_RF_TOP:
+ tmpValCfg1 |= (1 << 1);
+ break;
+ case GLB_AHB_CLOCK_IP_GPIP:
+ tmpValCfg1 |= (1 << 2);
+ break;
+ case GLB_AHB_CLOCK_IP_TZC:
+ tmpValCfg1 |= (1 << 5);
+ break;
+ case GLB_AHB_CLOCK_IP_EF_CTRL:
+ tmpValCfg1 |= (1 << 7);
+ break;
+ case GLB_AHB_CLOCK_IP_SF_CTRL:
+ tmpValCfg1 |= (1 << 11);
+ break;
+ case GLB_AHB_CLOCK_IP_EMAC:
+ tmpValCfg2 |= (1 << 19);
+ tmpValCfg2 |= (1 << 23);
+ break;
+ case GLB_AHB_CLOCK_IP_UART0:
+ tmpValCfg1 |= (1 << 16);
+ break;
+ case GLB_AHB_CLOCK_IP_UART1:
+ tmpValCfg1 |= (1 << 17);
+ break;
+ case GLB_AHB_CLOCK_IP_UART2:
+ tmpValCfg1 |= (1 << 26);
+ break;
+ case GLB_AHB_CLOCK_IP_UART3:
+ break;
+ case GLB_AHB_CLOCK_IP_SPI:
+ tmpValCfg1 |= (1 << 18);
+ break;
+ case GLB_AHB_CLOCK_IP_I2C:
+ tmpValCfg1 |= (1 << 19);
+ break;
+ case GLB_AHB_CLOCK_IP_PWM:
+ tmpValCfg1 |= (1 << 20);
+ break;
+ case GLB_AHB_CLOCK_IP_TIMER:
+ tmpValCfg1 |= (1 << 21);
+ break;
+ case GLB_AHB_CLOCK_IP_IR:
+ tmpValCfg1 |= (1 << 22);
+ break;
+ case GLB_AHB_CLOCK_IP_CHECKSUM:
+ tmpValCfg1 |= (1 << 23);
+ break;
+ case GLB_AHB_CLOCK_IP_QDEC:
+ break;
+ case GLB_AHB_CLOCK_IP_KYS:
+ break;
+ case GLB_AHB_CLOCK_IP_I2S:
+ tmpValCfg1 |= (1 << 23);
+ break;
+ case GLB_AHB_CLOCK_IP_USB11:
+ break;
+ case GLB_AHB_CLOCK_IP_CAM:
+ break;
+ case GLB_AHB_CLOCK_IP_MJPEG:
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+ tmpValCfg2 |= (1 << 8);
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+ tmpValCfg2 |= (1 << 9);
+ break;
+ case GLB_AHB_CLOCK_IP_ZB_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+ tmpValCfg2 |= (1 << 4);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+ tmpValCfg2 |= (1 << 10);
+ break;
+ case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_EMI_MISC:
+ tmpValCfg2 |= (1 << 16);
+ break;
+ case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+ tmpValCfg2 |= (1 << 17);
+ break;
+ case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+ tmpValCfg2 |= (1 << 18);
+ break;
+ case GLB_AHB_CLOCK_IP_USB20:
+ tmpValCfg1 |= (1 << 13);
+ break;
+ case GLB_AHB_CLOCK_IP_MIX2:
+ tmpValCfg2 |= (1 << 20);
+ break;
+ case GLB_AHB_CLOCK_IP_AUDIO:
+ tmpValCfg2 |= (1 << 21);
+ break;
+ case GLB_AHB_CLOCK_IP_SDH:
+ tmpValCfg2 |= (1 << 22);
+ break;
+ case GLB_AHB_CLOCK_IP_ZB2_NORMAL:
+ tmpValCfg2 |= (1 << 11);
+ break;
+ case GLB_AHB_CLOCK_IP_ZB2_LP:
+ break;
+ case GLB_AHB_CLOCK_IP_I2C1:
+ tmpValCfg1 |= (1 << 25);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_PHY:
+ tmpValCfg0 |= (1 << 7);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:
+ tmpValCfg0 |= (1 << 6);
+ break;
+ case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:
+ tmpValCfg0 |= (1 << 5);
+ break;
+ case GLB_AHB_CLOCK_IP_LZ4:
+ tmpValCfg1 |= (1 << 29);
+ break;
+ case GLB_AHB_CLOCK_IP_AUPDM:
+ tmpValCfg1 |= (1 << 28);
+ break;
+ case GLB_AHB_CLOCK_IP_GAUGE:
+ tmpValCfg1 |= (1 << 0);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief hold PSRAM clock
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PSRAM_PER_Clock_Gate(void)
+{
+ uint32_t tmpValCfg2 = 0;
+
+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+ /* GLB_AHB_CLOCK_IP_PSRAM0_CTRL */
+ tmpValCfg2 &= ~(1 << 17);
+ /* GLB_AHB_CLOCK_IP_PSRAM1_CTRL */
+ tmpValCfg2 &= ~(1 << 18);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief release PSRAM clock
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PSRAM_PER_Clock_UnGate(void)
+{
+ uint32_t tmpValCfg2 = 0;
+
+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+ /* GLB_AHB_CLOCK_IP_PSRAM0_CTRL */
+ tmpValCfg2 |= (1 << 17);
+ /* GLB_AHB_CLOCK_IP_PSRAM1_CTRL */
+ tmpValCfg2 |= (1 << 18);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief gate pll clock cgen
+ *
+ * @param clk: pll clock cgen
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);
+ tmpVal &= (~(1 << clk));
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief gate pll clock cgen
+ *
+ * @param clk: pll clock cgen
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);
+ tmpVal |= (1 << clk);
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief select PKA clock source
+ *
+ * @param clkSel: PKA clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief mcu system part reset
+ *
+ * @param sysPart: mcu reset part
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_MCU_SW_SYSTEM_TYPE(sysPart));
+
+ /* reset=0 */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal &= ~(1 << sysPart);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ BL_DRV_DUMMY;
+ /* reset=1 */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal |= (1 << sysPart);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ BL_DRV_DUMMY;
+ /* reset=1 */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal &= ~(1 << sysPart);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Software system reset
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)
+{
+ uint32_t tmpVal;
+
+ /* Swicth DSP clock to RC32M, no divider */
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ GLB_Set_DSP_System_CLK_Div(0, 0);
+
+ /* Swicth MCU clock to RC32M, no divider */
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+
+ /* reset M0/M1/LP/SYS(bus+...+D0+D1) */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+ /* waiting for reset */
+ while (1) {
+ arch_delay_us(10);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Software CPU reset
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)
+{
+ uint32_t tmpVal;
+
+ GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;
+
+ /* Do reset */
+ core = GLB_Get_Core_Type();
+
+ switch (core) {
+ case GLB_CORE_ID_M0:
+ /* Swicth MCU clock to RC32M, no divider */
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ break;
+ case GLB_CORE_ID_D0:
+ /* Swicth DSP clock to RC32M, no divider */
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ GLB_Set_DSP_System_CLK_Div(0, 0);
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+ break;
+ case GLB_CORE_ID_LP:
+ /* Swicth MCU clock to RC32M, no divider */
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+ break;
+ default:
+ break;
+ }
+
+ /* waiting for reset */
+ while (1) {
+ arch_delay_us(10);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Software power on reset
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)
+{
+ uint32_t tmpVal;
+
+ /* Swicth DSP clock to RC32M, no divider */
+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);
+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);
+ GLB_Set_DSP_System_CLK_Div(0, 0);
+
+ /* Swicth MCU clock to RC32M, no divider */
+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);
+
+ /* Do reset */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+ /* waiting for reset */
+ while (1) {
+ arch_delay_us(10);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set auto calc xtal type value
+ *
+ * @param calcXtalType: auto calc xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_XTAL_TYPE(calcXtalType));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);
+ tmpVal = tmpVal & 0xffff0000;
+ tmpVal |= GLB_AUTO_CALC_XTAL_FLAG_VALUE;
+ tmpVal |= calcXtalType;
+ BL_WR_REG(GLB_BASE, GLB_HW_RSV0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set auto calc xtal type value
+ *
+ * @param calcXtalType: auto calc xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);
+ if ((tmpVal & GLB_AUTO_CALC_XTAL_FLAG_MASK) == GLB_AUTO_CALC_XTAL_FLAG_VALUE) {
+ *calcXtalType = (tmpVal & 0xff);
+ return SUCCESS;
+ } else {
+ *calcXtalType = 0;
+ return ERROR;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief set flash id value
+ *
+ * @param idValue: flash id value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue)
+{
+ BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue | BFLB_FLASH_ID_VALID_FLAG));
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get flash id value
+ *
+ * @param None
+ *
+ * @return flash id
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1);
+ if ((tmpVal & BFLB_FLASH_ID_VALID_FLAG) != 0) {
+ return (tmpVal & BFLB_FLASH_ID_VALID_MASK);
+ }
+
+ return 0x00000000;
+}
+
+/****************************************************************************/ /**
+ * @brief set sram_ret value
+ *
+ * @param value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)
+{
+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG0, value);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get sram_ret value
+ *
+ * @param None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_RET(void)
+{
+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG0);
+}
+
+/****************************************************************************/ /**
+ * @brief set sram_slp value
+ *
+ * @param value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)
+{
+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG1, value);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get sram_slp value
+ *
+ * @param None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_SLP(void)
+{
+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG1);
+}
+
+/****************************************************************************/ /**
+ * @brief set sram_param value
+ *
+ * @param value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)
+{
+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG2, value);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get sram_parm value
+ *
+ * @param None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_PARM(void)
+{
+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG2);
+}
+
+/****************************************************************************/ /**
+ * @brief select EM type
+ *
+ * @param emType: EM type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_EM_TYPE(emType));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_CFG3);
+ switch (emType) {
+ case GLB_WRAM160KB_EM0KB:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00);
+ break;
+ case GLB_WRAM144KB_EM16KB:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);
+ break;
+ case GLB_WRAM128KB_EM32KB:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x0F);
+ break;
+ case GLB_WRAM112KB_EM48KB:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x3F);
+ break;
+ case GLB_WRAM96KB_EM64KB:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0xFF);
+ break;
+ default:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);
+ break;
+ }
+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set psram clock
+ *
+ * @param id: psram id
+ * @param enable: enable or disable psram clock
+ * @param pll: psram pll clock
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+ uint32_t en = 0;
+
+ CHECK_PARAM(IS_GLB_PSRAM_PLL_TYPE(pll));
+ CHECK_PARAM((div <= 0x3));
+
+ en = enable ? 1 : 0;
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);
+ switch (pll) {
+ case GLB_PSRAM_EMI_CPUPLL_400M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_CPUPLL_400M, en);
+ break;
+ case GLB_PSRAM_EMI_WIFIPLL_320M:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_WIFIPLL_320M, en);
+ break;
+ case GLB_PSRAM_EMI_AUPLL_DIV1:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_AUPLL_DIV1, en);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+ if (id == 1) {
+ /* psram B */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_EN, en);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL, pll);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV, div);
+ }
+ BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief trim ldo18io vout
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18IO_Vout(void)
+{
+ Efuse_Ana_LDO18IO_VOUT_Trim_Type trim;
+ uint32_t tmpVal = 0;
+
+ EF_Ctrl_Read_LDO18IO_Vout_Trim(&trim);
+ if (trim.trimLdo18ioVoutEn) {
+ if (trim.trimLdo18ioVoutParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18ioVoutVal, 4)) {
+ tmpVal = BL_RD_REG(AON_BASE, AON_LDO18IO);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO18IO_VOUT_TRIM_AON, trim.trimLdo18ioVoutVal);
+ BL_WR_REG(AON_BASE, AON_LDO18IO, tmpVal);
+ return SUCCESS;
+ }
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief trim ldo18flash vout
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18FLASH_Vout(void)
+{
+ Efuse_Ana_LDO18FLASH_Trim_Type trim;
+ uint32_t tmpVal = 0;
+
+ EF_Ctrl_Read_LDO18FLASH_Trim(&trim);
+ if (trim.trimLdo18flashVoutAonEn) {
+ if (trim.trimLdo18flashVoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18flashVoutAon, 4)) {
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18FLASH_VOUT_TRIM, trim.trimLdo18flashVoutAon);
+ BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal);
+ return SUCCESS;
+ }
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief set cnn clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param clkSel: cnn clock type
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_CNN_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x7));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV, div);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL, clkSel);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set display clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param clkSel: display clock type
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_DP_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0xF));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV, div);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL, clkSel);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_DP_CLK, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set DSP clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param clkSel: DSP clock type
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_CLK(uint8_t enable, GLB_DSP_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_CLK_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_DIV, div);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_SEL, clkSel);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_DP_CLK, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set h264 clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param clkSel: h264 clock type
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_H264_CLK_TYPE(clkSel));
+ CHECK_PARAM((div <= 0x7));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV, div);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL, clkSel);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set spi clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_SPI_CLK_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL, clkSel);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV, div);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set uart0 clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param uartClk: mm glb uart clock type
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk));
+ CHECK_PARAM((div <= 0x7));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV, div);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set uart1 clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param uartClk: mm glb uart clock type
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_UART1_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk));
+ CHECK_PARAM((div <= 0x7));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV, div);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set i2c0 clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param divEn: div enable
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_I2C0_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV, div);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);
+ }
+ if (divEn) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set i2c1 clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param divEn: div enable
+ * @param div: div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV, div);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);
+ }
+ if (divEn) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN);
+ }
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief sw sys reset
+ *
+ * @param sysPart: reset type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_SW_SYSTEM_TYPE(sysPart));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal &= ~(1 << sysPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+ BL_DRV_DUMMY;
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal |= (1 << sysPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+ BL_DRV_DUMMY;
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);
+ tmpVal &= ~(1 << sysPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief peripheral reset
+ *
+ * @param periPart: reset type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_PERIPHERAL_TYPE(periPart));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);
+ tmpVal &= ~(1 << periPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);
+ tmpVal |= (1 << periPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);
+ tmpVal &= ~(1 << periPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief sub reset
+ *
+ * @param subPart: reset type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Sub_Reset(GLB_DSP_SUB_Type subPart)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_SUB_TYPE(subPart));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB);
+ tmpVal &= ~(1 << subPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB);
+ tmpVal |= (1 << subPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB);
+ tmpVal &= ~(1 << subPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief codec sub reset
+ *
+ * @param codecPart: reset type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_CODEC_SUB_TYPE(codecPart));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);
+ tmpVal &= ~(1 << codecPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);
+ tmpVal |= (1 << codecPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);
+ tmpVal &= ~(1 << codecPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief image sensor reset
+ *
+ * @param imageSensorPart: reset type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_GLB_DSP_IMAGE_SENSOR_TYPE(imageSensorPart));
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);
+ tmpVal &= ~(1 << imageSensorPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);
+ tmpVal |= (1 << imageSensorPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);
+
+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);
+ tmpVal &= ~(1 << imageSensorPart);
+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief reconfigure WIFIPLL clock
+ *
+ * @param xtalType: XTAL frequency type
+ * @param pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList)
+{
+ GLB_PLL_REF_CLK_Type refClk;
+
+ if (xtalType == GLB_XTAL_RC32M) {
+ refClk = GLB_PLL_REFCLK_RC32M;
+ } else {
+ refClk = GLB_PLL_REFCLK_XTAL;
+ }
+
+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);
+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);
+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 1);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief reconfigure AUPLL clock
+ *
+ * @param xtalType: XTAL frequency type
+ * @param pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList)
+{
+ GLB_PLL_REF_CLK_Type refClk;
+
+ if (xtalType == GLB_XTAL_RC32M) {
+ refClk = GLB_PLL_REFCLK_RC32M;
+ } else {
+ refClk = GLB_PLL_REFCLK_XTAL;
+ }
+
+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);
+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);
+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 1);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief reconfigure CPUPLL clock
+ *
+ * @param xtalType: XTAL frequency type
+ * @param pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList)
+{
+ GLB_PLL_REF_CLK_Type refClk;
+
+ if (xtalType == GLB_XTAL_RC32M) {
+ refClk = GLB_PLL_REFCLK_RC32M;
+ } else {
+ refClk = GLB_PLL_REFCLK_XTAL;
+ }
+
+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);
+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);
+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 1);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief reconfigure MIPIPLL clock
+ *
+ * @param xtalType: XTAL frequency type
+ * @param pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type *pllCfgList)
+{
+ GLB_PLL_REF_CLK_Type refClk;
+
+ if (xtalType == GLB_XTAL_RC32M) {
+ refClk = GLB_PLL_REFCLK_RC32M;
+ } else {
+ refClk = GLB_PLL_REFCLK_XTAL;
+ }
+
+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);
+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);
+ GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 1);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief reconfigure MIPIPLL clock div
+ *
+ * @param divEn: div enable
+ * @param divRatio: div ratio
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio)
+{
+ uint32_t REG_PLL_BASE_ADDRESS = 0;
+ uint32_t tmpVal = 0;
+
+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
+
+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio);
+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief reconfigure UHSPLL clock
+ *
+ * @param xtalType: XTAL frequency type
+ * @param pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type *pllCfgList)
+{
+ GLB_PLL_REF_CLK_Type refClk;
+
+ if (xtalType == GLB_XTAL_RC32M) {
+ refClk = GLB_PLL_REFCLK_RC32M;
+ } else {
+ refClk = GLB_PLL_REFCLK_XTAL;
+ }
+
+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);
+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);
+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 1);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set ldo15cis vout select
+ *
+ * @param ldoLevel: ldo level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_Type ldoLevel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_GLB_LDO15CIS_LEVEL_TYPE(ldoLevel));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO15CIS);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO15CIS_VOUT_SEL, ldoLevel);
+ BL_WR_REG(GLB_BASE, GLB_LDO15CIS, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief config mipipll for CSI
+ *
+ * @param postDivSel: mipipll post div sel
+ * @param sdmin: mipipll sdmin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CSI_Config_MIPIPLL(uint8_t postDivSel, uint32_t sdmin)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG5);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_VCO_POSTDIV_SEL, postDivSel);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG5, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG6);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_SDMIN, sdmin);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG6, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief power up mipipll for CSI
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CSI_Power_Up_MIPIPLL(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_MIPIPLL_SFREG, 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_MIPIPLL, 1);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_FBDV_RSTB, 1);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_FBDV_RSTB, 0);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+ arch_delay_us(2);
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_FBDV_RSTB, 1);
+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_glb_gpio.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_glb_gpio.c
new file mode 100644
index 00000000..07ff3251
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_glb_gpio.c
@@ -0,0 +1,955 @@
+/**
+ ******************************************************************************
+ * @file bl808_glb_gpio.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808_clock.h"
+#include "bl808_glb.h"
+#include "bl808_hbn.h"
+#include "bl808_pds.h"
+#include "bl808_glb_gpio.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup GLB_GPIO
+ * @{
+ */
+
+/** @defgroup GLB_GPIO_Private_Macros
+ * @{
+ */
+#define GLB_GPIO_INT0_NUM (GLB_GPIO_PIN_MAX)
+#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
+
+/*@} end of group GLB_GPIO_Private_Macros */
+#define GLB_GPIO_TIMEOUT_COUNT (320 * 1000)
+/** @defgroup GLB_GPIO_Private_Types
+ * @{
+ */
+
+/*@} end of group GLB_GPIO_Private_Types */
+
+/** @defgroup GLB_GPIO_Private_Variables
+ * @{
+ */
+
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL };
+
+static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_ALL] = { NULL };
+#endif
+
+/*@} end of group GLB_GPIO_Private_Variables */
+
+/** @defgroup GLB_GPIO_Global_Variables
+ * @{
+ */
+
+/*@} end of group GLB_GPIO_Global_Variables */
+
+/** @defgroup GLB_GPIO_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group GLB_GPIO_Private_Fun_Declaration */
+
+/** @defgroup GLB_GPIO_Private_Functions
+ * @{
+ */
+
+/*@} end of group GLB_GPIO_Private_Functions */
+
+/** @defgroup GLB_GPIO_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief GPIO initialization
+ *
+ * @param cfg: GPIO configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+ uint8_t gpioPin = cfg->gpioPin;
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */
+ /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */
+ /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */
+ /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ /* Disable output anyway*/
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ /* input/output, pull up/down, drive, smt, function */
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+ if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+ /* not analog mode */
+
+ if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+ } else {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+ }
+
+ if (cfg->pullType == GPIO_PULL_UP) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+ } else if (cfg->pullType == GPIO_PULL_DOWN) {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+ }
+ if (gpioPin == GLB_GPIO_PIN_40) {
+ *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 27);
+ } else if (gpioPin == GLB_GPIO_PIN_41) {
+ *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 28);
+ }
+ } else {
+ /* analog mode */
+
+ /* clear ie && oe */
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+
+ /* clear pu && pd */
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+ }
+
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_MODE, cfg->outputMode);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief init GPIO function in pin list
+ *
+ * @param gpioFun: GPIO pin function
+ * @param pinList: GPIO pin list
+ * @param cnt: GPIO pin count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
+{
+ GLB_GPIO_Cfg_Type gpioCfg = {
+ .gpioPin = GLB_GPIO_PIN_0,
+ .gpioFun = (uint8_t)gpioFun,
+ .gpioMode = GPIO_MODE_AF,
+ .pullType = GPIO_PULL_UP,
+ .drive = 1,
+ .smtCtrl = 1
+ };
+
+ if (gpioFun == GPIO_FUN_ANALOG) {
+ gpioCfg.gpioMode = GPIO_MODE_ANALOG;
+ }
+
+ for (uint8_t i = 0; i < cnt; i++) {
+ gpioCfg.gpioPin = pinList[i];
+ GLB_GPIO_Init(&gpioCfg);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GPIO set input function enable
+ *
+ * @param gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Embedded flash set input function enable
+ *
+ * @param gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Embedded_Flash_Pad_Enable(void)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+ uint32_t gpioPin;
+
+ for (gpioPin = 48; gpioPin < 52; gpioPin++) {
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GPIO set input function disable
+ *
+ * @param gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GPIO set output function enable
+ *
+ * @param gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GPIO set output function disable
+ *
+ * @param gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GPIO set High-Z
+ *
+ * @param gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ /* Disable output anyway*/
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ /* ie=0, oe=0, drive=0, smt=0, pu=1 (pull up), pd=0, func=swgpio */
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, 0);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); /* pull up */
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, 0xB);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get GPIO function
+ *
+ * @param gpioPin: GPIO type
+ *
+ * @return GPIO function
+ *
+*******************************************************************************/
+uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
+}
+
+/****************************************************************************/ /**
+ * @brief Read GPIO
+ *
+ * @param gpioPin: GPIO type
+ *
+ * @return GPIO value
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_I) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief Write GPIO
+ *
+ * @param gpioPin: GPIO type
+ * @param val: GPIO value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+ if (val) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
+ }
+
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief turn GPIO output high
+ *
+ * @param gpioPin: GPIO type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin)
+{
+ if (gpioPin < GLB_GPIO_PIN_32) {
+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG138_OFFSET, 1 << gpioPin);
+ } else {
+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG139_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief turn GPIO output low
+ *
+ * @param gpioPin: GPIO type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin)
+{
+ if (gpioPin < GLB_GPIO_PIN_32) {
+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG140_OFFSET, 1 << gpioPin);
+ } else {
+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG141_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GPIO interrupt initialization
+ *
+ * @param intCfg: GPIO interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+ uint32_t gpioPin = intCfg->gpioPin;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MODE_SET, intCfg->trig);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intCfg->intMask);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set GLB GPIO interrupt mask
+ *
+ * @param gpioPin: GPIO type
+ * @param intMask: GPIO interrupt MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intMask);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get GLB GPIO interrupt status
+ *
+ * @param gpioPin: GPIO type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ return BL_GET_REG_BITS_VAL(BL_RD_WORD(gpioCfgAddress), GLB_GPIO_0_INT_STAT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief Clear GLB GPIO interrupt status
+ *
+ * @param gpioPin: GPIO type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+ uint32_t gpioCfgAddress;
+ uint32_t tmpVal;
+
+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+ /* clr=1 */
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ /* clr=0 */
+ tmpVal = BL_RD_WORD(gpioCfgAddress);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
+ BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+ return SUCCESS;
+}
+
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_FIFO_IRQHandler(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_END_MASK)) {
+ if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END] != NULL) {
+ glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END]();
+ }
+ }
+
+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FER_MASK)) {
+ if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER] != NULL) {
+ glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER]();
+ }
+ }
+
+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK)) {
+ if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO] != NULL) {
+ glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO]();
+ }
+ }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief GPIO INT0 IRQHandler install
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
+#endif
+
+ return SUCCESS;
+}
+
+BL_Err_Type GLB_GPIO_FIFO_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(GPIO_DMA_IRQn, GPIO_FIFO_IRQHandler);
+#endif
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief GPIO interrupt IRQ handler callback install
+ *
+ * @param gpioPin: GPIO pin type
+ * @param cbFun: callback function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
+{
+ if (gpioPin < GLB_GPIO_PIN_MAX) {
+ glbGpioInt0CbfArra[gpioPin] = cbFun;
+ }
+
+ return SUCCESS;
+}
+#endif
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun)
+{
+ /* Check the parameters */
+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+
+ glbGpioFifoCbfArra[intType] = cbFun;
+
+ return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief GPIO interrupt IRQ handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_INT0_IRQHandler(void)
+{
+ GLB_GPIO_Type gpioPin;
+ uint32_t timeOut = 0;
+
+ for (gpioPin = GLB_GPIO_PIN_0; gpioPin < GLB_GPIO_PIN_MAX; gpioPin++) {
+ if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
+ GLB_Clr_GPIO_IntStatus(gpioPin);
+
+ /* timeout check */
+ timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+
+ do {
+ timeOut--;
+ } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
+
+ if (!timeOut) {
+ //MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+ }
+
+ if (glbGpioInt0CbfArra[gpioPin] != NULL) {
+ /* Call the callback function */
+ glbGpioInt0CbfArra[gpioPin]();
+ }
+ }
+ }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief GPIO fifo function initialization
+ *
+ * @param cfg: GPIO fifo configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code0Phase));
+ CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code1Phase));
+ CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->latch));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_TX_EN, cfg->fifoDmaEnable);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_TX_FIFO_TH, cfg->fifoDmaThreshold);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_OUT_SEL_LATCH, cfg->latch);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_PARK_VALUE, cfg->idle);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE0_HIGH_TIME, cfg->code0FirstTime);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE1_HIGH_TIME, cfg->code1FirstTime);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE_TOTAL_TIME, cfg->codeTotalTime);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE0_HIGH, cfg->code0Phase);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE1_HIGH, cfg->code1Phase);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
+
+ GLB_GPIO_FIFO_IRQHandler_Install();
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Push data to GPIO fifo
+ *
+ * @param data: the pointer of data buffer
+ * @param len: the len of data buffer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len)
+{
+ uint32_t txLen = 0;
+ uint32_t timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
+
+ while (txLen < len) {
+ if (GLB_GPIO_Fifo_GetCount() > 0) {
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG144, data[txLen++]);
+ timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
+ } else {
+ timeoutCnt--;
+
+ if (timeoutCnt == 0) {
+ return TIMEOUT;
+ }
+ }
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get GPIO fifo available count
+ *
+ * @param None
+ *
+ * @return The count of available count
+ *
+*******************************************************************************/
+uint32_t GLB_GPIO_Fifo_GetCount(void)
+{
+ return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief Clear GPIO fifo
+ *
+ * @param None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_Clear(void)
+{
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, BL_SET_REG_BIT(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CLR));
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Mask or Unmask GPIO FIFO Interrupt
+ *
+ * @param intType: interrupt type
+ * @param intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+ /* Mask or unmask certain or all interrupt */
+ if (MASK == intMask) {
+ switch (intType) {
+ case GLB_GPIO_FIFO_INT_FER:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+ break;
+
+ case GLB_GPIO_FIFO_INT_FIFO:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+ break;
+
+ case GLB_GPIO_FIFO_INT_END:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+ break;
+
+ case GLB_GPIO_FIFO_INT_ALL:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+ break;
+
+ default:
+ break;
+ }
+ } else {
+ switch (intType) {
+ case GLB_GPIO_FIFO_INT_FER:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+ break;
+
+ case GLB_GPIO_FIFO_INT_FIFO:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+ break;
+
+ case GLB_GPIO_FIFO_INT_END:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+ break;
+
+ case GLB_GPIO_FIFO_INT_ALL:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ /* Write back */
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Clear GPIO fifo interrupt
+ *
+ * @param intType: interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+ /* Clear certain or all interrupt */
+ switch (intType) {
+ case GLB_GPIO_FIFO_INT_FER:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+ break;
+
+ case GLB_GPIO_FIFO_INT_FIFO:
+ //tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+ break;
+
+ case GLB_GPIO_FIFO_INT_END:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
+ break;
+
+ case GLB_GPIO_FIFO_INT_ALL:
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Write back */
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get GPIO fifo interrupt status
+ *
+ * @param intType: interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+
+ /* Get certain or all interrupt status */
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+ if (GLB_GPIO_FIFO_INT_ALL == intType) {
+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) ||
+ BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) ||
+ BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT)) {
+ return SET;
+ } else {
+ return RESET;
+ }
+ } else {
+ switch (intType) {
+ case GLB_GPIO_FIFO_INT_FER:
+ return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT);
+
+ case GLB_GPIO_FIFO_INT_FIFO:
+ return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT);
+
+ case GLB_GPIO_FIFO_INT_END:
+ return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT);
+
+ default:
+ return RESET;
+ }
+ }
+}
+BL_Sts_Type GLB_GPIO_Fifo_Enable(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
+
+ return SUCCESS;
+}
+BL_Sts_Type GLB_GPIO_Fifo_Disable(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
+
+ return SUCCESS;
+}
+
+/*@} end of group GLB_GPIO_Public_Functions */
+
+/*@} end of group GLB_GPIO */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_hbn.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_hbn.c
new file mode 100644
index 00000000..8baba502
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_hbn.c
@@ -0,0 +1,2136 @@
+/**
+ ******************************************************************************
+ * @file bl808_hbn.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808_hbn.h"
+#include "bl808_glb.h"
+#include "bflb_xip_sflash.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup HBN
+ * @{
+ */
+
+/** @defgroup HBN_Private_Macros
+ * @{
+ */
+#define HBN_CLK_SET_DUMMY_WAIT \
+ { \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ }
+
+/*@} end of group HBN_Private_Macros */
+
+/** @defgroup HBN_Private_Types
+ * @{
+ */
+
+/*@} end of group HBN_Private_Types */
+
+/** @defgroup HBN_Private_Variables
+ * @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_INT_MAX] = { NULL };
+static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_INT_MAX] = { NULL };
+#endif
+
+/*@} end of group HBN_Private_Variables */
+
+/** @defgroup HBN_Global_Variables
+ * @{
+ */
+
+/*@} end of group HBN_Global_Variables */
+
+/** @defgroup HBN_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group HBN_Private_Fun_Declaration */
+
+/** @defgroup HBN_Private_Functions
+ * @{
+ */
+
+/*@} end of group HBN_Private_Functions */
+
+/** @defgroup HBN_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Enter HBN
+ *
+ * @param cfg: HBN APP Config
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
+{
+ uint32_t valLow = 0, valHigh = 0;
+ uint64_t val;
+
+ if (cfg->useXtal32k) {
+ HBN_32K_Sel(HBN_32K_XTAL);
+ } else {
+ HBN_32K_Sel(HBN_32K_RC);
+ HBN_Power_Off_Xtal_32K();
+ }
+
+ /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
+ HBN_Hw_Pu_Pd_Cfg(DISABLE);
+
+ HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));
+ if (cfg->gpioWakeupSrc != 0) {
+ HBN_GPIO_INT_Enable(cfg->gpioTrigType);
+ }
+
+ /* HBN RTC config and enable */
+ HBN_Clear_RTC_Counter();
+ if (cfg->sleepTime != 0) {
+ HBN_Get_RTC_Timer_Val(&valLow, &valHigh);
+ val = valLow + ((uint64_t)valHigh << 32);
+ val += cfg->sleepTime;
+ HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);
+ HBN_Enable_RTC_Counter();
+ }
+
+ HBN_Power_Down_Flash(cfg->flashCfg);
+ //HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */
+
+ GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
+ GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_RC32M);
+ GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_RC32M);
+
+ HBN_Enable(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel, cfg->dcdcPuSeq);
+}
+
+/****************************************************************************/ /**
+ * @brief power down and switch clock
+ *
+ * @param flashCfg: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg)
+{
+ spi_flash_cfg_type bhFlashCfg;
+
+ if (flashCfg == NULL) {
+ L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(spi_flash_cfg_type));
+ bflb_xip_sflash_read_via_cache_need_lock(BL808_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg),
+ sizeof(spi_flash_cfg_type), 0, 0);
+ L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(spi_flash_cfg_type));
+
+ bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+ bflb_sflash_reset_continue_read(&bhFlashCfg);
+ } else {
+ bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+ bflb_sflash_reset_continue_read(flashCfg);
+ }
+
+ bflb_sflash_powerdown();
+}
+
+/****************************************************************************/ /**
+ * @brief Enable HBN mode
+ *
+ * @param aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to
+ * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param ldoLevel: LDO volatge level
+ * @param hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+ CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+ /* Setting from guide */
+ /* HBN_SRAM Retion */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+ BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+ /* AON GPIO IE */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ /* HBN mode LDO level */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ /* power on dcdc11&&dcdc18 sequence */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ if (dcdcPuSeq) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_DCDC_AON);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_DCDC_AON);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);
+ }
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ /* Select RC32M */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+ __NOP();
+ __NOP();
+ __NOP();
+ __NOP();
+
+ /* Set HBN flag */
+ BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+ switch (hbnLevel) {
+ case HBN_LEVEL_0:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+ break;
+
+ case HBN_LEVEL_1:
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+ break;
+
+ default:
+ break;
+ }
+ /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ /* Enable HBN mode */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ while (1) {
+ arch_delay_ms(1000);
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Reset HBN mode
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ /* Reset HBN mode */
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST);
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable HBN PIR
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Enable(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);
+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Disable HBN PIR
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Disable(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);
+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Config HBN PIR interrupt
+ *
+ * @param pirIntCfg: HBN PIR interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg)
+{
+ uint32_t tmpVal;
+ uint32_t bit4 = 0;
+ uint32_t bit5 = 0;
+ uint32_t bitVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+ /* low trigger interrupt */
+ if (pirIntCfg->lowIntEn == ENABLE) {
+ bit5 = 0;
+ } else {
+ bit5 = 1;
+ }
+
+ /* high trigger interrupt */
+ if (pirIntCfg->highIntEn == ENABLE) {
+ bit4 = 0;
+ } else {
+ bit4 = 1;
+ }
+
+ bitVal = bit4 | (bit5 << 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);
+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select HBN PIR low pass filter
+ *
+ * @param lpf: HBN PIR low pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);
+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select HBN PIR high pass filter
+ *
+ * @param hpf: HBN PIR high pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);
+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set HBN PIR threshold value
+ *
+ * @param threshold: HBN PIR threshold value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM((threshold <= 0x3FFF));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);
+ BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get HBN PIR threshold value
+ *
+ * @param None
+ *
+ * @return HBN PIR threshold value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Threshold(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH);
+}
+
+/****************************************************************************/ /**
+ * @brief Set HBN PIR interval value
+ *
+ * @param interval: HBN PIR interval value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM((interval <= 0xFFF));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);
+ BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get HBN PIR interval value
+ *
+ * @param None
+ *
+ * @return HBN PIR interval value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Interval(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+
+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL);
+}
+
+/****************************************************************************/ /**
+ * @brief get HBN bod out state
+ *
+ * @param None
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_BOD_OUT_State(void)
+{
+ return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_BOR_CFG), HBN_R_BOD_OUT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief set HBN bod config
+ *
+ * @param enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset
+ * @param threshold: bod threshold
+ * @param mode: bod work mode with por
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_BOD_THRES_TYPE(threshold));
+ CHECK_PARAM(IS_HBN_BOD_MODE_TYPE(mode));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+ if (enable) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 1);
+ } else {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 0);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, threshold);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_SEL, mode);
+ BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN set ldo11aon voltage out
+ *
+ * @param ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN set ldo11rt voltage out
+ *
+ * @param ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief HBN set ldo11_Rtc voltage out
+ *
+ * @param ldoLevel: LDO11_Rtc volatge level
+ * 0:0.60V 1:0.65V 2:0.70V 3:0.75V
+ * 4:0.80V 5:0.85V 6:0.9V 7:0.95V
+ * 8:1.0V 9:1.05V 10:1.1V 11:1.15V,
+ * 12:1.2V 13:1.25V 14:1.3V 15:1.35V
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+ HBN_RTC_MISC_Type rtcMiscCfg;
+
+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+ HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg);
+ rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel;
+ HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN set ldo11 all voltage out, not include dcdc11
+ *
+ * @param ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+ * @note not support LDO11_Rtc 0.65v & 0.6v
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+ uint32_t tmpVal;
+ HBN_RTC_MISC_Type rtcMiscCfg;
+
+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+ HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg);
+ rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel;
+ HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN select 32K
+ *
+ * @param clkType: HBN 32k clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType));
+
+ HBN_Trim_RC32K();
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Select uart clock source
+ *
+ * @param clkSel: uart clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ if ((HBN_UART_CLK_MCU_PBCLK == clkSel) || (HBN_UART_CLK_160M == clkSel)) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL2, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel);
+ } else {
+ /* mcu_bclk as default */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL2, 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, 0);
+ }
+
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get xclk clock source Select
+ *
+ * @param None
+ *
+ * @return xclk clock type selection
+ *
+*******************************************************************************/
+HBN_MCU_XCLK_Type ATTR_CLOCK_SECTION HBN_Get_MCU_XCLK_Sel(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+ return (HBN_MCU_XCLK_Type)(tmpVal & 0x1);
+}
+
+/****************************************************************************/ /**
+ * @brief Select xclk clock source
+ *
+ * @param xclk: xclk clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_Type xclk)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ CHECK_PARAM(IS_HBN_MCU_XCLK_TYPE(xclk));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+ switch (xclk) {
+ case HBN_MCU_XCLK_RC32M:
+ tmpVal2 &= (~(1 << 0));
+ break;
+ case HBN_MCU_XCLK_XTAL:
+ tmpVal2 |= (1 << 0);
+ break;
+ default:
+ break;
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+ HBN_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get root clock selection
+ *
+ * @param None
+ *
+ * @return root clock selection
+ *
+*******************************************************************************/
+HBN_MCU_ROOT_CLK_Type ATTR_CLOCK_SECTION HBN_Get_MCU_Root_CLK_Sel(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t rootClkSel = 0;
+
+ /* root_clock_select = hbn_root_clk_sel[1] */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ rootClkSel = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL) >> 1;
+ if (0 == rootClkSel) {
+ return HBN_MCU_ROOT_CLK_XCLK;
+ } else {
+ return HBN_MCU_ROOT_CLK_PLL;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Select root clk source
+ *
+ * @param rootClk: root clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_Type rootClk)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ CHECK_PARAM(IS_HBN_MCU_ROOT_CLK_TYPE(rootClk));
+
+ /* root_clock_select = hbn_root_clk_sel[1] */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+ switch (rootClk) {
+ case HBN_MCU_ROOT_CLK_XCLK:
+ tmpVal2 &= 0x1; //[1]=0
+ break;
+ case HBN_MCU_ROOT_CLK_PLL:
+ tmpVal2 |= 0x2; //[1]=1
+ break;
+ default:
+ break;
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+ HBN_CLK_SET_DUMMY_WAIT;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set HBN_RAM sleep mode
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_HRAM_slp(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET);
+ BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set HBN_RAM retension mode
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_HRAM_Ret(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+ BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power on XTAL 32K
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+ BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+ /* Delay >1s */
+ arch_delay_us(1100);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power off XTAL 32K
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+ BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power on RC32K
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);
+ BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+
+ /* Delay >800us */
+ arch_delay_us(880);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power off RC3K
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K);
+ BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Trim RC32K
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void)
+{
+ Efuse_Ana_RC32K_Trim_Type trim;
+ int32_t tmpVal = 0;
+
+ EF_Ctrl_Read_RC32K_Trim(&trim);
+ if (trim.trimRc32kExtCodeEn) {
+ if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) {
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN);
+ BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+ arch_delay_us(2);
+ return SUCCESS;
+ }
+ }
+
+ return ERROR;
+}
+
+/**
+ * @brief Power Off RC32K in all state
+ *
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_All_State(void)
+{
+ int32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K);
+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal);
+ HBN_Power_Off_RC32K();
+ return SUCCESS;
+}
+
+/**
+ * @brief Power Off RC32K In power off state
+ *
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_In_Poff(void)
+{
+ int32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K);
+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal);
+ HBN_Power_Off_RC32K();
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get HBN status flag
+ *
+ * @param None
+ *
+ * @return HBN status flag value
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Status_Flag(void)
+{
+ return BL_RD_REG(HBN_BASE, HBN_RSV0);
+}
+
+/****************************************************************************/ /**
+ * @brief Set HBN status flag
+ *
+ * @param flag: Status Flag
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag)
+{
+ BL_WR_REG(HBN_BASE, HBN_RSV0, flag);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get HBN wakeup address
+ *
+ * @param None
+ *
+ * @return HBN wakeup address
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Wakeup_Addr(void)
+{
+ return BL_RD_REG(HBN_BASE, HBN_RSV1);
+}
+
+/****************************************************************************/ /**
+ * @brief Set HBN wakeup address
+ *
+ * @param addr: HBN wakeup address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr)
+{
+ BL_WR_REG(HBN_BASE, HBN_RSV1, addr);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get core reboot flag
+ *
+ * @param None
+ *
+ * @return repower flag
+ *
+*******************************************************************************/
+uint8_t ATTR_TCM_SECTION HBN_Get_Core_Unhalt_Config(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {
+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT);
+ }
+
+ return 0x00;
+}
+
+/****************************************************************************/ /**
+ * @brief Set core reboot flag
+ *
+ * @param core: core ID
+ * @param hcfg: reboot cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Core_Reboot_Config(uint8_t core, uint8_t hcfg)
+{
+ uint32_t tmpVal = 0;
+ uint8_t unhalt = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);
+ unhalt = BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT);
+ if (hcfg) {
+ unhalt |= (1 << core);
+ } else {
+ unhalt &= ~(1 << core);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT, unhalt);
+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get MM power flag
+ *
+ * @param None
+ *
+ * @return repower flag
+ *
+*******************************************************************************/
+uint8_t ATTR_TCM_SECTION HBN_Get_MM_Power_Config(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {
+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_POWER_ON_MM);
+ }
+
+ return 0x00;
+}
+
+/****************************************************************************/ /**
+ * @brief Set MM power flag
+ *
+ * @param pcfg: power cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_MM_Power_Config(uint8_t pcfg)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);
+ if (pcfg) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_POWER_ON_MM);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_POWER_ON_MM);
+ }
+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get hand off config
+ *
+ * @param None
+ *
+ * @return hand off config
+ *
+*******************************************************************************/
+uint8_t HBN_Get_Hand_Off_Config(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {
+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_HAND_OFF_SEL);
+ }
+
+ return 0x00;
+}
+
+/****************************************************************************/ /**
+ * @brief Set hand off config
+ *
+ * @param dcfg: hand off config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Hand_Off_Config(uint8_t dcfg)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_HAND_OFF_SEL, dcfg);
+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get ldo18flash repower flag
+ *
+ * @param None
+ *
+ * @return repower flag
+ *
+*******************************************************************************/
+uint16_t ATTR_TCM_SECTION HBN_Get_Ldo18flash_Repower_Config(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ if (HBN_REPOWER_LDO18FLASH_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_REPOWER_LDO18FLASH)) {
+ return (uint16_t)tmpVal;
+ }
+
+ return 0x0000;
+}
+
+/****************************************************************************/ /**
+ * @brief Set ldo18flash repower flag
+ *
+ * @param delay: repower delay time
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo18flash_Repower_Delay(uint8_t delay)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REPOWER_LDO18FLASH, HBN_REPOWER_LDO18FLASH_FLAG);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REPOWER_LDO18FLASH_DLY, delay);
+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set Xtal type
+ *
+ * @param xtalType:Xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Xtal_Type(uint8_t xtalType)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+
+ tmpVal = tmpVal & 0xffff0000;
+ tmpVal |= HBN_XTAL_FLAG_VALUE;
+ tmpVal |= xtalType;
+
+ BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get Xtal type
+ *
+ * @param None
+ *
+ * @return Xtal type
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Type(uint8_t *xtalType)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+
+ if ((tmpVal & HBN_XTAL_FLAG_MASK) == HBN_XTAL_FLAG_VALUE) {
+ *xtalType = (tmpVal & 0xff);
+ return SUCCESS;
+ } else {
+ *xtalType = 0;
+ return ERROR;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Get Xtal value
+ *
+ * @param xtalVal:Xtal value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Value(uint32_t *xtalVal)
+{
+ uint32_t tmpVal = 0;
+ uint8_t xtalType = 0;
+
+ if (NULL == xtalVal) {
+ return ERROR;
+ }
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+ if ((tmpVal & HBN_XTAL_FLAG_MASK) == HBN_XTAL_FLAG_VALUE) {
+ xtalType = (tmpVal & 0xff);
+ switch(xtalType){
+ case GLB_XTAL_NONE:
+ *xtalVal = 0;
+ break;
+ case GLB_XTAL_24M:
+ *xtalVal = 24000000;
+ break;
+ case GLB_XTAL_32M:
+ *xtalVal = 32000000;
+ break;
+ case GLB_XTAL_38P4M:
+ *xtalVal = 38400000;
+ break;
+ case GLB_XTAL_40M:
+ *xtalVal = 40000000;
+ break;
+ case GLB_XTAL_26M:
+ *xtalVal = 26000000;
+ break;
+ case GLB_XTAL_RC32M:
+ *xtalVal = 32000000;
+ break;
+ default :
+ *xtalVal = 0;
+ break;
+ }
+ return SUCCESS;
+ }
+
+ *xtalVal = 0;
+ return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN clear RTC timer counter
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Clear_RTC_Counter(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ /* Clear RTC control bit0 */
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN clear RTC timer counter
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Enable_RTC_Counter(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ /* Set RTC control bit0 */
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN set RTC timer configuration
+ *
+ * @param delay: RTC interrupt delay 32 clocks
+ * @param compValLow: RTC interrupt commpare value low 32 bits
+ * @param compValHigh: RTC interrupt commpare value high 32 bits
+ * @param compMode: RTC interrupt commpare
+ * mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay));
+
+ BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow);
+ BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff);
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ /* Set interrupt delay option */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay);
+ /* Set RTC compare mode */
+ tmpVal |= (compMode << 1);
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN get RTC timer count value
+ *
+ * @param valLow: RTC count value pointer for low 32 bits
+ * @param valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+ uint32_t tmpVal;
+
+ /* Tigger RTC val read */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+ BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+ BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+
+ /* Read RTC val */
+ *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
+ *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_INT(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+ /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */
+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN enable GPIO interrupt
+ *
+ * @param gpioIntTrigType: HBN GPIO interrupt trigger type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN disable GPIO interrupt
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Disable(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN get interrupt status
+ *
+ * @param irqType: HBN interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type ATTR_TCM_SECTION HBN_Get_INT_State(HBN_INT_Type irqType)
+{
+ uint32_t tmpVal;
+
+ /* Check the parameters */
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT);
+
+ if (tmpVal & (1 << irqType)) {
+ return SET;
+ } else {
+ return RESET;
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief HBN get pin wakeup mode value
+ *
+ * @param None
+ *
+ * @return HBN pin wakeup mode value
+ *
+*******************************************************************************/
+uint8_t HBN_Get_Pin_Wakeup_Mode(void)
+{
+ return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE);
+}
+
+/****************************************************************************/ /**
+ * @brief HBN clear interrupt status
+ *
+ * @param irqType: HBN interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Clear_IRQ(HBN_INT_Type irqType)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(IS_HBN_INT_TYPE(irqType));
+
+ /* set clear bit */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+ tmpVal |= (1 << irqType);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+ /* unset clear bit */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+ tmpVal &= (~(1 << irqType));
+ BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN hardware pullup or pulldown configuration
+ *
+ * @param enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+ }
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN wakeup pin mask configuration
+ *
+ * @param maskVal: mask value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN aon pad ctrl configuration
+ *
+ * @param aonPadCtl1: ctrl value 1
+ * @param aonpadCtl2: ctrl value 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2)
+{
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, aonPadCtl1);
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, aonPadCtl2);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN aon pad cfg configuration
+ *
+ * @param aonPadHwCtrlEn: HW Keep GPIO at PDS or HBN Mode
+ * @param aonGpio: aon pad number
+ * @param aonPadCfg: aon pad configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg)
+{
+ uint32_t tmpVal0;
+ uint32_t tmpVal1;
+ uint32_t enAonCtrlGpio;
+ uint32_t aonPadIeSmt;
+ uint32_t aonPadPu;
+ uint32_t aonPadPd;
+ uint32_t aonPadOe;
+ uint8_t pu;
+ uint8_t pd;
+
+ CHECK_PARAM(IS_HBN_AON_PAD_TYPE(aonGpio));
+
+ if (NULL == aonPadCfg) {
+ return ERROR;
+ }
+
+ /* hbn_pad_ctrl_0 */
+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+ enAonCtrlGpio = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO);
+ if (aonPadCfg->ctrlEn) {
+ enAonCtrlGpio |= (1 << aonGpio);
+ } else {
+ enAonCtrlGpio &= ~(1 << aonGpio);
+ }
+ tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO, enAonCtrlGpio);
+ aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_PAD_IE_SMT);
+ if (aonPadCfg->inputEn) {
+ aonPadIeSmt |= (1 << aonGpio);
+ } else {
+ aonPadIeSmt &= ~(1 << aonGpio);
+ }
+ tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);
+
+ /* calc pu/pd */
+ switch (aonPadCfg->pullCfg) {
+ case HBN_GPIO_PAD_PULL_NONE:
+ pu = 0;
+ pd = 0;
+ break;
+ case HBN_GPIO_PAD_PULL_DOWN:
+ pu = 0;
+ pd = 1;
+ break;
+ case HBN_GPIO_PAD_PULL_UP:
+ pu = 1;
+ pd = 0;
+ break;
+ case HBN_GPIO_PAD_ACTIVE_IE:
+ pu = 1;
+ pd = 1;
+ break;
+ default:
+ pu = 0;
+ pd = 0;
+ break;
+ }
+
+ /* hbn_pad_ctrl_1 */
+ tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1);
+ aonPadPu = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PU);
+ if (pu) {
+ aonPadPu |= (1 << aonGpio);
+ } else {
+ aonPadPu &= ~(1 << aonGpio);
+ }
+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PU, aonPadPu);
+ aonPadPd = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PD);
+ if (pd) {
+ aonPadPd |= (1 << aonGpio);
+ } else {
+ aonPadPd &= ~(1 << aonGpio);
+ }
+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PD, aonPadPd);
+ aonPadOe = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_OE);
+ if (aonPadCfg->outputEn) {
+ aonPadOe |= (1 << aonGpio);
+ } else {
+ aonPadOe &= ~(1 << aonGpio);
+ }
+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_OE, aonPadOe);
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1);
+
+ /* hw ctrl enable/disable */
+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+ if (aonPadHwCtrlEn) {
+ tmpVal0 = BL_SET_REG_BIT(tmpVal0, HBN_REG_AON_GPIO_ISO_MODE);
+ } else {
+ tmpVal0 = BL_CLR_REG_BIT(tmpVal0, HBN_REG_AON_GPIO_ISO_MODE);
+ }
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN Set IO40&41 As Xtal_32K's IO
+ *
+ * @param xtal32kIoEn: Enable or disable IO40&41 As Xtal_32K's IO
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_IO4041_As_Xtal_32K_IO(uint8_t xtal32kIoEn)
+{
+ uint32_t tmpVal0;
+ uint32_t tmpVal1;
+
+ if (xtal32kIoEn) {
+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+ tmpVal0 |= ((uint32_t)0x3 << 27);
+ tmpVal0 &= ~((uint32_t)0x3 << 7);
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);
+
+ tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1);
+ tmpVal1 &= ~((uint32_t)0x3 << 7);
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1);
+ } else {
+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+ tmpVal0 &= ~((uint32_t)0x3 << 27);
+ tmpVal0 &= ~((uint32_t)0x3 << 7);
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);
+
+ tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1);
+ tmpVal1 |= ((uint32_t)0x3 << 7);
+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN enable ACOMP0 interrupt
+ *
+ * @param edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+ tmpVal2 = tmpVal2 | (1 << edge);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN disable ACOMP0 interrupt
+ *
+ * @param edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+ tmpVal2 = tmpVal2 & (~(1 << edge));
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN enable ACOMP1 interrupt
+ *
+ * @param edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+ tmpVal2 = tmpVal2 | (1 << edge);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN disable ACOMP1 interrupt
+ *
+ * @param edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+ tmpVal2 = tmpVal2 & (~(1 << edge));
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN enable BOD interrupt
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_BOD_IRQ(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN disable BOD interrupt
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_BOD_IRQ(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN out0 install interrupt callback
+ *
+ * @param intType: HBN out0 interrupt type
+ * @param cbFun: HBN out0 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun)
+{
+ /* Check the parameters */
+ CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType));
+
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler);
+#endif
+
+ hbnInt0CbfArra[intType] = cbFun;
+
+ return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief HBN out1 install interrupt callback
+ *
+ * @param intType: HBN out1 interrupt type
+ * @param cbFun: HBN out1 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun)
+{
+ /* Check the parameters */
+ CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType));
+
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler);
+#endif
+
+ hbnInt1CbfArra[intType] = cbFun;
+
+ return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief HBN aon pad debbug pull config
+ *
+ * @param puPdEn: Enable or disable aon pad pull down and pull up
+ * @param ieSmtEn: Enable or disable aon pad IE and SMT
+ * @param trigMode: trigger mode
+ * @param maskVal: int mask
+ * @param dlyEn: Enable or disable aon pad wakeup delay function
+ * @param dlySec: aon pad wakeup delay sec 1 to 7
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec)
+{
+ uint32_t tmpVal;
+
+ CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));
+ CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(trigMode));
+ CHECK_PARAM((maskVal <= 0x3FF));
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, puPdEn);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, trigMode);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Get RTC misc config
+ *
+ * @param cfg: configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg)
+{
+ uint32_t tmpVal = 0;
+ uint32_t *pCfg = (uint32_t *)cfg;
+
+ if (!cfg) {
+ return ERROR;
+ }
+
+ /* read [31:19] */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC);
+
+ /* use [30:19] */
+ *pCfg = tmpVal;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set RTC misc config
+ *
+ * @param cfg: configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg)
+{
+ uint32_t tmpVal = 0;
+
+ if (!cfg) {
+ return ERROR;
+ }
+
+ /* read [31:19] */
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC, ((*(uint32_t *)cfg)<<1));
+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Set Embedded Flash Pullup enabe or disable
+ *
+ * @param cfg: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg)
+{
+ uint32_t tmpVal = 0;
+
+ if (cfg->enableBodInt) {
+ HBN_Enable_BOD_IRQ();
+ } else {
+ HBN_Disable_BOD_IRQ();
+ }
+
+ tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, cfg->bodThreshold);
+ if (cfg->enablePorInBod) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOD_SEL);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOD_SEL);
+ }
+
+ if (cfg->enableBod) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOD);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOD);
+ }
+
+ BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief HBN OUT0 interrupt handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void)
+{
+ HBN_OUT0_INT_Type out0Int = HBN_OUT0_INT_GPIO9;
+
+ /* GPIO and RTC */
+ for (HBN_INT_Type gpioInt = HBN_INT_GPIO9; gpioInt <= HBN_INT_GPIO41; gpioInt++) {
+ if (SET == HBN_Get_INT_State(gpioInt)) {
+ HBN_Clear_IRQ(gpioInt);
+ switch (gpioInt) {
+ case HBN_INT_GPIO9:
+ out0Int = HBN_OUT0_INT_GPIO9;
+ break;
+ case HBN_INT_GPIO10:
+ out0Int = HBN_OUT0_INT_GPIO10;
+ break;
+ case HBN_INT_GPIO11:
+ out0Int = HBN_OUT0_INT_GPIO11;
+ break;
+ case HBN_INT_GPIO12:
+ out0Int = HBN_OUT0_INT_GPIO12;
+ break;
+ case HBN_INT_GPIO13:
+ out0Int = HBN_OUT0_INT_GPIO13;
+ break;
+ case HBN_INT_GPIO14:
+ out0Int = HBN_OUT0_INT_GPIO14;
+ break;
+ case HBN_INT_GPIO15:
+ out0Int = HBN_OUT0_INT_GPIO15;
+ break;
+ case HBN_INT_GPIO40:
+ out0Int = HBN_OUT0_INT_GPIO40;
+ break;
+ case HBN_INT_GPIO41:
+ out0Int = HBN_OUT0_INT_GPIO41;
+ break;
+ default:
+ break;
+ }
+ if (hbnInt0CbfArra[out0Int] != NULL) {
+ hbnInt0CbfArra[out0Int]();
+ }
+ }
+ }
+ if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {
+ HBN_Clear_IRQ(HBN_INT_RTC);
+ if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) {
+ hbnInt0CbfArra[HBN_OUT0_INT_RTC]();
+ }
+ }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief HBN OUT1 interrupt handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT1_IRQHandler(void)
+{
+ /* PIR */
+ if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
+ HBN_Clear_IRQ(HBN_INT_PIR);
+ if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) {
+ hbnInt1CbfArra[HBN_OUT1_INT_PIR]();
+ }
+ }
+ /* BOD */
+ if (SET == HBN_Get_INT_State(HBN_INT_BOD)) {
+ HBN_Clear_IRQ(HBN_INT_BOD);
+ if (hbnInt1CbfArra[HBN_OUT1_INT_BOD] != NULL) {
+ hbnInt1CbfArra[HBN_OUT1_INT_BOD]();
+ }
+ }
+ /* ACOMP0 */
+ if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
+ HBN_Clear_IRQ(HBN_INT_ACOMP0);
+ if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) {
+ hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0]();
+ }
+ }
+ /* ACOMP1 */
+ if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
+ HBN_Clear_IRQ(HBN_INT_ACOMP1);
+ if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) {
+ hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1]();
+ }
+ }
+}
+#endif
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_l1c.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_l1c.c
new file mode 100644
index 00000000..9f726047
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_l1c.c
@@ -0,0 +1,408 @@
+/**
+ ******************************************************************************
+ * @file bl808_l1c.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808_l1c.h"
+#include "bl808_common.h"
+#include "bl808_glb.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup L1C
+ * @{
+ */
+
+/** @defgroup L1C_Private_Macros
+ * @{
+ */
+
+/*@} end of group L1C_Private_Macros */
+
+/** @defgroup L1C_Private_Types
+ * @{
+ */
+
+/*@} end of group L1C_Private_Types */
+
+/** @defgroup L1C_Private_Variables
+ * @{
+ */
+
+/*@} end of group L1C_Private_Variables */
+
+/** @defgroup L1C_Global_Variables
+ * @{
+ */
+
+/*@} end of group L1C_Global_Variables */
+
+/** @defgroup L1C_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group L1C_Private_Fun_Declaration */
+
+/** @defgroup L1C_Private_Functions
+ * @{
+ */
+
+/*@} end of group L1C_Private_Functions */
+
+/** @defgroup L1C_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Enable I-Cache
+ *
+ * @param wayDsiable: cache way disable config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Enable(uint8_t wayDsiable)
+{
+#ifndef __riscv_32e
+ csi_icache_enable();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable D-Cache
+ *
+ * @param wayDsiable: cache way disable config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Enable(uint8_t wayDsiable)
+{
+#ifndef __riscv_32e
+ csi_dcache_enable();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Disable I-Cache
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Disable(void)
+{
+#ifndef __riscv_32e
+ csi_icache_disable();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Disable D-Cache
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Disable(void)
+{
+#ifndef __riscv_32e
+ csi_dcache_disable();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief L1C D-Cache write set
+ *
+ * @param wtEn: L1C write through enable
+ * @param wbEn: L1C write back enable
+ * @param waEn: L1C write allocate enable
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
+{
+ return;
+}
+
+/****************************************************************************/ /**
+ * @brief Clean all D_Cache
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_All(void)
+{
+#ifndef __riscv_32e
+ csi_dcache_clean();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Clean and invalid all D_Cache
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_All(void)
+{
+#ifndef __riscv_32e
+ csi_dcache_clean_invalid();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Invalid all I-Cache
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_All(void)
+{
+#ifndef __riscv_32e
+ csi_icache_invalid();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Invalid all D_Cache
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_All(void)
+{
+#ifndef __riscv_32e
+ csi_dcache_invalid();
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Clean D-Cache according to address
+ *
+ * @param addr: Address to clean
+ * @param len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len)
+{
+#ifndef __riscv_32e
+#ifdef CPU_D0
+ csi_dcache_clean_range((uintptr_t *)addr, len);
+#else
+ csi_dcache_clean_range((uint32_t *)(uintptr_t *)addr, len);
+#endif
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Clean and invalid D-Cache according to address
+ *
+ * @param addr: Address to clean
+ * @param len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len)
+{
+#ifndef __riscv_32e
+#ifdef CPU_D0
+ csi_dcache_clean_invalid_range((uintptr_t *)addr, len);
+#else
+ csi_dcache_clean_invalid_range((uint32_t *)(uintptr_t *)addr, len);
+#endif
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Invalid I-Cache according to address
+ *
+ * @param addr: Address to clean
+ * @param len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
+{
+ L1C_ICache_Invalid_All();
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Invalid D-Cache according to address
+ *
+ * @param addr: Address to clean
+ * @param len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
+{
+#ifndef __riscv_32e
+#ifdef CPU_D0
+ csi_dcache_invalid_range((uintptr_t *)addr, len);
+#else
+ csi_dcache_invalid_range((uint32_t *)(uintptr_t *)addr, len);
+#endif
+#endif
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief cache wrap
+ *
+ * @param en: wrap enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(uint8_t en)
+{
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief cache wrap
+ *
+ * @param core: cpu core
+ * @param cacheSetting: cache setting
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting)
+{
+ (void)core;
+ (void)cacheSetting;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Judge addr is in cache range
+ *
+ * @param addr: phyical addr
+ *
+ * @return 1 for addr is in cache range and 0 for not in cache range
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION L1C_Is_DCache_Range(uintptr_t addr)
+{
+ GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;
+
+ /* Get core type */
+ core = GLB_Get_Core_Type();
+ if(core==GLB_CORE_ID_D0){
+ if(((addr>>16)&0xffff)>=0x3ef8){
+ return 1;
+ }else{
+ return 0;
+ }
+ }else{
+ if(((addr>>16)&0xffff)>=0x4000){
+ return 1;
+ }else{
+ return 0;
+ }
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief Get None Cache address according to Cache address
+ *
+ * @param addr: cache addr
+ *
+ * @return none cache addr
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION L1C_Get_None_Cache_Addr(uintptr_t addr)
+{
+ GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;
+
+ /* Get core type */
+ core = GLB_Get_Core_Type();
+ if(core==GLB_CORE_ID_D0){
+ return addr;
+ }else{
+ return (addr&0x0FFFFFFF)|0x20000000;
+ }
+}
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_pds.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_pds.c
new file mode 100644
index 00000000..a2c24c81
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_pds.c
@@ -0,0 +1,1058 @@
+/**
+ ******************************************************************************
+ * @file bl808_pds.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808.h"
+#include "bl808_pds.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup PDS
+ * @{
+ */
+
+/** @defgroup PDS_Private_Macros
+ * @{
+ */
+
+/*@} end of group PDS_Private_Macros */
+
+/** @defgroup PDS_Private_Types
+ * @{
+ */
+
+/*@} end of group PDS_Private_Types */
+
+/** @defgroup PDS_Private_Variables
+ * @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX] = { NULL };
+#endif
+
+/*@} end of group PDS_Private_Variables */
+
+/** @defgroup PDS_Global_Variables
+ * @{
+ */
+
+/*@} end of group PDS_Global_Variables */
+
+/** @defgroup PDS_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group PDS_Private_Fun_Declaration */
+
+/** @defgroup PDS_Private_Functions
+ * @{
+ */
+
+/*@} end of group PDS_Private_Functions */
+
+/** @defgroup PDS_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief set gpio pad pull type in pds
+ *
+ * @param pad: gpio type
+ * @param pu: power up
+ * @param pd: power down
+ * @param ie: Active IE (interrupt)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_Type pad, uint8_t pu, uint8_t pd, uint8_t ie)
+{
+ uint32_t tmpVal;
+ uint32_t tmpValPu;
+ uint32_t tmpValPd;
+ uint32_t tmpValIe;
+ uint32_t pos;
+
+ CHECK_PARAM(IS_GLB_GPIO_TYPE(pad));
+
+ /* [0] : GPIO0~8 */
+ /* [1] : GPIO16~23 */
+ /* [2] : GPIO24~38 */
+ if (pad <= GLB_GPIO_PIN_8) {
+ pos = 0;
+ } else if ((pad >= GLB_GPIO_PIN_16) && (pad <= GLB_GPIO_PIN_23)) {
+ pos = 1;
+ } else if ((pad >= GLB_GPIO_PIN_24) && (pad <= GLB_GPIO_PIN_38)) {
+ pos = 2;
+ } else {
+ return ERROR;
+ }
+
+ /* pu/pd/ie config */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_I_SET);
+ tmpValPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET);
+ if (pu) {
+ tmpValPu |= (1 << pos);
+ } else {
+ tmpValPu &= ~(1 << pos);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET, tmpValPu);
+ tmpValPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET);
+ if (pd) {
+ tmpValPd |= (1 << pos);
+ } else {
+ tmpValPd &= ~(1 << pos);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET, tmpValPd);
+ tmpValIe = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET);
+ if (ie) {
+ tmpValIe |= (1 << pos);
+ } else {
+ tmpValIe &= ~(1 << pos);
+ }
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET, tmpValIe);
+ BL_WR_REG(PDS_BASE, PDS_GPIO_I_SET, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set gpio pad int mask type in pds
+ *
+ * @param pad: gpio type
+ * @param intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask)
+{
+ uint32_t tmpVal = 0;
+ uint32_t pos = 0;
+
+ /* [8:0] : GPIO0~8 */
+ /* [31:9] : GPIO16~38 */
+ if (pad <= GLB_GPIO_PIN_8) {
+ pos = pad;
+ } else if ((pad >= GLB_GPIO_PIN_16) && (pad <= GLB_GPIO_PIN_38)) {
+ pos = pad - 7;
+ } else {
+ return ERROR;
+ }
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_PD_SET);
+ if (UNMASK != intMask) {
+ /* MASK */
+ tmpVal |= (1 << pos);
+ } else {
+ /* UNMASK */
+ tmpVal &= ~(1 << pos);
+ }
+ BL_WR_REG(PDS_BASE, PDS_GPIO_PD_SET, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set gpio pad trig type in pds
+ *
+ * @param set: set type
+ * @param trig: trig type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_PDS_GPIO_INT_SET_TYPE(set));
+ CHECK_PARAM(IS_PDS_GPIO_INT_TRIG_TYPE(trig));
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+ switch (set) {
+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET1_INT_MODE, trig);
+ break;
+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET2_INT_MODE, trig);
+ break;
+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET3_INT_MODE, trig);
+ break;
+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET4_INT_MODE, trig);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set gpio pad int clear in pds
+ *
+ * @param set: set type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_PDS_GPIO_INT_SET_TYPE(set));
+
+ /* pds_gpio_setx_int_clr = 0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+ switch (set) {
+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+ /* pds_gpio_setx_int_clr = 1 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+ switch (set) {
+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+ /* pds_gpio_setx_int_clr = 0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+ switch (set) {
+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);
+ break;
+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);
+ break;
+ default:
+ break;
+ }
+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get gpio pad int status
+ *
+ * @param pad: gpio type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Sts_Type ATTR_TCM_SECTION PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad)
+{
+ uint32_t pos = 0;
+
+ /* [8:0] : GPIO0~8 */
+ /* [31:9] : GPIO16~38 */
+ if (pad <= GLB_GPIO_PIN_8) {
+ pos = pad;
+ } else if ((pad >= GLB_GPIO_PIN_16) && (pad <= GLB_GPIO_PIN_38)) {
+ pos = pad - 7;
+ } else {
+ return RESET;
+ }
+
+ return (BL_RD_REG(PDS_BASE, PDS_GPIO_STAT) & (1 << pos)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief set flash pad pull none
+ *
+ * @param pinCfg: flash pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg)
+{
+ switch (pinCfg) {
+ case SF_IO_EXT_SF2:
+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_34, 0, 0, 0);
+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_35, 0, 0, 0);
+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_36, 0, 0, 0);
+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_37, 0, 0, 0);
+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_38, 0, 0, 0);
+ break;
+ default:
+ break;
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set flash pad pull none
+ *
+ * @param pinCfg: flash pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg)
+{
+ uint32_t tmpVal;
+
+ switch (pinCfg) {
+ case SF_IO_EXT_SF2:
+ /* pu/pd/ie config */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_I_SET);
+ /* GPIO24~38 [8][5][2] = 0 */
+ tmpVal &= ~(0x124);
+ BL_WR_REG(PDS_BASE, PDS_GPIO_I_SET, tmpVal);
+ break;
+ default:
+ break;
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set MCU0 clock enable
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Clock_Enable(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set MCU0 clock disable
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Clock_Disable(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set MCU0 reset address
+ *
+ * @param addr: address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Reset_Address(uint32_t addr)
+{
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief enable LP clock
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_Clock_Enable(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG0);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PICO_CLK_EN);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief disable LP clock
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_Clock_Disable(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG0);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_PICO_CLK_EN);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG0, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set LP clock divider
+ *
+ * @param div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_System_CLK_Div(uint8_t div)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, 1);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, div);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set LP clock
+ *
+ * @param clkFreq: clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_LP_System_CLK(PDS_LP_SYS_CLK_Type clkFreq)
+{
+ CHECK_PARAM(IS_PDS_LP_SYS_CLK_TYPE(clkFreq));
+
+ /* do nothing */
+ (void)clkFreq;
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief reset LP rtc
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Reset_LP_RTC(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* lp rtc_rst=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_RST);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);
+
+ /* lp rtc_rst=1 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_E902_RTC_RST);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);
+
+ /* lp rtc_rst=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_RST);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set LP rtc clock
+ *
+ * @param enable: ENABLE or DISABLE
+ * @param div: clock div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_RTC_CLK(uint8_t enable, uint16_t div)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM((div <= 0x3FF));
+
+ /* lp rtc_en=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_EN);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);
+
+ /* lp rtc_div=div */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_E902_RTC_DIV, div);
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);
+
+ /* lp rtc_en=0/1 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);
+ if (enable) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_E902_RTC_EN);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_EN);
+ }
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief set LP reset address
+ *
+ * @param addr: address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_Reset_Address(uint32_t addr)
+{
+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get mm system power state
+ *
+ * @param None
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type ATTR_CLOCK_SECTION PDS_Get_MM_System_Power_On_State(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t pwrOff = 0;
+ uint32_t isoEn = 0;
+ uint32_t gateClk = 0;
+ uint32_t memStby = 0;
+ uint32_t pdsRst = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+ pwrOff = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_PWR_OFF);
+ isoEn = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_ISO_EN);
+ gateClk = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_GATE_CLK);
+ memStby = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_MEM_STBY);
+ pdsRst = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_PDS_RST);
+
+ if (pwrOff || isoEn || gateClk || memStby || pdsRst) {
+ /* mm system power off */
+ return RESET;
+ }
+
+ /* mm system power on */
+ return SET;
+}
+
+/****************************************************************************/ /**
+ * @brief power on mm system
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_MM_System(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* mm_pwr_off=0, [1]=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_PWR_OFF);
+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+ /* wait > 30us */
+ arch_delay_us(45);
+
+ /* mm_iso_en=0, [5]=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_ISO_EN);
+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+ /* mm_gate_clk=0, [17]=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_GATE_CLK);
+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+ /* mm_stby=0, [13]=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_MEM_STBY);
+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+ /* mm_reset=0, [9]=0 */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_PDS_RST);
+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Enable power down sleep
+ *
+ * @param cfg: power down sleep configuration 1
+ * @param cfg4: power down sleep configuration 2
+ * @param pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
+{
+ uint32_t tmpVal = 0;
+ /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
+ /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
+ if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
+ return ERROR;
+ } else if (pdsSleepCnt > PDS_WARMUP_LATENCY_CNT) {
+ BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
+ } else {
+ /* PDS sleep time 0 ,means mask pds_timer wakeup */
+ }
+
+ /* PDS_CTL4 config */
+ BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
+
+ /* PDS_CTL config */
+ if (cfg->pdsStart) {
+ /* clear pds int */
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+ BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
+ BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
+ } else {
+ BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief power down sleep force configure
+ *
+ * @param cfg2: power down sleep force configuration 1
+ * @param cfg3: power down sleep force configuration 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5)
+{
+ /* PDS_CTL2 config */
+ BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);
+
+ /* PDS_CTL3 config */
+ BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);
+
+ /* PDS_CTL5 config */
+ BL_WR_REG(PDS_BASE, PDS_CTL5, *(uint32_t *)cfg5);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief power down sleep ram configure
+ *
+ * @param ocramCfg: power down sleep force ocram configuration
+ * @param wramCfg: power down sleep force wram configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg)
+{
+ if ((NULL == ram1Cfg) || (NULL == ram2Cfg)) {
+ return ERROR;
+ }
+
+ BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ram1Cfg);
+ BL_WR_REG(PDS_BASE, PDS_RAM2, *(uint32_t *)ram2Cfg);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief power down sleep force configure
+ *
+ * @param defaultLvCfg: power down sleep default level configuration
+ * @param ramCfg: ram configuration
+ * @param pdsSleepCnt: power down sleep time count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,
+ PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg,
+ uint32_t pdsSleepCnt)
+{
+ /* RAM config need fix after ECO */
+ PDS_RAM_Config(ram1Cfg, ram2Cfg);
+ PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3), (PDS_CTL5_Type *)&(defaultLvCfg->pdsCtl5));
+ PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief power down sleep int mask
+ *
+ * @param intType: PDS int type
+ * @param intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+ if (intMask != UNMASK) {
+ tmpVal = tmpVal | (1 << (intType + PDS_INT_MASK_BIT_OFFSET));
+ } else {
+ tmpVal = tmpVal & ~(1 << (intType + PDS_INT_MASK_BIT_OFFSET));
+ }
+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief get power down sleep int status
+ *
+ * @param intType: PDS int type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
+{
+ return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << intType)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief clear power down sleep int status
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_IntClear(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Install PDS interrupt callback function
+ *
+ * @param intType: PDS int type
+ * @param cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
+#endif
+
+ pdsIntCbfArra[intType] = cbFun;
+
+ return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief Trim RC32M
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
+{
+ Efuse_Ana_RC32M_Trim_Type trim;
+ int32_t tmpVal = 0;
+
+ EF_Ctrl_Read_RC32M_Trim(&trim);
+ if (trim.trimRc32mExtCodeEn) {
+ if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
+ BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
+ arch_delay_us(2);
+ return SUCCESS;
+ }
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief PDS turn on USB
+ *
+ * @param waitReady : wait turn on usb finish
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady)
+{
+ uint32_t tmpVal = 0;
+
+ /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */
+ /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
+ /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */
+ /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */
+ /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */
+ /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */
+ /* #1.2ms; wait UCLK */
+ /* wait(soc616_b0.usb_uclk); */
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0);
+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW);
+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST);
+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+ /* greater than 5T */
+ arch_delay_us(1);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);
+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+ /* greater than 5T */
+ arch_delay_us(1);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);
+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+ /* wait UCLK 1.2ms */
+ arch_delay_ms(3);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);
+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+ if (waitReady) {
+ arch_delay_ms(2);
+ }
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief PDS turn off USB
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Turn_Off_USB(void)
+{
+ uint32_t tmpVal = 0;
+
+ /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */
+ /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
+ /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */
+ /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */
+ /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */
+ /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */
+ /* #1.2ms; wait UCLK */
+ /* wait(soc616_b0.usb_uclk); */
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0);
+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW);
+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST);
+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief USB phy suspend
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_USB_Suspend(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);
+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief USB phy resume
+ *
+ * @param None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_USB_Resume(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);
+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+ return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief Power down sleep wake up interrupt handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void)
+{
+ for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
+ if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType] != NULL)) {
+ pdsIntCbfArra[intType]();
+ }
+ }
+
+ PDS_IntClear();
+}
+#endif
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_psram_uhs.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_psram_uhs.c
new file mode 100644
index 00000000..1f06618a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_psram_uhs.c
@@ -0,0 +1,835 @@
+/**
+ ******************************************************************************
+ * @file bl808_psram_uhs.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808_psram_uhs.h"
+#include "bl808_uhs_phy.h"
+#include "bl808_common.h"
+#include "bl808_glb.h"
+#include "psram_uhs_reg.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup PSRAM_UHS
+ * @{
+ */
+
+/** @defgroup PSRAM_UHS_Private_Macros
+ * @{
+ */
+#define PSRAM_UHS_RW_TIMEOUT 0xffffffff
+/*@} end of group PSRAM_UHS_Private_Macros */
+
+/** @defgroup PSRAM_UHS_Private_Types
+ * @{
+ */
+
+/*@} end of group PSRAM_UHS_Private_Types */
+
+/** @defgroup PSRAM_UHS_Private_Variables
+ * @{
+ */
+
+/*@} end of group PSRAM_UHS_Private_Variables */
+
+/** @defgroup PSRAM_UHS_Global_Variables
+ * @{
+ */
+
+/*@} end of group PSRAM_UHS_Global_Variables */
+
+/** @defgroup PSRAM_UHS_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group PSRAM_UHS_Private_Fun_Declaration */
+
+/** @defgroup PSRAM_UHS_Private_Functions
+ * @{
+ */
+
+/*@} end of group PSRAM_UHS_Private_Functions */
+
+/** @defgroup PSRAM_UHS_Public_Functions
+ * @{
+ */
+int config_uhs_phy(uint32_t datarate)
+{
+ uint32_t tmpVal = 0;
+
+ if (datarate > 1866) {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F0A1323);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0b030404);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x050e0419);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x0a6a1c1c);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0711070e);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+
+ } else if (datarate > 1600) {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F283203);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0a020303);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040d0416);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x091e1818);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0710070d);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 3);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+
+ } else if (datarate > 1066) {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x09020303);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040c0313);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x07d11515);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x060f060c);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+ } else if (datarate > 800) {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x06010202);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0309020d);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x05360e0e);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x050c0509);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+
+ } else if (datarate > 666) {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F041020);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0208010a);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03e90b0b);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+ } else if (datarate > 400) {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F130010);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02080108);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03420909);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+ } else {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F020010);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x04000101);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02070106);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x01f50606);
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040a0407);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+ }
+ return 0;
+}
+
+static void power_up_ldo12uhs(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);
+
+#ifdef BL808D_REWORK
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN_SEL, 1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 0);
+#else
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 1);
+ BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);
+ arch_delay_us(300);
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_VOUT_SEL, 6);
+#endif
+ BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);
+ arch_delay_us(1);
+}
+
+static void set_cen_ck_ckn(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+ arch_delay_us(1);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
+ tmpVal &= 0xFFFCFFFF;
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
+ arch_delay_us(1);
+}
+
+static int set_or_uhs(uint32_t datarate)
+{
+ uint32_t tmpVal = 0;
+ uint32_t *uhs_phy_cfg_base_addr = (uint32_t *)(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_00_OFFSET);
+ // clang-format off
+ const static uint32_t uhs_phy_cfg_data[] ={
+ 0x802b0200, 0x60206020, 0x70027002, 0x70027002,
+ 0x70027002, 0x70027002, 0x70027002, 0x70027002,
+ 0x70027002, 0x70027002, 0x26000000, 0x26000006,
+ };
+ // clang-format on
+
+ for (uint32_t i = 0; i < 12; i++) {
+ uhs_phy_cfg_base_addr[i] = uhs_phy_cfg_data[i];
+ }
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30);
+ tmpVal &= 0x08ffffff;
+ tmpVal |= 0x07000000;
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30, tmpVal);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48);
+ tmpVal &= 0xfffffcff;
+ tmpVal |= 0x00000200;
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48, tmpVal);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C);
+ tmpVal &= 0xffe0ffff;
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C, tmpVal);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal &= 0xff88ff88;
+ tmpVal |= 0x00330033;
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+
+ arch_delay_us(1);
+
+ return 0;
+}
+static void switch_to_ldo12uhs(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
+ tmpVal &= 0xFFCFFFFF;
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
+ arch_delay_us(1);
+}
+
+static void release_cen_ck_ckn(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
+ tmpVal &= 0xFFFCFEFF;
+#ifdef BL808D_REWORK
+ tmpVal |= 0x10000;
+#else
+ tmpVal |= 0x30000;
+#endif
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
+ arch_delay_us(1);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 3);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+ arch_delay_us(1);
+}
+
+static void Psram_analog_init(uint32_t pck_freq)
+{
+ /* power on ldo12 */
+ power_up_ldo12uhs();
+
+ /* set cen ck ckn */
+ set_cen_ck_ckn();
+
+ /*
+ * overwrite default register content
+ * only support 2000M and 1500MHZ
+ */
+ set_or_uhs(pck_freq);
+
+ /* switch to ldo12 */
+ switch_to_ldo12uhs();
+
+ /* release cen ck */
+ release_cen_ck_ckn();
+
+ /* config phy paramater */
+ config_uhs_phy(pck_freq);
+}
+
+/****************************************************************************/ /**
+ * @brief Init Psram UHS ,set auto refresh cycle
+ *
+ * @param cfg: pck frequency unit is MHZ
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg)
+{
+ uint32_t tmpVal = 0;
+
+ CHECK_PARAM(IS_PSRAM_UHS_MEM_SIZE_TYPE(cfg->psramMemSize));
+ CHECK_PARAM(IS_PSRAM_UHS_PAGE_SIZE_TYPE(cfg->psramPageSize));
+
+ if (cfg->pck_freq > 2300) {
+ /* max support 2300MHZ */
+ while (1)
+ ;
+ } else if (cfg->pck_freq > 1600) {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1a03000f);
+ } else {
+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1202000b);
+ }
+
+ Psram_analog_init(cfg->pck_freq);
+
+ /* Wait 150 us */
+ arch_delay_us(150);
+
+ /* set refresh paramater */
+ /* 1. auto refresh clock source is pck_t, Adjust pck_t_div so that the frequency is around ~50Mhz */
+ /* tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);
+ tmpVal &= 0x00ffffff;
+
+ if (cfg->pck_freq >= 2200) {
+ tmpVal |= 0x05000000;
+ } else if (cfg->pck_freq >= 2000) {
+ tmpVal |= 0x04000000;
+ } else if (cfg->pck_freq >= 1500) {
+ tmpVal |= 0x03000000;
+ } else if (cfg->pck_freq >= 1400) {
+ tmpVal |= 0x02000000;
+ } else if (cfg->pck_freq >= 666) {
+ tmpVal |= 0x01000000;
+ }
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal); */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);
+ tmpVal &= 0x00ffffff;
+
+ if (cfg->pck_freq >= 2200) {
+ tmpVal |= 0x05000000;
+ } else if (cfg->pck_freq >= 1800) {
+ tmpVal |= 0x04000000;
+ } else if (cfg->pck_freq >= 1500) {
+ tmpVal |= 0x03000000;
+ } else if (cfg->pck_freq >= 1400) {
+ tmpVal |= 0x02000000;
+ } else if (cfg->pck_freq >= 666) {
+ tmpVal |= 0x01000000;
+ }
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal);
+
+ /* 2. setting refresh windows cycle count
+ * reg_win_cycle = refresh_window / Tpck_y
+ *
+ * refresh_window unit is ms
+ * when refresh tempotory > 85
+ * refresh_window = 16
+ * elsee
+ * refresh_window = 32
+ */
+ if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) {
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0x16e360);
+ } else {
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0xB71B0);
+ }
+ /* 3 & 4. setting refresh count in a windows fixed value 4096 in v0.2
+ * calculate Average cycle between two auto-refresh
+ * reg_refi_cycle = reg_win_cycle / reg_win_ref_cnt
+ * */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_WIN_REF_CNT, 0x1000);
+ if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (370));
+ } else {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (190));
+ }
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2, tmpVal);
+
+ /* 5 setting single auto refresh time */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, (uint32_t)(90 / T_pck_t));
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, 5);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4, tmpVal);
+
+ /* 6 auto-refesh enable */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_AF_EN);
+
+ /* 7&8 . set psram memory size and page size */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_ADDRMB_MSK, cfg->psramMemSize);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_LINEAR_BND_B, cfg->psramPageSize);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ /* 9. psram enable initial */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_INIT_EN);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief Read register for uhs
+ *
+ * @param reg_addr: read addr
+ * @param regVal: regVal
+ *
+ * @return success or not
+ *
+*******************************************************************************/
+int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal)
+{
+ uint32_t tmpVal = 0;
+ uint32_t cnt = 0;
+
+ /* 1 generate requeset and wait authorization*/
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ return -1;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));
+
+ /* 2 set mode reg */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, reg_addr);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ /* 3 enable controller Rx*/
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGR_PULSE);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
+
+ cnt = 0;
+
+ /* 4 wait read done */
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ return -1;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGR_DONE));
+
+ /* 5 steup up read data */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+
+ *regVal = (uint8_t)(BL_GET_REG_BITS_VAL(tmpVal, PSRAM_UHS_STS_CONFIG_READ));
+
+ /* 6 cancel requeset singnal */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief write register for winbond PSRAM
+ *
+ * @param regCfg: wirte reg data
+ *
+ * @return None
+ *
+*******************************************************************************/
+int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg)
+{
+ uint32_t tmpVal = 0;
+ uint32_t cnt = 0;
+ uint8_t regWriteList[] = { 0, 2 };
+ uint8_t i = 0;
+
+ CHECK_PARAM(IS_PSRAM_UHS_DRIVER_ST_TYPE(regCfg->driver_st));
+ CHECK_PARAM(IS_PSRAM_UHS_WARP_BURST_TYPE(regCfg->burst_size));
+ CHECK_PARAM(IS_PSRAM_UHS_LATENCY_TYPE(regCfg->lentency));
+
+ /* 1 congfi write reg*/
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE);
+
+ switch (regCfg->burst_size) {
+ case PSRAM_UHS_WARP_BURST_64:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
+ break;
+ case PSRAM_UHS_WARP_BURST_32:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
+ break;
+ case PSRAM_UHS_WARP_BURST_16:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
+ break;
+ case PSRAM_UHS_WARP_BURST_NONE:
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
+ break;
+ default:
+ return -1;
+ }
+ if (regCfg->driver_st != PSRAM_UHS_DRIVER_ST_NO_CHANGE) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DRIVE_ST, regCfg->driver_st);
+ }
+ if (regCfg->lentency != PSRAM_UHS_LATENCY_NO_CHANGE) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_LATENCY, regCfg->lentency);
+ }
+
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE, tmpVal);
+
+ /* 2 generate requeset and wait authorization */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ return -1;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));
+
+ for (i = 0; i < sizeof(regWriteList) / sizeof(uint8_t); i++) {
+ /* 3 set mode reg */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, regWriteList[i]);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ /* 4 enable controller */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
+
+ cnt = 0;
+
+ /* 5 wait write done */
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ return -1;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
+ }
+
+ /* 6 cancel requeset singnal */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief Timing Reset
+ *
+ * @param reg_addr: reg_addr
+ * @param regCfg: wirte reg data
+ *
+ * @return None
+ *
+*******************************************************************************/
+int PSram_UHS_Timing_Reset(void)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1);
+
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0);
+
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+
+ arch_delay_us(1000);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 0);
+
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 4);
+
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
+
+ return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief construct cmd wave for psram
+ *
+ * @param reg_addr: reg_addr
+ * @param regCfg: wirte reg data
+ *
+ * @return None
+ *
+*******************************************************************************/
+int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd)
+{
+ uint32_t tmpVal = 0;
+ uint32_t cnt = 0;
+
+ CHECK_PARAM(IS_PSRAM_UHS_CMD_TYPE(cmd));
+
+ /* generate requeset and wait authorization*/
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ goto exit;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));
+
+ /* enable cmd generate */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+
+ switch (cmd) {
+ case PSRAM_UHS_CMD_SELF_REFRESH_IN:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFI_PULSE);
+ break;
+ case PSRAM_UHS_CMD_SELF_REFRESH_EXIT:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFO_PULSE);
+ break;
+ case PSRAM_UHS_CMD_GLOBAL_RESET:
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_GLBR_PULSE);
+ /* Wait 15 us for reset */
+ arch_delay_us(15);
+ break;
+ case PSRAM_UHS_CMD_ZQ_CAL_LONG:
+
+ /* 3 set mode reg */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 5);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ /* 4 enable controller */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
+
+ cnt = 0;
+
+ /* 5 wait write done */
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ goto exit;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
+
+ break;
+ case PSRAM_UHS_CMD_ZQ_CAL_SHORT:
+
+ /* 3 set mode reg */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 6);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ /* 4 enable controller */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
+
+ cnt = 0;
+
+ /* 5 wait write done */
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ goto exit;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
+ break;
+ case PSRAM_UHS_CMD_ZQ_CAL_RESET:
+
+ /* 3 set mode reg */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 7);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ /* 4 enable controller */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
+
+ cnt = 0;
+
+ /* 5 wait write done */
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ goto exit;
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
+ break;
+ default:
+ goto exit;
+ break;
+ }
+
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
+
+ cnt = 0;
+
+ /* wait write done */
+ switch (cmd) {
+ case PSRAM_UHS_CMD_SELF_REFRESH_IN:
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ goto exit;
+
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFI_DONE));
+ break;
+ case PSRAM_UHS_CMD_SELF_REFRESH_EXIT:
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ goto exit;
+
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFO_DONE));
+ break;
+ case PSRAM_UHS_CMD_GLOBAL_RESET:
+ do {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
+ cnt++;
+ if (cnt > PSRAM_UHS_RW_TIMEOUT)
+ goto exit;
+
+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_GLBR_DONE));
+ break;
+ default:
+ goto exit;
+ }
+
+ /* 6 cancel requeset singnal */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ return 0;
+
+exit:
+ /* 6 cancel requeset singnal */
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
+
+ return -1;
+}
+
+/**
+ * @brief defualt init for 64MB x16 UHS PSRAM
+ * user should enable UHS PSRAM PLL before call this function
+ * @param uhs_pll_clk The uhs pll frequency used
+ */
+void Psram_UHS_x16_Init(uint32_t uhs_pll_clk)
+{
+ PSRAM_UHS_Cfg_Type psramDefaultCfg = {
+ 2000,
+ PSRAM_MEM_SIZE_64MB,
+ PSRAM_PAGE_SIZE_2KB,
+ PSRAM_UHS_NORMAL_TEMP,
+ };
+
+ PSRAM_UHS_Write_Reg_Cfg_Type writeReg = {
+ PSRAM_UHS_DRIVER_ST_40_PDPU,
+ PSRAM_UHS_WARP_BURST_NONE,
+ PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ,
+ };
+
+ psramDefaultCfg.pck_freq = uhs_pll_clk;
+
+ if ((uhs_pll_clk >= 2000) && (uhs_pll_clk <= 2300)) {
+ writeReg.lentency = PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ;
+ } else if ((uhs_pll_clk <= 1600) && (uhs_pll_clk > 1066)) {
+ writeReg.lentency = PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ;
+ } else if ((uhs_pll_clk < 1067) && (uhs_pll_clk > 800)) {
+ writeReg.lentency = PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ;
+ } else if ((uhs_pll_clk <= 800) && (uhs_pll_clk > 667)) {
+ writeReg.lentency = PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ;
+ } else if ((uhs_pll_clk < 667) && (uhs_pll_clk > 400)) {
+ writeReg.lentency = PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ;
+ } else if (uhs_pll_clk <= 400) {
+ writeReg.lentency = PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ;
+ }
+
+ /* first initial psram controller*/
+ Psram_UHS_Init(&psramDefaultCfg);
+
+ /* reset psram device*/
+ PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_GLOBAL_RESET);
+
+ arch_delay_us(100);
+
+ /* write 1GHZ configuration to psram device */
+ PSram_UHS_Write_Reg(&writeReg);
+}
+
+void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg)
+{
+ /* first initial psram controller*/
+ Psram_UHS_Init(cfg);
+
+ uhs_phy_init(cfg);
+}
+/*@} end of group PSRAM_UHS_Public_Functions */
+
+/*@} end of group PSRAM_UHS */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_sdh.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_sdh.c
new file mode 100644
index 00000000..b877bab3
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_sdh.c
@@ -0,0 +1,1361 @@
+/**
+ ******************************************************************************
+ * @file bl808_sdh.c
+ * @version V1.2
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2018 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl808.h"
+#include "string.h"
+#include "bl808_sdh.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup SDH
+ * @{
+ */
+
+/** @defgroup SDH_Private_Macros
+ * @{
+ */
+
+/*@} end of group SDH_Private_Macros */
+
+/** @defgroup SDH_Private_Types
+ * @{
+ */
+
+/*@} end of group SDH_Private_Types */
+
+/** @defgroup SDH_Private_Variables
+ * @{
+ */
+static uint32_t bootDummy = 0;
+static SDH_Handle_Cfg_Type *sdhHandle = NULL;
+
+/*@} end of group SDH_Private_Variables */
+
+/** @defgroup SDH_Global_Variables
+ * @{
+ */
+
+/*@} end of group SDH_Global_Variables */
+
+/** @defgroup SDH_Private_Fun_Declaration
+ * @{
+ */
+static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle);
+
+/*@} end of group SDH_Private_Fun_Declaration */
+
+/** @defgroup SDH_Private_Functions
+ * @{
+ */
+
+/*@} end of group SDH_Private_Functions */
+
+/** @defgroup SDH_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief Enable SDH DMA
+ *
+ * @param dmaMode: DMA mode select
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_EnableDMA(SDH_DMA_Mode_Type dmaMode)
+{
+ uint16_t tmpVal;
+
+ /* Check the parameters */
+ CHECK_PARAM(IS_SDH_DMA_MODE_TYPE(dmaMode));
+
+ /* Select DMA type */
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DMA_SEL, dmaMode);
+ BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_DMA_EN);
+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief Disable SDH DMA
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_DisableDMA(void)
+{
+ uint16_t tmpVal;
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_DMA_EN);
+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+}
+/****************************************************************************/ /**
+ * @brief SDH enable interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_ITConfig(uint32_t SDH_IT_FLAG, BL_Fun_Type NewState)
+{
+ if (NewState != DISABLE) {
+ /* Enable the SDH interrupts */
+ SDH_EnableIntSource(SDH_IT_FLAG);
+ } else {
+ /* Disable the SDH interrupts */
+ SDH_DisableIntSource(SDH_IT_FLAG);
+ }
+}
+/****************************************************************************/ /**
+ * @brief SDH enable interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_EnableStatus(void)
+{
+ uint32_t tmpVal;
+
+ /* Disable all interrupts */
+ SDH_DisableIntStatus(SDH_INT_ALL);
+
+ tmpVal = (SDH_INT_CMD_TIMEOUT | SDH_INT_CMD_CRC_ERROR | SDH_INT_CMD_ENDBIT_ERROR |
+ SDH_INT_CMD_INDEX_ERROR | SDH_INT_CMD_COMPLETED |
+ SDH_INT_CARD_INSERT | SDH_INT_CARD_REMOVE |
+ SDH_INT_DATA_COMPLETED | SDH_INT_DMA_COMPLETED |
+ SDH_INT_BUFFER_WRITE_READY | SDH_INT_BUFFER_READ_READY |
+ SDH_INT_DATA_TIMEOUT | SDH_INT_DATA_CRC_ERROR | SDH_INT_DATA_ENDBIT_ERROR |
+ SDH_INT_AUTO_CMD12_ERROR | SDH_INT_DMA_ERROR | SDH_INT_BLK_GAP_EVENT |
+ SDH_INT_RETUNE_EVENT | SDH_INT_TUNE_ERROR);
+
+ SDH_EnableIntStatus(tmpVal);
+}
+/****************************************************************************/ /**
+ * @brief SDH enable interrupt
+ *
+ * @param dataCfg: Transfer data config pointer
+ *
+ * @return SDH status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_ConfigDataTranfer(SDH_Data_Cfg_Type *dataCfg)
+{
+ uint16_t tmpVal;
+
+ if (dataCfg != NULL) {
+ /* For transfer boot continous, only need to set the CREQ bit */
+ if (dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) {
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_BLOCK_GAP_CTRL);
+ /* Clear stop at block gap request */
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_STOP_AT_BLOCK_GAP_REQ);
+ /* Continous transfer data */
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_CONT_REQ);
+ BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_GAP_CTRL, tmpVal);
+
+ return SDH_STAT_SUCCESS;
+ }
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+
+ /* Check data inhibit flag */
+ if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_DAT)) {
+ return SDH_STAT_BUSY;
+ }
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+
+ /* Check transfer block count */
+ if ((dataCfg->blockCount > SDH_MAX_BLOCK_COUNT) || ((dataCfg->txData == NULL) && (dataCfg->rxData == NULL))) {
+ return SDH_STAT_INVLAID_PARA;
+ }
+
+ if (dataCfg->rxData) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_TO_HOST_DIR);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_TO_HOST_DIR);
+ }
+
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x00);
+
+ /* auto command 23, auto send set block count cmd before multiple read/write */
+ if (dataCfg->enableAutoCommand23) {
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x02);
+ BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, dataCfg->blockCount);
+ } else if (dataCfg->enableAutoCommand12) {
+ /* auto command 12 */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x01);
+ }
+
+ if (dataCfg->blockCount > 1U) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_MULTI_BLK_SEL);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_MULTI_BLK_SEL);
+ }
+
+ /* Enable block count */
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_BLK_CNT_EN);
+
+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+
+ /* if transfer boot data, leave the block count to SDH_SetMmcBootConfig function */
+ if (dataCfg->dataType != SDH_TRANS_DATA_BOOT) {
+ /* config data block size/block count */
+ BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_SIZE, dataCfg->blockSize);
+ BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_COUNT, dataCfg->blockCount);
+ }
+ } else {
+ /* clear data flags */
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x00);
+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+
+ /* Check data inhibit flag */
+ if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_CMD)) {
+ return SDH_STAT_BUSY;
+ }
+ }
+
+ return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH enable interrupt
+ *
+ * @param cmd: Transfer data config pointer
+ *
+ * @return SDH status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_GetCmdResp(SDH_CMD_Cfg_Type *cmd)
+{
+ if (cmd->respType != SDH_RESP_NONE) {
+ cmd->response[0U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_0);
+ cmd->response[1U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_2);
+ cmd->response[2U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_4);
+ cmd->response[3U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_6);
+ }
+
+ return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH read data port
+ *
+ * @param dataCfg: Transfer data config pointer
+ *
+ * @return Read length
+ *
+*******************************************************************************/
+uint32_t SDH_ReadDataPort(SDH_Data_Cfg_Type *dataCfg)
+{
+ uint32_t tmpVal;
+ uint32_t totalLen, recvLen = 0;
+
+ totalLen = (dataCfg->blockCount * dataCfg->blockSize);
+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_TRANSFER_MODE);
+
+ if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) {
+ do {
+ dataCfg->rxData[dataCfg->rxDataLen++] = BL_RD_REG(SDH_BASE, SDH_SD_BUFFER_DATA_PORT_0);
+ recvLen += 4;
+ } while (recvLen < totalLen);
+ }
+
+ return recvLen;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH read data port
+ *
+ * @param dataCfg: Transfer data config pointer
+ *
+ * @return Read length
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_ReadDataPortBlock(SDH_Data_Cfg_Type *dataCfg)
+{
+ uint32_t intStatus = 0U;
+ SDH_Stat_Type error = SDH_STAT_SUCCESS;
+
+ /* Make sure the buffer size is 4 byte aligned */
+ if (dataCfg->blockSize % sizeof(uint32_t) != 0U) {
+ dataCfg->blockSize += sizeof(uint32_t) - (dataCfg->blockSize % sizeof(uint32_t));
+ }
+
+ while (!(intStatus & (SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_ERRORS | SDH_INT_TUNE_ERROR))) {
+ intStatus = SDH_GetIntStatus();
+ }
+
+ /* during std tuning process, software do not need to read data, but wait BRR is enough */
+ if ((dataCfg->dataType == SDH_TRANS_DATA_TUNING) && (intStatus & SDH_INT_BUFFER_READ_READY)) {
+ SDH_ClearIntStatus(SDH_INT_BUFFER_READ_READY);
+ return SDH_STAT_SUCCESS;
+ } else if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+ SDH_ClearIntStatus(SDH_INT_TUNE_ERROR);
+ /* if tuning error occur ,return directly */
+ error = SDH_STAT_TUNE_ERROR;
+ } else if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {
+ if (!(dataCfg->enableIgnoreError)) {
+ error = SDH_STAT_RECV_DATA_FAIL;
+ }
+
+ /* clear data error flag */
+ SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);
+ }
+
+ if (error == SDH_STAT_SUCCESS) {
+ SDH_ReadDataPort(dataCfg);
+ /* clear buffer read ready */
+ SDH_ClearIntStatus(SDH_INT_BUFFER_READ_READY);
+ intStatus = 0U;
+ }
+
+ /* Clear data complete flag after the last read operation. */
+ SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED);
+
+ return error;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH write data port
+ *
+ * @param dataCfg: Transfer data config pointer
+ *
+ * @return write length
+ *
+*******************************************************************************/
+uint32_t SDH_WriteDataPort(SDH_Data_Cfg_Type *dataCfg)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_TRANSFER_MODE);
+
+ if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) {
+ BL_WR_REG(SDH_BASE, SDH_SD_BUFFER_DATA_PORT_0, dataCfg->txData[dataCfg->txDataLen++]);
+ }
+
+ return 4;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH write data port
+ *
+ * @param dataCfg: Transfer data config pointer
+ *
+ * @return Write length
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_WriteDataPortBlock(SDH_Data_Cfg_Type *dataCfg)
+{
+ uint32_t totalLen;
+ uint32_t txLen = 0U, intStatus = 0U;
+ SDH_Stat_Type error = SDH_STAT_SUCCESS;
+
+ /* Make sure the buffer size is 4 byte aligned */
+ if (dataCfg->blockSize % sizeof(uint32_t) != 0U) {
+ dataCfg->blockSize += sizeof(uint32_t) - (dataCfg->blockSize % sizeof(uint32_t));
+ }
+
+ totalLen = (dataCfg->blockCount * dataCfg->blockSize);
+
+ while ((error == SDH_STAT_SUCCESS) && (txLen < totalLen)) {
+ while (!(intStatus & (SDH_INT_BUFFER_WRITE_READY | SDH_INT_DATA_ERRORS | SDH_INT_TUNE_ERROR))) {
+ intStatus = SDH_GetIntStatus();
+ }
+
+ if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+ SDH_ClearIntStatus(SDH_INT_TUNE_ERROR);
+ /* if tuning error occur ,return directly */
+ error = SDH_STAT_TUNE_ERROR;
+ } else if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {
+ if (!(dataCfg->enableIgnoreError)) {
+ error = SDH_STAT_RECV_DATA_FAIL;
+ }
+
+ /* clear data error flag */
+ SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);
+ }
+
+ if (error == SDH_STAT_SUCCESS) {
+ txLen += SDH_WriteDataPort(dataCfg);
+ /* clear buffer read ready */
+ SDH_ClearIntStatus(SDH_INT_BUFFER_WRITE_READY);
+ intStatus = 0U;
+ }
+ }
+
+ while (!(intStatus & (SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS))) {
+ intStatus = SDH_GetIntStatus();
+ }
+
+ if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {
+ if (!(dataCfg->enableIgnoreError)) {
+ error = SDH_STAT_RECV_DATA_FAIL;
+ }
+
+ /* clear data error flag */
+ SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);
+ }
+
+ SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED);
+
+ return error;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH send command
+ *
+ * @param cmd: command config pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_SendCommand(SDH_CMD_Cfg_Type *cmd)
+{
+ uint32_t tmpVal;
+ uint32_t flag = cmd->flag;
+ //uint32_t flag = 0;
+
+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+
+ if (((tmpVal & SDH_PRESENT_FLAG_CMD_INHBIT) == 0U) && (cmd->type != SDH_CMD_EMPTY)) {
+ /* Define the flag corresponding to each response type. */
+ switch (cmd->respType) {
+ case SDH_RESP_NONE:
+ break;
+
+ case SDH_RESP_R1: /* Response 1 */
+ case SDH_RESP_R5: /* Response 5 */
+ case SDH_RESP_R6: /* Response 6 */
+ case SDH_RESP_R7: /* Response 7 */
+ flag |= (SDH_TRANS_FLAG_RESP_48BITS | SDH_TRANS_FLAG_EN_CRC_CHECK | SDH_TRANS_FLAG_EN_INDEX_CHECK);
+ break;
+
+ case SDH_RESP_R1B: /* Response 1 with busy */
+ case SDH_RESP_R5B: /* Response 5 with busy */
+ flag |= (SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY | SDH_TRANS_FLAG_EN_CRC_CHECK | SDH_TRANS_FLAG_EN_INDEX_CHECK);
+ break;
+
+ case SDH_RESP_R2: /* Response 2 */
+ flag |= (SDH_TRANS_FLAG_RESP_136BITS | SDH_TRANS_FLAG_EN_CRC_CHECK);
+ break;
+
+ case SDH_RESP_R3: /* Response 3 */
+ case SDH_RESP_R4: /* Response 4 */
+ flag |= (SDH_TRANS_FLAG_RESP_48BITS);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Config command index */
+ tmpVal = flag >> 16;
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CMD_TYPE, cmd->type);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CMD_INDEX, cmd->index);
+
+ /* Config command argument */
+ BL_WR_REG(SDH_BASE, SDH_SD_ARG_LOW, cmd->argument);
+
+ /* Config command index */
+ BL_WR_REG16(SDH_BASE, SDH_SD_CMD, tmpVal);
+ }
+
+ /* FIXME:how to enable again */
+ if (cmd->type == SDH_CMD_EMPTY) {
+ SDH_DisableIntSource(SDH_INT_CMD_COMPLETED);
+ }
+}
+/****************************************************************************/ /**
+ * @brief SDH wait command send done
+ *
+ * @param cmd: Command config pointer
+ *
+ * @return Command deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_WaitCommandDone(SDH_CMD_Cfg_Type *cmd)
+{
+ uint32_t intStatus = 0U;
+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+
+ /* Wait command complete or encounters error. */
+ while (!(intStatus & (SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS | SDH_INT_TUNE_ERROR))) {
+ intStatus = SDH_GetIntStatus();
+ }
+
+ if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+ stat = SDH_STAT_TUNE_ERROR;
+ } else if ((intStatus & SDH_INT_CMD_ERRORS) != 0U) {
+ stat = SDH_STAT_SEND_CMD_FAIL;
+ }
+
+ /* Receive response when command completes successfully. */
+ if (stat == SDH_STAT_SUCCESS) {
+ stat = SDH_GetCmdResp(cmd);
+ }
+
+ SDH_ClearIntStatus(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS | SDH_INT_TUNE_ERROR);
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH transfer data
+ *
+ * @param dataCfg: Data config pointer
+ * @param enDMA: Whether enable DMA
+ *
+ * @return command deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_TransferDataBlocking(SDH_Data_Cfg_Type *dataCfg, uint8_t enDMA)
+{
+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+ uint32_t intStatus = 0U;
+
+ if (enDMA) {
+ /* Wait dataCfg complete or encounters error. */
+ while (!(intStatus & (SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS |
+ SDH_INT_DMA_ERROR | SDH_INT_TUNE_ERROR))) {
+ intStatus = SDH_GetIntStatus();
+ }
+
+ if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+ stat = SDH_STAT_TUNE_ERROR;
+ } else if ((intStatus & (SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR)) != 0U) {
+ if ((!(dataCfg->enableIgnoreError)) || (intStatus & SDH_INT_DATA_TIMEOUT)) {
+ stat = SDH_STAT_SEND_DATA_FAIL;
+ }
+ }
+
+ /* load dummy data */
+ if ((dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) && (stat == SDH_STAT_SUCCESS)) {
+ *(dataCfg->rxData) = bootDummy;
+ }
+
+ SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS |
+ SDH_INT_DMA_ERROR | SDH_INT_TUNE_ERROR);
+ } else {
+ if (dataCfg->rxData) {
+ stat = SDH_ReadDataPortBlock(dataCfg);
+ } else {
+ stat = SDH_WriteDataPortBlock(dataCfg);
+ }
+ }
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH set clock
+ *
+ * @param srcClock: Source clock frequency in Hz
+ * @param busClock: SDH clock frequency in Hz
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock)
+{
+ uint16_t tmpVal;
+ uint16_t div = srcClock / busClock / 2;
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL);
+
+ /* Disable internal clock*/
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_INT_CLK_EN);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_SD_CLK_EN);
+
+ /* Set divdier */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_FREQ_SEL_LO, div & 0xff);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_FREQ_SEL_HI, (div >> 8) & 0x3);
+ /* 0x1 = Programmable Clock Mode,0x0 = Divided Clock mode */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CLK_GEN_SEL, 0);
+
+ /* Enable internal clock*/
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_INT_CLK_EN);
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SD_CLK_EN);
+
+ BL_WR_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL, tmpVal);
+
+ /* Wait for clock stable */
+ do {
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL);
+ } while (!BL_IS_REG_BIT_SET(tmpVal, SDH_INT_CLK_STABLE));
+}
+
+/****************************************************************************/ /**
+ * @brief SDH disable clock
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_DisableSdClock(void)
+{
+ uint32_t tmpVal;
+
+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_CLOCK_CTRL);
+
+ /* Disable internal clock*/
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_INT_CLK_EN);
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_SD_CLK_EN);
+
+ BL_WR_REG(SDH_BASE, SDH_SD_CLOCK_CTRL, tmpVal);
+}
+/****************************************************************************
+ * @brief SDH init function
+ *
+ * @param cfg: SDH config pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Powon(void)
+{
+ uint32_t tmpVal;
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SD_BUS_POWER);
+ BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);
+}
+/****************************************************************************
+ * @brief SDH init function
+ *
+ * @param cfg: SDH config pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Ctrl_Init(const SDH_Cfg_Type *cfg)
+{
+ uint32_t tmpVal;
+
+ SDH_SetSdClock(cfg->srcClock, cfg->busClock);
+ SDH_DisableDMA();
+
+ /* Set SDH config */
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);
+
+ if (cfg->dataWidth == SDH_DATA_BUS_WIDTH_8BITS) {
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_EX_DATA_WIDTH);
+ } else {
+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_EX_DATA_WIDTH);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DATA_WIDTH, cfg->dataWidth);
+ }
+
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_HI_SPEED_EN, cfg->highSpeed);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_BUS_VLT, cfg->volt);
+
+ BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);
+
+ if (cfg->vlot18Enable) {
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_HOST_CTRL_2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_UHS_MODE_SEL, cfg->speed);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SDH_V18_EN, cfg->vlot18Enable);
+ BL_WR_REG16(SDH_BASE, SDH_HOST_CTRL_2, tmpVal);
+ }
+
+ tmpVal = BL_RD_REG(SDH_BASE, SDH_TX_CFG_REG);
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_TX_INT_CLK_SEL);
+ BL_WR_REG(SDH_BASE, SDH_TX_CFG_REG, tmpVal);
+
+ SDH_EnableStatus();
+
+#ifndef BFLB_USE_HAL_DRIVER
+ Interrupt_Handler_Register(SDH_IRQn, SDH_MMC1_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief SDH deinit function
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Deinit(void)
+{
+ SDH_DisableDMA();
+}
+
+/****************************************************************************/ /**
+ * @brief SDH reset function
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Reset(void)
+{
+ uint16_t tmpVal;
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);
+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SW_RST_ALL);
+ BL_WR_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET, tmpVal);
+
+ /* Wait for reset done */
+ do {
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);
+ } while (BL_IS_REG_BIT_SET(tmpVal, SDH_SW_RST_ALL));
+}
+/****************************************************************************/ /**
+ * @brief SDH set timeout function
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Set_Timeout(uint8_t tmo)
+{
+ uint16_t tmpVal;
+
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_TIMEOUT_VALUE, tmo);
+ BL_WR_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief SDH get capability
+ *
+ * @param capability: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_GetCapability(SDH_Cap_Cfg_Type *capability)
+{
+ /* Get the capability */
+ capability->maxBlockLength = 512;
+ capability->maxBlockCount = 65536;
+ capability->flags = (SDH_CAP_SUPPORT_8BITS |
+ SDH_CAP_SUPPORT_ADMA2 |
+ SDH_CAP_SUPPORT_ADMA1 |
+ SDH_CAP_SUPPORT_HIGHSPEED |
+ SDH_CAP_SUPPORT_SDMA |
+ SDH_CAP_SUPPORT_SUS_RES |
+ SDH_CAP_SUPPORT_VLT33 |
+ SDH_CAP_SUPPORT_VLT18 |
+ SDH_CAP_SUPPORT_SBUS_64BITS |
+ SDH_CAP_SUPPORT_ASYNC_INT |
+ SDH_CAP_SUPPORT_DDR50 |
+ SDH_CAP_SUPPORT_SDR104 |
+ SDH_CAP_SUPPORT_SDR50 |
+ SDH_CAP_SUPPORT_DRV_TYPE_A |
+ SDH_CAP_SUPPORT_DRV_TYPE_C |
+ SDH_CAP_SUPPORT_DRV_TYPE_D |
+ SDH_CAP_SUPPORT_SDR50_TUNE);
+}
+
+/****************************************************************************/ /**
+ * @brief SDH create ADMA1 descriptor
+ *
+ * @param adma1Entries: ADMA1 entries pointer
+ * @param maxEntries: ADMA1 entries size
+ * @param data: Data buffer to deal with
+ * @param dataLen: Data length
+ * @param flag: ADMA setting flag
+ *
+ * @return SDH deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_CreateADMA1Descriptor(uint32_t *adma1Entries, uint32_t maxEntries,
+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag)
+{
+ uint32_t miniEntries, startEntries = 0U;
+ uint32_t i, dmaBufferLen = 0U;
+
+ if (((uintptr_t)data % SDH_ADMA1_ADDRESS_ALIGN) != 0U) {
+ return SDH_STAT_DMA_ADDR_NOT_ALIGN;
+ }
+
+ if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
+ return SDH_STAT_NOT_SUPPORT;
+ }
+
+ /* TODO:align */
+ /* Make sure the buffer size is 4 byte aligned */
+ if (dataLen % sizeof(uint32_t) != 0U) {
+ /* make the data length as word-aligned */
+ dataLen += sizeof(uint32_t) - (dataLen % sizeof(uint32_t));
+ }
+
+ /* Check if ADMA descriptor's number is enough. */
+ if ((dataLen % SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) {
+ miniEntries = dataLen / SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+ } else {
+ miniEntries = ((dataLen / SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
+ }
+
+ /* ADMA1 needs two descriptors to finish a transfer */
+ miniEntries <<= 1U;
+
+ if (miniEntries + startEntries > maxEntries) {
+ return SDH_STAT_OUTOF_RANGE;
+ }
+
+ for (i = startEntries; i < (miniEntries + startEntries); i += 2U) {
+ if (dataLen > SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) {
+ dmaBufferLen = SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+ } else {
+ dmaBufferLen = dataLen;
+ }
+
+ adma1Entries[i] = (dmaBufferLen << SDH_ADMA1_DESCRIPTOR_LENGTH_POS);
+ adma1Entries[i] |= SDH_ADMA1_DESC_FLAG_SETLEN;
+ adma1Entries[i + 1U] = (uintptr_t)(data);
+ adma1Entries[i + 1U] |= SDH_ADMA1_DESC_FLAG_TRANSFER;
+ data += (dmaBufferLen / sizeof(uint32_t));
+ dataLen -= dmaBufferLen;
+ }
+
+ /* Set end of the descriptor */
+ adma1Entries[i - 1U] |= SDH_ADMA1_DESC_FLAG_END;
+
+ return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH create ADMA2 descriptor
+ *
+ * @param adma2Entries: ADMA2 entries pointer
+ * @param maxEntries: ADMA2 entries size
+ * @param data: Data buffer to deal with
+ * @param dataLen: Data length
+ * @param flag: ADMA setting flag
+ *
+ * @return SDH deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint32_t maxEntries,
+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag)
+{
+ uint32_t miniEntries, startEntries = 0U;
+ uint32_t i, dmaBufferLen = 0U;
+
+ if (((uintptr_t)data % SDH_ADMA2_ADDRESS_ALIGN) != 0U) {
+ return SDH_STAT_DMA_ADDR_NOT_ALIGN;
+ }
+
+ /* TODO:align */
+ /* Make sure the buffer size is 4 byte aligned */
+ if (dataLen % sizeof(uint32_t) != 0U) {
+ /* make the data length as word-aligned */
+ dataLen += sizeof(uint32_t) - (dataLen % sizeof(uint32_t));
+ }
+
+ /* Check if ADMA descriptor's number is enough. */
+ if ((dataLen % SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) {
+ miniEntries = dataLen / SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+ } else {
+ miniEntries = ((dataLen / SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
+ }
+
+ /* Calculate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor
+ data address and data size is enough */
+ if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
+ for (i = 0U; i < maxEntries; i++) {
+ if ((adma2Entries[i].attribute & SDH_ADMA2_DESC_FLAG_VALID) == 0U) {
+ break;
+ }
+ }
+
+ startEntries = i;
+ /* Add one entry for dummy entry */
+ miniEntries += 1U;
+ }
+
+ if (miniEntries + startEntries > maxEntries) {
+ return SDH_STAT_OUTOF_RANGE;
+ }
+
+ for (i = startEntries; i < (miniEntries + startEntries); i++) {
+ if (dataLen > SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) {
+ dmaBufferLen = SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+ } else {
+ /* TODO:align */
+ /* Adma don't support 0 data length transfer descriptor */
+ dmaBufferLen = (dataLen == 0U ? sizeof(uint32_t) : dataLen);
+ }
+
+ /* Each descriptor for ADMA2 is 64-bit in length */
+ adma2Entries[i].address = (dataLen == 0U) ? (uint32_t)(uintptr_t)&bootDummy : (uint32_t)(uintptr_t)data;
+ adma2Entries[i].attribute = (dmaBufferLen << SDH_ADMA2_DESCRIPTOR_LENGTH_POS);
+ adma2Entries[i].attribute |= (dataLen == 0U) ? 0U : (SDH_ADMA2_DESC_FLAG_TRANSFER);
+ // (dataLen == 0U) ? 0U : (SDH_ADMA2_DESC_FLAG_TRANSFER | SDH_ADMA2_DESC_FLAG_INT);
+ /* TODO:align */
+ data += (dmaBufferLen / sizeof(uint32_t));
+
+ if (dataLen != 0U) {
+ dataLen -= dmaBufferLen;
+ }
+ }
+
+ /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA
+ engine will not stop at block gap */
+ if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
+ //adma2Entries[startEntries + 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;
+ adma2Entries[i - 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;
+ } else {
+ /* Set the end bit */
+ adma2Entries[i - 1U].attribute |= SDH_ADMA2_DESC_FLAG_END;
+ }
+
+ return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH set DMA config
+ *
+ * @param dmaCfg: DMA config pointer
+ * @param data: Data pointer for sending
+ * @param enAutoCmd23: Whether enable auto command 23
+ *
+ * @return DMA config deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_SetInternalDmaConfig(SDH_DMA_Cfg_Type *dmaCfg, const uint32_t *data, uint8_t enAutoCmd23)
+{
+ uint16_t tmpVal;
+
+ if (dmaCfg->dmaMode == SDH_DMA_MODE_SIMPLE) {
+ /* Check DMA data buffer address align or not */
+ if (((uintptr_t)data % SDH_SDMA_LENGTH_ALIGN) != 0U) {
+ return SDH_STAT_DMA_ADDR_NOT_ALIGN;
+ }
+
+ /* In simple DMA mode if use auto CMD23, address should load to ADMA addr,
+ and block count should load to DS_ADDR*/
+ if (enAutoCmd23) {
+ BL_WR_REG(SDH_BASE, SDH_SD_ADMA_SYS_ADDR_1, (uintptr_t)data);
+ } else {
+ BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, (uintptr_t)data);
+ }
+ } else {
+ /* When use ADMA, disable simple DMA */
+ BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, (uint32_t)0);
+ BL_WR_REG(SDH_BASE, SDH_SD_ADMA_SYS_ADDR_1, (uintptr_t)(dmaCfg->admaEntries));
+ }
+
+ /* Select DMA mode and config the burst length */
+ SDH_EnableDMA(dmaCfg->dmaMode);
+
+ /* Set DMA burst size and FIFO threshold */
+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_AND_BURST_SIZE_SETUP);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DMA_SIZE, dmaCfg->fifoThreshold);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_BRST_SIZE, dmaCfg->burstSize);
+ BL_WR_REG16(SDH_BASE, SDH_SD_CLOCK_AND_BURST_SIZE_SETUP, tmpVal);
+
+ return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH create DMA entries according to DMA config
+ *
+ * @param dmaCfg: DMA config pointer
+ * @param dataCfg: Data config pointer
+ * @param flag: ADMA create entries flag
+ *
+ * @return Create entries result
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_CreateAdmaEntryConfig(SDH_DMA_Cfg_Type *dmaCfg, SDH_Data_Cfg_Type *dataCfg, SDH_ADMA_Flag_Type flag)
+{
+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+
+ /* TODO:align */
+ uint32_t bootDummyOffset = (dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT ? sizeof(uint32_t) : 0);
+ const uint32_t *data = (const uint32_t *)((dataCfg->rxData == NULL) ? dataCfg->txData : dataCfg->rxData);
+ uint32_t dataLen = dataCfg->blockSize * dataCfg->blockCount;
+
+ data += bootDummyOffset;
+ dataLen -= bootDummyOffset;
+
+ switch (dmaCfg->dmaMode) {
+ case SDH_DMA_MODE_SIMPLE:
+ stat = SDH_STAT_SUCCESS;
+ break;
+
+ case SDH_DMA_MODE_ADMA1:
+ stat = SDH_CreateADMA1Descriptor(dmaCfg->admaEntries, dmaCfg->maxEntries, data, dataLen, flag);
+ break;
+
+ case SDH_DMA_MODE_ADMA2:
+ stat = SDH_CreateADMA2Descriptor((SDH_ADMA2_Desc_Type *)dmaCfg->admaEntries, dmaCfg->maxEntries, data, dataLen, flag);
+ break;
+
+ default:
+ return SDH_STAT_SEND_DATA_FAIL;
+ }
+
+ /* For internal dma, internal DMA configurations should not update the configurations when continous transfer the
+ * boot data, only the DMA descriptor need update */
+ if ((stat == SDH_STAT_SUCCESS) && (dataCfg->dataType != SDH_TRANS_DATA_BOOT_CONT)) {
+ stat = SDH_SetInternalDmaConfig(dmaCfg, data, dataCfg->enableAutoCommand23);
+ }
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH transfer data in blocking way
+ *
+ * @param dmaCfg: DMA config pointer
+ * @param transfer: Transfer config pointer
+ *
+ * @return Transfer deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_TransferBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer)
+{
+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+ SDH_CMD_Cfg_Type *cmdCfg = transfer->cmdCfg;
+ SDH_Data_Cfg_Type *dataCfg = transfer->dataCfg;
+ uint32_t intStatus;
+ uint8_t enDMA = 1;
+ uint8_t executeTuning = ((dataCfg == NULL) ? 0 : dataCfg->dataType == SDH_TRANS_DATA_TUNING);
+ //volatile uint32_t tmp;
+ /* Check re-tuning request */
+ intStatus = SDH_GetIntStatus();
+
+ if ((intStatus & SDH_INT_RETUNE_EVENT) != 0U) {
+ SDH_ClearIntStatus(SDH_INT_RETUNE_EVENT);
+ return SDH_STAT_RETUNE_REQ;
+ }
+
+ /* Update ADMA descriptor table according to different DMA mode(simple DMA, ADMA1, ADMA2).*/
+ if ((dataCfg != NULL) && (dmaCfg != NULL) && (!executeTuning)) {
+ stat = SDH_CreateAdmaEntryConfig(dmaCfg, dataCfg, (dataCfg->dataType & SDH_TRANS_DATA_BOOT) ? SDH_ADMA_FLAG_MULTI_DESC : SDH_ADMA_FLAG_SINGLE_DESC);
+ }
+
+ /* If the DMA desciptor configure fail or not needed , disable it */
+ if ((stat != SDH_STAT_SUCCESS) || (dmaCfg == NULL)) {
+ enDMA = 0;
+ /* Disable DMA, using polling mode in this situation */
+ SDH_DisableDMA();
+ }
+
+ /* Config the data transfer parameter */
+ stat = SDH_ConfigDataTranfer(dataCfg);
+
+ if (SDH_STAT_SUCCESS != stat) {
+ return stat;
+ }
+
+ /* Send command first */
+ if (dataCfg != NULL) {
+ cmdCfg->flag = SDH_TRANS_FLAG_DATA_PRESENT;
+ } else {
+ cmdCfg->flag = 0;
+ }
+
+ SDH_SendCommand(cmdCfg);
+
+ /* Wait command done */
+ if ((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL)) {
+ stat = SDH_WaitCommandDone(cmdCfg);
+ }
+
+ /*
+ tmp = BL_RD_REG16(SDH_BASE,SDH_SD_ADMA_ERROR_STATUS);
+ bflb_platform_printf("SDH_SD_ADMA_ERROR_STATUS->0x%x!\r\n",tmp);
+ tmp = BL_RD_REG16(SDH_BASE,SDH_SD_AUTO_CMD12_ERROR_STATUS);
+ */
+
+ /* Wait for transferring data finish */
+ if ((dataCfg != NULL) && (stat == SDH_STAT_SUCCESS)) {
+ stat = SDH_TransferDataBlocking(dataCfg, enDMA);
+ }
+
+ return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH transfer data in blocking way
+ *
+ * @param handle: SDH handler
+ * @param dmaCfg: DMA config pointer
+ * @param transfer: Transfer config pointer
+ *
+ * @return Transfer deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_TransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer)
+{
+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+ SDH_CMD_Cfg_Type *cmdCfg = transfer->cmdCfg;
+ SDH_Data_Cfg_Type *dataCfg = transfer->dataCfg;
+ uint32_t intStatus;
+ uint8_t executeTuning = ((dataCfg == NULL) ? 0 : dataCfg->dataType == SDH_TRANS_DATA_TUNING);
+
+ /* Check re-tuning request */
+ intStatus = SDH_GetIntStatus();
+
+ if ((intStatus & SDH_INT_RETUNE_EVENT) != 0U) {
+ SDH_ClearIntStatus(SDH_INT_RETUNE_EVENT);
+ return SDH_STAT_RETUNE_REQ;
+ }
+
+ /* Update ADMA descriptor table according to different DMA mode(simple DMA, ADMA1, ADMA2).*/
+ if ((dataCfg != NULL) && (dmaCfg != NULL) && (!executeTuning)) {
+ stat = SDH_CreateAdmaEntryConfig(dmaCfg, dataCfg, (dataCfg->dataType & SDH_TRANS_DATA_BOOT) ? SDH_ADMA_FLAG_MULTI_DESC : SDH_ADMA_FLAG_SINGLE_DESC);
+ }
+
+ /* If the DMA desciptor configure fail or not needed , disable it */
+ if (stat != SDH_STAT_SUCCESS) {
+ /* Disable DMA, using polling mode in this situation */
+ //SDH_DisableDMA();
+ return stat;
+ }
+
+ /* Config the data transfer parameter */
+ stat = SDH_ConfigDataTranfer(dataCfg);
+
+ if (SDH_STAT_SUCCESS != stat) {
+ return stat;
+ }
+
+ /* Send command first */
+ if (dataCfg != NULL) {
+ cmdCfg->flag |= SDH_TRANS_FLAG_DATA_PRESENT;
+ }
+
+#if 0
+ SDH_SendCommand(cmdCfg);
+
+
+ /* Wait command done */
+ if((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL))
+ {
+ stat = SDH_WaitCommandDone(cmdCfg);
+ }
+
+#endif
+
+ return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH install callback function for handler
+ *
+ * @param handle: SDH handler
+ * @param callBack: SDH callBack function
+ * @param userData: User private data for SDH handler
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle,
+ const SDH_Trans_Callback_Cfg_Type *callBack, void *userData)
+{
+ /* Zero the handle. */
+ ARCH_MemSet(handle, 0, sizeof(SDH_Handle_Cfg_Type));
+
+ /* Set the callback. */
+ handle->callBack.SDH_CallBack_CardInserted = callBack->SDH_CallBack_CardInserted;
+ handle->callBack.SDH_CallBack_CardRemoved = callBack->SDH_CallBack_CardRemoved;
+ handle->callBack.SDH_CallBack_SdioInterrupt = callBack->SDH_CallBack_SdioInterrupt;
+ handle->callBack.SDH_CallBack_BlockGap = callBack->SDH_CallBack_BlockGap;
+ handle->callBack.SDH_CallBack_TransferFinished = callBack->SDH_CallBack_TransferFinished;
+ handle->callBack.SDH_CMDCallBack_TransferFinished = callBack->SDH_CMDCallBack_TransferFinished;
+ handle->callBack.SDH_CallBack_ReTuning = callBack->SDH_CallBack_ReTuning;
+ handle->callBack.SDH_CallBack_Vendor = callBack->SDH_CallBack_ReTuning;
+ handle->userData = userData;
+
+ /* Save the handle in global variables */
+ sdhHandle = handle;
+}
+
+/****************************************************************************/ /**
+ * @brief SDH interrupt handle
+ *
+ * @param intPeriph: Select the peripheral
+ * @param handle: SDH handler
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
+{
+ uint32_t intFlag, intMask;
+
+ intFlag = SDH_GetIntStatus();
+ intMask = SDH_GetIntEnableStatus();
+ intFlag &= intMask;
+
+ if (NULL == handle) {
+ SDH_ClearIntStatus(intFlag);
+ return;
+ }
+
+ handle->intFlag = intFlag;
+
+ /* Card insert interrupt */
+ if (intFlag & SDH_INT_CARD_INSERT) {
+ if (NULL != handle->callBack.SDH_CallBack_CardInserted) {
+ handle->callBack.SDH_CallBack_CardInserted(handle->userData);
+ }
+ }
+
+ /* Card remove interrupt */
+ if (intFlag & SDH_INT_CARD_REMOVE) {
+ if (NULL != handle->callBack.SDH_CallBack_CardRemoved) {
+ handle->callBack.SDH_CallBack_CardRemoved(handle->userData);
+ }
+ }
+
+ /* Command error interrupt */
+ if (intFlag & (SDH_INT_CMD_ERRORS)) {
+ if (NULL != handle->callBack.SDH_CMDCallBack_TransferFinished) {
+ handle->callBack.SDH_CMDCallBack_TransferFinished(handle, SDH_STAT_SEND_CMD_FAIL, handle->userData);
+ }
+ }
+
+ /* Command success interrupt */
+ if (intFlag & SDH_INT_CMD_COMPLETED) {
+ if (NULL != handle->callBack.SDH_CMDCallBack_TransferFinished &&
+ NULL == handle->dataCfg) {
+ /* Only deal with pure command, user need check response to make sure in SDH_CallBack_TransferFinished */
+ handle->callBack.SDH_CMDCallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);
+ }
+ }
+
+ /* Data error interrupt */
+ if (intFlag & (SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR)) {
+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+ handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SEND_DATA_FAIL, handle->userData);
+ }
+ }
+
+ /* Data success interrupt*/
+ if (intFlag & SDH_INT_DATA_COMPLETED) {
+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+ handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);
+ }
+ }
+
+ /* Card interrupt */
+ if (intFlag & SDH_INT_CARD) {
+ if (handle->callBack.SDH_CallBack_SdioInterrupt) {
+ handle->callBack.SDH_CallBack_SdioInterrupt(handle->userData);
+ }
+ }
+
+ /* Buffer read ready interrupt*/
+ if (intFlag & SDH_INT_BUFFER_READ_READY) {
+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+ handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);
+ } else {
+ handle->dataCfg->rxDataLen += SDH_ReadDataPort(handle->dataCfg);
+ }
+ }
+
+ /* Buffer write ready interrupt */
+ if (intFlag & SDH_INT_BUFFER_WRITE_READY) {
+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+ handle->dataCfg->txDataLen += SDH_WriteDataPort(handle->dataCfg);
+ }
+ }
+
+ /* DMA success interrupt*/
+ if (intFlag & SDH_INT_DMA_COMPLETED) {
+ if (handle->dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) {
+ *(handle->dataCfg->rxData) = bootDummy;
+ }
+ }
+
+ /* Block gap event interrupt */
+ if (intFlag & SDH_INT_BLK_GAP_EVENT) {
+ if (handle->callBack.SDH_CallBack_BlockGap) {
+ handle->callBack.SDH_CallBack_BlockGap(handle->userData);
+ }
+ }
+
+ /* Re-tuning event interrupt */
+ if (intFlag & SDH_INT_RETUNE_EVENT) {
+ if (handle->callBack.SDH_CallBack_ReTuning) {
+ handle->callBack.SDH_CallBack_ReTuning(handle->userData);
+ }
+ }
+
+ /* Vendor specified interrupt */
+ if (intFlag & (SDH_INT_SPI_ERROR |
+ SDH_INT_AXI_RESP_ERROR |
+ SDH_INT_CPL_TIMEOUT_ERROR |
+ SDH_INT_CRC_STAT_ERROR)) {
+ if (handle->callBack.SDH_CallBack_Vendor) {
+ handle->callBack.SDH_CallBack_Vendor(handle->userData);
+ }
+ }
+
+ SDH_ClearIntStatus(intFlag);
+}
+
+/****************************************************************************/ /**
+ * @brief SDH interrupt handler
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_MMC1_IRQHandler(void)
+{
+ SDH_IntHandler(SDH_IRQn, sdhHandle);
+}
+
+/*@} end of group SDH_Public_Functions */
+
+/*@} end of group SDH */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_tzc_sec.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_tzc_sec.c
new file mode 100644
index 00000000..6ae89f3f
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_tzc_sec.c
@@ -0,0 +1,898 @@
+/**
+ ******************************************************************************
+ * @file bl808_tzc_sec.c
+ * @version V1.0
+ * @date
+ * @brief This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2020 Bouffalo Lab
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "string.h"
+#include "bl808_tzc_sec.h"
+#include "bl808_glb.h"
+
+/** @addtogroup BL808_Peripheral_Driver
+ * @{
+ */
+
+/** @addtogroup TZC_ENG
+ * @{
+ */
+
+/** @defgroup TZC_ENG_Private_Macros
+ * @{
+ */
+
+/*@} end of group TZC_ENG_Private_Macros */
+
+/** @defgroup TZC_ENG_Private_Types
+ * @{
+ */
+
+/*@} end of group TZC_ENG_Private_Types */
+
+/** @defgroup TZC_ENG_Private_Variables
+ * @{
+ */
+
+/*@} end of group TZC_ENG_Private_Variables */
+
+/** @defgroup TZC_ENG_Global_Variables
+ * @{
+ */
+
+/*@} end of group TZC_ENG_Global_Variables */
+
+/** @defgroup TZC_ENG_Private_Fun_Declaration
+ * @{
+ */
+
+/*@} end of group TZC_ENG_Private_Fun_Declaration */
+
+/** @defgroup TZC_ENG_Private_Functions
+ * @{
+ */
+
+/*@} end of group TZC_ENG_Private_Functions */
+
+/** @defgroup TZC_ENG_Public_Functions
+ * @{
+ */
+
+/****************************************************************************/ /**
+ * @brief None
+ *
+ * @param None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_Sboot_Done(void)
+{
+ uint32_t tmpVal;
+ /* Set Sboot done */
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+}
+
+void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ if (masterType < TZC_SEC_MASTER_D0) {
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
+
+ if (group == 0) {
+ tmpVal &= (~(1 << masterType));
+ } else {
+ tmpVal |= (1 << masterType);
+ }
+ tmpVal |= (1 << (masterType + 16));
+ tmpVal2 |= (1 << masterType);
+
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
+ } else {
+ masterType -= TZC_SEC_MASTER_D0;
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID);
+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK);
+
+ if (group == 0) {
+ tmpVal &= (~(1 << masterType));
+ } else {
+ tmpVal |= (1 << masterType);
+ }
+ tmpVal |= (1 << (masterType + 16));
+ tmpVal2 |= (1 << masterType);
+
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID, tmpVal);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK, tmpVal2);
+ }
+}
+
+void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group)
+{
+ uint32_t tmpVal;
+
+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SLAVE_MAX) {
+ return;
+ }
+ group = 1 << (group);
+
+ if (slaveType >= TZC_SEC_SLAVE_MM) {
+ slaveType -= TZC_SEC_SLAVE_MM;
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0);
+ /* set group */
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ /* set lock*/
+ tmpVal |= (1 << (slaveType + 16));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0, tmpVal);
+ } else if (slaveType < TZC_SEC_SLAVE_EMI_MISC) {
+ slaveType -= TZC_SEC_SLAVE_GLB;
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1);
+ /* set group */
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);
+ /* set lock */
+ tmpVal |= (1 << slaveType);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);
+ } else {
+ slaveType -= TZC_SEC_SLAVE_EMI_MISC;
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2);
+ /* set group */
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);
+ /* set lock */
+ tmpVal |= (1 << (slaveType + TZC_SEC_SLAVE_EMI_MISC));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);
+ }
+}
+
+void Tzc_Sec_Set_MM_Slave_Group(TZC_SEC_MM_Slave_Type slaveType, uint8_t group)
+{
+ uint32_t tmpVal;
+
+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_MM_SLAVE_MAX) {
+ return;
+ }
+ group = 1 << (group);
+
+ if (slaveType < TZC_SEC_MM_SLAVE_ISP_MISC) {
+ /* set group */
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S0);
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S0, tmpVal);
+
+ /* set lock */
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK0);
+ tmpVal |= (1 << slaveType);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK0, tmpVal);
+
+ } else if (slaveType < TZC_SEC_MM_SLAVE_CODEC_MISC) {
+ slaveType -= TZC_SEC_MM_SLAVE_ISP_MISC;
+
+ /* set group */
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S1);
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S1, tmpVal);
+
+ /* set lock */
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1);
+ tmpVal |= (1 << (slaveType + 16));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1, tmpVal);
+ } else {
+ slaveType -= TZC_SEC_MM_SLAVE_CODEC_MISC;
+
+ /* set group */
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S2);
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S2, tmpVal);
+
+ /* set lock */
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1);
+ tmpVal |= (1 << slaveType);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1, tmpVal);
+ }
+}
+
+void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group)
+{
+ uint32_t tmpVal;
+
+ if (slaveType >= TZC_SEC_GLB_CTRL_MAX || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0);
+ /* set group */
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2);
+ /* set lock */
+ tmpVal |= (1 << slaveType);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2, tmpVal);
+}
+
+void Tzc_Sec_Set_MM_Glb_Ctrl_Group(TZC_SEC_MM_GLB_Ctrl_Type slaveType, uint8_t group)
+{
+ uint32_t tmpVal;
+
+ if (slaveType >= TZC_SEC_MM_GLB_CTRL_MAX || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_0);
+ /* set group */
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_0, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_2);
+ /* set lock */
+ tmpVal |= (1 << slaveType);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_2, tmpVal);
+}
+
+void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group)
+{
+ uint32_t tmpVal;
+ uint32_t tmpVal2;
+
+ if (cpu == GLB_CORE_ID_M0) {
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
+
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_CPU_TZMID, group);
+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_CPU_TZMID_LOCK, 1);
+
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
+ } else if (cpu == GLB_CORE_ID_D0) {
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID);
+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK);
+
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_MMCPU_TZMID, group);
+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_MMCPU_TZMID, 1);
+
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID, tmpVal);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK, tmpVal2);
+
+ } else if (cpu == GLB_CORE_ID_LP) {
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
+
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_PICO_TZMID, group);
+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_PICO_TZMID_LOCK, 1);
+
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
+ }
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set ROM region access configuration
+ *
+ * @param region: ROM region index 0-2
+ * @param startAddr: ROM region start address
+ * @param length: ROM region length
+ * @param group: ROM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 24);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set OCRAM region access configuration
+ *
+ * @param region: OCRAM region index 0-2
+ * @param startAddr: OCRAM region start address
+ * @param length: OCRAM region length
+ * @param group: OCRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3) {
+ return;
+ }
+ group = group & 0xf;
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+ tmpVal &= (~(0xf << (region * 4)));
+ tmpVal |= (group << (region * 4));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_OCRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 20);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set OCRAM regionx access configuration
+ *
+ * @param group: OCRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint8_t region = 3;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 4)));
+ tmpVal |= (group << (region * 4));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 20);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set WRAM region access configuration
+ *
+ * @param region: WRAM region index 0-2
+ * @param startAddr: WRAM region start address
+ * @param length: WRAM region length
+ * @param group: WRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3) {
+ return;
+ }
+ group = group & 0xf;
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+ tmpVal &= (~(0xf << (region * 4)));
+ tmpVal |= (group << (region * 4));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_WRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 20);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set WRAM regionx access configuration
+ *
+ * @param group: WRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint8_t region = 3;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 4)));
+ tmpVal |= (group << (region * 4));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 20);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set Flash region access configuration
+ *
+ * @param region: Flash region index 0-2
+ * @param startAddr: Flash region start address
+ * @param length: Flash region length
+ * @param group: Flash region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t tmpVal2 = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 4 || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 0xf & (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+ tmpVal &= (~(0xf << (region * 4)));
+ tmpVal |= (group << (region * 4));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+
+ /* Set range */
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* Set range MSB */
+ tmpVal = BL_RD_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET);
+ tmpVal = tmpVal & (0xff << (8 * region));
+ tmpVal2 = ((alignEnd >> 26) & 0x7) | (((startAddr >> 26) & 0x7) << 3);
+ tmpVal2 = tmpVal2 << (8 * region);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET, tmpVal | tmpVal2);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 20);
+ tmpVal |= 1 << (region + 25);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set Flash regionx access configuration
+ *
+ * @param group: Flash region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint8_t region = 4;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 4)));
+ tmpVal |= (group << (region * 4));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 20);
+ tmpVal |= 1 << (region + 25);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set L2SRAM region access configuration
+ *
+ * @param region: L2SRAM region index 0-2
+ * @param startAddr: L2SRAM region start address
+ * @param length: L2SRAM region length
+ * @param group: L2SRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_L2SRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_L2SRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 24);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set VRAM region access configuration
+ *
+ * @param region: VRAM region index 0-2
+ * @param startAddr: VRAM region start address
+ * @param length: VRAM region length
+ * @param group: VRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_VRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_VRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 24);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set PSRAMA region access configuration
+ *
+ * @param region: PSRAMA region index 0-2
+ * @param startAddr: PSRAMA region start address
+ * @param length: PSRAMA region length
+ * @param group: PSRAMA region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_PSRAMA_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMA_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 24);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
+}
+
+/**
+ * @brief TrustZone Security set Release PSRAMA region access
+ *
+ */
+void Tzc_Sec_PSRAMA_Access_Release(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t region = 0;
+ /* set disable */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
+ tmpVal &= (~(1 << (region + 16)));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set PSRAMB region access configuration
+ *
+ * @param region: PSRAMB region index 0-2
+ * @param startAddr: PSRAMB region start address
+ * @param length: PSRAMB region length
+ * @param group: PSRAMB region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 24);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+}
+/**
+ * @brief TrustZone Security set Release PSRAMB region access
+ *
+ */
+void Tzc_Sec_PSRAMB_Access_Release(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t region = 0;
+ /* set disable */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+ tmpVal &= (~(1 << (region + 16)));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+}
+/****************************************************************************/ /**
+ * @brief TrustZone Security set XRAM region access configuration
+ *
+ * @param region: XRAM region index 0-2
+ * @param startAddr: XRAM region start address
+ * @param length: XRAM region length
+ * @param group: XRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_XRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
+
+ /* check the parameter */
+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL, tmpVal);
+
+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_XRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable and lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ tmpVal |= 1 << (region + 24);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set sec_eng module config
+ *
+ * @param mode: sec_eng control mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD, mode);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+ /* set lock */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD_LOCK, 1);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set sf_ctrl module config
+ *
+ * @param mode: sf_ctrl control mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD, mode);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+ /* set lock */
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD_LOCK, 1);
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group)
+{
+ uint32_t tmpVal;
+
+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SE_CTRL_MAX) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0);
+ /* set group */
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+ /* set lock */
+ tmpVal |= (1 << (slaveType));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group)
+{
+ uint32_t tmpVal;
+
+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SF_CTRL_MAX) {
+ return;
+ }
+ group = 1 << (group);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1);
+ /* set group */
+ tmpVal &= (~(3 << (slaveType * 2)));
+ tmpVal |= (group << (slaveType * 2));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);
+
+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+ /* set lock */
+ tmpVal |= (1 << (slaveType + 16));
+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief TrustZone Security set watchdog reset delay value
+ *
+ * @param mode: sec_eng control mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_WDT_DLY, delayValue);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
+}
+
+/*@} end of group TZC_ENG_Public_Functions */
+
+/*@} end of group TZC_ENG */
+
+/*@} end of group BL808_Peripheral_Driver */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_uhs_phy.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_uhs_phy.c
new file mode 100644
index 00000000..72d5a6fc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/src/bl808_uhs_phy.c
@@ -0,0 +1,2894 @@
+#include "bl808_uhs_phy.h"
+#include
+#include
+#include
+#include "psram_uhs_reg.h"
+#include "glb_reg.h"
+#include "pds_reg.h"
+
+#define bl808_DBG_RF (0) // 0 is for commit with only err log, 1 is for all debug log, 2 is for key debug log
+#if bl808_DBG_RF == 1
+ #define uhs_phy_printf_debug printf // debug mode
+ #define uhs_phy_printf printf
+ #define uhs_phy_printfe printf
+#elif bl808_DBG_RF == 2
+ #define uhs_phy_printf_debug(...)
+ #define uhs_phy_printf printf // commit it out in release version, use to collect data
+ // #define uhs_phy_printf(...) // used in release version
+ #define uhs_phy_printfe printf
+#else
+ #define uhs_phy_printf_debug(...)
+ #define uhs_phy_printf(...)
+ #define uhs_phy_printfe printf
+#endif
+
+#define ODT_EN (0)
+// #define PSRAM_32MB (0)
+#define CACHE_EN (0) // unused !
+
+static uhs_phy_cal_res_struct cal_res;
+uhs_phy_cal_res_struct* uhs_phy_cal_res = &cal_res;
+static uint8_t err_flag = 0;
+#define CHECK_ERR_FLAG(func,args) {\
+ func args;\
+ if(err_flag)return err_flag;\
+}
+
+static uint32_t cache_state = 0;
+static uint8_t uhs_latency_code = 1;
+static uint32_t dqs_dq_delta = 0;
+static uint32_t dcache_original = 0;
+static uint32_t dcache_current = 0;
+static uint32_t dcache_end = 0;
+static uint8_t regr_done_err = 0;
+static uint8_t reg_read_err = 0;
+static uint8_t reg_write_err = 0;
+static uint8_t init_array_write_err = 0;
+static uint8_t array_read_err = 0;
+static uint32_t addr_dump = 0x3000F000;
+//
+static uint32_t addr_rarray = 0x50000000;
+static uint32_t data0_rarray = 0x12345678;
+static uint32_t data1_rarray = 0x87654321;
+// uint32_t datarate_glb;
+static uint32_t latency_wr[2] = {9,30};
+static PSRAM_UHS_Cfg_Type *cfg_glb;
+// static uint32_t addr_sr[3] = {0x3000f014,0x3000f018,0x3000f020};
+// static uint32_t val_sr[3] = {0x0,0x0,0x0};
+static uint32_t latency_wr_2kM[2] = {13,41};
+static uint8_t cal_done_flag = 0;
+static uint8_t print_flag = 0;
+// static uint32_t latency_wr_2kM_init[2] = {13,36};
+static uint8_t flag_ck1 = 0;
+static uint8_t flag_ck2 = 0;
+
+void set_uhs_latency_w(uint32_t uhs_latency);
+void set_uhs_latency_r(uint32_t uhs_latency);
+void uhs_reset(uint8_t ma_rb);
+void uhs_phy_reg_dump(void);
+void set_or_uhs(void);
+uint8_t mr_read_back(void);
+uint8_t uhs_phy_init_core(PSRAM_UHS_Cfg_Type *cfg);
+
+void uhs_phy_delay_us(uint32_t us)
+{
+ arch_delay_us(us);
+}
+
+void uhs_phy_delay_ms(uint32_t ms)
+{
+ arch_delay_ms(ms);
+}
+
+void uhs_phy_af_reg(uint32_t REG_PCK_T_DIV,uint32_t REG_WIN_CYCLE,uint32_t REG_WIN_REF_CNT,uint32_t REG_REFI_CYCLE,uint32_t REG_BUST_CYCLE)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,REG_PCK_T_DIV);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,REG_WIN_CYCLE);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,REG_WIN_REF_CNT);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,REG_REFI_CYCLE);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,REG_BUST_CYCLE);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+}
+
+void uhs_phy_af_onoff(uint8_t onoff){
+ uint32_t tmpVal = 0;
+
+ if(onoff){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ uhs_phy_delay_us(50);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ // uhs_phy_delay_us(50);
+ }else{
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x0);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ // uhs_phy_delay_us(50);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ uhs_phy_delay_us(50);
+ }
+}
+
+void uhs_phy_af_cfg(void)
+{
+ // uint32_t tmpVal = 0;
+
+ uhs_phy_af_onoff(0);
+
+ if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB && cfg_glb->isHighTem == PSRAM_UHS_HIGH_TEMP){
+ if(cfg_glb->pck_freq == 2000){
+ uhs_phy_af_reg(0x4,0xF423F,0x2000,0x79,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1900){
+ uhs_phy_af_reg(0x4,0xE7EEF,0x2000,0x72,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1800){
+ uhs_phy_af_reg(0x4,0xDBB9F,0x2000,0x6C,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1700){
+ uhs_phy_af_reg(0x4,0xCF84F,0x2000,0x66,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1600){
+ uhs_phy_af_reg(0x4,0xC34FF,0x2000,0x60,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1500){
+ uhs_phy_af_reg(0x4,0xB71AF,0x2000,0x5A,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1400){
+ uhs_phy_af_reg(0x4,0xAAE5F,0x2000,0x54,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1300){
+ uhs_phy_af_reg(0x4,0x9EB0F,0x2000,0x4E,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1200){
+ uhs_phy_af_reg(0x4,0x927BF,0x2000,0x48,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1100){
+ uhs_phy_af_reg(0x4,0x8646F,0x2000,0x42,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1000){
+ uhs_phy_af_reg(0x4,0x7A11F,0x2000,0x3C,0x3);
+ }
+ else if(cfg_glb->pck_freq == 900){
+ uhs_phy_af_reg(0x4,0x6DDCF,0x2000,0x35,0x3);
+ }
+ else{
+ uhs_phy_af_reg(0x4,0x61A7F,0x2000,0x2F,0x3);
+ }
+ }
+ else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ if(cfg_glb->pck_freq == 2000){
+ uhs_phy_af_reg(0x4,0x1E847F,0x2000,0xF3,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1900){
+ uhs_phy_af_reg(0x4,0x1CFDDF,0x2000,0xE6,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1800){
+ uhs_phy_af_reg(0x4,0x1B773F,0x2000,0xDA,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1700){
+ uhs_phy_af_reg(0x4,0x19F09F,0x2000,0xCE,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1600){
+ uhs_phy_af_reg(0x4,0x1869FF,0x2000,0xC2,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1500){
+ uhs_phy_af_reg(0x4,0x16E35F,0x2000,0xB6,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1400){
+ uhs_phy_af_reg(0x4,0x155CBF,0x2000,0xA9,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1300){
+ uhs_phy_af_reg(0x4,0x13D61F,0x2000,0x9D,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1200){
+ uhs_phy_af_reg(0x4,0x124F7F,0x2000,0x91,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1100){
+ uhs_phy_af_reg(0x4,0x10C8DF,0x2000,0x85,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1000){
+ uhs_phy_af_reg(0x4,0xF423F,0x2000,0x79,0x3);
+ }
+ else if(cfg_glb->pck_freq == 900){
+ uhs_phy_af_reg(0x4,0xDBB9F,0x2000,0x6C,0x3);
+ }
+ else{
+ uhs_phy_af_reg(0x4,0xC34FF,0x2000,0x60,0x3);
+ }
+ }
+ else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB && cfg_glb->isHighTem == PSRAM_UHS_HIGH_TEMP){
+ if(cfg_glb->pck_freq == 2000){
+ uhs_phy_af_reg(0x4,0xF423F,0x1000,0xF3,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1900){
+ uhs_phy_af_reg(0x4,0xE7EEF,0x1000,0xE6,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1800){
+ uhs_phy_af_reg(0x4,0xDBB9F,0x1000,0xDA,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1700){
+ uhs_phy_af_reg(0x4,0xCF84F,0x1000,0xCE,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1600){
+ uhs_phy_af_reg(0x4,0xC34FF,0x1000,0xC2,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1500){
+ uhs_phy_af_reg(0x4,0xB71AF,0x1000,0xB6,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1400){
+ uhs_phy_af_reg(0x4,0xAAE5F,0x1000,0xA9,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1300){
+ uhs_phy_af_reg(0x4,0x9EB0F,0x1000,0x9D,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1200){
+ uhs_phy_af_reg(0x4,0x927BF,0x1000,0x91,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1100){
+ uhs_phy_af_reg(0x4,0x8646F,0x1000,0x85,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1000){
+ uhs_phy_af_reg(0x4,0x7A11F,0x1000,0x79,0x3);
+ }
+ else if(cfg_glb->pck_freq == 900){
+ uhs_phy_af_reg(0x4,0x6DDCF,0x1000,0x6C,0x3);
+ }
+ else{
+ uhs_phy_af_reg(0x4,0x61A7F,0x1000,0x60,0x3);
+ }
+ }
+ else{
+ if(cfg_glb->pck_freq == 2000){
+ uhs_phy_af_reg(0x4,0x1E847F,0x1000,0x1E7,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1900){
+ uhs_phy_af_reg(0x4,0x1CFDDF,0x1000,0x1CE,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1800){
+ uhs_phy_af_reg(0x4,0x1B773F,0x1000,0x1B6,0x6);
+ }
+ else if(cfg_glb->pck_freq == 1700){
+ uhs_phy_af_reg(0x4,0x19F09F,0x1000,0x19E,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1600){
+ uhs_phy_af_reg(0x4,0x1869FF,0x1000,0x185,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1500){
+ uhs_phy_af_reg(0x4,0x16E35F,0x1000,0x16D,0x5);
+ }
+ else if(cfg_glb->pck_freq == 1400){
+ uhs_phy_af_reg(0x4,0x155CBF,0x1000,0x154,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1300){
+ uhs_phy_af_reg(0x4,0x13D61F,0x1000,0x13C,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1200){
+ uhs_phy_af_reg(0x4,0x124F7F,0x1000,0x123,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1100){
+ uhs_phy_af_reg(0x4,0x10C8DF,0x1000,0x10B,0x4);
+ }
+ else if(cfg_glb->pck_freq == 1000){
+ uhs_phy_af_reg(0x4,0xF423F,0x1000,0xF3,0x3);
+ }
+ else if(cfg_glb->pck_freq == 900){
+ uhs_phy_af_reg(0x4,0xDBB9F,0x1000,0xDA,0x3);
+ }
+ else{
+ uhs_phy_af_reg(0x4,0xC34FF,0x1000,0xC2,0x3);
+ }
+ }
+
+ uhs_phy_af_onoff(1);
+}
+
+void Psram_UHS_Init_Override(PSRAM_UHS_Cfg_Type *cfg){
+ uint32_t tmpVal = 0;
+
+ Psram_UHS_Init(cfg);
+ if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x1f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ }
+
+ #if CAL_MODE == 1
+ uhs_phy_af_cfg();
+ #endif
+
+ set_or_uhs();
+
+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_VOUT_SEL, 5);
+ BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);
+ uhs_phy_printf("GLB_LDO12UHS: %lx\r\n",tmpVal);
+ uhs_phy_delay_us(250);
+}
+
+void power_up_mm(uint8_t off)
+{
+ uint32_t tmpVal = 0;
+ if (off == 0)
+ {
+ // power up MM domain
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(150);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ // uhs_phy_delay_us(10);
+ // uhs_phy_delay_ms(1);
+ }
+ else
+ {
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ uhs_phy_delay_us(150);
+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,off);
+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+ }
+ uhs_phy_delay_us(100);
+}
+
+void power_up_uhspll(void)
+{
+ // power_up_uhspll
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL,0x1);
+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDM_RSTB,0x0);
+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+ uhs_phy_delay_us(50);
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDM_RSTB,0x1);
+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+ uhs_phy_delay_us(50);
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x0);
+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+ uhs_phy_delay_us(50);
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x1);
+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+ uhs_phy_delay_us(50);
+}
+
+void power_up_ldo12uhs(void)
+{
+ // use internal LDO
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_VOUT_SEL,0x5);
+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+ uhs_phy_delay_us(200);
+ // use external LDO
+ // tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN,0x0);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x1);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0);
+ // BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+}
+
+void set_cen_ck_ckn(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xfc);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+ uhs_phy_delay_us(10);
+}
+
+void set_or_uhs(void)
+{
+ uint32_t tmpVal = 0;
+
+ if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+ }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+ }
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,0x8);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,0xB);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,0x7);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,0x7);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,0x6);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,0x6);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_SR,0x2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_SR,0x2);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_P_REG,0x3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_N_REG,0x3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_P_REG,0x3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_N_REG,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0N_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1N_DLY_RX,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+ uhs_phy_delay_us(200);
+}
+
+void switch_to_ldo12uhs(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcc);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+ uhs_phy_delay_us(200);
+}
+
+void release_cen_ck_ckn(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcf);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x3);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+ uhs_phy_delay_us(10);
+}
+
+void uhs_phy_pwr_down(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x0);
+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+ uhs_phy_delay_us(100);
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0);
+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xff);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+ uhs_phy_delay_us(100);
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x0);
+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+ uhs_phy_delay_us(100);
+}
+
+void psram_init(void)
+{
+ uint8_t i;
+ uint32_t tmpVal = 0;
+ for (i = 0; i < 1; i++){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ // if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x1f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+ // }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+ // }
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_LINEAR_BND_B,0xb);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_GLBR_PULSE,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+ uhs_phy_delay_us(100);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ uhs_phy_delay_us(100);
+ }
+
+ // // psram auto refresh at 2000Mbps
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,0x001E0C4);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,0x1007);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,0x01d);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,0x1);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,0x40);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+ // // psram cmd timing < 2000Mbps
+ // BL_WR_WORD(0x3000F030,0x18090610);
+}
+
+void set_uhs_phy_init(void)
+{
+ // set phy & controller
+ uint32_t tmpVal = 0;
+ // default latency(800MHz)
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,0x2);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,0x7);
+ // // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x0);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x1);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,0x2);
+ // // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x1);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x2);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,0x2);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_CTRL_HW,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x05000501);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x02080108);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x03e90b0b);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x040b0308);
+ }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x09020303);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x040c0313);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x07d11515);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x060f050c);
+ }
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_CEN_ANA,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+ uhs_phy_delay_us(100);
+}
+
+void set_uhs_phy(void)
+{
+ uint32_t tmpVal = 0;
+ // set phy & controller
+ // latency code=3 (1066MHz)
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a1323); // if fail than use 0x0f391323
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a0313); // tDQSS -> -1
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a3233); // tDQSS -> 1
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_CTRL_HW,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ set_uhs_latency_w(latency_wr[0]);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x0b030404);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x050e0418);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x0a6a1c1c);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x07110710);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,0x01333333);
+
+ uhs_phy_delay_us(100);
+}
+
+uint8_t uhs_err_handler(uint8_t err)
+{
+ err_flag = 1;
+ uhs_phy_cal_res->err_type = err;
+#ifndef BFLB_BOOT2
+ switch (err) {
+ case UHS_REGR_GNT_ERR:
+ uhs_phy_printfe("UHS_REGR_GNT_ERR\r\n");
+ break;
+ case UHS_REGR_DONE_ERR:
+ uhs_phy_printfe("UHS_REGR_DONE_ERR = %d\r\n",regr_done_err);
+ uhs_phy_cal_res->err_sub_type = regr_done_err;
+ break;
+ case UHS_REGW_GNT_ERR:
+ uhs_phy_printfe("UHS_REGW_GNT_ERR\r\n");
+ break;
+ case UHS_REGW_DONE_ERR:
+ uhs_phy_printfe("UHS_REGW_DONE_ERR\r\n");
+ break;
+ case UHS_LATENCY_CODE_WRITE_ERR:
+ uhs_phy_printfe("UHS_LATENCY_CODE_WRITE_ERR\r\n");
+ break;
+ case UHS_INIT_ARRAY_WRITE_ERR:
+ uhs_phy_printfe("UHS_INIT_ARRAY_WRITE_ERR = %d\r\n",init_array_write_err);
+ uhs_phy_cal_res->err_sub_type = init_array_write_err;
+ break;
+ case UHS_REG_READ_CAL_ERR:
+ uhs_phy_printfe("UHS_REG_READ_CAL_ERR = %d\r\n",reg_read_err);
+ uhs_phy_cal_res->err_sub_type = reg_read_err;
+ break;
+ case UHS_REG_WRITE_CAL_ERR:
+ uhs_phy_printfe("UHS_REG_WRITE_CAL_ERR = %d\r\n",reg_write_err);
+ uhs_phy_cal_res->err_sub_type = reg_write_err;
+ break;
+ case UHS_ARRAY_READ_LAT_ERR:
+ uhs_phy_printfe("UHS_ARRAY_READ_LAT_ERR = %d\r\n",array_read_err);
+ uhs_phy_cal_res->err_sub_type = array_read_err;
+ break;
+ case UHS_ARRAY_WRITE_CK_ERR:
+ uhs_phy_printfe("UHS_ARRAY_WRITE_CK_ERR\r\n");
+ break;
+ case UHS_ARRAY_READ_CAL_ERR:
+ uhs_phy_printfe("UHS_ARRAY_READ_CAL_ERR\r\n");
+ break;
+ case UHS_ARRAY_WRITE_CAL_ERR:
+ uhs_phy_printfe("UHS_ARRAY_WRITE_CAL_ERR\r\n");
+ break;
+ case UHS_CACHE_ENABLE_ERR:
+ uhs_phy_printfe("UHS_CACHE_ENABLE_ERR\r\n");
+ break;
+ case UHS_CACHE_DISABLE_ERR:
+ uhs_phy_printfe("UHS_CACHE_DISABLE_ERR\r\n");
+ break;
+ case UHS_CACHE_RECOVER_ERR:
+ uhs_phy_printfe("UHS_CACHE_RECOVER_ERR\r\n");
+ break;
+ case UHS_REG_WRITE_2kM_ERR:
+ uhs_phy_printfe("UHS_REG_WRITE_2kM_ERR\r\n");
+ break;
+ case UHS_BAD_DIE_ERR:
+ uhs_phy_printfe("UHS_BAD_DIE_ERR\r\n");
+ break;
+ case UHS_DIAGONAL_TEST_ERR:
+ uhs_phy_printfe("UHS_DIAGONAL_TEST_ERR\r\n");
+ break;
+ case UHS_ALL_ADDR_TEST_ERR:
+ uhs_phy_printfe("UHS_ALL_ADDR_TEST_ERR\r\n");
+ break;
+ default:
+ break;
+ }
+ uhs_phy_printfe("ERR_AT %ldMbps\r\n",cfg_glb->pck_freq);
+ uhs_phy_reg_dump();
+#else
+ uhs_phy_printfe("uhs_err_handler:%d\r\n",err);
+#endif
+ #if CAL_MODE == 0 || CAL_MODE == 1
+ while(1){
+ uhs_phy_printfe("%d",err);
+ uhs_phy_delay_ms(10000);
+ };
+ #endif
+ return err_flag;
+}
+
+void uhs_phy_reg_dump(void){
+ uint32_t len = 0x150;
+ uint32_t i = 0;
+
+ // uhs_phy_printf_debug("UHS_PHY_REG_DUMP_START\r\n");
+ // for(i = 0;i <= len;i = i+4){
+ // uhs_phy_printf_debug("0x%lx,0x%lx\r\n",(addr_dump + i),*((volatile uint32_t*)(addr_dump + i)));
+ // }
+ // uhs_phy_printf_debug("UHS_PHY_REG_DUMP_END\r\n");
+ uhs_phy_printfe("UHS_PHY_REG_DUMP_START\r\n");
+ for(i = 0;i <= len;i = i+4){
+ uhs_phy_printfe("0x%lx,0x%lx\r\n",(addr_dump + i),*((volatile uint32_t*)(addr_dump + i)));
+ }
+ uhs_phy_printfe("UHS_PHY_REG_DUMP_END\r\n");
+}
+
+uint8_t uhs_reg_w(uint32_t uhs_latency,uint32_t uhs_drive,uint32_t ma,uint32_t BL_32)
+{
+ uint32_t tmpVal = 0;
+ uint32_t count = 0;
+ if(ma == 0)
+ {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_LATENCY,uhs_latency);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DRIVE_ST,uhs_drive);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal);
+ }
+ else if(ma == 2)
+ {
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE);
+ if (BL_32 == 1){
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0);
+ }else if (BL_32 == 2){
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x1);
+ }else{
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x0);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0);
+ }
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal);
+ }
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ // uhs_phy_printf_debug("reg_w GNT while\r\n");
+ while (1)
+ {
+ if (count == 100000){
+ return uhs_err_handler(UHS_REGW_GNT_ERR);
+ }
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT);
+ if (tmpVal == 1)
+ {
+ uhs_phy_printf_debug("reg_w GNT pass\r\n");
+ break;
+ }
+ count ++;
+ }
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1); //reg_regw_pulse
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+
+ count = 0;
+ while (1)
+ {
+ if (count == 100000){
+ return uhs_err_handler(UHS_REGW_DONE_ERR);
+ }
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGW_DONE); //regw_done
+ if (tmpVal == 1)
+ {
+ uhs_phy_printf_debug("reg_w DONE pass\r\n");
+ break;
+ }
+ count ++;
+ }
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ uhs_phy_delay_us(10);
+
+ return 0;
+}
+
+uint8_t uhs_reg_r(uint32_t ma,uint8_t flag)
+{
+ uint32_t tmpVal = 0;
+ // uint32_t tmpInd = 0;
+ uint32_t count = 0;
+ uint8_t opc = 1;
+
+ if (flag == 1){
+ uhs_phy_af_onoff(0);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_FORCE_FSM,0x1);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+ uhs_phy_delay_us(50);
+ }
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+ while (1)
+ {
+ if (count == 100000){
+ return uhs_err_handler(UHS_REGR_GNT_ERR);
+ }
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT);
+ if (tmpVal == 1)
+ {
+ uhs_phy_printf_debug("reg_r GNT pass\r\n");
+ break;
+ }
+ count ++;
+ }
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGR_PULSE,0x1); //reg_regr_pulse
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+
+ count = 0;
+ while (1)
+ {
+ if (flag == 1){
+ if (count == 100){
+ regr_done_err = 2;
+ return uhs_err_handler(UHS_REGR_DONE_ERR);
+ }
+ uhs_phy_delay_us(20);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); //regr_done
+ if (tmpVal == 1){
+ uhs_phy_printf_debug("reg_r DONE pass\r\n");
+ break;
+ }
+ count ++;
+
+ // if (tmpVal == 1){
+ // uhs_phy_printf_debug("reg_r DONE pass\r\n");
+ // opc = 1;
+ // }else{
+ // uhs_phy_printf_debug("reg_r DONE fail\r\n");
+ // opc = 0;
+ // }
+ // break;
+ }
+ else{
+ if (count == 100000){
+ regr_done_err = 1;
+ return uhs_err_handler(UHS_REGR_DONE_ERR);
+ }
+ uhs_phy_delay_us(10);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); //regr_done
+ if (tmpVal == 1){
+ uhs_phy_printf_debug("reg_r DONE pass\r\n");
+ break;
+ }
+ count ++;
+ }
+ }
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+ if (opc == 0){
+ uhs_reset(0);
+ }
+
+ if (flag == 1){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_FORCE_FSM,0x0);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+ uhs_phy_delay_us(50);
+
+ uhs_phy_af_onoff(1);
+ }
+
+ uhs_phy_delay_us(10);
+ return opc;
+}
+
+
+void cfg_dq_rx(uint8_t dq){
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+ uhs_phy_delay_us(10);
+}
+
+void cfg_dqs_rx(uint8_t dqs){
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,dqs);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,dqs);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+ uhs_phy_delay_us(10);
+}
+
+void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv){
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,array_ck_dly_drv);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,array_cen_dly_drv);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);
+ uhs_phy_delay_us(50);
+}
+
+void uhs_reset(uint8_t ma_rb)
+{
+ // uint32_t tmpVal = 0;
+ // uint32_t len = 0x150;
+ // uint32_t val_sr[len>>2];
+ // int32_t i = 0;
+
+ uhs_phy_printf("IN_UHS_RESET\r\n");
+
+ // for( i = len ; i >= 0 ; i = i-4 ){
+ // if( i != 0x4 ){
+ // val_sr[i>>2] = *((volatile uint32_t*)(addr_dump + i));
+ // }
+ // }
+
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0);
+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ // uhs_phy_delay_us(100);
+
+ // tmpVal = BL_RD_WORD(0x30007044);
+ // tmpVal = tmpVal | 0x00008000;
+ // BL_WR_WORD(0x30007044,tmpVal);
+ // uhs_phy_delay_us(100);
+ // tmpVal = tmpVal & 0xFFFF7FFF;
+ // BL_WR_WORD(0x30007044,tmpVal);
+ // uhs_phy_delay_us(200);
+
+ // BL_WR_WORD(0x3000F030,0x18090610);
+
+ // #if PSRAM_32MB
+ // PSRAM_UHS_Cfg_Type psramCfg = {
+ // datarate,
+ // PSRAM_MEM_SIZE_32MB,
+ // PSRAM_PAGE_SIZE_2KB,
+ // 0,
+ // };
+ // #else
+ // PSRAM_UHS_Cfg_Type psramCfg = {
+ // datarate,
+ // PSRAM_MEM_SIZE_64MB,
+ // PSRAM_PAGE_SIZE_2KB,
+ // 0,
+ // };
+ // #endif
+ // Psram_UHS_Init_Override(cfg_glb); //controller init
+
+ // set_or_uhs();
+ // set_uhs_phy();
+
+ // for( i = len ; i >= 0 ; i = i-4 ){
+ // if( i != 0x4 ){
+ // *((volatile uint32_t*)(addr_dump + i)) = val_sr[i>>2];
+ // }
+ // }
+ // uhs_phy_delay_us(400);
+
+ if (ma_rb){
+ mr_read_back();
+ }else{
+ power_up_mm(1);
+ uhs_phy_pwr_down();
+ latency_wr_2kM[1] --;
+ uhs_phy_init_core(cfg_glb);
+ }
+
+ uhs_phy_printf("OUT_UHS_RESET\r\n");
+}
+
+void set_uhs_latency_r(uint32_t uhs_latency)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ uhs_phy_delay_us(50);
+}
+
+void set_uhs_latency_w(uint32_t uhs_latency)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,uhs_latency%4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,uhs_latency/4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,(uhs_latency+1)%4);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,(uhs_latency+1)/4);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ uhs_phy_delay_us(50);
+}
+
+uint8_t mr_read_back(void)
+{
+ uint8_t cnt1;
+ uint32_t tmpVal;
+ for (cnt1=0;cnt1<=4;cnt1++){
+ if(cnt1 != 3){
+ CHECK_ERR_FLAG(uhs_reg_r,(cnt1,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf("MA%d = 0x%lx\r\n",cnt1,tmpVal);
+ }
+ }
+ return 0;
+}
+
+uint8_t reg_read_cal(void)
+{
+ uint32_t tmpVal = 0;
+ uint32_t tmpVal_1 = 1;
+ uint32_t uhs_latency = 42;
+ int32_t i = 0;
+ uint8_t dqs_dq_flag = 0;
+ uint32_t reg_dqs = 0;
+ uint32_t reg_dq = 0;
+
+ // for(uhs_latency = 41; uhs_latency > 0; uhs_latency --)
+ for(uhs_latency = latency_wr_2kM[1]; uhs_latency > 0; uhs_latency --)
+ {
+ if(uhs_latency == 34)
+ {
+ reg_read_err = 1;
+ return uhs_err_handler(UHS_REG_READ_CAL_ERR);
+ }
+ uhs_phy_printf_debug("reg read cal 1st by latency= %ld\r\n",uhs_latency);
+ set_uhs_latency_r(uhs_latency);
+
+ // sweep dqs
+ cfg_dq_rx(0);
+ for(i = 15; i >= 0; i --)
+ {
+ cfg_dqs_rx(i);
+ // tmpVal_1 = uhs_reg_r(0,1);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+ if (cal_done_flag == 1)
+ return 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 1st dqs--, 0x%lx\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code) && (tmpVal_1 == 1)){
+ uhs_phy_printf_debug("reg read pass by dqs= %ld\r\n",i);
+ // reg_dqs = i;
+ dqs_dq_flag = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg read fail by dqs= %ld\r\n",i);
+ }
+ // if(tmpVal_1 == 0){
+ // uhs_phy_printf_debug("read done not found!!!\r\n");
+ // // uhs_reset(datarate);
+ // set_uhs_latency_r(uhs_latency);
+ // cfg_dq_rx(0);
+ // }
+ }
+
+ // sweep dq
+ cfg_dqs_rx(0);
+ for(i = 15; i >=0; i --)
+ {
+ cfg_dq_rx(i);
+ // tmpVal_1 = uhs_reg_r(0,1);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+ if (cal_done_flag == 1)
+ return 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 1st dq--, 0x%lx\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code) && (tmpVal_1 == 1)){
+ uhs_phy_printf_debug("reg read pass by dq= %ld\r\n",i);
+ // reg_dq = i;
+ dqs_dq_flag = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg read fail by dq= %ld\r\n",i);
+ }
+ // if(tmpVal_1 == 0){
+ // uhs_phy_printf_debug("read done not found!!!\r\n");
+ // // uhs_reset(datarate);
+ // set_uhs_latency_r(uhs_latency);
+ // cfg_dqs_rx(0);
+ // }
+ }
+ if (dqs_dq_flag == 1){
+ dqs_dq_flag = 0;
+
+ uhs_latency = uhs_latency - 2;
+ uhs_phy_printf_debug("reg read cal 2nd by latency= %ld\r\n",uhs_latency);
+ set_uhs_latency_r(uhs_latency); //got a good robust uhs_latency
+ latency_wr[1] = uhs_latency;
+ //******verify the uhs_latency and get dqs/dq timing
+ //sweep dqs
+ cfg_dq_rx(0);
+ for(i = 15; i >= 0; i --)
+ {
+ cfg_dqs_rx(i);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dqs--, 0x%lx\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code))
+ {
+ uhs_phy_printf("reg read pass by --dqs= %ld\r\n",i);
+ reg_dqs += i;
+ dqs_dq_flag = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg read fail by dqs= %ld\r\n",i);
+ }
+ }
+ for(i = 0; i <= 15; i ++)
+ {
+ cfg_dqs_rx(i);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dqs++, 0x%lx\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code))
+ {
+ uhs_phy_printf("reg read pass by ++dqs= %ld\r\n",i);
+ reg_dqs += i;
+ dqs_dq_flag = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg read fail by dqs= %ld\r\n",i);
+ }
+ }
+ // sweep dq
+ cfg_dqs_rx(0);
+ for(i = 15; i >= 0; i --)
+ {
+ cfg_dq_rx(i);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dq--, 0x%lx\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code))
+ {
+ uhs_phy_printf("reg read pass by --dq= %ld\r\n",i);
+ reg_dq += i;
+ dqs_dq_flag = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg read fail by dq= %ld\r\n",i);
+ }
+ }
+ for(i = 0; i <= 15; i ++)
+ {
+ cfg_dq_rx(i);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dq++, 0x%lx\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code))
+ {
+ uhs_phy_printf("reg read pass by ++dq= %ld\r\n",i);
+ reg_dq += i;
+ dqs_dq_flag = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg read fail by dq= %ld\r\n",i);
+ }
+ }
+
+ if(dqs_dq_flag == 0)
+ {
+ reg_read_err = 2;
+ return uhs_err_handler(UHS_REG_READ_CAL_ERR);
+ }
+
+ if(reg_dqs >= reg_dq)
+ {
+ reg_dqs = (reg_dqs-reg_dq)/2;
+ reg_dq = 0;
+ }
+ else
+ {
+ reg_dq = (reg_dq-reg_dqs)/2;
+ reg_dqs = 0;
+ }
+
+ // set dqs & dq by register read calibration result
+ cfg_dqs_rx(reg_dqs);
+ cfg_dq_rx(reg_dq);
+ CHECK_ERR_FLAG(mr_read_back,());
+ uhs_phy_printf("reg_read_cal pass, latency= %ld, dqs= %ld, dq= %ld\r\n",uhs_latency,reg_dqs,reg_dq);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+void cfg_dq_drv(uint32_t dq){
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,dq);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,dq);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+ // uhs_phy_delay_us(10);
+}
+
+void cfg_dqs_drv(uint32_t dqs){
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,dqs);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,dqs);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+ uhs_phy_delay_us(10);
+}
+
+uint8_t reg_write_cal(void) //only need sweep dqs
+{
+ uint32_t tmpVal = 0;
+ // uint32_t tmpVal_1 = 0;
+ int32_t i = 0;
+ uint32_t reg_dqs;
+ uint32_t reg_dq = 0;
+ uint32_t reg_dqs1 = 0;
+ uint32_t reg_dqs2 = 0;
+ uint8_t dqs_dq_flag1 = 0;
+ uint8_t dqs_dq_flag2 = 0;
+ // reg_write_err = 0;
+
+ // sweep1 dqs
+ for(i = 15; i >=0; i --)
+ {
+ cfg_dqs_drv(i);
+ CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,1)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==1
+ CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ if(tmpVal == (16 + 32))
+ {
+ uhs_phy_printf("reg write pass by -- dqs1= %ld\r\n",i);
+ reg_dqs1 = i;
+ dqs_dq_flag1 = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg write fail by -- dqs1= %ld\r\n",i);
+ }
+ }
+ // sweep2 dqs
+ for(i = 0; i <=15; i ++)
+ {
+ cfg_dqs_drv(i);
+ CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,2)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==0,BL_64==1
+ CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ if(tmpVal == (8 + 16))
+ {
+ uhs_phy_printf("reg write pass by ++ dqs2= %ld\r\n",i);
+ reg_dqs2 = i;
+ dqs_dq_flag2 = 1;
+ break;
+ }
+ else{
+ uhs_phy_printf_debug("reg write fail by ++ dqs2= %ld\r\n",i);
+ }
+ }
+
+ if(dqs_dq_flag1 == 1 && dqs_dq_flag2 == 1){
+ reg_dqs = (reg_dqs1 + reg_dqs2) / 2 ;
+ }else if(dqs_dq_flag1 == 1 && dqs_dq_flag2 == 0){
+ reg_dqs = reg_dqs1;
+ }else if(dqs_dq_flag1 == 0 && dqs_dq_flag2 == 1){
+ reg_dqs = reg_dqs2;
+ }
+ else{
+ reg_write_err = 1;
+ return uhs_err_handler(UHS_REG_WRITE_CAL_ERR);
+ }
+
+ // if ck_dly_drv = 4, fix reg_dqs to 0
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+ tmpVal = (tmpVal >> 16) & 0xF;
+ if(tmpVal == 4){
+ reg_dqs = 0;
+ }
+ // set dqs by register write cal result
+ cfg_dqs_drv(reg_dqs);
+ CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,0)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==1
+ CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ if(tmpVal == 0){
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+ reg_dq = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV);
+ uhs_phy_printf("reg write cal pass dqs= %ld, dq= %ld\r\n",reg_dqs,reg_dq);
+ }
+ else{
+ reg_write_err = 2;
+ return uhs_err_handler(UHS_REG_WRITE_CAL_ERR);
+ }
+
+ dqs_dq_delta = 16 + reg_dqs - reg_dq;
+ uhs_phy_printf("reg_write_cal return dqs_dq_delta= %ld\r\n",dqs_dq_delta);
+
+ return 0;
+}
+
+void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1)
+{
+ uint32_t addr_tmp = addr;
+ uint32_t data = data0;
+ uint32_t i = 0;
+
+ if (print_flag){
+ uhs_phy_printf("IN_ARRAY_WRITE_FIX\r\n");
+ }
+ for(i = 0; i < (len>>2); i ++)
+ {
+ addr_tmp = (i << 2) + addr;
+ if((i % 2) == 0)
+ data = data0 + i;
+ else
+ data = data1 + i;
+
+ BL_WR_WORD(addr_tmp,data);
+ }
+ if (print_flag){
+ uhs_phy_printf("BEFORE CACHE FUCNTION\r\n");
+ }
+ if (cache_state){
+ // #if CACHE_EN
+ __DSB();
+ __ISB();
+ L1C_DCache_Clean_Invalid_All();
+ __DSB();
+ __ISB();
+ // #endif
+ }
+ uhs_phy_delay_us(10);
+ if (print_flag){
+ uhs_phy_printf("OUT_ARRAY_WRITE_FIX\r\n");
+ }
+}
+
+uint8_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1)
+{
+ uint8_t array_read_pass = 1;
+ uint32_t addr_tmp = addr;
+ uint32_t data = data0;
+ uint32_t data_read = 0;
+ uint32_t i = 0;
+
+ if (print_flag){
+ uhs_phy_printf("IN_ARRAY_READ_FIX\r\n");
+ }
+ for(i = 0; i < (len>>2); i ++)
+ {
+ // data_read = 0;
+ // data_read += *((volatile uint8_t *)(addr+(i<<2)+3));
+ // data_read <<= 8;
+ // data_read += *((volatile uint8_t *)(addr+(i<<2)+2));
+ // data_read <<= 8;
+ // data_read += *((volatile uint8_t *)(addr+(i<<2)+1));
+ // data_read <<= 8;
+ // data_read += *((volatile uint8_t *)(addr+(i<<2)+0));
+
+ addr_tmp = (i << 2) + addr;
+ data_read = BL_RD_WORD(addr_tmp);
+ if((i % 2) == 0)
+ data = data0 + i;
+ else
+ data = data1 + i;
+
+ if (print_flag && i == 0){
+ uhs_phy_printf("addr 0x%lx, write_val 0x%lx, read_val 0x%lx\r\n",addr_tmp,data,data_read);
+ }
+ if(data_read != data){
+ array_read_pass = 0;
+ uhs_phy_printf("addr 0x%lx, write_val 0x%lx, read_val error 0x%lx\r\n",addr_tmp,data,data_read);
+ break;
+ }
+ }
+ if (print_flag){
+ uhs_phy_printf("BEFORE CACHE FUCNTION\r\n");
+ }
+ if (cache_state){
+ // #if CACHE_EN
+ __DSB();
+ __ISB();
+ L1C_DCache_Clean_Invalid_All();
+ __DSB();
+ __ISB();
+ // #endif
+ }
+ uhs_phy_delay_us(10);
+ if (print_flag){
+ uhs_phy_printf("OUT_ARRAY_READ_FIX\r\n");
+ }
+ return array_read_pass;
+}
+
+void set_ck_dly_drv(uint32_t array_ck_dly_drv)
+{
+ uint32_t array_dqx_dly_drv = 0;
+ uint32_t array_dqsx_dly_drv = 0;
+ uint32_t array_cen_dly_drv = 0;
+
+ uhs_phy_delay_us(10); // ck modify need time
+
+ array_dqx_dly_drv = (array_ck_dly_drv >=4) ? (array_ck_dly_drv-4) : 0;
+ array_cen_dly_drv = array_dqx_dly_drv + 1;
+ array_dqx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqx_dly_drv;
+ array_cen_dly_drv = (array_cen_dly_drv > 15) ? 15 : array_cen_dly_drv;
+ array_dqsx_dly_drv = (array_dqsx_dly_drv > 15) ? 15 : array_dqsx_dly_drv;
+
+ cfg_dq_drv(array_dqx_dly_drv);
+ // cfg_dqs_drv(array_dqsx_dly_drv);
+ cfg_ck_cen_drv(array_ck_dly_drv,array_cen_dly_drv);
+ // uhs_phy_printf_debug("array_dqx_dly_drv= %ld,array_dqsx_dly_drv= %ld,array_ck_dly_drv= %ld,array_cen_dly_drv= %ld\r\n",array_dqx_dly_drv,array_dqsx_dly_drv,array_ck_dly_drv,array_cen_dly_drv); //debug
+ // uhs_phy_delay_us(50); // ck modify need time
+}
+
+uint8_t array_read_latency_cal(void)
+{
+ // uint32_t tmpVal = 0;
+ uint32_t uhs_latency = 42;
+ // uint8_t array_ck_dly_drv_val[3] = {15,4,9};
+ uint8_t array_ck_dly_drv_val[3] = {4,9,15};
+ uint8_t ck_i;
+ uint32_t array_ck_dly_drv = 0;
+ int32_t i = 0;
+ uint32_t array_dqs = 0;
+ uint32_t array_dq = 0;
+ uint32_t dqs_flag;
+ uint32_t dq_flag;
+ uint32_t len = 128;
+ uint8_t rwindow = 0;
+
+ for(uhs_latency = latency_wr[1]; uhs_latency > 0; uhs_latency --)
+ {
+ if(uhs_latency == 34)
+ {
+ array_read_err = 1;
+ return uhs_err_handler(UHS_ARRAY_READ_LAT_ERR);
+ }
+
+ uhs_phy_printf_debug("array read cal by latency= %ld\r\n",uhs_latency);
+ set_uhs_latency_r(uhs_latency);
+
+ for (ck_i = 0; ck_i < (sizeof(array_ck_dly_drv_val)/sizeof(array_ck_dly_drv_val[0])); ck_i++){
+ array_ck_dly_drv = array_ck_dly_drv_val[ck_i];
+ set_ck_dly_drv(array_ck_dly_drv);
+ uhs_phy_printf_debug("array read cal by ck= %ld\r\n",array_ck_dly_drv);
+
+ rwindow = 0;
+
+ // sweep dqs
+ cfg_dq_rx(0);
+ for(i = 15; i >= 0; i --)
+ {
+ cfg_dqs_rx(i);
+ dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(dqs_flag == 1)
+ {
+ uhs_phy_printf("array_read_dqs_dq_cal pass by --dqs= %ld\r\n",i);
+ array_dqs += i;
+ rwindow += i;
+ uhs_phy_cal_res->rwindow_end = i;
+ break;
+ }
+ }
+ for(i = 0; i <= 15; i ++)
+ {
+ cfg_dqs_rx(i);
+ dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(dqs_flag == 1)
+ {
+ uhs_phy_printf("array_read_dqs_dq_cal pass by ++dqs= %ld\r\n",i);
+ array_dqs += i;
+ rwindow = (i > 0) ? (rwindow - i) : (rwindow + 1);
+ uhs_phy_cal_res->rwindow_begin = i;
+ break;
+ }
+ }
+ // sweep dq
+ cfg_dqs_rx(0);
+ for(i = 15; i >= 0; i --)
+ {
+ cfg_dq_rx(i);
+ dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(dq_flag == 1)
+ {
+ uhs_phy_printf("array_read_dqs_dq_cal pass by --dq= %ld\r\n",i);
+ array_dq += i;
+ rwindow += i;
+ break;
+ }
+ }
+ for(i = 0; i <= 15; i ++)
+ {
+ cfg_dq_rx(i);
+ dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(dq_flag == 1)
+ {
+ uhs_phy_printf("array_read_dqs_dq_cal pass by ++dq= %ld\r\n",i);
+ array_dq += i;
+ rwindow -= i;
+ break;
+ }
+ }
+
+ if(dqs_flag == 1 || dq_flag == 1){
+ if(array_dqs >= array_dq)
+ {
+ array_dqs = (array_dqs-array_dq)/2;
+ array_dq = 0;
+ }
+ else
+ {
+ #if CAL_MODE == 2
+ array_read_err = 2;
+ return uhs_err_handler(UHS_ARRAY_READ_LAT_ERR);
+ #endif
+ array_dq = (array_dq-array_dqs)/2;
+ array_dqs = 0;
+ }
+ cfg_dq_rx(array_dq);
+ cfg_dqs_rx(array_dqs);
+ uhs_phy_printf("array_read_dqs_dq_cal valid code number= %d\r\n",rwindow);
+ uhs_phy_cal_res->rwindow = rwindow;
+ uhs_phy_cal_res->rdqs = array_dqs;
+ uhs_phy_cal_res->rdq = array_dq;
+ uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs= %ld, array_dq= %ld\r\n",array_dqs,array_dq);
+ break;
+ }
+ }
+ if(dqs_flag == 1 || dq_flag == 1){
+ uhs_phy_cal_res->rl = uhs_latency;
+ uhs_phy_printf("array_read_latency_cal pass, latency= %ld, ck= %ld\r\n",uhs_latency,array_ck_dly_drv);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+uint8_t array_write_ck_cal(void)
+{
+ uint32_t array_ck_dly_drv = 0;
+ uint32_t array_ck_dly_drv1 = 15;
+ uint32_t array_ck_dly_drv2 = 4;
+ uint32_t flag_1 = 0;
+ uint32_t flag_2 = 0;
+ uint32_t len = 1024<<4;
+
+ for(array_ck_dly_drv = 4; array_ck_dly_drv <= 15; array_ck_dly_drv ++)
+ {
+ set_ck_dly_drv(array_ck_dly_drv);
+ flag_2 = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if (flag_2 == 0){
+ uhs_phy_printf("array_write_ck_cal ck++ = %ld, flag_2 = %ld\r\n",array_ck_dly_drv,flag_2);
+ }
+ if(flag_2 == 0 && flag_ck2 == 0){
+ flag_ck2 = 1;
+ uhs_phy_printf("array_write_ck_cal fail by ++ck= %ld\r\n",array_ck_dly_drv);
+ array_ck_dly_drv2 = array_ck_dly_drv;
+ // break;
+ }
+ }
+ if (flag_ck2 == 1)
+ flag_2 = 0;
+ for(array_ck_dly_drv = 15; array_ck_dly_drv >= 4; array_ck_dly_drv --)
+ {
+ set_ck_dly_drv(array_ck_dly_drv);
+ flag_1 = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if (flag_1 == 0){
+ uhs_phy_printf("array_write_ck_cal ck-- = %ld, flag_1 = %ld\r\n",array_ck_dly_drv,flag_1);
+ }
+ if(flag_1 == 0 && flag_ck1 == 0){
+ flag_ck1 = 1;
+ uhs_phy_printf("array_write_ck_cal fail by --ck= %ld\r\n",array_ck_dly_drv);
+ array_ck_dly_drv1 = array_ck_dly_drv;
+ // break;
+ }
+ }
+ if (flag_ck1 == 1)
+ flag_1 = 0;
+
+ if (flag_1 == 0 && flag_2 == 0){
+ if(array_ck_dly_drv1 == 15 && array_ck_dly_drv2 == 4)
+ {
+ return uhs_err_handler(UHS_ARRAY_WRITE_CK_ERR);
+ }
+ else if ((15 - array_ck_dly_drv1) >= (array_ck_dly_drv2 - 4)){
+ array_ck_dly_drv = 15;
+ }
+ else{
+ array_ck_dly_drv = 4;
+ }
+ }
+ else if (flag_1 == 0 && flag_2 == 1){
+ array_ck_dly_drv = (array_ck_dly_drv1 > 9) ? 4 : 15;
+ }else if (flag_1 == 1 && flag_2 == 0){
+ array_ck_dly_drv = (array_ck_dly_drv2 > 9) ? 4 : 15;
+ }
+ else {
+ array_ck_dly_drv = (15 + 4) / 2;
+ }
+
+ set_ck_dly_drv(array_ck_dly_drv);
+ uhs_phy_cal_res->ck = array_ck_dly_drv;
+ uhs_phy_printf("array_write_ck_cal pass, ck= %ld\r\n",array_ck_dly_drv);
+
+ return 0;
+}
+
+uint8_t array_read_dqs_dq_cal(void)
+{
+ int32_t i = 0;
+ uint32_t array_dqs = 0;
+ uint32_t array_dq = 0;
+ uint32_t dqs_flag;
+ uint32_t dq_flag;
+ uint32_t len = 128;
+
+ // sweep dqs
+ cfg_dq_rx(0);
+
+ for(i = 15; i >= 0; i --)
+ {
+ cfg_dqs_rx(i);
+ dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(dqs_flag == 1)
+ {
+ uhs_phy_printf("array_read_dqs_dq_cal pass by dqs= %ld\r\n",i);
+ array_dqs = i;
+ break;
+ }
+ }
+ // sweep dq
+ cfg_dqs_rx(0);
+ for(i = 15; i >=0; i --)
+ {
+ cfg_dq_rx(i);
+ dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(dq_flag == 1)
+ {
+ uhs_phy_printf("array_read_dqs_dq_cal pass by dq= %ld\r\n",i);
+ array_dq = i;
+ break;
+ }
+ }
+ if(dqs_flag == 0 && dq_flag == 0)
+ {
+ return uhs_err_handler(UHS_ARRAY_READ_CAL_ERR);
+ }
+ if(array_dqs > array_dq)
+ {
+ array_dqs = (array_dqs-array_dq)/2;
+ array_dq = 0;
+ }
+ else
+ {
+ array_dq = (array_dq-array_dqs)/2;
+ array_dqs = 0;
+ }
+ cfg_dq_rx(array_dq);
+ cfg_dqs_rx(array_dqs);
+ uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs= %ld, array_dq= %ld\r\n",array_dqs,array_dq);
+
+ return 0;
+}
+
+uint8_t array_write_dqs_dq_cal(void)
+{
+ uint32_t tmpVal = 0;
+ int32_t i = 0;
+ uint32_t dqs_flag1 = 0;
+ uint32_t dqs_flag2 = 0;
+ uint32_t array_dqs_dly_drv = 0;
+ uint32_t array_dqs_dly_drv1 = 0;
+ uint32_t array_dqs_dly_drv2 = 0;
+
+ uint32_t addr = 0x50000000;
+ uint32_t len = 128;
+ uint32_t data0 = 0x23456789;
+ uint32_t data1 = 0x98765432;
+
+ uint8_t wwindow = 0;
+
+ for(i = 15; i >= 0; i --)
+ {
+ cfg_dqs_drv(i);
+ array_write_fix(addr,len,data0,data1);
+ dqs_flag1 = array_read_fix(addr,len,data0,data1);
+ if(dqs_flag1 == 1)
+ {
+ uhs_phy_printf("array_write_dqs_dq_cal pass by -- dqs1= %ld\r\n",i);
+ array_dqs_dly_drv1 = i;
+ uhs_phy_cal_res->wwindow_end = i;
+ break;
+ }
+ else
+ {
+ uhs_phy_printf_debug("array_write_dqs_dq_cal fail by -- dqs1= %ld\r\n",i);
+ }
+ }
+ for(i = 0; i <= 15; i ++)
+ {
+ cfg_dqs_drv(i);
+ array_write_fix(addr,len,data1,data0);
+ dqs_flag2 = array_read_fix(addr,len,data1,data0);
+ if(dqs_flag2 == 1)
+ {
+ uhs_phy_printf("array_write_dqs_dq_cal pass by ++ dqs2= %ld\r\n",i);
+ array_dqs_dly_drv2 = i;
+ uhs_phy_cal_res->wwindow_begin = i;
+ break;
+ }
+ else
+ {
+ uhs_phy_printf_debug("array_write_dqs_dq_cal fail by ++ dqs2= %ld\r\n",i);
+ }
+ }
+
+ if(dqs_flag1 == 1 && dqs_flag2 == 1)
+ {
+ array_dqs_dly_drv = (array_dqs_dly_drv1 + array_dqs_dly_drv2) / 2 ;
+ }
+ else if(dqs_flag1 == 1 && dqs_flag2 == 0){
+ array_dqs_dly_drv = array_dqs_dly_drv1;
+ }else if(dqs_flag1 == 0 && dqs_flag2 == 1){
+ array_dqs_dly_drv = array_dqs_dly_drv2;
+ }else{
+ return uhs_err_handler(UHS_ARRAY_WRITE_CAL_ERR);
+ }
+
+ //debug
+ // array_dqs_dly_drv = 4;
+
+ // if ck_dly_drv = 4, fix dqsx_dly_drv to 0
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+ tmpVal = (tmpVal >> 16) & 0xF;
+ if(tmpVal == 4){
+ array_dqs_dly_drv = 0;
+ uhs_phy_cal_res->wwindow_begin = 0;
+ }
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV);
+
+ wwindow = (array_dqs_dly_drv > 0) ? (array_dqs_dly_drv1 - array_dqs_dly_drv2 + 1) : (array_dqs_dly_drv1 - 0 + 1);
+ uhs_phy_printf("array_write_dqs_dq_cal valid code number= %d\r\n",wwindow);
+ uhs_phy_cal_res->wwindow = wwindow;
+ uhs_phy_cal_res->wdqs = array_dqs_dly_drv;
+ uhs_phy_cal_res->wdq = tmpVal;
+ uhs_phy_printf("array_write_dqs_dq_cal pass by array_dqs_dly_drv= %ld,array_dq_dly_drv= %ld\r\n",array_dqs_dly_drv,tmpVal);
+ // set dqs by register write cal result
+ cfg_dqs_drv(array_dqs_dly_drv);
+
+ return 0;
+}
+
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq)
+{
+ uint32_t xtalFreq = 0;
+ uint32_t factor = 0;
+ GLB_MU_PLL_CFG_BASIC_Type uhsPllMCfg = {
+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */
+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */
+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */
+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */
+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */
+ };
+ GLB_MU_PLL_Cfg_Type uhsPllCfg[GLB_XTAL_MAX] = {
+ { NULL, 0x0 }, /*!< XTAL is None */
+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 24M */
+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 32M */
+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 38.4M */
+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 40M */
+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 26M */
+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is RC32M */
+ };
+ GLB_PLL_REF_CLK_Type refClk;
+
+ /* calc clkpllRefdivRatio */
+ switch(xtalType){
+ case GLB_XTAL_NONE:
+ return ERROR;
+ case GLB_XTAL_24M:
+ xtalFreq = 240;
+ uhsPllMCfg.clkpllRefdivRatio = 1;
+ break;
+ case GLB_XTAL_32M:
+ xtalFreq = 320;
+ uhsPllMCfg.clkpllRefdivRatio = 2;
+ break;
+ case GLB_XTAL_38P4M:
+ xtalFreq = 384;
+ uhsPllMCfg.clkpllRefdivRatio = 2;
+ break;
+ case GLB_XTAL_40M:
+ xtalFreq = 400;
+ uhsPllMCfg.clkpllRefdivRatio = 2;
+ break;
+ case GLB_XTAL_26M:
+ xtalFreq = 260;
+ uhsPllMCfg.clkpllRefdivRatio = 1;
+ break;
+ case GLB_XTAL_RC32M:
+ xtalFreq = 320;
+ uhsPllMCfg.clkpllRefdivRatio = 2;
+ break;
+ default :
+ break;
+ }
+ /* calc clkpllSelSampleClk */
+ factor = pllFreq*20480/(xtalFreq/uhsPllMCfg.clkpllRefdivRatio);
+ if(factor<32*2048){
+ uhsPllMCfg.clkpllSelSampleClk = 0;
+ }else if(factor<64*2048){
+ uhsPllMCfg.clkpllSelSampleClk = 1;
+ }else if(factor<128*2048){
+ uhsPllMCfg.clkpllSelSampleClk = 2;
+ }else{
+ uhsPllMCfg.clkpllSelSampleClk = 2;
+ }
+ /* calc clkpllVcoSpeed */
+ if(pllFreq<800){
+ uhsPllMCfg.clkpllVcoSpeed = 1;
+ }else if(pllFreq<1000){
+ uhsPllMCfg.clkpllVcoSpeed = 2;
+ }else if(pllFreq<1200){
+ uhsPllMCfg.clkpllVcoSpeed = 3;
+ }else if(pllFreq<1500){
+ uhsPllMCfg.clkpllVcoSpeed = 4;
+ }else if(pllFreq<1700){
+ uhsPllMCfg.clkpllVcoSpeed = 5;
+ }else if(pllFreq<1900){
+ uhsPllMCfg.clkpllVcoSpeed = 6;
+ }else if(pllFreq<2200){
+ uhsPllMCfg.clkpllVcoSpeed = 7;
+ }else{
+ uhsPllMCfg.clkpllVcoSpeed = 8;
+ }
+ /* calc clkpllEvenDivRatio */
+ uhsPllMCfg.clkpllEvenDivRatio = pllFreq/50;
+ /* calc clkpllSdmin */
+ uhsPllCfg[GLB_XTAL_24M].clkpllSdmin = factor;
+ uhsPllCfg[GLB_XTAL_32M].clkpllSdmin = factor;
+ uhsPllCfg[GLB_XTAL_38P4M].clkpllSdmin = factor;
+ uhsPllCfg[GLB_XTAL_40M].clkpllSdmin = factor;
+ uhsPllCfg[GLB_XTAL_26M].clkpllSdmin = factor;
+ uhsPllCfg[GLB_XTAL_RC32M].clkpllSdmin = factor;
+
+ if (xtalType == GLB_XTAL_RC32M) {
+ refClk = GLB_PLL_REFCLK_RC32M;
+ } else {
+ refClk = GLB_PLL_REFCLK_XTAL;
+ }
+
+ // GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);
+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);
+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(uhsPllCfg[xtalType]), 1);
+
+ return SUCCESS;
+}
+
+uint8_t init_reg_write(void){
+ uint32_t tmpVal = 0;
+ uint8_t wl_i;
+ uint32_t wl;
+ uint32_t wdqs;
+ // uint8_t wdq_val[3] = {0,11,5};
+ uint8_t wdq_val[3] = {0,5,11};
+ uint8_t wdq_i;
+ uint32_t wdq;
+ uint32_t rl;
+ uint32_t rdqs;
+ uint32_t rdq;
+ uint8_t rl_i;
+ uint8_t wl_val_32[6] = {1,0,2,3,4,5};
+ uint8_t rl_val_32[5] = {36,37,38,39,40};
+ uint8_t wl_val_64[6] = {9,8,10,7,11,6};
+ uint8_t rl_val_64[5] = {36,37,38,39,40};
+ uint8_t wl_val[6];
+ uint8_t rl_val[5];
+
+ if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+ wl_val[wl_i] = wl_val_32[wl_i];
+ }
+ for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){
+ rl_val[rl_i] = rl_val_32[rl_i];
+ }
+ }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+ wl_val[wl_i] = wl_val_64[wl_i];
+ }
+ for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){
+ rl_val[rl_i] = rl_val_64[rl_i];
+ }
+ }
+
+ // set to 2000Mbps
+ for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){
+ rl = rl_val[rl_i];
+ set_uhs_latency_r(rl);
+ for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+ wl = wl_val[wl_i];
+ latency_wr[0] = wl;
+ set_uhs_latency_w(wl);
+ for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){
+ wdq = wdq_val[wdq_i];
+ cfg_dq_drv(wdq);
+ cfg_ck_cen_drv(wdq + 4,wdq + 1);
+ for (wdqs = 0; wdqs <= 15; wdqs++){
+ cfg_dqs_drv(wdqs);
+ set_uhs_phy_init();
+ CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,0,0)); //uhs_latency_code==3,uhs_drive==2,ma==0,BL_32==0
+ set_uhs_phy();
+ rdq = 0;
+ cfg_dq_rx(rdq);
+ for (rdqs = 0; rdqs <= 15; rdqs++){
+ cfg_dqs_rx(rdqs);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 = 0x%lx, rdqs++\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code)){
+ uhs_phy_printf("LATENCY_CODE_WRITE_SUCCESS, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ return 0;
+ }
+ else{
+ uhs_phy_printf_debug("LATENCY_CODE_WRITE_FAIL, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ }
+ }
+ rdqs = 0;
+ cfg_dqs_rx(rdqs);
+ for (rdq = 0; rdq <= 15; rdq++){
+ cfg_dq_rx(rdq);
+ CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 = 0x%lx, rdq++\r\n",tmpVal);
+ if(tmpVal == ((2<<3)+uhs_latency_code)){
+ uhs_phy_printf("LATENCY_CODE_WRITE_SUCCESS, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ return 0;
+ }
+ else{
+ uhs_phy_printf_debug("LATENCY_CODE_WRITE_FAIL, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ }
+ }
+ }
+ }
+ }
+ }
+ return uhs_err_handler(UHS_LATENCY_CODE_WRITE_ERR);
+}
+
+uint8_t init_array_write(void){
+ uint8_t wl_val[6] = {13,12,14,11,15,10};
+ uint8_t wl_i;
+ uint32_t wl;
+ uint32_t wdqs;
+ // uint8_t wdq_val[3] = {0,11,5};
+ uint8_t wdq_val[3] = {0,5,11};
+ uint8_t wdq_i;
+ uint32_t wdq;
+ uint32_t rl;
+ uint32_t rdqs;
+ uint32_t rdq;
+ uint32_t len = 1024<<4;
+ uint32_t flag = 0;
+ print_flag = 1;
+
+ for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+ wl = wl_val[wl_i];
+ latency_wr[0] = wl;
+ set_uhs_latency_w(wl);
+ for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){
+ wdq = wdq_val[wdq_i];
+ cfg_dq_drv(wdq);
+ cfg_ck_cen_drv(wdq + 4,wdq + 1);
+ for (wdqs = 0; wdqs <= 15; wdqs++){
+ cfg_dqs_drv(wdqs);
+ array_write_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ for (rl = latency_wr[1]; rl >= 35; rl--){
+ set_uhs_latency_r(rl);
+ rdq = 0;
+ cfg_dq_rx(rdq);
+ for (rdqs = 0; rdqs <= 15; rdqs++){
+ cfg_dqs_rx(rdqs);
+ flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(flag == 1){
+ uhs_phy_printf("INIT_ARRAY_WRITE_SUCCESS, rdqs++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ print_flag = 0;
+ #if CAL_MODE == 2
+ if(wl != 13){
+ init_array_write_err = 2;
+ return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR);
+ }
+ #endif
+ uhs_phy_cal_res->wl = wl;
+ return 0;
+ }
+ else{
+ uhs_phy_printf_debug("INIT_ARRAY_WRITE_FAIL, rdqs++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ }
+ }
+ rdqs = 0;
+ cfg_dqs_rx(rdqs);
+ for (rdq = 0; rdq <= 15; rdq++){
+ cfg_dq_rx(rdq);
+ flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+ if(flag == 1){
+ uhs_phy_printf("INIT_ARRAY_WRITE_SUCCESS, rdq++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ print_flag = 0;
+ #if CAL_MODE == 2
+ if(wl != 13){
+ init_array_write_err = 2;
+ return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR);
+ }
+ #endif
+ uhs_phy_cal_res->wl = wl;
+ return 0;
+ }
+ else{
+ uhs_phy_printf_debug("INIT_ARRAY_WRITE_FAIL, rdq++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+ }
+ }
+ }
+ }
+ }
+ }
+ init_array_write_err = 1;
+ return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR);
+}
+
+void set_odt_en(void){
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_RSVD_REG);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MR2_2_0,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_RSVD_REG,tmpVal);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,0x2); //reg_mode_reg
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+ uhs_phy_delay_us(10);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1); //reg_regw_pulse
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+ uhs_phy_delay_us(10);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0xf); // odt_sel
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x1);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_DLY,0x3);
+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal);
+}
+
+uint8_t init_reg_write_2kM(void){
+ uint32_t tmpVal = 0;
+ uint8_t wl_val[6] = {13,12,14,11,15,10};
+ uint8_t wl_i;
+ uint32_t wl;
+ uint32_t wdqs;
+ // uint8_t wdq_val[3] = {0,11,5};
+ uint8_t wdq_val[3] = {0,5,11};
+ uint8_t wdq_i;
+ uint32_t wdq;
+
+ // set to 2000Mbps
+ for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+ wl = wl_val[wl_i];
+ latency_wr[0] = wl;
+ set_uhs_latency_w(wl);
+ for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){
+ wdq = wdq_val[wdq_i];
+ cfg_dq_drv(wdq);
+ cfg_ck_cen_drv(wdq + 4,wdq + 1);
+ for (wdqs = 0; wdqs <= 15; wdqs++){
+ cfg_dqs_drv(wdqs);
+ set_odt_en();
+ CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ uhs_phy_printf_debug("MA2 = 0x%lx\r\n",tmpVal);
+ if(tmpVal == 3){
+ uhs_phy_printf("2kM_REG_WRITE_SUCCESS, wl = %ld, wdqs = %ld, wdq = %ld\r\n",wl,wdqs,wdq);
+ return 0;
+ }
+ else{
+ uhs_phy_printf_debug("2kM_REG_WRITE_FAIL, wl = %ld, wdqs = %ld, wdq = %ld\r\n",wl,wdqs,wdq);
+ }
+ }
+ }
+ }
+ return uhs_err_handler(UHS_REG_WRITE_2kM_ERR);
+}
+
+uint8_t self_cal()
+{
+ uint32_t tmpVal = 0;
+ uint32_t datarate;
+ datarate = cfg_glb->pck_freq;
+
+ if (datarate >= 933*2){
+ uhs_latency_code = UHS_LATENCY_CODE_1066;
+ }else if(datarate >= 800*2){
+ uhs_latency_code = UHS_LATENCY_CODE_933;
+ }else if(datarate >= 533*2){
+ uhs_latency_code = UHS_LATENCY_CODE_800;
+ }else if(datarate >= 400*2){
+ uhs_latency_code = UHS_LATENCY_CODE_533;
+ }else if(datarate >= 333*2){
+ uhs_latency_code = UHS_LATENCY_CODE_400;
+ }else if(datarate >= 200*2){
+ uhs_latency_code = UHS_LATENCY_CODE_333;
+ }else{
+ uhs_latency_code = UHS_LATENCY_CODE_200;
+ }
+ // #if PSRAM_32MB
+ // PSRAM_UHS_Cfg_Type psramCfg = {
+ // datarate,
+ // PSRAM_MEM_SIZE_32MB,
+ // PSRAM_PAGE_SIZE_2KB,
+ // 0,
+ // };
+ // #else
+ // PSRAM_UHS_Cfg_Type psramCfg = {
+ // datarate,
+ // PSRAM_MEM_SIZE_64MB,
+ // PSRAM_PAGE_SIZE_2KB,
+ // 0,
+ // };
+ // #endif
+
+ uhs_phy_printf("********** INIT_REG_WRITE **********\r\n");
+ CHECK_ERR_FLAG(init_reg_write,()); //write latency code
+ // uhs_phy_printf("START_CAL_AT %ldMbps\r\n",datarate);
+ // datarate_glb = datarate;
+ // ramsize_glb = cfg->psramMemSize;
+ GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,datarate);
+ Psram_UHS_Init_Override(cfg_glb); //controller init
+ set_uhs_phy();
+
+ #if CAL_MODE == 0
+ return 0;
+ // then load efuse, to set uhs phy regs
+ // call set_odt_en(), to set psram odt MR if need
+ // call mr_read_back()
+ #endif
+
+ uhs_phy_printf("********** REG_READ_CAL **********\r\n");
+ // uhs_phy_reg_dump();
+ // ******register read latency & dqs & dq calibration
+ CHECK_ERR_FLAG(reg_read_cal,());
+ if (cal_done_flag == 1)
+ return 0;
+ // if (datarate >= 1800){
+ // latency_wr[1] = 39;
+ // }else if(datarate >= 1600){
+ // latency_wr[1] = 38;
+ // }else if(datarate >= 1100){
+ // latency_wr[1] = 37;
+ // }else{
+ // latency_wr[1] = 36;
+ // }
+
+ CHECK_ERR_FLAG(uhs_reg_r,(1,0));
+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ tmpVal &= 0x10;
+ }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ tmpVal &= 0x20;
+ }
+ if (tmpVal != 0){
+ return uhs_err_handler(UHS_BAD_DIE_ERR);
+ }
+
+ uhs_phy_printf("UHS_PHY_CAL, ODT_EN = %d\r\n",ODT_EN);
+ #if ODT_EN
+ uhs_phy_printf("********** INIT_REG_WRITE_2kM **********\r\n");
+ CHECK_ERR_FLAG(init_reg_write_2kM,());
+ #endif
+
+ uhs_phy_printf("********** INIT_ARRAY_WRITE **********\r\n");
+ #if bl808_DBG_RF == 2
+ uhs_phy_reg_dump();
+ #endif
+ // reg_write_cal();
+ CHECK_ERR_FLAG(init_array_write,());
+ uhs_phy_printf("********** ARRAY_READ_CAL **********\r\n");
+ // uhs_phy_reg_dump();
+ // ******array read latency & dqs & dq calibration
+ CHECK_ERR_FLAG(array_read_latency_cal,());
+ uhs_phy_printf("********** ARRAY_WRITE_CK_CAL **********\r\n");
+ // uhs_phy_reg_dump();
+ flag_ck1 = 0;
+ flag_ck2 = 0;
+ CHECK_ERR_FLAG(array_write_ck_cal,());
+ uhs_phy_printf("********** ARRAY_WRITE_CAL **********\r\n");
+ // uhs_phy_reg_dump();
+ // array_read_dqs_dq_cal(); //calibrated in array_read_latency_cal
+ CHECK_ERR_FLAG(array_write_dqs_dq_cal,());
+ // uhs_phy_reg_dump();
+
+ return 0;
+}
+
+void soft_reset(void)
+{
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_SWRST_CFG2);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_CTRL_PWRON_RST,0x1); // soft power on reset
+ BL_WR_REG(GLB_BASE,GLB_SWRST_CFG2,tmpVal);
+ uhs_phy_delay_ms(1);
+}
+
+uint8_t uhs_diagonal_test(uint32_t data0,uint32_t data1)
+{
+ uint32_t RA = 0x0; //X_address
+ uint32_t CA = 0x0; //Y_address
+ uint32_t CA_init = 0x0;
+ uint32_t dataTmp;
+ uint32_t STRESS_TEST_BASE = 0x50000000;
+ uint32_t RowAddr = 0x3fff; //256Mb X_address
+
+ if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ RowAddr = 0x3fff;
+ }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ RowAddr = 0x7fff;
+ }
+
+ // data0
+ for (RA = 0x0; RA <= RowAddr; RA++){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ CA_init = (RA & 0x7f) << 3;
+ for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0;
+ }
+ }
+ for (RA = 0x0; RA <= RowAddr; RA++){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ CA_init = (RA & 0x7f) << 3;
+ for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+ if(dataTmp != data0){
+ uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+ uhs_phy_printfe("data_w data0: 0x%lx\r\n", data0);
+ uhs_phy_printfe("addr_r data0: 0x%lx\r\n", dataTmp);
+ return uhs_err_handler(UHS_DIAGONAL_TEST_ERR);
+ }
+ }
+ }
+ // data1
+ for (RA = 0x0; RA <= RowAddr; RA++){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ CA_init = (RA & 0x7f) << 3;
+ for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ *((volatile uint32_t*)(STRESS_TEST_BASE)) = data1;
+ }
+ }
+ for (RA = 0x0; RA <= RowAddr; RA++){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ CA_init = (RA & 0x7f) << 3;
+ for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+ if(dataTmp != data1){
+ uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+ uhs_phy_printfe("data_w data1: 0x%lx\r\n", data1);
+ uhs_phy_printfe("addr_r data1: 0x%lx\r\n", dataTmp);
+ return uhs_err_handler(UHS_DIAGONAL_TEST_ERR);
+ }
+ }
+ }
+
+ uhs_phy_printf("uhs_diagonal_test success\r\n");
+ return 0;
+}
+
+uint8_t uhs_all_addr_test(void)
+{
+ int32_t RA = 0x0; //X_address
+ int32_t CA = 0x0; //Y_address
+ uint32_t dataTmp;
+ uint32_t STRESS_TEST_BASE = 0x50000000;
+ uint32_t RowAddr = 0x3fff; //256Mb X_address
+ uint32_t data0 = 0xffffffff;
+ uint32_t data1 = 0x00000000;
+
+ if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ RowAddr = 0x3fff;
+ }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ RowAddr = 0x7fff;
+ }
+
+ // ****** Y_address -> X_address
+ //data0
+ for (RA = 0x0; RA <= RowAddr; RA++){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ for (CA = 0x0; CA <= 0x3ff; CA = CA + 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0;
+ }
+ }
+ for (RA = 0x0; RA <= RowAddr; RA++){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ for(CA = 0x0; CA <= 0x3ff; CA = CA + 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+ if(dataTmp != data0){
+ uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+ uhs_phy_printfe("data_w data0 first: 0x%lx\r\n", data0);
+ uhs_phy_printfe("addr_r data0 first: 0x%lx\r\n", dataTmp);
+ return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR);
+ }
+ }
+ }
+ // data1
+ for (RA = 0x0; RA <= RowAddr; RA++){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ for (CA = 0x0; CA <= 0x3ff; CA = CA + 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ *((volatile uint32_t*)(STRESS_TEST_BASE)) = data1;
+ }
+ }
+ // ****** X_address -> Y_address
+ // data1
+ for (RA = RowAddr; RA >= 0x0; RA--){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ for(CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+ if(dataTmp != data1){
+ uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+ uhs_phy_printfe("data_w data1: 0x%lx\r\n", data1);
+ uhs_phy_printfe("addr_r data1: 0x%lx\r\n", dataTmp);
+ return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR);
+ }
+ }
+ }
+ //data0
+ for (RA = RowAddr; RA >= 0x0; RA--){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ for (CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0;
+ }
+ }
+ for (RA = RowAddr; RA >= 0x0; RA--){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+ for(CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){
+ STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+ STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+ dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+ if(dataTmp != data0){
+ uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+ uhs_phy_printfe("data_w data0 second: 0x%lx\r\n", data0);
+ uhs_phy_printfe("addr_r data0 second: 0x%lx\r\n", dataTmp);
+ return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR);
+ }
+ }
+ }
+ uhs_phy_printf("uhs_all_addr_test success\r\n");
+ return 0;
+}
+
+
+void dump_uhs_phy_cal_res(void)
+{
+ #if CAL_MODE != 2
+ // dump uhs_phy_cal_res
+ uhs_phy_printf("uhs_phy_cal_res->cal_mode = %d\r\n",uhs_phy_cal_res->cal_mode);
+ uhs_phy_printf("uhs_phy_cal_res->err_type = %d\r\n",uhs_phy_cal_res->err_type);
+ uhs_phy_printf("uhs_phy_cal_res->err_sub_type = %d\r\n",uhs_phy_cal_res->err_sub_type);
+ uhs_phy_printf("uhs_phy_cal_res->datarate = %d\r\n",uhs_phy_cal_res->datarate);
+ uhs_phy_printf("uhs_phy_cal_res->rl = %d\r\n",uhs_phy_cal_res->rl);
+ uhs_phy_printf("uhs_phy_cal_res->rdqs = %d\r\n",uhs_phy_cal_res->rdqs);
+ uhs_phy_printf("uhs_phy_cal_res->rdq = %d\r\n",uhs_phy_cal_res->rdq);
+ uhs_phy_printf("uhs_phy_cal_res->rwindow = %d\r\n",uhs_phy_cal_res->rwindow);
+ uhs_phy_printf("uhs_phy_cal_res->rwindow_begin = %d\r\n",uhs_phy_cal_res->rwindow_begin);
+ uhs_phy_printf("uhs_phy_cal_res->rwindow_end = %d\r\n",uhs_phy_cal_res->rwindow_end);
+ uhs_phy_printf("uhs_phy_cal_res->ck = %d\r\n",uhs_phy_cal_res->ck);
+ uhs_phy_printf("uhs_phy_cal_res->wl = %d\r\n",uhs_phy_cal_res->wl);
+ uhs_phy_printf("uhs_phy_cal_res->wdqs = %d\r\n",uhs_phy_cal_res->wdqs);
+ uhs_phy_printf("uhs_phy_cal_res->wdq = %d\r\n",uhs_phy_cal_res->wdq);
+ uhs_phy_printf("uhs_phy_cal_res->wwindow = %d\r\n",uhs_phy_cal_res->wwindow);
+ uhs_phy_printf("uhs_phy_cal_res->wwindow_begin = %d\r\n",uhs_phy_cal_res->wwindow_begin);
+ uhs_phy_printf("uhs_phy_cal_res->wwindow_end = %d\r\n",uhs_phy_cal_res->wwindow_end);
+ uhs_phy_printf("uhs_phy_cal_res->cal_done = %d\r\n",uhs_phy_cal_res->cal_done);
+ uhs_phy_printf("uhs_phy_cal_res->crc_res = %lx\r\n",uhs_phy_cal_res->crc_res);
+ #else
+ // dump uhs_phy_cal_res
+ uhs_phy_printf("uhs_phy_cal_res->cal_mode = %ld\r\n",uhs_phy_cal_res->cal_mode);
+ uhs_phy_printf("uhs_phy_cal_res->err_type = %lx\r\n",uhs_phy_cal_res->err_type);
+ uhs_phy_printf("uhs_phy_cal_res->err_sub_type = %ld\r\n",uhs_phy_cal_res->err_sub_type);
+ uhs_phy_printf("uhs_phy_cal_res->datarate = %ld\r\n",uhs_phy_cal_res->datarate);
+ uhs_phy_printf("uhs_phy_cal_res->rl = %ld\r\n",uhs_phy_cal_res->rl);
+ uhs_phy_printf("uhs_phy_cal_res->rdqs = %ld\r\n",uhs_phy_cal_res->rdqs);
+ uhs_phy_printf("uhs_phy_cal_res->rdq = %ld\r\n",uhs_phy_cal_res->rdq);
+ uhs_phy_printf("uhs_phy_cal_res->rwindow = %ld\r\n",uhs_phy_cal_res->rwindow);
+ uhs_phy_printf("uhs_phy_cal_res->rwindow_begin = %ld\r\n",uhs_phy_cal_res->rwindow_begin);
+ uhs_phy_printf("uhs_phy_cal_res->rwindow_end = %ld\r\n",uhs_phy_cal_res->rwindow_end);
+ uhs_phy_printf("uhs_phy_cal_res->ck = %ld\r\n",uhs_phy_cal_res->ck);
+ uhs_phy_printf("uhs_phy_cal_res->wl = %ld\r\n",uhs_phy_cal_res->wl);
+ uhs_phy_printf("uhs_phy_cal_res->wdqs = %ld\r\n",uhs_phy_cal_res->wdqs);
+ uhs_phy_printf("uhs_phy_cal_res->wdq = %ld\r\n",uhs_phy_cal_res->wdq);
+ uhs_phy_printf("uhs_phy_cal_res->wwindow = %ld\r\n",uhs_phy_cal_res->wwindow);
+ uhs_phy_printf("uhs_phy_cal_res->wwindow_begin = %ld\r\n",uhs_phy_cal_res->wwindow_begin);
+ uhs_phy_printf("uhs_phy_cal_res->wwindow_end = %ld\r\n",uhs_phy_cal_res->wwindow_end);
+ uhs_phy_printf("uhs_phy_cal_res->cal_done = %lx\r\n",uhs_phy_cal_res->cal_done);
+ uhs_phy_printf("uhs_phy_cal_res->crc_res = %lx\r\n",uhs_phy_cal_res->crc_res);
+ #endif
+}
+
+void uhs_phy_init(PSRAM_UHS_Cfg_Type *cfg)
+{
+ memset((void*)uhs_phy_cal_res, 0, sizeof(uhs_phy_cal_res_struct));
+ uhs_phy_cal_res->cal_mode = CAL_MODE;
+ uhs_phy_cal_res->datarate = cfg->pck_freq;
+
+ err_flag = 0;
+
+ __DSB();
+ __ISB();
+ cache_state = __get_MHCR();
+ cache_state &= (0x1<<1);
+ __DSB();
+ __ISB();
+
+ cfg_glb = cfg;
+ latency_wr_2kM[1] = 41;
+ uhs_phy_init_core(cfg);
+}
+
+extern uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len);
+uint8_t uhs_phy_init_core(PSRAM_UHS_Cfg_Type *cfg)
+{
+ cal_done_flag = 0;
+ if(latency_wr_2kM[1] == 34)
+ {
+ reg_read_err = 3;
+ return uhs_err_handler(UHS_REG_READ_CAL_ERR);
+ }
+
+ uint32_t pck_freq_temp;
+
+ uhs_phy_printf_debug("uhs phy init\r\n");
+ if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ uhs_phy_printf("\r\n########## START_CAL_AT %ldMbps, PSRAM_MEM_SIZE_32MB, CACHE_EN = %ld ##########\r\n",cfg->pck_freq,cache_state);
+ }else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ uhs_phy_printf("\r\n########## START_CAL_AT %ldMbps, PSRAM_MEM_SIZE_64MB, CACHE_EN = %ld ##########\r\n",cfg->pck_freq,cache_state);
+ }
+ #if CAL_MODE != 2
+ uhs_phy_printf("CAL_MODE = %d\r\n",uhs_phy_cal_res->cal_mode);
+ #else
+ uhs_phy_printf("CAL_MODE = %ld\r\n",uhs_phy_cal_res->cal_mode);
+ #endif
+
+ power_up_mm(0);
+ power_up_uhspll();
+
+ power_up_ldo12uhs();
+ set_cen_ck_ckn();
+
+ set_or_uhs();
+ switch_to_ldo12uhs();
+ release_cen_ck_ckn();
+
+ uint32_t tmpVal = 0;
+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG9);
+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SSC_EN,0x0); // uhspll_ssc_en
+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG9,tmpVal);
+ pck_freq_temp = cfg->pck_freq;
+ if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ cfg->pck_freq = 800;
+ // PSRAM_UHS_Cfg_Type psramCfg = {
+ // 800,
+ // PSRAM_MEM_SIZE_32MB,
+ // PSRAM_PAGE_SIZE_2KB,
+ // 0,
+ // };
+
+ GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,800); //stuck
+ Psram_UHS_Init_Override(cfg); // controller init
+ set_uhs_phy_init(); // phy init
+ set_uhs_latency_w(1);
+ set_uhs_latency_r(17);
+ psram_init(); // psram init after set freq & set_phy
+
+ // uhs_reg_r(0,1);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ // uhs_phy_printf_debug("readout MA0 = 0x%lx\r\n",tmpVal);
+ // if(tmpVal == ((2<<3)+5)) // 700M --> default uhs_latency_code == 5
+ // {
+ // uhs_phy_printf_debug("register read pass at 700Mbps\r\n");
+ // }
+ // else{
+ // uhs_phy_printf_debug("register read fail at 700Mbps\r\n");
+ // }
+ }
+ else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ cfg->pck_freq = 1400;
+ // PSRAM_UHS_Cfg_Type psramCfg = {
+ // 1400,
+ // PSRAM_MEM_SIZE_64MB,
+ // PSRAM_PAGE_SIZE_2KB,
+ // 0,
+ // };
+
+ GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,1400); //stuck
+ Psram_UHS_Init_Override(cfg); // controller init
+ set_uhs_phy_init(); // phy init
+ set_uhs_latency_w(9);
+ set_uhs_latency_r(30);
+ psram_init(); // psram init after set freq & set_phy
+
+ // uhs_reg_r(0,1);
+ // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+ // if(tmpVal == ((2<<3)+1)) // 1400M --> default uhs_latency_code == 1
+ // {
+ // uhs_phy_printf_debug("register read pass at 1400Mbps\r\n");
+ // }
+ // else{
+ // uhs_phy_printf_debug("register read fail at 1400Mbps\r\n");
+ // }
+ }
+
+ cfg->pck_freq = pck_freq_temp;
+ self_cal();
+ uhs_phy_delay_ms(1);
+ cal_done_flag = 1;
+ #if CAL_MODE == 2
+ if(err_flag == 0){
+ uhs_phy_printf("********** UHS_DIAGONAL_TEST **********\r\n");
+ uhs_diagonal_test(0x5555aaaa,0xaaaa5555);
+ // uhs_phy_printf("********** UHS_ALL_ADDR_TEST **********\r\n");
+ // uhs_all_addr_test();
+ }
+ // uhs_phy_printfe("!!!!!!!!!! uhs_phy_cal_res->err_type = %d !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type);l
+ uint32_t magic_os = 0x89abcdef;
+ uhs_phy_cal_res->err_type += magic_os;
+ uhs_phy_cal_res->cal_done = magic_os;
+ uhs_phy_cal_res->crc_res = BFLB_Soft_CRC32(uhs_phy_cal_res, sizeof(uhs_phy_cal_res_struct)-4);
+ #elif CAL_MODE == 1
+ uhs_phy_cal_res->cal_done = 1;
+ uhs_phy_cal_res->crc_res = BFLB_Soft_CRC32(uhs_phy_cal_res, sizeof(uhs_phy_cal_res_struct)-4);
+ #endif
+
+ #if CAL_MODE != 2
+ uhs_phy_printf("!!!!!!!!!! uhs_phy_cal_res->err_type = %d !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type);
+ #else
+ uhs_phy_printf("!!!!!!!!!! uhs_phy_cal_res->err_type = %lx !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type);
+ #endif
+
+ dump_uhs_phy_cal_res();
+ return uhs_phy_cal_res->err_type;
+
+ //get dcache original state
+ __DSB();
+ __ISB();
+ dcache_original = __get_MHCR();
+ dcache_original &= (0x1<<1);
+ __DSB();
+ __ISB();
+ uhs_phy_printf_debug("dcache_original= 0x%lx\r\n",dcache_original);
+
+ uhs_phy_printf("UHS_PHY_CAL, CACHE_EN = %d\r\n",CACHE_EN);
+ #if CACHE_EN
+ csi_dcache_enable();
+ #else
+ csi_dcache_disable();
+ #endif
+
+ //get dcache current state
+ __DSB();
+ __ISB();
+ dcache_current = __get_MHCR();
+ dcache_current &= (0x1<<1);
+ __DSB();
+ __ISB();
+ uhs_phy_printf_debug("dcache_current= 0x%lx\r\n",dcache_current);
+
+ cfg->pck_freq = pck_freq_temp;
+ #if CACHE_EN
+ if(dcache_current == (0x1<<1))
+ {
+ self_cal();
+ }
+ else
+ {
+ uhs_phy_printf_debug("dcache enable fail\r\n");
+ return uhs_err_handler(UHS_CACHE_ENABLE_ERR);
+ }
+ if (dcache_original == 0)
+ {
+ csi_dcache_disable();
+ }
+ #else
+ if(dcache_current == 0x0)
+ {
+ self_cal();
+ }
+ else
+ {
+ uhs_phy_printf_debug("dcache disable fail\r\n");
+ return uhs_err_handler(UHS_CACHE_DISABLE_ERR);
+ }
+ if (dcache_original == (0x1<<1))
+ {
+ csi_dcache_enable();
+ }
+ #endif
+
+ //get dcache end state
+ __DSB();
+ __ISB();
+ dcache_end = __get_MHCR();
+ dcache_end &= (0x1<<1);
+ __DSB();
+ __ISB();
+ if(dcache_end == dcache_original)
+ {
+ uhs_phy_printf_debug("dcache state right , dcache_state= 0x%lx\r\n",dcache_end);
+ }
+ else
+ {
+ uhs_phy_printf_debug("dcache state error\r\n");
+ return uhs_err_handler(UHS_CACHE_RECOVER_ERR);
+ }
+
+ uhs_phy_delay_ms(1);
+
+ if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){
+ uhs_phy_printf("########## END_CAL_AT %ldMbps, PSRAM_MEM_SIZE_32MB ##########\r\n",cfg->pck_freq);
+ }else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){
+ uhs_phy_printf("########## END_CAL_AT %ldMbps, PSRAM_MEM_SIZE_64MB ##########\r\n",cfg->pck_freq);
+ }
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/interrupt.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/interrupt.c
new file mode 100644
index 00000000..6a594133
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/interrupt.c
@@ -0,0 +1,154 @@
+#include "bflb_core.h"
+#include
+#include "irq_ctx.h"
+#include "bl808_glb.h"
+
+extern void riscv_savefpu(const uintptr_t *regs);
+extern void riscv_restorefpu(const uintptr_t *regs);
+
+#define RV_EXCEPTION_NUM (16)
+typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs);
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM] __attribute__((aligned(16)));
+
+static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) __attribute__((noreturn));
+static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs)
+{
+ printf("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type());
+ // clang-format off
+ printf("mstatus = 0x%16llx, FS=%d, MPP=%d, MPIE=%d\n\r", regs[REG_INT_CTX_NDX],
+ (regs[REG_INT_CTX_NDX] >> 13) & 0x3,
+ (regs[REG_INT_CTX_NDX] >> 11) & 0x3,
+ (regs[REG_INT_CTX_NDX] >> 7) & 1);
+ printf("mcause: %d, mtval = 0x%16llx, mepc = 0x%16llx\n\r\n\r", (cause & 0xf), val, regs[REG_EPC_NDX]);
+
+const char *mcause_str[] = {
+ "Instruction address misaligned",
+ "Instruction access fault",
+ "Illegal instruction",
+ "Breakpoint",
+ "Load address misaligned",
+ "Load access fault",
+ "Store/AMO address misaligned",
+ "Store/AMO access fault",
+ "Environment call from U-mode",
+ "Environment call from S-mode",
+ "RSVD",
+ "Environment call from M-mode",
+ "Instruction page fault",
+ "Load page fault",
+ "RSVD",
+ "Store/AMO page fault"
+};
+ if ((cause & 0xf))
+ printf("%s\r\n\r\n", mcause_str[cause & 0xf]);
+
+#ifdef CONFIG_TRAP_DUMP_ALL_REGS
+ printf("ra = 0x%16llx ", regs[REG_RA]); printf("sp = 0x%16llx ", regs[REG_SP]); printf("gp = 0x%16llx ", regs[REG_GP]);
+ printf("tp = 0x%16llx ", regs[REG_TP]); printf("\n\r");
+
+ printf("t0 = 0x%16llx ", regs[REG_T0]); printf("t1 = 0x%16llx ", regs[REG_T1]); printf("t2 = 0x%16llx ", regs[REG_T2]);
+ printf("t3 = 0x%16llx ", regs[REG_T3]); printf("\n\r");
+ printf("t4 = 0x%16llx ", regs[REG_T4]); printf("t5 = 0x%16llx ", regs[REG_T5]); printf("t6 = 0x%16llx ", regs[REG_T6]);
+ printf("\n\r");
+
+ printf("a0 = 0x%16llx ", regs[REG_A0]); printf("a1 = 0x%16llx ", regs[REG_A1]); printf("a2 = 0x%16llx ", regs[REG_A2]);
+ printf("a3 = 0x%16llx ", regs[REG_A3]); printf("\n\r");
+ printf("a4 = 0x%16llx ", regs[REG_A4]); printf("a5 = 0x%16llx ", regs[REG_A5]); printf("a6 = 0x%16llx ", regs[REG_A6]);
+ printf("a7 = 0x%16llx ", regs[REG_A7]); printf("\n\r");
+
+ printf("s0 = 0x%16llx ", regs[REG_S0]); printf("s1 = 0x%16llx ", regs[REG_S1]); printf("s2 = 0x%16llx ", regs[REG_S2]);
+ printf("s3 = 0x%16llx ", regs[REG_S3]); printf("\n\r");
+ printf("s4 = 0x%16llx ", regs[REG_S4]); printf("s5 = 0x%16llx ", regs[REG_S5]); printf("s6 = 0x%16llx ", regs[REG_S6]);
+ printf("s7 = 0x%16llx ", regs[REG_S7]); printf("\n\r");
+ printf("s8 = 0x%16llx ", regs[REG_S8]); printf("s9 = 0x%16llx ", regs[REG_S9]); printf("s10 = 0x%16llx ", regs[REG_S10]);
+ printf("s11 = 0x%16llx ", regs[REG_S11]); printf("\n\r");
+#endif
+ // clang-format on
+ printf("\n\r");
+
+ while (1) {
+ }
+}
+
+static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs)
+{
+ regs[REG_EPC_NDX] += 4;
+ __asm volatile("nop" ::
+ : "memory");
+
+ return 0;
+}
+
+static exception_handler exception_handlers[RV_EXCEPTION_NUM] = {
+ exception_handler_default, /* 0: Instruction Address Misaligned */
+ exception_handler_default, /* 1: Instruction Access Fault */
+ exception_handler_default, /* 2: Illegal Instruction */
+ exception_handler_default, /* 3: Breakpoint */
+ exception_handler_default, /* 4: Load Address Misaligned */
+ exception_handler_default, /* 5: Load Access Fault */
+ exception_handler_default, /* 6: Store/AMO Address Misaligned */
+ exception_handler_default, /* 7: Store/AMO Access Fault */
+ exception_handler_default, /* 8: Environment Call from U-mode */
+ exception_handler_default, /* 9: Environment Call from S-mode */
+ exception_handler_default, /* 10: Environment Call from H-mode */
+ exception_handler_ECALL_M, /* 11: Environment Call from M-mode */
+ exception_handler_default, /* 12: Instruction Page Fault */
+ exception_handler_default, /* 13: Load Page Fault */
+ exception_handler_default, /* 14: Reserved */
+ exception_handler_default, /* 15: Store/AMO Page Fault */
+};
+
+exception_handler exception_handler_install(uintptr_t vec, exception_handler handler)
+{
+ exception_handler previous = NULL;
+
+ if (RV_EXCEPTION_NUM > vec) {
+ previous = exception_handlers[vec];
+ exception_handlers[vec] = handler;
+ }
+
+ return previous;
+}
+
+uintptr_t *trap_c(uintptr_t cause, uintptr_t *regs)
+{
+ uint32_t vec = 0;
+ uintptr_t tval = __get_MTVAL();
+
+ riscv_savefpu(regs);
+
+ vec = cause & 0x3FF;
+
+ if (RV_EXCEPTION_NUM > vec) {
+ exception_handlers[vec](cause, tval, regs);
+ } else {
+ while (1)
+ ;
+ }
+
+ riscv_restorefpu(regs);
+
+ return regs;
+}
+
+void interrupt_entry(uint64_t irq_num)
+{
+ irq_callback handler;
+ void *arg;
+ // volatile uint32_t irq_num;
+
+ //irq_num = PLIC->PLIC_H0_MCLAIM & 0x3ff;
+
+ if (irq_num < CONFIG_IRQ_NUM) {
+ handler = g_irqvector[irq_num].handler;
+ arg = g_irqvector[irq_num].arg;
+ if (handler) {
+ handler(irq_num, arg);
+ } else {
+ }
+ } else {
+ }
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/irq_ctx.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/irq_ctx.h
new file mode 100644
index 00000000..3639e2dd
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/irq_ctx.h
@@ -0,0 +1,372 @@
+#ifndef __IRQ_CTX_H__
+#define __IRQ_CTX_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#define CONFIG_ARCH_FPU
+#define CONFIG_ARCH_DPFPU
+
+/* Processor PC */
+
+#define REG_EPC_NDX 0
+
+/* General pupose registers
+ * $0: Zero register does not need to be saved
+ * $1: ra (return address)
+ */
+
+#define REG_X1_NDX 1
+
+/* $2: Stack POinter
+ * $3: Global Pointer
+ * $4: Thread Pointer
+ */
+
+#define REG_X2_NDX 2
+#define REG_X3_NDX 3
+#define REG_X4_NDX 4
+
+/* $5-$7 = t0-t3: Temporary registers */
+
+#define REG_X5_NDX 5
+#define REG_X6_NDX 6
+#define REG_X7_NDX 7
+
+/* $8: s0 / fp Frame pointer */
+
+#define REG_X8_NDX 8
+
+/* $89 s1 Saved register */
+
+#define REG_X9_NDX 9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_X10_NDX 10
+#define REG_X11_NDX 11
+#define REG_X12_NDX 12
+#define REG_X13_NDX 13
+#define REG_X14_NDX 14
+#define REG_X15_NDX 15
+#define REG_X16_NDX 16
+#define REG_X17_NDX 17
+
+/* $18-$27 = s2-s11: Saved registers */
+
+#define REG_X18_NDX 18
+#define REG_X19_NDX 19
+#define REG_X20_NDX 20
+#define REG_X21_NDX 21
+#define REG_X22_NDX 22
+#define REG_X23_NDX 23
+#define REG_X24_NDX 24
+#define REG_X25_NDX 25
+#define REG_X26_NDX 26
+#define REG_X27_NDX 27
+
+/* $28-31 = t3-t6: Temporary (Volatile) registers */
+
+#define REG_X28_NDX 28
+#define REG_X29_NDX 29
+#define REG_X30_NDX 30
+#define REG_X31_NDX 31
+
+/* Interrupt Context register */
+
+#define REG_INT_CTX_NDX 32
+
+#define INT_XCPT_REGS 33
+
+#define INT_XCPT_SIZE (8 * INT_XCPT_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+#if defined(CONFIG_ARCH_DPFPU)
+#define FPU_REG_SIZE 1 /* size in uint64_t */
+#elif defined(CONFIG_ARCH_QPFPU)
+#define FPU_REG_SIZE 2
+#else
+#error not supported !!!
+#endif
+
+#define REG_F0_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 0)
+#define REG_F1_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 1)
+#define REG_F2_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 2)
+#define REG_F3_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 3)
+#define REG_F4_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 4)
+#define REG_F5_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 5)
+#define REG_F6_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 6)
+#define REG_F7_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 7)
+#define REG_F8_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 8)
+#define REG_F9_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 9)
+#define REG_F10_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 10)
+#define REG_F11_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 11)
+#define REG_F12_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 12)
+#define REG_F13_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 13)
+#define REG_F14_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 14)
+#define REG_F15_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 15)
+#define REG_F16_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 16)
+#define REG_F17_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 17)
+#define REG_F18_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 18)
+#define REG_F19_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 19)
+#define REG_F20_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 20)
+#define REG_F21_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 21)
+#define REG_F22_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 22)
+#define REG_F23_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 23)
+#define REG_F24_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 24)
+#define REG_F25_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 25)
+#define REG_F26_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 26)
+#define REG_F27_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 27)
+#define REG_F28_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 28)
+#define REG_F29_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 29)
+#define REG_F30_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 30)
+#define REG_F31_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 31)
+#define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32)
+
+#define FPU_XCPT_REGS (FPU_REG_SIZE * 33)
+#else
+#define FPU_XCPT_REGS 0
+#endif
+
+#define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS)
+
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+/* In assembly language, values have to be referenced as byte address
+ * offsets. But in C, it is more convenient to reference registers as
+ * register save table offsets.
+ */
+
+#ifdef __ASSEMBLY__
+#define REG_EPC (8 * REG_EPC_NDX)
+#define REG_X1 (8 * REG_X1_NDX)
+#define REG_X2 (8 * REG_X2_NDX)
+#define REG_X3 (8 * REG_X3_NDX)
+#define REG_X4 (8 * REG_X4_NDX)
+#define REG_X5 (8 * REG_X5_NDX)
+#define REG_X6 (8 * REG_X6_NDX)
+#define REG_X7 (8 * REG_X7_NDX)
+#define REG_X8 (8 * REG_X8_NDX)
+#define REG_X9 (8 * REG_X9_NDX)
+#define REG_X10 (8 * REG_X10_NDX)
+#define REG_X11 (8 * REG_X11_NDX)
+#define REG_X12 (8 * REG_X12_NDX)
+#define REG_X13 (8 * REG_X13_NDX)
+#define REG_X14 (8 * REG_X14_NDX)
+#define REG_X15 (8 * REG_X15_NDX)
+#define REG_X16 (8 * REG_X16_NDX)
+#define REG_X17 (8 * REG_X17_NDX)
+#define REG_X18 (8 * REG_X18_NDX)
+#define REG_X19 (8 * REG_X19_NDX)
+#define REG_X20 (8 * REG_X20_NDX)
+#define REG_X21 (8 * REG_X21_NDX)
+#define REG_X22 (8 * REG_X22_NDX)
+#define REG_X23 (8 * REG_X23_NDX)
+#define REG_X24 (8 * REG_X24_NDX)
+#define REG_X25 (8 * REG_X25_NDX)
+#define REG_X26 (8 * REG_X26_NDX)
+#define REG_X27 (8 * REG_X27_NDX)
+#define REG_X28 (8 * REG_X28_NDX)
+#define REG_X29 (8 * REG_X29_NDX)
+#define REG_X30 (8 * REG_X30_NDX)
+#define REG_X31 (8 * REG_X31_NDX)
+#define REG_INT_CTX (8 * REG_INT_CTX_NDX)
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0 (8 * REG_F0_NDX)
+#define REG_F1 (8 * REG_F1_NDX)
+#define REG_F2 (8 * REG_F2_NDX)
+#define REG_F3 (8 * REG_F3_NDX)
+#define REG_F4 (8 * REG_F4_NDX)
+#define REG_F5 (8 * REG_F5_NDX)
+#define REG_F6 (8 * REG_F6_NDX)
+#define REG_F7 (8 * REG_F7_NDX)
+#define REG_F8 (8 * REG_F8_NDX)
+#define REG_F9 (8 * REG_F9_NDX)
+#define REG_F10 (8 * REG_F10_NDX)
+#define REG_F11 (8 * REG_F11_NDX)
+#define REG_F12 (8 * REG_F12_NDX)
+#define REG_F13 (8 * REG_F13_NDX)
+#define REG_F14 (8 * REG_F14_NDX)
+#define REG_F15 (8 * REG_F15_NDX)
+#define REG_F16 (8 * REG_F16_NDX)
+#define REG_F17 (8 * REG_F17_NDX)
+#define REG_F18 (8 * REG_F18_NDX)
+#define REG_F19 (8 * REG_F19_NDX)
+#define REG_F20 (8 * REG_F20_NDX)
+#define REG_F21 (8 * REG_F21_NDX)
+#define REG_F22 (8 * REG_F22_NDX)
+#define REG_F23 (8 * REG_F23_NDX)
+#define REG_F24 (8 * REG_F24_NDX)
+#define REG_F25 (8 * REG_F25_NDX)
+#define REG_F26 (8 * REG_F26_NDX)
+#define REG_F27 (8 * REG_F27_NDX)
+#define REG_F28 (8 * REG_F28_NDX)
+#define REG_F29 (8 * REG_F29_NDX)
+#define REG_F30 (8 * REG_F30_NDX)
+#define REG_F31 (8 * REG_F31_NDX)
+#define REG_FCSR (8 * REG_FCSR_NDX)
+#endif
+
+#else
+#define REG_EPC REG_EPC_NDX
+#define REG_X1 REG_X1_NDX
+#define REG_X2 REG_X2_NDX
+#define REG_X3 REG_X3_NDX
+#define REG_X4 REG_X4_NDX
+#define REG_X5 REG_X5_NDX
+#define REG_X6 REG_X6_NDX
+#define REG_X7 REG_X7_NDX
+#define REG_X8 REG_X8_NDX
+#define REG_X9 REG_X9_NDX
+#define REG_X10 REG_X10_NDX
+#define REG_X11 REG_X11_NDX
+#define REG_X12 REG_X12_NDX
+#define REG_X13 REG_X13_NDX
+#define REG_X14 REG_X14_NDX
+#define REG_X15 REG_X15_NDX
+#define REG_X16 REG_X16_NDX
+#define REG_X17 REG_X17_NDX
+#define REG_X18 REG_X18_NDX
+#define REG_X19 REG_X19_NDX
+#define REG_X20 REG_X20_NDX
+#define REG_X21 REG_X21_NDX
+#define REG_X22 REG_X22_NDX
+#define REG_X23 REG_X23_NDX
+#define REG_X24 REG_X24_NDX
+#define REG_X25 REG_X25_NDX
+#define REG_X26 REG_X26_NDX
+#define REG_X27 REG_X27_NDX
+#define REG_X28 REG_X28_NDX
+#define REG_X29 REG_X29_NDX
+#define REG_X30 REG_X30_NDX
+#define REG_X31 REG_X31_NDX
+#define REG_INT_CTX REG_INT_CTX_NDX
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0 REG_F0_NDX
+#define REG_F1 REG_F1_NDX
+#define REG_F2 REG_F2_NDX
+#define REG_F3 REG_F3_NDX
+#define REG_F4 REG_F4_NDX
+#define REG_F5 REG_F5_NDX
+#define REG_F6 REG_F6_NDX
+#define REG_F7 REG_F7_NDX
+#define REG_F8 REG_F8_NDX
+#define REG_F9 REG_F9_NDX
+#define REG_F10 REG_F10_NDX
+#define REG_F11 REG_F11_NDX
+#define REG_F12 REG_F12_NDX
+#define REG_F13 REG_F13_NDX
+#define REG_F14 REG_F14_NDX
+#define REG_F15 REG_F15_NDX
+#define REG_F16 REG_F16_NDX
+#define REG_F17 REG_F17_NDX
+#define REG_F18 REG_F18_NDX
+#define REG_F19 REG_F19_NDX
+#define REG_F20 REG_F20_NDX
+#define REG_F21 REG_F21_NDX
+#define REG_F22 REG_F22_NDX
+#define REG_F23 REG_F23_NDX
+#define REG_F24 REG_F24_NDX
+#define REG_F25 REG_F25_NDX
+#define REG_F26 REG_F26_NDX
+#define REG_F27 REG_F27_NDX
+#define REG_F28 REG_F28_NDX
+#define REG_F29 REG_F29_NDX
+#define REG_F30 REG_F30_NDX
+#define REG_F31 REG_F31_NDX
+#define REG_FCSR REG_FCSR_NDX
+#endif
+
+#endif
+
+/* Now define more user friendly alternative name that can be used either
+ * in assembly or C contexts.
+ */
+
+/* $1 = ra: Return address */
+
+#define REG_RA REG_X1
+
+/* $2 = sp: The value of the stack pointer on return from the exception */
+
+#define REG_SP REG_X2
+
+/* $3 = gp: Only needs to be saved under conditions where there are
+ * multiple, per-thread values for the GP.
+ */
+
+#define REG_GP REG_X3
+
+/* $4 = tp: Thread Pointer */
+
+#define REG_TP REG_X4
+
+/* $5-$7 = t0-t2: Caller saved temporary registers */
+
+#define REG_T0 REG_X5
+#define REG_T1 REG_X6
+#define REG_T2 REG_X7
+
+/* $8 = either s0 or fp: Depends if a frame pointer is used or not */
+
+#define REG_S0 REG_X8
+#define REG_FP REG_X8
+
+/* $9 = s1: Caller saved register */
+
+#define REG_S1 REG_X9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_A0 REG_X10
+#define REG_A1 REG_X11
+#define REG_A2 REG_X12
+#define REG_A3 REG_X13
+#define REG_A4 REG_X14
+#define REG_A5 REG_X15
+#define REG_A6 REG_X16
+#define REG_A7 REG_X17
+
+/* $18-$27 = s2-s11: Callee saved registers */
+
+#define REG_S2 REG_X18
+#define REG_S3 REG_X19
+#define REG_S4 REG_X20
+#define REG_S5 REG_X21
+#define REG_S6 REG_X22
+#define REG_S7 REG_X23
+#define REG_S8 REG_X24
+#define REG_S9 REG_X25
+#define REG_S10 REG_X26
+#define REG_S11 REG_X27
+
+/* $28-$31 = t3-t6: Caller saved temporary registers */
+
+#define REG_T3 REG_X28
+#define REG_T4 REG_X29
+#define REG_T5 REG_X30
+#define REG_T6 REG_X31
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __IRQ_CTX_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/riscv_fpu.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/riscv_fpu.S
new file mode 100644
index 00000000..a88e6230
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/riscv_fpu.S
@@ -0,0 +1,221 @@
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+#if defined(CONFIG_ARCH_FPU)
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Symbols
+ ************************************************************************************/
+
+ .globl riscv_fpuconfig
+ .globl riscv_savefpu
+ .globl riscv_savefpu_force
+ .globl riscv_restorefpu
+
+ .file "riscv_fpu.S"
+
+#define FS_MASK 0x6000
+#define FS_OFF 0x0000
+#define FS_INITIAL 0x2000
+#define FS_CLEAN 0x4000
+#define FS_DIRTY 0x6000
+
+#if defined(CONFIG_ARCH_DPFPU)
+# define FLOAD fld
+# define FSTORE fsd
+# define LOAD ld
+# define STORE sd
+#elif defined(CONFIG_ARCH_QPFPU)
+# define FLOAD flq
+# define FSTORE fsq
+#else
+# define FLOAD flw
+# define FSTORE fsw
+# define LOAD lw
+# define STORE sw
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: riscv_fpuconfig
+ *
+ * Description:
+ * init fpu
+ *
+ * C Function Prototype:
+ * void riscv_fpuconfig(void);
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * This function does not return anything explicitly.
+ *
+ ************************************************************************************/
+
+ .type riscv_fpuconfig, function
+
+riscv_fpuconfig:
+ li a0, FS_INITIAL
+ csrs mstatus, a0
+ csrwi fcsr, 0
+ ret
+
+/************************************************************************************
+ * Name: riscv_savefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), save the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void riscv_savefpu(uintptr_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area in which to save the floating point
+ * registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+ .type riscv_savefpu, function
+
+riscv_savefpu:
+ LOAD t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_DIRTY
+ bne t2, t1, 1f
+ li t1, ~FS_MASK
+ and t0, t0, t1
+ li t1, FS_CLEAN
+ or t0, t0, t1
+ STORE t0, REG_INT_CTX(a0)
+
+ /* Store all floating point registers */
+riscv_savefpu_force:
+
+ FSTORE f0, REG_F0(a0)
+ FSTORE f1, REG_F1(a0)
+ FSTORE f2, REG_F2(a0)
+ FSTORE f3, REG_F3(a0)
+ FSTORE f4, REG_F4(a0)
+ FSTORE f5, REG_F5(a0)
+ FSTORE f6, REG_F6(a0)
+ FSTORE f7, REG_F7(a0)
+ FSTORE f8, REG_F8(a0)
+ FSTORE f9, REG_F9(a0)
+ FSTORE f10, REG_F10(a0)
+ FSTORE f11, REG_F11(a0)
+ FSTORE f12, REG_F12(a0)
+ FSTORE f13, REG_F13(a0)
+ FSTORE f14, REG_F14(a0)
+ FSTORE f15, REG_F15(a0)
+ FSTORE f16, REG_F16(a0)
+ FSTORE f17, REG_F17(a0)
+ FSTORE f18, REG_F18(a0)
+ FSTORE f19, REG_F19(a0)
+ FSTORE f20, REG_F20(a0)
+ FSTORE f21, REG_F21(a0)
+ FSTORE f22, REG_F22(a0)
+ FSTORE f23, REG_F23(a0)
+ FSTORE f24, REG_F24(a0)
+ FSTORE f25, REG_F25(a0)
+ FSTORE f26, REG_F26(a0)
+ FSTORE f27, REG_F27(a0)
+ FSTORE f28, REG_F28(a0)
+ FSTORE f29, REG_F29(a0)
+ FSTORE f30, REG_F30(a0)
+ FSTORE f31, REG_F31(a0)
+
+ frcsr t0
+ STORE t0, REG_FCSR(a0)
+
+1:
+ ret
+
+/************************************************************************************
+ * Name: riscv_restorefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), restore the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void riscv_restorefpu(const uintptr_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area containing the floating point
+ * registers.
+ *
+ * Returned Value:
+ * This function does not return anything explicitly. However, it is called from
+ * interrupt level assembly logic that assumes that r0 is preserved.
+ *
+ ************************************************************************************/
+
+ .type riscv_restorefpu, function
+
+riscv_restorefpu:
+ LOAD t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_INITIAL
+ ble t2, t1, 1f
+
+ /* Load all floating point registers */
+
+ FLOAD f0, REG_F0(a0)
+ FLOAD f1, REG_F1(a0)
+ FLOAD f2, REG_F2(a0)
+ FLOAD f3, REG_F3(a0)
+ FLOAD f4, REG_F4(a0)
+ FLOAD f5, REG_F5(a0)
+ FLOAD f6, REG_F6(a0)
+ FLOAD f7, REG_F7(a0)
+ FLOAD f8, REG_F8(a0)
+ FLOAD f9, REG_F9(a0)
+ FLOAD f10, REG_F10(a0)
+ FLOAD f11, REG_F11(a0)
+ FLOAD f12, REG_F12(a0)
+ FLOAD f13, REG_F13(a0)
+ FLOAD f14, REG_F14(a0)
+ FLOAD f15, REG_F15(a0)
+ FLOAD f16, REG_F16(a0)
+ FLOAD f17, REG_F17(a0)
+ FLOAD f18, REG_F18(a0)
+ FLOAD f19, REG_F19(a0)
+ FLOAD f20, REG_F20(a0)
+ FLOAD f21, REG_F21(a0)
+ FLOAD f22, REG_F22(a0)
+ FLOAD f23, REG_F23(a0)
+ FLOAD f24, REG_F24(a0)
+ FLOAD f25, REG_F25(a0)
+ FLOAD f26, REG_F26(a0)
+ FLOAD f27, REG_F27(a0)
+ FLOAD f28, REG_F28(a0)
+ FLOAD f29, REG_F29(a0)
+ FLOAD f30, REG_F30(a0)
+ FLOAD f31, REG_F31(a0)
+
+ /* Store the floating point control and status register */
+
+ LOAD t0, REG_FCSR(a0)
+ fscsr t0
+
+1:
+ ret
+
+#endif /* CONFIG_ARCH_FPU */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/start.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/start.S
new file mode 100644
index 00000000..b2d73760
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/start.S
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2016-2020 Bouffalo Lab
+ */
+#include
+
+ .section .init
+ .align 2
+ .globl __start
+ .type __start, %function
+__start:
+.option push
+.option norelax
+ la gp, __global_pointer$
+.option pop
+
+ li t0, MSTATUS_MIE | MSTATUS_SIE
+ csrc mstatus, t0
+
+ /* mapbaddr */
+ /* ? clear PLIC ?*/
+ csrr t1, 0xfc1
+ li t2, 0x00200004
+ add t2, t2, t1
+ lw t3, 0(t2)
+ sw t3, 0(t2)
+ li t4, 0x00201004
+ add t2, t4, t1
+ lw t3, 0(t2)
+ sw t3, 0(t2)
+
+ csrw mie, zero
+ csrw mip, zero
+
+ /* invalid all MMU TLB Entry */
+ sfence.vma x0,x0
+
+ /* TODO: debug */
+ csrw mcycle, zero
+ csrw minstret, zero
+
+ /*
+ * enable thead ISA extension:
+ * THEADISAEE = 1, MM = 1,
+ */
+ csrr t0, mxstatus
+ li t1, (1 << 22) | (1 << 15)
+ or t1, t1, t0
+ csrw mxstatus, t1
+
+ /* FP: initial state */
+ csrr t0, mstatus
+ li t1, ~0x6000
+ and t0, t0, t1
+ li t1, 0x2000
+ or t0, t0, t1
+ csrw mstatus, t0
+ /* csrwi fcsr, 0 */
+
+ /* RVV: initial state */
+ li t0, ~(3 << 23)
+ csrr t1, mstatus
+ and t2, t1, t0
+ li t0, 1 << 23
+ or t2, t2, t0
+ csrw mstatus, t2
+
+ la a0, __Vectors__
+ ori a0, a0, 1
+ csrw mtvec, a0
+
+ la a0, __Vectors_S__
+ ori a0, a0, 1
+ csrw stvec, a0
+
+ .weak __StackTop
+ la sp, __StackTop
+ csrw mscratch, sp
+
+ jal SystemInit
+
+ /* start load code to itcm like. */
+ jal start_load
+
+ jal System_Post_Init
+
+ jal main
+
+ .size __start, . - __start
+
+__exit:
+ j __exit
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/start_load.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/start_load.c
new file mode 100644
index 00000000..12adf18a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/start_load.c
@@ -0,0 +1,84 @@
+#include
+
+#define __STARTUP_CLEAR_BSS 1
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __itcm_load_addr;
+extern uint32_t __dtcm_load_addr;
+extern uint32_t __system_ram_load_addr;
+extern uint32_t __ram_load_addr;
+extern uint32_t __nocache_ram_load_addr;
+
+extern uint32_t __text_code_start__;
+extern uint32_t __text_code_end__;
+extern uint32_t __tcm_code_start__;
+extern uint32_t __tcm_code_end__;
+extern uint32_t __tcm_data_start__;
+extern uint32_t __tcm_data_end__;
+extern uint32_t __ram_data_start__;
+extern uint32_t __ram_data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __noinit_data_start__;
+extern uint32_t __noinit_data_end__;
+extern uint32_t __nocache_ram_data_start__;
+extern uint32_t __nocache_ram_data_end__;
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+//extern uint32_t __copy_table_start__;
+//extern uint32_t __copy_table_end__;
+//extern uint32_t __zero_table_start__;
+//extern uint32_t __zero_table_end__;
+
+void start_load(void)
+{
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+ /* Copy ITCM code */
+ pSrc = &__itcm_load_addr;
+ pDest = &__tcm_code_start__;
+
+ for (; pDest < &__tcm_code_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* Copy DTCM code */
+ pSrc = &__dtcm_load_addr;
+ pDest = &__tcm_data_start__;
+
+ for (; pDest < &__tcm_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* BF Add OCARAM data copy */
+ pSrc = &__ram_load_addr;
+ pDest = &__ram_data_start__;
+
+ for (; pDest < &__ram_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+#ifdef __STARTUP_CLEAR_BSS
+ /* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for (; pDest < &__bss_end__;) {
+ *pDest++ = 0ul;
+ }
+
+#endif
+}
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/system_bl808.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/system_bl808.c
new file mode 100644
index 00000000..f4f940a7
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/system_bl808.c
@@ -0,0 +1,56 @@
+#include "bl808_clock.h"
+#include "bl808_ef_cfg.h"
+
+#define BL808_B0 (0x0)
+#define BL808_B1 (0x1)
+
+void SystemInit(void)
+{
+ uintptr_t tmpVal = 0;
+
+ while ((BL_RD_WORD(IPC_SYNC_ADDR1) != IPC_SYNC_FLAG) ||
+ (BL_RD_WORD(IPC_SYNC_ADDR2) != IPC_SYNC_FLAG)) {
+ // clang-format off
+ __NOP(); __NOP(); __NOP(); __NOP();
+ __NOP(); __NOP(); __NOP(); __NOP();
+ __NOP(); __NOP(); __NOP(); __NOP();
+ __NOP(); __NOP(); __NOP(); __NOP();
+ // clang-format on
+ /* if cache is off, comment this and this api need to start load itcm*/
+ // L1C_DCache_Invalid_By_Addr(IPC_SYNC_ADDR1, 8);
+ };
+ /* clear this flags for system reboot */
+ BL_WR_WORD(IPC_SYNC_ADDR1, 0x0);
+ BL_WR_WORD(IPC_SYNC_ADDR2, 0x0);
+
+ /* turn on cache to speed up boot sequence */
+ csi_icache_enable();
+ csi_dcache_enable();
+
+ /* enable I/D Cache preload. */
+ tmpVal = __get_MHINT();
+ tmpVal |= (1 << 8) | (1 << 2);
+ /* clear AMR */
+ tmpVal &= (~0x18);
+ __set_MHINT(tmpVal);
+}
+
+void System_Post_Init(void)
+{
+ csi_dcache_clean();
+ csi_icache_invalid();
+
+ /* fix amr setting */
+ uintptr_t tmpVal = 0;
+ bflb_efuse_device_info_type chip_info;
+ bflb_ef_ctrl_get_device_info(&chip_info);
+ /* if not B0 enable AMR */
+ if (chip_info.chipInfo != BL808_B0) {
+ tmpVal = __get_MHINT();
+ tmpVal |= (1 << 3);
+ __set_MHINT(tmpVal);
+ }
+
+ /* global IRQ enable */
+ __enable_irq();
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/vector.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/vector.S
new file mode 100644
index 00000000..42102d13
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/d0/vector.S
@@ -0,0 +1,724 @@
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+/* Enable interrupts when returning from the handler */
+#define MSTATUS_PRV1 0x0080
+#define SSTATUS_PRV1 0x0020
+
+.section .text
+ .align 6
+ .globl __Vectors__
+ .type __Vectors__, @object
+__Vectors__:
+.option push
+.option norvc
+ j exception_common /* 0 */
+ j Stspend_Handler /* 1 */
+ j Default_Handler /* 2 */
+#if defined(__OS_FREERTOS__)
+ j Mtspend_Handler /* 3 */
+#else
+ j M_SoftIRQ_ISR /* 3 : Machine Software Interrupt */
+#endif
+ j Default_Handler /* 4 */
+ j Scoret_Handler /* 5 */
+ j Default_Handler /* 6 */
+ j Mcoret_Handler /* 7 */
+ j Default_Handler /* 8 */
+ j Sirq_Handler_M /* 9 */
+ j Default_Handler /* 10 */
+ j Default_IRQHandler /* 11 */
+ j Default_Handler /* 12 */
+ j Default_Handler /* 13 */
+ j Default_Handler /* 14 */
+ j Default_Handler /* 15 */
+ j Default_Handler /* 16 */
+ j HPM_OVF_IRQHandler /* 17 */
+.option pop
+
+.section .text
+ .align 6
+ .globl __Vectors_S__
+ .type __Vectors_S__, @object
+__Vectors_S__:
+.option push
+.option norvc
+ j exception_common /* 0 */
+ j Stspend_Handler_S /* 1 */
+ j Default_Handler /* 2 */
+ j M_SoftIRQ_ISR /* 3 */
+ j Default_Handler /* 4 */
+ j Scoret_Handler /* 5 */
+ j Default_Handler /* 6 */
+ j Mcoret_Handler /* 7 */
+ j Default_Handler /* 8 */
+ j Sirq_Handler /* 9 */
+ j Default_Handler /* 10 */
+ j Default_IRQHandler /* 11 */
+ j Default_Handler /* 12 */
+ j Default_Handler /* 13 */
+ j Default_Handler /* 14 */
+ j Default_Handler /* 15 */
+ j Default_Handler /* 16 */
+ j HPM_OVF_IRQHandler /* 17 */
+.option pop
+
+.section .bss.vector.g_trap_stack
+ .align 4
+ .globl g_trapstackalloc
+ .global g_trapstackbase
+ .global g_top_trapstack
+g_trapstackalloc:
+g_trapstackbase:
+ .space 2048 /* 32I(64bit) + 32D(64bit) + 32V(128bit) */
+g_top_trapstack:
+g_trap_sp:
+
+irq_nested_level:
+.long 0
+
+.text
+
+ .align 2
+ .global Scoret_Handler
+ .weak Scoret_Handler
+ .type Scoret_Handler, %function
+Scoret_Handler:
+ j Stspend_Handler
+
+ .align 2
+ .global Mcoret_Handler
+ .weak Mcoret_Handler
+ .type Mcoret_Handler, %function
+Mcoret_Handler:
+ addi sp, sp, -(76+76)
+ sd t0, (4+4)(sp)
+ sd t1, (8+8)(sp)
+ sd t2, (12+12)(sp)
+
+ csrr t0, mepc
+ sd t0, (68+68)(sp)
+ sd t2, (72+72)(sp)
+ sd ra, (0 +0 )(sp)
+ sd a0, (16+16)(sp)
+ sd a1, (20+20)(sp)
+ sd a2, (24+24)(sp)
+ sd a3, (28+28)(sp)
+ sd a4, (32+32)(sp)
+ sd a5, (36+36)(sp)
+ sd a6, (40+40)(sp)
+ sd a7, (44+44)(sp)
+ sd t3, (48+48)(sp)
+ sd t4, (52+52)(sp)
+ sd t5, (56+56)(sp)
+ sd t6, (60+60)(sp)
+
+ addi sp, sp, -160
+ fsd ft0, (0 +0 )(sp)
+ fsd ft1, (4 +4 )(sp)
+ fsd ft2, (8 +8 )(sp)
+ fsd ft3, (12+12)(sp)
+ fsd ft4, (16+16)(sp)
+ fsd ft5, (20+20)(sp)
+ fsd ft6, (24+24)(sp)
+ fsd ft7, (28+28)(sp)
+ fsd fa0, (32+32)(sp)
+ fsd fa1, (36+36)(sp)
+ fsd fa2, (40+40)(sp)
+ fsd fa3, (44+44)(sp)
+ fsd fa4, (48+48)(sp)
+ fsd fa5, (52+52)(sp)
+ fsd fa6, (56+56)(sp)
+ fsd fa7, (60+60)(sp)
+ fsd ft8, (64+64)(sp)
+ fsd ft9, (68+68)(sp)
+ fsd ft10,(72+72)(sp)
+ fsd ft11,(76+76)(sp)
+
+#if defined(__OS_FREERTOS__)
+ la t2, CORET_IRQHandler
+ jalr t2
+#else
+ li a0, 7
+ la t2, interrupt_entry
+ jalr t2
+#endif
+ csrc mstatus, 8
+
+ li t0, MSTATUS_PRV1
+ csrs mstatus, t0
+
+ fld ft0, (0 +0 )(sp)
+ fld ft1, (4 +4 )(sp)
+ fld ft2, (8 +8 )(sp)
+ fld ft3, (12+12)(sp)
+ fld ft4, (16+16)(sp)
+ fld ft5, (20+20)(sp)
+ fld ft6, (24+24)(sp)
+ fld ft7, (28+28)(sp)
+ fld fa0, (32+32)(sp)
+ fld fa1, (36+36)(sp)
+ fld fa2, (40+40)(sp)
+ fld fa3, (44+44)(sp)
+ fld fa4, (48+48)(sp)
+ fld fa5, (52+52)(sp)
+ fld fa6, (56+56)(sp)
+ fld fa7, (60+60)(sp)
+ fld ft8, (64+64)(sp)
+ fld ft9, (68+68)(sp)
+ fld ft10,(72+72)(sp)
+ fld ft11,(76+76)(sp)
+
+ addi sp, sp, 160
+
+ ld t0, (68+68)(sp)
+ csrw mepc, t0
+ ld ra, (0 +0 )(sp)
+ ld t0, (4 +4 )(sp)
+ ld t1, (8 +8 )(sp)
+ ld t2, (12+12)(sp)
+ ld a0, (16+16)(sp)
+ ld a1, (20+20)(sp)
+ ld a2, (24+24)(sp)
+ ld a3, (28+28)(sp)
+ ld a4, (32+32)(sp)
+ ld a5, (36+36)(sp)
+ ld a6, (40+40)(sp)
+ ld a7, (44+44)(sp)
+ ld t3, (48+48)(sp)
+ ld t4, (52+52)(sp)
+ ld t5, (56+56)(sp)
+ ld t6, (60+60)(sp)
+
+ addi sp, sp, (76+76)
+ mret
+
+/****************************************************************************
+ * Name: Sirq_Handler
+ ****************************************************************************/
+ /* S-mode external IRQ handler */
+ .align 2
+ .global Sirq_Handler
+ .weak Sirq_Handler
+ .type Sirq_Handler, %function
+Sirq_Handler:
+ addi sp, sp, -(76+76)
+ sd t0, (4+4)(sp)
+ sd t1, (8+8)(sp)
+ sd t2, (12+12)(sp)
+
+ li t0, 0xe0201000
+ lw t2, 4(t0)
+
+ csrr t0, sepc
+ sd t0, (68+68)(sp)
+ sd t2, (72+72)(sp)
+ sd ra, (0 +0 )(sp)
+ sd a0, (16+16)(sp)
+ sd a1, (20+20)(sp)
+ sd a2, (24+24)(sp)
+ sd a3, (28+28)(sp)
+ sd a4, (32+32)(sp)
+ sd a5, (36+36)(sp)
+ sd a6, (40+40)(sp)
+ sd a7, (44+44)(sp)
+ sd t3, (48+48)(sp)
+ sd t4, (52+52)(sp)
+ sd t5, (56+56)(sp)
+ sd t6, (60+60)(sp)
+
+ addi sp, sp, -160
+ fsd ft0, (0 +0 )(sp)
+ fsd ft1, (4 +4 )(sp)
+ fsd ft2, (8 +8 )(sp)
+ fsd ft3, (12+12)(sp)
+ fsd ft4, (16+16)(sp)
+ fsd ft5, (20+20)(sp)
+ fsd ft6, (24+24)(sp)
+ fsd ft7, (28+28)(sp)
+ fsd fa0, (32+32)(sp)
+ fsd fa1, (36+36)(sp)
+ fsd fa2, (40+40)(sp)
+ fsd fa3, (44+44)(sp)
+ fsd fa4, (48+48)(sp)
+ fsd fa5, (52+52)(sp)
+ fsd fa6, (56+56)(sp)
+ fsd fa7, (60+60)(sp)
+ fsd ft8, (64+64)(sp)
+ fsd ft9, (68+68)(sp)
+ fsd ft10,(72+72)(sp)
+ fsd ft11,(76+76)(sp)
+
+ andi t2, t2, 0x3FF
+ mv a0, t2
+ slli t2, t2, 3
+
+ la t2, interrupt_entry
+ jalr t2
+
+ csrc sstatus, 2
+
+
+ /* write PLIC_CLAIM and exit interrupt */
+ lw a1, (72+72+160)(sp)
+ andi a0, a1, 0x3FF
+
+ li a2, 0xe0201000
+ sw a0, 4(a2)
+
+ li t0, SSTATUS_PRV1
+ csrs sstatus, t0
+
+ fld ft0, (0 +0 )(sp)
+ fld ft1, (4 +4 )(sp)
+ fld ft2, (8 +8 )(sp)
+ fld ft3, (12+12)(sp)
+ fld ft4, (16+16)(sp)
+ fld ft5, (20+20)(sp)
+ fld ft6, (24+24)(sp)
+ fld ft7, (28+28)(sp)
+ fld fa0, (32+32)(sp)
+ fld fa1, (36+36)(sp)
+ fld fa2, (40+40)(sp)
+ fld fa3, (44+44)(sp)
+ fld fa4, (48+48)(sp)
+ fld fa5, (52+52)(sp)
+ fld fa6, (56+56)(sp)
+ fld fa7, (60+60)(sp)
+ fld ft8, (64+64)(sp)
+ fld ft9, (68+68)(sp)
+ fld ft10,(72+72)(sp)
+ fld ft11,(76+76)(sp)
+
+ addi sp, sp, 160
+
+ ld t0, (68+68)(sp)
+ csrw sepc, t0
+ ld ra, (0 +0 )(sp)
+ ld t0, (4 +4 )(sp)
+ ld t1, (8 +8 )(sp)
+ ld t2, (12+12)(sp)
+ ld a0, (16+16)(sp)
+ ld a1, (20+20)(sp)
+ ld a2, (24+24)(sp)
+ ld a3, (28+28)(sp)
+ ld a4, (32+32)(sp)
+ ld a5, (36+36)(sp)
+ ld a6, (40+40)(sp)
+ ld a7, (44+44)(sp)
+ ld t3, (48+48)(sp)
+ ld t4, (52+52)(sp)
+ ld t5, (56+56)(sp)
+ ld t6, (60+60)(sp)
+
+ addi sp, sp, (76+76)
+ sret
+
+/****************************************************************************
+ * Name: Sirq_Handler_M
+ ****************************************************************************/
+ /* Sirq in M-Mode will be handled here */
+ /* 1. IRQ is enabled in PLIC for S-Mode */
+ /* 2. No IRQ delegation */
+ .align 2
+ .global Sirq_Handler_M
+ .weak Sirq_Handler_M
+ .type Sirq_Handler_M, %function
+Sirq_Handler_M:
+ addi sp, sp, -(76+76)
+ sd t0, (4+4)(sp)
+ sd t1, (8+8)(sp)
+ sd t2, (12+12)(sp)
+
+ csrr t0, 0xfc1
+ li t1, 0x00201000
+ add t0, t0, t1
+ lw t2, 4(t0)
+
+ csrr t0, mepc
+ sd t0, (68+68)(sp)
+ sd t2, (72+72)(sp)
+ sd ra, (0 +0 )(sp)
+ sd a0, (16+16)(sp)
+ sd a1, (20+20)(sp)
+ sd a2, (24+24)(sp)
+ sd a3, (28+28)(sp)
+ sd a4, (32+32)(sp)
+ sd a5, (36+36)(sp)
+ sd a6, (40+40)(sp)
+ sd a7, (44+44)(sp)
+ sd t3, (48+48)(sp)
+ sd t4, (52+52)(sp)
+ sd t5, (56+56)(sp)
+ sd t6, (60+60)(sp)
+
+ addi sp, sp, -160
+ fsd ft0, (0 +0 )(sp)
+ fsd ft1, (4 +4 )(sp)
+ fsd ft2, (8 +8 )(sp)
+ fsd ft3, (12+12)(sp)
+ fsd ft4, (16+16)(sp)
+ fsd ft5, (20+20)(sp)
+ fsd ft6, (24+24)(sp)
+ fsd ft7, (28+28)(sp)
+ fsd fa0, (32+32)(sp)
+ fsd fa1, (36+36)(sp)
+ fsd fa2, (40+40)(sp)
+ fsd fa3, (44+44)(sp)
+ fsd fa4, (48+48)(sp)
+ fsd fa5, (52+52)(sp)
+ fsd fa6, (56+56)(sp)
+ fsd fa7, (60+60)(sp)
+ fsd ft8, (64+64)(sp)
+ fsd ft9, (68+68)(sp)
+ fsd ft10,(72+72)(sp)
+ fsd ft11,(76+76)(sp)
+
+ andi t2, t2, 0x3FF
+ mv a0, t2
+ slli t2, t2, 3
+
+ la t2, interrupt_entry
+ jalr t2
+
+ csrc mstatus, 8
+
+
+ /* write PLIC_CLAIM and exit interrupt */
+ lw a1, (72+72+160)(sp)
+ andi a0, a1, 0x3FF
+
+ csrr a2, 0xfc1
+ li a1, 0x00201000
+ add a2, a2, a1
+ sw a0, 4(a2)
+
+ li t0, MSTATUS_PRV1
+ csrs mstatus, t0
+
+ fld ft0, (0 +0 )(sp)
+ fld ft1, (4 +4 )(sp)
+ fld ft2, (8 +8 )(sp)
+ fld ft3, (12+12)(sp)
+ fld ft4, (16+16)(sp)
+ fld ft5, (20+20)(sp)
+ fld ft6, (24+24)(sp)
+ fld ft7, (28+28)(sp)
+ fld fa0, (32+32)(sp)
+ fld fa1, (36+36)(sp)
+ fld fa2, (40+40)(sp)
+ fld fa3, (44+44)(sp)
+ fld fa4, (48+48)(sp)
+ fld fa5, (52+52)(sp)
+ fld fa6, (56+56)(sp)
+ fld fa7, (60+60)(sp)
+ fld ft8, (64+64)(sp)
+ fld ft9, (68+68)(sp)
+ fld ft10,(72+72)(sp)
+ fld ft11,(76+76)(sp)
+
+ addi sp, sp, 160
+
+ ld t0, (68+68)(sp)
+ csrw mepc, t0
+ ld ra, (0 +0 )(sp)
+ ld t0, (4 +4 )(sp)
+ ld t1, (8 +8 )(sp)
+ ld t2, (12+12)(sp)
+ ld a0, (16+16)(sp)
+ ld a1, (20+20)(sp)
+ ld a2, (24+24)(sp)
+ ld a3, (28+28)(sp)
+ ld a4, (32+32)(sp)
+ ld a5, (36+36)(sp)
+ ld a6, (40+40)(sp)
+ ld a7, (44+44)(sp)
+ ld t3, (48+48)(sp)
+ ld t4, (52+52)(sp)
+ ld t5, (56+56)(sp)
+ ld t6, (60+60)(sp)
+
+ addi sp, sp, (76+76)
+ mret
+
+/****************************************************************************
+ * Name: Default_IRQHandler
+ ****************************************************************************/
+ /* M-mode external IRQ handler */
+ .align 2
+ .global Default_IRQHandler
+ .weak Default_IRQHandler
+ .type Default_IRQHandler, %function
+Default_IRQHandler:
+ addi sp, sp, -(76+76)
+ sd t0, (4+4)(sp)
+ sd t1, (8+8)(sp)
+ sd t2, (12+12)(sp)
+
+ csrr t0, 0xfc1
+ li t1, 0x00200000
+ add t0, t0, t1
+ lw t2, 4(t0)
+
+ csrr t0, mepc
+ sd t0, (68+68)(sp)
+ sd t2, (72+72)(sp)
+ sd ra, (0 +0 )(sp)
+ sd a0, (16+16)(sp)
+ sd a1, (20+20)(sp)
+ sd a2, (24+24)(sp)
+ sd a3, (28+28)(sp)
+ sd a4, (32+32)(sp)
+ sd a5, (36+36)(sp)
+ sd a6, (40+40)(sp)
+ sd a7, (44+44)(sp)
+ sd t3, (48+48)(sp)
+ sd t4, (52+52)(sp)
+ sd t5, (56+56)(sp)
+ sd t6, (60+60)(sp)
+
+ addi sp, sp, -160
+ fsd ft0, (0 +0 )(sp)
+ fsd ft1, (4 +4 )(sp)
+ fsd ft2, (8 +8 )(sp)
+ fsd ft3, (12+12)(sp)
+ fsd ft4, (16+16)(sp)
+ fsd ft5, (20+20)(sp)
+ fsd ft6, (24+24)(sp)
+ fsd ft7, (28+28)(sp)
+ fsd fa0, (32+32)(sp)
+ fsd fa1, (36+36)(sp)
+ fsd fa2, (40+40)(sp)
+ fsd fa3, (44+44)(sp)
+ fsd fa4, (48+48)(sp)
+ fsd fa5, (52+52)(sp)
+ fsd fa6, (56+56)(sp)
+ fsd fa7, (60+60)(sp)
+ fsd ft8, (64+64)(sp)
+ fsd ft9, (68+68)(sp)
+ fsd ft10,(72+72)(sp)
+ fsd ft11,(76+76)(sp)
+
+ la t0, irq_nested_level
+ lw t1, 0(t0)
+ addi t1, t1, 1
+ sw t1, 0(t0)
+
+ andi t2, t2, 0x3FF
+ mv a0, t2
+ slli t2, t2, 3
+
+ la t2, interrupt_entry
+ jalr t2
+
+ csrc mstatus, 8
+
+
+ la t0, irq_nested_level
+ lw t1, 0(t0)
+ addi t1, t1, -1
+ sw t1, 0(t0)
+
+ /* write PLIC_CLAIM and exit interrupt */
+ lw a1, (72+72+160)(sp)
+ andi a0, a1, 0x3FF
+
+ csrr a2, 0xfc1
+ li a1, 0x00200000
+ add a2, a2, a1
+ sw a0, 4(a2)
+
+ li t0, MSTATUS_PRV1
+ csrs mstatus, t0
+
+ fld ft0, (0 +0 )(sp)
+ fld ft1, (4 +4 )(sp)
+ fld ft2, (8 +8 )(sp)
+ fld ft3, (12+12)(sp)
+ fld ft4, (16+16)(sp)
+ fld ft5, (20+20)(sp)
+ fld ft6, (24+24)(sp)
+ fld ft7, (28+28)(sp)
+ fld fa0, (32+32)(sp)
+ fld fa1, (36+36)(sp)
+ fld fa2, (40+40)(sp)
+ fld fa3, (44+44)(sp)
+ fld fa4, (48+48)(sp)
+ fld fa5, (52+52)(sp)
+ fld fa6, (56+56)(sp)
+ fld fa7, (60+60)(sp)
+ fld ft8, (64+64)(sp)
+ fld ft9, (68+68)(sp)
+ fld ft10,(72+72)(sp)
+ fld ft11,(76+76)(sp)
+
+ addi sp, sp, 160
+
+ ld t0, (68+68)(sp)
+ csrw mepc, t0
+ ld ra, (0 +0 )(sp)
+ ld t0, (4 +4 )(sp)
+ ld t1, (8 +8 )(sp)
+ ld t2, (12+12)(sp)
+ ld a0, (16+16)(sp)
+ ld a1, (20+20)(sp)
+ ld a2, (24+24)(sp)
+ ld a3, (28+28)(sp)
+ ld a4, (32+32)(sp)
+ ld a5, (36+36)(sp)
+ ld a6, (40+40)(sp)
+ ld a7, (44+44)(sp)
+ ld t3, (48+48)(sp)
+ ld t4, (52+52)(sp)
+ ld t5, (56+56)(sp)
+ ld t6, (60+60)(sp)
+
+ addi sp, sp, (76+76)
+ mret
+
+/****************************************************************************
+ * Name: exception_common
+ ****************************************************************************/
+ .align 6
+ .weak exception_common
+ .global exception_common
+ .global Default_Handler
+ .type exception_common, %function
+
+Default_Handler:
+exception_common:
+
+ addi sp, sp, -XCPTCONTEXT_SIZE
+
+ sd x1, REG_X1(sp) /* ra */
+ /* sd x3, REG_X3(sp) */ /* gp */
+ sd x4, REG_X4(sp) /* tp */
+ sd x5, REG_X5(sp) /* t0 */
+ sd x6, REG_X6(sp) /* t1 */
+ sd x7, REG_X7(sp) /* t2 */
+ sd x8, REG_X8(sp) /* s0 */
+ sd x9, REG_X9(sp) /* s1 */
+ sd x10, REG_X10(sp) /* a0 */
+ sd x11, REG_X11(sp) /* a1 */
+ sd x12, REG_X12(sp) /* a2 */
+ sd x13, REG_X13(sp) /* a3 */
+ sd x14, REG_X14(sp) /* a4 */
+ sd x15, REG_X15(sp) /* a5 */
+ sd x16, REG_X16(sp) /* a6 */
+ sd x17, REG_X17(sp) /* a7 */
+ sd x18, REG_X18(sp) /* s2 */
+ sd x19, REG_X19(sp) /* s3 */
+ sd x20, REG_X20(sp) /* s4 */
+ sd x21, REG_X21(sp) /* s5 */
+ sd x22, REG_X22(sp) /* s6 */
+ sd x23, REG_X23(sp) /* s7 */
+ sd x24, REG_X24(sp) /* s8 */
+ sd x25, REG_X25(sp) /* s9 */
+ sd x26, REG_X26(sp) /* s10 */
+ sd x27, REG_X27(sp) /* s11 */
+ sd x28, REG_X28(sp) /* t3 */
+ sd x29, REG_X29(sp) /* t4 */
+ sd x30, REG_X30(sp) /* t5 */
+ sd x31, REG_X31(sp) /* t6 */
+
+ csrr s0, mstatus
+ sd s0, REG_INT_CTX(sp) /* mstatus */
+
+ addi s0, sp, XCPTCONTEXT_SIZE
+ sd s0, REG_X2(sp) /* original SP */
+
+ /* Setup arg0(exception cause), arg1(context) */
+
+ csrr a0, mcause /* exception cause */
+ csrr s0, mepc
+ sd s0, REG_EPC(sp) /* exception PC */
+
+ mv a1, sp /* context = sp */
+
+ la sp, g_trap_sp
+
+ /* Call interrupt handler in C */
+
+ jal x1, trap_c
+
+ /* If context switch is needed, return a new sp */
+
+ mv sp, a0
+ ld s0, REG_EPC(sp) /* restore mepc */
+ csrw mepc, s0
+
+ ld s0, REG_INT_CTX(sp) /* restore mstatus */
+ csrw mstatus, s0
+
+ /* ld x3, REG_X3(sp) */ /* gp */
+ ld x4, REG_X4(sp) /* tp */
+ ld x5, REG_X5(sp) /* t0 */
+ ld x6, REG_X6(sp) /* t1 */
+ ld x7, REG_X7(sp) /* t2 */
+ ld x8, REG_X8(sp) /* s0 */
+ ld x9, REG_X9(sp) /* s1 */
+ ld x10, REG_X10(sp) /* a0 */
+ ld x11, REG_X11(sp) /* a1 */
+ ld x12, REG_X12(sp) /* a2 */
+ ld x13, REG_X13(sp) /* a3 */
+ ld x14, REG_X14(sp) /* a4 */
+ ld x15, REG_X15(sp) /* a5 */
+ ld x16, REG_X16(sp) /* a6 */
+ ld x17, REG_X17(sp) /* a7 */
+ ld x18, REG_X18(sp) /* s2 */
+ ld x19, REG_X19(sp) /* s3 */
+ ld x20, REG_X20(sp) /* s4 */
+ ld x21, REG_X21(sp) /* s5 */
+ ld x22, REG_X22(sp) /* s6 */
+ ld x23, REG_X23(sp) /* s7 */
+ ld x24, REG_X24(sp) /* s8 */
+ ld x25, REG_X25(sp) /* s9 */
+ ld x26, REG_X26(sp) /* s10 */
+ ld x27, REG_X27(sp) /* s11 */
+ ld x28, REG_X28(sp) /* t3 */
+ ld x29, REG_X29(sp) /* t4 */
+ ld x30, REG_X30(sp) /* t5 */
+ ld x31, REG_X31(sp) /* t6 */
+
+ ld x1, REG_X1(sp) /* ra */
+
+ ld sp, REG_X2(sp) /* restore original sp */
+
+ /* Return from Machine Interrupt */
+
+ mret
+
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .globl \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler Stspend_Handler
+ def_irq_handler Stspend_Handler_S
+ def_irq_handler Mtspend_Handler
+ def_irq_handler M_SoftIRQ_ISR
+ def_irq_handler CORET_IRQHandler
+ def_irq_handler STIM0_IRQHandler
+ def_irq_handler STIM1_IRQHandler
+ def_irq_handler STIM2_IRQHandler
+ def_irq_handler STIM3_IRQHandler
+ def_irq_handler TIM0_IRQHandler
+ def_irq_handler TIM1_IRQHandler
+ def_irq_handler TIM2_IRQHandler
+ def_irq_handler TIM3_IRQHandler
+ def_irq_handler USART_IRQHandler
+ def_irq_handler GPIO0_IRQHandler
+ def_irq_handler GPIO1_IRQHandler
+ def_irq_handler GPIO2_IRQHandler
+ def_irq_handler GPIO3_IRQHandler
+ def_irq_handler GPIO4_IRQHandler
+ def_irq_handler GPIO5_IRQHandler
+ def_irq_handler GPIO6_IRQHandler
+ def_irq_handler GPIO7_IRQHandler
+ def_irq_handler PAD_IRQHandler
+ def_irq_handler HPM_OVF_IRQHandler
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/interrupt.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/interrupt.c
new file mode 100644
index 00000000..a9a4275d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/interrupt.c
@@ -0,0 +1,206 @@
+/**
+ * @file interrupt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bflb_core.h"
+#include
+#include "irq_ctx.h"
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
+
+extern void default_trap_handler(void);
+extern void default_interrupt_handler(void);
+
+const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* 3: M-mode Soft IRQ */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* 7: M-mode Timer IRQ */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+
+ default_interrupt_handler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */
+ default_interrupt_handler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */
+ default_interrupt_handler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */
+ default_interrupt_handler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */
+ default_interrupt_handler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */
+ default_interrupt_handler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */
+ default_interrupt_handler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */
+ default_interrupt_handler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */
+ default_interrupt_handler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */
+ default_interrupt_handler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */
+ default_interrupt_handler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */
+ default_interrupt_handler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */
+ default_interrupt_handler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */
+ default_interrupt_handler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */
+ default_interrupt_handler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */
+ default_interrupt_handler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */
+ default_interrupt_handler, //0, /* 16 + 16 */
+ default_interrupt_handler, //0, /* 16 + 17 */
+ default_interrupt_handler, //0, /* 16 + 18 */
+ default_interrupt_handler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */
+ default_interrupt_handler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */
+ default_interrupt_handler, //0, /* 16 + 21 */
+ default_interrupt_handler, //0, /* 16 + 22 */
+ default_interrupt_handler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */
+ default_interrupt_handler, //0, /* 16 + 24 */
+ default_interrupt_handler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */
+ default_interrupt_handler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */
+ default_interrupt_handler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */
+ default_interrupt_handler, //0, /* 16 + 28 */
+ default_interrupt_handler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */
+ default_interrupt_handler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */
+ default_interrupt_handler, //0, /* 16 + 31 */
+ default_interrupt_handler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */
+ default_interrupt_handler, //0, /* 16 + 33 */
+ default_interrupt_handler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */
+ default_interrupt_handler, //0, /* 16 + 35 */
+ default_interrupt_handler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */
+ default_interrupt_handler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */
+ default_interrupt_handler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */
+ default_interrupt_handler, //0, /* 16 + 39 */
+ default_interrupt_handler, //0, /* 16 + 40 */
+ default_interrupt_handler, //0, /* 16 + 41 */
+ default_interrupt_handler, //0, /* 16 + 42 */
+ default_interrupt_handler, //0, /* 16 + 43 */
+ default_interrupt_handler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */
+ default_interrupt_handler, //0, /* 16 + 45 */
+ default_interrupt_handler, //0, /* 16 + 46 */
+ default_interrupt_handler, //0, /* 16 + 47 */
+ default_interrupt_handler, //0, /* 16 + 48 */
+ default_interrupt_handler, //0, /* 16 + 49 */
+ default_interrupt_handler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */
+ default_interrupt_handler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */
+ default_interrupt_handler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */
+ default_interrupt_handler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */
+ default_interrupt_handler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */
+ default_interrupt_handler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */
+ default_interrupt_handler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */
+ default_interrupt_handler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */
+ default_interrupt_handler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */
+ default_interrupt_handler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */
+ default_interrupt_handler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */
+ default_interrupt_handler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */
+ default_interrupt_handler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */
+ default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */
+};
+
+void exception_entry(uintptr_t *regs)
+{
+ unsigned long cause;
+ unsigned long epc;
+ unsigned long tval;
+
+ printf("exception_entry\r\n");
+
+ cause = READ_CSR(CSR_MCAUSE);
+ printf("mcause=%08x\r\n", (int)cause);
+ epc = READ_CSR(CSR_MEPC);
+ printf("mepc:%08x\r\n", (int)epc);
+ tval = READ_CSR(CSR_MTVAL);
+ printf("mtval:%08x\r\n", (int)tval);
+
+ cause = (cause & 0x3ff);
+
+ const char *mcause_str[] = {
+ "Instruction address misaligned",
+ "Instruction access fault",
+ "Illegal instruction",
+ "Breakpoint",
+ "Load address misaligned",
+ "Load access fault",
+ "Store/AMO address misaligned",
+ "Store/AMO access fault",
+ "Environment call from U-mode",
+ "Environment call from S-mode",
+ "RSVD",
+ "Environment call from M-mode",
+ "Instruction page fault",
+ "Load page fault",
+ "RSVD",
+ "Store/AMO page fault"
+ };
+
+ printf("%s\r\n", mcause_str[cause & 0xf]);
+// clang-format off
+#ifdef CONFIG_TRAP_DUMP_ALL_REGS
+ printf("ra = 0x%08x ", regs[REG_RA]); printf("sp = 0x%08x ", regs[REG_SP]); printf("gp = 0x%08x ", regs[REG_GP]);
+ printf("tp = 0x%08x ", regs[REG_TP]); printf("\n\r");
+
+ printf("t0 = 0x%08x ", regs[REG_T0]); printf("t1 = 0x%08x ", regs[REG_T1]); printf("t2 = 0x%08x ", regs[REG_T2]);
+ printf("t3 = 0x%08x ", regs[REG_T3]); printf("\n\r");
+ printf("t4 = 0x%08x ", regs[REG_T4]); printf("t5 = 0x%08x ", regs[REG_T5]); printf("t6 = 0x%08x ", regs[REG_T6]);
+ printf("\n\r");
+
+ printf("a0 = 0x%08x ", regs[REG_A0]); printf("a1 = 0x%08x ", regs[REG_A1]); printf("a2 = 0x%08x ", regs[REG_A2]);
+ printf("a3 = 0x%08x ", regs[REG_A3]); printf("\n\r");
+ printf("a4 = 0x%08x ", regs[REG_A4]); printf("a5 = 0x%08x ", regs[REG_A5]); printf("a6 = 0x%08x ", regs[REG_A6]);
+ printf("a7 = 0x%08x ", regs[REG_A7]); printf("\n\r");
+
+ printf("s0 = 0x%08x ", regs[REG_S0]); printf("s1 = 0x%08x ", regs[REG_S1]); printf("s2 = 0x%08x ", regs[REG_S2]);
+ printf("s3 = 0x%08x ", regs[REG_S3]); printf("\n\r");
+ printf("s4 = 0x%08x ", regs[REG_S4]); printf("s5 = 0x%08x ", regs[REG_S5]); printf("s6 = 0x%08x ", regs[REG_S6]);
+ printf("s7 = 0x%08x ", regs[REG_S7]); printf("\n\r");
+ printf("s8 = 0x%08x ", regs[REG_S8]); printf("s9 = 0x%08x ", regs[REG_S9]); printf("s10 = 0x%08x ", regs[REG_S10]);
+ printf("s11 = 0x%08x ", regs[REG_S11]); printf("\n\r");
+#endif
+ // clang-format on
+ if ((cause == 8) || (cause == 11)) {
+ epc += 4;
+ WRITE_CSR(CSR_MEPC, epc);
+ } else {
+ while (1) {
+ }
+ }
+}
+
+void interrupt_entry(void)
+{
+ irq_callback handler;
+ void *arg;
+ volatile uint32_t mcause = 0UL;
+ uint32_t irq_num;
+
+ mcause = READ_CSR(CSR_MCAUSE);
+ irq_num = mcause & 0x3FF;
+
+ if (irq_num < CONFIG_IRQ_NUM) {
+ handler = g_irqvector[irq_num].handler;
+ arg = g_irqvector[irq_num].arg;
+ if (handler) {
+ handler(irq_num, arg);
+ } else {
+ }
+ } else {
+ }
+}
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/irq_ctx.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/irq_ctx.h
new file mode 100644
index 00000000..4c9bc7dd
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/irq_ctx.h
@@ -0,0 +1,372 @@
+#ifndef __IRQ_CTX_H__
+#define __IRQ_CTX_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Processor PC */
+
+#define REG_EPC_NDX 0
+
+/* General pupose registers
+ * $0: Zero register does not need to be saved
+ * $1: ra (return address)
+ */
+
+#define REG_X1_NDX 1
+
+/* $2: Stack POinter
+ * $3: Global Pointer
+ * $4: Thread Pointer
+ */
+
+#define REG_X2_NDX 2
+#define REG_X3_NDX 3
+#define REG_X4_NDX 4
+
+/* $5-$7 = t0-t3: Temporary registers */
+
+#define REG_X5_NDX 5
+#define REG_X6_NDX 6
+#define REG_X7_NDX 7
+
+/* $8: s0 / fp Frame pointer */
+
+#define REG_X8_NDX 8
+
+/* $89 s1 Saved register */
+
+#define REG_X9_NDX 9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_X10_NDX 10
+#define REG_X11_NDX 11
+#define REG_X12_NDX 12
+#define REG_X13_NDX 13
+#define REG_X14_NDX 14
+#define REG_X15_NDX 15
+#define REG_X16_NDX 16
+#define REG_X17_NDX 17
+
+/* $18-$27 = s2-s11: Saved registers */
+
+#define REG_X18_NDX 18
+#define REG_X19_NDX 19
+#define REG_X20_NDX 20
+#define REG_X21_NDX 21
+#define REG_X22_NDX 22
+#define REG_X23_NDX 23
+#define REG_X24_NDX 24
+#define REG_X25_NDX 25
+#define REG_X26_NDX 26
+#define REG_X27_NDX 27
+
+/* $28-31 = t3-t6: Temporary (Volatile) registers */
+
+#define REG_X28_NDX 28
+#define REG_X29_NDX 29
+#define REG_X30_NDX 30
+#define REG_X31_NDX 31
+
+/* Interrupt Context register */
+
+#define REG_INT_CTX_NDX 32
+
+#define INT_XCPT_REGS 33
+
+#define INT_XCPT_SIZE (4 * INT_XCPT_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+#define FPU_REG_SIZE 1 /* size in uint32_t */
+
+#define REG_F0_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 0)
+#define REG_F1_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 1)
+#define REG_F2_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 2)
+#define REG_F3_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 3)
+#define REG_F4_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 4)
+#define REG_F5_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 5)
+#define REG_F6_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 6)
+#define REG_F7_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 7)
+#define REG_F8_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 8)
+#define REG_F9_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 9)
+#define REG_F10_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 10)
+#define REG_F11_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 11)
+#define REG_F12_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 12)
+#define REG_F13_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 13)
+#define REG_F14_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 14)
+#define REG_F15_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 15)
+#define REG_F16_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 16)
+#define REG_F17_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 17)
+#define REG_F18_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 18)
+#define REG_F19_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 19)
+#define REG_F20_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 20)
+#define REG_F21_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 21)
+#define REG_F22_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 22)
+#define REG_F23_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 23)
+#define REG_F24_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 24)
+#define REG_F25_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 25)
+#define REG_F26_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 26)
+#define REG_F27_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 27)
+#define REG_F28_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 28)
+#define REG_F29_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 29)
+#define REG_F30_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 30)
+#define REG_F31_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 31)
+#define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32)
+
+#define FPU_XCPT_REGS (FPU_REG_SIZE * 33)
+#else
+#define FPU_XCPT_REGS 0
+#endif
+
+#define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS)
+
+#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
+
+/* In assembly language, values have to be referenced as byte address
+ * offsets. But in C, it is more convenient to reference registers as
+ * register save table offsets.
+ */
+
+#ifdef __ASSEMBLY__
+#define REG_EPC (4 * REG_EPC_NDX)
+#define REG_X1 (4 * REG_X1_NDX)
+#define REG_X2 (4 * REG_X2_NDX)
+#define REG_X3 (4 * REG_X3_NDX)
+#define REG_X4 (4 * REG_X4_NDX)
+#define REG_X5 (4 * REG_X5_NDX)
+#define REG_X6 (4 * REG_X6_NDX)
+#define REG_X7 (4 * REG_X7_NDX)
+#define REG_X8 (4 * REG_X8_NDX)
+#define REG_X9 (4 * REG_X9_NDX)
+#define REG_X10 (4 * REG_X10_NDX)
+#define REG_X11 (4 * REG_X11_NDX)
+#define REG_X12 (4 * REG_X12_NDX)
+#define REG_X13 (4 * REG_X13_NDX)
+#define REG_X14 (4 * REG_X14_NDX)
+#define REG_X15 (4 * REG_X15_NDX)
+#define REG_X16 (4 * REG_X16_NDX)
+#define REG_X17 (4 * REG_X17_NDX)
+#define REG_X18 (4 * REG_X18_NDX)
+#define REG_X19 (4 * REG_X19_NDX)
+#define REG_X20 (4 * REG_X20_NDX)
+#define REG_X21 (4 * REG_X21_NDX)
+#define REG_X22 (4 * REG_X22_NDX)
+#define REG_X23 (4 * REG_X23_NDX)
+#define REG_X24 (4 * REG_X24_NDX)
+#define REG_X25 (4 * REG_X25_NDX)
+#define REG_X26 (4 * REG_X26_NDX)
+#define REG_X27 (4 * REG_X27_NDX)
+#define REG_X28 (4 * REG_X28_NDX)
+#define REG_X29 (4 * REG_X29_NDX)
+#define REG_X30 (4 * REG_X30_NDX)
+#define REG_X31 (4 * REG_X31_NDX)
+#define REG_INT_CTX (4 * REG_INT_CTX_NDX)
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0 (4 * REG_F0_NDX)
+#define REG_F1 (4 * REG_F1_NDX)
+#define REG_F2 (4 * REG_F2_NDX)
+#define REG_F3 (4 * REG_F3_NDX)
+#define REG_F4 (4 * REG_F4_NDX)
+#define REG_F5 (4 * REG_F5_NDX)
+#define REG_F6 (4 * REG_F6_NDX)
+#define REG_F7 (4 * REG_F7_NDX)
+#define REG_F8 (4 * REG_F8_NDX)
+#define REG_F9 (4 * REG_F9_NDX)
+#define REG_F10 (4 * REG_F10_NDX)
+#define REG_F11 (4 * REG_F11_NDX)
+#define REG_F12 (4 * REG_F12_NDX)
+#define REG_F13 (4 * REG_F13_NDX)
+#define REG_F14 (4 * REG_F14_NDX)
+#define REG_F15 (4 * REG_F15_NDX)
+#define REG_F16 (4 * REG_F16_NDX)
+#define REG_F17 (4 * REG_F17_NDX)
+#define REG_F18 (4 * REG_F18_NDX)
+#define REG_F19 (4 * REG_F19_NDX)
+#define REG_F20 (4 * REG_F20_NDX)
+#define REG_F21 (4 * REG_F21_NDX)
+#define REG_F22 (4 * REG_F22_NDX)
+#define REG_F23 (4 * REG_F23_NDX)
+#define REG_F24 (4 * REG_F24_NDX)
+#define REG_F25 (4 * REG_F25_NDX)
+#define REG_F26 (4 * REG_F26_NDX)
+#define REG_F27 (4 * REG_F27_NDX)
+#define REG_F28 (4 * REG_F28_NDX)
+#define REG_F29 (4 * REG_F29_NDX)
+#define REG_F30 (4 * REG_F30_NDX)
+#define REG_F31 (4 * REG_F31_NDX)
+#define REG_FCSR (4 * REG_FCSR_NDX)
+#endif
+
+#else
+#define REG_EPC REG_EPC_NDX
+#define REG_X1 REG_X1_NDX
+#define REG_X2 REG_X2_NDX
+#define REG_X3 REG_X3_NDX
+#define REG_X4 REG_X4_NDX
+#define REG_X5 REG_X5_NDX
+#define REG_X6 REG_X6_NDX
+#define REG_X7 REG_X7_NDX
+#define REG_X8 REG_X8_NDX
+#define REG_X9 REG_X9_NDX
+#define REG_X10 REG_X10_NDX
+#define REG_X11 REG_X11_NDX
+#define REG_X12 REG_X12_NDX
+#define REG_X13 REG_X13_NDX
+#define REG_X14 REG_X14_NDX
+#define REG_X15 REG_X15_NDX
+#define REG_X16 REG_X16_NDX
+#define REG_X17 REG_X17_NDX
+#define REG_X18 REG_X18_NDX
+#define REG_X19 REG_X19_NDX
+#define REG_X20 REG_X20_NDX
+#define REG_X21 REG_X21_NDX
+#define REG_X22 REG_X22_NDX
+#define REG_X23 REG_X23_NDX
+#define REG_X24 REG_X24_NDX
+#define REG_X25 REG_X25_NDX
+#define REG_X26 REG_X26_NDX
+#define REG_X27 REG_X27_NDX
+#define REG_X28 REG_X28_NDX
+#define REG_X29 REG_X29_NDX
+#define REG_X30 REG_X30_NDX
+#define REG_X31 REG_X31_NDX
+#define REG_INT_CTX REG_INT_CTX_NDX
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0 REG_F0_NDX
+#define REG_F1 REG_F1_NDX
+#define REG_F2 REG_F2_NDX
+#define REG_F3 REG_F3_NDX
+#define REG_F4 REG_F4_NDX
+#define REG_F5 REG_F5_NDX
+#define REG_F6 REG_F6_NDX
+#define REG_F7 REG_F7_NDX
+#define REG_F8 REG_F8_NDX
+#define REG_F9 REG_F9_NDX
+#define REG_F10 REG_F10_NDX
+#define REG_F11 REG_F11_NDX
+#define REG_F12 REG_F12_NDX
+#define REG_F13 REG_F13_NDX
+#define REG_F14 REG_F14_NDX
+#define REG_F15 REG_F15_NDX
+#define REG_F16 REG_F16_NDX
+#define REG_F17 REG_F17_NDX
+#define REG_F18 REG_F18_NDX
+#define REG_F19 REG_F19_NDX
+#define REG_F20 REG_F20_NDX
+#define REG_F21 REG_F21_NDX
+#define REG_F22 REG_F22_NDX
+#define REG_F23 REG_F23_NDX
+#define REG_F24 REG_F24_NDX
+#define REG_F25 REG_F25_NDX
+#define REG_F26 REG_F26_NDX
+#define REG_F27 REG_F27_NDX
+#define REG_F28 REG_F28_NDX
+#define REG_F29 REG_F29_NDX
+#define REG_F30 REG_F30_NDX
+#define REG_F31 REG_F31_NDX
+#define REG_FCSR REG_FCSR_NDX
+#endif
+
+#endif
+
+/* Now define more user friendly alternative name that can be used either
+ * in assembly or C contexts.
+ */
+
+/* $1 = ra: Return address */
+
+#define REG_RA REG_X1
+
+/* $2 = sp: The value of the stack pointer on return from the exception */
+
+#define REG_SP REG_X2
+
+/* $3 = gp: Only needs to be saved under conditions where there are
+ * multiple, per-thread values for the GP.
+ */
+
+#define REG_GP REG_X3
+
+/* $4 = tp: Thread Pointer */
+
+#define REG_TP REG_X4
+
+/* $5-$7 = t0-t2: Caller saved temporary registers */
+
+#define REG_T0 REG_X5
+#define REG_T1 REG_X6
+#define REG_T2 REG_X7
+
+/* $8 = either s0 or fp: Depends if a frame pointer is used or not */
+
+#define REG_S0 REG_X8
+#define REG_FP REG_X8
+
+/* $9 = s1: Caller saved register */
+
+#define REG_S1 REG_X9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_A0 REG_X10
+#define REG_A1 REG_X11
+#define REG_A2 REG_X12
+#define REG_A3 REG_X13
+#define REG_A4 REG_X14
+#define REG_A5 REG_X15
+#define REG_A6 REG_X16
+#define REG_A7 REG_X17
+
+/* $18-$27 = s2-s11: Callee saved registers */
+
+#define REG_S2 REG_X18
+#define REG_S3 REG_X19
+#define REG_S4 REG_X20
+#define REG_S5 REG_X21
+#define REG_S6 REG_X22
+#define REG_S7 REG_X23
+#define REG_S8 REG_X24
+#define REG_S9 REG_X25
+#define REG_S10 REG_X26
+#define REG_S11 REG_X27
+
+/* $28-$31 = t3-t6: Caller saved temporary registers */
+
+#define REG_T3 REG_X28
+#define REG_T4 REG_X29
+#define REG_T5 REG_X30
+#define REG_T6 REG_X31
+
+#ifndef __ASSEMBLY__
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+# ifdef CONFIG_ARCH_FPU
+ extern void riscv_savefpu(uintptr_t *regs);
+ extern void riscv_restorefpu(uintptr_t *regs);
+# else
+ void riscv_savefpu(uintptr_t *regs) {};
+ void riscv_restorefpu(uintptr_t *regs) {};
+# endif
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __IRQ_CTX_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/riscv_fpu.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/riscv_fpu.S
new file mode 100644
index 00000000..a88e6230
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/riscv_fpu.S
@@ -0,0 +1,221 @@
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+#if defined(CONFIG_ARCH_FPU)
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Symbols
+ ************************************************************************************/
+
+ .globl riscv_fpuconfig
+ .globl riscv_savefpu
+ .globl riscv_savefpu_force
+ .globl riscv_restorefpu
+
+ .file "riscv_fpu.S"
+
+#define FS_MASK 0x6000
+#define FS_OFF 0x0000
+#define FS_INITIAL 0x2000
+#define FS_CLEAN 0x4000
+#define FS_DIRTY 0x6000
+
+#if defined(CONFIG_ARCH_DPFPU)
+# define FLOAD fld
+# define FSTORE fsd
+# define LOAD ld
+# define STORE sd
+#elif defined(CONFIG_ARCH_QPFPU)
+# define FLOAD flq
+# define FSTORE fsq
+#else
+# define FLOAD flw
+# define FSTORE fsw
+# define LOAD lw
+# define STORE sw
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: riscv_fpuconfig
+ *
+ * Description:
+ * init fpu
+ *
+ * C Function Prototype:
+ * void riscv_fpuconfig(void);
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * This function does not return anything explicitly.
+ *
+ ************************************************************************************/
+
+ .type riscv_fpuconfig, function
+
+riscv_fpuconfig:
+ li a0, FS_INITIAL
+ csrs mstatus, a0
+ csrwi fcsr, 0
+ ret
+
+/************************************************************************************
+ * Name: riscv_savefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), save the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void riscv_savefpu(uintptr_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area in which to save the floating point
+ * registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+ .type riscv_savefpu, function
+
+riscv_savefpu:
+ LOAD t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_DIRTY
+ bne t2, t1, 1f
+ li t1, ~FS_MASK
+ and t0, t0, t1
+ li t1, FS_CLEAN
+ or t0, t0, t1
+ STORE t0, REG_INT_CTX(a0)
+
+ /* Store all floating point registers */
+riscv_savefpu_force:
+
+ FSTORE f0, REG_F0(a0)
+ FSTORE f1, REG_F1(a0)
+ FSTORE f2, REG_F2(a0)
+ FSTORE f3, REG_F3(a0)
+ FSTORE f4, REG_F4(a0)
+ FSTORE f5, REG_F5(a0)
+ FSTORE f6, REG_F6(a0)
+ FSTORE f7, REG_F7(a0)
+ FSTORE f8, REG_F8(a0)
+ FSTORE f9, REG_F9(a0)
+ FSTORE f10, REG_F10(a0)
+ FSTORE f11, REG_F11(a0)
+ FSTORE f12, REG_F12(a0)
+ FSTORE f13, REG_F13(a0)
+ FSTORE f14, REG_F14(a0)
+ FSTORE f15, REG_F15(a0)
+ FSTORE f16, REG_F16(a0)
+ FSTORE f17, REG_F17(a0)
+ FSTORE f18, REG_F18(a0)
+ FSTORE f19, REG_F19(a0)
+ FSTORE f20, REG_F20(a0)
+ FSTORE f21, REG_F21(a0)
+ FSTORE f22, REG_F22(a0)
+ FSTORE f23, REG_F23(a0)
+ FSTORE f24, REG_F24(a0)
+ FSTORE f25, REG_F25(a0)
+ FSTORE f26, REG_F26(a0)
+ FSTORE f27, REG_F27(a0)
+ FSTORE f28, REG_F28(a0)
+ FSTORE f29, REG_F29(a0)
+ FSTORE f30, REG_F30(a0)
+ FSTORE f31, REG_F31(a0)
+
+ frcsr t0
+ STORE t0, REG_FCSR(a0)
+
+1:
+ ret
+
+/************************************************************************************
+ * Name: riscv_restorefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), restore the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void riscv_restorefpu(const uintptr_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area containing the floating point
+ * registers.
+ *
+ * Returned Value:
+ * This function does not return anything explicitly. However, it is called from
+ * interrupt level assembly logic that assumes that r0 is preserved.
+ *
+ ************************************************************************************/
+
+ .type riscv_restorefpu, function
+
+riscv_restorefpu:
+ LOAD t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_INITIAL
+ ble t2, t1, 1f
+
+ /* Load all floating point registers */
+
+ FLOAD f0, REG_F0(a0)
+ FLOAD f1, REG_F1(a0)
+ FLOAD f2, REG_F2(a0)
+ FLOAD f3, REG_F3(a0)
+ FLOAD f4, REG_F4(a0)
+ FLOAD f5, REG_F5(a0)
+ FLOAD f6, REG_F6(a0)
+ FLOAD f7, REG_F7(a0)
+ FLOAD f8, REG_F8(a0)
+ FLOAD f9, REG_F9(a0)
+ FLOAD f10, REG_F10(a0)
+ FLOAD f11, REG_F11(a0)
+ FLOAD f12, REG_F12(a0)
+ FLOAD f13, REG_F13(a0)
+ FLOAD f14, REG_F14(a0)
+ FLOAD f15, REG_F15(a0)
+ FLOAD f16, REG_F16(a0)
+ FLOAD f17, REG_F17(a0)
+ FLOAD f18, REG_F18(a0)
+ FLOAD f19, REG_F19(a0)
+ FLOAD f20, REG_F20(a0)
+ FLOAD f21, REG_F21(a0)
+ FLOAD f22, REG_F22(a0)
+ FLOAD f23, REG_F23(a0)
+ FLOAD f24, REG_F24(a0)
+ FLOAD f25, REG_F25(a0)
+ FLOAD f26, REG_F26(a0)
+ FLOAD f27, REG_F27(a0)
+ FLOAD f28, REG_F28(a0)
+ FLOAD f29, REG_F29(a0)
+ FLOAD f30, REG_F30(a0)
+ FLOAD f31, REG_F31(a0)
+
+ /* Store the floating point control and status register */
+
+ LOAD t0, REG_FCSR(a0)
+ fscsr t0
+
+1:
+ ret
+
+#endif /* CONFIG_ARCH_FPU */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/start.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/start.S
new file mode 100644
index 00000000..a9b43f66
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/start.S
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016-2020 Bouffalo Lab
+ */
+
+ .section .init
+ .align 2
+ .globl __start
+ .type __start, %function
+__start:
+.option push
+.option norelax
+ la gp, __global_pointer$
+.option pop
+ csrci mstatus, 8
+
+ /* mtvec: for all exceptions and non-vector mode IRQs */
+ la a0, default_trap_handler
+ ori a0, a0, 3
+ csrw mtvec, a0
+
+ /* mtvt: for all vector mode IRQs */
+ la a0, __Vectors
+ csrw mtvt, a0
+
+ .weak __StackTop
+ la sp, __StackTop
+ csrw mscratch, sp
+
+ /* Load data section removed */
+
+ /* Clear bss section removed */
+
+ jal SystemInit
+
+ /* start load code to itcm like. */
+ jal start_load
+
+ jal System_Post_Init
+
+ jal main
+
+ .size __start, . - __start
+
+__exit:
+ j __exit
+
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/start_load.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/start_load.c
new file mode 100644
index 00000000..f9715fcc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/start_load.c
@@ -0,0 +1,92 @@
+#include
+
+#define __STARTUP_CLEAR_BSS 1
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __itcm_load_addr;
+extern uint32_t __dtcm_load_addr;
+extern uint32_t __system_ram_load_addr;
+extern uint32_t __ram_load_addr;
+extern uint32_t __nocache_ram_load_addr;
+
+extern uint32_t __text_code_start__;
+extern uint32_t __text_code_end__;
+extern uint32_t __tcm_code_start__;
+extern uint32_t __tcm_code_end__;
+extern uint32_t __tcm_data_start__;
+extern uint32_t __tcm_data_end__;
+extern uint32_t __ram_data_start__;
+extern uint32_t __ram_data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __noinit_data_start__;
+extern uint32_t __noinit_data_end__;
+extern uint32_t __nocache_ram_data_start__;
+extern uint32_t __nocache_ram_data_end__;
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+//extern uint32_t __copy_table_start__;
+//extern uint32_t __copy_table_end__;
+//extern uint32_t __zero_table_start__;
+//extern uint32_t __zero_table_end__;
+
+void start_load(void)
+{
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+ /* Copy ITCM code */
+ pSrc = &__itcm_load_addr;
+ pDest = &__tcm_code_start__;
+
+ for (; pDest < &__tcm_code_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* Copy DTCM code */
+ pSrc = &__dtcm_load_addr;
+ pDest = &__tcm_data_start__;
+
+ for (; pDest < &__tcm_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* BF Add OCARAM data copy */
+ pSrc = &__ram_load_addr;
+ pDest = &__ram_data_start__;
+
+ for (; pDest < &__ram_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* BF Add no cache ram data copy */
+ pSrc = &__nocache_ram_load_addr;
+ pDest = &__nocache_ram_data_start__;
+
+ for (; pDest < &__nocache_ram_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+#ifdef __STARTUP_CLEAR_BSS
+ /* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for (; pDest < &__bss_end__;) {
+ *pDest++ = 0ul;
+ }
+
+#endif
+}
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/system_bl808.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/system_bl808.c
new file mode 100644
index 00000000..3daccc9c
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/system_bl808.c
@@ -0,0 +1,24 @@
+#include "bl808.h"
+
+void SystemInit(void)
+{
+ uint32_t i = 0;
+
+ /* get interrupt level from info */
+ CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
+
+ /* Every interrupt should be clear by software*/
+ for (i = 0; i < IRQn_LAST; i++) {
+ CLIC->CLICINT[i].IE = 0;
+ CLIC->CLICINT[i].IP = 0;
+ CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+ }
+
+ CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
+}
+
+void System_Post_Init(void)
+{
+ /* global IRQ enable */
+ __enable_irq();
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/vector.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/vector.S
new file mode 100644
index 00000000..2cbe3bed
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/lp/vector.S
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+ /******************************************************************************
+ * @file vectors.S
+ * @brief define default vector handlers. Should use with
+ * GCC for CSKY Embedded Processors
+ * @version V1.0
+ * @date 28. Nove 2017
+ ******************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+/* Enable interrupts when returning from the handler */
+#define MSTATUS_PRV1 0x1880
+
+.section .bss
+ .align 2
+ .globl g_trapstackalloc
+ .global g_trapstackbase
+ .global g_top_trapstack
+g_trapstackalloc:
+g_trapstackbase:
+ .space 512
+g_top_trapstack:
+
+ .align 2
+ .globl g_trap_sp
+ .type g_trap_sp, object
+g_trap_sp:
+ .long 0
+ .size g_trap_sp, .-g_trap_sp
+
+irq_nested_level:
+.long 0
+
+ .align 2
+ .global default_interrupt_handler
+ .weak default_interrupt_handler
+ .type default_interrupt_handler, %function
+default_interrupt_handler:
+ addi sp, sp, -48
+ sw t0, 4(sp)
+ sw t1, 8(sp)
+ csrr t0, mepc
+ csrr t1, mcause
+ sw t1, 40(sp)
+ sw t0, 44(sp)
+ csrs mstatus, 8
+
+ sw ra, 0(sp)
+ sw t2, 12(sp)
+ sw a0, 16(sp)
+ sw a1, 20(sp)
+ sw a2, 24(sp)
+ sw a3, 28(sp)
+ sw a4, 32(sp)
+ sw a5, 36(sp)
+
+ andi t1, t1, 0x3FF
+ csrw mscratch, t1
+ slli t1, t1, 2
+
+ la t2, interrupt_entry
+ jalr t2
+
+ /* deal N+32 irq */
+ csrr t1, mscratch
+ add t1, t1,32
+ slli t1, t1, 2
+
+ la t2, interrupt_entry
+ jalr t2
+
+ csrc mstatus, 8
+
+ lw a1, 40(sp)
+ andi a0, a1, 0x3FF
+ slli a0, a0, 2
+
+ /* clear pending */
+ li a2, 0xE0801000
+ add a2, a2, a0
+ sb zero, 0(a2)
+
+ li t0, MSTATUS_PRV1
+ csrs mstatus, t0
+ csrw mcause, a1
+ lw t0, 44(sp)
+ csrw mepc, t0
+ lw ra, 0(sp)
+ lw t0, 4(sp)
+ lw t1, 8(sp)
+ lw t2, 12(sp)
+ lw a0, 16(sp)
+ lw a1, 20(sp)
+ lw a2, 24(sp)
+ lw a3, 28(sp)
+ lw a4, 32(sp)
+ lw a5, 36(sp)
+
+ addi sp, sp, 48
+ mret
+
+/******************************************************************************
+ * Functions:
+ * void trap(void);
+ * default exception handler
+ ******************************************************************************/
+ .align 2
+ .global default_trap_handler
+ .type default_trap_handler, %function
+default_trap_handler:
+trap:
+ /* Check for interrupt */
+ addi sp, sp, -4
+ sw t0, 0x0(sp)
+ csrr t0, mcause
+
+ blt t0, x0, .Lirq
+
+ addi sp, sp, 4
+
+ la t0, g_trap_sp
+ addi t0, t0, -XCPTCONTEXT_SIZE
+ sw x1, REG_X1(t0)
+ sw x2, REG_X2(t0)
+ sw x3, REG_X3(t0)
+ sw x4, REG_X4(t0)
+ sw x6, REG_X6(t0)
+ sw x7, REG_X7(t0)
+ sw x8, REG_X8(t0)
+ sw x9, REG_X9(t0)
+ sw x10, REG_X10(t0)
+ sw x11, REG_X11(t0)
+ sw x12, REG_X12(t0)
+ sw x13, REG_X13(t0)
+ sw x14, REG_X14(t0)
+ sw x15, REG_X15(t0)
+ csrr a0, mepc
+ sw a0, REG_EPC(t0)
+ csrr a0, mstatus
+ sw a0, REG_INT_CTX(t0)
+
+ mv a0, t0
+ lw t0, -4(sp)
+ mv sp, a0
+ sw t0, REG_X5(sp)
+
+ jal exception_entry
+
+ lw t0, REG_INT_CTX(sp)
+ csrw mstatus, t0
+ lw t0, REG_EPC(sp)
+ csrw mepc, t0
+
+ lw x15, REG_X15(sp)
+ lw x14, REG_X14(sp)
+ lw x13, REG_X13(sp)
+ lw x12, REG_X12(sp)
+ lw x11, REG_X11(sp)
+ lw x10, REG_X10(sp)
+ lw x9, REG_X9(sp)
+ lw x8, REG_X8(sp)
+ lw x7, REG_X7(sp)
+ lw x6, REG_X6(sp)
+ lw x5, REG_X5(sp)
+ lw x4, REG_X4(sp)
+ lw x3, REG_X3(sp)
+ lw x1, REG_X1(sp)
+ lw x2, REG_X2(sp)
+
+ mret
+
+.Lirq:
+ lw t0, 0x0(sp)
+ addi sp, sp, 4
+ j default_interrupt_handler
+
+ .size default_trap_handler, . - default_trap_handler
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/interrupt.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/interrupt.c
new file mode 100644
index 00000000..8cec10bc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/interrupt.c
@@ -0,0 +1,204 @@
+/**
+ * @file interrupt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bflb_core.h"
+#include
+#include "irq_ctx.h"
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
+
+extern void default_trap_handler(void);
+extern void default_interrupt_handler(void);
+
+const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* 3: M-mode Soft IRQ */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* 7: M-mode Timer IRQ */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+ default_interrupt_handler, /* */
+
+ default_interrupt_handler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */
+ default_interrupt_handler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */
+ default_interrupt_handler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */
+ default_interrupt_handler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */
+ default_interrupt_handler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */
+ default_interrupt_handler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */
+ default_interrupt_handler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */
+ default_interrupt_handler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */
+ default_interrupt_handler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */
+ default_interrupt_handler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */
+ default_interrupt_handler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */
+ default_interrupt_handler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */
+ default_interrupt_handler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */
+ default_interrupt_handler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */
+ default_interrupt_handler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */
+ default_interrupt_handler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */
+ default_interrupt_handler, //0, /* 16 + 16 */
+ default_interrupt_handler, //0, /* 16 + 17 */
+ default_interrupt_handler, //0, /* 16 + 18 */
+ default_interrupt_handler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */
+ default_interrupt_handler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */
+ default_interrupt_handler, //0, /* 16 + 21 */
+ default_interrupt_handler, //0, /* 16 + 22 */
+ default_interrupt_handler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */
+ default_interrupt_handler, //0, /* 16 + 24 */
+ default_interrupt_handler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */
+ default_interrupt_handler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */
+ default_interrupt_handler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */
+ default_interrupt_handler, //0, /* 16 + 28 */
+ default_interrupt_handler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */
+ default_interrupt_handler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */
+ default_interrupt_handler, //0, /* 16 + 31 */
+ default_interrupt_handler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */
+ default_interrupt_handler, //0, /* 16 + 33 */
+ default_interrupt_handler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */
+ default_interrupt_handler, //0, /* 16 + 35 */
+ default_interrupt_handler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */
+ default_interrupt_handler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */
+ default_interrupt_handler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */
+ default_interrupt_handler, //0, /* 16 + 39 */
+ default_interrupt_handler, //0, /* 16 + 40 */
+ default_interrupt_handler, //0, /* 16 + 41 */
+ default_interrupt_handler, //0, /* 16 + 42 */
+ default_interrupt_handler, //0, /* 16 + 43 */
+ default_interrupt_handler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */
+ default_interrupt_handler, //0, /* 16 + 45 */
+ default_interrupt_handler, //0, /* 16 + 46 */
+ default_interrupt_handler, //0, /* 16 + 47 */
+ default_interrupt_handler, //0, /* 16 + 48 */
+ default_interrupt_handler, //0, /* 16 + 49 */
+ default_interrupt_handler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */
+ default_interrupt_handler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */
+ default_interrupt_handler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */
+ default_interrupt_handler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */
+ default_interrupt_handler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */
+ default_interrupt_handler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */
+ default_interrupt_handler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */
+ default_interrupt_handler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */
+ default_interrupt_handler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */
+ default_interrupt_handler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */
+ default_interrupt_handler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */
+ default_interrupt_handler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */
+ default_interrupt_handler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */
+ default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */
+};
+
+__attribute__( ( section( "privileged_functions" ) ) ) void vPrintI (unsigned int a0 )
+{
+ volatile uint32_t mcause = 0UL;
+ volatile uint32_t mstatus = 0UL;
+ volatile uint32_t reg_a0;
+
+ __asm__ volatile ("mv %0, a0" : "=r" (reg_a0)); // Копіюємо значення з a0 у змінну value
+
+ mstatus = READ_CSR(CSR_MSTATUS);
+ printf("\r\nmstatusI=%08x\r\n", (int)mstatus);
+ mcause = READ_CSR(CSR_MCAUSE);
+ printf("%08x\r\n", (int)mcause);
+ printf("%08x\r\n", reg_a0);
+}
+// void exception_entry(uintptr_t *regs)
+void exception_entry(void)
+{
+ unsigned long cause;
+ unsigned long epc;
+ unsigned long tval;
+
+ cause = READ_CSR(CSR_MCAUSE);
+ printf("mcause=%08x\r\n", (int)cause);
+ epc = READ_CSR(CSR_MEPC);
+ printf("mepc:%08x\r\n", (int)epc);
+ // printf("%08x\r\n", reg_a0);
+ // printf("%08x\r\n", reg_a0);
+
+ // tval = READ_CSR(CSR_MTVAL);
+ tval = READ_CSR(0x305);
+ printf("mtval:%08x\r\n", (int)tval);
+
+ cause = (cause & 0x3ff);
+
+#ifndef CONFIG_TRAP_DUMP_DISABLE
+ const char *mcause_str[] = {
+ "Instruction address misaligned",
+ "Instruction access fault",
+ "Illegal instruction",
+ "Breakpoint",
+ "Load address misaligned",
+ "Load access fault",
+ "Store/AMO address misaligned",
+ "Store/AMO access fault",
+ "Environment call from U-mode",
+ "Environment call from S-mode",
+ "RSVD",
+ "Environment call from M-mode",
+ "Instruction page fault",
+ "Load page fault",
+ "RSVD",
+ "Store/AMO page fault"
+ };
+
+ printf("%s\r\n", mcause_str[cause & 0xf]);
+#endif
+ if ((cause == 8) || (cause == 11)) {
+ epc += 4;
+ WRITE_CSR(CSR_MEPC, epc);
+ } else {
+ while (1) {
+ }
+ }
+}
+
+void interrupt_entry(void)
+{
+ irq_callback handler;
+ void *arg;
+ volatile uint32_t mcause = 0UL;
+ uint32_t irq_num;
+
+ mcause = READ_CSR(CSR_MCAUSE);
+ printf("inerrupt: mcause=%08x\r\n", (int)mcause);
+ while (1);
+ irq_num = mcause & 0x3FF;
+
+ if (irq_num < CONFIG_IRQ_NUM) {
+ handler = g_irqvector[irq_num].handler;
+ arg = g_irqvector[irq_num].arg;
+ if (handler) {
+ handler(irq_num, arg);
+ } else {
+ }
+ } else {
+ }
+}
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/irq_ctx.h b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/irq_ctx.h
new file mode 100644
index 00000000..24fe032a
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/irq_ctx.h
@@ -0,0 +1,378 @@
+#ifndef __IRQ_CTX_H__
+#define __IRQ_CTX_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#if defined(__riscv_flen)
+# define CONFIG_ARCH_FPU
+#else
+# undef CONFIG_ARCH_FPU
+#endif
+
+/* Processor PC */
+
+#define REG_EPC_NDX 0
+
+/* General pupose registers
+ * $0: Zero register does not need to be saved
+ * $1: ra (return address)
+ */
+
+#define REG_X1_NDX 1
+
+/* $2: Stack POinter
+ * $3: Global Pointer
+ * $4: Thread Pointer
+ */
+
+#define REG_X2_NDX 2
+#define REG_X3_NDX 3
+#define REG_X4_NDX 4
+
+/* $5-$7 = t0-t3: Temporary registers */
+
+#define REG_X5_NDX 5
+#define REG_X6_NDX 6
+#define REG_X7_NDX 7
+
+/* $8: s0 / fp Frame pointer */
+
+#define REG_X8_NDX 8
+
+/* $89 s1 Saved register */
+
+#define REG_X9_NDX 9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_X10_NDX 10
+#define REG_X11_NDX 11
+#define REG_X12_NDX 12
+#define REG_X13_NDX 13
+#define REG_X14_NDX 14
+#define REG_X15_NDX 15
+#define REG_X16_NDX 16
+#define REG_X17_NDX 17
+
+/* $18-$27 = s2-s11: Saved registers */
+
+#define REG_X18_NDX 18
+#define REG_X19_NDX 19
+#define REG_X20_NDX 20
+#define REG_X21_NDX 21
+#define REG_X22_NDX 22
+#define REG_X23_NDX 23
+#define REG_X24_NDX 24
+#define REG_X25_NDX 25
+#define REG_X26_NDX 26
+#define REG_X27_NDX 27
+
+/* $28-31 = t3-t6: Temporary (Volatile) registers */
+
+#define REG_X28_NDX 28
+#define REG_X29_NDX 29
+#define REG_X30_NDX 30
+#define REG_X31_NDX 31
+
+/* Interrupt Context register */
+
+#define REG_INT_CTX_NDX 32
+
+#define INT_XCPT_REGS 33
+
+#define INT_XCPT_SIZE (4 * INT_XCPT_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+#define FPU_REG_SIZE 1 /* size in uint32_t */
+
+#define REG_F0_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 0)
+#define REG_F1_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 1)
+#define REG_F2_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 2)
+#define REG_F3_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 3)
+#define REG_F4_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 4)
+#define REG_F5_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 5)
+#define REG_F6_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 6)
+#define REG_F7_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 7)
+#define REG_F8_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 8)
+#define REG_F9_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 9)
+#define REG_F10_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 10)
+#define REG_F11_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 11)
+#define REG_F12_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 12)
+#define REG_F13_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 13)
+#define REG_F14_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 14)
+#define REG_F15_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 15)
+#define REG_F16_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 16)
+#define REG_F17_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 17)
+#define REG_F18_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 18)
+#define REG_F19_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 19)
+#define REG_F20_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 20)
+#define REG_F21_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 21)
+#define REG_F22_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 22)
+#define REG_F23_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 23)
+#define REG_F24_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 24)
+#define REG_F25_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 25)
+#define REG_F26_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 26)
+#define REG_F27_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 27)
+#define REG_F28_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 28)
+#define REG_F29_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 29)
+#define REG_F30_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 30)
+#define REG_F31_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 31)
+#define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32)
+
+#define FPU_XCPT_REGS (FPU_REG_SIZE * 33)
+#else
+#define FPU_XCPT_REGS 0
+#endif
+
+#define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS)
+
+#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
+
+/* In assembly language, values have to be referenced as byte address
+ * offsets. But in C, it is more convenient to reference registers as
+ * register save table offsets.
+ */
+
+#ifdef __ASSEMBLY__
+#define REG_EPC (4 * REG_EPC_NDX)
+#define REG_X1 (4 * REG_X1_NDX)
+#define REG_X2 (4 * REG_X2_NDX)
+#define REG_X3 (4 * REG_X3_NDX)
+#define REG_X4 (4 * REG_X4_NDX)
+#define REG_X5 (4 * REG_X5_NDX)
+#define REG_X6 (4 * REG_X6_NDX)
+#define REG_X7 (4 * REG_X7_NDX)
+#define REG_X8 (4 * REG_X8_NDX)
+#define REG_X9 (4 * REG_X9_NDX)
+#define REG_X10 (4 * REG_X10_NDX)
+#define REG_X11 (4 * REG_X11_NDX)
+#define REG_X12 (4 * REG_X12_NDX)
+#define REG_X13 (4 * REG_X13_NDX)
+#define REG_X14 (4 * REG_X14_NDX)
+#define REG_X15 (4 * REG_X15_NDX)
+#define REG_X16 (4 * REG_X16_NDX)
+#define REG_X17 (4 * REG_X17_NDX)
+#define REG_X18 (4 * REG_X18_NDX)
+#define REG_X19 (4 * REG_X19_NDX)
+#define REG_X20 (4 * REG_X20_NDX)
+#define REG_X21 (4 * REG_X21_NDX)
+#define REG_X22 (4 * REG_X22_NDX)
+#define REG_X23 (4 * REG_X23_NDX)
+#define REG_X24 (4 * REG_X24_NDX)
+#define REG_X25 (4 * REG_X25_NDX)
+#define REG_X26 (4 * REG_X26_NDX)
+#define REG_X27 (4 * REG_X27_NDX)
+#define REG_X28 (4 * REG_X28_NDX)
+#define REG_X29 (4 * REG_X29_NDX)
+#define REG_X30 (4 * REG_X30_NDX)
+#define REG_X31 (4 * REG_X31_NDX)
+#define REG_INT_CTX (4 * REG_INT_CTX_NDX)
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0 (4 * REG_F0_NDX)
+#define REG_F1 (4 * REG_F1_NDX)
+#define REG_F2 (4 * REG_F2_NDX)
+#define REG_F3 (4 * REG_F3_NDX)
+#define REG_F4 (4 * REG_F4_NDX)
+#define REG_F5 (4 * REG_F5_NDX)
+#define REG_F6 (4 * REG_F6_NDX)
+#define REG_F7 (4 * REG_F7_NDX)
+#define REG_F8 (4 * REG_F8_NDX)
+#define REG_F9 (4 * REG_F9_NDX)
+#define REG_F10 (4 * REG_F10_NDX)
+#define REG_F11 (4 * REG_F11_NDX)
+#define REG_F12 (4 * REG_F12_NDX)
+#define REG_F13 (4 * REG_F13_NDX)
+#define REG_F14 (4 * REG_F14_NDX)
+#define REG_F15 (4 * REG_F15_NDX)
+#define REG_F16 (4 * REG_F16_NDX)
+#define REG_F17 (4 * REG_F17_NDX)
+#define REG_F18 (4 * REG_F18_NDX)
+#define REG_F19 (4 * REG_F19_NDX)
+#define REG_F20 (4 * REG_F20_NDX)
+#define REG_F21 (4 * REG_F21_NDX)
+#define REG_F22 (4 * REG_F22_NDX)
+#define REG_F23 (4 * REG_F23_NDX)
+#define REG_F24 (4 * REG_F24_NDX)
+#define REG_F25 (4 * REG_F25_NDX)
+#define REG_F26 (4 * REG_F26_NDX)
+#define REG_F27 (4 * REG_F27_NDX)
+#define REG_F28 (4 * REG_F28_NDX)
+#define REG_F29 (4 * REG_F29_NDX)
+#define REG_F30 (4 * REG_F30_NDX)
+#define REG_F31 (4 * REG_F31_NDX)
+#define REG_FCSR (4 * REG_FCSR_NDX)
+#endif
+
+#else
+#define REG_EPC REG_EPC_NDX
+#define REG_X1 REG_X1_NDX
+#define REG_X2 REG_X2_NDX
+#define REG_X3 REG_X3_NDX
+#define REG_X4 REG_X4_NDX
+#define REG_X5 REG_X5_NDX
+#define REG_X6 REG_X6_NDX
+#define REG_X7 REG_X7_NDX
+#define REG_X8 REG_X8_NDX
+#define REG_X9 REG_X9_NDX
+#define REG_X10 REG_X10_NDX
+#define REG_X11 REG_X11_NDX
+#define REG_X12 REG_X12_NDX
+#define REG_X13 REG_X13_NDX
+#define REG_X14 REG_X14_NDX
+#define REG_X15 REG_X15_NDX
+#define REG_X16 REG_X16_NDX
+#define REG_X17 REG_X17_NDX
+#define REG_X18 REG_X18_NDX
+#define REG_X19 REG_X19_NDX
+#define REG_X20 REG_X20_NDX
+#define REG_X21 REG_X21_NDX
+#define REG_X22 REG_X22_NDX
+#define REG_X23 REG_X23_NDX
+#define REG_X24 REG_X24_NDX
+#define REG_X25 REG_X25_NDX
+#define REG_X26 REG_X26_NDX
+#define REG_X27 REG_X27_NDX
+#define REG_X28 REG_X28_NDX
+#define REG_X29 REG_X29_NDX
+#define REG_X30 REG_X30_NDX
+#define REG_X31 REG_X31_NDX
+#define REG_INT_CTX REG_INT_CTX_NDX
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0 REG_F0_NDX
+#define REG_F1 REG_F1_NDX
+#define REG_F2 REG_F2_NDX
+#define REG_F3 REG_F3_NDX
+#define REG_F4 REG_F4_NDX
+#define REG_F5 REG_F5_NDX
+#define REG_F6 REG_F6_NDX
+#define REG_F7 REG_F7_NDX
+#define REG_F8 REG_F8_NDX
+#define REG_F9 REG_F9_NDX
+#define REG_F10 REG_F10_NDX
+#define REG_F11 REG_F11_NDX
+#define REG_F12 REG_F12_NDX
+#define REG_F13 REG_F13_NDX
+#define REG_F14 REG_F14_NDX
+#define REG_F15 REG_F15_NDX
+#define REG_F16 REG_F16_NDX
+#define REG_F17 REG_F17_NDX
+#define REG_F18 REG_F18_NDX
+#define REG_F19 REG_F19_NDX
+#define REG_F20 REG_F20_NDX
+#define REG_F21 REG_F21_NDX
+#define REG_F22 REG_F22_NDX
+#define REG_F23 REG_F23_NDX
+#define REG_F24 REG_F24_NDX
+#define REG_F25 REG_F25_NDX
+#define REG_F26 REG_F26_NDX
+#define REG_F27 REG_F27_NDX
+#define REG_F28 REG_F28_NDX
+#define REG_F29 REG_F29_NDX
+#define REG_F30 REG_F30_NDX
+#define REG_F31 REG_F31_NDX
+#define REG_FCSR REG_FCSR_NDX
+#endif
+
+#endif
+
+/* Now define more user friendly alternative name that can be used either
+ * in assembly or C contexts.
+ */
+
+/* $1 = ra: Return address */
+
+#define REG_RA REG_X1
+
+/* $2 = sp: The value of the stack pointer on return from the exception */
+
+#define REG_SP REG_X2
+
+/* $3 = gp: Only needs to be saved under conditions where there are
+ * multiple, per-thread values for the GP.
+ */
+
+#define REG_GP REG_X3
+
+/* $4 = tp: Thread Pointer */
+
+#define REG_TP REG_X4
+
+/* $5-$7 = t0-t2: Caller saved temporary registers */
+
+#define REG_T0 REG_X5
+#define REG_T1 REG_X6
+#define REG_T2 REG_X7
+
+/* $8 = either s0 or fp: Depends if a frame pointer is used or not */
+
+#define REG_S0 REG_X8
+#define REG_FP REG_X8
+
+/* $9 = s1: Caller saved register */
+
+#define REG_S1 REG_X9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_A0 REG_X10
+#define REG_A1 REG_X11
+#define REG_A2 REG_X12
+#define REG_A3 REG_X13
+#define REG_A4 REG_X14
+#define REG_A5 REG_X15
+#define REG_A6 REG_X16
+#define REG_A7 REG_X17
+
+/* $18-$27 = s2-s11: Callee saved registers */
+
+#define REG_S2 REG_X18
+#define REG_S3 REG_X19
+#define REG_S4 REG_X20
+#define REG_S5 REG_X21
+#define REG_S6 REG_X22
+#define REG_S7 REG_X23
+#define REG_S8 REG_X24
+#define REG_S9 REG_X25
+#define REG_S10 REG_X26
+#define REG_S11 REG_X27
+
+/* $28-$31 = t3-t6: Caller saved temporary registers */
+
+#define REG_T3 REG_X28
+#define REG_T4 REG_X29
+#define REG_T5 REG_X30
+#define REG_T6 REG_X31
+
+#ifndef __ASSEMBLY__
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+# ifdef CONFIG_ARCH_FPU
+ extern void riscv_savefpu(uintptr_t *regs);
+ extern void riscv_restorefpu(uintptr_t *regs);
+# else
+ void riscv_savefpu(uintptr_t *regs) {};
+ void riscv_restorefpu(uintptr_t *regs) {};
+# endif
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __IRQ_CTX_H__ */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/riscv_fpu.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/riscv_fpu.S
new file mode 100644
index 00000000..a88e6230
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/riscv_fpu.S
@@ -0,0 +1,221 @@
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+#if defined(CONFIG_ARCH_FPU)
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Symbols
+ ************************************************************************************/
+
+ .globl riscv_fpuconfig
+ .globl riscv_savefpu
+ .globl riscv_savefpu_force
+ .globl riscv_restorefpu
+
+ .file "riscv_fpu.S"
+
+#define FS_MASK 0x6000
+#define FS_OFF 0x0000
+#define FS_INITIAL 0x2000
+#define FS_CLEAN 0x4000
+#define FS_DIRTY 0x6000
+
+#if defined(CONFIG_ARCH_DPFPU)
+# define FLOAD fld
+# define FSTORE fsd
+# define LOAD ld
+# define STORE sd
+#elif defined(CONFIG_ARCH_QPFPU)
+# define FLOAD flq
+# define FSTORE fsq
+#else
+# define FLOAD flw
+# define FSTORE fsw
+# define LOAD lw
+# define STORE sw
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: riscv_fpuconfig
+ *
+ * Description:
+ * init fpu
+ *
+ * C Function Prototype:
+ * void riscv_fpuconfig(void);
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * This function does not return anything explicitly.
+ *
+ ************************************************************************************/
+
+ .type riscv_fpuconfig, function
+
+riscv_fpuconfig:
+ li a0, FS_INITIAL
+ csrs mstatus, a0
+ csrwi fcsr, 0
+ ret
+
+/************************************************************************************
+ * Name: riscv_savefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), save the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void riscv_savefpu(uintptr_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area in which to save the floating point
+ * registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+ .type riscv_savefpu, function
+
+riscv_savefpu:
+ LOAD t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_DIRTY
+ bne t2, t1, 1f
+ li t1, ~FS_MASK
+ and t0, t0, t1
+ li t1, FS_CLEAN
+ or t0, t0, t1
+ STORE t0, REG_INT_CTX(a0)
+
+ /* Store all floating point registers */
+riscv_savefpu_force:
+
+ FSTORE f0, REG_F0(a0)
+ FSTORE f1, REG_F1(a0)
+ FSTORE f2, REG_F2(a0)
+ FSTORE f3, REG_F3(a0)
+ FSTORE f4, REG_F4(a0)
+ FSTORE f5, REG_F5(a0)
+ FSTORE f6, REG_F6(a0)
+ FSTORE f7, REG_F7(a0)
+ FSTORE f8, REG_F8(a0)
+ FSTORE f9, REG_F9(a0)
+ FSTORE f10, REG_F10(a0)
+ FSTORE f11, REG_F11(a0)
+ FSTORE f12, REG_F12(a0)
+ FSTORE f13, REG_F13(a0)
+ FSTORE f14, REG_F14(a0)
+ FSTORE f15, REG_F15(a0)
+ FSTORE f16, REG_F16(a0)
+ FSTORE f17, REG_F17(a0)
+ FSTORE f18, REG_F18(a0)
+ FSTORE f19, REG_F19(a0)
+ FSTORE f20, REG_F20(a0)
+ FSTORE f21, REG_F21(a0)
+ FSTORE f22, REG_F22(a0)
+ FSTORE f23, REG_F23(a0)
+ FSTORE f24, REG_F24(a0)
+ FSTORE f25, REG_F25(a0)
+ FSTORE f26, REG_F26(a0)
+ FSTORE f27, REG_F27(a0)
+ FSTORE f28, REG_F28(a0)
+ FSTORE f29, REG_F29(a0)
+ FSTORE f30, REG_F30(a0)
+ FSTORE f31, REG_F31(a0)
+
+ frcsr t0
+ STORE t0, REG_FCSR(a0)
+
+1:
+ ret
+
+/************************************************************************************
+ * Name: riscv_restorefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), restore the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void riscv_restorefpu(const uintptr_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area containing the floating point
+ * registers.
+ *
+ * Returned Value:
+ * This function does not return anything explicitly. However, it is called from
+ * interrupt level assembly logic that assumes that r0 is preserved.
+ *
+ ************************************************************************************/
+
+ .type riscv_restorefpu, function
+
+riscv_restorefpu:
+ LOAD t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_INITIAL
+ ble t2, t1, 1f
+
+ /* Load all floating point registers */
+
+ FLOAD f0, REG_F0(a0)
+ FLOAD f1, REG_F1(a0)
+ FLOAD f2, REG_F2(a0)
+ FLOAD f3, REG_F3(a0)
+ FLOAD f4, REG_F4(a0)
+ FLOAD f5, REG_F5(a0)
+ FLOAD f6, REG_F6(a0)
+ FLOAD f7, REG_F7(a0)
+ FLOAD f8, REG_F8(a0)
+ FLOAD f9, REG_F9(a0)
+ FLOAD f10, REG_F10(a0)
+ FLOAD f11, REG_F11(a0)
+ FLOAD f12, REG_F12(a0)
+ FLOAD f13, REG_F13(a0)
+ FLOAD f14, REG_F14(a0)
+ FLOAD f15, REG_F15(a0)
+ FLOAD f16, REG_F16(a0)
+ FLOAD f17, REG_F17(a0)
+ FLOAD f18, REG_F18(a0)
+ FLOAD f19, REG_F19(a0)
+ FLOAD f20, REG_F20(a0)
+ FLOAD f21, REG_F21(a0)
+ FLOAD f22, REG_F22(a0)
+ FLOAD f23, REG_F23(a0)
+ FLOAD f24, REG_F24(a0)
+ FLOAD f25, REG_F25(a0)
+ FLOAD f26, REG_F26(a0)
+ FLOAD f27, REG_F27(a0)
+ FLOAD f28, REG_F28(a0)
+ FLOAD f29, REG_F29(a0)
+ FLOAD f30, REG_F30(a0)
+ FLOAD f31, REG_F31(a0)
+
+ /* Store the floating point control and status register */
+
+ LOAD t0, REG_FCSR(a0)
+ fscsr t0
+
+1:
+ ret
+
+#endif /* CONFIG_ARCH_FPU */
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/start.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/start.S
new file mode 100644
index 00000000..cdf18b04
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/start.S
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2016-2020 Bouffalo Lab
+ */
+
+ .section .init
+ .align 2
+ .globl __start
+ .type __start, %function
+__start:
+.option push
+.option norelax
+ la gp, __global_pointer$
+.option pop
+ csrci mstatus, 8
+
+ /* mtvec: for all exceptions and non-vector mode IRQs */
+ la a0, default_trap_handler
+ ori a0, a0, 3
+ csrw mtvec, a0
+
+ /* mtvt: for all vector mode IRQs */
+ la a0, __Vectors
+ csrw mtvt, a0
+ li a0, -1
+ csrc medeleg, a0
+ csrc mideleg, a0
+
+#if defined(__riscv_flen)
+ /* FP: initial state */
+ csrr t0, mstatus
+ li t1, ~0x6000
+ and t0, t0, t1
+ li t1, 0x2000
+ or t0, t0, t1
+ csrw mstatus, t0
+ /* csrwi fcsr, 0 */
+#endif
+
+ .weak __StackTop
+ la sp, __StackTop
+ csrw mscratch, sp
+
+ /* Load data section removed */
+
+ /* Clear bss section removed */
+
+ jal SystemInit
+
+ /* start load code to itcm like. */
+ jal start_load
+
+ jal System_Post_Init
+
+ jal main
+
+ .size __start, . - __start
+
+__exit:
+ j __exit
+
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/start_load.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/start_load.c
new file mode 100644
index 00000000..f9715fcc
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/start_load.c
@@ -0,0 +1,92 @@
+#include
+
+#define __STARTUP_CLEAR_BSS 1
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __itcm_load_addr;
+extern uint32_t __dtcm_load_addr;
+extern uint32_t __system_ram_load_addr;
+extern uint32_t __ram_load_addr;
+extern uint32_t __nocache_ram_load_addr;
+
+extern uint32_t __text_code_start__;
+extern uint32_t __text_code_end__;
+extern uint32_t __tcm_code_start__;
+extern uint32_t __tcm_code_end__;
+extern uint32_t __tcm_data_start__;
+extern uint32_t __tcm_data_end__;
+extern uint32_t __ram_data_start__;
+extern uint32_t __ram_data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __noinit_data_start__;
+extern uint32_t __noinit_data_end__;
+extern uint32_t __nocache_ram_data_start__;
+extern uint32_t __nocache_ram_data_end__;
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+//extern uint32_t __copy_table_start__;
+//extern uint32_t __copy_table_end__;
+//extern uint32_t __zero_table_start__;
+//extern uint32_t __zero_table_end__;
+
+void start_load(void)
+{
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+ /* Copy ITCM code */
+ pSrc = &__itcm_load_addr;
+ pDest = &__tcm_code_start__;
+
+ for (; pDest < &__tcm_code_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* Copy DTCM code */
+ pSrc = &__dtcm_load_addr;
+ pDest = &__tcm_data_start__;
+
+ for (; pDest < &__tcm_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* BF Add OCARAM data copy */
+ pSrc = &__ram_load_addr;
+ pDest = &__ram_data_start__;
+
+ for (; pDest < &__ram_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+ /* BF Add no cache ram data copy */
+ pSrc = &__nocache_ram_load_addr;
+ pDest = &__nocache_ram_data_start__;
+
+ for (; pDest < &__nocache_ram_data_end__;) {
+ *pDest++ = *pSrc++;
+ }
+
+#ifdef __STARTUP_CLEAR_BSS
+ /* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for (; pDest < &__bss_end__;) {
+ *pDest++ = 0ul;
+ }
+
+#endif
+}
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/system_bl808.c b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/system_bl808.c
new file mode 100644
index 00000000..9d0cf71d
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/system_bl808.c
@@ -0,0 +1,124 @@
+#include "bl808_clock.h"
+#include "bl808_pds.h"
+#include "tzc_sec_reg.h"
+#include "rv_hart.h"
+#include "rv_pmp.h"
+
+static void Tzc_Sec_PSRAMA_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t endAddr, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
+
+ tmpVal = ((((endAddr >> 10) & 0xffff) - 1) & 0xffff) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMA_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable but not lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
+}
+
+static void Tzc_Sec_PSRAMB_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t endAddr, uint8_t group)
+{
+ uint32_t tmpVal = 0;
+
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+ tmpVal &= (~(3 << (region * 2)));
+ tmpVal |= (group << (region * 2));
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+
+ tmpVal = ((((endAddr >> 10) & 0xffff) - 1) & 0xffff) | (((startAddr >> 10) & 0xffff) << 16);
+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+ /* set enable but not lock */
+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+ tmpVal |= 1 << (region + 16);
+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+}
+
+// static void pmp_init(void)
+// {
+// const pmp_config_entry_t pmp_entry_tab[1] = {
+// /* no access */
+// [0] = {
+// .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
+// .entry_pa_base = 0x80000000,
+// .entry_pa_length = PMP_REG_SZ_256M,
+// }
+// };
+// rvpmp_init(pmp_entry_tab, sizeof(pmp_entry_tab) / sizeof(pmp_config_entry_t));
+// }
+
+void SystemInit(void)
+{
+ uint32_t i = 0;
+
+ /* CPU Prefetching barrier */
+ Tzc_Sec_PSRAMA_Access_Set_Not_Lock(0, 0x0, 64 * 1024 * 1024, 0);
+ Tzc_Sec_PSRAMB_Access_Set_Not_Lock(0, 0x0, 64 * 1024 * 1024, 0);
+ // pmp_init();
+
+ /* enable mstatus FS */
+ uint32_t mstatus = __get_MSTATUS();
+ mstatus |= (1 << 13);
+ __set_MSTATUS(mstatus);
+
+ /* enable mxstatus THEADISAEE */
+ uint32_t mxstatus = __get_MXSTATUS();
+ mxstatus |= (1 << 22);
+ /* enable mxstatus MM */
+ mxstatus |= (1 << 15);
+ __set_MXSTATUS(mxstatus);
+
+ /* get interrupt level from info */
+ CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
+
+ /* Every interrupt should be clear by software*/
+ for (i = 0; i < IRQn_LAST; i++) {
+ CLIC->CLICINT[i].IE = 0;
+ CLIC->CLICINT[i].IP = 0;
+ CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+ }
+
+ /* tspend interrupt will be clear auto*/
+ /* tspend use positive interrupt */
+ CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
+
+ csi_dcache_enable();
+ csi_icache_enable();
+
+ /* enable preload $ AMR for D$ */
+ __set_MHINT(0x000c);
+
+ /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/
+ uint32_t mexstatus = __get_MEXSTATUS();
+ mexstatus &= ~(0x3 << 16);
+ __set_MEXSTATUS(mexstatus);
+
+ GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, 0);
+ GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 0);
+ GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35, 0);
+ GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 0);
+
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG1, 0xffffffff);
+ BL_WR_REG(GLB_BASE, GLB_UART_CFG2, 0x0000ffff);
+
+ GLB_Set_EM_Sel(GLB_WRAM160KB_EM0KB);
+}
+
+void System_Post_Init(void)
+{
+ csi_dcache_clean();
+ csi_icache_invalid();
+
+ PDS_Power_On_MM_System();
+ /* make D0 all ram avalable for mcu usage */
+ GLB_Set_DSP_L2SRAM_Available_Size(3, 1, 1, 1);
+
+ /* global IRQ enable */
+ __enable_irq();
+}
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/vector.S b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/vector.S
new file mode 100644
index 00000000..8b605245
--- /dev/null
+++ b/arch/riscv32/bl808/src/drivers/soc/bl808/std/startup/m0/vector.S
@@ -0,0 +1,320 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+ /******************************************************************************
+ * @file vectors.S
+ * @brief define default vector handlers. Should use with
+ * GCC for CSKY Embedded Processors
+ * @version V1.0
+ * @date 28. Nove 2017
+ ******************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+/* Enable interrupts when returning from the handler */
+#define MSTATUS_PRV1 0x1880
+
+.section .bss.g_trap_stack
+
+ .align 4
+ .global g_trap_sp_base
+ .global g_trap_sp
+g_trap_sp_base:
+#if defined(__riscv_flen)
+ .space 1024
+#else
+ .space 512
+#endif
+g_trap_sp:
+#if 0
+.section .bss.g_irq_stack
+ .align 4
+ .global g_irq_sp_base
+ .global g_irq_sp
+g_irq_sp_base:
+ .space 1024
+g_irq_sp:
+#endif
+/******************************************************************************
+ * Functions:
+ * void default_interrupt_handler(void);
+ * default handler for all the vector mode IRQs
+ ******************************************************************************/
+
+ .section .text.vectors.default_interrupt_handler, "ax", %progbits
+ .align 6
+ .global default_interrupt_handler
+ .weak default_interrupt_handler
+ /* FreeRTOS will define tspend_handler for context switch */
+ .type default_interrupt_handler, %function
+default_interrupt_handler:
+ /* ipush */
+ addi sp, sp, -76
+
+ /* save x5 x6 then save mepc mcause */
+ sw x5, 4(sp)
+ sw x6, 8(sp)
+ csrr t0, mepc
+ csrr t1, mcause
+ sw t1, 64(sp)
+ sw t0, 68(sp)
+ csrr t0, mscratch
+ sw t0, 72(sp)
+ /* save regs */
+ sw x1, 0(sp)
+ sw x7, 12(sp)
+ sw x10, 16(sp)
+ sw x11, 20(sp)
+ sw x12, 24(sp)
+ sw x13, 28(sp)
+ sw x14, 32(sp)
+ sw x15, 36(sp)
+ sw x16, 40(sp)
+ sw x17, 44(sp)
+ sw x28, 48(sp)
+ sw x29, 52(sp)
+ sw x30, 56(sp)
+ sw x31, 60(sp)
+
+ /*
+ * IRQ stack contents after ipush:
+ * ~mem addr high:
+ * + 0: <--- init IRQ sp (mscratch)
+ * - 4: mepc
+ * - 8: mcause
+ * - 12: x1 (ra)
+ * - 16: x5 (t0)
+ * - 20: x6 (t1)
+ * - 24: x7 (t2)
+ * - 28: x10 (a0)
+ * - 32: x11 (a1)
+ * - 36: x12 (a2)
+ * - 40: x13 (a3)
+ * - 44: x14 (a4)
+ * - 48: x15 (a5)
+ * - 52: x16 (a6)
+ * - 56: x17 (a7)
+ * - 60: x28 (t3)
+ * - 64: x29 (t4)
+ * - 68: x30 (t5)
+ * - 72: x31 (t6) <--- current IRQ sp
+ * ~mem addr low:
+ */
+ /* WARNING: global IRQ enabled by ipush */
+ csrs mstatus, 8
+
+ /* keep stack 16bytes aligned */
+ addi sp, sp, -88
+
+ /* - 76: mstatus */
+ csrr t1, mstatus
+ sw t1, 84(sp)
+ srli t2, t1, 13
+ andi t2, t2, 0x3
+ li t0, 0x3
+ bne t2, t0, .F_RegNotSave1
+
+ fsw ft0, 0(sp)
+ fsw ft1, 4(sp)
+ fsw ft2, 8(sp)
+ fsw ft3, 12(sp)
+ fsw ft4, 16(sp)
+ fsw ft5, 20(sp)
+ fsw ft6, 24(sp)
+ fsw ft7, 28(sp)
+ fsw fa0, 32(sp)
+ fsw fa1, 36(sp)
+ fsw fa2, 40(sp)
+ fsw fa3, 44(sp)
+ fsw fa4, 48(sp)
+ fsw fa5, 52(sp)
+ fsw fa6, 56(sp)
+ fsw fa7, 60(sp)
+ fsw ft8, 64(sp)
+ fsw ft9, 68(sp)
+ fsw ft10,72(sp)
+ fsw ft11,76(sp)
+.F_RegNotSave1:
+
+ csrr a0, mcause
+ andi t1, a0, 0x3FF
+ /* get ISR */
+ la t2, interrupt_entry
+ jalr t2
+
+ lw t1, 84(sp)
+ srli t2, t1, 13
+ andi t2, t2, 0x3
+ li t0, 0x3
+ bne t2, t0, .F_RegNotLoad
+
+ flw ft0, 0(sp)
+ flw ft1, 4(sp)
+ flw ft2, 8(sp)
+ flw ft3, 12(sp)
+ flw ft4, 16(sp)
+ flw ft5, 20(sp)
+ flw ft6, 24(sp)
+ flw ft7, 28(sp)
+ flw fa0, 32(sp)
+ flw fa1, 36(sp)
+ flw fa2, 40(sp)
+ flw fa3, 44(sp)
+ flw fa4, 48(sp)
+ flw fa5, 52(sp)
+ flw fa6, 56(sp)
+ flw fa7, 60(sp)
+ flw ft8, 64(sp)
+ flw ft9, 68(sp)
+ flw ft10,72(sp)
+ flw ft11,76(sp)
+
+.F_RegNotLoad:
+ addi sp, sp, 88
+ /* mret included, and IRQ tail-chain may happen */
+ /* ipop */
+
+ csrc mstatus, 8
+ /* restore mepc mcause mscrath */
+ lw t0, 68(sp)
+ csrw mepc, t0
+ lw t0, 64(sp)
+ csrw mcause, t0
+ lw t0, 72(sp)
+ csrw mscratch, t0
+ /* restore regs */
+ lw x1, 0(sp)
+ lw x5, 4(sp)
+ lw x6, 8(sp)
+ lw x7, 12(sp)
+ lw x10, 16(sp)
+ lw x11, 20(sp)
+ lw x12, 24(sp)
+ lw x13, 28(sp)
+ lw x14, 32(sp)
+ lw x15, 36(sp)
+ lw x16, 40(sp)
+ lw x17, 44(sp)
+ lw x28, 48(sp)
+ lw x29, 52(sp)
+ lw x30, 56(sp)
+ lw x31, 60(sp)
+
+ addi sp, sp, 76
+ mret
+
+ .size default_interrupt_handler, . - default_interrupt_handler
+
+/******************************************************************************
+ * Functions:
+ * void trap(void);
+ * default handler for exceptions and non-vector mode IRQs
+ ******************************************************************************/
+ .section .text.vectors.default_trap_handler, "ax", %progbits
+ .align 6
+ .global trap
+ .type trap, %function
+ .weak default_trap_handler
+ .global default_trap_handler
+ .type default_trap_handler, %function
+default_trap_handler:
+trap:
+ /* Check for interrupt */
+ sw t0, -4(sp)
+ csrr t0, mcause
+
+ /* IRQ, but in non-vector mode */
+ blt t0, x0, .Lirq
+
+ la t0, g_trap_sp
+ addi t0, t0, -XCPTCONTEXT_SIZE
+ sw x1, REG_X1(t0)
+ sw x2, REG_X2(t0)
+ sw x3, REG_X3(t0)
+ sw x4, REG_X4(t0)
+ sw x6, REG_X6(t0)
+ sw x7, REG_X7(t0)
+ sw x8, REG_X8(t0)
+ sw x9, REG_X9(t0)
+ sw x10, REG_X10(t0)
+ sw x11, REG_X11(t0)
+ sw x12, REG_X12(t0)
+ sw x13, REG_X13(t0)
+ sw x14, REG_X14(t0)
+ sw x15, REG_X15(t0)
+ sw x16, REG_X16(t0)
+ sw x17, REG_X17(t0)
+ sw x18, REG_X18(t0)
+ sw x19, REG_X19(t0)
+ sw x20, REG_X20(t0)
+ sw x21, REG_X21(t0)
+ sw x22, REG_X22(t0)
+ sw x23, REG_X23(t0)
+ sw x24, REG_X24(t0)
+ sw x25, REG_X25(t0)
+ sw x26, REG_X26(t0)
+ sw x27, REG_X27(t0)
+ sw x28, REG_X28(t0)
+ sw x29, REG_X29(t0)
+ sw x30, REG_X30(t0)
+ sw x31, REG_X31(t0)
+ csrr a0, mepc
+ sw a0, REG_EPC(t0)
+ csrr a0, mstatus
+ sw a0, REG_INT_CTX(t0)
+
+ mv a0, t0
+ lw t0, -4(sp)
+ mv sp, a0
+ sw t0, REG_X5(sp)
+
+ jal exception_entry
+
+ lw t0, REG_INT_CTX(sp)
+ csrw mstatus, t0
+ lw t0, REG_EPC(sp)
+ csrw mepc, t0
+
+ lw x31, REG_X31(sp)
+ lw x30, REG_X30(sp)
+ lw x29, REG_X29(sp)
+ lw x28, REG_X28(sp)
+ lw x27, REG_X27(sp)
+ lw x26, REG_X26(sp)
+ lw x25, REG_X25(sp)
+ lw x24, REG_X24(sp)
+ lw x23, REG_X23(sp)
+ lw x22, REG_X22(sp)
+ lw x21, REG_X21(sp)
+ lw x20, REG_X20(sp)
+ lw x19, REG_X19(sp)
+ lw x18, REG_X18(sp)
+ lw x17, REG_X17(sp)
+ lw x16, REG_X16(sp)
+ lw x15, REG_X15(sp)
+ lw x14, REG_X14(sp)
+ lw x13, REG_X13(sp)
+ lw x12, REG_X12(sp)
+ lw x11, REG_X11(sp)
+ lw x10, REG_X10(sp)
+ lw x9, REG_X9(sp)
+ lw x8, REG_X8(sp)
+ lw x7, REG_X7(sp)
+ lw x6, REG_X6(sp)
+ lw x5, REG_X5(sp)
+ lw x4, REG_X4(sp)
+ lw x3, REG_X3(sp)
+ lw x1, REG_X1(sp)
+ lw x2, REG_X2(sp)
+
+ mret
+
+.Lirq:
+ lw t0, -4(sp)
+/* MSOFT IRQ for FreeRTOS context switch
+ * Config MSOFT IRQ to non-vector mode
+ * tspend_handler is a weak alias to default_interrupt_handler
+ */
+ j default_interrupt_handler
+
+ .size default_trap_handler, . - default_trap_handler
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/pine64_ox64/Kconfig b/arch/riscv32/bl808/src/pine64_ox64/Kconfig
new file mode 100644
index 00000000..dcb681bb
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/Kconfig
@@ -0,0 +1,9 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the docs folder of mTower repository.
+#
+
+if PLATFORM_NUMAKER_PFM_M2351
+comment "NuMaker-PFM-M2351 Peripheral Configuration Options"
+
+endif # PLATFORM_NUMAKER_PFM_M2351
diff --git a/arch/riscv32/bl808/src/pine64_ox64/Makefile b/arch/riscv32/bl808/src/pine64_ox64/Makefile
new file mode 100644
index 00000000..df8d7035
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/Makefile
@@ -0,0 +1,125 @@
+############################################################################
+# arch/riscv32/bl808/src/pine64_ox64/Makefile
+#
+# Copyright (c) 2024 Samsung Electronics Co., Ltd. All Rights Reserved.
+# Author: Taras Drozdovskyi t.drozdovsky@samsung.com
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+-include $(TOPDIR)/.config
+-include Make.defs
+
+MTOWER_NS = $(TOPDIR)/mtower_ns.bin
+
+ifeq ($(CONFIG_BOOTLOADER2),y)
+BL2 := $(TOPDIR)/build/secure$(subst $(TOPDIR),,$(shell pwd))/../NuBL2/bl2.bin
+ECDSA_KEYS := ../NuBL2/KeyInfo/ecdsa_keys.bin
+else
+BL2 := null
+ECDSA_KEYS := null
+endif
+
+# ifeq ($(CONFIG_BOOTLOADER32),y)
+# BL32 := $(TOPDIR)/build/secure$(subst $(TOPDIR),,$(shell pwd))/secure/bl32.bin
+# else
+# BL32 := null
+# endif
+ifeq ($(CONFIG_BOOTLOADER33),y)
+BL33 := $(TOPDIR)/build/nonsecure$(subst $(TOPDIR),,$(shell pwd))/nonsecure/bl33.bin
+else
+BL33 := null
+endif
+
+mtower$(EXEEXT):
+ifeq ($(CONFIG_BOOTLOADER2),y)
+ $(Q) $(MAKE) -C ../NuBL2 TOPDIR="$(TOPDIR)" NuBL2$(EXEEXT)
+endif
+# ifeq ($(CONFIG_BOOTLOADER32),y)
+# $(Q) $(MAKE) -C secure TOPDIR="$(TOPDIR)" mtower_s$(EXEEXT)
+# endif
+ifeq ($(CONFIG_BOOTLOADER33),y)
+ $(Q) $(MAKE) -C nonsecure TOPDIR="$(TOPDIR)" mtower_ns$(EXEEXT)
+endif
+# $(TOPDIR)/tools/fwinfogen $(BL2) $(BL32) $(MTOWER_S) $(ECDSA_KEYS) $(BL33) $(MTOWER_NS)
+# $(Q) cp -f $(TOPDIR)/mtower_ns.bin /media/sf_Shared/
+# $(Q) cp -f $(TOPDIR)/mtower_s.bin /media/sf_Shared/
+
+# $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+# $(Q) printf "$(GREEN)| Secure image |$(NORMAL)\n"
+# $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+# $(Q) printf "$(GREEN)| Name | Start addr | End addr | Size | File name |$(NORMAL)\n"
+# $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+# ifeq ($(CONFIG_BOOTLOADER2),y)
+# $(eval bl2_sz = `stat -c%s $(TOPDIR)/build/secure$(subst $(TOPDIR),,$(shell pwd))/../NuBL2/bl2.bin`)
+# $(eval bl2_start = 0x00000000)
+
+# $(Q) printf "$(GREEN)| Boot loader 2 | 0x%08x | 0x%08x | %u\t| bl2.bin |$(NORMAL)\n" $(bl2_start) $$(( $(bl2_start) + $(bl2_sz) )) $(bl2_sz)
+# endif
+
+# ifeq ($(CONFIG_BOOTLOADER32),y)
+# $(eval bl32_sz = `stat -c%s $(TOPDIR)/build/secure$(subst $(TOPDIR),,$(shell pwd))/secure/bl32.bin`)
+# $(eval bl32_start = $(CONFIG_START_ADDRESS_BL32))
+
+# $(Q) printf "$(GREEN)| Secure handler | 0x%08x | 0x%08x | %u\t| bl32.bin |$(NORMAL)\n" $(bl32_start) $$(( $(bl32_start) + $(bl32_sz) )) $(bl32_sz)
+# ifeq ($(CONFIG_BOOTLOADER2),y)
+# $(Q) printf "$(GREEN)| FW info of BL32 | 0x%08x | 0x%08x | %u\t| *auto gen* |$(NORMAL)\n" 0x00038000 0x000380c0 192
+# endif
+
+# endif
+# $(eval mtower_s_sz = `stat -c%s $(TOPDIR)/mtower_s.bin`)
+# $(eval mtower_s_start = 0x00000000)
+# $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+# $(Q) printf "$(GREEN)| mtower_s | 0x%08x | 0x%08x | %u\t| mtower_s.bin |$(NORMAL)\n" $(mtower_s_start) $$(( $(mtower_s_start) + $(mtower_s_sz) )) $(mtower_s_sz)
+# $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+
+ifeq ($(CONFIG_BOOTLOADER33),y)
+ $(eval bl33_sz = `stat -c%s $(TOPDIR)/build/nonsecure$(subst $(TOPDIR),,$(shell pwd))/nonsecure/bl33.bin`)
+ $(eval bl33_start = $(CONFIG_START_ADDRESS_BL33))
+
+ $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+ $(Q) printf "$(GREEN)| Non-Secure image |$(NORMAL)\n"
+ $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+ $(Q) printf "$(GREEN)| Name | Start addr | End addr | Size | File name |$(NORMAL)\n"
+ $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+ $(Q) printf "$(GREEN)| FreeRTOS | 0x%08x | 0x%08x | %u\t| bl33.bin |$(NORMAL)\n" $(bl33_start) $$(( $(bl33_start) + $(bl33_sz) )) $(bl33_sz)
+# ifeq ($(CONFIG_BOOTLOADER2),y)
+# $(Q) printf "$(GREEN)| FW info of BL33 | 0x%08x | 0x%08x | %u\t| *auto gen* |$(NORMAL)\n" 0x00078000 0x000780c0 192
+# endif
+# $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+# $(eval mtower_ns_sz = `stat -c%s $(TOPDIR)/mtower_ns.bin`)
+# $(eval mtower_ns_start = $(CONFIG_START_ADDRESS_BL33))
+# $(Q) printf "$(GREEN)| mtower_ns | 0x%08x | 0x%08x | %u\t| mtower_ns.bin |$(NORMAL)\n" $(mtower_ns_start) $$(( $(mtower_ns_start) + $(mtower_ns_sz) )) $(mtower_ns_sz)
+ $(Q) printf "$(GREEN)+-----------------------------------------------------------------------+$(NORMAL)\n"
+
+endif
+
+clean:
+# $(Q) $(MAKE) -C secure TOPDIR="$(TOPDIR)" clean
+ $(Q) $(MAKE) -C nonsecure TOPDIR="$(TOPDIR)" clean
+ $(Q) rm -rf $(TOPDIR)/build
+# $(Q) rm -f $(TOPDIR)/mtower_s.bin
+ $(Q) rm -f $(TOPDIR)/mtower_ns.bin
+
+distclean: clean
+
+flash:
+ $(Q) sudo $(TOPDIR)/../bl_mcu_sdk/tools/bflb_tools/bouffalo_flash_cube/BLFlashCommand-ubuntu \
+ --interface=uart \
+ --baudrate=115200 \
+ --port=/dev/ttyUSB0 \
+ --chipname=bl808 \
+ --cpu_id=m0 \
+ --config=./nonsecure/flash_prog_cfg.ini
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/FreeRTOSConfig.h b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/FreeRTOSConfig.h
new file mode 100644
index 00000000..16683a89
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/FreeRTOSConfig.h
@@ -0,0 +1,145 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL)
+#define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL)
+#else
+#if __riscv_xlen == 64
+#define configMTIME_BASE_ADDRESS (0)
+#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL)
+#else
+#define configCLINT_BASE_ADDRESS (0xE0000000UL)
+#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL)
+#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL)
+#endif
+#endif
+
+/*
+ * configMINIMAL_STACK_SIZE must be a value greater than the stack use by
+ * the minimal task + the sizeof the register saved.
+ * The size of the register is differrent from a core to another, e.g. on RiscV
+ * it could be 32 base register + 32 register for FPU and some other for the
+ * specific extensions.
+ */
+#ifdef __riscv_fdiv
+#define configMINIMAL_STACK_SIZE ( ( size_t ) 288 )
+#else
+// #define configMINIMAL_STACK_SIZE ( ( size_t ) 236 )
+#define configMINIMAL_STACK_SIZE ( ( size_t ) 288 )
+#endif /* __riscv_fdiv */
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ((uint32_t)(1 * 1000 * 1000))
+#define configTICK_RATE_HZ ((TickType_t)2)
+#define configMAX_PRIORITIES (7)
+// #define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */
+#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024)
+#define configMAX_TASK_NAME_LEN (16)
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 0
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configUSE_APPLICATION_TASK_TAG 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configUSE_POSIX_ERRNO 1
+#define portUSING_MPU_WRAPPERS 1
+#define portasmHAS_CLINT 1
+#define configISR_STACK_SIZE_WORDS 4096
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES (2)
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 4
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE)
+/* Task priorities. Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+#define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3)
+#endif
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 1
+#define INCLUDE_xTaskGetHandle 1
+#define INCLUDE_xSemaphoreGetMutexHolder 1
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+// void vApplicationMallocFailedHook(void);
+// void vAssertCalled(void);
+
+// #include
+
+// #define configASSERT(x) \
+// if ((x) == 0) { \
+// printf("file [%s]\r\n", __FILE__); \
+// printf("func [%s]\r\n", __FUNCTION__); \
+// printf("line [%d]\r\n", __LINE__); \
+// printf("%s\r\n", (const char *)(#x)); \
+// vAssertCalled(); \
+// }
+
+// #if (configUSE_TICKLESS_IDLE != 0)
+// void vApplicationSleep(uint32_t xExpectedIdleTime);
+// #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime)
+// #endif
+// #define portUSING_MPU_WRAPPERS
+#endif /* FREERTOS_CONFIG_H */
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/Make.defs b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/Make.defs
new file mode 100644
index 00000000..f3a6b79b
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/Make.defs
@@ -0,0 +1,146 @@
+############################################################################
+# arch/cortex-m23/m2351/src/numaker_pfm_m2351/nonsecure/Make.defs
+#
+# Copyright (c) 2018-2019 Samsung Electronics Co., Ltd. All Rights Reserved.
+# Author: Taras Drozdovskyi t.drozdovsky@samsung.com
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+############################################################################
+
+HEAD_ASRC =
+
+# Common BL808 files
+
+CMN_ASRCS =
+
+CMN_CSRCS =
+
+# Required CHIP files
+
+#CHIP_ASRCS_NS = ../../drivers/soc/bl808/std/startup/m0/riscv_fpu.S \
+# ../../drivers/soc/bl808/std/startup/m0/start.S \
+# ../../drivers/soc/bl808/std/startup/m0/vector.S
+
+# ../../../../../../FreeRTOS-metal/FreeRTOS-Kernel/portable/GCC/RISC-V/portASM.S \
+# ../../freedom-metal/src/vector.S \
+# ../../freedom-metal/src/trap.S \
+# ../../freedom-metal/gloss/crt0.S \
+# ../../freedom-metal/src/entry.S \
+# ../../freedom-metal/src/scrub.S
+
+CHIP_CSRCS_NS = main.c \
+ board.c \
+ fw_header.c \
+ printf.c
+
+#CHIP_CSRCS_NS = example-freertos-rtower.c \
+# Bridge_Freedom-metal_FreeRTOS.c \
+# printf.c
+
+# CHIP_CSRCS_NS += ../../freedom-metal/gloss/sys_write.c
+
+
+#CHIP_CSRCS_NS += ../../drivers/soc/bl808/std/src/bl808_aon.c \
+# ../../drivers/soc/bl808/std/src/bl808_clock.c \
+# ../../drivers/soc/bl808/std/port/bl808_clock.c \
+# ../../drivers/soc/bl808/std/src/bl808_common.c \
+# ../../drivers/soc/bl808/std/src/bl808_ef_cfg.c \
+# ../../drivers/soc/bl808/std/src/bl808_glb.c \
+# ../../drivers/soc/bl808/std/src/bl808_glb_gpio.c \
+# ../../drivers/soc/bl808/std/src/bl808_hbn.c \
+# ../../drivers/soc/bl808/std/src/bl808_l1c.c \
+# ../../drivers/soc/bl808/std/src/bl808_pds.c \
+# ../../drivers/soc/bl808/std/src/bl808_psram_uhs.c \
+# ../../drivers/soc/bl808/std/src/bl808_sdh.c \
+# ../../drivers/soc/bl808/std/src/bl808_tzc_sec.c \
+# ../../drivers/soc/bl808/std/src/bl808_uhs_phy.c \
+# ../../drivers/soc/bl808/std/startup/m0/interrupt.c \
+# ../../drivers/soc/bl808/std/startup/m0/start_load.c \
+# ../../drivers/soc/bl808/std/startup/m0/system_bl808.c
+# ../../drivers/lhal/config/bl808/device_table.c \
+# ../../drivers/lhal/src/bflb_adc.c \
+# ../../drivers/lhal/src/bflb_cks.c \
+# ../../drivers/lhal/src/bflb_dac.c \
+# ../../drivers/lhal/src/bflb_emac.c \
+# ../../drivers/lhal/src/bflb_i2s.c \
+# ../../drivers/lhal/src/bflb_kys.c \
+# ../../drivers/lhal/src/bflb_pwm_v1.c \
+# ../../drivers/lhal/src/bflb_sec_aes.c \
+# ../../drivers/lhal/src/bflb_auadc.c \
+# ../../drivers/lhal/src/bflb_clock.c \
+# ../../drivers/lhal/src/bflb_dbi.c \
+# ../../drivers/lhal/src/bflb_flash.c \
+# ../../drivers/lhal/src/bflb_ir.c \
+# ../../drivers/lhal/src/bflb_l1c.c \
+# ../../drivers/lhal/src/bflb_pwm_v2.c \
+# ../../drivers/lhal/src/bflb_sec_irq.c \
+# ../../drivers/lhal/src/bflb_audac.c \
+# ../../drivers/lhal/src/bflb_common.c \
+# ../../drivers/lhal/src/bflb_dma.c \
+# ../../drivers/lhal/src/bflb_gpio.c \
+# ../../drivers/lhal/src/bflb_irq.c \
+# ../../drivers/lhal/src/bflb_mjpeg.c \
+# ../../drivers/lhal/src/bflb_rtc.c \
+# ../../drivers/lhal/src/bflb_sec_sha.c \
+# ../../drivers/lhal/src/bflb_timer.c \
+# ../../drivers/lhal/src/bflb_wdg.c \
+# ../../drivers/lhal/src/bflb_cam.c \
+# ../../drivers/lhal/src/bflb_csi.c \
+# ../../drivers/lhal/src/bflb_ef_ctrl.c \
+# ../../drivers/lhal/src/bflb_i2c.c \
+# ../../drivers/lhal/src/bflb_iso11898.c \
+# ../../drivers/lhal/src/bflb_mtimer.c \
+# ../../drivers/lhal/src/bflb_sdio2.c \
+# ../../drivers/lhal/src/bflb_sec_trng.c \
+# ../../drivers/lhal/src/bflb_uart.c \
+# ../../drivers/lhal/src/flash/bflb_sf_ctrl.c \
+# ../../drivers/lhal/src/flash/bflb_sflash.c \
+# ../../drivers/lhal/src/flash/bflb_sf_cfg.c \
+# ../../drivers/lhal/src/flash/bflb_xip_sflash.c
+
+# ../../components/mm/mem.c \
+# ../../components/mm/mmheap/bflb_mmheap.c \
+# ../../components/mm/mmheap/mmheap.c \
+# ../../components/utils/log/log.c
+
+# ../../components/libc/printf.c \
+
+# ../../components/mm/tlsf/bflb_tlsf.c \
+
+# ../../drivers/lhal/src/bflb_usb_v1.c \
+# ../../drivers/lhal/src/bflb_usb_v2.c \
+# ../../drivers/lhal/src/bflb_spi.c \
+# ../../drivers/lhal/src/bflb_spi_psram.c \
+
+
+# ../../../../../../tee_client/libteec/src/tee_client_api.c
+# ../../Device/Nuvoton/M2351/Source/system_M2351.c \
+# ../../Device/Nuvoton/M2351/Source/GCC/_syscalls.c \
+
+ifeq ($(CONFIG_APPS_HELLO_WORLD),y)
+CHIP_CSRCS_NS += ../../../../../../apps/hello_world/ca/hello_world_ns.c
+endif
+
+ifeq ($(CONFIG_APPS_AES),y)
+CHIP_CSRCS_NS += ../../../../../../apps/aes/ca/aes_ns.c
+endif
+
+ifeq ($(CONFIG_APPS_HOTP),y)
+CHIP_CSRCS_NS += ../../../../../../apps/hotp/ca/hotp_ns.c
+endif
+
+ifeq ($(CONFIG_APPS_TEST),y)
+CHIP_CSRCS_NS += ../../../../../../apps/test/ca/test_ns.c
+endif
+
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/Makefile b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/Makefile
new file mode 100644
index 00000000..5755618d
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/Makefile
@@ -0,0 +1,93 @@
+############################################################################
+# arch/riscv32/bl808/src/pine64_ox64/nonsecure/Makefile
+#
+# Copyright (c) 2024 Samsung Electronics Co., Ltd. All Rights Reserved.
+# Author: Taras Drozdovskyi t.drozdovsky@samsung.com
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+-include $(TOPDIR)/.config
+-include Make.defs
+
+ifeq ($(CONFIG_APPS_HELLO_WORLD),y)
+CFLAGS += -I$(TOPDIR)/apps/hello_world
+endif
+
+ifeq ($(CONFIG_APPS_AES),y)
+CFLAGS += -I$(TOPDIR)/apps/aes
+endif
+
+ifeq ($(CONFIG_APPS_HOTP),y)
+CFLAGS += -I$(TOPDIR)/apps/hotp
+endif
+
+ifeq ($(CONFIG_APPS_TEST),y)
+CFLAGS += -I$(TOPDIR)/apps/test
+endif
+
+CFLAGS += -DDEBUG_PORT=$(subst ",,$(CONFIG_NONSECURE_DEBUG_UART))
+
+OBJDIR = $(TOPDIR)/build/nonsecure$(subst $(TOPDIR),,$(shell pwd))
+
+MTOWER_NS = $(TOPDIR)/mtower_ns$(EXEEXT)
+
+ASRCS_NS = $(CHIP_ASRCS_NS) $(CMN_ASRCS)
+AOBJS_NS = $(addprefix $(OBJDIR)/, $(ASRCS_NS:.S=$(OBJEXT)))
+
+CSRCS_NS = $(CHIP_CSRCS_NS) $(CMN_CSRCS)
+COBJS_NS = $(addprefix $(OBJDIR)/, $(CSRCS_NS:.c=$(OBJEXT)))
+
+OBJS_NS = $(AOBJS_NS) $(COBJS_NS)
+
+LIBPATHS = -L. -L"$(TOPDIR)/lib"
+
+LIBS = -llibc -lmm -llhal -lstd -lfreertos -Wl,--no-whole-archive -lc -lm
+
+$(AOBJS_NS): $(OBJDIR)/%$(OBJEXT): %.S
+ $(Q) mkdir -p $(OBJDIR)/$(dir $<)
+ @echo "AS: $<"
+# $(Q) $(CC) -c $(AFLAGS) -DHeap_Size=0x00000700 -DStack_Size=0x00000B00 $< -o $@
+ $(Q) $(CC) -c $(CFLAGS) $< -o $@
+
+$(COBJS_NS): $(OBJDIR)/%$(OBJEXT): %.c
+ $(Q) mkdir -p $(OBJDIR)/$(dir $<)
+ @echo "CC: $<"
+ $(Q) $(CC) -c $(CFLAGS) $< -o $@
+
+mtower_ns$(EXEEXT): $(OBJS_NS)
+ $(Q) $(MAKE) -C ../../ TOPDIR="$(TOPDIR)" liblibc.a
+ $(Q) $(MAKE) -C ../../ TOPDIR="$(TOPDIR)" libmm.a
+ $(Q) $(MAKE) -C ../../ TOPDIR="$(TOPDIR)" liblhal.a
+ $(Q) $(MAKE) -C ../../ TOPDIR="$(TOPDIR)" libstd.a
+ $(Q) $(MAKE) -C ../../ TOPDIR="$(TOPDIR)" libfreertos.a
+ @echo "LD: mTower_ns$(EXEEXT)"
+# $(Q) $(CC) $(CFLAGS) -Wl,--section-start=.text=$(CONFIG_START_ADDRESS_BL33) -Tmetal.freertos.lds $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf
+# $(Q) $(CC) $(CFLAGS) -nostartfiles -Wl,--defsym,__stack_size=0x300 -Wl,--defsym,__heap_size=0x100 -Tmetal.freertos.lds $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf
+# $(Q) $(CC) $(CFLAGS) -nostartfiles -Wl,--defsym,__stack_size=0x300 -Wl,--defsym,__heap_size=0x100 -Tbl808_flash_m0.ld $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf
+# $(Q) $(CC) $(CFLAGS) -nostartfiles -fms-extensions -ffunction-sections -fdata-sections --specs=nano.specs -Tbl808_flash_m0.ld $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf
+# -Wl,-Map=$(TOPDIR)/../bl_mcu_sdk/examples/helloworld/build/build_out/helloworld_bl808_m0.map
+# $(Q) $(CC) -Tbl808_flash_m0.ld -Wl,--cref -Wl,--gc-sections -nostartfiles -fms-extensions -ffunction-sections -fdata-sections --specs=nano.specs -ufw_header -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907 $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf
+# $(Q) $(CC) $(CFLAGS) -Tbl808_flash_m0.ld -Wl,--cref -Wl,--gc-sections -nostartfiles -fms-extensions -ffunction-sections -fdata-sections --specs=nano.specs -ufw_header -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907 $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf
+# -Wl,-Map=$(TOPDIR)/../bl_mcu_sdk/examples/helloworld/build/build_out/helloworld_bl808_m0.map
+ $(Q) $(CC) -Tbl808_flash_m0.ld -Wl,--gc-sections -nostartfiles -fms-extensions -ffunction-sections -fdata-sections --specs=nano.specs -ufw_header -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907 $(OBJS_NS) -o $(OBJDIR)/bl33.elf $(LIBPATHS) $(LIBS)
+ $(Q) $(OBJCOPY) -S -O binary $(OBJDIR)/bl33.elf $(OBJDIR)/bl33.bin
+ $(Q) $(OBJCOPY) -S -O ihex $(OBJDIR)/bl33.elf $(OBJDIR)/bl33.hex
+
+clean:
+ $(Q) rm -f ../../StdDriver/src/*$(OBJEXT)
+
+distclean: clean
+
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/bl808_flash_m0.ld b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/bl808_flash_m0.ld
new file mode 100644
index 00000000..cbd6d8e0
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/bl808_flash_m0.ld
@@ -0,0 +1,300 @@
+/****************************************************************************************
+* @file flash.ld
+*
+* @brief This file is the link script file (gnuarm or armgcc).
+*
+* Copyright (C) BouffaloLab 2021
+*
+****************************************************************************************
+*/
+
+/* configure the CPU type */
+OUTPUT_ARCH( "riscv" )
+/* link with the standard c library */
+INPUT(-lc)
+/* link with the standard GCC library */
+INPUT(-lgcc)
+/* configure the entry point */
+ENTRY(__start)
+
+/* StackSize = 0x0400; 1KB */
+StackSize = 0x1000; /* 4KB */
+HeapMinSize = 0x1000; /* 4KB */
+
+MEMORY
+{
+ fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
+ xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
+ itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K
+ dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K
+ nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K
+ ram_memory (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K
+ xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
+}
+
+SECTIONS
+{
+ .fw_header :
+ {
+ KEEP(*(.fw_header))
+ } > fw_header_memory
+
+ .text :
+ {
+ . = ALIGN(4);
+ __text_code_start__ = .;
+
+ KEEP (*(SORT_NONE(.init)))
+ KEEP (*(SORT_NONE(.vector)))
+ . = ALIGN(128);
+ __unprivileged_section_start__ = .;
+
+ *(.text)
+ *(.text.*)
+
+ /* section information for shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for usb usbh_class_info */
+ . = ALIGN(4);
+ __usbh_class_info_start__ = .;
+ KEEP(*(.usbh_class_info))
+ . = ALIGN(4);
+ __usbh_class_info_end__ = .;
+
+ /*put .rodata**/
+ *(EXCLUDE_FILE( *bl808_glb*.o* \
+ *bl808_glb_gpio*.o* \
+ *bl808_pds*.o* \
+ *bl808_aon*.o* \
+ *bl808_hbn*.o* \
+ *bl808_l1c*.o* \
+ *bl808_common*.o* \
+ *bl808_clock*.o* \
+ *bl808_ef_ctrl*.o* \
+ *bl808_sf_cfg*.o* \
+ *bl808_sf_ctrl*.o* \
+ *bl808_sflash*.o* \
+ *bl808_xip_sflash*.o* \
+ *bl808_romapi_patch*.o* ) .rodata*)
+ *(.srodata)
+ *(.srodata.*)
+
+ . = ALIGN(4);
+ __text_code_end__ = .;
+ } > xip_memory
+
+ .unprivileged_section : ALIGN (128)
+ {
+ . = ALIGN(32);
+ /* __unprivileged_section_start__ = .; */
+ KEEP(*(unprivileged_section))
+ *main.o*(.unprivileged_section*)
+ . = ALIGN(128);
+ __unprivileged_section_end__ = .;
+ } > xip_memory
+
+ .privileged_functions : ALIGN (128)
+ {
+ . = ALIGN(32);
+ __privileged_functions_start__ = .;
+ KEEP(*(privileged_functions))
+ __privileged_functions_end__ = .;
+ } > xip_memory
+
+ . = ALIGN(4);
+ __itcm_load_addr = .;
+
+ .itcm_region : AT (__itcm_load_addr)
+ {
+ . = ALIGN(4);
+ __tcm_code_start__ = .;
+
+ *(.tcm_code.*)
+ *(.tcm_const.*)
+ *(.sclock_rlt_code.*)
+ *(.sclock_rlt_const.*)
+
+ *bl808_glb*.o*(.rodata*)
+ *bl808_glb_gpio*.o*(.rodata*)
+ *bl808_pds*.o*(.rodata*)
+ *bl808_aon*.o*(.rodata*)
+ *bl808_hbn*.o*(.rodata*)
+ *bl808_l1c*.o*(.rodata*)
+ *bl808_common*.o*(.rodata*)
+ *bl808_clock*.o*(.rodata*)
+ *bl808_ef_ctrl*.o*(.rodata*)
+ *bl808_sf_cfg*.o*(.rodata*)
+ *bl808_sf_ctrl*.o*(.rodata*)
+ *bl808_sflash*.o*(.rodata*)
+ *bl808_xip_sflash*.o*(.rodata*)
+ *bl808_romapi_patch*.o*(.rodata*)
+
+ . = ALIGN(4);
+ __tcm_code_end__ = .;
+ } > itcm_memory
+
+ __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+ .dtcm_region : AT (__dtcm_load_addr)
+ {
+ . = ALIGN(4);
+ __tcm_data_start__ = .;
+
+ *(.tcm_data)
+ /* *finger_print.o(.data*) */
+
+ . = ALIGN(4);
+ __tcm_data_end__ = .;
+ } > dtcm_memory
+
+ /*************************************************************************/
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(0x4);
+ . = . + StackSize;
+ . = ALIGN(0x4);
+ } > dtcm_memory
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
+ PROVIDE( __freertos_irq_stack_top = __StackTop);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+ /*************************************************************************/
+ __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
+ .nocache_ram_region : AT (__nocache_ram_load_addr)
+ {
+ . = ALIGN(4);
+ __nocache_ram_data_start__ = .;
+
+ *(.nocache_ram)
+
+ . = ALIGN(4);
+ __nocache_ram_data_end__ = .;
+ } > nocache_ram_memory
+
+ __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
+
+ /* Data section */
+ RAM_DATA : AT (__ram_load_addr)
+ {
+ . = ALIGN(4);
+ __ram_data_start__ = .;
+
+ PROVIDE( __global_pointer$ = . + 0x800 );
+
+ *(.data)
+ *(.data.*)
+ *(.sdata)
+ *(.sdata.*)
+ *(.sdata2)
+ *(.sdata2.*)
+/*
+ . = ALIGN(128);
+ __unprivileged_data_section_start__ = .;
+ KEEP(*(unprivileged_data_section))
+ *main.o*(.unprivileged_data_section*)
+ . = ALIGN(128);
+
+ __unprivileged_data_section_end__ = .;
+ . = ALIGN(128);
+*/
+ . = ALIGN(4);
+ __bflog_tags_start__ = .;
+ *(.bflog_tags_array)
+ . = ALIGN(4);
+ __bflog_tags_end__ = .;
+ __ram_data_end__ = .;
+ /*
+ . = ALIGN(128);
+ __unprivileged_data_section_start__ = .;
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ */
+ } > ram_memory
+
+ __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
+ ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
+
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ /*
+ . = ALIGN(128);
+
+ __unprivileged_data_section_end__ = .;
+ */
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram_memory
+
+ .noinit_data (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __noinit_data_start__ = .;
+
+ *(.noinit_data*)
+
+ . = ALIGN(4);
+ __noinit_data_end__ = .;
+ } > ram_memory
+
+ .nocache_noinit_ram_region (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __nocache_noinit_ram_data_start__ = .;
+
+ *(.nocache_noinit_ram)
+ *(.noncacheable)
+
+ . = ALIGN(4);
+ __nocache_noinit_ram_data_end__ = .;
+ } > nocache_ram_memory
+
+ .privileged_data (NOLOAD) : ALIGN(32) {
+ __privileged_data_start__ = .;
+ *(privileged_data)
+ /* Non kernel data is kept out of the first _Privileged_Data_Region_Size
+ bytes of SRAM. */
+ . = ALIGN(32);
+ __privileged_data_end__ = .;
+ } > ram_memory
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(4);
+ __HeapBase = .;
+
+ /*__end__ = .;*/
+ /*end = __end__;*/
+ KEEP(*(.heap*))
+
+ . = ALIGN(4);
+ __HeapLimit = .;
+ } > ram_memory
+
+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
+ ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
+
+}
+
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/board.c b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/board.c
new file mode 100644
index 00000000..6d93dc2c
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/board.c
@@ -0,0 +1,615 @@
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl808_glb.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_tzc_sec.h"
+#include "bl808_ef_cfg.h"
+#include "bl808_uhs_phy.h"
+#include "board.h"
+
+#include "mem.h"
+
+#ifdef CONFIG_BSP_SDH_SDCARD
+#include "sdh_sdcard.h"
+#endif
+
+extern void log_start(void);
+
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+static struct bflb_device_s *uart0;
+
+#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
+static struct bflb_device_s *rtc;
+#endif
+
+#if defined(CPU_M0)
+static void system_clock_init(void)
+{
+ /* wifipll/audiopll */
+ GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL |
+ GLB_PLL_CPUPLL |
+ GLB_PLL_UHSPLL |
+ GLB_PLL_MIPIPLL);
+
+ GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M);
+ GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M);
+ GLB_Config_CPU_PLL(GLB_XTAL_40M, cpuPllCfg_480M);
+
+ CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
+}
+
+static void peripheral_clock_init(void)
+{
+ PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+ PERIPHERAL_CLOCK_SEC_ENABLE();
+ PERIPHERAL_CLOCK_DMA0_ENABLE();
+ PERIPHERAL_CLOCK_UART0_ENABLE();
+ PERIPHERAL_CLOCK_UART1_ENABLE();
+ PERIPHERAL_CLOCK_SPI0_1_ENABLE();
+ PERIPHERAL_CLOCK_I2C0_ENABLE();
+ PERIPHERAL_CLOCK_PWM0_ENABLE();
+ PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+ PERIPHERAL_CLOCK_IR_ENABLE();
+ PERIPHERAL_CLOCK_I2S_ENABLE();
+ PERIPHERAL_CLOCK_USB_ENABLE();
+ PERIPHERAL_CLOCK_CAN_UART2_ENABLE();
+
+ GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 4);
+ GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
+ GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, 0);
+ GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
+ GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
+ GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
+ GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+ GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
+ GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
+ GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
+ GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
+
+ GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
+
+#ifdef CONFIG_BSP_SDH_SDCARD
+ PERIPHERAL_CLOCK_SDH_ENABLE();
+ uint32_t tmp_val;
+ tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5);
+ uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN);
+ tmp_val2 &= ~(1 << 0);
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2);
+ BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val);
+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH);
+#endif
+#ifdef CONFIG_BSP_CSI
+ GLB_CSI_Config_MIPIPLL(2, 0x21000);
+ GLB_CSI_Power_Up_MIPIPLL();
+ GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1);
+#endif
+ GLB_Set_USB_CLK_From_WIFIPLL(1);
+}
+
+#ifdef CONFIG_PSRAM
+#define WB_4MB_PSRAM (1)
+#define UHS_32MB_PSRAM (2)
+#define UHS_64MB_PSRAM (3)
+#define WB_32MB_PSRAM (4)
+#define NONE_UHS_PSRAM (-1)
+
+int uhs_psram_init(void)
+{
+ PSRAM_UHS_Cfg_Type psramDefaultCfg = {
+ 2000,
+ PSRAM_MEM_SIZE_32MB,
+ PSRAM_PAGE_SIZE_2KB,
+ PSRAM_UHS_NORMAL_TEMP,
+ };
+
+ bflb_efuse_device_info_type chip_info;
+ bflb_ef_ctrl_get_device_info(&chip_info);
+ if (chip_info.psramInfo == UHS_32MB_PSRAM) {
+ psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB;
+ } else if (chip_info.psramInfo == UHS_64MB_PSRAM) {
+ psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB;
+ } else {
+ return -1;
+ }
+
+ //init uhs PLL; Must open uhs pll first, and then initialize uhs psram
+ GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
+ //init uhs psram ;
+ // Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000);
+ Psram_UHS_x16_Init_Override(&psramDefaultCfg);
+ Tzc_Sec_PSRAMA_Access_Release();
+
+ // example: 2000Mbps typical cal values
+ uhs_phy_cal_res->rl = 39;
+ uhs_phy_cal_res->rdqs = 3;
+ uhs_phy_cal_res->rdq = 0;
+ uhs_phy_cal_res->wl = 13;
+ uhs_phy_cal_res->wdqs = 4;
+ uhs_phy_cal_res->wdq = 5;
+ uhs_phy_cal_res->ck = 9;
+ /* TODO: use uhs psram trim update */
+ set_uhs_latency_r(uhs_phy_cal_res->rl);
+ cfg_dqs_rx(uhs_phy_cal_res->rdqs);
+ cfg_dq_rx(uhs_phy_cal_res->rdq);
+ set_uhs_latency_w(uhs_phy_cal_res->wl);
+ cfg_dq_drv(uhs_phy_cal_res->wdq);
+ cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1);
+ cfg_dqs_drv(uhs_phy_cal_res->wdqs);
+ // set_odt_en();
+ mr_read_back();
+ return 0;
+}
+#endif
+#endif
+
+void bl_show_log(void)
+{
+ printf("\r\n");
+ printf(" ____ __ __ _ _ _ \r\n");
+ printf(" | _ \\ / _|/ _| | | | | | | \r\n");
+ printf(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n");
+ printf(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n");
+ printf(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n");
+ printf(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n");
+ printf("\r\n");
+ printf("Build:%s,%s\r\n", __TIME__, __DATE__);
+ printf("Copyright (c) 2022 Bouffalolab team\r\n");
+}
+
+void bl_show_flashinfo(void)
+{
+ spi_flash_cfg_type flashCfg;
+ uint8_t *pFlashCfg = NULL;
+ uint32_t flashCfgLen = 0;
+ uint32_t flashJedecId = 0;
+
+ flashJedecId = bflb_flash_get_jedec_id();
+ bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen);
+ arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen);
+ printf("=========== flash cfg ==============\r\n");
+ printf("jedec id 0x%06X\r\n", flashJedecId);
+ printf("mid 0x%02X\r\n", flashCfg.mid);
+ printf("iomode 0x%02X\r\n", flashCfg.io_mode);
+ printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
+ printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
+ printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
+ printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
+ printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
+ printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
+ printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
+ printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
+ printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
+ printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
+ printf("=====================================\r\n");
+}
+
+extern void bflb_uart_set_console(struct bflb_device_s *dev);
+
+static void console_init()
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+#if defined(CPU_M0)
+ bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX);
+ bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX);
+#elif defined(CPU_D0)
+ /* sipeed m1s dock */
+ bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+#elif defined(CPU_LP)
+ /* map GPIO_PIN_18 and GPIO_PIN_19 as UART for LP core */
+ bflb_gpio_uart_init(gpio, GPIO_PIN_18, GPIO_UART_FUNC_UART1_TX);
+ bflb_gpio_uart_init(gpio, GPIO_PIN_19, GPIO_UART_FUNC_UART1_RX);
+#endif
+ struct bflb_uart_config_s cfg;
+ cfg.baudrate = 2000000;
+ cfg.data_bits = UART_DATA_BITS_8;
+ cfg.stop_bits = UART_STOP_BITS_1;
+ cfg.parity = UART_PARITY_NONE;
+ cfg.flow_ctrl = 0;
+ cfg.tx_fifo_threshold = 7;
+ cfg.rx_fifo_threshold = 7;
+#if defined(CPU_M0)
+ uart0 = bflb_device_get_by_name("uart0");
+#elif defined(CPU_D0)
+ uart0 = bflb_device_get_by_name("uart3");
+#elif defined(CPU_LP)
+ uart0 = bflb_device_get_by_name("uart1");
+#endif
+ bflb_uart_init(uart0, &cfg);
+
+ bflb_uart_putchar(uart0, 'A');
+
+ bflb_uart_set_console(uart0);
+ bflb_uart_putchar(uart0, 'B');
+}
+
+#if defined(CPU_M0)
+void board_init(void)
+{
+ int ret = -1;
+ uintptr_t flag;
+
+ flag = bflb_irq_save();
+
+ GLB_Halt_CPU(GLB_CORE_ID_D0);
+ GLB_Halt_CPU(GLB_CORE_ID_LP);
+
+ ret = bflb_flash_init();
+
+ system_clock_init();
+ peripheral_clock_init();
+ bflb_irq_initialize();
+
+ console_init();
+ // printf("\r\nflag = %p\r\n",flag);
+ // printf("\r\nflag = %x\r\n",flag);
+
+#ifdef CONFIG_PSRAM
+ if (uhs_psram_init() < 0) {
+ while (1) {
+ }
+ }
+#endif
+ size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
+ kmem_init((void *)&__HeapBase, heap_len);
+
+ // bl_show_log();
+ // if (ret != 0) {
+ // printf("flash init fail!!!\r\n");
+ // }
+ // bl_show_flashinfo();
+
+ // printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
+
+ // printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
+ // printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
+
+ // log_start();
+
+// #if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
+// rtc = bflb_device_get_by_name("rtc");
+// #endif
+
+// /* set CPU D0 boot XIP address and flash address */
+// Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
+// /* D0 boot from 0x58000000 */
+// GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
+// /* D0 image offset on flash is CONFIG_D0_FLASH_ADDR+0x1000(header) */
+// bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR + 0x1000, 1, SF_CTRL_FLASH_BANK0);
+
+// Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_LP, 0);
+// /* LP boot from 0x58020000 */
+// GLB_Set_CPU_Reset_Address(GLB_CORE_ID_LP, 0x58020000);
+ bflb_irq_restore(flag);
+ // GLB_Release_CPU(GLB_CORE_ID_D0);
+ // GLB_Release_CPU(GLB_CORE_ID_LP);
+
+ /* release d0 and then do can run */
+ // BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
+ // BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
+ // L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8);
+}
+#elif defined(CPU_D0)
+void board_init(void)
+{
+ CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
+
+ bflb_irq_initialize();
+
+ size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
+ kmem_init((void *)&__HeapBase, heap_len);
+
+ console_init();
+
+ bl_show_log();
+
+ printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
+
+ printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
+ printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
+ printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
+
+ log_start();
+}
+#elif defined(CPU_LP)
+void board_init(void)
+{
+ CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
+
+ bflb_irq_initialize();
+
+ console_init();
+
+ bl_show_log();
+
+ printf("lp does not use memheap due to little ram \r\n");
+
+ printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
+ printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
+ printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
+
+ log_start();
+}
+#endif
+
+void board_uartx_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+
+ bflb_gpio_uart_init(gpio, GPIO_PIN_4, GPIO_UART_FUNC_UART1_TX);
+ bflb_gpio_uart_init(gpio, GPIO_PIN_5, GPIO_UART_FUNC_UART1_RX);
+ bflb_gpio_uart_init(gpio, GPIO_PIN_6, GPIO_UART_FUNC_UART1_CTS);
+ bflb_gpio_uart_init(gpio, GPIO_PIN_7, GPIO_UART_FUNC_UART1_RTS);
+}
+
+void board_i2c0_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ /* I2C0_SDA */
+ bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ /* I2C0_SCL */
+ bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+}
+
+void board_spi0_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ /* spi cs */
+ bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ /* spi miso */
+ bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ /* spi mosi */
+ bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ /* spi clk */
+ bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+}
+
+void board_pwm_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+}
+
+void board_adc_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ /* ADC_CH0 */
+ bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH1 */
+ bflb_gpio_init(gpio, GPIO_PIN_5, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH2 */
+ bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH3 */
+ bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH4 */
+ bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH5 */
+ //bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH6 */
+ bflb_gpio_init(gpio, GPIO_PIN_12, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH7 */
+ bflb_gpio_init(gpio, GPIO_PIN_13, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH8 */
+ bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH9 */
+ bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH10 */
+ bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* ADC_CH11,note the FLASH pin */
+ //bflb_gpio_init(gpio, GPIO_PIN_34, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+}
+
+void board_dac_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ /* DAC_CHA */
+ bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ /* DAC_CHB */
+ bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+}
+
+void board_ir_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+ bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_0);
+ GLB_IR_RX_GPIO_Sel(GLB_GPIO_PIN_17);
+}
+
+void board_emac_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_32, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+
+#if defined(BL808)
+ // GLB_PER_Clock_UnGate(1<<12);
+#endif
+}
+
+void board_sdh_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_init(gpio, GPIO_PIN_0, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+ bflb_gpio_init(gpio, GPIO_PIN_1, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+ bflb_gpio_init(gpio, GPIO_PIN_2, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+ bflb_gpio_init(gpio, GPIO_PIN_3, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+ bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+ bflb_gpio_init(gpio, GPIO_PIN_5, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+}
+
+void board_dvp_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ /* I2C GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+
+ /* Power down GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_reset(gpio, GPIO_PIN_21);
+
+ /* Reset GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_set(gpio, GPIO_PIN_20);
+
+ /* MCLK GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+
+ /* DVP GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_32, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+}
+
+void board_csi_gpio_init(void)
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+
+ GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V);
+#if 1 /* sipeed m1s dock */
+ /* I2C GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+
+ /* MCLK GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+
+ /* Power down GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_reset(gpio, GPIO_PIN_40);
+
+ /* Reset GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_41, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_mtimer_delay_us(20);
+ bflb_gpio_set(gpio, GPIO_PIN_41);
+#else
+ /* I2C GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+
+ /* MCLK GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+
+ /* Power down GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_gpio_reset(gpio, GPIO_PIN_6);
+
+ /* Reset GPIO */
+ bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+ bflb_mtimer_delay_us(20);
+ bflb_gpio_set(gpio, GPIO_PIN_23);
+#endif
+}
+
+void board_iso11898_gpio_init()
+{
+ struct bflb_device_s *gpio;
+
+ gpio = bflb_device_get_by_name("gpio");
+ bflb_gpio_iso11898_init(gpio, GPIO_PIN_14, GPIO_ISO11898_FUNC_TX);
+ bflb_gpio_iso11898_init(gpio, GPIO_PIN_15, GPIO_ISO11898_FUNC_RX);
+}
+
+#ifdef CONFIG_BFLOG
+__attribute__((weak)) uint64_t bflog_clock(void)
+{
+ return bflb_mtimer_get_time_us();
+}
+
+__attribute__((weak)) uint32_t bflog_time(void)
+{
+ return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc));
+}
+
+__attribute__((weak)) char *bflog_thread(void)
+{
+ return "";
+}
+#endif
+
+#ifdef CONFIG_LUA
+__attribute__((weak)) clock_t luaport_clock(void)
+{
+ return (clock_t)bflb_mtimer_get_time_us();
+}
+
+__attribute__((weak)) time_t luaport_time(time_t *seconds)
+{
+ time_t t = (time_t)BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc));
+ if (seconds != NULL) {
+ *seconds = t;
+ }
+
+ return t;
+}
+#endif
+
+#ifdef CONFIG_FATFS
+#include "bflb_timestamp.h"
+__attribute__((weak)) uint32_t get_fattime(void)
+{
+ bflb_timestamp_t tm;
+
+ bflb_timestamp_utc2time(BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)), &tm);
+
+ return ((uint32_t)(tm.year - 1980) << 25) /* Year 2015 */
+ | ((uint32_t)tm.mon << 21) /* Month 1 */
+ | ((uint32_t)tm.mday << 16) /* Mday 1 */
+ | ((uint32_t)tm.hour << 11) /* Hour 0 */
+ | ((uint32_t)tm.min << 5) /* Min 0 */
+ | ((uint32_t)tm.sec >> 1); /* Sec 0 */
+}
+#endif
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/board.h b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/board.h
new file mode 100644
index 00000000..99f61e98
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/board.h
@@ -0,0 +1,29 @@
+#ifndef _BOARD_H
+#define _BOARD_H
+
+void board_init(void);
+
+void board_jtag_gpio_init(void);
+void board_uartx_gpio_init(void);
+void board_i2c0_gpio_init(void);
+void board_spi0_gpio_init(void);
+void board_pwm_gpio_init(void);
+void board_adc_gpio_init(void);
+void board_dac_gpio_init(void);
+void board_ir_gpio_init(void);
+void board_emac_gpio_init(void);
+void board_sdh_gpio_init(void);
+void board_dvp_gpio_init(void);
+void board_csi_gpio_init(void);
+void board_iso11898_gpio_init(void);
+
+#define DEFAULT_TEST_UART "uart1"
+#define DEFAULT_TEST_UART_DMA_TX_REQUEST DMA_REQUEST_UART1_TX
+#define DEFAULT_TEST_UART_DMA_RX_REQUEST DMA_REQUEST_UART1_RX
+#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART1_TDR
+#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART1_RDR
+
+#define CONFIG_D0_FLASH_ADDR 0x100000
+#define CONFIG_LP_FLASH_ADDR 0x20000
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/flash_prog_cfg.ini b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/flash_prog_cfg.ini
new file mode 100644
index 00000000..b2ab73ea
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/flash_prog_cfg.ini
@@ -0,0 +1,11 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ../../../../../../build/nonsecure/arch/riscv32/bl808/src/pine64_ox64/nonsecure/bl33.bin
+address = 0x000000
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/fw_header.c b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/fw_header.c
new file mode 100644
index 00000000..73f79484
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/fw_header.c
@@ -0,0 +1,208 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+ .magiccode = 0x504e4642,
+ .rivison = 0x00000001,
+ /*flash config */
+ .flash_cfg.magiccode = 0x47464346,
+ .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+ .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+ .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+ .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+ .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
+ .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
+ .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
+ .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
+ .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
+ .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
+ .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
+ .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
+ .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
+ .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
+ .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
+ .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
+ .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
+ .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
+ .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
+ .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
+ .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
+ .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
+ .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
+ .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
+ .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
+ .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
+ .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
+ .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
+ .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
+ .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
+ .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
+ .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
+ .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
+ .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
+ .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
+ .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
+ .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
+ .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
+ .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
+ .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
+ .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
+ .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
+ .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
+ .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
+ .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
+ .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
+ .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
+ .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
+ .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
+ .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
+ .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
+ .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
+ .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
+ .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
+ .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
+ .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
+ .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
+ .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
+ .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
+ .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
+ .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
+ .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
+ .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
+ .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
+ .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
+ .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
+ .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
+ .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
+ .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+ .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
+ .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
+ .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
+ .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
+ .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
+ .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
+ .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
+ .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
+ .flash_cfg.cfg.qeData = 0, /*!< QE set data */
+ .flash_cfg.crc32 = 0xdeadbeef,
+ /* clock cfg */
+ .clk_cfg.magiccode = 0x47464350,
+ .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
+ .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
+ .clk_cfg.cfg.mcu_clk_div = 0x00,
+ .clk_cfg.cfg.mcu_bclk_div = 0x00,
+
+ .clk_cfg.cfg.mcu_pbclk_div = 0x03,
+ .clk_cfg.cfg.lp_div = 0x01,
+ .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
+ .clk_cfg.cfg.dsp_clk_div = 0x00,
+
+ .clk_cfg.cfg.dsp_bclk_div = 0x01,
+ .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
+ .clk_cfg.cfg.dsp_pbclk_div = 0x00,
+ .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
+
+ .clk_cfg.cfg.emi_clk_div = 0x01,
+ .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
+ .clk_cfg.cfg.flash_clk_div = 0x00,
+ .clk_cfg.cfg.wifipll_pu = 0x01,
+
+ .clk_cfg.cfg.aupll_pu = 0x01,
+ .clk_cfg.cfg.cpupll_pu = 0x01,
+ .clk_cfg.cfg.mipipll_pu = 0x01,
+ .clk_cfg.cfg.uhspll_pu = 0x01,
+
+ .clk_cfg.crc32 = 0xdeadbeef,
+
+ /* basic cfg */
+ .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
+ .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
+ .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
+ .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
+ .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
+ .basic_cfg.no_segment = 0x1, /* [8] no segment info */
+ .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
+ .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
+ .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
+ .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
+ .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
+ .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
+ .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
+ .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
+ .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
+#if 0
+# 0 : cmds bypass wrap commands to macro, original mode;
+# 1 : cmds handle wrap commands, original mode;
+# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
+# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
+#endif
+ .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
+#if 0
+# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
+# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
+#endif
+ .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
+ .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
+ .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
+ .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
+
+#ifdef BFLB_BOOT2
+ .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
+#else
+ .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
+#endif
+ .basic_cfg.aes_region_len = 0x00000000, /* aes region length */
+
+ .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
+ .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
+
+ /* cpu cfg */
+ .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
+ .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
+ .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
+ .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[0].rsvd = 0x0,
+
+ .cpu_cfg[0].cache_range_h = 0x00000000,
+ .cpu_cfg[0].cache_range_l = 0x00000000,
+ /* image_address_offset */
+ .cpu_cfg[0].image_address_offset = 0x0,
+ .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
+ .cpu_cfg[0].msp_val = 0x00000000, /* msp value */
+
+ /* cpu cfg */
+ .cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */
+ .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
+ .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
+ .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
+ .cpu_cfg[1].rsvd = 0x0,
+
+ .cpu_cfg[1].cache_range_h = 0x00000000,
+ .cpu_cfg[1].cache_range_l = 0x00000000,
+ /* image_address_offset */
+ .cpu_cfg[1].image_address_offset = 0x0,
+ .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
+ .cpu_cfg[1].msp_val = 0x00000000, /* msp value */
+
+ /* address of partition table 0 */ /* 4 */
+ .boot2_pt_table_0_rsvd = 0x00000000,
+ /* address of partition table 1 */ /* 4 */
+ .boot2_pt_table_1_rsvd = 0x00000000,
+
+ /* address of flashcfg table list */ /* 4 */
+ .flash_cfg_table_addr = 0x00000000,
+ /* flashcfg table list len */ /* 4 */
+ .flash_cfg_table_len = 0x00000000,
+
+ .rsvd1[0] = 0x20000320,
+ .rsvd1[1] = 0x00000000,
+ .rsvd1[2] = 0x2000F038,
+ .rsvd1[3] = 0x18000000,
+
+ .crc32 = 0xdeadbeef /* 4 */
+};
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/fw_header.h b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/fw_header.h
new file mode 100644
index 00000000..cbbbc607
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/fw_header.h
@@ -0,0 +1,213 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+ uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+ uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+ uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+ uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+ uint8_t resetEnCmd; /*!< Flash enable reset command */
+ uint8_t resetCmd; /*!< Flash reset command */
+ uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
+ uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
+ uint8_t jedecIdCmd; /*!< JEDEC ID command */
+ uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
+ uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
+ uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
+ uint8_t sectorSize; /*!< *1024bytes */
+ uint8_t mid; /*!< Manufacturer ID */
+ uint16_t pageSize; /*!< Page size */
+ uint8_t chipEraseCmd; /*!< Chip erase cmd */
+ uint8_t sectorEraseCmd; /*!< Sector erase command */
+ uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
+ uint8_t blk64EraseCmd; /*!< Block 64K erase command */
+ uint8_t writeEnableCmd; /*!< Need before every erase or program */
+ uint8_t pageProgramCmd; /*!< Page program cmd */
+ uint8_t qpageProgramCmd; /*!< QIO page program cmd */
+ uint8_t qppAddrMode; /*!< QIO page program address mode */
+ uint8_t fastReadCmd; /*!< Fast read command */
+ uint8_t frDmyClk; /*!< Fast read command dummy clock */
+ uint8_t qpiFastReadCmd; /*!< QPI fast read command */
+ uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
+ uint8_t fastReadDoCmd; /*!< Fast read dual output command */
+ uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
+ uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
+ uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
+ uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
+ uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
+ uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
+ uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
+ uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
+ uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
+ uint8_t qpiPageProgramCmd; /*!< QPI program command */
+ uint8_t writeVregEnableCmd; /*!< Enable write reg */
+ uint8_t wrEnableIndex; /*!< Write enable register index */
+ uint8_t qeIndex; /*!< Quad mode enable register index */
+ uint8_t busyIndex; /*!< Busy status register index */
+ uint8_t wrEnableBit; /*!< Write enable bit pos */
+ uint8_t qeBit; /*!< Quad enable bit pos */
+ uint8_t busyBit; /*!< Busy status bit pos */
+ uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
+ uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
+ uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
+ uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
+ uint8_t releasePowerDown; /*!< Release power down command */
+ uint8_t busyReadRegLen; /*!< Register length of contain busy status */
+ uint8_t readRegCmd[4]; /*!< Read register command buffer */
+ uint8_t writeRegCmd[4]; /*!< Write register command buffer */
+ uint8_t enterQpi; /*!< Enter qpi command */
+ uint8_t exitQpi; /*!< Exit qpi command */
+ uint8_t cReadMode; /*!< Config data for continuous read mode */
+ uint8_t cRExit; /*!< Config data for exit continuous read mode */
+ uint8_t burstWrapCmd; /*!< Enable burst wrap command */
+ uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
+ uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
+ uint8_t burstWrapData; /*!< Data to enable burst wrap */
+ uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
+ uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+ uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
+ uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
+ uint16_t timeEsector; /*!< 4K erase time */
+ uint16_t timeE32k; /*!< 32K erase time */
+ uint16_t timeE64k; /*!< 64K erase time */
+ uint16_t timePagePgm; /*!< Page program time */
+ uint16_t timeCe; /*!< Chip erase time in ms */
+ uint8_t pdDelay; /*!< Release power down command delay time for wake up */
+ uint8_t qeData; /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+ uint32_t magiccode;
+ struct spi_flash_cfg_t cfg;
+ uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+ uint8_t xtal_type;
+ uint8_t mcu_clk;
+ uint8_t mcu_clk_div;
+ uint8_t mcu_bclk_div;
+
+ uint8_t mcu_pbclk_div;
+ uint8_t lp_div;
+ uint8_t dsp_clk;
+ uint8_t dsp_clk_div;
+
+ uint8_t dsp_bclk_div;
+ uint8_t dsp_pbclk;
+ uint8_t dsp_pbclk_div;
+ uint8_t emi_clk;
+
+ uint8_t emi_clk_div;
+ uint8_t flash_clk_type;
+ uint8_t flash_clk_div;
+ uint8_t wifipll_pu;
+
+ uint8_t aupll_pu;
+ uint8_t cpupll_pu;
+ uint8_t mipipll_pu;
+ uint8_t uhspll_pu;
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+ uint32_t magiccode;
+ struct sys_clk_cfg_t cfg;
+ uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
+ uint32_t sign_type : 2; /* [1: 0] for sign */
+ uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
+ uint32_t key_sel : 2; /* [5: 4] key slot */
+ uint32_t xts_mode : 1; /* [6] for xts mode */
+ uint32_t aes_region_lock : 1; /* [7] rsvd */
+ uint32_t no_segment : 1; /* [8] no segment info */
+ uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
+ uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
+ uint32_t cpu_master_id : 4; /* [14: 11] master id */
+ uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
+ uint32_t crc_ignore : 1; /* [16] ignore crc */
+ uint32_t hash_ignore : 1; /* [17] hash ignore */
+ uint32_t power_on_mm : 1; /* [18] power on mm */
+ uint32_t em_sel : 3; /* [21: 19] em_sel */
+ uint32_t cmds_en : 1; /* [22] command spliter enable */
+ uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
+ uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
+ uint32_t icache_invalid : 1; /* [29] icache invalid */
+ uint32_t dcache_invalid : 1; /* [30] dcache invalid */
+ uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
+
+ uint32_t group_image_offset; /* flash controller offset */
+ uint32_t aes_region_len; /* aes region length */
+
+ uint32_t img_len_cnt; /* image length or segment count */
+ uint32_t hash[32 / 4]; /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
+ uint8_t config_enable; /* coinfig this cpu */
+ uint8_t halt_cpu; /* halt this cpu */
+ uint8_t cache_enable : 1; /* cache setting */
+ uint8_t cache_wa : 1; /* cache setting */
+ uint8_t cache_wb : 1; /* cache setting */
+ uint8_t cache_wt : 1; /* cache setting */
+ uint8_t cache_way_dis : 4; /* cache setting */
+ uint8_t rsvd;
+
+ uint32_t cache_range_h; /* cache range high */
+ uint32_t cache_range_l; /* cache range low */
+
+ uint32_t image_address_offset; /* image_address_offset */
+ uint32_t rsvd0; /* rsvd0 */
+ uint32_t msp_val; /* msp value */
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+ uint8_t aesiv[16];
+ uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+ uint8_t eckeyx[32]; /* ec key in boot header */
+ uint8_t eckeyy[32]; /* ec key in boot header */
+ uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+ uint32_t sig_len;
+ uint8_t signature[32];
+ uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+ uint32_t magiccode; /* 4 */
+ uint32_t rivison; /* 4 */
+
+ struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+ struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */
+
+ struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
+
+ struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
+
+ uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
+ uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
+
+ uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
+ uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
+
+ uint32_t rsvd0[8]; /* rsvd */
+ uint32_t rsvd1[8]; /* rsvd */
+
+ uint32_t rsvd3[5]; /* 20 */
+
+ uint32_t crc32; /* 4 */
+};
+
+#define BFLB_FW_LENGTH_OFFSET 140
+#define BFLB_FW_HASH_OFFSET 144
+
+#endif
\ No newline at end of file
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/main.c b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/main.c
new file mode 100644
index 00000000..a0c6321d
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/main.c
@@ -0,0 +1,998 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include
+#include "semphr.h"
+#include "board.h"
+#include "task.h"
+#include "queue.h"
+
+#include
+#include "version.h">
+
+#include "tzc_sec_reg.h"
+#include "rv_hart.h"
+#include "rv_pmp.h"
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl808_glb.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_tzc_sec.h"
+#include "bl808_ef_cfg.h"
+#include "bl808_uhs_phy.h"
+#include "board.h"
+
+#include "mem.h"
+
+#ifdef CONFIG_BSP_SDH_SDCARD
+#include "sdh_sdcard.h"
+#endif
+
+struct bflb_device_s *uart0;
+extern void bflb_uart_set_console(struct bflb_device_s *dev);
+
+extern pmp_info_t xPmpInfo;
+
+#define CONFIG_APPS_SPY
+#define CONFIG_APPS_HELLO_WORLD
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+
+#ifndef _RTL_
+/* The 1s value is converted to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_TICK_COUNT_FOR_1S pdMS_TO_TICKS( 1000 )
+#else
+/* For RTL Simulation we reduce the waiting timing, otherwise the simulation
+ * will take too more time */
+/* The 10ms value is converted to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_TICK_COUNT_FOR_1S pdMS_TO_TICKS( 10 )
+#endif
+/* The maximum number items the queue can hold. The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue. Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH ( 1 )
+
+#if( portUSING_MPU_WRAPPERS == 1 )
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;
+extern pmp_info_t xPmpInfo;
+#endif
+
+/*-----------------------------------------------------------*/
+/*
+ * Functions:
+ * - prvSetupHardware: Setup Hardware according CPU and Board.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+// void vTaskCode( void * pvParameters ) FREERTOS_SYSTEM_CALL; // PRIVILEGED_FUNCTION;
+static void vTaskCode( void * pvParameters ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Implements the task which has Read Only access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvROAccessTask( void * pvParameters );
+
+/**
+ * @brief Implements the task which has Read Write access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvRWAccessTask( void * pvParameters );
+
+/**
+ * @brief Size of the shared memory region.
+ */
+#define SHARED_MEMORY_SIZE 16
+
+/**
+ * @brief Memory region shared between two tasks.
+ */
+__attribute__ ((aligned(128))) uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ];
+// static uint8_t ucSharedMemory1[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) );
+// static uint8_t ucSharedMemory2[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+void _putchar(char character){
+ MPU_bflb_uart_putchar(uart0, character);
+}
+
+/* Task to be created. */
+// void vTaskCode( void * pvParameters ) FREERTOS_SYSTEM_CALL // PRIVILEGED_FUNCTION
+// static void vTaskCode( void * pvParameters ) PRIVILEGED_FUNCTION
+// {
+// unsigned long ulCounter = 0;
+// char pcWriteBuffer[200];
+
+// ( void ) pvParameters;
+
+// /* Must not just run off the end of a task function, so delete this task.
+// Note that because this task was created using xTaskCreate() the stack was
+// allocated dynamically and I have not included any code to free it again. */
+// // vTaskDelete( NULL );
+
+// /* The parameter value is expected to be 1 as 1 is passed in the
+// pvParameters value in the call to xTaskCreate() below. */
+// // configASSERT( ( ( uint32_t ) pvParameters ) == 1 );
+
+// if (portIS_PRIVILEGED() == 1) {
+// printf("%s task is running in priveleged mode\r\n", pcTaskGetName(NULL));
+// } else {
+// printf("%s task is running in unpriveleged mode\r\n", pcTaskGetName(NULL));
+// }
+// write( STDOUT_FILENO, "Test task\r\n", strlen( "Test task\r\n" ) );
+
+// for( ;; )
+// {
+// /* Task code goes here. */
+// vTaskDelay(mainQUEUE_TICK_COUNT_FOR_1S);
+// vTaskList( pcWriteBuffer );
+// printf("\033[2J\r\n");
+// printf( pcWriteBuffer );
+// printf("\r\n");
+// // printf("[ %s ] : %d\r\n", pcTaskGetName(NULL), ++ulCounter );
+// // write( STDOUT_FILENO, "Test task\r\n", strlen( "Test task\r\n" ) );
+// }
+// }
+
+/*-----------------------------------------------------------*/
+
+static void prvROAccessTask( void * pvParameters )
+{
+ /* Unused parameters. */
+ ( void ) pvParameters;
+
+ if (portIS_PRIVILEGED() == 1) {
+ printf("ROAccess task is running in priveleged mode\r\n");
+ } else {
+ printf("ROAccess task is running in unpriveleged mode\r\n");
+ }
+
+ // ucSharedMemory[ 0 ] = 1;
+
+ for( ; ; )
+ {
+ /* Wait for a 3 seconds. */
+ vTaskDelay( pdMS_TO_TICKS( 3 * 1000 ) );
+ // vTaskDelete(NULL);
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRWAccessTask( void * pvParameters )
+{
+ /* Unused parameters. */
+ ( void ) pvParameters;
+
+ if (portIS_PRIVILEGED() == 1) {
+ printf("RWAccess task is running in priveleged mode\r\n");
+ } else {
+ printf("RWAccess task is running in unpriveleged mode\r\n");
+ }
+
+ // printf("[ RWAccess ] : ucSharedMemory[0] = %d\r\n", ucSharedMemory[0]);
+ // ucSharedMemory[0] = 1;
+ // printf("[ RWAccess ] : ucSharedMemory[0] = %d\r\n", ucSharedMemory[0]);
+ // metal_tty_putc( '#' );
+
+ for( ; ; )
+ {
+ /* This task has RW access to ucSharedMemory and therefore can write to
+ * it. */
+ // ucSharedMemory[ 0 ] = 0;
+
+ /* Wait for a 3 seconds. */
+ vTaskDelay( pdMS_TO_TICKS( 3 * 1000 ) );
+ // vTaskDelete(NULL);
+ }
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief clnSrvTask - cleaning service.
+ *
+ * @param None
+ *
+ * @returns None
+ */
+static void clnSrvTask( void *pvParameters )
+{
+ const TickType_t xDelay = 1000 / portTICK_PERIOD_MS;
+
+ (void)pvParameters;
+
+ do {
+ vTaskPrioritySet( xTaskGetIdleTaskHandle(), uxTaskPriorityGet(xTaskGetCurrentTaskHandle()));
+// taskYIELD();
+ vTaskDelay( xDelay );
+ vTaskPrioritySet( xTaskGetIdleTaskHandle(), tskIDLE_PRIORITY);
+ vTaskDelay( xDelay );
+ } while (1);
+}
+
+#define BUFFER_SIZE 300
+// static __attribute__ ((aligned(16))) StackType_t xISRStack[ configMINIMAL_STACK_SIZE + 1 ] = { 0 }; //__attribute__ ((section (".heap"))) ;
+static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; //__attribute__ ((section (".heap"))) ;
+__attribute__ ((aligned(4))) uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] __attribute__ ((section (".heap")));
+
+//static StackType_t xSendTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 128 ) ) );
+//static StackType_t xReceiveTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 128 ) ) );
+/**
+ * @brief menuTask1 - .
+ *
+ * @param None
+ *
+ * @returns None
+ */
+
+void* aligned_malloc(size_t size, size_t alignment) {
+ // Allocate additional space for saving the original address and for alignment
+ uintptr_t raw_address = (uintptr_t)pvPortMalloc(size + alignment - 1 + sizeof(void*));
+
+ if (!raw_address) {
+ return NULL; // Memory allocation error
+ }
+
+ // Find the nearest aligned address
+ uintptr_t aligned_address = (raw_address + sizeof(void*) + alignment - 1) & ~(alignment - 1);
+
+ // Store the original address before the aligned address
+ ((void**)aligned_address)[-1] = (void*)raw_address;
+
+ return (void*)aligned_address;
+}
+
+void aligned_free(void* aligned_ptr) {
+ // Restore the original address and release it
+ void* raw_address = ((void**)aligned_ptr)[-1];
+ vPortFree(raw_address);
+}
+
+static void menuTask(void *pvParameters) PRIVILEGED_FUNCTION
+{
+ /* Define a buffer that is large enough to hold the generated table. In most
+ * cases the buffer will be too large to allocate on the stack, hence in this
+ * example it is declared static. */
+ ( void ) pvParameters;
+
+ static char cBuffer[BUFFER_SIZE];
+ extern uint32_t __unprivileged_data_section_start__[];
+ extern uint32_t __unprivileged_data_section_end__[];
+ TaskHandle_t xHandle_TaskROAccess = NULL, xHandle_TaskRWAccess = NULL, xHandle_ReceiveTask = NULL, xHandle_SendTask = NULL;
+
+ static TaskParameters_t xROAccessTaskParameters =
+ {
+ .pvTaskCode = prvROAccessTask,
+ .pcName = "ROAccess",
+ .usStackDepth = 128, //configMINIMAL_STACK_SIZE,
+ .pvParameters = NULL,
+ .uxPriority = mainQUEUE_SEND_TASK_PRIORITY,
+ .puxStackBuffer = NULL,
+ // .puxStackBuffer = xROAccessTaskStack,
+ };
+
+ static TaskParameters_t xRWAccessTaskParameters =
+ {
+ .pvTaskCode = prvRWAccessTask,
+ .pcName = "RWAccess",
+ .usStackDepth = 128, //configMINIMAL_STACK_SIZE,
+ .pvParameters = NULL,
+ .uxPriority = mainQUEUE_SEND_TASK_PRIORITY,
+ .puxStackBuffer = NULL,
+ // .puxStackBuffer = xRWAccessTaskStack,
+ };
+ static TaskParameters_t xTaskRXDefinition =
+ {
+ .pvTaskCode = prvQueueReceiveTask,
+ .pcName = "Rx",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = NULL,
+ .uxPriority = mainQUEUE_RECEIVE_TASK_PRIORITY - 1 ,
+ .puxStackBuffer = NULL,
+ };
+ static TaskParameters_t xTaskTXDefinition =
+ {
+ .pvTaskCode = prvQueueSendTask,
+ .pcName = "Tx",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = NULL,
+ .uxPriority = mainQUEUE_SEND_TASK_PRIORITY,
+ .puxStackBuffer = NULL,
+ };
+
+
+
+ (void)pvParameters;
+ int32_t lResult;
+ extern uint32_t __unprivileged_data_section_start__[];
+ extern uint32_t __unprivileged_data_section_end__[];
+ extern uint32_t __tcm_code_start__[];
+ extern uint32_t __tcm_code_end__[];
+ extern uint32_t __tcm_data_end__[];
+ extern uint32_t __tcm_data_start__[];
+ extern uint32_t __ram_data_start__[];
+
+ extern uint32_t privilege_status;
+
+ int ch;
+ do
+ {
+ portDISABLE_INTERRUPTS();
+ printf("\n+- Menu -----------------------------------------------------+\r\n");
+#ifdef CONFIG_APPS_HELLO_WORLD
+ printf("| [1] - Run 2 unprvl apps & demo interaction between them |\r\n");
+ printf("| [2] - Delete 2 unprvl apps |\r\n");
+#endif
+#ifdef CONFIG_APPS_HOTP
+ printf("| [3] - Run HOTP (Ported from OP-TEE, user TA) |\r\n");
+#endif
+ printf("| [4] - Get FreeRTOS Task List |\r\n");
+#ifdef CONFIG_APPS_TEST
+ printf("| [5] - Run Test Suite for GP TEE Client & Internal API |\r\n");
+#endif
+#ifdef CONFIG_APPS_HW_SECURITY_EXCEPTION_EXAMPLE
+ printf("| [6] - Run H/W Security exception example (from non-secure) |\r\n");
+ printf("| [7] - Run H/W Security exception example (from secure) |\r\n");
+#endif
+#ifdef CONFIG_APPS_SPY
+ printf("| [8] - Run test & spy (trying to get protected data) unprvl |\r\n");
+ printf("| [9] - Delete test & spy unprvl apps |\r\n");
+#endif
+ printf("+------------------------------------------------------------+\r\n");
+ portENABLE_INTERRUPTS();
+ while (1) {
+ ch = bflb_uart_getchar(uart0);
+ if (ch == -1) {
+ // taskYIELD();
+ // vTaskDelay(mainQUEUE_TICK_COUNT_FOR_1S);
+ } else break;
+ }
+ printf("\n[%c]\r\n", (char) ch);
+
+ switch (ch) {
+#ifdef CONFIG_APPS_HELLO_WORLD
+ case '1':
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+ if( xQueue != NULL )
+ {
+ /*
+ * Prepare xRegions for Receive Task
+ */
+ memset(&xTaskRXDefinition.xRegions, 0, sizeof(xTaskRXDefinition.xRegions));
+
+ // authorize access to data and bss
+ // Low address
+ // printf("xTaskRXDefinition.xRegions[0].pvBaseAddress = %p\r\n", xTaskRXDefinition.xRegions[0].pvBaseAddress);
+ // High address
+
+ xTaskRXDefinition.xRegions[0].ulLengthInBytes = 0x10000;
+ xTaskRXDefinition.xRegions[0].ulParameters = ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) 0xE0000000UL,
+ (size_t *) &xTaskRXDefinition.xRegions[0].pvBaseAddress,
+ xTaskRXDefinition.xRegions[0].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[0] = %d\r\n",lResult);
+
+ xTaskRXDefinition.xRegions[1].ulLengthInBytes = 8192UL;
+ xTaskRXDefinition.xRegions[1].ulParameters = ((portPMP_REGION_READ_ONLY) |
+ (portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_EXECUTE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) 0x62020000UL,
+ (size_t *) &xTaskRXDefinition.xRegions[1].pvBaseAddress,
+ xTaskRXDefinition.xRegions[1].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[1] = %d\r\n",lResult);
+
+ xTaskRXDefinition.xRegions[2].ulLengthInBytes = 0x10000;
+ xTaskRXDefinition.xRegions[2].ulParameters = ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) __ram_data_start__,
+ (size_t *) &xTaskRXDefinition.xRegions[2].pvBaseAddress,
+ xTaskRXDefinition.xRegions[2].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[2] = %d\r\n",lResult);
+
+
+ // allocate stack (It will take 2 PMP Slot - So it is not needed to put align the StackBuffer)
+ // xTaskRXDefinition.puxStackBuffer = ( StackType_t * ) pvPortMalloc( xTaskRXDefinition.usStackDepth * sizeof( StackType_t ) * 2);
+ xTaskRXDefinition.puxStackBuffer = ( StackType_t * )aligned_malloc(xTaskRXDefinition.usStackDepth * sizeof( StackType_t ),128);
+ // xTaskRXDefinition.puxStackBuffer = xReceiveTaskStack;
+ // portDISABLE_INTERRUPTS();
+ // printf("xTaskRXDefinition.puxStackBuffer = %p\r\n", xTaskRXDefinition.puxStackBuffer);
+ // portENABLE_INTERRUPTS();
+ xTaskCreateRestricted( &xTaskRXDefinition,
+ &xHandle_ReceiveTask);
+
+ /*
+ * Prepare xRegions for Send Task
+ */
+ memset(&xTaskTXDefinition.xRegions, 0, sizeof(xTaskTXDefinition.xRegions));
+
+ xTaskTXDefinition.xRegions[2].ulLengthInBytes = 0x10000;
+ xTaskTXDefinition.xRegions[2].ulParameters = ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) __ram_data_start__,
+ (size_t *) &xTaskTXDefinition.xRegions[2].pvBaseAddress,
+ xTaskTXDefinition.xRegions[2].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[2] = %d\r\n",lResult);
+
+ // authorize access to data and bss
+
+ // High address
+
+ // allocate stack (It will take 2 PMP Slot - So it is not needed to put align the StackBuffer)
+ // xTaskTXDefinition.puxStackBuffer = ( StackType_t * ) pvPortMalloc( xTaskTXDefinition.usStackDepth * sizeof( StackType_t ) );
+ xTaskTXDefinition.puxStackBuffer = ( StackType_t * )aligned_malloc(xTaskTXDefinition.usStackDepth * sizeof( StackType_t ),128);
+
+ // printf("xTaskTXDefinition.puxStackBuffer = %p\r\n", xTaskTXDefinition.puxStackBuffer);
+
+ xTaskCreateRestricted( &xTaskTXDefinition,
+ &xHandle_SendTask);
+
+ }
+
+ break;
+ case '2':
+ if (xHandle_ReceiveTask != NULL)
+ vTaskDelete(xHandle_ReceiveTask);
+ if (xHandle_SendTask != NULL)
+ vTaskDelete(xHandle_SendTask);
+ if (xTaskRXDefinition.puxStackBuffer != NULL)
+ vPortFree(xTaskRXDefinition.puxStackBuffer);
+ if (xTaskTXDefinition.puxStackBuffer != NULL)
+ vPortFree(xTaskTXDefinition.puxStackBuffer);
+ break;
+#endif
+ case '4':
+ /* Obtain the current tick count. */
+ printf("\nAuto-reload timer callback executing = %d\r\n", xTaskGetTickCount());
+
+ /* Pass the buffer into vTaskList() to generate the table of information. */
+ vTaskList(cBuffer);
+ portDISABLE_INTERRUPTS();
+ printf("%s\n", cBuffer);
+ portENABLE_INTERRUPTS();
+ break;
+#ifdef CONFIG_APPS_SPY
+ case '8':
+ /*
+ * Prepare xRegions for xROAccess Task
+ */
+ memset(&xROAccessTaskParameters.xRegions, 0, sizeof(xROAccessTaskParameters.xRegions));
+
+ // authorize access to data and bss
+ // Low address
+
+ xROAccessTaskParameters.xRegions[0].ulLengthInBytes = 0x10000;
+ xROAccessTaskParameters.xRegions[0].ulParameters = ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) 0xE0000000UL,
+ (size_t *) &xROAccessTaskParameters.xRegions[0].pvBaseAddress,
+ xROAccessTaskParameters.xRegions[0].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[0] = %d\r\n",lResult);
+
+
+ xROAccessTaskParameters.xRegions[1].ulLengthInBytes = 8192UL;
+ xROAccessTaskParameters.xRegions[1].ulParameters = ((portPMP_REGION_READ_ONLY) |
+ (portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_EXECUTE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) 0x62020000UL,
+ (size_t *) &xROAccessTaskParameters.xRegions[1].pvBaseAddress,
+ xROAccessTaskParameters.xRegions[1].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[1] = %d\r\n",lResult);
+
+ xROAccessTaskParameters.xRegions[2].ulLengthInBytes = 0x10000;
+ xROAccessTaskParameters.xRegions[2].ulParameters = ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) __ram_data_start__,
+ (size_t *) &xROAccessTaskParameters.xRegions[2].pvBaseAddress,
+ xROAccessTaskParameters.xRegions[2].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[2] = %d\r\n",lResult);
+
+ // xROAccessTaskParameters.puxStackBuffer = ( StackType_t * ) pvPortMalloc( xROAccessTaskParameters.usStackDepth * sizeof( StackType_t ) );
+ xROAccessTaskParameters.puxStackBuffer = ( StackType_t * )aligned_malloc(xROAccessTaskParameters.usStackDepth * sizeof( StackType_t ),128);
+ // xROAccessTaskParameters.puxStackBuffer = xROAccessTaskStack;
+ // printf("xROAccessTaskParameters.puxStackBuffer = %p\r\n", xROAccessTaskParameters.puxStackBuffer);
+
+
+ xTaskCreateRestricted( &xROAccessTaskParameters,
+ &xHandle_TaskROAccess);
+
+ /*
+ * Prepare xRegions for xRWAccess Task
+ */
+ memset(&xRWAccessTaskParameters.xRegions, 0, sizeof(xRWAccessTaskParameters.xRegions));
+
+ // authorize access to data and bss
+ // Low address
+
+ xRWAccessTaskParameters.xRegions[0].ulLengthInBytes = 0x10000;
+ xRWAccessTaskParameters.xRegions[0].ulParameters = ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) 0xE0000000UL,
+ (size_t *) &xRWAccessTaskParameters.xRegions[0].pvBaseAddress,
+ xRWAccessTaskParameters.xRegions[0].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[0] = %d\r\n",lResult);
+
+
+ xRWAccessTaskParameters.xRegions[1].ulLengthInBytes = 8192UL;
+ xRWAccessTaskParameters.xRegions[1].ulParameters = ((portPMP_REGION_READ_ONLY) |
+ (portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_EXECUTE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) 0x62020000UL,
+ (size_t *) &xRWAccessTaskParameters.xRegions[1].pvBaseAddress,
+ xRWAccessTaskParameters.xRegions[1].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[1] = %d\r\n",lResult);
+
+ xRWAccessTaskParameters.xRegions[2].ulLengthInBytes = 0x10000;
+ xRWAccessTaskParameters.xRegions[2].ulParameters = ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+
+ lResult = napot_addr_modifier ( xPmpInfo.granularity,
+ (size_t) __ram_data_start__,
+ (size_t *) &xRWAccessTaskParameters.xRegions[2].pvBaseAddress,
+ xRWAccessTaskParameters.xRegions[2].ulLengthInBytes);
+ if(lResult)
+ printf("lResult R[2] = %d\r\n",lResult);
+
+ // printf("xROAccessTaskParameters.xRegions[0].ulLengthInBytes = %d\r\n", xROAccessTaskParameters.xRegions[0].ulLengthInBytes);
+
+ // xRWAccessTaskParameters.puxStackBuffer = ( StackType_t * ) pvPortMalloc( xRWAccessTaskParameters.usStackDepth * sizeof( StackType_t ) );
+ xRWAccessTaskParameters.puxStackBuffer = ( StackType_t * )aligned_malloc(xRWAccessTaskParameters.usStackDepth * sizeof( StackType_t ),128);
+ // xRWAccessTaskParameters.puxStackBuffer = xRWAccessTaskStack;
+ // printf("xRWAccessTaskParameters.puxStackBuffer = %p\r\n", xRWAccessTaskParameters.puxStackBuffer);
+
+ xTaskCreateRestricted( &xRWAccessTaskParameters,
+ &xHandle_TaskRWAccess);
+
+ // spyAppTask();
+ break;
+ case '9':
+ if (xHandle_TaskROAccess != NULL)
+ vTaskDelete(xHandle_TaskROAccess);
+ if (xHandle_TaskRWAccess != NULL)
+ vTaskDelete(xHandle_TaskRWAccess);
+ if (xROAccessTaskParameters.puxStackBuffer != NULL)
+ vPortFree(xROAccessTaskParameters.puxStackBuffer);
+ if (xRWAccessTaskParameters.puxStackBuffer != NULL)
+ vPortFree(xRWAccessTaskParameters.puxStackBuffer);
+ break;
+#endif
+ default:
+ break;
+ }
+ taskYIELD();
+ vTaskDelay(mainQUEUE_TICK_COUNT_FOR_1S);
+
+ } while (1);
+}
+
+
+static void ledBlinkTask( void *pvParameters ) PRIVILEGED_FUNCTION
+{
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ struct bflb_device_s *gpio; //make instance of GPIO
+
+ //Get gpio device handle, i.e.) define IC pin here where IC's GPIO = 26, pin silkscreen = 13
+ //this is the GPIO device index that is referenced from 0, make sure to check the schematic
+ gpio = bflb_device_get_by_name("gpio");
+
+ //Set as gpio as output
+ bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_0);
+
+ //Turn ON pin
+ bflb_gpio_set(gpio, GPIO_PIN_26);
+
+ if (portIS_PRIVILEGED() == 1) {
+ printf("ledBlinkTask task is running in priveleged mode\r\n");
+ } else {
+ printf("ledBlinkTask task is running in unpriveleged mode\r\n");
+ }
+
+
+ for( ;; )
+ {
+ vTaskDelay(mainQUEUE_TICK_COUNT_FOR_1S);
+ bflb_gpio_reset(gpio, GPIO_PIN_26);
+ printf("[ledBlinkTask] Led OFF\r\n");
+ vTaskDelay(mainQUEUE_TICK_COUNT_FOR_1S);
+ bflb_gpio_set(gpio, GPIO_PIN_26);
+ printf("[ledBlinkTask] Led ON\r\n");
+ }
+}
+
+/*-----------------------------------------------------------*/
+int main( void )
+{
+ // TaskHandle_t xHandle_ReceiveTask, xHandle_SendTask, xHandle_TaskListTasks, xHandle_TaskROAccess, xHandle_TaskRWAccess;
+
+ // static StackType_t xTaskListTasksShowStack[ configMINIMAL_STACK_SIZE * 3] __attribute__( ( aligned( 32 ) ) );
+ // static StackType_t xSendTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 128 ) ) );
+ // static StackType_t xReceiveTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 128 ) ) );
+ // static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+ // static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+
+
+ // const char * const pcMessage = "FreeRTOS-TEE Demo start\r\n";
+ // const char * const pcMessageEnd = "FreeRTOS-TEE Demo end\r\n";
+ const char * const pcMessageEndError = "FreeRTOS-TEE Demo end - Error no enough PMP entry\r\n";
+ const char * const pcMessageGranularityError = "FreeRTOS-TEE Demo end - Error platform granularity no supported\r\n";
+
+ extern uint32_t __unprivileged_data_section_start__[];
+ extern uint32_t __unprivileged_data_section_end__[];
+ extern uint32_t __unprivileged_section_start__[];
+ extern uint32_t __unprivileged_section_end__[];
+
+ // extern uint32_t __heap_start[];
+ // extern uint32_t __heap_end[];
+ //extern unsigned long __privileged_data_start__[];
+ //extern unsigned long __privileged_data_end__[];
+ extern unsigned long __privileged_functions_start__[];
+ extern unsigned long __privileged_functions_end__[];
+ // extern unsigned long metal_segment_stack_begin[];
+ // extern unsigned long metal_segment_stack_end[];
+ volatile unsigned long *pul;
+
+ prvSetupHardware();
+ // __asm volatile ( "csrc mstatus, 0x8" );
+ printf("\n\n\t-= mTower v" VERSION " =- " __DATE__ " " __TIME__"\r\n\n");
+ // printf("ucSharedMemory = %p\r\n", ucSharedMemory);
+ __enable_irq();
+
+ // printf("__ricsv_xlen = %d\r\n", __riscv_xlen);
+
+ // pul = __unprivileged_data_section_start__;
+ // printf("__unprivileged_data_section_start__ = %p\r\n", pul);
+
+ // pul = __unprivileged_data_section_end__;
+ // printf("__unprivileged_data_section_end__ = %p\r\n", pul);
+
+ extern uint32_t __text_code_start__[];
+ extern uint32_t __text_code_end__[];
+ extern uint32_t __tcm_code_start__[];
+ extern uint32_t __tcm_code_end__[];
+
+ extern uint32_t __fsymtab_start[];
+ extern uint32_t __fsymtab_end[];
+ extern uint32_t __vsymtab_start[];
+ extern uint32_t __vsymtab_end[];
+ extern uint32_t __usbh_class_info_end__[];
+
+ // printf("__fsymtab_start = %p\r\n", &__fsymtab_start);
+ // printf("__fsymtab_end = %p\r\n", &__fsymtab_end);
+ // printf("__vsymtab_start = %p\r\n", &__vsymtab_start);
+ // printf("__vsymtab_end = %p\r\n", &__vsymtab_end);
+
+ // printf("__usbh_class_info_end__ = %p\r\n", &__usbh_class_info_end__);
+ // pul = __unprivileged_section_start__;
+ // printf("__unprivileged_section_start__ = %p\r\n", pul);
+
+ // pul = __unprivileged_section_end__;
+ // printf("__unprivileged_section_end__ = %p\r\n", pul);
+
+ // pul = __privileged_functions_start__;
+ // printf("__privileged_functions_start__ = %p\r\n", pul);
+
+ // pul = __privileged_functions_end__;
+ // printf("__privileged_functions_end__ = %p\r\n", pul);
+
+ // printf("__text_code_start__ = %p\r\n", &__text_code_start__);
+ extern uint32_t __tcm_data_end__[];
+ extern uint32_t __tcm_data_start__[];
+ // printf("__text_code_end__ = %p\r\n", __text_code_end__);
+ // printf("__tcm_code_start__ = %p\r\n", __tcm_code_start__);
+ // printf("__tcm_code_end__ = %p\r\n", __tcm_code_end__);
+ // printf("__tcm_data_start__ = %p\r\n", __tcm_data_start__);
+ // printf("__tcm_data_end__ = %p\r\n", __tcm_data_end__);
+ // printf("uart0 = %p\r\n", uart0);
+
+ // printf("prvQueueReceiveTask = %p\r\n", prvQueueReceiveTask);
+ // printf("MPU_vTaskDelay = %p\r\n", vTaskDelay);
+ // printf("xIsPrivileged = %p\r\n", xIsPrivileged);
+ // printf("bflb_uart_putchar = %p\r\n", bflb_uart_putchar);
+ // bflb_uart_putchar
+
+ // pul = __privileged_data_start__;
+ // printf("__privileged_data_start__ = %p\r\n", pul);
+
+ // pul = __privileged_data_end__;
+ // printf("__privileged_data_end__ = %p\r\n", pul);
+
+ // pul = metal_segment_stack_begin;
+ // printf("metal_segment_stack_begin = %p\r\n", pul);
+
+ // pul = metal_segment_stack_end;
+ // printf("metal_segment_stack_end = %p\r\n", pul);
+
+ // pul = __heap_start;
+ // printf("__heap_start = %p\r\n", pul);
+
+ // pul = __heap_end;
+ // printf("__heap_end = %p\r\n", pul);
+
+ // printf("sizeof( StackType_t ) = %d\r\n", sizeof( StackType_t ));
+ // printf("portTOTAL_NUM_CFG_REG = %d\r\n", portTOTAL_NUM_CFG_REG);
+ // printf("\r\nBefore hello\r\n");
+
+ /*
+ * Call xPortFreeRTOSInit in order to set xISRTopStack
+ */
+ // printf("xISRStack = %p\r\n",(StackType_t)&( xISRStack[ ( (configMINIMAL_STACK_SIZE - 1) & ~portBYTE_ALIGNMENT_MASK ) ] ));
+ // printf("xISRStack = %p\r\n",&( xISRStack ));
+ // printf("xISRStack = %p\r\n",(StackType_t)&( xISRStack[ ( (configMINIMAL_STACK_SIZE - 1) & ~portBYTE_ALIGNMENT_MASK ) ] ));
+ // __enable_irq();
+
+ if ( 0 != xPortFreeRTOSInit((StackType_t)&( xISRStack[ ( (configMINIMAL_STACK_SIZE - 1) & ~portBYTE_ALIGNMENT_MASK ) ] ))) {
+ printf("ERROR");
+ while(1);
+ // _exit(-1);
+ }
+
+ BaseType_t xReturned;
+ TaskHandle_t xHandle = NULL;
+
+ // xReturned = xTaskCreate(
+ // vTaskCode, /* Function that implements the task. */
+ // "PRVLGD", /* Text name for the task. */
+ // 512, /* Stack size in words, not bytes. */
+ // NULL, //( void * ) 1, /* Parameter passed into the task. */
+ // mainQUEUE_SEND_TASK_PRIORITY | portPRIVILEGE_BIT,/* Priority at which the task is created. */
+ // &xHandle ); /* Used to pass out the created task's handle. */
+
+ xTaskCreate(menuTask, /* The function that implements the task. */
+ "menu", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
+ 768, /* The size of the stack to allocate to the task. */
+ (void *)NULL, /* The parameter passed to the task - just to check the functionality. */
+ mainQUEUE_SEND_TASK_PRIORITY | portPRIVILEGE_BIT, /* The priority assigned to the task. */
+ NULL);
+ __enable_irq();
+
+ xTaskCreate(ledBlinkTask, /* The function that implements the task. */
+ "ledBlink", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
+ 128, /* The size of the stack to allocate to the task. */
+ (void *)NULL, /* The parameter passed to the task - just to check the functionality. */
+ mainQUEUE_SEND_TASK_PRIORITY | portPRIVILEGE_BIT, /* The priority assigned to the task. */
+ NULL);
+ __enable_irq();
+
+#if( portUSING_MPU_WRAPPERS == 1 )
+ if (xPmpInfo.nb_pmp < 8)
+ {
+ printf("%s", pcMessageEndError);
+ _exit(0);
+ // } else if (xPmpInfo.granularity > 4) {
+ } else if (xPmpInfo.granularity > 128) {
+ /*
+ * platfrom granularity > 4 bytes is not supported yet, some
+ * modifications are needed on FreeRTOS port to do so.
+ */
+ printf("%s", pcMessageGranularityError);
+ _exit(0);
+ }
+ // printf("xPmpInfo.nb_pmp = %d\r\n", xPmpInfo.nb_pmp);
+ // printf("xPmpInfo.granularity= %d\r\n", xPmpInfo.granularity);
+
+ if(0 == xPmpInfo.granularity)
+ {
+ init_pmp (&xPmpInfo);
+ }
+ __enable_irq();
+
+ /* Start the tasks and timer running. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was insufficient FreeRTOS heap memory available for the Idle and/or
+ timer tasks to be created.
+ or task have stoppped the Scheduler */
+
+ // vTaskDelete( xHandle_SendTask );
+ // vTaskDelete( xHandle_ReceiveTask );
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) */
+}
+
+/*-----------------------------------------------------------*/
+static __attribute__( ( section( ".unprivileged_section" ) ) ) void prvQueueSendTask( void *pvParameters )
+{
+ TickType_t xNextWakeTime;
+ BaseType_t xReturned;
+ unsigned long ulCounter = 0;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+ ( void ) xReturned;
+
+ printf("prvQueueSendTask task: ");
+ if (portIS_PRIVILEGED() == 1) {
+ printf("TX task is running in priveleged mode\r\n");
+ } else {
+ printf("Tx task is running in unpriveleged mode\r\n");
+ }
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ; ; )
+ {
+ printf("[ Tx ] : %d\r\n", ++ulCounter );
+
+ /* Place this task in the blocked state until it is time to run again. */
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_TICK_COUNT_FOR_1S);
+ // vTaskDelay( mainQUEUE_TICK_COUNT_FOR_1S * 500);
+
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ toggle the LED. 0 is used as the block time so the sending operation
+ will not block - it shouldn't need to block as the queue should always
+ be empty at this point in the code. */
+ xReturned = xQueueSend( xQueue, &ulCounter, 0U );
+ configASSERT( xReturned == pdPASS );
+ }
+
+ /**
+ * SiFive CI/CD need to have a exit(0) status to pass
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+ /* We run into user mode, so need to be machine mode before to call vTaskEndScheduler */
+ // xPortRaisePrivilege();
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) */
+ // vTaskEndScheduler();
+}
+/*-----------------------------------------------------------*/
+
+static __attribute__( ( section( ".unprivileged_section" ) ) ) void prvQueueReceiveTask( void *pvParameters )
+{
+ unsigned long ulReceivedValue;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ printf("prvQueueReceiveTask task: ");
+ if (portIS_PRIVILEGED() == 1) {
+ printf("RX task is running in priveleged mode\r\n");
+ } else {
+ printf("Rx task is running in unpriveleged mode\r\n");
+ }
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue, but
+ is it the expected value? If it is, toggle the LED. */
+
+ printf("[ Rx ] : %d\r\n", ulReceivedValue );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+ // const char * const pcWarningMsg = "At least one of LEDs is null.\r\n";
+ board_init();
+ uart0 = bflb_device_get_by_name("uart0");
+ bflb_uart_set_console(bflb_device_get_by_name("uart0"));
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((weak)) void vApplicationTickHook(void)
+{
+ //printf("vApplicationTickHook\r\n");
+}
+
+__attribute__((weak)) void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName)
+{
+ printf("vApplicationStackOverflowHook\r\n");
+
+ while (1)
+ ;
+}
+
+__attribute__((weak)) void vApplicationMallocFailedHook(void)
+{
+ const char * const pcErrorMsg = "ERROR malloc \r\n";
+ printf("vApplicationMallocFailedHook\r\n");
+ printf(pcErrorMsg);
+ while (1)
+ ;
+}
+
+__attribute__((weak)) void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize)
+{
+ /* If the buffers to be provided to the Idle task are declared inside this
+ function then they must be declared static - otherwise they will be allocated on
+ the stack and so not exists after this function exits. */
+ static StaticTask_t xIdleTaskTCB;
+ static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+ state will be stored. */
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+ /* Pass out the array that will be used as the Idle task's stack. */
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+ Note that, as the array is necessarily of type StackType_t,
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+
+/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+application must provide an implementation of vApplicationGetTimerTaskMemory()
+to provide the memory that is used by the Timer service task. */
+__attribute__((weak)) void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize)
+{
+ /* If the buffers to be provided to the Timer task are declared inside this
+ function then they must be declared static - otherwise they will be allocated on
+ the stack and so not exists after this function exits. */
+ static StaticTask_t xTimerTaskTCB;
+ static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer
+ task's state will be stored. */
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+ /* Pass out the array that will be used as the Timer task's stack. */
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+ Note that, as the array is necessarily of type StackType_t,
+ configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/printf.c b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/printf.c
new file mode 100644
index 00000000..059bbd16
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/printf.c
@@ -0,0 +1,923 @@
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+// 2014-2019, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on
+// embedded systems with a very limited resources. These routines are thread
+// safe and reentrant!
+// Use this instead of the bloated standard/newlib printf cause these use
+// malloc for printf (and may not be thread safe).
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#include
+#include
+
+#include "printf.h"
+
+
+// define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the
+// printf_config.h header file
+// default: undefined
+#ifdef PRINTF_INCLUDE_CONFIG_H
+#include "printf_config.h"
+#endif
+
+
+// 'ntoa' conversion buffer size, this must be big enough to hold one converted
+// numeric number including padded zeros (dynamically created on stack)
+// default: 32 byte
+#ifndef PRINTF_NTOA_BUFFER_SIZE
+#define PRINTF_NTOA_BUFFER_SIZE 32U
+#endif
+
+// 'ftoa' conversion buffer size, this must be big enough to hold one converted
+// float number including padded zeros (dynamically created on stack)
+// default: 32 byte
+#ifndef PRINTF_FTOA_BUFFER_SIZE
+#define PRINTF_FTOA_BUFFER_SIZE 32U
+#endif
+
+// support for the floating point type (%f)
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_FLOAT
+#define PRINTF_SUPPORT_FLOAT
+#endif
+
+// support for exponential floating point notation (%e/%g)
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL
+#define PRINTF_SUPPORT_EXPONENTIAL
+#endif
+
+// define the default floating point precision
+// default: 6 digits
+#ifndef PRINTF_DEFAULT_FLOAT_PRECISION
+#define PRINTF_DEFAULT_FLOAT_PRECISION 6U
+#endif
+
+// define the largest float suitable to print with %f
+// default: 1e9
+#ifndef PRINTF_MAX_FLOAT
+#define PRINTF_MAX_FLOAT 1e9
+#endif
+
+// support for the long long types (%llu or %p)
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG
+#define PRINTF_SUPPORT_LONG_LONG
+#endif
+
+// support for the ptrdiff_t type (%t)
+// ptrdiff_t is normally defined in as long or long long type
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T
+#define PRINTF_SUPPORT_PTRDIFF_T
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+
+// internal flag definitions
+#define FLAGS_ZEROPAD (1U << 0U)
+#define FLAGS_LEFT (1U << 1U)
+#define FLAGS_PLUS (1U << 2U)
+#define FLAGS_SPACE (1U << 3U)
+#define FLAGS_HASH (1U << 4U)
+#define FLAGS_UPPERCASE (1U << 5U)
+#define FLAGS_CHAR (1U << 6U)
+#define FLAGS_SHORT (1U << 7U)
+#define FLAGS_LONG (1U << 8U)
+#define FLAGS_LONG_LONG (1U << 9U)
+#define FLAGS_PRECISION (1U << 10U)
+#define FLAGS_ADAPT_EXP (1U << 11U)
+
+
+// import float.h for DBL_MAX
+#if defined(PRINTF_SUPPORT_FLOAT)
+#include
+#endif
+
+
+// output function type
+typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen);
+
+
+// wrapper (used as buffer) for output function type
+typedef struct {
+ void (*fct)(char character, void* arg);
+ void* arg;
+} out_fct_wrap_type;
+
+
+// internal buffer output
+static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen)
+{
+ if (idx < maxlen) {
+ ((char*)buffer)[idx] = character;
+ }
+}
+
+
+// internal null output
+static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen)
+{
+ (void)character; (void)buffer; (void)idx; (void)maxlen;
+}
+
+
+// internal _putchar wrapper
+static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen)
+{
+ (void)buffer; (void)idx; (void)maxlen;
+ if (character) {
+// #ifdef C_SECURE_CODE
+// volatile uint32_t* mytest = 0x50080000 + 0x84;
+// *mytest &= ~(1 << 5);
+// __putchar(character);
+// #else
+ _putchar(character);
+// #endif
+// #ifdef C_SECURE_CODE
+// *mytest |= (1 << 5);
+// #endif
+ }
+}
+
+
+// internal output function wrapper
+static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen)
+{
+ (void)idx; (void)maxlen;
+ if (character) {
+ // buffer is the output fct pointer
+ ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg);
+ }
+}
+
+
+// internal secure strlen
+// \return The length of the string (excluding the terminating 0) limited by 'maxsize'
+static inline unsigned int _strnlen_s(const char* str, size_t maxsize)
+{
+ const char* s;
+ for (s = str; *s && maxsize--; ++s);
+ return (unsigned int)(s - str);
+}
+
+
+// internal test if char is a digit (0-9)
+// \return true if char is a digit
+static inline bool _is_digit(char ch)
+{
+ return (ch >= '0') && (ch <= '9');
+}
+
+
+// internal ASCII string to unsigned int conversion
+static unsigned int _atoi(const char** str)
+{
+ unsigned int i = 0U;
+ while (_is_digit(**str)) {
+ i = i * 10U + (unsigned int)(*((*str)++) - '0');
+ }
+ return i;
+}
+
+
+// output the specified string in reverse, taking care of any zero-padding
+static size_t _out_rev(out_fct_type out, char* buffer, size_t idx, size_t maxlen, const char* buf, size_t len, unsigned int width, unsigned int flags)
+{
+ const size_t start_idx = idx;
+
+ // pad spaces up to given width
+ if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
+ for (size_t i = len; i < width; i++) {
+ out(' ', buffer, idx++, maxlen);
+ }
+ }
+
+ // reverse string
+ while (len) {
+ out(buf[--len], buffer, idx++, maxlen);
+ }
+
+ // append pad spaces up to given width
+ if (flags & FLAGS_LEFT) {
+ while (idx - start_idx < width) {
+ out(' ', buffer, idx++, maxlen);
+ }
+ }
+
+ return idx;
+}
+
+
+// internal itoa format
+static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+ // pad leading zeros
+ if (!(flags & FLAGS_LEFT)) {
+ if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {
+ width--;
+ }
+ while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+ buf[len++] = '0';
+ }
+ while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+ buf[len++] = '0';
+ }
+ }
+
+ // handle hash
+ if (flags & FLAGS_HASH) {
+ if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) {
+ len--;
+ if (len && (base == 16U)) {
+ len--;
+ }
+ }
+ if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+ buf[len++] = 'x';
+ }
+ else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+ buf[len++] = 'X';
+ }
+ else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+ buf[len++] = 'b';
+ }
+ if (len < PRINTF_NTOA_BUFFER_SIZE) {
+ buf[len++] = '0';
+ }
+ }
+
+ if (len < PRINTF_NTOA_BUFFER_SIZE) {
+ if (negative) {
+ buf[len++] = '-';
+ }
+ else if (flags & FLAGS_PLUS) {
+ buf[len++] = '+'; // ignore the space if the '+' exists
+ }
+ else if (flags & FLAGS_SPACE) {
+ buf[len++] = ' ';
+ }
+ }
+
+ return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);
+}
+
+
+// internal itoa for 'long' type
+static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+ char buf[PRINTF_NTOA_BUFFER_SIZE];
+ size_t len = 0U;
+
+ // no hash for 0 values
+ if (!value) {
+ flags &= ~FLAGS_HASH;
+ }
+
+ // write if precision != 0 and value is != 0
+ if (!(flags & FLAGS_PRECISION) || value) {
+ do {
+ const char digit = (char)(value % base);
+ buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
+ value /= base;
+ } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
+ }
+
+ return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
+}
+
+
+// internal itoa for 'long long' type
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+ char buf[PRINTF_NTOA_BUFFER_SIZE];
+ size_t len = 0U;
+
+ // no hash for 0 values
+ if (!value) {
+ flags &= ~FLAGS_HASH;
+ }
+
+ // write if precision != 0 and value is != 0
+ if (!(flags & FLAGS_PRECISION) || value) {
+ do {
+ const char digit = (char)(value % base);
+ buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
+ value /= base;
+ } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
+ }
+
+ return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
+}
+#endif // PRINTF_SUPPORT_LONG_LONG
+
+
+#if defined(PRINTF_SUPPORT_FLOAT)
+
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+// forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT
+static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags);
+#endif
+
+
+// internal ftoa for fixed decimal floating point
+static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags)
+{
+ char buf[PRINTF_FTOA_BUFFER_SIZE];
+ size_t len = 0U;
+ double diff = 0.0;
+
+ // powers of 10
+ static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 };
+
+ // test for special values
+ if (value != value)
+ return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags);
+ if (value < -DBL_MAX)
+ return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags);
+ if (value > DBL_MAX)
+ return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, width, flags);
+
+ // test for very large values
+ // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad
+ if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) {
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+ return _etoa(out, buffer, idx, maxlen, value, prec, width, flags);
+#else
+ return 0U;
+#endif
+ }
+
+ // test for negative
+ bool negative = false;
+ if (value < 0) {
+ negative = true;
+ value = 0 - value;
+ }
+
+ // set default precision, if not set explicitly
+ if (!(flags & FLAGS_PRECISION)) {
+ prec = PRINTF_DEFAULT_FLOAT_PRECISION;
+ }
+ // limit precision to 9, cause a prec >= 10 can lead to overflow errors
+ while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) {
+ buf[len++] = '0';
+ prec--;
+ }
+
+ int whole = (int)value;
+ double tmp = (value - whole) * pow10[prec];
+ unsigned long frac = (unsigned long)tmp;
+ diff = tmp - frac;
+
+ if (diff > 0.5) {
+ ++frac;
+ // handle rollover, e.g. case 0.99 with prec 1 is 1.0
+ if (frac >= pow10[prec]) {
+ frac = 0;
+ ++whole;
+ }
+ }
+ else if (diff < 0.5) {
+ }
+ else if ((frac == 0U) || (frac & 1U)) {
+ // if halfway, round up if odd OR if last digit is 0
+ ++frac;
+ }
+
+ if (prec == 0U) {
+ diff = value - (double)whole;
+ if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) {
+ // exactly 0.5 and ODD, then round up
+ // 1.5 -> 2, but 2.5 -> 2
+ ++whole;
+ }
+ }
+ else {
+ unsigned int count = prec;
+ // now do fractional part, as an unsigned number
+ while (len < PRINTF_FTOA_BUFFER_SIZE) {
+ --count;
+ buf[len++] = (char)(48U + (frac % 10U));
+ if (!(frac /= 10U)) {
+ break;
+ }
+ }
+ // add extra 0s
+ while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) {
+ buf[len++] = '0';
+ }
+ if (len < PRINTF_FTOA_BUFFER_SIZE) {
+ // add decimal
+ buf[len++] = '.';
+ }
+ }
+
+ // do whole part, number is reversed
+ while (len < PRINTF_FTOA_BUFFER_SIZE) {
+ buf[len++] = (char)(48 + (whole % 10));
+ if (!(whole /= 10)) {
+ break;
+ }
+ }
+
+ // pad leading zeros
+ if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) {
+ if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {
+ width--;
+ }
+ while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) {
+ buf[len++] = '0';
+ }
+ }
+
+ if (len < PRINTF_FTOA_BUFFER_SIZE) {
+ if (negative) {
+ buf[len++] = '-';
+ }
+ else if (flags & FLAGS_PLUS) {
+ buf[len++] = '+'; // ignore the space if the '+' exists
+ }
+ else if (flags & FLAGS_SPACE) {
+ buf[len++] = ' ';
+ }
+ }
+
+ return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);
+}
+
+
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse
+static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags)
+{
+ // check for NaN and special values
+ if ((value != value) || (value > DBL_MAX) || (value < -DBL_MAX)) {
+ return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags);
+ }
+
+ // determine the sign
+ const bool negative = value < 0;
+ if (negative) {
+ value = -value;
+ }
+
+ // default precision
+ if (!(flags & FLAGS_PRECISION)) {
+ prec = PRINTF_DEFAULT_FLOAT_PRECISION;
+ }
+
+ // determine the decimal exponent
+ // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c)
+ union {
+ uint64_t U;
+ double F;
+ } conv;
+
+ conv.F = value;
+ int exp2 = (int)((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2
+ conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2)
+ // now approximate log10 from the log2 integer part and an expansion of ln around 1.5
+ int expval = (int)(0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168);
+ // now we want to compute 10^expval but we want to be sure it won't overflow
+ exp2 = (int)(expval * 3.321928094887362 + 0.5);
+ const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453;
+ const double z2 = z * z;
+ conv.U = (uint64_t)(exp2 + 1023) << 52U;
+ // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex
+ conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14)))));
+ // correct for rounding errors
+ if (value < conv.F) {
+ expval--;
+ conv.F /= 10;
+ }
+
+ // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters
+ unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U;
+
+ // in "%g" mode, "prec" is the number of *significant figures* not decimals
+ if (flags & FLAGS_ADAPT_EXP) {
+ // do we want to fall-back to "%f" mode?
+ if ((value >= 1e-4) && (value < 1e6)) {
+ if ((int)prec > expval) {
+ prec = (unsigned)((int)prec - expval - 1);
+ }
+ else {
+ prec = 0;
+ }
+ flags |= FLAGS_PRECISION; // make sure _ftoa respects precision
+ // no characters in exponent
+ minwidth = 0U;
+ expval = 0;
+ }
+ else {
+ // we use one sigfig for the whole part
+ if ((prec > 0) && (flags & FLAGS_PRECISION)) {
+ --prec;
+ }
+ }
+ }
+
+ // will everything fit?
+ unsigned int fwidth = width;
+ if (width > minwidth) {
+ // we didn't fall-back so subtract the characters required for the exponent
+ fwidth -= minwidth;
+ } else {
+ // not enough characters, so go back to default sizing
+ fwidth = 0U;
+ }
+ if ((flags & FLAGS_LEFT) && minwidth) {
+ // if we're padding on the right, DON'T pad the floating part
+ fwidth = 0U;
+ }
+
+ // rescale the float value
+ if (expval) {
+ value /= conv.F;
+ }
+
+ // output the floating part
+ const size_t start_idx = idx;
+ idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP);
+
+ // output the exponent part
+ if (minwidth) {
+ // output the exponential symbol
+ out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen);
+ // output the exponent value
+ idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth-1, FLAGS_ZEROPAD | FLAGS_PLUS);
+ // might need to right-pad spaces
+ if (flags & FLAGS_LEFT) {
+ while (idx - start_idx < width) out(' ', buffer, idx++, maxlen);
+ }
+ }
+ return idx;
+}
+#endif // PRINTF_SUPPORT_EXPONENTIAL
+#endif // PRINTF_SUPPORT_FLOAT
+
+
+// internal vsnprintf
+static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va)
+{
+ unsigned int flags, width, precision, n;
+ size_t idx = 0U;
+
+ if (!buffer) {
+ // use null output function
+ out = _out_null;
+ }
+
+ while (*format)
+ {
+ // format specifier? %[flags][width][.precision][length]
+ if (*format != '%') {
+ // no
+ out(*format, buffer, idx++, maxlen);
+ format++;
+ continue;
+ }
+ else {
+ // yes, evaluate it
+ format++;
+ }
+
+ // evaluate flags
+ flags = 0U;
+ do {
+ switch (*format) {
+ case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break;
+ case '-': flags |= FLAGS_LEFT; format++; n = 1U; break;
+ case '+': flags |= FLAGS_PLUS; format++; n = 1U; break;
+ case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break;
+ case '#': flags |= FLAGS_HASH; format++; n = 1U; break;
+ default : n = 0U; break;
+ }
+ } while (n);
+
+ // evaluate width field
+ width = 0U;
+ if (_is_digit(*format)) {
+ width = _atoi(&format);
+ }
+ else if (*format == '*') {
+ const int w = va_arg(va, int);
+ if (w < 0) {
+ flags |= FLAGS_LEFT; // reverse padding
+ width = (unsigned int)-w;
+ }
+ else {
+ width = (unsigned int)w;
+ }
+ format++;
+ }
+
+ // evaluate precision field
+ precision = 0U;
+ if (*format == '.') {
+ flags |= FLAGS_PRECISION;
+ format++;
+ if (_is_digit(*format)) {
+ precision = _atoi(&format);
+ }
+ else if (*format == '*') {
+ const int prec = (int)va_arg(va, int);
+ precision = prec > 0 ? (unsigned int)prec : 0U;
+ format++;
+ }
+ }
+
+ // evaluate length field
+ switch (*format) {
+ case 'l' :
+ flags |= FLAGS_LONG;
+ format++;
+ if (*format == 'l') {
+ flags |= FLAGS_LONG_LONG;
+ format++;
+ }
+ break;
+ case 'h' :
+ flags |= FLAGS_SHORT;
+ format++;
+ if (*format == 'h') {
+ flags |= FLAGS_CHAR;
+ format++;
+ }
+ break;
+#if defined(PRINTF_SUPPORT_PTRDIFF_T)
+ case 't' :
+ flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+ format++;
+ break;
+#endif
+ case 'j' :
+ flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+ format++;
+ break;
+ case 'z' :
+ flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+ format++;
+ break;
+ default :
+ break;
+ }
+
+ // evaluate specifier
+ switch (*format) {
+ case 'd' :
+ case 'i' :
+ case 'u' :
+ case 'x' :
+ case 'X' :
+ case 'o' :
+ case 'b' : {
+ // set the base
+ unsigned int base;
+ if (*format == 'x' || *format == 'X') {
+ base = 16U;
+ }
+ else if (*format == 'o') {
+ base = 8U;
+ }
+ else if (*format == 'b') {
+ base = 2U;
+ }
+ else {
+ base = 10U;
+ flags &= ~FLAGS_HASH; // no hash for dec format
+ }
+ // uppercase
+ if (*format == 'X') {
+ flags |= FLAGS_UPPERCASE;
+ }
+
+ // no plus or space flag for u, x, X, o, b
+ if ((*format != 'i') && (*format != 'd')) {
+ flags &= ~(FLAGS_PLUS | FLAGS_SPACE);
+ }
+
+ // ignore '0' flag when precision is given
+ if (flags & FLAGS_PRECISION) {
+ flags &= ~FLAGS_ZEROPAD;
+ }
+
+ // convert the integer
+ if ((*format == 'i') || (*format == 'd')) {
+ // signed
+ if (flags & FLAGS_LONG_LONG) {
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+ const long long value = va_arg(va, long long);
+ idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+#endif
+ }
+ else if (flags & FLAGS_LONG) {
+ const long value = va_arg(va, long);
+ idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+ }
+ else {
+ const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int);
+ idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+ }
+ }
+ else {
+ // unsigned
+ if (flags & FLAGS_LONG_LONG) {
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+ idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags);
+#endif
+ }
+ else if (flags & FLAGS_LONG) {
+ idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags);
+ }
+ else {
+ const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int);
+ idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags);
+ }
+ }
+ format++;
+ break;
+ }
+#if defined(PRINTF_SUPPORT_FLOAT)
+ case 'f' :
+ case 'F' :
+ if (*format == 'F') flags |= FLAGS_UPPERCASE;
+ idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
+ format++;
+ break;
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+ case 'e':
+ case 'E':
+ case 'g':
+ case 'G':
+ if ((*format == 'g')||(*format == 'G')) flags |= FLAGS_ADAPT_EXP;
+ if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE;
+ idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
+ format++;
+ break;
+#endif // PRINTF_SUPPORT_EXPONENTIAL
+#endif // PRINTF_SUPPORT_FLOAT
+ case 'c' : {
+ unsigned int l = 1U;
+ // pre padding
+ if (!(flags & FLAGS_LEFT)) {
+ while (l++ < width) {
+ out(' ', buffer, idx++, maxlen);
+ }
+ }
+ // char output
+ out((char)va_arg(va, int), buffer, idx++, maxlen);
+ // post padding
+ if (flags & FLAGS_LEFT) {
+ while (l++ < width) {
+ out(' ', buffer, idx++, maxlen);
+ }
+ }
+ format++;
+ break;
+ }
+
+ case 's' : {
+ const char* p = va_arg(va, char*);
+ unsigned int l = _strnlen_s(p, precision ? precision : (size_t)-1);
+ // pre padding
+ if (flags & FLAGS_PRECISION) {
+ l = (l < precision ? l : precision);
+ }
+ if (!(flags & FLAGS_LEFT)) {
+ while (l++ < width) {
+ out(' ', buffer, idx++, maxlen);
+ }
+ }
+ // string output
+ while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) {
+ out(*(p++), buffer, idx++, maxlen);
+ }
+ // post padding
+ if (flags & FLAGS_LEFT) {
+ while (l++ < width) {
+ out(' ', buffer, idx++, maxlen);
+ }
+ }
+ format++;
+ break;
+ }
+
+ case 'p' : {
+ width = sizeof(void*) * 2U;
+ flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE;
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+ const bool is_ll = sizeof(uintptr_t) == sizeof(long long);
+ if (is_ll) {
+ idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags);
+ }
+ else {
+#endif
+ idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags);
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+ }
+#endif
+ format++;
+ break;
+ }
+
+ case '%' :
+ out('%', buffer, idx++, maxlen);
+ format++;
+ break;
+
+ default :
+ out(*format, buffer, idx++, maxlen);
+ format++;
+ break;
+ }
+ }
+
+ // termination
+ out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen);
+
+ // return written chars without terminating \0
+ return (int)idx;
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+
+int printf_(const char* format, ...)
+{
+ va_list va;
+ va_start(va, format);
+ char buffer[1];
+ const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va);
+ va_end(va);
+ return ret;
+}
+
+
+int sprintf_(char* buffer, const char* format, ...)
+{
+ va_list va;
+ va_start(va, format);
+ const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va);
+ va_end(va);
+ return ret;
+}
+
+
+int snprintf_(char* buffer, size_t count, const char* format, ...)
+{
+ va_list va;
+ va_start(va, format);
+ const int ret = _vsnprintf(_out_buffer, buffer, count, format, va);
+ va_end(va);
+ return ret;
+}
+
+
+int vprintf_(const char* format, va_list va)
+{
+ char buffer[1];
+ return _vsnprintf(_out_char, buffer, (size_t)-1, format, va);
+}
+
+
+int vsnprintf_(char* buffer, size_t count, const char* format, va_list va)
+{
+ return _vsnprintf(_out_buffer, buffer, count, format, va);
+}
+
+
+int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...)
+{
+ va_list va;
+ va_start(va, format);
+ const out_fct_wrap_type out_fct_wrap = { out, arg };
+ const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va);
+ va_end(va);
+ return ret;
+}
diff --git a/arch/riscv32/bl808/src/pine64_ox64/nonsecure/printf.h b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/printf.h
new file mode 100644
index 00000000..1e3e2794
--- /dev/null
+++ b/arch/riscv32/bl808/src/pine64_ox64/nonsecure/printf.h
@@ -0,0 +1,121 @@
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+// 2014-2019, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on
+// embedded systems with a very limited resources.
+// Use this instead of bloated standard/newlib printf.
+// These routines are thread safe and reentrant.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#ifndef _PRINTF_H_
+#define _PRINTF_H_
+
+#include
+#include
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Output a character to a custom device like UART, used by the printf() function
+ * This function is declared here only. You have to write your custom implementation somewhere
+ * \param character Character to output
+ */
+// #ifdef C_SECURE_CODE
+// void __putchar(char character);
+// #else
+void _putchar(char character);
+// #endif
+
+
+/**
+ * Tiny printf implementation
+ * You have to implement _putchar if you use printf()
+ * To avoid conflicts with the regular printf() API it is overridden by macro defines
+ * and internal underscore-appended functions like printf_() are used
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are written into the array, not counting the terminating null character
+ */
+#define printf printf_
+int printf_(const char* format, ...);
+
+
+/**
+ * Tiny sprintf implementation
+ * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD!
+ * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output!
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ */
+#define sprintf sprintf_
+int sprintf_(char* buffer, const char* format, ...);
+
+
+/**
+ * Tiny snprintf/vsnprintf implementation
+ * \param buffer A pointer to the buffer where to store the formatted string
+ * \param count The maximum number of characters to store in the buffer, including a terminating null character
+ * \param format A string that specifies the format of the output
+ * \param va A value identifying a variable arguments list
+ * \return The number of characters that COULD have been written into the buffer, not counting the terminating
+ * null character. A value equal or larger than count indicates truncation. Only when the returned value
+ * is non-negative and less than count, the string has been completely written.
+ */
+#define snprintf snprintf_
+#define vsnprintf vsnprintf_
+int snprintf_(char* buffer, size_t count, const char* format, ...);
+int vsnprintf_(char* buffer, size_t count, const char* format, va_list va);
+
+
+/**
+ * Tiny vprintf implementation
+ * \param format A string that specifies the format of the output
+ * \param va A value identifying a variable arguments list
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ */
+#define vprintf vprintf_
+int vprintf_(const char* format, va_list va);
+
+
+/**
+ * printf with output function
+ * You may use this as dynamic alternative to printf() with its fixed _putchar() output
+ * \param out An output function which takes one character and an argument pointer
+ * \param arg An argument pointer for user data passed to output function
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are sent to the output function, not counting the terminating null character
+ */
+int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // _PRINTF_H_
diff --git a/configs/pine64_ox64/Make.defs b/configs/pine64_ox64/Make.defs
index b1ae800f..292ebbc7 100644
--- a/configs/pine64_ox64/Make.defs
+++ b/configs/pine64_ox64/Make.defs
@@ -1,7 +1,7 @@
############################################################################
# Make.defs
#
-# Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved.
+# Copyright (c) 2024 Samsung Electronics Co., Ltd. All Rights Reserved.
# Author: Taras Drozdovskyi t.drozdovsky@samsung.com
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -53,18 +53,30 @@ ifeq ($(CONFIG_DEBUG_INF_GDB),y)
ARCHOPTIMIZATION += -ggdb
endif
-ARCHCPUFLAGS = -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907
+ARCHOPTIMIZATION += -falign-loops=4 -falign-functions=4 -falign-jumps=4 -malign-data=xlen
+ARCHOPTIMIZATION += -fno-jump-tables -fno-common -fstrict-volatile-bitfields -fshort-enums -fno-builtin
+
+ARCHCOMPILATION += -MMD -std=gnu99 -fms-extensions -fmessage-length=0
+
+#ARCHCPUFLAGS = -march=rv32imafcpzpsfoperand_xtheade
+ARCHCPUFLAGS = -march=rv32imafpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907 -mno-fdiv
#-mcmodel=medlow --specs=nano.specs
-#ARCHDEFINES += -DMTIME_RATE_HZ_DEF=32768 -DportUSING_MPU_WRAPPERS=1
-#ARCHDEFINES += -DCHIP=bl808 -DCPU_ID=m0 -DBOARD=bl808dk -DCONFIG_COMX=COM5 -DCMAKE_EXPORT_COMPILE_COMMANDS=OFF -DCONFIG_TLSF=y
-#ARCHDEFINES += -DBL808 -DCPU_M0 -DARCH_RISCV -DCONFIG_IRQ_NUM=80 -DBOARD=bl808dk -DBOARD_DIR= -DCONFIG_DEBUG=1 -DCONFIG_ROMAPI=1 -DCONFIG_USB_HS=y
+#ARCHDEFINES += -DMTIME_RATE_HZ_DEF=32768
+#ARCHDEFINES += -DCHIP=bl808 -DCPU_ID=m0 -DBOARD=bl808dk -DCONFIG_COMX=COM5 -DCMAKE_EXPORT_COMPILE_COMMANDS=OFF
+#ARCHDEFINES += -DBOARD_DIR= -DCONFIG_DEBUG=1 -DCONFIG_ROMAPI=1 -DCONFIG_USB_HS=y
#ARCHDEFINES += -DNEWLIB=0 -DNEWLIB_STANDARD=0
ARCHDEFINES += -DARCH_RISCV -DBFLB_TIMESTAMP_TIMEZONE=8 -DBFLB_USE_HAL_DRIVER -DBL808 -DCPU_M0
-ARCHDEFINES += -DCONFIG_IRQ_NUM=80 -DCONFIG_LIBC_FLOAT=1 -DCONFIG_LIBC_FLOAT_EX=1 -DCONFIG_LIBC_LONG_LONG=1 -DCONFIG_LOG_LEVEL=3 -DCONFIG_TLSF
-ARCHDEFINES += -DportasmHANDLE_INTERRUPT=interrupt_entry -Ddefault_interrupt_handler=freertos_risc_v_trap_handler -DCONFIG_FREERTOS
+ARCHDEFINES += -DCONFIG_IRQ_NUM=80 -DCONFIG_LIBC_FLOAT=1 -DCONFIG_LIBC_FLOAT_EX=1 -DCONFIG_LIBC_LONG_LONG=1 -DCONFIG_TLSF
+ARCHDEFINES += -DportasmHANDLE_INTERRUPT=interrupt_entry -DCONFIG_FREERTOS
+
+#ARCHDEFINES += -Ddefault_trap_handler=freertos_risc_v_trap_handler
+ARCHDEFINES += -Ddefault_interrupt_handler=freertos_risc_v_trap_handler
+
+ARCHDEFINES += -DportHANDLE_INTERRUPT=interrupt_entry
+ARCHDEFINES += -DportHANDLE_EXCEPTION=exception_entry
ARCHDEFINES += -DportUSING_MPU_WRAPPERS=1
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
@@ -72,16 +84,10 @@ AFLAGS = $(CFLAGS) -D__ASSEMBLY__
LDFLAGS = $(ARCHOPTIMIZATION)
ARCHINCLUDES = -I$(TOPDIR)/include
-#ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/bsp/board/bl808dk/.
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/libc/newlib/.
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/libc/.
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/mm/.
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/mm/tlsf/.
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/utils/log
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/utils/ring_buffer
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/utils/bflb_block_pool
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/utils/bflb_timestamp
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/utils/getopt
+ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/libc/newlib
+ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/libc
+ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/mm
+ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/mm/tlsf
ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/drivers/lhal/include
ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/drivers/lhal/include/arch
ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/drivers/lhal/include/arch/risc-v/t-head
@@ -91,21 +97,14 @@ ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/drivers/lhal/src/flash
ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/drivers/soc/bl808/std/include
ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/drivers/soc/bl808/std/include/hardware
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/pine64_ox64/nonsecure$
-
-#ARCHINCLUDES += -I$(TOPDIR)/FreeRTOS-metal/FreeRTOS-Kernel/include
-#ARCHINCLUDES += -I$(TOPDIR)/FreeRTOS-metal/FreeRTOS-Kernel/portable/GCC/RISC-V
-#ARCHINCLUDES += -I$(TOPDIR)/FreeRTOS-metal/FreeRTOS-Kernel/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions
-
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/os/freertos/include
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/os/freertos/portable/GCC/RISC-V/common
-ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/components/os/freertos/portable/GCC/RISC-V/common/chip_specific_extensions/RV32I_CLINT_no_extensions
-
-CFLAGS = -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -fstrict-volatile-bitfields -fshort-enums -fno-builtin
+ARCHINCLUDES += -I$(TOPDIR)/arch/riscv32/bl808/src/pine64_ox64/nonsecure
+ARCHINCLUDES += -I$(TOPDIR)/include/mtower
-CFLAGS += -MMD -std=gnu99 -g3 -O2
+ARCHINCLUDES += -I$(TOPDIR)/freertos/include
+ARCHINCLUDES += -I$(TOPDIR)/freertos/portable/GCC/RISC-V
+ARCHINCLUDES += -I$(TOPDIR)/freertos/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions
-CFLAGS += $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES)
+CFLAGS += $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHCOMPILATION) $(ARCHINCLUDES) $(ARCHDEFINES)
ASMEXT = .S
OBJEXT = .o
diff --git a/configs/pine64_ox64/defconfig b/configs/pine64_ox64/defconfig
index e578f307..0e6d94d9 100644
--- a/configs/pine64_ox64/defconfig
+++ b/configs/pine64_ox64/defconfig
@@ -42,7 +42,7 @@ CONFIG_DEBUGLEVEL=2
CONFIG_BOOTLOADER32=y
CONFIG_BOOTLOADER33=y
CONFIG_START_ADDRESS_BL32=0x00000000
-CONFIG_START_ADDRESS_BL33=0x10040000
+CONFIG_START_ADDRESS_BL33=0x58000000
#
# System Type
@@ -135,6 +135,15 @@ CONFIG_GCC_VERSION_T_HEAD_10_2_0=y
CONFIG_GCC_SITE="https://github.com/bouffalolab/toolchain_gcc_t-head_linux"
CONFIG_GCC_FOLDER="toolchain_gcc_t-head_linux-master"
+#
+# Standard Libc Configuration
+#
+
+#
+# Heap of secure part
+#
+CONFIG_TOTAL_HEAP_SIZE=0x2000
+
#
# GP TEE Configuration
#
diff --git a/docs/images/platforms/pine64_ox64/pine64-ox64.jpg b/docs/images/platforms/pine64_ox64/pine64-ox64.jpg
new file mode 100644
index 00000000..0a39312f
Binary files /dev/null and b/docs/images/platforms/pine64_ox64/pine64-ox64.jpg differ
diff --git a/docs/pine64_ox64.md b/docs/pine64_ox64.md
new file mode 100644
index 00000000..ecabf824
--- /dev/null
+++ b/docs/pine64_ox64.md
@@ -0,0 +1,30 @@
+# mTower on Pine64 Ox64 - RISC-V BL808
+
+[![Pine64 Ox64](images/platforms/pine64_ox64/pine64-ox64.jpg)](https://wiki.pine64.org/wiki/Ox64)
+
+# Contents
+1. [Introduction](#1-introduction)
+2. [Regular build](#2-regular-build)
+3. [BLDevCube Tool](#3-bldevcube-programming-tool)
+4. [Flash mTower on the device and run](#4-flash-mtower-on-the-device-and-run)
+5. [References](#5-references)
+
+## 1. Introduction
+The instructions here will tell how to run mTower on the [Pine64 Ox64] board.
+
+## 2. Regular build
+Start out by following the "Get and build the solution" in the [build.md] file.
+> Warning: Need to download the toolchain (exec. `make toolchain`).
+
+## 3. BlDevCube Programming Tool
+> TBD
+
+## 4. Flash mTower on the device and run
+```sh
+make flash
+```
+
+## 5. References
+
+[build.md]: build.md
+[Pine64 Ox64]: https://wiki.pine64.org/wiki/Ox64
diff --git a/freertos/portable/Common/mpu_wrappers.c b/freertos/portable/Common/mpu_wrappers.c
index 9ba0fbc4..ed3dcd67 100644
--- a/freertos/portable/Common/mpu_wrappers.c
+++ b/freertos/portable/Common/mpu_wrappers.c
@@ -45,6 +45,10 @@
#include "stream_buffer.h"
#include "mpu_prototypes.h"
+#ifdef BL808
+#include "bflb_uart.h"
+#endif
+
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/*-----------------------------------------------------------*/
@@ -140,6 +144,16 @@
}
#endif
/*-----------------------------------------------------------*/
+#ifdef BL808
+void MPU_bflb_uart_putchar(struct bflb_device_s *uart0, int character)
+{
+ BaseType_t xRunningPrivileged;
+
+ xPortRaisePrivilege( xRunningPrivileged );
+ bflb_uart_putchar(uart0, character);
+ vPortResetPrivilege( xRunningPrivileged );
+}
+#endif
#if ( INCLUDE_uxTaskPriorityGet == 1 )
UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
diff --git a/freertos/portable/GCC/RISC-V/bl808_port.c b/freertos/portable/GCC/RISC-V/bl808_port.c
new file mode 100644
index 00000000..1bd16cb4
--- /dev/null
+++ b/freertos/portable/GCC/RISC-V/bl808_port.c
@@ -0,0 +1,1102 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* ------------------------------------------------------------------
+ * This file is part of the FreeRTOS distribution and was contributed
+ * to the project by SiFive
+ *
+ * Implementation of functions defined in portable.h for the RISC-V
+ * RV32 port.
+ * ------------------------------------------------------------------
+ */
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include
+#include "task.h"
+#include "portmacro.h"
+#include "string.h"
+
+#include "csi_rv32_gcc.h"
+
+PRIVILEGED_DATA __attribute__ ((aligned(16))) StackType_t xISRStackTop;
+// PRIVILEGED_DATA __attribute__ ((aligned(128))) StackType_t xISRStackTop;
+
+#ifdef configCLINT_BASE_ADDRESS
+ #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIME_BASE_ADDRESS
+ #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIMECMP_BASE_ADDRESS
+ #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
+
+#if( configENABLE_FPU == 1 )
+ /*
+ * Setup the Floating Point Unit (FPU).
+ */
+ void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/*-----------------------------------------------------------*/
+
+/* Used to program the machine timer compare register. */
+//PRIVILEGED_DATA
+uint64_t ullNextTime = 0ULL;
+const uint64_t *pullNextTime = &ullNextTime;
+const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */
+//uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+// PRIVILEGED_DATA
+volatile uint64_t * pullMachineTimerCompareRegister;
+BaseType_t TrapNetCounter = 0;
+const BaseType_t *pTrapNetCounter = &TrapNetCounter;
+
+#if( portUSING_MPU_WRAPPERS == 1 )
+/** Variable that contains the current privilege state */
+volatile __attribute__ ((aligned(128))) uint32_t privilege_status = ePortMACHINE_MODE;
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+#endif
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking. A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ #warning This path not tested, or even compiled yet.
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+ the task stacks, and so will legitimately appear in many positions within
+ the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
+
+ static const uint8_t ucExpectedStackBytes[] = {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
+
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+#if( portUSING_MPU_WRAPPERS == 1 )
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+pmp_info_t xPmpInfo = {0,0};
+
+BaseType_t xIsPrivileged( void )
+{
+ return(privilege_status == ePortMACHINE_MODE);
+}
+
+/**
+ * @brief Setup of base region (first 3 regions)
+ * @details those regions won't be reconfigured during context switch
+ *
+ */
+static void prvSetupPMP( void ) PRIVILEGED_FUNCTION
+{
+ extern uint32_t __unprivileged_section_start__[];
+ extern uint32_t __unprivileged_section_end__[];
+
+ uint8_t ucDefaultAttribute;
+ size_t uxDefaultBaseAddr;
+ /**
+ * considered as unused in certain cases because of macro
+ * configASSERT_DEFINED
+ */
+ int32_t lResult __attribute__((unused)) = PMP_DEFAULT_ERROR;
+
+ if(0 == xPmpInfo.granularity) {
+ lResult = init_pmp (&xPmpInfo);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+ }
+
+ /* Check the expected PMP is present. */
+ if( portMINIMAL_NB_PMP <= xPmpInfo.nb_pmp)
+ {
+ /* First setup the start address of the unprivilleged flash */
+ ucDefaultAttribute = 0;
+ uxDefaultBaseAddr = 0;
+
+ lResult = addr_modifier (xPmpInfo.granularity,
+ ( size_t ) __unprivileged_section_start__,
+ &uxDefaultBaseAddr);
+ if(lResult)
+ printf("lResult [0] = %d\r\n", lResult);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ ucDefaultAttribute =
+ ((portPMP_REGION_READ_ONLY) |
+ (portPMP_REGION_EXECUTE) |
+ (portPMP_REGION_ADDR_MATCH_NA4));
+
+ lResult = write_pmp_config (&xPmpInfo, portUNPRIVILEGED_EXECUTE_REGION_START,
+ ucDefaultAttribute, uxDefaultBaseAddr);
+ if(lResult)
+ printf("lResult [0] = %d\r\n", lResult);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ /* Setup the end address of the unprivilleged flash */
+ ucDefaultAttribute = 0;
+ uxDefaultBaseAddr = 0;
+ lResult = addr_modifier (xPmpInfo.granularity,
+ ( size_t ) __unprivileged_section_end__,
+ &uxDefaultBaseAddr);
+ if(lResult)
+ printf("lResult [1] = %d\r\n", lResult);
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ ucDefaultAttribute = ((portPMP_REGION_READ_ONLY) |
+ (portPMP_REGION_EXECUTE) |
+ (portPMP_REGION_ADDR_MATCH_TOR));
+
+ lResult = write_pmp_config (&xPmpInfo, portUNPRIVILEGED_EXECUTE_REGION_END,
+ ucDefaultAttribute, uxDefaultBaseAddr);
+ if(lResult)
+ printf("lResult [1] = %d\r\n", lResult);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ /* Allow read only on the privilege status varibale */
+ // ucDefaultAttribute = 0;
+ // uxDefaultBaseAddr = 0;
+
+ // lResult = addr_modifier (xPmpInfo.granularity,
+ // ( size_t ) &privilege_status,
+ // &uxDefaultBaseAddr);
+ // if(lResult)
+ // printf("lResult [2] = %d\r\n", lResult);
+ // #if( configASSERT_DEFINED == 1 )
+ // {
+ // configASSERT(0 <= lResult);
+ // }
+ // #endif
+
+ // ucDefaultAttribute =
+ // ((portPMP_REGION_READ_WRITE) |
+ // // (portPMP_REGION_ADDR_MATCH_NAPOT));
+ // (portPMP_REGION_ADDR_MATCH_NA4));
+
+ // lResult = write_pmp_config (&xPmpInfo, portPRIVILEGE_STATUS_REGION,
+ // ucDefaultAttribute, uxDefaultBaseAddr);
+ // printf("lResult [2] = %d\r\n", lResult);
+ // #if( configASSERT_DEFINED == 1 )
+ // {
+ // configASSERT(0 <= lResult);
+ // }
+ // #endif
+ ucDefaultAttribute = 0;
+ uxDefaultBaseAddr = 0x2000A000;
+
+ lResult = napot_addr_modifier (xPmpInfo.granularity,
+ ( size_t ) 0x2000A000,
+ &uxDefaultBaseAddr, 512);
+ if(lResult)
+ printf("lResult [2] = %d\r\n", lResult);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ ucDefaultAttribute =
+ ((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NAPOT));
+ // (portPMP_REGION_ADDR_MATCH_NA4));
+
+ lResult = write_pmp_config (&xPmpInfo, portPRIVILEGE_STATUS_REGION,
+ ucDefaultAttribute, uxDefaultBaseAddr);
+ if(lResult)
+ printf("lResult [2] = %d\r\n", lResult);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+ }
+}
+#endif
+/*-----------------------------------------------------------*/
+
+#define CSR_STR(csr) #csr
+
+#define READ_CSR(reg) \
+ ({ \
+ unsigned long tmp; \
+ asm volatile("csrr %0, " CSR_STR(reg) : "=r"(tmp)); \
+ tmp; \
+ })
+
+/**
+ * @brief
+ *
+ * @param xIsrTop
+ */
+BaseType_t xPortFreeRTOSInit( StackType_t xIsrTop ) PRIVILEGED_FUNCTION
+{
+ UBaseType_t uxHartid;
+
+ extern BaseType_t xPortMoveISRStackTop( StackType_t *xISRStackTop);
+ extern void freertos_risc_v_trap_handler(void);
+
+ /**
+ * We do the initialization of FreeRTOS priviledged data section
+ */
+ #if( portUSING_MPU_WRAPPERS == 1 )
+ {
+ /**
+ * Considered by the compiler as unused because of the inline asm block
+ */
+ extern uint32_t __privileged_data_start__[] __attribute__((unused));
+ extern uint32_t __privileged_data_end__[] __attribute__((unused));
+ __asm__ __volatile__ (
+ /* Zero the privileged_data segment. */
+ "la t1, __privileged_data_start__ \n"
+ "la t2, __privileged_data_end__ \n"
+
+ "bge t1, t2, 2f \n"
+
+ "1: \n"
+ #if __riscv_xlen == 32
+ "sw x0, 0(t1) \n"
+ "addi t1, t1, 4 \n"
+ "blt t1, t2, 1b \n"
+ #else
+ "sd x0, 0(t1) \n"
+ "addi t1, t1, 8 \n"
+ "blt t1, t2, 1b \n"
+ #endif
+ "2: \n"
+ ::
+ : "t1", "t2"
+
+ );
+
+ }
+ #endif
+
+ /*
+ * xIsrStack Is a Buffer Allocated into Application
+ * xIsrStack_top is the Top adress of this Buffer
+ * it will contain the isrstack and space or the registeries backup
+ *
+ * Top +----------------------+ xIsrTop
+ * | .... |
+ * | |
+ * Bottom +----------------------+ xISRStack
+ *
+ * stack mapping after :
+ * Top +----------------------+ xIsrTop
+ * | Space to store |
+ * | context before |
+ * | FreeRtos scheduling |
+ * | .... |
+ * +----------------------+ xISRStackTop
+ * | stack space for |
+ * | ISR execution |
+ * | .... |
+ * | |
+ * Bottom +----------------------+ xISRStack
+ */
+
+ xISRStackTop = xIsrTop;
+
+ if ( 0 == xPortMoveISRStackTop(&xISRStackTop)){
+ /* Error no enough place to store cntext or bad parameter */
+ return -1;
+ }
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* Check alignment of the interrupt stack - which is the same as the
+ stack that was being used by main() prior to the scheduler being
+ started. */
+ configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ #endif /* configASSERT_DEFINED */
+
+ __asm__ __volatile__ ("csrr %0, mhartid" : "=r"(uxHartid));
+
+ pullMachineTimerCompareRegister = ( volatile uint64_t *) ( configMTIMECMP_BASE_ADDRESS + uxHartid * sizeof(uint64_t) );
+
+ #if( configCLINT_BASE_ADDRESS != 0 )
+ /* There is a clint then interrupts can branch directly to the FreeRTOS
+ * trap handler.
+ */
+ // unsigned long tval;
+
+ // tval = READ_CSR(0x305);
+ // printf("mtval:%08x\r\n", (int)tval);
+ // printf("freertos_risc_v_trap_handler:%p\r\n", freertos_risc_v_trap_handler);
+
+ __asm__ __volatile__ (
+ "la t0, freertos_risc_v_trap_handler\n"
+ "csrw mtvec, t0\n"
+ );
+
+ // tval = READ_CSR(0x305);
+ // printf("mtval:%08x\r\n", (int)tval);
+ // printf("freertos_risc_v_trap_handler:%08x\r\n", freertos_risc_v_trap_handler);
+ #else
+ #warning "*** The interrupt controller must to be configured before (ouside of this file). ***"
+ #endif
+
+ #if( portUSING_MPU_WRAPPERS == 1 )
+ /* Configure the regions in the PMP that are common to all tasks. */
+ prvSetupPMP();
+ #endif
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Do the PMP config switch when switching task
+ * @param ulNbPmp number of configurable PMP
+ * @param xPMPSettings PMP configs stored in task TCB
+ * @warning the number of configurable PMP is not the total number of PMP
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+__attribute__ (( naked )) void vPortPmpSwitch ( uint32_t ulNbPmp,
+ xMPU_SETTINGS * xPMPSettings) PRIVILEGED_FUNCTION
+#else
+__attribute__ (( naked )) void vPortPmpSwitch ( uint32_t ulNbPmp) PRIVILEGED_FUNCTION
+#endif
+{
+#if( portUSING_MPU_WRAPPERS == 1 )
+ /**
+ * a0: xPmpInfo.nb_pmp - 3 (3 because We use 3 pmp config by default)
+ * a1: pxCurrentTCB->xPMPSettings (supposed to be the 2nd element of structure TCB_t)
+ */
+ #if( __riscv_xlen == 32 )
+ __asm__ __volatile__ (
+ "addi a0, %0, -3 \n\t"
+ "addi a1, %1, 4 \n\t"
+ :: "r"(xPmpInfo.nb_pmp), "r"(pxCurrentTCB) : "a0", "a1"
+ );
+ #endif /* ( __riscv_xlen == 32 ) */
+ #if( __riscv_xlen == 64 )
+ __asm__ __volatile__ (
+ "addi a0, %0, -3 \n\t"
+ "addi a1, %1, 8 \n\t"
+ :: "r"(xPmpInfo.nb_pmp), "r"(pxCurrentTCB) : "a0", "a1"
+ );
+ #endif /* ( __riscv_xlen == 64 ) */
+
+ /* Compute jump offset to avoid configure unuse PMP */
+ __asm__ __volatile__ (
+ "li t0, 13 \n" /* maximum number of reconfigurable PMP for a core */
+ "sub a2, t0, a0 \n"
+ "slli a2, a2, 3 \n" /* compute the jump offset */
+ ::: "a0", "a2", "t0"
+ );
+
+ /* clear pmp config before setting addr */
+#if __riscv_xlen == 32
+ __asm__ __volatile__ (
+ "li t1, 0x18181818 \n"
+ /**
+ * we avoid disabling permanent PMP config, therefore those region mask
+ * are set to 0
+ */
+ "li t2, 0x18000000 \n"
+ "csrc pmpcfg0, t2 \n"
+ "csrc pmpcfg1, t1 \n"
+ "csrc pmpcfg2, t1 \n"
+ "csrc pmpcfg3, t1 \n"
+ :::"t1", "t2"
+ );
+#elif __riscv_xlen == 64
+ __asm__ __volatile__ (
+ "li t1, 0x1818181818181818 \n"
+ /**
+ * we avoid disabling permanent PMP config, therefore those region mask
+ * are set to 0
+ */
+ "li t2, 0x1818181818000000 \n"
+ "csrc pmpcfg0, t2 \n"
+ "csrc pmpcfg2, t1 \n"
+ :::"t1", "t2"
+ );
+#endif
+
+ /**
+ * Save pmp address in pmpaddrx registers
+ * Please note that pmpaddr0, pmpaddr1, pmpaddr2 are not reconfigured,
+ * they are configured once at the initialization of the scheduler
+ */
+#if __riscv_xlen == 32
+ __asm__ __volatile__ (
+ "add t0, a1, 32 \n" /* get pmp address configs */
+ "la t1, 1f \n" /* compute the jump address */
+ "add t2, t1, a2 \n"
+ "jr t2 \n"
+ "1: \n"
+ "lw t2, 48(t0) \n"
+ "csrw pmpaddr15, t2 \n"
+ "lw t1, 44(t0) \n"
+ "csrw pmpaddr14, t1 \n"
+ "lw t2, 40(t0) \n"
+ "csrw pmpaddr13, t2 \n"
+ "lw t1, 36(t0) \n"
+ "csrw pmpaddr12, t1 \n"
+ "lw t2, 32(t0) \n"
+ "csrw pmpaddr11, t2 \n"
+ "lw t1, 28(t0) \n"
+ "csrw pmpaddr10, t1 \n"
+ "lw t2, 24(t0) \n"
+ "csrw pmpaddr9, t2 \n"
+ "lw t1, 20(t0) \n"
+ "csrw pmpaddr8, t1 \n"
+ "lw t2, 16(t0) \n"
+ "csrw pmpaddr7, t2 \n"
+ "lw t1, 12(t0) \n"
+ "csrw pmpaddr6, t1 \n"
+ "lw t2, 8(t0) \n"
+ "csrw pmpaddr5, t2 \n"
+ "lw t1, 4(t0) \n"
+ "csrw pmpaddr4, t1 \n"
+ "lw t2, 0(t0) \n"
+ "csrw pmpaddr3, t2 \n"
+ ::: "t0", "t1", "t2"
+ );
+#elif __riscv_xlen == 64
+ __asm__ __volatile__ (
+ "add t0, a1, 32 \n" /* get pmp address configs */
+ "la t1, 1f \n" /* compute the jump address */
+ "add t2, t1, a2 \n"
+ "jr t2 \n"
+ "1: \n"
+ "ld t2, 96(t0) \n"
+ "csrw pmpaddr15, t2 \n"
+ "ld t1, 88(t0) \n"
+ "csrw pmpaddr14, t1 \n"
+ "ld t2, 80(t0) \n"
+ "csrw pmpaddr13, t2 \n"
+ "ld t1, 72(t0) \n"
+ "csrw pmpaddr12, t1 \n"
+ "ld t2, 64(t0) \n"
+ "csrw pmpaddr11, t2 \n"
+ "ld t1, 56(t0) \n"
+ "csrw pmpaddr10, t1 \n"
+ "ld t2, 48(t0) \n"
+ "csrw pmpaddr9, t2 \n"
+ "ld t1, 40(t0) \n"
+ "csrw pmpaddr8, t1 \n"
+ "ld t2, 32(t0) \n"
+ "csrw pmpaddr7, t2 \n"
+ "ld t1, 24(t0) \n"
+ "csrw pmpaddr6, t1 \n"
+ "ld t2, 16(t0) \n"
+ "csrw pmpaddr5, t2 \n"
+ "ld t1, 8(t0) \n"
+ "csrw pmpaddr4, t1 \n"
+ "ld t2, 0(t0) \n"
+ "csrw pmpaddr3, t2 \n"
+ ::: "t0", "t1", "t2"
+ );
+#endif
+
+
+#if __riscv_xlen == 32
+ /* Compute jump offset to avoid configure unuse PMP 32bits version */
+ __asm__ __volatile__ (
+ "addi a0, a0, 2 \n"
+ "srli t1, a0, 2 \n" /* divide by 4 */
+ "li t2, 3 \n" /* number of config regs (4) */
+ "sub t2, t2, t1 \n"
+ "slli t2, t2, 4 \n"
+ ::: "a0", "t1", "t2"
+ );
+#elif __riscv_xlen == 64
+ /* Compute jump offset to avoid configure unuse PMP 64bits version */
+ __asm__ __volatile__ (
+ "addi a0, a0, 2 \n"
+ "srli t1, a0, 3 \n" /* divide by 8 */
+ "li t2, 1 \n" /* number of config regs (2) */
+ "sub t2, t2, t1 \n"
+ "slli t2, t2, 4 \n"
+ ::: "a0", "t1", "t2"
+ );
+#endif
+
+ /* Configure PMP mode (rights and mode) */
+#if __riscv_xlen == 32
+ __asm__ __volatile__ (
+ "add a0, a1, 16 \n" /* get pmp config mask */
+
+ "la t0, 1f \n"
+ "add t0, t0, t2 \n"
+ "jr t0 \n"
+ "1: \n"
+
+ "lw t1, 12(a0) \n"
+ "lw t2, 12(a1)\n"
+ "csrc pmpcfg3, t1 \n"
+ "csrs pmpcfg3, t2 \n"
+
+ "lw t1, 8(a0) \n"
+ "lw t2, 8(a1)\n"
+ "csrc pmpcfg2, t1 \n"
+ "csrs pmpcfg2, t2 \n"
+
+ "lw t1, 4(a0) \n"
+ "lw t2, 4(a1)\n"
+ "csrc pmpcfg1, t1 \n"
+ "csrs pmpcfg1, t2 \n"
+
+ "lw t1, 0(a0) \n"
+ "lw t2, 0(a1)\n"
+ "csrc pmpcfg0, t1 \n"
+ "csrs pmpcfg0, t2 \n"
+ ::: "t0", "t1", "t2", "a0", "a1"
+ );
+#elif __riscv_xlen == 64
+ __asm__ __volatile__ (
+ "add a0, a1, 16 \n" /* get pmp config mask */
+
+ "la t0, 1f \n"
+ "add t0, t0, t2 \n"
+ "jr t0 \n"
+ "1: \n"
+
+ "ld t1, 8(a0) \n"
+ "ld t2, 8(a1)\n"
+ "csrc pmpcfg2, t1 \n"
+ "csrs pmpcfg2, t2 \n"
+
+ "ld t1, 0(a0) \n"
+ "ld t2, 0(a1)\n"
+ "csrc pmpcfg0, t1 \n"
+ "csrs pmpcfg0, t2 \n"
+ ::: "t0", "t1", "t2", "a0", "a1"
+ );
+#endif
+ __asm__ __volatile__ (
+ "fence.i \n"
+ :::
+ );
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) */
+
+ __asm__ __volatile__ (
+ "ret \n"
+ :::
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+
+ void vPortSetupTimerInterrupt( void )
+ {
+ #if( __riscv_xlen == 32 )
+ uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+ // volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );
+ // volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );
+ volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
+ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
+
+ #endif /* __riscv_xlen == 32 */
+ #if( __riscv_xlen == 64 )
+ volatile uint64_t * const pulTime = ( volatile uint64_t * const ) ( configMTIME_BASE_ADDRESS );
+ #endif /* __riscv_xlen == 64 */
+
+ #if( __riscv_xlen == 32 )
+ do
+ {
+ ulCurrentTimeHigh = *pulTimeHigh;
+ ulCurrentTimeLow = *pulTimeLow;
+ } while( ulCurrentTimeHigh != *pulTimeHigh );
+
+ ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+ ullNextTime <<= 32ULL;
+ ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+ #endif /* __riscv_xlen == 32 */
+ #if( __riscv_xlen == 64 )
+ ullNextTime = *pulTime;
+ #endif /* __riscv_xlen == 64 */
+
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ *pullMachineTimerCompareRegister = ullNextTime;
+
+ /* Prepare the time to use after the next tick interrupt. */
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ // printf("pulTimeLow = %p\r\n",pulTimeLow);
+ // printf("pullMachineTimerCompareRegister = %p\r\n",pullMachineTimerCompareRegister);
+ // printf("pulTimeLow = %x\r\n",*pulTimeLow);
+ // printf("pulTimeHigh = %x\r\n",*pulTimeHigh);
+ // printf("ullNextTime = %llx\r\n",ullNextTime);
+ // printf("pullNextTime = %llx\r\n",*pullNextTime);
+ // printf("pullNextTime = %p\r\n",pullNextTime);
+ // printf("pullMachineTimerCompareRegister = %llx\r\n",*pullMachineTimerCompareRegister);
+ // printf("uxTimerIncrementsForOneTick = %x\r\n", uxTimerIncrementsForOneTick);
+ }
+
+#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Start scheduler
+ *
+ * @return BaseType_t error code (pdFAIL or pdPASS)
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION
+{
+ extern void xPortStartFirstTask( void );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t mtvec = 0;
+
+ /* Check the least significant two bits of mtvec are 00 - indicating
+ single vector mode. */
+ __asm__ __volatile__ (
+ " csrr %0, mtvec \n"
+ : "=r"( mtvec )
+ );
+ // printf("mtvec = %x\r\n", mtvec);
+ configASSERT( ( mtvec & 0x03UL ) == 0 );
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* If there is a CLINT then it is ok to use the default implementation
+ in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+ configure whichever clock is to be used to generate the tick interrupt. */
+ vPortSetupTimerInterrupt();
+ // #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+ // {
+ // /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
+ // for external interrupt. _RB_ What happens here when mtime is not present as
+ // with pulpino? */
+ // __asm volatile( "csrs mie, %0" :: "r"(0x880) );
+ // }
+ // #else
+ // {
+ // /* Enable external interrupts. */
+ // __asm volatile( "csrs mie, %0" :: "r"(0x800) );
+ // }
+ // #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
+ extern void bflb_irq_enable(int irq);
+ bflb_irq_enable(7);
+ xPortStartFirstTask();
+
+ /* Should not get here as after calling xPortStartFirstTask() only tasks
+ should be executing. */
+ return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ //extern void xPortRestoreBeforeFirstTask(void);
+
+ //xPortRestoreBeforeFirstTask();
+
+ /*
+ * Should not get here as after calling xPortRestoreBeforeFirstTask() we should
+ * return after de execution of xPortStartFirstTask in xPortStartScheduler function.
+ */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+#if( portUSING_MPU_WRAPPERS == 1 )
+__attribute__((naked)) void vPortSyscall( unsigned int Value ) PRIVILEGED_FUNCTION
+{
+ /* Remove compiler warning about unused parameter. */
+ ( void ) Value;
+
+ __asm__ __volatile__ (
+ " ecall \n"
+ " ret \n"
+ :::
+ );
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((naked)) void vRaisePrivilege( void ) PRIVILEGED_FUNCTION
+{
+ __asm__ __volatile__ (
+ " .extern privilege_status \n"
+ " li a0,%0 \n"
+ " ecall \n"
+ " la a0, privilege_status \n"
+ " li t0, %1 \n"
+ " sw t0, 0(a0) \n" /* we use sw because privilege_status is uint32_t */
+ " ret \n"
+ ::"i"(portSVC_SWITCH_TO_MACHINE), "i"(ePortMACHINE_MODE):
+ );
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((naked)) void vResetPrivilege( void ) PRIVILEGED_FUNCTION
+{
+ __asm__ __volatile__ (
+ " .extern privilege_status \n"
+ " li a0,%0 \n"
+ " ecall \n"
+ " la a0, privilege_status \n"
+ " li t0, %1 \n"
+ " sw t0, 0(a0) \n" /* we use sw because privilege_status is uint32_t */
+ " ret \n"
+ ::"i"(portSVC_SWITCH_TO_USER), "i"(ePortUSER_MODE):
+ );
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Store PMP settings in Task TCB - the name this function
+ * is vPortStoreTaskMPUSettings in order to be MPU compliant
+ *
+ * @param[out] xPMPSettings PMP settings stored in Task TCB
+ * @param[in] xRegions PMP configuration of the task
+ * @param[in] pxBottomOfStack address of bottom of stack
+ * @param[in] ulStackDepth size of stack
+ */
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xPMPSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t *pxBottomOfStack,
+ uint32_t ulStackDepth ) PRIVILEGED_FUNCTION
+{
+ int32_t lIndex;
+ uint32_t ul;
+
+ /**
+ * considered as unused in certain cases because of macro
+ * configASSERT_DEFINED
+ */
+ int32_t lResult __attribute__((unused)) = PMP_DEFAULT_ERROR;
+ size_t uxBaseAddressChecked = 0;
+
+ if(0 == xPmpInfo.granularity) {
+ lResult = init_pmp (&xPmpInfo);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+ }
+
+ memset(xPMPSettings, 0, sizeof(xMPU_SETTINGS));
+
+ if( xRegions == NULL ) {
+ /* No PMP regions are specified so allow access to all data section */
+
+ /* Config stack start address */
+ uxBaseAddressChecked = 0;
+ lResult = addr_modifier (xPmpInfo.granularity,
+ (size_t) pxBottomOfStack,
+ &uxBaseAddressChecked);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ xPMPSettings->uxRegionBaseAddress[0] = uxBaseAddressChecked;
+
+ xPMPSettings->uxPmpConfigRegAttribute[portGET_PMPCFG_IDX(portSTACK_REGION_START)] +=
+ ((UBaseType_t)((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NA4)) <<
+ portPMPCFG_BIT_SHIFT(portSTACK_REGION_START));
+
+ xPMPSettings->uxPmpConfigRegMask[portGET_PMPCFG_IDX(portSTACK_REGION_START)] +=
+ ((UBaseType_t)0xFF << portPMPCFG_BIT_SHIFT(portSTACK_REGION_START));
+
+ /* Config stack end address and TOR */
+ uxBaseAddressChecked = 0;
+ lResult = addr_modifier (xPmpInfo.granularity,
+ (size_t) pxBottomOfStack + ( size_t ) ulStackDepth * sizeof( StackType_t ),
+ &uxBaseAddressChecked);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ xPMPSettings->uxRegionBaseAddress[1] = uxBaseAddressChecked;
+
+ xPMPSettings->uxPmpConfigRegAttribute[portGET_PMPCFG_IDX(portSTACK_REGION_END)] +=
+ ((UBaseType_t)((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_TOR)) <<
+ portPMPCFG_BIT_SHIFT(portSTACK_REGION_END));
+
+ xPMPSettings->uxPmpConfigRegMask[portGET_PMPCFG_IDX(portSTACK_REGION_END)] +=
+ ((UBaseType_t)0xFF << portPMPCFG_BIT_SHIFT(portSTACK_REGION_END));
+
+ /* Invalidate all other configurable regions. */
+ for( ul = 2; ul < portNUM_CONFIGURABLE_REGIONS_REAL (xPmpInfo.nb_pmp) + 2; ul++ )
+ {
+ xPMPSettings->uxRegionBaseAddress[ul] = 0UL;
+ xPMPSettings->uxPmpConfigRegMask[portGET_PMPCFG_IDX(portSTACK_REGION_START + ul)] +=
+ ((UBaseType_t)0xFF << portPMPCFG_BIT_SHIFT(portSTACK_REGION_START + ul));
+ }
+ }
+ else
+ {
+ /* This function is called automatically when the task is created - in
+ which case the stack region parameters will be valid. At all other
+ times the stack parameters will not be valid and it is assumed that the
+ stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Config stack start address */
+ uxBaseAddressChecked = 0;
+ lResult = addr_modifier (xPmpInfo.granularity,
+ (size_t) pxBottomOfStack,
+ &uxBaseAddressChecked);
+ if(lResult)
+ printf("lResult [3] = %d\r\n",lResult);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ xPMPSettings->uxRegionBaseAddress[0] = uxBaseAddressChecked;
+
+ xPMPSettings->uxPmpConfigRegAttribute[portGET_PMPCFG_IDX(portSTACK_REGION_START)] +=
+ ((UBaseType_t)((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_NA4)) <<
+ portPMPCFG_BIT_SHIFT(portSTACK_REGION_START));
+
+ xPMPSettings->uxPmpConfigRegMask[portGET_PMPCFG_IDX(portSTACK_REGION_START)] +=
+ ((UBaseType_t)0xFF << portPMPCFG_BIT_SHIFT(portSTACK_REGION_START));
+
+ /* Config stack end address and TOR */
+ uxBaseAddressChecked = 0;
+ lResult = addr_modifier (xPmpInfo.granularity,
+ (size_t) pxBottomOfStack + ( size_t ) ulStackDepth * sizeof( StackType_t ),
+ &uxBaseAddressChecked);
+ if(lResult)
+ printf("lResult [4] = %d\r\n",lResult);
+ #if( configASSERT_DEFINED == 1 )
+ {
+ configASSERT(0 <= lResult);
+ }
+ #endif
+
+ xPMPSettings->uxRegionBaseAddress[1] = uxBaseAddressChecked;
+
+ xPMPSettings->uxPmpConfigRegAttribute[portGET_PMPCFG_IDX(portSTACK_REGION_END)] +=
+ ((UBaseType_t)((portPMP_REGION_READ_WRITE) |
+ (portPMP_REGION_ADDR_MATCH_TOR)) <<
+ portPMPCFG_BIT_SHIFT(portSTACK_REGION_END));
+
+ xPMPSettings->uxPmpConfigRegMask[portGET_PMPCFG_IDX(portSTACK_REGION_END)] +=
+ ((UBaseType_t)0xFF << portPMPCFG_BIT_SHIFT(portSTACK_REGION_END));
+ }
+
+ lIndex = 0;
+
+ for( ul = 2; ul < (portNUM_CONFIGURABLE_REGIONS_REAL (xPmpInfo.nb_pmp) + 2); ul++ )
+ {
+ if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+ {
+ xPMPSettings->uxRegionBaseAddress[ul] = (size_t) xRegions[ lIndex ].pvBaseAddress;
+
+ xPMPSettings->uxPmpConfigRegAttribute[portGET_PMPCFG_IDX(portSTACK_REGION_START + ul)] +=
+ ((UBaseType_t)( xRegions[ lIndex ].ulParameters ) <<
+ portPMPCFG_BIT_SHIFT(portSTACK_REGION_START + ul));
+
+ xPMPSettings->uxPmpConfigRegMask[portGET_PMPCFG_IDX(portSTACK_REGION_START + ul)] +=
+ ((UBaseType_t)0xFF << portPMPCFG_BIT_SHIFT(portSTACK_REGION_START + ul));
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xPMPSettings->uxRegionBaseAddress[ul] = 0UL;
+ xPMPSettings->uxPmpConfigRegMask[portGET_PMPCFG_IDX(portSTACK_REGION_START + ul)] +=
+ ((UBaseType_t)0xFF << portPMPCFG_BIT_SHIFT(portSTACK_REGION_START + ul));
+ }
+
+ lIndex++;
+ }
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ // check we do not want to configure unavailable regions
+ if(xPmpInfo.nb_pmp < MAX_PMP_REGION) {
+ configASSERT(xRegions[ lIndex ].ulLengthInBytes == 0UL);
+ }
+ }
+ #endif
+ }
+}
+/*-----------------------------------------------------------*/
+#endif
+
+__attribute__((naked)) void vPortUpdatePrivilegeStatus( UBaseType_t status ) PRIVILEGED_FUNCTION
+{
+ /* Remove compiler warning about unused parameter. */
+ ( void ) status;
+
+ #if ( portUSING_MPU_WRAPPERS == 1 )
+ __asm__ __volatile__(
+ " .extern privilege_status \n"
+ " li t0, 0x1800 \n"
+ " and t0, a0, t0 \n"
+ " srli t0, t0, 11 \n"
+ " la a0, privilege_status \n"
+ " sw t0, 0(a0)"
+ ::: "t0", "a0"
+ );
+ #endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+
+ __asm__ __volatile__ (
+ " ret \n"
+ :::
+ );
+}
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION
+#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters ) PRIVILEGED_FUNCTION
+#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+{
+ UBaseType_t mstatus;
+ extern StackType_t * pxPortAsmInitialiseStack( StackType_t *, TaskFunction_t, void *, UBaseType_t);
+
+ /* Generate the value to set in mstatus. */
+ #if( portUSING_MPU_WRAPPERS == 1 )
+ /**
+ * Generate the value:
+ * - 0x80 (MPIE set and MPP = usermode) if run in unprivilege mode (xRunPrivileged == 0).
+ * - 0x1880 (MPIE set and MPP = machinemode) if run in privilege mode (xRunPrivileged != 0).
+ */
+ __enable_irq();
+
+ __asm__ __volatile__ (
+ " csrr t0, mstatus \n" /* Obtain current mstatus value. */
+ " andi t0, t0, ~0x8 \n" /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
+ " addi t1, x0, 0x188 \n" /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
+ " slli t1, t1, 4 \n"
+ " not t2, t1 \n" /* reset previous value */
+ " and t0, t0, t2 \n"
+ " mv t1, x0 \n"
+ " beqz a3, 1f \n"
+ " addi t1, t1, 0x180 \n"
+ " 1: \n"
+ " ori t1, t1, 0x8 \n"
+ " slli t1, t1, 4 \n"
+ " or %0, t0, t1 \n"
+ :"=r" ( mstatus )::"t0", "t1", "t2", "a3"
+ );
+ #else
+ __asm__ __volatile__ (
+ " csrr t0, mstatus \n" /* Obtain current mstatus value. */
+ " andi t0, t0, ~0x8 \n" /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
+ " addi t1, x0, 0x188 \n" /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
+ " slli t1, t1, 4 \n"
+ " not t2, t1 \n" /* reset previous value */
+ " and t0, t0, t2 \n"
+ " addi t1, x0, 0x188 \n"
+ " slli t1, t1, 4 \n"
+ " or %0, t0, t1 \n"
+ :"=r" ( mstatus )::"t0", "t1", "t2"
+ );
+ #endif /* ( portUSING_MPU_WRAPPERS == 1 ) */
+
+ return pxPortAsmInitialiseStack(pxTopOfStack, pxCode, pvParameters, mstatus);
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ __asm__ __volatile__ (
+ "csrr t0, misa \n" /* Get misa */
+ "li t1, 0x10028 \n" /* 0x10028 = Q,F,D Quad, Single or Double precission floating point */
+ "and t0, t0, t1 \n"
+ "beqz t0, 1f \n" /* check if Q,F or D is present into misa */
+ "csrr t0, mstatus \n" /* Floating point unit is present so need to put it into initial state */
+ "lui t1, 0x2 \n" /* t1 = 0x1 << 12 */
+ "or t0, t0, t1 \n"
+ "csrw mstatus, t0 \n" /* Set FS to initial state */
+ "csrwi fcsr, 0 \n" /* Clear Floating-point Control and Status Register */
+ "1: \n"
+ :::
+ );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
diff --git a/freertos/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/freertos/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 00000000..01c4280d
--- /dev/null
+++ b/freertos/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,69 @@
+/*
+ * FreeRTOS Kernel V10.4.6
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
+ * is common to all currently supported RISC-V chips. There is only one
+ * portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
+ * as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
+ * compiler's!) include path. For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions
+ *
+ */
+
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_SIFIVE_CLINT 1
+#define portasmHAS_MTIME 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+ /* No additional registers to save, so this macro does nothing. */
+ .endm
+
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+ /* No additional registers to restore, so this macro does nothing. */
+ .endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/freertos/portable/GCC/RISC-V/portASM.S b/freertos/portable/GCC/RISC-V/portASM.S
index ad19d045..2712db09 100644
--- a/freertos/portable/GCC/RISC-V/portASM.S
+++ b/freertos/portable/GCC/RISC-V/portASM.S
@@ -135,8 +135,13 @@
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
definitions. */
-#ifndef portasmHAS_CLINT
- #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
+
+#if !defined(portasmHAS_CLINT) && !defined(portasmHAS_MTIME)
+ #error freertos_risc_v_chip_specific_extensions.h must define either portasmHAS_CLINT or portasmHAS_MTIME (or both) to either 1 (present) or 0 (not present).
+#endif
+
+#ifdef portasmHAS_CLINT
+ #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef portHANDLE_INTERRUPT
@@ -396,6 +401,8 @@ freertos_risc_v_trap_handler:
*/
csrw mscratch, t0
csrr t0, mcause
+ // li a1, 0x807FFFFF
+ // and t0, t0, a1
blt t0, x0, handle_interrupt
handle_exception:
@@ -424,6 +431,8 @@ handle_exception:
* else: problem
*/
+ slli t0, t0, 9
+ srli t0, t0, 9
addi t0, t0, -8
blt t0, x0, is_exception /* mcause < 8, must be fault */
addi t0, t0, -4
@@ -573,17 +582,23 @@ handle_interrupt:
/* Load pxCurrentTCB and update first TCB member(pxTopOfStack) with sp. */
load_x s0, pxCurrentTCB
store_x sp, 0( s0 )
+// csrr a0, mcause
+// li t0, 0x807FFFFF
+// and a0, a0, t0
/* Save sp into s1 */
mv s1, sp
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
-#if( portasmHAS_CLINT != 0 )
+#if ( portasmHAS_CLINT != 0 ) || ( portasmHAS_MTIME != 0 )
addi t0, x0, 1
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
+ addi t1, x0, 7
csrr t2, mcause
+ slli t2, t2, 9
+ srli t2, t2, 9
bne t2, t1, test_if_external_interrupt
load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
@@ -624,10 +639,12 @@ restore_before_exit:
test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
csrr t2, mcause
+ li a1, 0x807FFFFF
+ and t2, t2, a1
bne t2, t1, unrecoverable_error /* Something as yet unhandled. */
j unrecoverable_error
-#endif /* portasmHAS_CLINT */
+#endif /* portasmHAS_MTIME or portasmHAS_CLINT*/
external_interrupt:
/* Switch to ISR stack before function call. */
diff --git a/freertos/portable/GCC/RISC-V/portmacro.h b/freertos/portable/GCC/RISC-V/portmacro.h
index df5af4e6..2a024fa8 100644
--- a/freertos/portable/GCC/RISC-V/portmacro.h
+++ b/freertos/portable/GCC/RISC-V/portmacro.h
@@ -297,7 +297,7 @@ extern void vTaskExitCritical( void );
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
-#if( portUSING_MPU_WRAPPERS == 1 )
+#if( portUSING_MPU_WRAPPERS == 1 && !defined(BL808))
#define portDISABLE_INTERRUPTS() vPortSyscall(portSVC_DISABLE_INTERRUPTS)
#define portENABLE_INTERRUPTS() vPortSyscall(portSVC_ENABLE_INTERRUPTS)
#else
diff --git a/freertos/tasks.c b/freertos/tasks.c
index 43517ab8..7a1a25a4 100644
--- a/freertos/tasks.c
+++ b/freertos/tasks.c
@@ -2749,7 +2749,7 @@ BaseType_t xTaskIncrementTick( void )
/* Minor optimisation. The tick count cannot change in this
* block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
-
+ // printf("\r\ntask=%s\r\n", pxCurrentTCB->pcTaskName);
/* Increment the RTOS tick, switching the delayed and overflowed
* delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
@@ -3028,6 +3028,7 @@ void vTaskSwitchContext( void )
}
else
{
+ // printf("\r\nSwitchContextS=%s\r\n", pxCurrentTCB->pcTaskName);
xYieldPending = pdFALSE;
traceTASK_SWITCHED_OUT();
@@ -3091,6 +3092,7 @@ void vTaskSwitchContext( void )
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
+ // printf("\r\nSwitchContextE=%s\r\n", pxCurrentTCB->pcTaskName);
}
/*-----------------------------------------------------------*/