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  • Technical University Munich
  • Munich, Germany
  • 00:41 (UTC -12:00)
  • X @sathviksat

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  1. stuwerk01_tum stuwerk01_tum Public

    StudentWerk 01 Python Automation for RISC_V Inst set

    Python 1

  2. xxv_open_nic_driver xxv_open_nic_driver Public

    Xilinx Open NIC driver to support XXV 10G/25G IP with Open NIC design

    1

  3. VerilogSystemDesignLab VerilogSystemDesignLab Public

    Verilog System Design Lab 2023, TUM

  4. sancar17/ACNN-using-PL sancar17/ACNN-using-PL Public

    C++

  5. open-nic-shell open-nic-shell Public

    Forked from Xilinx/open-nic-shell

    AMD OpenNIC Shell includes the HDL source files

    SystemVerilog

  6. sancar17/hls1 sancar17/hls1 Public

    C++