rv32icoredef.sv

// Generated by SandPiper(TM) 1.14-2022/10/10-beta-Pro from Redwood EDA, LLC.
// (Installed here: /usr/local/mono/sandpiper/distro.)
// Redwood EDA, LLC does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality.


// For silencing unused signal messages.
`define BOGUS_USE(ignore)


genvar dmem, imem, xreg;


//
// Signals declared top-level.
//

// For |cpu$br_tgt_pc.
logic [31:0] CPU_br_tgt_pc_a2,
             CPU_br_tgt_pc_a3;

// For |cpu$dec_bits.
logic [10:0] CPU_dec_bits_a2;

// For |cpu$dmem_addr.
logic [3:0] CPU_dmem_addr_a4;

// For |cpu$dmem_rd_data.
logic [31:0] CPU_dmem_rd_data_a4,
             CPU_dmem_rd_data_a5;

// For |cpu$dmem_rd_en.
logic CPU_dmem_rd_en_a4;

// For |cpu$dmem_wr_data.
logic [31:0] CPU_dmem_wr_data_a4;

// For |cpu$dmem_wr_en.
logic CPU_dmem_wr_en_a4;

// For |cpu$dummy.
logic [0:0] CPU_dummy_a0;

// For |cpu$funct3.
logic [2:0] CPU_funct3_a1,
            CPU_funct3_a2;

// For |cpu$funct3_valid.
logic CPU_funct3_valid_a1;

// For |cpu$funct7.
logic [6:0] CPU_funct7_a1;
logic [5:5] CPU_funct7_a2;

// For |cpu$funct7_valid.
logic CPU_funct7_valid_a1;

// For |cpu$imem_rd_addr.
logic [4-1:0] CPU_imem_rd_addr_a1,
              CPU_imem_rd_addr_a2,
              CPU_imem_rd_addr_a3,
              CPU_imem_rd_addr_a4,
              CPU_imem_rd_addr_a5;

// For |cpu$imem_rd_data.
logic [31:0] CPU_imem_rd_data_a1;

// For |cpu$imem_rd_en.
logic CPU_imem_rd_en_a1,
      CPU_imem_rd_en_a2,
      CPU_imem_rd_en_a3,
      CPU_imem_rd_en_a4,
      CPU_imem_rd_en_a5;

// For |cpu$imm.
logic [31:0] CPU_imm_a1,
             CPU_imm_a2,
             CPU_imm_a3,
             CPU_imm_a4,
             CPU_imm_a5;

// For |cpu$inc_pc.
logic [31:0] CPU_inc_pc_a1,
             CPU_inc_pc_a2,
             CPU_inc_pc_a3;

// For |cpu$instr.
logic [31:0] CPU_instr_a1;

// For |cpu$is_add.
logic CPU_is_add_a2,
      CPU_is_add_a3,
      CPU_is_add_a4,
      CPU_is_add_a5;

// For |cpu$is_addi.
logic CPU_is_addi_a2,
      CPU_is_addi_a3,
      CPU_is_addi_a4,
      CPU_is_addi_a5;

// For |cpu$is_and.
logic CPU_is_and_a2,
      CPU_is_and_a3,
      CPU_is_and_a4,
      CPU_is_and_a5;

// For |cpu$is_andi.
logic CPU_is_andi_a2,
      CPU_is_andi_a3,
      CPU_is_andi_a4,
      CPU_is_andi_a5;

// For |cpu$is_auipc.
logic CPU_is_auipc_a2,
      CPU_is_auipc_a3,
      CPU_is_auipc_a4,
      CPU_is_auipc_a5;

// For |cpu$is_b_instr.
logic CPU_is_b_instr_a1;

// For |cpu$is_beq.
logic CPU_is_beq_a2,
      CPU_is_beq_a3,
      CPU_is_beq_a4,
      CPU_is_beq_a5;

// For |cpu$is_bge.
logic CPU_is_bge_a2,
      CPU_is_bge_a3,
      CPU_is_bge_a4,
      CPU_is_bge_a5;

// For |cpu$is_bgeu.
logic CPU_is_bgeu_a2,
      CPU_is_bgeu_a3,
      CPU_is_bgeu_a4,
      CPU_is_bgeu_a5;

// For |cpu$is_blt.
logic CPU_is_blt_a2,
      CPU_is_blt_a3,
      CPU_is_blt_a4,
      CPU_is_blt_a5;

// For |cpu$is_bltu.
logic CPU_is_bltu_a2,
      CPU_is_bltu_a3,
      CPU_is_bltu_a4,
      CPU_is_bltu_a5;

// For |cpu$is_bne.
logic CPU_is_bne_a2,
      CPU_is_bne_a3,
      CPU_is_bne_a4,
      CPU_is_bne_a5;

// For |cpu$is_csrrc.
logic CPU_is_csrrc_a0,
      CPU_is_csrrc_a1,
      CPU_is_csrrc_a2,
      CPU_is_csrrc_a3,
      CPU_is_csrrc_a4,
      CPU_is_csrrc_a5;

// For |cpu$is_csrrci.
logic CPU_is_csrrci_a0,
      CPU_is_csrrci_a1,
      CPU_is_csrrci_a2,
      CPU_is_csrrci_a3,
      CPU_is_csrrci_a4,
      CPU_is_csrrci_a5;

// For |cpu$is_csrrs.
logic CPU_is_csrrs_a0,
      CPU_is_csrrs_a1,
      CPU_is_csrrs_a2,
      CPU_is_csrrs_a3,
      CPU_is_csrrs_a4,
      CPU_is_csrrs_a5;

// For |cpu$is_csrrsi.
logic CPU_is_csrrsi_a0,
      CPU_is_csrrsi_a1,
      CPU_is_csrrsi_a2,
      CPU_is_csrrsi_a3,
      CPU_is_csrrsi_a4,
      CPU_is_csrrsi_a5;

// For |cpu$is_csrrw.
logic CPU_is_csrrw_a0,
      CPU_is_csrrw_a1,
      CPU_is_csrrw_a2,
      CPU_is_csrrw_a3,
      CPU_is_csrrw_a4,
      CPU_is_csrrw_a5;

// For |cpu$is_csrrwi.
logic CPU_is_csrrwi_a0,
      CPU_is_csrrwi_a1,
      CPU_is_csrrwi_a2,
      CPU_is_csrrwi_a3,
      CPU_is_csrrwi_a4,
      CPU_is_csrrwi_a5;

// For |cpu$is_i_instr.
logic CPU_is_i_instr_a1;

// For |cpu$is_j_instr.
logic CPU_is_j_instr_a1;

// For |cpu$is_jal.
logic CPU_is_jal_a2,
      CPU_is_jal_a3,
      CPU_is_jal_a4,
      CPU_is_jal_a5;

// For |cpu$is_jalb.
logic CPU_is_jalb_a2,
      CPU_is_jalb_a3,
      CPU_is_jalb_a4,
      CPU_is_jalb_a5;

// For |cpu$is_jalr.
logic CPU_is_jalr_a0,
      CPU_is_jalr_a1,
      CPU_is_jalr_a2,
      CPU_is_jalr_a3,
      CPU_is_jalr_a4,
      CPU_is_jalr_a5;

// For |cpu$is_jump.
logic CPU_is_jump_a3;

// For |cpu$is_lb.
logic CPU_is_lb_a2,
      CPU_is_lb_a3,
      CPU_is_lb_a4,
      CPU_is_lb_a5;

// For |cpu$is_lbu.
logic CPU_is_lbu_a2,
      CPU_is_lbu_a3,
      CPU_is_lbu_a4,
      CPU_is_lbu_a5;

// For |cpu$is_lh.
logic CPU_is_lh_a2,
      CPU_is_lh_a3,
      CPU_is_lh_a4,
      CPU_is_lh_a5;

// For |cpu$is_lhu.
logic CPU_is_lhu_a2,
      CPU_is_lhu_a3,
      CPU_is_lhu_a4,
      CPU_is_lhu_a5;

// For |cpu$is_load.
logic CPU_is_load_a2,
      CPU_is_load_a3,
      CPU_is_load_a4,
      CPU_is_load_a5;

// For |cpu$is_lui.
logic CPU_is_lui_a2,
      CPU_is_lui_a3,
      CPU_is_lui_a4,
      CPU_is_lui_a5;

// For |cpu$is_lw.
logic CPU_is_lw_a2,
      CPU_is_lw_a3,
      CPU_is_lw_a4,
      CPU_is_lw_a5;

// For |cpu$is_or.
logic CPU_is_or_a2,
      CPU_is_or_a3,
      CPU_is_or_a4,
      CPU_is_or_a5;

// For |cpu$is_ori.
logic CPU_is_ori_a2,
      CPU_is_ori_a3,
      CPU_is_ori_a4,
      CPU_is_ori_a5;

// For |cpu$is_r_instr.
logic CPU_is_r_instr_a1;

// For |cpu$is_s_instr.
logic CPU_is_s_instr_a1,
      CPU_is_s_instr_a2,
      CPU_is_s_instr_a3,
      CPU_is_s_instr_a4;

// For |cpu$is_sb.
logic CPU_is_sb_a2,
      CPU_is_sb_a3,
      CPU_is_sb_a4,
      CPU_is_sb_a5;

// For |cpu$is_sh.
logic CPU_is_sh_a2,
      CPU_is_sh_a3,
      CPU_is_sh_a4,
      CPU_is_sh_a5;

// For |cpu$is_sll.
logic CPU_is_sll_a2,
      CPU_is_sll_a3,
      CPU_is_sll_a4,
      CPU_is_sll_a5;

// For |cpu$is_slli.
logic CPU_is_slli_a2,
      CPU_is_slli_a3,
      CPU_is_slli_a4,
      CPU_is_slli_a5;

// For |cpu$is_slt.
logic CPU_is_slt_a2,
      CPU_is_slt_a3,
      CPU_is_slt_a4,
      CPU_is_slt_a5;

// For |cpu$is_slti.
logic CPU_is_slti_a2,
      CPU_is_slti_a3,
      CPU_is_slti_a4,
      CPU_is_slti_a5;

// For |cpu$is_sltiu.
logic CPU_is_sltiu_a2,
      CPU_is_sltiu_a3,
      CPU_is_sltiu_a4,
      CPU_is_sltiu_a5;

// For |cpu$is_sltu.
logic CPU_is_sltu_a2,
      CPU_is_sltu_a3,
      CPU_is_sltu_a4,
      CPU_is_sltu_a5;

// For |cpu$is_sra.
logic CPU_is_sra_a2,
      CPU_is_sra_a3,
      CPU_is_sra_a4,
      CPU_is_sra_a5;

// For |cpu$is_srai.
logic CPU_is_srai_a0,
      CPU_is_srai_a1,
      CPU_is_srai_a2,
      CPU_is_srai_a3,
      CPU_is_srai_a4,
      CPU_is_srai_a5;

// For |cpu$is_sral.
logic CPU_is_sral_a2,
      CPU_is_sral_a3,
      CPU_is_sral_a4,
      CPU_is_sral_a5;

// For |cpu$is_srl.
logic CPU_is_srl_a2,
      CPU_is_srl_a3,
      CPU_is_srl_a4,
      CPU_is_srl_a5;

// For |cpu$is_srli.
logic CPU_is_srli_a2,
      CPU_is_srli_a3,
      CPU_is_srli_a4,
      CPU_is_srli_a5;

// For |cpu$is_store.
logic CPU_is_store_a0,
      CPU_is_store_a1,
      CPU_is_store_a2,
      CPU_is_store_a3,
      CPU_is_store_a4,
      CPU_is_store_a5;

// For |cpu$is_sub.
logic CPU_is_sub_a2,
      CPU_is_sub_a3,
      CPU_is_sub_a4,
      CPU_is_sub_a5;

// For |cpu$is_sw.
logic CPU_is_sw_a2,
      CPU_is_sw_a3,
      CPU_is_sw_a4,
      CPU_is_sw_a5;

// For |cpu$is_u_instr.
logic CPU_is_u_instr_a1;

// For |cpu$is_xor.
logic CPU_is_xor_a2,
      CPU_is_xor_a3,
      CPU_is_xor_a4,
      CPU_is_xor_a5;

// For |cpu$is_xori.
logic CPU_is_xori_a2,
      CPU_is_xori_a3,
      CPU_is_xori_a4,
      CPU_is_xori_a5;

// For |cpu$jalr_tgt_pc.
logic CPU_jalr_tgt_pc_a2,
      CPU_jalr_tgt_pc_a3;

// For |cpu$ld_data.
logic [31:0] CPU_ld_data_a5;

// For |cpu$opcode.
logic [6:0] CPU_opcode_a1,
            CPU_opcode_a2;

// For |cpu$pc.
logic [31:0] CPU_pc_a0,
             CPU_pc_a1,
             CPU_pc_a2,
             CPU_pc_a3,
             CPU_pc_a4,
             CPU_pc_a5;

// For |cpu$rd.
logic [4:0] CPU_rd_a1,
            CPU_rd_a2,
            CPU_rd_a3,
            CPU_rd_a4,
            CPU_rd_a5;

// For |cpu$rd_valid.
logic CPU_rd_valid_a1,
      CPU_rd_valid_a2,
      CPU_rd_valid_a3,
      CPU_rd_valid_a4,
      CPU_rd_valid_a5;

// For |cpu$reset.
logic CPU_reset_a0,
      CPU_reset_a1,
      CPU_reset_a2,
      CPU_reset_a3,
      CPU_reset_a4;

// For |cpu$result.
logic [31:0] CPU_result_a3,
             CPU_result_a4,
             CPU_result_a5;

// For |cpu$rf_rd_data1.
logic [31:0] CPU_rf_rd_data1_a2;

// For |cpu$rf_rd_data2.
logic [31:0] CPU_rf_rd_data2_a2;

// For |cpu$rf_rd_en1.
logic CPU_rf_rd_en1_a2;

// For |cpu$rf_rd_en2.
logic CPU_rf_rd_en2_a2;

// For |cpu$rf_rd_index1.
logic [4:0] CPU_rf_rd_index1_a2;

// For |cpu$rf_rd_index2.
logic [4:0] CPU_rf_rd_index2_a2;

// For |cpu$rf_wr_data.
logic [31:0] CPU_rf_wr_data_a3;

// For |cpu$rf_wr_en.
logic CPU_rf_wr_en_a3;

// For |cpu$rf_wr_index.
logic [4:0] CPU_rf_wr_index_a3;

// For |cpu$rs1.
logic [4:0] CPU_rs1_a1,
            CPU_rs1_a2,
            CPU_rs1_a3,
            CPU_rs1_a4,
            CPU_rs1_a5;

// For |cpu$rs1_valid.
logic CPU_rs1_valid_a1,
      CPU_rs1_valid_a2,
      CPU_rs1_valid_a3,
      CPU_rs1_valid_a4,
      CPU_rs1_valid_a5;

// For |cpu$rs2.
logic [4:0] CPU_rs2_a1,
            CPU_rs2_a2,
            CPU_rs2_a3,
            CPU_rs2_a4,
            CPU_rs2_a5;

// For |cpu$rs2_valid.
logic CPU_rs2_valid_a1,
      CPU_rs2_valid_a2,
      CPU_rs2_valid_a3,
      CPU_rs2_valid_a4,
      CPU_rs2_valid_a5;

// For |cpu$sltiu_rslt.
logic [31:0] CPU_sltiu_rslt_a3;

// For |cpu$sltu_rslt.
logic [31:0] CPU_sltu_rslt_a3;

// For |cpu$src1_value.
logic [31:0] CPU_src1_value_a2,
             CPU_src1_value_a3,
             CPU_src1_value_a4,
             CPU_src1_value_a5;

// For |cpu$src2_value.
logic [31:0] CPU_src2_value_a2,
             CPU_src2_value_a3,
             CPU_src2_value_a4,
             CPU_src2_value_a5;

// For |cpu$start.
logic CPU_start_a0,
      CPU_start_a1,
      CPU_start_a2,
      CPU_start_a3,
      CPU_start_a4,
      CPU_start_a5;

// For |cpu$taken_br.
logic CPU_taken_br_a3;

// For |cpu$valid.
logic CPU_valid_a3,
      CPU_valid_a4,
      CPU_valid_a5;

// For |cpu$valid_jump.
logic CPU_valid_jump_a3;

// For |cpu$valid_load.
logic CPU_valid_load_a3,
      CPU_valid_load_a4,
      CPU_valid_load_a5;

// For |cpu$valid_taken_br.
logic CPU_valid_taken_br_a3,
      CPU_valid_taken_br_a4,
      CPU_valid_taken_br_a5;

// For |cpu/dmem$value.
logic [31:0] CPU_Dmem_value_a4 [15:0],
             CPU_Dmem_value_a5 [15:0];

// For |cpu/imem$instr.
logic [31:0] CPU_Imem_instr_a1 [9:0];

// For |cpu/xreg$value.
logic [31:0] CPU_Xreg_value_a3 [31:0],
             CPU_Xreg_value_a4 [31:0],
             CPU_Xreg_value_a5 [31:0],
             CPU_Xreg_value_a6 [31:0],
             CPU_Xreg_value_a7 [31:0],
             CPU_Xreg_value_a8 [31:0],
             CPU_Xreg_value_a9 [31:0],
             CPU_Xreg_value_a10 [31:0];

// For |cpuviz$imm.
logic [31:0] CPUVIZ_imm_a5;

// For |cpuviz$is_add.
logic CPUVIZ_is_add_a5;

// For |cpuviz$is_addi.
logic CPUVIZ_is_addi_a5;

// For |cpuviz$is_and.
logic CPUVIZ_is_and_a5;

// For |cpuviz$is_andi.
logic CPUVIZ_is_andi_a5;

// For |cpuviz$is_auipc.
logic CPUVIZ_is_auipc_a5;

// For |cpuviz$is_beq.
logic CPUVIZ_is_beq_a5;

// For |cpuviz$is_bge.
logic CPUVIZ_is_bge_a5;

// For |cpuviz$is_bgeu.
logic CPUVIZ_is_bgeu_a5;

// For |cpuviz$is_blt.
logic CPUVIZ_is_blt_a5;

// For |cpuviz$is_bltu.
logic CPUVIZ_is_bltu_a5;

// For |cpuviz$is_bne.
logic CPUVIZ_is_bne_a5;

// For |cpuviz$is_csrrc.
logic CPUVIZ_is_csrrc_a5;

// For |cpuviz$is_csrrci.
logic CPUVIZ_is_csrrci_a5;

// For |cpuviz$is_csrrs.
logic CPUVIZ_is_csrrs_a5;

// For |cpuviz$is_csrrsi.
logic CPUVIZ_is_csrrsi_a5;

// For |cpuviz$is_csrrw.
logic CPUVIZ_is_csrrw_a5;

// For |cpuviz$is_csrrwi.
logic CPUVIZ_is_csrrwi_a5;

// For |cpuviz$is_jal.
logic CPUVIZ_is_jal_a5;

// For |cpuviz$is_jalr.
logic CPUVIZ_is_jalr_a5;

// For |cpuviz$is_lb.
logic CPUVIZ_is_lb_a5;

// For |cpuviz$is_lbu.
logic CPUVIZ_is_lbu_a5;

// For |cpuviz$is_lh.
logic CPUVIZ_is_lh_a5;

// For |cpuviz$is_lhu.
logic CPUVIZ_is_lhu_a5;

// For |cpuviz$is_load.
logic CPUVIZ_is_load_a5;

// For |cpuviz$is_lui.
logic CPUVIZ_is_lui_a5;

// For |cpuviz$is_lw.
logic CPUVIZ_is_lw_a5;

// For |cpuviz$is_or.
logic CPUVIZ_is_or_a5;

// For |cpuviz$is_ori.
logic CPUVIZ_is_ori_a5;

// For |cpuviz$is_sb.
logic CPUVIZ_is_sb_a5;

// For |cpuviz$is_sh.
logic CPUVIZ_is_sh_a5;

// For |cpuviz$is_sll.
logic CPUVIZ_is_sll_a5;

// For |cpuviz$is_slli.
logic CPUVIZ_is_slli_a5;

// For |cpuviz$is_slt.
logic CPUVIZ_is_slt_a5;

// For |cpuviz$is_slti.
logic CPUVIZ_is_slti_a5;

// For |cpuviz$is_sltiu.
logic CPUVIZ_is_sltiu_a5;

// For |cpuviz$is_sltu.
logic CPUVIZ_is_sltu_a5;

// For |cpuviz$is_sra.
logic CPUVIZ_is_sra_a5;

// For |cpuviz$is_srai.
logic CPUVIZ_is_srai_a5;

// For |cpuviz$is_srl.
logic CPUVIZ_is_srl_a5;

// For |cpuviz$is_srli.
logic CPUVIZ_is_srli_a5;

// For |cpuviz$is_store.
logic CPUVIZ_is_store_a5;

// For |cpuviz$is_sub.
logic CPUVIZ_is_sub_a5;

// For |cpuviz$is_sw.
logic CPUVIZ_is_sw_a5;

// For |cpuviz$is_xor.
logic CPUVIZ_is_xor_a5;

// For |cpuviz$is_xori.
logic CPUVIZ_is_xori_a5;

// For |cpuviz$mnemonic.
logic [10*8-1:0] CPUVIZ_mnemonic_a5;

// For |cpuviz$pc.
logic [31:0] CPUVIZ_pc_a5;

// For |cpuviz$rd.
logic [4:0] CPUVIZ_rd_a5;

// For |cpuviz$rd_valid.
logic CPUVIZ_rd_valid_a5;

// For |cpuviz$result.
logic [31:0] CPUVIZ_result_a5;

// For |cpuviz$rs1.
logic [4:0] CPUVIZ_rs1_a5;

// For |cpuviz$rs1_valid.
logic CPUVIZ_rs1_valid_a5;

// For |cpuviz$rs2.
logic [4:0] CPUVIZ_rs2_a5;

// For |cpuviz$rs2_valid.
logic CPUVIZ_rs2_valid_a5;

// For |cpuviz$src1_value.
logic [31:0] CPUVIZ_src1_value_a5;

// For |cpuviz$src2_value.
logic [31:0] CPUVIZ_src2_value_a5;

// For |cpuviz$valid.
logic CPUVIZ_valid_a5;

// For |cpuviz/defaults$dummy.
logic [0:0] CPUVIZ_Defaults_dummy_a0;

// For |cpuviz/defaults$imem_rd_addr.
logic [4-1:0] CPUVIZ_Defaults_imem_rd_addr_a0;

// For |cpuviz/defaults$imem_rd_en.
logic CPUVIZ_Defaults_imem_rd_en_a0;

// For |cpuviz/defaults$imm.
logic [31:0] CPUVIZ_Defaults_imm_a0;

// For |cpuviz/defaults$is_add.
logic CPUVIZ_Defaults_is_add_a0;

// For |cpuviz/defaults$is_addi.
logic CPUVIZ_Defaults_is_addi_a0;

// For |cpuviz/defaults$is_and.
logic CPUVIZ_Defaults_is_and_a0;

// For |cpuviz/defaults$is_andi.
logic CPUVIZ_Defaults_is_andi_a0;

// For |cpuviz/defaults$is_auipc.
logic CPUVIZ_Defaults_is_auipc_a0;

// For |cpuviz/defaults$is_beq.
logic CPUVIZ_Defaults_is_beq_a0;

// For |cpuviz/defaults$is_bge.
logic CPUVIZ_Defaults_is_bge_a0;

// For |cpuviz/defaults$is_bgeu.
logic CPUVIZ_Defaults_is_bgeu_a0;

// For |cpuviz/defaults$is_blt.
logic CPUVIZ_Defaults_is_blt_a0;

// For |cpuviz/defaults$is_bltu.
logic CPUVIZ_Defaults_is_bltu_a0;

// For |cpuviz/defaults$is_bne.
logic CPUVIZ_Defaults_is_bne_a0;

// For |cpuviz/defaults$is_csrrc.
logic CPUVIZ_Defaults_is_csrrc_a0;

// For |cpuviz/defaults$is_csrrci.
logic CPUVIZ_Defaults_is_csrrci_a0;

// For |cpuviz/defaults$is_csrrs.
logic CPUVIZ_Defaults_is_csrrs_a0;

// For |cpuviz/defaults$is_csrrsi.
logic CPUVIZ_Defaults_is_csrrsi_a0;

// For |cpuviz/defaults$is_csrrw.
logic CPUVIZ_Defaults_is_csrrw_a0;

// For |cpuviz/defaults$is_csrrwi.
logic CPUVIZ_Defaults_is_csrrwi_a0;

// For |cpuviz/defaults$is_jal.
logic CPUVIZ_Defaults_is_jal_a0;

// For |cpuviz/defaults$is_jalr.
logic CPUVIZ_Defaults_is_jalr_a0;

// For |cpuviz/defaults$is_lb.
logic CPUVIZ_Defaults_is_lb_a0;

// For |cpuviz/defaults$is_lbu.
logic CPUVIZ_Defaults_is_lbu_a0;

// For |cpuviz/defaults$is_lh.
logic CPUVIZ_Defaults_is_lh_a0;

// For |cpuviz/defaults$is_lhu.
logic CPUVIZ_Defaults_is_lhu_a0;

// For |cpuviz/defaults$is_load.
logic CPUVIZ_Defaults_is_load_a0;

// For |cpuviz/defaults$is_lui.
logic CPUVIZ_Defaults_is_lui_a0;

// For |cpuviz/defaults$is_lw.
logic CPUVIZ_Defaults_is_lw_a0;

// For |cpuviz/defaults$is_or.
logic CPUVIZ_Defaults_is_or_a0;

// For |cpuviz/defaults$is_ori.
logic CPUVIZ_Defaults_is_ori_a0;

// For |cpuviz/defaults$is_s_instr.
logic CPUVIZ_Defaults_is_s_instr_a0;

// For |cpuviz/defaults$is_sb.
logic CPUVIZ_Defaults_is_sb_a0;

// For |cpuviz/defaults$is_sh.
logic CPUVIZ_Defaults_is_sh_a0;

// For |cpuviz/defaults$is_sll.
logic CPUVIZ_Defaults_is_sll_a0;

// For |cpuviz/defaults$is_slli.
logic CPUVIZ_Defaults_is_slli_a0;

// For |cpuviz/defaults$is_slt.
logic CPUVIZ_Defaults_is_slt_a0;

// For |cpuviz/defaults$is_slti.
logic CPUVIZ_Defaults_is_slti_a0;

// For |cpuviz/defaults$is_sltiu.
logic CPUVIZ_Defaults_is_sltiu_a0;

// For |cpuviz/defaults$is_sltu.
logic CPUVIZ_Defaults_is_sltu_a0;

// For |cpuviz/defaults$is_sra.
logic CPUVIZ_Defaults_is_sra_a0;

// For |cpuviz/defaults$is_srai.
logic CPUVIZ_Defaults_is_srai_a0;

// For |cpuviz/defaults$is_srl.
logic CPUVIZ_Defaults_is_srl_a0;

// For |cpuviz/defaults$is_srli.
logic CPUVIZ_Defaults_is_srli_a0;

// For |cpuviz/defaults$is_store.
logic CPUVIZ_Defaults_is_store_a0;

// For |cpuviz/defaults$is_sub.
logic CPUVIZ_Defaults_is_sub_a0;

// For |cpuviz/defaults$is_sw.
logic CPUVIZ_Defaults_is_sw_a0;

// For |cpuviz/defaults$is_xor.
logic CPUVIZ_Defaults_is_xor_a0;

// For |cpuviz/defaults$is_xori.
logic CPUVIZ_Defaults_is_xori_a0;

// For |cpuviz/defaults$ld_data.
logic [31:0] CPUVIZ_Defaults_ld_data_a0;

// For |cpuviz/defaults$pc.
logic [31:0] CPUVIZ_Defaults_pc_a0;

// For |cpuviz/defaults$rd.
logic [4:0] CPUVIZ_Defaults_rd_a0;

// For |cpuviz/defaults$rd_valid.
logic CPUVIZ_Defaults_rd_valid_a0;

// For |cpuviz/defaults$result.
logic [31:0] CPUVIZ_Defaults_result_a0;

// For |cpuviz/defaults$rf_rd_en1.
logic CPUVIZ_Defaults_rf_rd_en1_a0;

// For |cpuviz/defaults$rf_rd_en2.
logic CPUVIZ_Defaults_rf_rd_en2_a0;

// For |cpuviz/defaults$rf_rd_index1.
logic [4:0] CPUVIZ_Defaults_rf_rd_index1_a0;

// For |cpuviz/defaults$rf_rd_index2.
logic [4:0] CPUVIZ_Defaults_rf_rd_index2_a0;

// For |cpuviz/defaults$rf_wr_data.
logic [31:0] CPUVIZ_Defaults_rf_wr_data_a0;

// For |cpuviz/defaults$rf_wr_en.
logic CPUVIZ_Defaults_rf_wr_en_a0;

// For |cpuviz/defaults$rf_wr_index.
logic [4:0] CPUVIZ_Defaults_rf_wr_index_a0;

// For |cpuviz/defaults$rs1.
logic [4:0] CPUVIZ_Defaults_rs1_a0;

// For |cpuviz/defaults$rs1_valid.
logic CPUVIZ_Defaults_rs1_valid_a0;

// For |cpuviz/defaults$rs2.
logic [4:0] CPUVIZ_Defaults_rs2_a0;

// For |cpuviz/defaults$rs2_valid.
logic CPUVIZ_Defaults_rs2_valid_a0;

// For |cpuviz/defaults$src1_value.
logic [31:0] CPUVIZ_Defaults_src1_value_a0;

// For |cpuviz/defaults$src2_value.
logic [31:0] CPUVIZ_Defaults_src2_value_a0;

// For |cpuviz/defaults$valid.
logic CPUVIZ_Defaults_valid_a0;


//
// Scope: |cpu
//

// Clock signals.
logic clkP_CPU_dmem_rd_en_a5 ;
logic clkP_CPU_funct3_valid_a2 ;
logic clkP_CPU_funct7_valid_a2 ;
logic clkP_CPU_rd_valid_a2 ;
logic clkP_CPU_rd_valid_a3 ;
logic clkP_CPU_rd_valid_a4 ;
logic clkP_CPU_rd_valid_a5 ;
logic clkP_CPU_rs1_valid_a2 ;
logic clkP_CPU_rs1_valid_a3 ;
logic clkP_CPU_rs1_valid_a4 ;
logic clkP_CPU_rs1_valid_a5 ;
logic clkP_CPU_rs2_valid_a2 ;
logic clkP_CPU_rs2_valid_a3 ;
logic clkP_CPU_rs2_valid_a4 ;
logic clkP_CPU_rs2_valid_a5 ;



   //
   // Scope: |cpu
   //

      // Staging of $br_tgt_pc.
      always_ff @(posedge clk) CPU_br_tgt_pc_a3[31:0] <= CPU_br_tgt_pc_a2[31:0];

      // Staging of $dmem_rd_data.
      always_ff @(posedge clkP_CPU_dmem_rd_en_a5) CPU_dmem_rd_data_a5[31:0] <= CPU_dmem_rd_data_a4[31:0];

      // Staging of $funct3.
      always_ff @(posedge clkP_CPU_funct3_valid_a2) CPU_funct3_a2[2:0] <= CPU_funct3_a1[2:0];

      // Staging of $funct7.
      always_ff @(posedge clkP_CPU_funct7_valid_a2) CPU_funct7_a2[5] <= CPU_funct7_a1[5];

      // Staging of $imem_rd_addr.
      always_ff @(posedge clk) CPU_imem_rd_addr_a2[4-1:0] <= CPU_imem_rd_addr_a1[4-1:0];
      always_ff @(posedge clk) CPU_imem_rd_addr_a3[4-1:0] <= CPU_imem_rd_addr_a2[4-1:0];
      always_ff @(posedge clk) CPU_imem_rd_addr_a4[4-1:0] <= CPU_imem_rd_addr_a3[4-1:0];
      always_ff @(posedge clk) CPU_imem_rd_addr_a5[4-1:0] <= CPU_imem_rd_addr_a4[4-1:0];

      // Staging of $imem_rd_en.
      always_ff @(posedge clk) CPU_imem_rd_en_a2 <= CPU_imem_rd_en_a1;
      always_ff @(posedge clk) CPU_imem_rd_en_a3 <= CPU_imem_rd_en_a2;
      always_ff @(posedge clk) CPU_imem_rd_en_a4 <= CPU_imem_rd_en_a3;
      always_ff @(posedge clk) CPU_imem_rd_en_a5 <= CPU_imem_rd_en_a4;

      // Staging of $imm.
      always_ff @(posedge clk) CPU_imm_a2[31:0] <= CPU_imm_a1[31:0];
      always_ff @(posedge clk) CPU_imm_a3[31:0] <= CPU_imm_a2[31:0];
      always_ff @(posedge clk) CPU_imm_a4[31:0] <= CPU_imm_a3[31:0];
      always_ff @(posedge clk) CPU_imm_a5[31:0] <= CPU_imm_a4[31:0];

      // Staging of $inc_pc.
      always_ff @(posedge clk) CPU_inc_pc_a2[31:0] <= CPU_inc_pc_a1[31:0];
      always_ff @(posedge clk) CPU_inc_pc_a3[31:0] <= CPU_inc_pc_a2[31:0];

      // Staging of $is_add.
      always_ff @(posedge clk) CPU_is_add_a3 <= CPU_is_add_a2;
      always_ff @(posedge clk) CPU_is_add_a4 <= CPU_is_add_a3;
      always_ff @(posedge clk) CPU_is_add_a5 <= CPU_is_add_a4;

      // Staging of $is_addi.
      always_ff @(posedge clk) CPU_is_addi_a3 <= CPU_is_addi_a2;
      always_ff @(posedge clk) CPU_is_addi_a4 <= CPU_is_addi_a3;
      always_ff @(posedge clk) CPU_is_addi_a5 <= CPU_is_addi_a4;

      // Staging of $is_and.
      always_ff @(posedge clk) CPU_is_and_a3 <= CPU_is_and_a2;
      always_ff @(posedge clk) CPU_is_and_a4 <= CPU_is_and_a3;
      always_ff @(posedge clk) CPU_is_and_a5 <= CPU_is_and_a4;

      // Staging of $is_andi.
      always_ff @(posedge clk) CPU_is_andi_a3 <= CPU_is_andi_a2;
      always_ff @(posedge clk) CPU_is_andi_a4 <= CPU_is_andi_a3;
      always_ff @(posedge clk) CPU_is_andi_a5 <= CPU_is_andi_a4;

      // Staging of $is_auipc.
      always_ff @(posedge clk) CPU_is_auipc_a3 <= CPU_is_auipc_a2;
      always_ff @(posedge clk) CPU_is_auipc_a4 <= CPU_is_auipc_a3;
      always_ff @(posedge clk) CPU_is_auipc_a5 <= CPU_is_auipc_a4;

      // Staging of $is_beq.
      always_ff @(posedge clk) CPU_is_beq_a3 <= CPU_is_beq_a2;
      always_ff @(posedge clk) CPU_is_beq_a4 <= CPU_is_beq_a3;
      always_ff @(posedge clk) CPU_is_beq_a5 <= CPU_is_beq_a4;

      // Staging of $is_bge.
      always_ff @(posedge clk) CPU_is_bge_a3 <= CPU_is_bge_a2;
      always_ff @(posedge clk) CPU_is_bge_a4 <= CPU_is_bge_a3;
      always_ff @(posedge clk) CPU_is_bge_a5 <= CPU_is_bge_a4;

      // Staging of $is_bgeu.
      always_ff @(posedge clk) CPU_is_bgeu_a3 <= CPU_is_bgeu_a2;
      always_ff @(posedge clk) CPU_is_bgeu_a4 <= CPU_is_bgeu_a3;
      always_ff @(posedge clk) CPU_is_bgeu_a5 <= CPU_is_bgeu_a4;

      // Staging of $is_blt.
      always_ff @(posedge clk) CPU_is_blt_a3 <= CPU_is_blt_a2;
      always_ff @(posedge clk) CPU_is_blt_a4 <= CPU_is_blt_a3;
      always_ff @(posedge clk) CPU_is_blt_a5 <= CPU_is_blt_a4;

      // Staging of $is_bltu.
      always_ff @(posedge clk) CPU_is_bltu_a3 <= CPU_is_bltu_a2;
      always_ff @(posedge clk) CPU_is_bltu_a4 <= CPU_is_bltu_a3;
      always_ff @(posedge clk) CPU_is_bltu_a5 <= CPU_is_bltu_a4;

      // Staging of $is_bne.
      always_ff @(posedge clk) CPU_is_bne_a3 <= CPU_is_bne_a2;
      always_ff @(posedge clk) CPU_is_bne_a4 <= CPU_is_bne_a3;
      always_ff @(posedge clk) CPU_is_bne_a5 <= CPU_is_bne_a4;

      // Staging of $is_csrrc.
      always_ff @(posedge clk) CPU_is_csrrc_a1 <= CPU_is_csrrc_a0;
      always_ff @(posedge clk) CPU_is_csrrc_a2 <= CPU_is_csrrc_a1;
      always_ff @(posedge clk) CPU_is_csrrc_a3 <= CPU_is_csrrc_a2;
      always_ff @(posedge clk) CPU_is_csrrc_a4 <= CPU_is_csrrc_a3;
      always_ff @(posedge clk) CPU_is_csrrc_a5 <= CPU_is_csrrc_a4;

      // Staging of $is_csrrci.
      always_ff @(posedge clk) CPU_is_csrrci_a1 <= CPU_is_csrrci_a0;
      always_ff @(posedge clk) CPU_is_csrrci_a2 <= CPU_is_csrrci_a1;
      always_ff @(posedge clk) CPU_is_csrrci_a3 <= CPU_is_csrrci_a2;
      always_ff @(posedge clk) CPU_is_csrrci_a4 <= CPU_is_csrrci_a3;
      always_ff @(posedge clk) CPU_is_csrrci_a5 <= CPU_is_csrrci_a4;

      // Staging of $is_csrrs.
      always_ff @(posedge clk) CPU_is_csrrs_a1 <= CPU_is_csrrs_a0;
      always_ff @(posedge clk) CPU_is_csrrs_a2 <= CPU_is_csrrs_a1;
      always_ff @(posedge clk) CPU_is_csrrs_a3 <= CPU_is_csrrs_a2;
      always_ff @(posedge clk) CPU_is_csrrs_a4 <= CPU_is_csrrs_a3;
      always_ff @(posedge clk) CPU_is_csrrs_a5 <= CPU_is_csrrs_a4;

      // Staging of $is_csrrsi.
      always_ff @(posedge clk) CPU_is_csrrsi_a1 <= CPU_is_csrrsi_a0;
      always_ff @(posedge clk) CPU_is_csrrsi_a2 <= CPU_is_csrrsi_a1;
      always_ff @(posedge clk) CPU_is_csrrsi_a3 <= CPU_is_csrrsi_a2;
      always_ff @(posedge clk) CPU_is_csrrsi_a4 <= CPU_is_csrrsi_a3;
      always_ff @(posedge clk) CPU_is_csrrsi_a5 <= CPU_is_csrrsi_a4;

      // Staging of $is_csrrw.
      always_ff @(posedge clk) CPU_is_csrrw_a1 <= CPU_is_csrrw_a0;
      always_ff @(posedge clk) CPU_is_csrrw_a2 <= CPU_is_csrrw_a1;
      always_ff @(posedge clk) CPU_is_csrrw_a3 <= CPU_is_csrrw_a2;
      always_ff @(posedge clk) CPU_is_csrrw_a4 <= CPU_is_csrrw_a3;
      always_ff @(posedge clk) CPU_is_csrrw_a5 <= CPU_is_csrrw_a4;

      // Staging of $is_csrrwi.
      always_ff @(posedge clk) CPU_is_csrrwi_a1 <= CPU_is_csrrwi_a0;
      always_ff @(posedge clk) CPU_is_csrrwi_a2 <= CPU_is_csrrwi_a1;
      always_ff @(posedge clk) CPU_is_csrrwi_a3 <= CPU_is_csrrwi_a2;
      always_ff @(posedge clk) CPU_is_csrrwi_a4 <= CPU_is_csrrwi_a3;
      always_ff @(posedge clk) CPU_is_csrrwi_a5 <= CPU_is_csrrwi_a4;

      // Staging of $is_jal.
      always_ff @(posedge clk) CPU_is_jal_a3 <= CPU_is_jal_a2;
      always_ff @(posedge clk) CPU_is_jal_a4 <= CPU_is_jal_a3;
      always_ff @(posedge clk) CPU_is_jal_a5 <= CPU_is_jal_a4;

      // Staging of $is_jalb.
      always_ff @(posedge clk) CPU_is_jalb_a3 <= CPU_is_jalb_a2;
      always_ff @(posedge clk) CPU_is_jalb_a4 <= CPU_is_jalb_a3;
      always_ff @(posedge clk) CPU_is_jalb_a5 <= CPU_is_jalb_a4;

      // Staging of $is_jalr.
      always_ff @(posedge clk) CPU_is_jalr_a1 <= CPU_is_jalr_a0;
      always_ff @(posedge clk) CPU_is_jalr_a2 <= CPU_is_jalr_a1;
      always_ff @(posedge clk) CPU_is_jalr_a3 <= CPU_is_jalr_a2;
      always_ff @(posedge clk) CPU_is_jalr_a4 <= CPU_is_jalr_a3;
      always_ff @(posedge clk) CPU_is_jalr_a5 <= CPU_is_jalr_a4;

      // Staging of $is_lb.
      always_ff @(posedge clk) CPU_is_lb_a3 <= CPU_is_lb_a2;
      always_ff @(posedge clk) CPU_is_lb_a4 <= CPU_is_lb_a3;
      always_ff @(posedge clk) CPU_is_lb_a5 <= CPU_is_lb_a4;

      // Staging of $is_lbu.
      always_ff @(posedge clk) CPU_is_lbu_a3 <= CPU_is_lbu_a2;
      always_ff @(posedge clk) CPU_is_lbu_a4 <= CPU_is_lbu_a3;
      always_ff @(posedge clk) CPU_is_lbu_a5 <= CPU_is_lbu_a4;

      // Staging of $is_lh.
      always_ff @(posedge clk) CPU_is_lh_a3 <= CPU_is_lh_a2;
      always_ff @(posedge clk) CPU_is_lh_a4 <= CPU_is_lh_a3;
      always_ff @(posedge clk) CPU_is_lh_a5 <= CPU_is_lh_a4;

      // Staging of $is_lhu.
      always_ff @(posedge clk) CPU_is_lhu_a3 <= CPU_is_lhu_a2;
      always_ff @(posedge clk) CPU_is_lhu_a4 <= CPU_is_lhu_a3;
      always_ff @(posedge clk) CPU_is_lhu_a5 <= CPU_is_lhu_a4;

      // Staging of $is_load.
      always_ff @(posedge clk) CPU_is_load_a3 <= CPU_is_load_a2;
      always_ff @(posedge clk) CPU_is_load_a4 <= CPU_is_load_a3;
      always_ff @(posedge clk) CPU_is_load_a5 <= CPU_is_load_a4;

      // Staging of $is_lui.
      always_ff @(posedge clk) CPU_is_lui_a3 <= CPU_is_lui_a2;
      always_ff @(posedge clk) CPU_is_lui_a4 <= CPU_is_lui_a3;
      always_ff @(posedge clk) CPU_is_lui_a5 <= CPU_is_lui_a4;

      // Staging of $is_lw.
      always_ff @(posedge clk) CPU_is_lw_a3 <= CPU_is_lw_a2;
      always_ff @(posedge clk) CPU_is_lw_a4 <= CPU_is_lw_a3;
      always_ff @(posedge clk) CPU_is_lw_a5 <= CPU_is_lw_a4;

      // Staging of $is_or.
      always_ff @(posedge clk) CPU_is_or_a3 <= CPU_is_or_a2;
      always_ff @(posedge clk) CPU_is_or_a4 <= CPU_is_or_a3;
      always_ff @(posedge clk) CPU_is_or_a5 <= CPU_is_or_a4;

      // Staging of $is_ori.
      always_ff @(posedge clk) CPU_is_ori_a3 <= CPU_is_ori_a2;
      always_ff @(posedge clk) CPU_is_ori_a4 <= CPU_is_ori_a3;
      always_ff @(posedge clk) CPU_is_ori_a5 <= CPU_is_ori_a4;

      // Staging of $is_s_instr.
      always_ff @(posedge clk) CPU_is_s_instr_a2 <= CPU_is_s_instr_a1;
      always_ff @(posedge clk) CPU_is_s_instr_a3 <= CPU_is_s_instr_a2;
      always_ff @(posedge clk) CPU_is_s_instr_a4 <= CPU_is_s_instr_a3;

      // Staging of $is_sb.
      always_ff @(posedge clk) CPU_is_sb_a3 <= CPU_is_sb_a2;
      always_ff @(posedge clk) CPU_is_sb_a4 <= CPU_is_sb_a3;
      always_ff @(posedge clk) CPU_is_sb_a5 <= CPU_is_sb_a4;

      // Staging of $is_sh.
      always_ff @(posedge clk) CPU_is_sh_a3 <= CPU_is_sh_a2;
      always_ff @(posedge clk) CPU_is_sh_a4 <= CPU_is_sh_a3;
      always_ff @(posedge clk) CPU_is_sh_a5 <= CPU_is_sh_a4;

      // Staging of $is_sll.
      always_ff @(posedge clk) CPU_is_sll_a3 <= CPU_is_sll_a2;
      always_ff @(posedge clk) CPU_is_sll_a4 <= CPU_is_sll_a3;
      always_ff @(posedge clk) CPU_is_sll_a5 <= CPU_is_sll_a4;

      // Staging of $is_slli.
      always_ff @(posedge clk) CPU_is_slli_a3 <= CPU_is_slli_a2;
      always_ff @(posedge clk) CPU_is_slli_a4 <= CPU_is_slli_a3;
      always_ff @(posedge clk) CPU_is_slli_a5 <= CPU_is_slli_a4;

      // Staging of $is_slt.
      always_ff @(posedge clk) CPU_is_slt_a3 <= CPU_is_slt_a2;
      always_ff @(posedge clk) CPU_is_slt_a4 <= CPU_is_slt_a3;
      always_ff @(posedge clk) CPU_is_slt_a5 <= CPU_is_slt_a4;

      // Staging of $is_slti.
      always_ff @(posedge clk) CPU_is_slti_a3 <= CPU_is_slti_a2;
      always_ff @(posedge clk) CPU_is_slti_a4 <= CPU_is_slti_a3;
      always_ff @(posedge clk) CPU_is_slti_a5 <= CPU_is_slti_a4;

      // Staging of $is_sltiu.
      always_ff @(posedge clk) CPU_is_sltiu_a3 <= CPU_is_sltiu_a2;
      always_ff @(posedge clk) CPU_is_sltiu_a4 <= CPU_is_sltiu_a3;
      always_ff @(posedge clk) CPU_is_sltiu_a5 <= CPU_is_sltiu_a4;

      // Staging of $is_sltu.
      always_ff @(posedge clk) CPU_is_sltu_a3 <= CPU_is_sltu_a2;
      always_ff @(posedge clk) CPU_is_sltu_a4 <= CPU_is_sltu_a3;
      always_ff @(posedge clk) CPU_is_sltu_a5 <= CPU_is_sltu_a4;

      // Staging of $is_sra.
      always_ff @(posedge clk) CPU_is_sra_a3 <= CPU_is_sra_a2;
      always_ff @(posedge clk) CPU_is_sra_a4 <= CPU_is_sra_a3;
      always_ff @(posedge clk) CPU_is_sra_a5 <= CPU_is_sra_a4;

      // Staging of $is_srai.
      always_ff @(posedge clk) CPU_is_srai_a1 <= CPU_is_srai_a0;
      always_ff @(posedge clk) CPU_is_srai_a2 <= CPU_is_srai_a1;
      always_ff @(posedge clk) CPU_is_srai_a3 <= CPU_is_srai_a2;
      always_ff @(posedge clk) CPU_is_srai_a4 <= CPU_is_srai_a3;
      always_ff @(posedge clk) CPU_is_srai_a5 <= CPU_is_srai_a4;

      // Staging of $is_sral.
      always_ff @(posedge clk) CPU_is_sral_a3 <= CPU_is_sral_a2;
      always_ff @(posedge clk) CPU_is_sral_a4 <= CPU_is_sral_a3;
      always_ff @(posedge clk) CPU_is_sral_a5 <= CPU_is_sral_a4;

      // Staging of $is_srl.
      always_ff @(posedge clk) CPU_is_srl_a3 <= CPU_is_srl_a2;
      always_ff @(posedge clk) CPU_is_srl_a4 <= CPU_is_srl_a3;
      always_ff @(posedge clk) CPU_is_srl_a5 <= CPU_is_srl_a4;

      // Staging of $is_srli.
      always_ff @(posedge clk) CPU_is_srli_a3 <= CPU_is_srli_a2;
      always_ff @(posedge clk) CPU_is_srli_a4 <= CPU_is_srli_a3;
      always_ff @(posedge clk) CPU_is_srli_a5 <= CPU_is_srli_a4;

      // Staging of $is_store.
      always_ff @(posedge clk) CPU_is_store_a1 <= CPU_is_store_a0;
      always_ff @(posedge clk) CPU_is_store_a2 <= CPU_is_store_a1;
      always_ff @(posedge clk) CPU_is_store_a3 <= CPU_is_store_a2;
      always_ff @(posedge clk) CPU_is_store_a4 <= CPU_is_store_a3;
      always_ff @(posedge clk) CPU_is_store_a5 <= CPU_is_store_a4;

      // Staging of $is_sub.
      always_ff @(posedge clk) CPU_is_sub_a3 <= CPU_is_sub_a2;
      always_ff @(posedge clk) CPU_is_sub_a4 <= CPU_is_sub_a3;
      always_ff @(posedge clk) CPU_is_sub_a5 <= CPU_is_sub_a4;

      // Staging of $is_sw.
      always_ff @(posedge clk) CPU_is_sw_a3 <= CPU_is_sw_a2;
      always_ff @(posedge clk) CPU_is_sw_a4 <= CPU_is_sw_a3;
      always_ff @(posedge clk) CPU_is_sw_a5 <= CPU_is_sw_a4;

      // Staging of $is_xor.
      always_ff @(posedge clk) CPU_is_xor_a3 <= CPU_is_xor_a2;
      always_ff @(posedge clk) CPU_is_xor_a4 <= CPU_is_xor_a3;
      always_ff @(posedge clk) CPU_is_xor_a5 <= CPU_is_xor_a4;

      // Staging of $is_xori.
      always_ff @(posedge clk) CPU_is_xori_a3 <= CPU_is_xori_a2;
      always_ff @(posedge clk) CPU_is_xori_a4 <= CPU_is_xori_a3;
      always_ff @(posedge clk) CPU_is_xori_a5 <= CPU_is_xori_a4;

      // Staging of $jalr_tgt_pc.
      always_ff @(posedge clk) CPU_jalr_tgt_pc_a3 <= CPU_jalr_tgt_pc_a2;

      // Staging of $opcode.
      always_ff @(posedge clk) CPU_opcode_a2[6:0] <= CPU_opcode_a1[6:0];

      // Staging of $pc.
      always_ff @(posedge clk) CPU_pc_a1[31:0] <= CPU_pc_a0[31:0];
      always_ff @(posedge clk) CPU_pc_a2[31:0] <= CPU_pc_a1[31:0];
      always_ff @(posedge clk) CPU_pc_a3[31:0] <= CPU_pc_a2[31:0];
      always_ff @(posedge clk) CPU_pc_a4[31:0] <= CPU_pc_a3[31:0];
      always_ff @(posedge clk) CPU_pc_a5[31:0] <= CPU_pc_a4[31:0];

      // Staging of $rd.
      always_ff @(posedge clkP_CPU_rd_valid_a2) CPU_rd_a2[4:0] <= CPU_rd_a1[4:0];
      always_ff @(posedge clkP_CPU_rd_valid_a3) CPU_rd_a3[4:0] <= CPU_rd_a2[4:0];
      always_ff @(posedge clkP_CPU_rd_valid_a4) CPU_rd_a4[4:0] <= CPU_rd_a3[4:0];
      always_ff @(posedge clkP_CPU_rd_valid_a5) CPU_rd_a5[4:0] <= CPU_rd_a4[4:0];

      // Staging of $rd_valid.
      always_ff @(posedge clk) CPU_rd_valid_a2 <= CPU_rd_valid_a1;
      always_ff @(posedge clk) CPU_rd_valid_a3 <= CPU_rd_valid_a2;
      always_ff @(posedge clk) CPU_rd_valid_a4 <= CPU_rd_valid_a3;
      always_ff @(posedge clk) CPU_rd_valid_a5 <= CPU_rd_valid_a4;

      // Staging of $reset.
      always_ff @(posedge clk) CPU_reset_a1 <= CPU_reset_a0;
      always_ff @(posedge clk) CPU_reset_a2 <= CPU_reset_a1;
      always_ff @(posedge clk) CPU_reset_a3 <= CPU_reset_a2;
      always_ff @(posedge clk) CPU_reset_a4 <= CPU_reset_a3;

      // Staging of $result.
      always_ff @(posedge clk) CPU_result_a4[31:0] <= CPU_result_a3[31:0];
      always_ff @(posedge clk) CPU_result_a5[31:0] <= CPU_result_a4[31:0];

      // Staging of $rs1.
      always_ff @(posedge clkP_CPU_rs1_valid_a2) CPU_rs1_a2[4:0] <= CPU_rs1_a1[4:0];
      always_ff @(posedge clkP_CPU_rs1_valid_a3) CPU_rs1_a3[4:0] <= CPU_rs1_a2[4:0];
      always_ff @(posedge clkP_CPU_rs1_valid_a4) CPU_rs1_a4[4:0] <= CPU_rs1_a3[4:0];
      always_ff @(posedge clkP_CPU_rs1_valid_a5) CPU_rs1_a5[4:0] <= CPU_rs1_a4[4:0];

      // Staging of $rs1_valid.
      always_ff @(posedge clk) CPU_rs1_valid_a2 <= CPU_rs1_valid_a1;
      always_ff @(posedge clk) CPU_rs1_valid_a3 <= CPU_rs1_valid_a2;
      always_ff @(posedge clk) CPU_rs1_valid_a4 <= CPU_rs1_valid_a3;
      always_ff @(posedge clk) CPU_rs1_valid_a5 <= CPU_rs1_valid_a4;

      // Staging of $rs2.
      always_ff @(posedge clkP_CPU_rs2_valid_a2) CPU_rs2_a2[4:0] <= CPU_rs2_a1[4:0];
      always_ff @(posedge clkP_CPU_rs2_valid_a3) CPU_rs2_a3[4:0] <= CPU_rs2_a2[4:0];
      always_ff @(posedge clkP_CPU_rs2_valid_a4) CPU_rs2_a4[4:0] <= CPU_rs2_a3[4:0];
      always_ff @(posedge clkP_CPU_rs2_valid_a5) CPU_rs2_a5[4:0] <= CPU_rs2_a4[4:0];

      // Staging of $rs2_valid.
      always_ff @(posedge clk) CPU_rs2_valid_a2 <= CPU_rs2_valid_a1;
      always_ff @(posedge clk) CPU_rs2_valid_a3 <= CPU_rs2_valid_a2;
      always_ff @(posedge clk) CPU_rs2_valid_a4 <= CPU_rs2_valid_a3;
      always_ff @(posedge clk) CPU_rs2_valid_a5 <= CPU_rs2_valid_a4;

      // Staging of $src1_value.
      always_ff @(posedge clk) CPU_src1_value_a3[31:0] <= CPU_src1_value_a2[31:0];
      always_ff @(posedge clk) CPU_src1_value_a4[31:0] <= CPU_src1_value_a3[31:0];
      always_ff @(posedge clk) CPU_src1_value_a5[31:0] <= CPU_src1_value_a4[31:0];

      // Staging of $src2_value.
      always_ff @(posedge clk) CPU_src2_value_a3[31:0] <= CPU_src2_value_a2[31:0];
      always_ff @(posedge clk) CPU_src2_value_a4[31:0] <= CPU_src2_value_a3[31:0];
      always_ff @(posedge clk) CPU_src2_value_a5[31:0] <= CPU_src2_value_a4[31:0];

      // Staging of $start.
      always_ff @(posedge clk) CPU_start_a1 <= CPU_start_a0;
      always_ff @(posedge clk) CPU_start_a2 <= CPU_start_a1;
      always_ff @(posedge clk) CPU_start_a3 <= CPU_start_a2;
      always_ff @(posedge clk) CPU_start_a4 <= CPU_start_a3;
      always_ff @(posedge clk) CPU_start_a5 <= CPU_start_a4;

      // Staging of $valid.
      always_ff @(posedge clk) CPU_valid_a4 <= CPU_valid_a3;
      always_ff @(posedge clk) CPU_valid_a5 <= CPU_valid_a4;

      // Staging of $valid_load.
      always_ff @(posedge clk) CPU_valid_load_a4 <= CPU_valid_load_a3;
      always_ff @(posedge clk) CPU_valid_load_a5 <= CPU_valid_load_a4;

      // Staging of $valid_taken_br.
      always_ff @(posedge clk) CPU_valid_taken_br_a4 <= CPU_valid_taken_br_a3;
      always_ff @(posedge clk) CPU_valid_taken_br_a5 <= CPU_valid_taken_br_a4;


      //
      // Scope: /dmem[15:0]
      //
      for (dmem = 0; dmem <= 15; dmem++) begin : L1gen_CPU_Dmem
         // Staging of $dummy.
         always_ff @(posedge clk) L1b_CPU_Dmem[dmem].L1_dummy_a1[0:0] <= L1b_CPU_Dmem[dmem].L1_dummy_a0[0:0];
         always_ff @(posedge clk) L1b_CPU_Dmem[dmem].L1_dummy_a2[0:0] <= L1b_CPU_Dmem[dmem].L1_dummy_a1[0:0];
         always_ff @(posedge clk) L1b_CPU_Dmem[dmem].L1_dummy_a3[0:0] <= L1b_CPU_Dmem[dmem].L1_dummy_a2[0:0];
         always_ff @(posedge clk) L1b_CPU_Dmem[dmem].L1_dummy_a4[0:0] <= L1b_CPU_Dmem[dmem].L1_dummy_a3[0:0];
         always_ff @(posedge clk) L1b_CPU_Dmem[dmem].L1_dummy_a5[0:0] <= L1b_CPU_Dmem[dmem].L1_dummy_a4[0:0];

         // Staging of $value.
         always_ff @(posedge clk) CPU_Dmem_value_a5[dmem][31:0] <= CPU_Dmem_value_a4[dmem][31:0];

         // Staging of $wr.
         always_ff @(posedge clk) L1_CPU_Dmem[dmem].L1_wr_a5 <= L1_CPU_Dmem[dmem].L1_wr_a4;

      end

      //
      // Scope: /xreg[31:0]
      //
      for (xreg = 0; xreg <= 31; xreg++) begin : L1gen_CPU_Xreg
         // Staging of $dummy.
         always_ff @(posedge clk) L1b_CPU_Xreg[xreg].L1_dummy_a1[0:0] <= L1b_CPU_Xreg[xreg].L1_dummy_a0[0:0];
         always_ff @(posedge clk) L1b_CPU_Xreg[xreg].L1_dummy_a2[0:0] <= L1b_CPU_Xreg[xreg].L1_dummy_a1[0:0];
         always_ff @(posedge clk) L1b_CPU_Xreg[xreg].L1_dummy_a3[0:0] <= L1b_CPU_Xreg[xreg].L1_dummy_a2[0:0];
         always_ff @(posedge clk) L1b_CPU_Xreg[xreg].L1_dummy_a4[0:0] <= L1b_CPU_Xreg[xreg].L1_dummy_a3[0:0];
         always_ff @(posedge clk) L1b_CPU_Xreg[xreg].L1_dummy_a5[0:0] <= L1b_CPU_Xreg[xreg].L1_dummy_a4[0:0];

         // Staging of $value.
         always_ff @(posedge clk) CPU_Xreg_value_a4[xreg][31:0] <= CPU_Xreg_value_a3[xreg][31:0];
         always_ff @(posedge clk) CPU_Xreg_value_a5[xreg][31:0] <= CPU_Xreg_value_a4[xreg][31:0];
         always_ff @(posedge clk) CPU_Xreg_value_a6[xreg][31:0] <= CPU_Xreg_value_a5[xreg][31:0];
         always_ff @(posedge clk) CPU_Xreg_value_a7[xreg][31:0] <= CPU_Xreg_value_a6[xreg][31:0];
         always_ff @(posedge clk) CPU_Xreg_value_a8[xreg][31:0] <= CPU_Xreg_value_a7[xreg][31:0];
         always_ff @(posedge clk) CPU_Xreg_value_a9[xreg][31:0] <= CPU_Xreg_value_a8[xreg][31:0];
         always_ff @(posedge clk) CPU_Xreg_value_a10[xreg][31:0] <= CPU_Xreg_value_a9[xreg][31:0];

         // Staging of $wr.
         always_ff @(posedge clk) L1_CPU_Xreg[xreg].L1_wr_a4 <= L1_CPU_Xreg[xreg].L1_wr_a3;
         always_ff @(posedge clk) L1_CPU_Xreg[xreg].L1_wr_a5 <= L1_CPU_Xreg[xreg].L1_wr_a4;

      end


   //
   // Scope: |cpuviz
   //


      //
      // Scope: /dmem[15:0]
      //
      for (dmem = 0; dmem <= 15; dmem++) begin : L1gen_CPUVIZ_Dmem
         // Staging of $value.
         always_ff @(posedge clk) L1_CPUVIZ_Dmem[dmem].L1_value_a6[31:0] <= L1_CPUVIZ_Dmem[dmem].L1_value_a5[31:0];

      end

      //
      // Scope: /xreg[31:0]
      //
      for (xreg = 0; xreg <= 31; xreg++) begin : L1gen_CPUVIZ_Xreg
         // Staging of $value.
         always_ff @(posedge clk) L1_CPUVIZ_Xreg[xreg].L1_value_a6[31:0] <= L1_CPUVIZ_Xreg[xreg].L1_value_a5[31:0];

      end




//
// Gated clocks.
//



   //
   // Scope: |cpu
   //

      clk_gate gen_clkP_CPU_dmem_rd_en_a5(clkP_CPU_dmem_rd_en_a5, clk, 1'b1, CPU_dmem_rd_en_a4, 1'b0);
      clk_gate gen_clkP_CPU_funct3_valid_a2(clkP_CPU_funct3_valid_a2, clk, 1'b1, CPU_funct3_valid_a1, 1'b0);
      clk_gate gen_clkP_CPU_funct7_valid_a2(clkP_CPU_funct7_valid_a2, clk, 1'b1, CPU_funct7_valid_a1, 1'b0);
      clk_gate gen_clkP_CPU_rd_valid_a2(clkP_CPU_rd_valid_a2, clk, 1'b1, CPU_rd_valid_a1, 1'b0);
      clk_gate gen_clkP_CPU_rd_valid_a3(clkP_CPU_rd_valid_a3, clk, 1'b1, CPU_rd_valid_a2, 1'b0);
      clk_gate gen_clkP_CPU_rd_valid_a4(clkP_CPU_rd_valid_a4, clk, 1'b1, CPU_rd_valid_a3, 1'b0);
      clk_gate gen_clkP_CPU_rd_valid_a5(clkP_CPU_rd_valid_a5, clk, 1'b1, CPU_rd_valid_a4, 1'b0);
      clk_gate gen_clkP_CPU_rs1_valid_a2(clkP_CPU_rs1_valid_a2, clk, 1'b1, CPU_rs1_valid_a1, 1'b0);
      clk_gate gen_clkP_CPU_rs1_valid_a3(clkP_CPU_rs1_valid_a3, clk, 1'b1, CPU_rs1_valid_a2, 1'b0);
      clk_gate gen_clkP_CPU_rs1_valid_a4(clkP_CPU_rs1_valid_a4, clk, 1'b1, CPU_rs1_valid_a3, 1'b0);
      clk_gate gen_clkP_CPU_rs1_valid_a5(clkP_CPU_rs1_valid_a5, clk, 1'b1, CPU_rs1_valid_a4, 1'b0);
      clk_gate gen_clkP_CPU_rs2_valid_a2(clkP_CPU_rs2_valid_a2, clk, 1'b1, CPU_rs2_valid_a1, 1'b0);
      clk_gate gen_clkP_CPU_rs2_valid_a3(clkP_CPU_rs2_valid_a3, clk, 1'b1, CPU_rs2_valid_a2, 1'b0);
      clk_gate gen_clkP_CPU_rs2_valid_a4(clkP_CPU_rs2_valid_a4, clk, 1'b1, CPU_rs2_valid_a3, 1'b0);
      clk_gate gen_clkP_CPU_rs2_valid_a5(clkP_CPU_rs2_valid_a5, clk, 1'b1, CPU_rs2_valid_a4, 1'b0);





//
// Debug Signals
//

   if (1) begin : DEBUG_SIGS


      //
      // Scope: |cpu
      //
      if (1) begin : \|cpu 
         logic [31:0] \/@2$br_tgt_pc ;
         assign \/@2$br_tgt_pc = CPU_br_tgt_pc_a2;
         logic [10:0] \/@2$dec_bits ;
         assign \/@2$dec_bits = CPU_dec_bits_a2;
         logic [3:0] \/@4$dmem_addr ;
         assign \/@4$dmem_addr = CPU_dmem_addr_a4;
         logic [31:0] \/?$dmem_rd_en@4$dmem_rd_data ;
         assign \/?$dmem_rd_en@4$dmem_rd_data = CPU_dmem_rd_data_a4;
         logic  \/@4$dmem_rd_en ;
         assign \/@4$dmem_rd_en = CPU_dmem_rd_en_a4;
         logic [31:0] \/@4$dmem_wr_data ;
         assign \/@4$dmem_wr_data = CPU_dmem_wr_data_a4;
         logic  \/@4$dmem_wr_en ;
         assign \/@4$dmem_wr_en = CPU_dmem_wr_en_a4;
         logic [0:0] \/@0$dummy ;
         assign \/@0$dummy = CPU_dummy_a0;
         logic [2:0] \/?$funct3_valid@1$funct3 ;
         assign \/?$funct3_valid@1$funct3 = CPU_funct3_a1;
         logic  \/@1$funct3_valid ;
         assign \/@1$funct3_valid = CPU_funct3_valid_a1;
         logic [6:0] \/?$funct7_valid@1$funct7 ;
         assign \/?$funct7_valid@1$funct7 = CPU_funct7_a1;
         logic  \/@1$funct7_valid ;
         assign \/@1$funct7_valid = CPU_funct7_valid_a1;
         logic [4-1:0] \/@1$imem_rd_addr ;
         assign \/@1$imem_rd_addr = CPU_imem_rd_addr_a1;
         logic [31:0] \/?$imem_rd_en@1$imem_rd_data ;
         assign \/?$imem_rd_en@1$imem_rd_data = CPU_imem_rd_data_a1;
         logic  \/@1$imem_rd_en ;
         assign \/@1$imem_rd_en = CPU_imem_rd_en_a1;
         logic [31:0] \/@1$imm ;
         assign \/@1$imm = CPU_imm_a1;
         logic [31:0] \/@1$inc_pc ;
         assign \/@1$inc_pc = CPU_inc_pc_a1;
         logic [31:0] \/@1$instr ;
         assign \/@1$instr = CPU_instr_a1;
         logic  \/@2$is_add ;
         assign \/@2$is_add = CPU_is_add_a2;
         logic  \/@2$is_addi ;
         assign \/@2$is_addi = CPU_is_addi_a2;
         logic  \/@2$is_and ;
         assign \/@2$is_and = CPU_is_and_a2;
         logic  \/@2$is_andi ;
         assign \/@2$is_andi = CPU_is_andi_a2;
         logic  \/@2$is_auipc ;
         assign \/@2$is_auipc = CPU_is_auipc_a2;
         logic  \/@1$is_b_instr ;
         assign \/@1$is_b_instr = CPU_is_b_instr_a1;
         logic  \/@2$is_beq ;
         assign \/@2$is_beq = CPU_is_beq_a2;
         logic  \/@2$is_bge ;
         assign \/@2$is_bge = CPU_is_bge_a2;
         logic  \/@2$is_bgeu ;
         assign \/@2$is_bgeu = CPU_is_bgeu_a2;
         logic  \/@2$is_blt ;
         assign \/@2$is_blt = CPU_is_blt_a2;
         logic  \/@2$is_bltu ;
         assign \/@2$is_bltu = CPU_is_bltu_a2;
         logic  \/@2$is_bne ;
         assign \/@2$is_bne = CPU_is_bne_a2;
         logic  \/@0$is_csrrc ;
         assign \/@0$is_csrrc = CPU_is_csrrc_a0;
         logic  \/@0$is_csrrci ;
         assign \/@0$is_csrrci = CPU_is_csrrci_a0;
         logic  \/@0$is_csrrs ;
         assign \/@0$is_csrrs = CPU_is_csrrs_a0;
         logic  \/@0$is_csrrsi ;
         assign \/@0$is_csrrsi = CPU_is_csrrsi_a0;
         logic  \/@0$is_csrrw ;
         assign \/@0$is_csrrw = CPU_is_csrrw_a0;
         logic  \/@0$is_csrrwi ;
         assign \/@0$is_csrrwi = CPU_is_csrrwi_a0;
         logic  \/@1$is_i_instr ;
         assign \/@1$is_i_instr = CPU_is_i_instr_a1;
         logic  \/@1$is_j_instr ;
         assign \/@1$is_j_instr = CPU_is_j_instr_a1;
         logic  \/@2$is_jal ;
         assign \/@2$is_jal = CPU_is_jal_a2;
         logic  \/@2$is_jalb ;
         assign \/@2$is_jalb = CPU_is_jalb_a2;
         logic  \/@0$is_jalr ;
         assign \/@0$is_jalr = CPU_is_jalr_a0;
         logic  \/@3$is_jump ;
         assign \/@3$is_jump = CPU_is_jump_a3;
         logic  \/@2$is_lb ;
         assign \/@2$is_lb = CPU_is_lb_a2;
         logic  \/@2$is_lbu ;
         assign \/@2$is_lbu = CPU_is_lbu_a2;
         logic  \/@2$is_lh ;
         assign \/@2$is_lh = CPU_is_lh_a2;
         logic  \/@2$is_lhu ;
         assign \/@2$is_lhu = CPU_is_lhu_a2;
         logic  \/@2$is_load ;
         assign \/@2$is_load = CPU_is_load_a2;
         logic  \/@2$is_lui ;
         assign \/@2$is_lui = CPU_is_lui_a2;
         logic  \/@2$is_lw ;
         assign \/@2$is_lw = CPU_is_lw_a2;
         logic  \/@2$is_or ;
         assign \/@2$is_or = CPU_is_or_a2;
         logic  \/@2$is_ori ;
         assign \/@2$is_ori = CPU_is_ori_a2;
         logic  \/@1$is_r_instr ;
         assign \/@1$is_r_instr = CPU_is_r_instr_a1;
         logic  \/@1$is_s_instr ;
         assign \/@1$is_s_instr = CPU_is_s_instr_a1;
         logic  \/@2$is_sb ;
         assign \/@2$is_sb = CPU_is_sb_a2;
         logic  \/@2$is_sh ;
         assign \/@2$is_sh = CPU_is_sh_a2;
         logic  \/@2$is_sll ;
         assign \/@2$is_sll = CPU_is_sll_a2;
         logic  \/@2$is_slli ;
         assign \/@2$is_slli = CPU_is_slli_a2;
         logic  \/@2$is_slt ;
         assign \/@2$is_slt = CPU_is_slt_a2;
         logic  \/@2$is_slti ;
         assign \/@2$is_slti = CPU_is_slti_a2;
         logic  \/@2$is_sltiu ;
         assign \/@2$is_sltiu = CPU_is_sltiu_a2;
         logic  \/@2$is_sltu ;
         assign \/@2$is_sltu = CPU_is_sltu_a2;
         logic  \/@2$is_sra ;
         assign \/@2$is_sra = CPU_is_sra_a2;
         logic  \/@0$is_srai ;
         assign \/@0$is_srai = CPU_is_srai_a0;
         logic  \/@2$is_sral ;
         assign \/@2$is_sral = CPU_is_sral_a2;
         logic  \/@2$is_srl ;
         assign \/@2$is_srl = CPU_is_srl_a2;
         logic  \/@2$is_srli ;
         assign \/@2$is_srli = CPU_is_srli_a2;
         logic  \/@0$is_store ;
         assign \/@0$is_store = CPU_is_store_a0;
         logic  \/@2$is_sub ;
         assign \/@2$is_sub = CPU_is_sub_a2;
         logic  \/@2$is_sw ;
         assign \/@2$is_sw = CPU_is_sw_a2;
         logic  \/@1$is_u_instr ;
         assign \/@1$is_u_instr = CPU_is_u_instr_a1;
         logic  \/@2$is_xor ;
         assign \/@2$is_xor = CPU_is_xor_a2;
         logic  \/@2$is_xori ;
         assign \/@2$is_xori = CPU_is_xori_a2;
         logic  \/@2$jalr_tgt_pc ;
         assign \/@2$jalr_tgt_pc = CPU_jalr_tgt_pc_a2;
         logic [31:0] \/@5$ld_data ;
         assign \/@5$ld_data = CPU_ld_data_a5;
         logic [6:0] \/@1$opcode ;
         assign \/@1$opcode = CPU_opcode_a1;
         logic [31:0] \/@0$pc ;
         assign \/@0$pc = CPU_pc_a0;
         logic [4:0] \/?$rd_valid@1$rd ;
         assign \/?$rd_valid@1$rd = CPU_rd_a1;
         logic  \/@1$rd_valid ;
         assign \/@1$rd_valid = CPU_rd_valid_a1;
         logic  \/@0$reset ;
         assign \/@0$reset = CPU_reset_a0;
         logic [31:0] \/@3$result ;
         assign \/@3$result = CPU_result_a3;
         logic [31:0] \/?$rf_rd_en1@2$rf_rd_data1 ;
         assign \/?$rf_rd_en1@2$rf_rd_data1 = CPU_rf_rd_data1_a2;
         logic [31:0] \/?$rf_rd_en2@2$rf_rd_data2 ;
         assign \/?$rf_rd_en2@2$rf_rd_data2 = CPU_rf_rd_data2_a2;
         logic  \/@2$rf_rd_en1 ;
         assign \/@2$rf_rd_en1 = CPU_rf_rd_en1_a2;
         logic  \/@2$rf_rd_en2 ;
         assign \/@2$rf_rd_en2 = CPU_rf_rd_en2_a2;
         logic [4:0] \/@2$rf_rd_index1 ;
         assign \/@2$rf_rd_index1 = CPU_rf_rd_index1_a2;
         logic [4:0] \/@2$rf_rd_index2 ;
         assign \/@2$rf_rd_index2 = CPU_rf_rd_index2_a2;
         logic [31:0] \/@3$rf_wr_data ;
         assign \/@3$rf_wr_data = CPU_rf_wr_data_a3;
         logic  \/@3$rf_wr_en ;
         assign \/@3$rf_wr_en = CPU_rf_wr_en_a3;
         logic [4:0] \/@3$rf_wr_index ;
         assign \/@3$rf_wr_index = CPU_rf_wr_index_a3;
         logic [4:0] \/?$rs1_valid@1$rs1 ;
         assign \/?$rs1_valid@1$rs1 = CPU_rs1_a1;
         logic  \/@1$rs1_valid ;
         assign \/@1$rs1_valid = CPU_rs1_valid_a1;
         logic [4:0] \/?$rs2_valid@1$rs2 ;
         assign \/?$rs2_valid@1$rs2 = CPU_rs2_a1;
         logic  \/@1$rs2_valid ;
         assign \/@1$rs2_valid = CPU_rs2_valid_a1;
         logic [31:0] \/@3$sltiu_rslt ;
         assign \/@3$sltiu_rslt = CPU_sltiu_rslt_a3;
         logic [31:0] \/@3$sltu_rslt ;
         assign \/@3$sltu_rslt = CPU_sltu_rslt_a3;
         logic [31:0] \/@2$src1_value ;
         assign \/@2$src1_value = CPU_src1_value_a2;
         logic [31:0] \/@2$src2_value ;
         assign \/@2$src2_value = CPU_src2_value_a2;
         logic  \/@0$start ;
         assign \/@0$start = CPU_start_a0;
         logic  \/@3$taken_br ;
         assign \/@3$taken_br = CPU_taken_br_a3;
         logic  \/@3$valid ;
         assign \/@3$valid = CPU_valid_a3;
         logic  \/@3$valid_jump ;
         assign \/@3$valid_jump = CPU_valid_jump_a3;
         logic  \/@3$valid_load ;
         assign \/@3$valid_load = CPU_valid_load_a3;
         logic  \/@3$valid_taken_br ;
         assign \/@3$valid_taken_br = CPU_valid_taken_br_a3;

         //
         // Scope: /dmem[15:0]
         //
         for (dmem = 0; dmem <= 15; dmem++) begin : \/dmem 
            logic [0:0] \//@0$dummy ;
            assign \//@0$dummy = L1b_CPU_Dmem[dmem].L1_dummy_a0;
            logic [31:0] \//@4$value ;
            assign \//@4$value = CPU_Dmem_value_a4[dmem];
            logic  \//@4$wr ;
            assign \//@4$wr = L1_CPU_Dmem[dmem].L1_wr_a4;
         end

         //
         // Scope: /imem[9:0]
         //
         for (imem = 0; imem <= 9; imem++) begin : \/imem 
            logic [31:0] \//@1$instr ;
            assign \//@1$instr = CPU_Imem_instr_a1[imem];
         end

         //
         // Scope: /xreg[31:0]
         //
         for (xreg = 0; xreg <= 31; xreg++) begin : \/xreg 
            logic [0:0] \//@0$dummy ;
            assign \//@0$dummy = L1b_CPU_Xreg[xreg].L1_dummy_a0;
            logic [31:0] \//@3$value ;
            assign \//@3$value = CPU_Xreg_value_a3[xreg];
            logic  \//@3$wr ;
            assign \//@3$wr = L1_CPU_Xreg[xreg].L1_wr_a3;
         end
      end

      //
      // Scope: |cpuviz
      //
      if (1) begin : \|cpuviz 
         logic [31:0] \/@5$imm ;
         assign \/@5$imm = CPUVIZ_imm_a5;
         logic  \/@5$is_add ;
         assign \/@5$is_add = CPUVIZ_is_add_a5;
         logic  \/@5$is_addi ;
         assign \/@5$is_addi = CPUVIZ_is_addi_a5;
         logic  \/@5$is_and ;
         assign \/@5$is_and = CPUVIZ_is_and_a5;
         logic  \/@5$is_andi ;
         assign \/@5$is_andi = CPUVIZ_is_andi_a5;
         logic  \/@5$is_auipc ;
         assign \/@5$is_auipc = CPUVIZ_is_auipc_a5;
         logic  \/@5$is_beq ;
         assign \/@5$is_beq = CPUVIZ_is_beq_a5;
         logic  \/@5$is_bge ;
         assign \/@5$is_bge = CPUVIZ_is_bge_a5;
         logic  \/@5$is_bgeu ;
         assign \/@5$is_bgeu = CPUVIZ_is_bgeu_a5;
         logic  \/@5$is_blt ;
         assign \/@5$is_blt = CPUVIZ_is_blt_a5;
         logic  \/@5$is_bltu ;
         assign \/@5$is_bltu = CPUVIZ_is_bltu_a5;
         logic  \/@5$is_bne ;
         assign \/@5$is_bne = CPUVIZ_is_bne_a5;
         logic  \/@5$is_csrrc ;
         assign \/@5$is_csrrc = CPUVIZ_is_csrrc_a5;
         logic  \/@5$is_csrrci ;
         assign \/@5$is_csrrci = CPUVIZ_is_csrrci_a5;
         logic  \/@5$is_csrrs ;
         assign \/@5$is_csrrs = CPUVIZ_is_csrrs_a5;
         logic  \/@5$is_csrrsi ;
         assign \/@5$is_csrrsi = CPUVIZ_is_csrrsi_a5;
         logic  \/@5$is_csrrw ;
         assign \/@5$is_csrrw = CPUVIZ_is_csrrw_a5;
         logic  \/@5$is_csrrwi ;
         assign \/@5$is_csrrwi = CPUVIZ_is_csrrwi_a5;
         logic  \/@5$is_jal ;
         assign \/@5$is_jal = CPUVIZ_is_jal_a5;
         logic  \/@5$is_jalr ;
         assign \/@5$is_jalr = CPUVIZ_is_jalr_a5;
         logic  \/@5$is_lb ;
         assign \/@5$is_lb = CPUVIZ_is_lb_a5;
         logic  \/@5$is_lbu ;
         assign \/@5$is_lbu = CPUVIZ_is_lbu_a5;
         logic  \/@5$is_lh ;
         assign \/@5$is_lh = CPUVIZ_is_lh_a5;
         logic  \/@5$is_lhu ;
         assign \/@5$is_lhu = CPUVIZ_is_lhu_a5;
         logic  \/@5$is_load ;
         assign \/@5$is_load = CPUVIZ_is_load_a5;
         logic  \/@5$is_lui ;
         assign \/@5$is_lui = CPUVIZ_is_lui_a5;
         logic  \/@5$is_lw ;
         assign \/@5$is_lw = CPUVIZ_is_lw_a5;
         logic  \/@5$is_or ;
         assign \/@5$is_or = CPUVIZ_is_or_a5;
         logic  \/@5$is_ori ;
         assign \/@5$is_ori = CPUVIZ_is_ori_a5;
         logic  \/@5$is_sb ;
         assign \/@5$is_sb = CPUVIZ_is_sb_a5;
         logic  \/@5$is_sh ;
         assign \/@5$is_sh = CPUVIZ_is_sh_a5;
         logic  \/@5$is_sll ;
         assign \/@5$is_sll = CPUVIZ_is_sll_a5;
         logic  \/@5$is_slli ;
         assign \/@5$is_slli = CPUVIZ_is_slli_a5;
         logic  \/@5$is_slt ;
         assign \/@5$is_slt = CPUVIZ_is_slt_a5;
         logic  \/@5$is_slti ;
         assign \/@5$is_slti = CPUVIZ_is_slti_a5;
         logic  \/@5$is_sltiu ;
         assign \/@5$is_sltiu = CPUVIZ_is_sltiu_a5;
         logic  \/@5$is_sltu ;
         assign \/@5$is_sltu = CPUVIZ_is_sltu_a5;
         logic  \/@5$is_sra ;
         assign \/@5$is_sra = CPUVIZ_is_sra_a5;
         logic  \/@5$is_srai ;
         assign \/@5$is_srai = CPUVIZ_is_srai_a5;
         logic  \/@5$is_srl ;
         assign \/@5$is_srl = CPUVIZ_is_srl_a5;
         logic  \/@5$is_srli ;
         assign \/@5$is_srli = CPUVIZ_is_srli_a5;
         logic  \/@5$is_store ;
         assign \/@5$is_store = CPUVIZ_is_store_a5;
         logic  \/@5$is_sub ;
         assign \/@5$is_sub = CPUVIZ_is_sub_a5;
         logic  \/@5$is_sw ;
         assign \/@5$is_sw = CPUVIZ_is_sw_a5;
         logic  \/@5$is_xor ;
         assign \/@5$is_xor = CPUVIZ_is_xor_a5;
         logic  \/@5$is_xori ;
         assign \/@5$is_xori = CPUVIZ_is_xori_a5;
         logic [10*8-1:0] \/@5$mnemonic ;
         assign \/@5$mnemonic = CPUVIZ_mnemonic_a5;
         logic [31:0] \/@5$pc ;
         assign \/@5$pc = CPUVIZ_pc_a5;
         logic [4:0] \/@5$rd ;
         assign \/@5$rd = CPUVIZ_rd_a5;
         logic  \/@5$rd_valid ;
         assign \/@5$rd_valid = CPUVIZ_rd_valid_a5;
         logic [31:0] \/@5$result ;
         assign \/@5$result = CPUVIZ_result_a5;
         logic [4:0] \/@5$rs1 ;
         assign \/@5$rs1 = CPUVIZ_rs1_a5;
         logic  \/@5$rs1_valid ;
         assign \/@5$rs1_valid = CPUVIZ_rs1_valid_a5;
         logic [4:0] \/@5$rs2 ;
         assign \/@5$rs2 = CPUVIZ_rs2_a5;
         logic  \/@5$rs2_valid ;
         assign \/@5$rs2_valid = CPUVIZ_rs2_valid_a5;
         logic [31:0] \/@5$src1_value ;
         assign \/@5$src1_value = CPUVIZ_src1_value_a5;
         logic [31:0] \/@5$src2_value ;
         assign \/@5$src2_value = CPUVIZ_src2_value_a5;
         logic  \/@5$valid ;
         assign \/@5$valid = CPUVIZ_valid_a5;

         //
         // Scope: /defaults
         //
         if (1) begin : \/defaults 
            logic [0:0] \//@0$dummy ;
            assign \//@0$dummy = CPUVIZ_Defaults_dummy_a0;
            logic [4-1:0] \//@0$imem_rd_addr ;
            assign \//@0$imem_rd_addr = CPUVIZ_Defaults_imem_rd_addr_a0;
            logic  \//@0$imem_rd_en ;
            assign \//@0$imem_rd_en = CPUVIZ_Defaults_imem_rd_en_a0;
            logic [31:0] \//@0$imm ;
            assign \//@0$imm = CPUVIZ_Defaults_imm_a0;
            logic  \//@0$is_add ;
            assign \//@0$is_add = CPUVIZ_Defaults_is_add_a0;
            logic  \//@0$is_addi ;
            assign \//@0$is_addi = CPUVIZ_Defaults_is_addi_a0;
            logic  \//@0$is_and ;
            assign \//@0$is_and = CPUVIZ_Defaults_is_and_a0;
            logic  \//@0$is_andi ;
            assign \//@0$is_andi = CPUVIZ_Defaults_is_andi_a0;
            logic  \//@0$is_auipc ;
            assign \//@0$is_auipc = CPUVIZ_Defaults_is_auipc_a0;
            logic  \//@0$is_beq ;
            assign \//@0$is_beq = CPUVIZ_Defaults_is_beq_a0;
            logic  \//@0$is_bge ;
            assign \//@0$is_bge = CPUVIZ_Defaults_is_bge_a0;
            logic  \//@0$is_bgeu ;
            assign \//@0$is_bgeu = CPUVIZ_Defaults_is_bgeu_a0;
            logic  \//@0$is_blt ;
            assign \//@0$is_blt = CPUVIZ_Defaults_is_blt_a0;
            logic  \//@0$is_bltu ;
            assign \//@0$is_bltu = CPUVIZ_Defaults_is_bltu_a0;
            logic  \//@0$is_bne ;
            assign \//@0$is_bne = CPUVIZ_Defaults_is_bne_a0;
            logic  \//@0$is_csrrc ;
            assign \//@0$is_csrrc = CPUVIZ_Defaults_is_csrrc_a0;
            logic  \//@0$is_csrrci ;
            assign \//@0$is_csrrci = CPUVIZ_Defaults_is_csrrci_a0;
            logic  \//@0$is_csrrs ;
            assign \//@0$is_csrrs = CPUVIZ_Defaults_is_csrrs_a0;
            logic  \//@0$is_csrrsi ;
            assign \//@0$is_csrrsi = CPUVIZ_Defaults_is_csrrsi_a0;
            logic  \//@0$is_csrrw ;
            assign \//@0$is_csrrw = CPUVIZ_Defaults_is_csrrw_a0;
            logic  \//@0$is_csrrwi ;
            assign \//@0$is_csrrwi = CPUVIZ_Defaults_is_csrrwi_a0;
            logic  \//@0$is_jal ;
            assign \//@0$is_jal = CPUVIZ_Defaults_is_jal_a0;
            logic  \//@0$is_jalr ;
            assign \//@0$is_jalr = CPUVIZ_Defaults_is_jalr_a0;
            logic  \//@0$is_lb ;
            assign \//@0$is_lb = CPUVIZ_Defaults_is_lb_a0;
            logic  \//@0$is_lbu ;
            assign \//@0$is_lbu = CPUVIZ_Defaults_is_lbu_a0;
            logic  \//@0$is_lh ;
            assign \//@0$is_lh = CPUVIZ_Defaults_is_lh_a0;
            logic  \//@0$is_lhu ;
            assign \//@0$is_lhu = CPUVIZ_Defaults_is_lhu_a0;
            logic  \//@0$is_load ;
            assign \//@0$is_load = CPUVIZ_Defaults_is_load_a0;
            logic  \//@0$is_lui ;
            assign \//@0$is_lui = CPUVIZ_Defaults_is_lui_a0;
            logic  \//@0$is_lw ;
            assign \//@0$is_lw = CPUVIZ_Defaults_is_lw_a0;
            logic  \//@0$is_or ;
            assign \//@0$is_or = CPUVIZ_Defaults_is_or_a0;
            logic  \//@0$is_ori ;
            assign \//@0$is_ori = CPUVIZ_Defaults_is_ori_a0;
            logic  \//@0$is_s_instr ;
            assign \//@0$is_s_instr = CPUVIZ_Defaults_is_s_instr_a0;
            logic  \//@0$is_sb ;
            assign \//@0$is_sb = CPUVIZ_Defaults_is_sb_a0;
            logic  \//@0$is_sh ;
            assign \//@0$is_sh = CPUVIZ_Defaults_is_sh_a0;
            logic  \//@0$is_sll ;
            assign \//@0$is_sll = CPUVIZ_Defaults_is_sll_a0;
            logic  \//@0$is_slli ;
            assign \//@0$is_slli = CPUVIZ_Defaults_is_slli_a0;
            logic  \//@0$is_slt ;
            assign \//@0$is_slt = CPUVIZ_Defaults_is_slt_a0;
            logic  \//@0$is_slti ;
            assign \//@0$is_slti = CPUVIZ_Defaults_is_slti_a0;
            logic  \//@0$is_sltiu ;
            assign \//@0$is_sltiu = CPUVIZ_Defaults_is_sltiu_a0;
            logic  \//@0$is_sltu ;
            assign \//@0$is_sltu = CPUVIZ_Defaults_is_sltu_a0;
            logic  \//@0$is_sra ;
            assign \//@0$is_sra = CPUVIZ_Defaults_is_sra_a0;
            logic  \//@0$is_srai ;
            assign \//@0$is_srai = CPUVIZ_Defaults_is_srai_a0;
            logic  \//@0$is_srl ;
            assign \//@0$is_srl = CPUVIZ_Defaults_is_srl_a0;
            logic  \//@0$is_srli ;
            assign \//@0$is_srli = CPUVIZ_Defaults_is_srli_a0;
            logic  \//@0$is_store ;
            assign \//@0$is_store = CPUVIZ_Defaults_is_store_a0;
            logic  \//@0$is_sub ;
            assign \//@0$is_sub = CPUVIZ_Defaults_is_sub_a0;
            logic  \//@0$is_sw ;
            assign \//@0$is_sw = CPUVIZ_Defaults_is_sw_a0;
            logic  \//@0$is_xor ;
            assign \//@0$is_xor = CPUVIZ_Defaults_is_xor_a0;
            logic  \//@0$is_xori ;
            assign \//@0$is_xori = CPUVIZ_Defaults_is_xori_a0;
            logic [31:0] \//@0$ld_data ;
            assign \//@0$ld_data = CPUVIZ_Defaults_ld_data_a0;
            logic [31:0] \//@0$pc ;
            assign \//@0$pc = CPUVIZ_Defaults_pc_a0;
            logic [4:0] \//@0$rd ;
            assign \//@0$rd = CPUVIZ_Defaults_rd_a0;
            logic  \//@0$rd_valid ;
            assign \//@0$rd_valid = CPUVIZ_Defaults_rd_valid_a0;
            logic [31:0] \//@0$result ;
            assign \//@0$result = CPUVIZ_Defaults_result_a0;
            logic  \//@0$rf_rd_en1 ;
            assign \//@0$rf_rd_en1 = CPUVIZ_Defaults_rf_rd_en1_a0;
            logic  \//@0$rf_rd_en2 ;
            assign \//@0$rf_rd_en2 = CPUVIZ_Defaults_rf_rd_en2_a0;
            logic [4:0] \//@0$rf_rd_index1 ;
            assign \//@0$rf_rd_index1 = CPUVIZ_Defaults_rf_rd_index1_a0;
            logic [4:0] \//@0$rf_rd_index2 ;
            assign \//@0$rf_rd_index2 = CPUVIZ_Defaults_rf_rd_index2_a0;
            logic [31:0] \//@0$rf_wr_data ;
            assign \//@0$rf_wr_data = CPUVIZ_Defaults_rf_wr_data_a0;
            logic  \//@0$rf_wr_en ;
            assign \//@0$rf_wr_en = CPUVIZ_Defaults_rf_wr_en_a0;
            logic [4:0] \//@0$rf_wr_index ;
            assign \//@0$rf_wr_index = CPUVIZ_Defaults_rf_wr_index_a0;
            logic [4:0] \//@0$rs1 ;
            assign \//@0$rs1 = CPUVIZ_Defaults_rs1_a0;
            logic  \//@0$rs1_valid ;
            assign \//@0$rs1_valid = CPUVIZ_Defaults_rs1_valid_a0;
            logic [4:0] \//@0$rs2 ;
            assign \//@0$rs2 = CPUVIZ_Defaults_rs2_a0;
            logic  \//@0$rs2_valid ;
            assign \//@0$rs2_valid = CPUVIZ_Defaults_rs2_valid_a0;
            logic [31:0] \//@0$src1_value ;
            assign \//@0$src1_value = CPUVIZ_Defaults_src1_value_a0;
            logic [31:0] \//@0$src2_value ;
            assign \//@0$src2_value = CPUVIZ_Defaults_src2_value_a0;
            logic  \//@0$valid ;
            assign \//@0$valid = CPUVIZ_Defaults_valid_a0;

            //
            // Scope: /dmem[15:0]
            //
            for (dmem = 0; dmem <= 15; dmem++) begin : \/dmem 
               logic [0:0] \///@0$dummy ;
               assign \///@0$dummy = L1_CPUVIZ_Defaults_Dmem[dmem].L1_dummy_a0;
               logic [31:0] \///@0$value ;
               assign \///@0$value = L1_CPUVIZ_Defaults_Dmem[dmem].L1_value_a0;
               logic  \///@0$wr ;
               assign \///@0$wr = L1_CPUVIZ_Defaults_Dmem[dmem].L1_wr_a0;
            end

            //
            // Scope: /xreg[31:0]
            //
            for (xreg = 0; xreg <= 31; xreg++) begin : \/xreg 
               logic [0:0] \///@0$dummy ;
               assign \///@0$dummy = L1_CPUVIZ_Defaults_Xreg[xreg].L1_dummy_a0;
               logic [31:0] \///@0$value ;
               assign \///@0$value = L1_CPUVIZ_Defaults_Xreg[xreg].L1_value_a0;
               logic  \///@0$wr ;
               assign \///@0$wr = L1_CPUVIZ_Defaults_Xreg[xreg].L1_wr_a0;
            end
         end

         //
         // Scope: /dmem[15:0]
         //
         for (dmem = 0; dmem <= 15; dmem++) begin : \/dmem 
            logic [0:0] \//@5$dummy ;
            assign \//@5$dummy = L1_CPUVIZ_Dmem[dmem].L1_dummy_a5;
            logic [31:0] \//@5$value ;
            assign \//@5$value = L1_CPUVIZ_Dmem[dmem].L1_value_a5;
            logic  \//@5$wr ;
            assign \//@5$wr = L1_CPUVIZ_Dmem[dmem].L1_wr_a5;
         end

         //
         // Scope: /imem[9:0]
         //
         for (imem = 0; imem <= 9; imem++) begin : \/imem 
            logic [31:0] \//@1$instr ;
            assign \//@1$instr = L1_CPUVIZ_Imem[imem].L1_instr_a1;
            logic [40*8-1:0] \//@1$instr_str ;
            assign \//@1$instr_str = L1_CPUVIZ_Imem[imem].L1_instr_str_a1;
         end

         //
         // Scope: /xreg[31:0]
         //
         for (xreg = 0; xreg <= 31; xreg++) begin : \/xreg 
            logic [0:0] \//@5$dummy ;
            assign \//@5$dummy = L1_CPUVIZ_Xreg[xreg].L1_dummy_a5;
            logic [31:0] \//@5$value ;
            assign \//@5$value = L1_CPUVIZ_Xreg[xreg].L1_value_a5;
            logic  \//@5$wr ;
            assign \//@5$wr = L1_CPUVIZ_Xreg[xreg].L1_wr_a5;
         end
      end


   end