diff --git a/matter/efr32/efr32mg24/BRD2601B/autogen/sl_board_default_init.c b/matter/efr32/efr32mg24/BRD2601B/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..c3a6b48665 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2601B/autogen/sl_board_default_init.c @@ -0,0 +1,34 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ +} diff --git a/matter/efr32/efr32mg24/BRD2601B/autogen/sl_component_catalog.h b/matter/efr32/efr32mg24/BRD2601B/autogen/sl_component_catalog.h index 5e302f33d5..46683e8206 100644 --- a/matter/efr32/efr32mg24/BRD2601B/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg24/BRD2601B/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg24/BRD2601B/autogen/sl_event_handler.c b/matter/efr32/efr32mg24/BRD2601B/autogen/sl_event_handler.c index 1263fddd92..e313a27728 100644 --- a/matter/efr32/efr32mg24/BRD2601B/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg24/BRD2601B/autogen/sl_event_handler.c @@ -2,15 +2,16 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -36,12 +37,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -66,6 +68,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg24/BRD2601B/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg24/BRD2601B/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2601B/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD2601B/config/circular_queue_config.h b/matter/efr32/efr32mg24/BRD2601B/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2601B/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD2601B/config/sl_board_control_config.h b/matter/efr32/efr32mg24/BRD2601B/config/sl_board_control_config.h new file mode 100644 index 0000000000..01c4c6908b --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2601B/config/sl_board_control_config.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Barometric Pressure sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_PRESSURE 0 + +// Enable Light sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_LIGHT 0 + +// Enable Inertial Measurement Unit +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_IMU 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortC +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 9 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortC +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 9 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_PRESSURE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_PRESSURE] +#define SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT gpioPortC +#define SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN 9 +// [GPIO_SL_BOARD_ENABLE_SENSOR_PRESSURE]$ + +// SL_BOARD_ENABLE_SENSOR_LIGHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_LIGHT] +#define SL_BOARD_ENABLE_SENSOR_LIGHT_PORT gpioPortC +#define SL_BOARD_ENABLE_SENSOR_LIGHT_PIN 9 +// [GPIO_SL_BOARD_ENABLE_SENSOR_LIGHT]$ + +// SL_BOARD_ENABLE_SENSOR_IMU +// $[GPIO_SL_BOARD_ENABLE_SENSOR_IMU] +#define SL_BOARD_ENABLE_SENSOR_IMU_PORT gpioPortC +#define SL_BOARD_ENABLE_SENSOR_IMU_PIN 9 +// [GPIO_SL_BOARD_ENABLE_SENSOR_IMU]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortC +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 8 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2601B/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg24/BRD2601B/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..cd39c270af --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2601B/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD2601B/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg24/BRD2601B/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2601B/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_hfxo_config.h b/matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_dcdc_config.h similarity index 65% rename from matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_hfxo_config.h rename to matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_dcdc_config.h index 2ad97ef495..4fb88397d2 100644 --- a/matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_hfxo_config.h +++ b/matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_dcdc_config.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief DEVICE_INIT_HFXO Config + * @brief DEVICE_INIT_DCDC Config ******************************************************************************* * # License * Copyright 2022 Silicon Laboratories Inc. www.silabs.com @@ -28,30 +28,31 @@ * ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> -// Mode +// Enable DC/DC Converter // -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 87 +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 // <<< end of configuration section >>> -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2601B/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg24/BRD2601B/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg24/BRD2601B/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg24/BRD2601B/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/efr32mg24/BRD2703A/autogen/sl_board_default_init.c b/matter/efr32/efr32mg24/BRD2703A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..c3a6b48665 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2703A/autogen/sl_board_default_init.c @@ -0,0 +1,34 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ +} diff --git a/matter/efr32/efr32mg24/BRD2703A/autogen/sl_component_catalog.h b/matter/efr32/efr32mg24/BRD2703A/autogen/sl_component_catalog.h index 6f24244a52..26e5a7a321 100644 --- a/matter/efr32/efr32mg24/BRD2703A/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg24/BRD2703A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg24/BRD2703A/autogen/sl_event_handler.c b/matter/efr32/efr32mg24/BRD2703A/autogen/sl_event_handler.c index 8f74982292..5fb9720854 100644 --- a/matter/efr32/efr32mg24/BRD2703A/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg24/BRD2703A/autogen/sl_event_handler.c @@ -2,15 +2,16 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -33,12 +34,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -62,6 +64,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg24/BRD2703A/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg24/BRD2703A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2703A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD2703A/config/circular_queue_config.h b/matter/efr32/efr32mg24/BRD2703A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2703A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD2703A/config/sl_board_control_config.h b/matter/efr32/efr32mg24/BRD2703A/config/sl_board_control_config.h new file mode 100644 index 0000000000..ad7793aa7e --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2703A/config/sl_board_control_config.h @@ -0,0 +1,42 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2703A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg24/BRD2703A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..516ec1173a --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2703A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 100 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 37 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD2703A/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg24/BRD2703A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD2703A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_hfxo_config.h b/matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_dcdc_config.h similarity index 65% rename from matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_hfxo_config.h rename to matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_dcdc_config.h index 9f3b31ed85..4fb88397d2 100644 --- a/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_hfxo_config.h +++ b/matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_dcdc_config.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief DEVICE_INIT_HFXO Config + * @brief DEVICE_INIT_DCDC Config ******************************************************************************* * # License * Copyright 2022 Silicon Laboratories Inc. www.silabs.com @@ -28,30 +28,31 @@ * ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> -// Mode +// Enable DC/DC Converter // -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 95 +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 // <<< end of configuration section >>> -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2703A/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg24/BRD2703A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg24/BRD2703A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg24/BRD2703A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/efr32mg24/BRD4186A/autogen/sl_board_default_init.c b/matter/efr32/efr32mg24/BRD4186A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/efr32mg24/BRD4186A/autogen/sl_component_catalog.h b/matter/efr32/efr32mg24/BRD4186A/autogen/sl_component_catalog.h index a71fd1d9e9..74ba9d159b 100644 --- a/matter/efr32/efr32mg24/BRD4186A/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg24/BRD4186A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg24/BRD4186A/autogen/sl_event_handler.c b/matter/efr32/efr32mg24/BRD4186A/autogen/sl_event_handler.c index 54b50884df..064b0bf1d1 100644 --- a/matter/efr32/efr32mg24/BRD4186A/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg24/BRD4186A/autogen/sl_event_handler.c @@ -2,15 +2,16 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -36,12 +37,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -68,6 +70,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg24/BRD4186A/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg24/BRD4186A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4186A/config/circular_queue_config.h b/matter/efr32/efr32mg24/BRD4186A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4186A/config/sl_board_control_config.h b/matter/efr32/efr32mg24/BRD4186A/config/sl_board_control_config.h new file mode 100644 index 0000000000..e175eb54c9 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186A/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4186A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg24/BRD4186A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..c8a5581741 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 87 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 36 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4186A/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg24/BRD4186A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_hfxo_config.h b/matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_dcdc_config.h similarity index 65% rename from matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_hfxo_config.h rename to matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_dcdc_config.h index 2ad97ef495..4fb88397d2 100644 --- a/matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_hfxo_config.h +++ b/matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_dcdc_config.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief DEVICE_INIT_HFXO Config + * @brief DEVICE_INIT_DCDC Config ******************************************************************************* * # License * Copyright 2022 Silicon Laboratories Inc. www.silabs.com @@ -28,30 +28,31 @@ * ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> -// Mode +// Enable DC/DC Converter // -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 87 +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 // <<< end of configuration section >>> -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg24/BRD4186A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4186A/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg24/BRD4186A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg24/BRD4186A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg24/BRD4186A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/efr32mg24/BRD4186C/autogen/sl_board_default_init.c b/matter/efr32/efr32mg24/BRD4186C/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186C/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/efr32mg24/BRD4186C/autogen/sl_component_catalog.h b/matter/efr32/efr32mg24/BRD4186C/autogen/sl_component_catalog.h index 81e17adcec..09d8a38733 100644 --- a/matter/efr32/efr32mg24/BRD4186C/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg24/BRD4186C/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg24/BRD4186C/autogen/sl_event_handler.c b/matter/efr32/efr32mg24/BRD4186C/autogen/sl_event_handler.c index 9e9f4882d2..d8ad57994a 100644 --- a/matter/efr32/efr32mg24/BRD4186C/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg24/BRD4186C/autogen/sl_event_handler.c @@ -2,17 +2,18 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #if !RSI_BLE_ENABLE #include "sl_rail_util_power_manager_init.h" #endif #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -41,12 +42,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -80,6 +82,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg24/BRD4186C/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg24/BRD4186C/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186C/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4186C/config/circular_queue_config.h b/matter/efr32/efr32mg24/BRD4186C/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186C/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_board_control_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_board_control_config.h new file mode 100644 index 0000000000..e175eb54c9 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186C/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_bt_rtos_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_bt_rtos_config.h index a0ef9988b1..c87ca11c3b 100644 --- a/matter/efr32/efr32mg24/BRD4186C/config/sl_bt_rtos_config.h +++ b/matter/efr32/efr32mg24/BRD4186C/config/sl_bt_rtos_config.h @@ -46,7 +46,7 @@ // Default: 1000 // Define the stack size of the Bluetooth link layer task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE (1024) +#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE 1024 // Bluetooth host stack task priority // Default: 51 (CMSIS-RTOS2 osPriorityRealtime3) @@ -58,7 +58,7 @@ // Default: 2000 // Define the stack size of the Bluetooth host stack task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE (2048) +#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE 2048 // Bluetooth event handler task priority // Default: 50 (CMSIS-RTOS2 osPriorityRealtime2) @@ -71,7 +71,7 @@ // Default: 1000 // Define the stack size of the Bluetooth event handler task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE (1536) +#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE 1536 // End Priority Configuration for Bluetooth RTOS Tasks diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..c8a5581741 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186C/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 87 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 36 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186C/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_debug_swo_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_debug_swo_config.h new file mode 100644 index 0000000000..34761be508 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4186C/config/sl_debug_swo_config.h @@ -0,0 +1,99 @@ +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEBUG_SWO_CONFIG_H +#define SL_DEBUG_SWO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO Configuration + +// SWO Frequency +// Must be 875 kHz for communication with Silicon Labs debuggers +// Default: 875000 +#define SL_DEBUG_SWO_FREQ 875000 + +// Enable interrupt event trace +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_IRQ 0 + +// Enable Program Counter samples +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_PC 0 + +// SWO debug sample intervals +// <64=> 64 +// <128=> 128 +// <192=> 192 +// <256=> 256 +// <320=> 320 +// <384=> 384 +// <448=> 448 +// <512=> 512 +// <576=> 576 +// <640=> 640 +// <704=> 704 +// <768=> 768 +// <832=> 832 +// <896=> 896 +// <960=> 960 +// <1024=> 1024 +// <2048=> 2048 +// <3072=> 3072 +// <4096=> 4096 +// <5102=> 5102 +// <6144=> 6144 +// <7168=> 7168 +// <8192=> 8192 +// <9216=> 9216 +// <10240=> 10240 +// <11264=> 11264 +// <12288=> 12288 +// <13312=> 13312 +// <14336=> 14336 +// <15360=> 15360 +// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 +// Default: 15360 +#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEBUG +// $[GPIO_SL_DEBUG] +#define SL_DEBUG_PERIPHERAL GPIO + +#define SL_DEBUG_SWV_PORT gpioPortA +#define SL_DEBUG_SWV_PIN 3 +// [GPIO_SL_DEBUG]$ +// <<< sl:end pin_tool >>> + +#endif // SL_DEBUG_SWO_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_hfxo_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_dcdc_config.h similarity index 65% rename from matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_hfxo_config.h rename to matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_dcdc_config.h index 9f3b31ed85..4fb88397d2 100644 --- a/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_hfxo_config.h +++ b/matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_dcdc_config.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief DEVICE_INIT_HFXO Config + * @brief DEVICE_INIT_DCDC Config ******************************************************************************* * # License * Copyright 2022 Silicon Laboratories Inc. www.silabs.com @@ -28,30 +28,31 @@ * ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> -// Mode +// Enable DC/DC Converter // -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 95 +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 // <<< end of configuration section >>> -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg24/BRD4186C/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4186C/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg24/BRD4186C/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg24/BRD4186C/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg24/BRD4186C/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/efr32mg24/BRD4187A/autogen/sl_board_default_init.c b/matter/efr32/efr32mg24/BRD4187A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/efr32mg24/BRD4187A/autogen/sl_component_catalog.h b/matter/efr32/efr32mg24/BRD4187A/autogen/sl_component_catalog.h index 81e17adcec..09d8a38733 100644 --- a/matter/efr32/efr32mg24/BRD4187A/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg24/BRD4187A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg24/BRD4187A/autogen/sl_event_handler.c b/matter/efr32/efr32mg24/BRD4187A/autogen/sl_event_handler.c index 9506096174..00e3f5f54b 100644 --- a/matter/efr32/efr32mg24/BRD4187A/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg24/BRD4187A/autogen/sl_event_handler.c @@ -2,17 +2,18 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #if !RSI_BLE_ENABLE #include "sl_rail_util_power_manager_init.h" #endif #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -44,12 +45,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -81,6 +83,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg24/BRD4187A/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg24/BRD4187A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4187A/config/circular_queue_config.h b/matter/efr32/efr32mg24/BRD4187A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4187A/config/sl_board_control_config.h b/matter/efr32/efr32mg24/BRD4187A/config/sl_board_control_config.h new file mode 100644 index 0000000000..e175eb54c9 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187A/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4187A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg24/BRD4187A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..278e4b5243 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 95 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 44 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4187A/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg24/BRD4187A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_dcdc_config.h b/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..695e68ec96 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 9 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg24/BRD4187A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4187A/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg24/BRD4187A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg24/BRD4187A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg24/BRD4187A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/efr32mg24/BRD4187C/autogen/sl_board_default_init.c b/matter/efr32/efr32mg24/BRD4187C/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187C/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/efr32mg24/BRD4187C/autogen/sl_component_catalog.h b/matter/efr32/efr32mg24/BRD4187C/autogen/sl_component_catalog.h index 81e17adcec..09d8a38733 100644 --- a/matter/efr32/efr32mg24/BRD4187C/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg24/BRD4187C/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg24/BRD4187C/autogen/sl_event_handler.c b/matter/efr32/efr32mg24/BRD4187C/autogen/sl_event_handler.c index f11bb6587e..3714b4a3f1 100644 --- a/matter/efr32/efr32mg24/BRD4187C/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg24/BRD4187C/autogen/sl_event_handler.c @@ -2,17 +2,18 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #if !RSI_BLE_ENABLE #include "sl_rail_util_power_manager_init.h" #endif // !RSI_BLE_ENABLE #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -41,12 +42,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -80,6 +82,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg24/BRD4187C/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg24/BRD4187C/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187C/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4187C/config/circular_queue_config.h b/matter/efr32/efr32mg24/BRD4187C/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187C/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg24/BRD4187C/config/sl_board_control_config.h b/matter/efr32/efr32mg24/BRD4187C/config/sl_board_control_config.h new file mode 100644 index 0000000000..e175eb54c9 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187C/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4187C/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg24/BRD4187C/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..278e4b5243 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187C/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 95 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 44 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4187C/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg24/BRD4187C/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187C/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_dcdc_config.h b/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..695e68ec96 --- /dev/null +++ b/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 9 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg24/BRD4187C/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD4187C/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg24/BRD4187C/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg24/BRD4187C/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg24/BRD4187C/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/efr32mg26/BRD2608A/autogen/sl_board_default_init.c b/matter/efr32/efr32mg26/BRD2608A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..c3a6b48665 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD2608A/autogen/sl_board_default_init.c @@ -0,0 +1,34 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ +} diff --git a/matter/efr32/efr32mg26/BRD2608A/autogen/sl_component_catalog.h b/matter/efr32/efr32mg26/BRD2608A/autogen/sl_component_catalog.h index 18a8ca1e44..1d31ccb7e9 100644 --- a/matter/efr32/efr32mg26/BRD2608A/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg26/BRD2608A/autogen/sl_component_catalog.h @@ -14,10 +14,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg26/BRD2608A/autogen/sl_event_handler.c b/matter/efr32/efr32mg26/BRD2608A/autogen/sl_event_handler.c index 9e9f4882d2..d8ad57994a 100644 --- a/matter/efr32/efr32mg26/BRD2608A/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg26/BRD2608A/autogen/sl_event_handler.c @@ -2,17 +2,18 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #if !RSI_BLE_ENABLE #include "sl_rail_util_power_manager_init.h" #endif #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -41,12 +42,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -80,6 +82,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg26/BRD4116A/autogen/sl_board_default_init.c b/matter/efr32/efr32mg26/BRD4116A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4116A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/efr32mg26/BRD4116A/autogen/sl_component_catalog.h b/matter/efr32/efr32mg26/BRD4116A/autogen/sl_component_catalog.h index 426f1dd298..fde042621e 100644 --- a/matter/efr32/efr32mg26/BRD4116A/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg26/BRD4116A/autogen/sl_component_catalog.h @@ -14,10 +14,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg26/BRD4116A/autogen/sl_event_handler.c b/matter/efr32/efr32mg26/BRD4116A/autogen/sl_event_handler.c index 9e9f4882d2..d8ad57994a 100644 --- a/matter/efr32/efr32mg26/BRD4116A/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg26/BRD4116A/autogen/sl_event_handler.c @@ -2,17 +2,18 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #if !RSI_BLE_ENABLE #include "sl_rail_util_power_manager_init.h" #endif #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -41,12 +42,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -80,6 +82,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg26/BRD4116A/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg26/BRD4116A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4116A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg26/BRD4116A/config/circular_queue_config.h b/matter/efr32/efr32mg26/BRD4116A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4116A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_board_control_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_board_control_config.h new file mode 100644 index 0000000000..e175eb54c9 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4116A/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_bt_rtos_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_bt_rtos_config.h index a0ef9988b1..c87ca11c3b 100644 --- a/matter/efr32/efr32mg26/BRD4116A/config/sl_bt_rtos_config.h +++ b/matter/efr32/efr32mg26/BRD4116A/config/sl_bt_rtos_config.h @@ -46,7 +46,7 @@ // Default: 1000 // Define the stack size of the Bluetooth link layer task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE (1024) +#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE 1024 // Bluetooth host stack task priority // Default: 51 (CMSIS-RTOS2 osPriorityRealtime3) @@ -58,7 +58,7 @@ // Default: 2000 // Define the stack size of the Bluetooth host stack task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE (2048) +#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE 2048 // Bluetooth event handler task priority // Default: 50 (CMSIS-RTOS2 osPriorityRealtime2) @@ -71,7 +71,7 @@ // Default: 1000 // Define the stack size of the Bluetooth event handler task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE (1536) +#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE 1536 // End Priority Configuration for Bluetooth RTOS Tasks diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..49ffefdd1d --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4116A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 90 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 44 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..0dc99bc7b9 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4116A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,293 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_dcdc_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..4fb88397d2 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_hfxo_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_hfxo_config.h deleted file mode 100644 index b22887f972..0000000000 --- a/matter/efr32/efr32mg26/BRD4116A/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 90 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4116A/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg26/BRD4116A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg26/BRD4116A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg26/BRD4116A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/efr32mg26/BRD4117A/autogen/sl_board_default_init.c b/matter/efr32/efr32mg26/BRD4117A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4117A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/efr32mg26/BRD4117A/autogen/sl_component_catalog.h b/matter/efr32/efr32mg26/BRD4117A/autogen/sl_component_catalog.h index 426f1dd298..fde042621e 100644 --- a/matter/efr32/efr32mg26/BRD4117A/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg26/BRD4117A/autogen/sl_component_catalog.h @@ -14,10 +14,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg26/BRD4117A/autogen/sl_event_handler.c b/matter/efr32/efr32mg26/BRD4117A/autogen/sl_event_handler.c index 9e9f4882d2..d8ad57994a 100644 --- a/matter/efr32/efr32mg26/BRD4117A/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg26/BRD4117A/autogen/sl_event_handler.c @@ -2,17 +2,18 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #if !RSI_BLE_ENABLE #include "sl_rail_util_power_manager_init.h" #endif #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -41,12 +42,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -80,6 +82,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg26/BRD4118A/autogen/sl_board_default_init.c b/matter/efr32/efr32mg26/BRD4118A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4118A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/efr32mg26/BRD4118A/autogen/sl_component_catalog.h b/matter/efr32/efr32mg26/BRD4118A/autogen/sl_component_catalog.h index 426f1dd298..fde042621e 100644 --- a/matter/efr32/efr32mg26/BRD4118A/autogen/sl_component_catalog.h +++ b/matter/efr32/efr32mg26/BRD4118A/autogen/sl_component_catalog.h @@ -14,10 +14,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/efr32mg26/BRD4118A/autogen/sl_event_handler.c b/matter/efr32/efr32mg26/BRD4118A/autogen/sl_event_handler.c index 9e9f4882d2..d8ad57994a 100644 --- a/matter/efr32/efr32mg26/BRD4118A/autogen/sl_event_handler.c +++ b/matter/efr32/efr32mg26/BRD4118A/autogen/sl_event_handler.c @@ -2,17 +2,18 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "pa_conversions_efr32.h" #if !RSI_BLE_ENABLE #include "sl_rail_util_power_manager_init.h" #endif #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -41,12 +42,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -80,6 +82,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/efr32mg26/BRD4118A/config/buffer_pool_allocator_config.h b/matter/efr32/efr32mg26/BRD4118A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4118A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/efr32mg26/BRD4118A/config/circular_queue_config.h b/matter/efr32/efr32mg26/BRD4118A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4118A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_board_control_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_board_control_config.h new file mode 100644 index 0000000000..213305b870 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4118A/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortC +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 10 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_bt_rtos_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_bt_rtos_config.h index a0ef9988b1..c87ca11c3b 100644 --- a/matter/efr32/efr32mg26/BRD4118A/config/sl_bt_rtos_config.h +++ b/matter/efr32/efr32mg26/BRD4118A/config/sl_bt_rtos_config.h @@ -46,7 +46,7 @@ // Default: 1000 // Define the stack size of the Bluetooth link layer task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE (1024) +#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE 1024 // Bluetooth host stack task priority // Default: 51 (CMSIS-RTOS2 osPriorityRealtime3) @@ -58,7 +58,7 @@ // Default: 2000 // Define the stack size of the Bluetooth host stack task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE (2048) +#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE 2048 // Bluetooth event handler task priority // Default: 50 (CMSIS-RTOS2 osPriorityRealtime2) @@ -71,7 +71,7 @@ // Default: 1000 // Define the stack size of the Bluetooth event handler task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE (1536) +#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE 1536 // End Priority Configuration for Bluetooth RTOS Tasks diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..e325b6cd84 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4118A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 82 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 37 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_clock_manager_tree_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..0dc99bc7b9 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4118A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,293 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for LCDCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for LDCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE +#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_dcdc_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..4fb88397d2 --- /dev/null +++ b/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_dpll_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_hfxo_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_hfxo_config.h deleted file mode 100644 index 15eeb6e2e7..0000000000 --- a/matter/efr32/efr32mg26/BRD4118A/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 82 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/matter/efr32/efr32mg26/BRD4118A/config/sl_memory_manager_region_config.h b/matter/efr32/efr32mg26/BRD4118A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/efr32mg26/BRD4118A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/efr32mg26/BRD4118A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/mgm24/BRD2704A/autogen/sl_board_default_init.c b/matter/efr32/mgm24/BRD2704A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..c3a6b48665 --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/autogen/sl_board_default_init.c @@ -0,0 +1,34 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ +} diff --git a/matter/efr32/mgm24/BRD2704A/autogen/sl_component_catalog.h b/matter/efr32/mgm24/BRD2704A/autogen/sl_component_catalog.h index 9b40bff892..6ece55491e 100644 --- a/matter/efr32/mgm24/BRD2704A/autogen/sl_component_catalog.h +++ b/matter/efr32/mgm24/BRD2704A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/mgm24/BRD2704A/autogen/sl_event_handler.c b/matter/efr32/mgm24/BRD2704A/autogen/sl_event_handler.c index 53c007401a..5252ea9648 100644 --- a/matter/efr32/mgm24/BRD2704A/autogen/sl_event_handler.c +++ b/matter/efr32/mgm24/BRD2704A/autogen/sl_event_handler.c @@ -2,16 +2,17 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "sl_fem_util.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -31,12 +32,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -57,6 +59,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/mgm24/BRD2704A/autogen/sl_simple_led_instances.c b/matter/efr32/mgm24/BRD2704A/autogen/sl_simple_led_instances.c index be4be8b8ff..86a8e9e52a 100644 --- a/matter/efr32/mgm24/BRD2704A/autogen/sl_simple_led_instances.c +++ b/matter/efr32/mgm24/BRD2704A/autogen/sl_simple_led_instances.c @@ -37,7 +37,6 @@ #endif #include "sl_simple_led_led0_config.h" -#include "sl_simple_led_led1_config.h" sl_simple_led_context_t simple_led0_context = { .port = SL_SIMPLE_LED_LED0_PORT, @@ -53,28 +52,12 @@ const sl_led_t sl_led_led0 = { .toggle = sl_simple_led_toggle, .get_state = sl_simple_led_get_state, }; -sl_simple_led_context_t simple_led1_context = { - .port = SL_SIMPLE_LED_LED1_PORT, - .pin = SL_SIMPLE_LED_LED1_PIN, - .polarity = SL_SIMPLE_LED_LED1_POLARITY, -}; - -const sl_led_t sl_led_led1 = { - .context = &simple_led1_context, - .init = sl_simple_led_init, - .turn_on = sl_simple_led_turn_on, - .turn_off = sl_simple_led_turn_off, - .toggle = sl_simple_led_toggle, - .get_state = sl_simple_led_get_state, -}; const sl_led_t *sl_simple_led_array[] = { - &sl_led_led0, - &sl_led_led1 + &sl_led_led0 }; void sl_simple_led_init_instances(void) { sl_led_init(&sl_led_led0); - sl_led_init(&sl_led_led1); } diff --git a/matter/efr32/mgm24/BRD2704A/config/buffer_pool_allocator_config.h b/matter/efr32/mgm24/BRD2704A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD2704A/config/circular_queue_config.h b/matter/efr32/mgm24/BRD2704A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_board_control_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_board_control_config.h new file mode 100644 index 0000000000..ad7793aa7e --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/config/sl_board_control_config.h @@ -0,0 +1,42 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..bb5ea633a2 --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 0 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_clock_manager_tree_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..7f2199791a --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_device_init_dcdc_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..8904e24d82 --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,28 @@ +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 3 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_device_init_dpll_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/mgm24/BRD2704A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_device_init_hfxo_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_device_init_hfxo_config.h deleted file mode 100644 index dcf6e51cb9..0000000000 --- a/matter/efr32/mgm24/BRD2704A/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_HFXO_PRECISION 500 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 140 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_memory_manager_region_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/mgm24/BRD2704A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/mgm24/BRD2704A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/mgm24/BRD2704A/config/sl_rail_util_rssi_config.h b/matter/efr32/mgm24/BRD2704A/config/sl_rail_util_rssi_config.h new file mode 100644 index 0000000000..fcc53de024 --- /dev/null +++ b/matter/efr32/mgm24/BRD2704A/config/sl_rail_util_rssi_config.h @@ -0,0 +1,44 @@ +/***************************************************************************/ /** + * @file + * @brief RSSI configuration header file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_RSSI_CONFIG_H +#define SL_RAIL_UTIL_RSSI_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RSSI Offset Configuration + +// Software RSSI offset value +// Default: 0 +#define SL_RAIL_UTIL_RSSI_OFFSET 0 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_RSSI_CONFIG_H \ No newline at end of file diff --git a/matter/efr32/mgm24/BRD4316A/autogen/sl_board_default_init.c b/matter/efr32/mgm24/BRD4316A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/mgm24/BRD4316A/autogen/sl_component_catalog.h b/matter/efr32/mgm24/BRD4316A/autogen/sl_component_catalog.h index c39d43cc6e..533c965231 100644 --- a/matter/efr32/mgm24/BRD4316A/autogen/sl_component_catalog.h +++ b/matter/efr32/mgm24/BRD4316A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT @@ -28,9 +29,15 @@ #define SL_CATALOG_HFXO_MANAGER_PRESENT #define SL_CATALOG_INTERRUPT_MANAGER_PRESENT #define SL_CATALOG_IOSTREAM_PRESENT -#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT #define SL_CATALOG_MEMORY_MANAGER_PRESENT #define SL_CATALOG_MEMORY_PROFILER_API_PRESENT +#ifdef DISPLAY_ENABLED +#define SL_CATALOG_DMD_MEMLCD_PRESENT +#define SL_CATALOG_MEMLCD_USART_PRESENT +#endif +#ifdef CONFIG_USE_EXTERNAL_FLASH +#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT +#endif // CONFIG_USE_EXTERNAL_FLASH #define SL_CATALOG_NVM3_PRESENT #define SL_CATALOG_POWER_MANAGER_PRESENT #define SL_CATALOG_PSA_CRYPTO_PRESENT @@ -45,6 +52,8 @@ #define SL_CATALOG_SIMPLE_BUTTON_BTN1_PRESENT #define SL_CATALOG_SLEEPTIMER_PRESENT #define SL_CATALOG_SLI_PROTOCOL_CRYPTO_PRESENT +#if defined(CONFIG_ENABLE_UART) #define SL_CATALOG_UARTDRV_EUSART_PRESENT +#endif #endif // SL_COMPONENT_CATALOG_H diff --git a/matter/efr32/mgm24/BRD4316A/autogen/sl_event_handler.c b/matter/efr32/mgm24/BRD4316A/autogen/sl_event_handler.c index c5dd61ff44..3ce21c0ef0 100644 --- a/matter/efr32/mgm24/BRD4316A/autogen/sl_event_handler.c +++ b/matter/efr32/mgm24/BRD4316A/autogen/sl_event_handler.c @@ -2,16 +2,17 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "sl_fem_util.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -34,12 +35,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -65,6 +67,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/mgm24/BRD4316A/config/buffer_pool_allocator_config.h b/matter/efr32/mgm24/BRD4316A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4316A/config/circular_queue_config.h b/matter/efr32/mgm24/BRD4316A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4316A/config/psa_crypto_config.h b/matter/efr32/mgm24/BRD4316A/config/psa_crypto_config.h index 44dc70284f..20703b41d2 100644 --- a/matter/efr32/mgm24/BRD4316A/config/psa_crypto_config.h +++ b/matter/efr32/mgm24/BRD4316A/config/psa_crypto_config.h @@ -56,7 +56,7 @@ // If no v1 files are used, its support can be disabled for space // optimization. // Default: 0 -#define SL_PSA_ITS_SUPPORT_V1_DRIVER 1 +#define SL_PSA_ITS_SUPPORT_V1_DRIVER 0 // Enable V2 ITS Driver Support <0-1> // Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys @@ -69,7 +69,7 @@ // driver before in GSDK 4.1.x and earlier, or the keys has been already // migrated. // Default: 0 -#define SL_PSA_ITS_SUPPORT_V2_DRIVER 1 +#define SL_PSA_ITS_SUPPORT_V2_DRIVER 0 // Enable support for V3 ITS Driver <0-1> // Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_board_control_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_board_control_config.h new file mode 100644 index 0000000000..4bf1c27bd7 --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 4 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortD +#define SL_BOARD_ENABLE_DISPLAY_PIN 3 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 2 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_bt_rtos_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_bt_rtos_config.h index a0ef9988b1..c87ca11c3b 100644 --- a/matter/efr32/mgm24/BRD4316A/config/sl_bt_rtos_config.h +++ b/matter/efr32/mgm24/BRD4316A/config/sl_bt_rtos_config.h @@ -46,7 +46,7 @@ // Default: 1000 // Define the stack size of the Bluetooth link layer task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE (1024) +#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE 1024 // Bluetooth host stack task priority // Default: 51 (CMSIS-RTOS2 osPriorityRealtime3) @@ -58,7 +58,7 @@ // Default: 2000 // Define the stack size of the Bluetooth host stack task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE (2048) +#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE 2048 // Bluetooth event handler task priority // Default: 50 (CMSIS-RTOS2 osPriorityRealtime2) @@ -71,7 +71,7 @@ // Default: 1000 // Define the stack size of the Bluetooth event handler task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE (1536) +#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE 1536 // End Priority Configuration for Bluetooth RTOS Tasks diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..cd39c270af --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_clock_manager_tree_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_device_init_dcdc_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..059d2d670c --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 6 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_device_init_dpll_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/mgm24/BRD4316A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_device_init_hfxo_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_device_init_hfxo_config.h deleted file mode 100644 index 78b14ee253..0000000000 --- a/matter/efr32/mgm24/BRD4316A/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 140 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_hfxo_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_memlcd_usart_config.h similarity index 57% rename from matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_hfxo_config.h rename to matter/efr32/mgm24/BRD4316A/config/sl_memlcd_usart_config.h index 78b14ee253..8266448b81 100644 --- a/matter/efr32/efr32mg24/BRD2601B/config/sl_device_init_hfxo_config.h +++ b/matter/efr32/mgm24/BRD4316A/config/sl_memlcd_usart_config.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief DEVICE_INIT_HFXO Config + * @brief SPI abstraction used by memory lcd display ******************************************************************************* * # License * Copyright 2022 Silicon Laboratories Inc. www.silabs.com @@ -28,30 +28,39 @@ * ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H -// <<< Use Configuration Wizard in Context Menu >>> +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal +// USART0 TX on PC00 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 0 -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 +// USART0 CLK on PC02 +#define SL_MEMLCD_SPI_CLK_PORT gpioPortC +#define SL_MEMLCD_SPI_CLK_PIN 2 -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 +// [USART_SL_MEMLCD_SPI]$ -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 140 +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 6 -// <<< end of configuration section >>> +// [GPIO_SL_MEMLCD_SPI_CS]$ -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortA +#define SL_MEMLCD_EXTCOMIN_PIN 0 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_memory_manager_region_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/mgm24/BRD4316A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/mgm24/BRD4316A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_mx25_flash_shutdown_usart_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..c48ea84a26 --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4316A/config/sl_rail_util_rssi_config.h b/matter/efr32/mgm24/BRD4316A/config/sl_rail_util_rssi_config.h new file mode 100644 index 0000000000..fcc53de024 --- /dev/null +++ b/matter/efr32/mgm24/BRD4316A/config/sl_rail_util_rssi_config.h @@ -0,0 +1,44 @@ +/***************************************************************************/ /** + * @file + * @brief RSSI configuration header file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_RSSI_CONFIG_H +#define SL_RAIL_UTIL_RSSI_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RSSI Offset Configuration + +// Software RSSI offset value +// Default: 0 +#define SL_RAIL_UTIL_RSSI_OFFSET 0 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_RSSI_CONFIG_H \ No newline at end of file diff --git a/matter/efr32/mgm24/BRD4317A/autogen/sl_board_default_init.c b/matter/efr32/mgm24/BRD4317A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/mgm24/BRD4317A/autogen/sl_component_catalog.h b/matter/efr32/mgm24/BRD4317A/autogen/sl_component_catalog.h index fff712b0b1..533c965231 100644 --- a/matter/efr32/mgm24/BRD4317A/autogen/sl_component_catalog.h +++ b/matter/efr32/mgm24/BRD4317A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/mgm24/BRD4317A/autogen/sl_event_handler.c b/matter/efr32/mgm24/BRD4317A/autogen/sl_event_handler.c index 3473ae02ca..28e07478a4 100644 --- a/matter/efr32/mgm24/BRD4317A/autogen/sl_event_handler.c +++ b/matter/efr32/mgm24/BRD4317A/autogen/sl_event_handler.c @@ -2,16 +2,17 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "sl_fem_util.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -36,12 +37,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -67,6 +69,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/mgm24/BRD4317A/config/buffer_pool_allocator_config.h b/matter/efr32/mgm24/BRD4317A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4317A/config/circular_queue_config.h b/matter/efr32/mgm24/BRD4317A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_board_control_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_board_control_config.h new file mode 100644 index 0000000000..4bf1c27bd7 --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 4 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortD +#define SL_BOARD_ENABLE_DISPLAY_PIN 3 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 2 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_bt_rtos_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_bt_rtos_config.h index a0ef9988b1..c87ca11c3b 100644 --- a/matter/efr32/mgm24/BRD4317A/config/sl_bt_rtos_config.h +++ b/matter/efr32/mgm24/BRD4317A/config/sl_bt_rtos_config.h @@ -46,7 +46,7 @@ // Default: 1000 // Define the stack size of the Bluetooth link layer task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE (1024) +#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE 1024 // Bluetooth host stack task priority // Default: 51 (CMSIS-RTOS2 osPriorityRealtime3) @@ -58,7 +58,7 @@ // Default: 2000 // Define the stack size of the Bluetooth host stack task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE (2048) +#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE 2048 // Bluetooth event handler task priority // Default: 50 (CMSIS-RTOS2 osPriorityRealtime2) @@ -71,7 +71,7 @@ // Default: 1000 // Define the stack size of the Bluetooth event handler task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE (1536) +#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE 1536 // End Priority Configuration for Bluetooth RTOS Tasks diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..cd39c270af --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_clock_manager_tree_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_device_init_dcdc_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..35674eedf9 --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 3 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_device_init_dpll_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/mgm24/BRD4317A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_device_init_hfxo_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_device_init_hfxo_config.h deleted file mode 100644 index 78b14ee253..0000000000 --- a/matter/efr32/mgm24/BRD4317A/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 140 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_hfxo_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_memlcd_usart_config.h similarity index 57% rename from matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_hfxo_config.h rename to matter/efr32/mgm24/BRD4317A/config/sl_memlcd_usart_config.h index 0b35c5e78e..8266448b81 100644 --- a/matter/efr32/efr32mg24/BRD2703A/config/sl_device_init_hfxo_config.h +++ b/matter/efr32/mgm24/BRD4317A/config/sl_memlcd_usart_config.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief DEVICE_INIT_HFXO Config + * @brief SPI abstraction used by memory lcd display ******************************************************************************* * # License * Copyright 2022 Silicon Laboratories Inc. www.silabs.com @@ -28,30 +28,39 @@ * ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H -// <<< Use Configuration Wizard in Context Menu >>> +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal +// USART0 TX on PC00 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 0 -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 +// USART0 CLK on PC02 +#define SL_MEMLCD_SPI_CLK_PORT gpioPortC +#define SL_MEMLCD_SPI_CLK_PIN 2 -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 +// [USART_SL_MEMLCD_SPI]$ -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 100 +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 6 -// <<< end of configuration section >>> +// [GPIO_SL_MEMLCD_SPI_CS]$ -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortA +#define SL_MEMLCD_EXTCOMIN_PIN 0 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_memory_manager_region_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/mgm24/BRD4317A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/mgm24/BRD4317A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_mx25_flash_shutdown_usart_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..c48ea84a26 --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4317A/config/sl_rail_util_rssi_config.h b/matter/efr32/mgm24/BRD4317A/config/sl_rail_util_rssi_config.h new file mode 100644 index 0000000000..fcc53de024 --- /dev/null +++ b/matter/efr32/mgm24/BRD4317A/config/sl_rail_util_rssi_config.h @@ -0,0 +1,44 @@ +/***************************************************************************/ /** + * @file + * @brief RSSI configuration header file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_RSSI_CONFIG_H +#define SL_RAIL_UTIL_RSSI_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RSSI Offset Configuration + +// Software RSSI offset value +// Default: 0 +#define SL_RAIL_UTIL_RSSI_OFFSET 0 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_RSSI_CONFIG_H \ No newline at end of file diff --git a/matter/efr32/mgm24/BRD4318A/autogen/sl_board_default_init.c b/matter/efr32/mgm24/BRD4318A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/mgm24/BRD4318A/autogen/sl_component_catalog.h b/matter/efr32/mgm24/BRD4318A/autogen/sl_component_catalog.h index 0d213bc403..76cc564a4f 100644 --- a/matter/efr32/mgm24/BRD4318A/autogen/sl_component_catalog.h +++ b/matter/efr32/mgm24/BRD4318A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/mgm24/BRD4318A/autogen/sl_event_handler.c b/matter/efr32/mgm24/BRD4318A/autogen/sl_event_handler.c index 35362ef9d8..79fa5affbd 100644 --- a/matter/efr32/mgm24/BRD4318A/autogen/sl_event_handler.c +++ b/matter/efr32/mgm24/BRD4318A/autogen/sl_event_handler.c @@ -2,16 +2,17 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "sl_fem_util.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -35,12 +36,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -67,6 +69,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/mgm24/BRD4318A/config/buffer_pool_allocator_config.h b/matter/efr32/mgm24/BRD4318A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4318A/config/circular_queue_config.h b/matter/efr32/mgm24/BRD4318A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_board_control_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_board_control_config.h new file mode 100644 index 0000000000..e175eb54c9 --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_bt_rtos_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_bt_rtos_config.h index a0ef9988b1..c87ca11c3b 100644 --- a/matter/efr32/mgm24/BRD4318A/config/sl_bt_rtos_config.h +++ b/matter/efr32/mgm24/BRD4318A/config/sl_bt_rtos_config.h @@ -46,7 +46,7 @@ // Default: 1000 // Define the stack size of the Bluetooth link layer task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE (1024) +#define SL_BT_RTOS_LINK_LAYER_TASK_STACK_SIZE 1024 // Bluetooth host stack task priority // Default: 51 (CMSIS-RTOS2 osPriorityRealtime3) @@ -58,7 +58,7 @@ // Default: 2000 // Define the stack size of the Bluetooth host stack task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE (2048) +#define SL_BT_RTOS_HOST_STACK_TASK_STACK_SIZE 2048 // Bluetooth event handler task priority // Default: 50 (CMSIS-RTOS2 osPriorityRealtime2) @@ -71,7 +71,7 @@ // Default: 1000 // Define the stack size of the Bluetooth event handler task. The value is in bytes // and will be word aligned when it is applied at the task creation. -#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE (1536) +#define SL_BT_RTOS_EVENT_HANDLER_STACK_SIZE 1536 // End Priority Configuration for Bluetooth RTOS Tasks diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..cd39c270af --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_clock_manager_tree_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..ff9a50a254 --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_device_init_dcdc_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..059d2d670c --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 6 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_device_init_dpll_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/mgm24/BRD4318A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_device_init_hfxo_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_device_init_hfxo_config.h deleted file mode 100644 index dcf6e51cb9..0000000000 --- a/matter/efr32/mgm24/BRD4318A/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_HFXO_PRECISION 500 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 140 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_memlcd_usart_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..3490e3829e --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 1 + +// USART0 CLK on PC03 +#define SL_MEMLCD_SPI_CLK_PORT gpioPortC +#define SL_MEMLCD_SPI_CLK_PIN 3 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortC +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_memory_manager_region_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/mgm24/BRD4318A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/mgm24/BRD4318A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_mx25_flash_shutdown_usart_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..3b217bb736 --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4318A/config/sl_rail_util_rssi_config.h b/matter/efr32/mgm24/BRD4318A/config/sl_rail_util_rssi_config.h new file mode 100644 index 0000000000..fcc53de024 --- /dev/null +++ b/matter/efr32/mgm24/BRD4318A/config/sl_rail_util_rssi_config.h @@ -0,0 +1,44 @@ +/***************************************************************************/ /** + * @file + * @brief RSSI configuration header file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_RSSI_CONFIG_H +#define SL_RAIL_UTIL_RSSI_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RSSI Offset Configuration + +// Software RSSI offset value +// Default: 0 +#define SL_RAIL_UTIL_RSSI_OFFSET 0 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_RSSI_CONFIG_H \ No newline at end of file diff --git a/matter/efr32/mgm24/BRD4319A/autogen/sl_board_default_init.c b/matter/efr32/mgm24/BRD4319A/autogen/sl_board_default_init.c new file mode 100644 index 0000000000..bd43db368b --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/matter/efr32/mgm24/BRD4319A/autogen/sl_component_catalog.h b/matter/efr32/mgm24/BRD4319A/autogen/sl_component_catalog.h index b803515cb0..120451711a 100644 --- a/matter/efr32/mgm24/BRD4319A/autogen/sl_component_catalog.h +++ b/matter/efr32/mgm24/BRD4319A/autogen/sl_component_catalog.h @@ -15,10 +15,11 @@ #define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT #define SL_CATALOG_BLUETOOTH_PRESENT #define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT #define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_EMLIB_RMU_PRESENT diff --git a/matter/efr32/mgm24/BRD4319A/autogen/sl_event_handler.c b/matter/efr32/mgm24/BRD4319A/autogen/sl_event_handler.c index cc58766f16..8f85b99455 100644 --- a/matter/efr32/mgm24/BRD4319A/autogen/sl_event_handler.c +++ b/matter/efr32/mgm24/BRD4319A/autogen/sl_event_handler.c @@ -2,16 +2,17 @@ #include "em_chip.h" #include "sl_interrupt_manager.h" +#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" #include "sl_clock_manager.h" #include "sl_hfxo_manager.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" #include "SEGGER_RTT.h" -#include "sl_memory_manager.h" #include "sl_fem_util.h" #include "pa_conversions_efr32.h" #include "sl_rail_util_power_manager_init.h" #include "sl_rail_util_pti.h" +#include "sl_board_control.h" #include "sl_bt_rtos_adaptation.h" #include "sl_sleeptimer.h" #include "gpiointerrupt.h" @@ -33,12 +34,13 @@ void sl_platform_init(void) { CHIP_Init(); sl_interrupt_manager_init(); + sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); sl_clock_manager_runtime_init(); sl_hfxo_manager_init_hardware(); - sl_device_init_hfxo(); - sl_device_init_dpll(); SEGGER_RTT_Init(); - sl_memory_init(); + sl_board_init(); nvm3_initDefault(); osKernelInitialize(); sl_power_manager_init(); @@ -61,6 +63,7 @@ void sl_driver_init(void) void sl_service_init(void) { + sl_board_configure_vcom(); sl_sleeptimer_init(); sl_hfxo_manager_init(); sl_mbedtls_init(); diff --git a/matter/efr32/mgm24/BRD4319A/config/buffer_pool_allocator_config.h b/matter/efr32/mgm24/BRD4319A/config/buffer_pool_allocator_config.h new file mode 100644 index 0000000000..2c3fd2e677 --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/buffer_pool_allocator_config.h @@ -0,0 +1,29 @@ +/***************************************************************************//** + * @file buffer_pool_allocator_config.h + * @brief Configuration file for buffer pool allocator. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __BUFFER_POOL_ALLOCATOR_CONFIG_H__ +#define __BUFFER_POOL_ALLOCATOR_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory Manager Configuration + +// Number Buffer Pools +// <0-256:1> +// Default: 5 +#define BUFFER_POOL_ALLOCATOR_POOL_SIZE 5 + +// Length of Each Buffer Pool +// <0-1024:1> +// Default: 256 +#define BUFFER_POOL_ALLOCATOR_BUFFER_SIZE_MAX 256 + +// Clear Each Newly Allocated Buffer +#define BUFFER_POOL_ALLOCATOR_CLEAR_ON_INIT 0 + +// +// <<< end of configuration section >>> + +#endif // __BUFFER_POOL_ALLOCATOR_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4319A/config/circular_queue_config.h b/matter/efr32/mgm24/BRD4319A/config/circular_queue_config.h new file mode 100644 index 0000000000..81a7173d6a --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/circular_queue_config.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * @file circular_queue_config.h + * @brief Configuration file for circular queue. + * @copyright Copyright 2015 Silicon Laboratories, Inc. www.silabs.com + ******************************************************************************/ + +#ifndef __CIRCULAR_QUEUE_CONFIG_H__ +#define __CIRCULAR_QUEUE_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +// Circular Queue Configuration + +// Max Queue Length +// <0-256:1> +// Default: 5 +#ifndef CIRCULAR_QUEUE_LEN_MAX +#define CIRCULAR_QUEUE_LEN_MAX 16 +#endif + +// +// <<< end of configuration section >>> + +#endif // __CIRCULAR_QUEUE_CONFIG_H__ diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_board_control_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_board_control_config.h new file mode 100644 index 0000000000..a1885def29 --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/sl_board_control_config.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortC +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_clock_manager_oscillator_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000000..bb5ea633a2 --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,321 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) +// Enable to configure HFXO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN 1 +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 0 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 1 +#endif + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_clock_manager_tree_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000000..7f2199791a --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/sl_clock_manager_tree_config.h @@ -0,0 +1,282 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_debug_swo_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_debug_swo_config.h new file mode 100644 index 0000000000..34761be508 --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/sl_debug_swo_config.h @@ -0,0 +1,99 @@ +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEBUG_SWO_CONFIG_H +#define SL_DEBUG_SWO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO Configuration + +// SWO Frequency +// Must be 875 kHz for communication with Silicon Labs debuggers +// Default: 875000 +#define SL_DEBUG_SWO_FREQ 875000 + +// Enable interrupt event trace +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_IRQ 0 + +// Enable Program Counter samples +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_PC 0 + +// SWO debug sample intervals +// <64=> 64 +// <128=> 128 +// <192=> 192 +// <256=> 256 +// <320=> 320 +// <384=> 384 +// <448=> 448 +// <512=> 512 +// <576=> 576 +// <640=> 640 +// <704=> 704 +// <768=> 768 +// <832=> 832 +// <896=> 896 +// <960=> 960 +// <1024=> 1024 +// <2048=> 2048 +// <3072=> 3072 +// <4096=> 4096 +// <5102=> 5102 +// <6144=> 6144 +// <7168=> 7168 +// <8192=> 8192 +// <9216=> 9216 +// <10240=> 10240 +// <11264=> 11264 +// <12288=> 12288 +// <13312=> 13312 +// <14336=> 14336 +// <15360=> 15360 +// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 +// Default: 15360 +#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEBUG +// $[GPIO_SL_DEBUG] +#define SL_DEBUG_PERIPHERAL GPIO + +#define SL_DEBUG_SWV_PORT gpioPortA +#define SL_DEBUG_SWV_PIN 3 +// [GPIO_SL_DEBUG]$ +// <<< sl:end pin_tool >>> + +#endif // SL_DEBUG_SWO_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_device_init_dcdc_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..7f308d3934 --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 0 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_device_init_dpll_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_device_init_dpll_config.h deleted file mode 100644 index eea3705c71..0000000000 --- a/matter/efr32/mgm24/BRD4319A/config/sl_device_init_dpll_config.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_device_init_hfxo_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_device_init_hfxo_config.h deleted file mode 100644 index 78b14ee253..0000000000 --- a/matter/efr32/mgm24/BRD4319A/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 140 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_memory_manager_region_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_memory_manager_region_config.h index f940d40ec4..f34bb11775 100644 --- a/matter/efr32/mgm24/BRD4319A/config/sl_memory_manager_region_config.h +++ b/matter/efr32/mgm24/BRD4319A/config/sl_memory_manager_region_config.h @@ -40,7 +40,7 @@ // The stack size configured here will be used by the stack that the // application uses when coming out of a reset. #ifndef SL_STACK_SIZE -#define SL_STACK_SIZE 0 +#define SL_STACK_SIZE 4608 #endif // diff --git a/matter/efr32/mgm24/BRD4319A/config/sl_rail_util_rssi_config.h b/matter/efr32/mgm24/BRD4319A/config/sl_rail_util_rssi_config.h new file mode 100644 index 0000000000..fcc53de024 --- /dev/null +++ b/matter/efr32/mgm24/BRD4319A/config/sl_rail_util_rssi_config.h @@ -0,0 +1,44 @@ +/***************************************************************************/ /** + * @file + * @brief RSSI configuration header file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_RSSI_CONFIG_H +#define SL_RAIL_UTIL_RSSI_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RSSI Offset Configuration + +// Software RSSI offset value +// Default: 0 +#define SL_RAIL_UTIL_RSSI_OFFSET 0 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_RSSI_CONFIG_H \ No newline at end of file diff --git a/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h index e804f16129..2c64163d90 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h +++ b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h @@ -1,14 +1,14 @@ // This file is autogenerated by Simplicity Configuration Tools. -// The contents of this file will be replaced in their entirety upon -// regeneration. -// +// The contents of this file will be replaced in their entirety upon regeneration. +// // Source template file: RTE_Components.h.jinja + #ifndef RTE_COMPONENTS_H #define RTE_COMPONENTS_H /* standard device header from emlib */ -#define CMSIS_device_header "em_device.h" +#define CMSIS_device_header "em_device.h" /* components are auto-generated here */ @@ -22,12 +22,13 @@ #define RTE_RTOS_FreeRTOS_TIMERS -#define RTE_RTOS_FreeRTOS_HEAP_4 +#define RTE_RTOS_FreeRTOS_HEAP_3 + #endif /* RTE_COMPONENTS_H */ /* This file is autogenerated by Simplicity Configuration Tools. */ -/* The contents of this file will be replaced in their entirety upon - * regeneration. */ +/* The contents of this file will be replaced in their entirety upon regeneration. */ /* */ /* Source template file: RTE_Components.h.jinja */ + diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h index 791e02c587..a2427b757a 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h @@ -3,26 +3,28 @@ // APIs present in project #define SL_CATALOG_BTN0_PRESENT -#define SL_CATALOG_BUTTON_PRESENT -#define SL_CATALOG_BUTTON_BTN0_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_BTN0_PRESENT #define SL_CATALOG_BTN1_PRESENT -#define SL_CATALOG_BUTTON_BTN1_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_BTN1_PRESENT #define SL_CATALOG_LED0_PRESENT -#define SL_CATALOG_LED_PRESENT -#define SL_CATALOG_LED_LED0_PRESENT +#define SL_CATALOG_SIMPLE_LED_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED0_PRESENT #define SL_CATALOG_LED1_PRESENT -#define SL_CATALOG_LED_LED1_PRESENT -#define SL_CATALOG_TIMER0_PRESENT -#define SL_CATALOG_ULP_TIMERS_INSTANCE_PRESENT -#define SL_CATALOG_TEMP_ULP_TIMER_TIMER0_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED1_PRESENT +#define SL_CATALOG_ULP_TIMER_PRESENT +#define SL_CATALOG_ULP_TIMER_TIMER0_PRESENT #define SL_CATALOG_CMSIS_OS_COMMON_PRESENT #define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT #define SL_CATALOG_EMLIB_CORE_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT #define SL_CATALOG_FREERTOS_KERNEL_PRESENT #define SL_CATALOG_KERNEL_PRESENT +#define SL_CATALOG_GLIB_PRESENT #define SL_CATALOG_IOSTREAM_PRESENT +#define SL_CATALOG_MEMORY_MANAGER_PRESENT #define SL_CATALOG_NVM3_PRESENT +#define SL_CATALOG_SEGGER_RTT_PRESENT #ifdef DISPLAY_ENABLED #define SL_CATALOG_SLEEPTIMER_PRESENT #define SL_CATALOG_DMD_MEMLCD_PRESENT diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c index 40959485d2..402e659ada 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c @@ -1,19 +1,21 @@ #include "sl_event_handler.h" -#include "cmsis_os2.h" +#include "system_si91x.h" +#include "rsi_nvic_priorities_config.h" +#include "sli_siwx917_soc.h" #include "rsi_board.h" -#include "rsi_chip.h" #include "rsi_debug.h" -#include "rsi_nvic_priorities_config.h" -#include "rsi_wisemcu_hardware_setup.h" -#include "sl_iostream_init_instances.h" -#include "sl_iostream_rtt.h" +#include "SEGGER_RTT.h" +#include "sl_sleeptimer.h" #include "sl_si91x_button_instances.h" #include "sl_si91x_led_instances.h" -#include "sl_sleeptimer.h" -#include "sli_siwx917_soc.h" +#include "sl_ulp_timer_instances.h" +#include "sl_iostream_rtt.h" +#include "cmsis_os2.h" +#include "sl_iostream_init_instances.h" -void sl_platform_init(void) { +void sl_platform_init(void) +{ SystemCoreClockUpdate(); sl_si91x_device_init_nvic(); sli_si91x_platform_init(); @@ -25,22 +27,35 @@ void sl_platform_init(void) { osKernelInitialize(); } -void sl_kernel_start(void) { osKernelStart(); } +void sl_kernel_start(void) +{ + osKernelStart(); +} -void sl_driver_init(void) { +void sl_driver_init(void) +{ button_init_instances(); led_init_instances(); } -void sl_service_init(void) { +void sl_service_init(void) +{ #ifdef DISPLAY_ENABLED sl_sleeptimer_init(); #endif sl_iostream_init_instances(); } -void sl_stack_init(void) {} +void sl_stack_init(void) +{ +} + +void sl_internal_app_init(void) +{ +} -void sl_internal_app_init(void) {} +void sl_iostream_init_instances(void) +{ + sl_iostream_rtt_init(); +} -void sl_iostream_init_instances(void) { sl_iostream_rtt_init(); } diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.c b/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.c index ce72b733aa..fe071eee61 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.c +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.c @@ -1,22 +1,22 @@ -#include "sl_iostream_handles.h" #include "sl_iostream.h" +#include "sl_iostream_handles.h" #include "string.h" const sl_iostream_instance_info_t *sl_iostream_instances_info[] = { &sl_iostream_instance_rtt_info, - + }; -const uint32_t sl_iostream_instances_count = - sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); +const uint32_t sl_iostream_instances_count = sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); -/***************************************************************************/ /** - * Get iostream instance handle for a given name - * - * @return Instance handle if it exist, NULL otherwise. - ******************************************************************************/ -sl_iostream_t *sl_iostream_get_handle(char *name) { +/***************************************************************************//** + * Get iostream instance handle for a given name + * + * @return Instance handle if it exist, NULL otherwise. + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_handle(char *name) +{ for (uint32_t i = 0; i < sl_iostream_instances_count; i++) { if (strcmp(sl_iostream_instances_info[i]->name, name) == 0) { return sl_iostream_instances_info[i]->handle; diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.h index c15c11c2bc..770dc48896 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.h +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_iostream_handles.h @@ -3,6 +3,7 @@ #include "sl_iostream.h" #include "sl_iostream_rtt.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.c b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.c index a81d88dd53..d8966e5438 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.c +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.c @@ -1,56 +1,59 @@ /***************************************************************************/ /** - * @file sl_si91x_button_instances.c.jinja - * @brief Button Driver Instances - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ + * @file sl_si91x_button_instances.c.jinja + * @brief Button Driver Instances + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_button_pin_config.h" #include "sl_si91x_button_instances.h" #include "sl_si91x_button_btn0_config.h" #include "sl_si91x_button_btn1_config.h" -#include "sl_si91x_button_pin_config.h" -sl_button_t const button_btn0 = {.port = SL_BUTTON_BTN0_PORT, - .pin = SL_BUTTON_BTN0_PIN, - .button_number = SL_BUTTON_BTN0_NUMBER, -#ifdef SL_BUTTON_BTN0_PAD - .pad = SL_BUTTON_BTN0_PAD, -#endif - .interrupt_config = - SL_BUTTON_CONFIG_BTN0_INTR}; -sl_button_t const button_btn1 = {.port = SL_BUTTON_BTN1_PORT, - .pin = SL_BUTTON_BTN1_PIN, - .button_number = SL_BUTTON_BTN1_NUMBER, -#ifdef SL_BUTTON_BTN1_PAD - .pad = SL_BUTTON_BTN1_PAD, -#endif - .interrupt_config = - SL_BUTTON_CONFIG_BTN1_INTR}; +sl_button_t const button_btn0 = { + .port = SL_BUTTON_BTN0_PORT, + .pin = SL_BUTTON_BTN0_PIN, + .button_number = SL_BUTTON_BTN0_NUMBER, + #ifdef SL_BUTTON_BTN0_PAD + .pad = SL_BUTTON_BTN0_PAD, + #endif + .interrupt_config = SL_BUTTON_CONFIG_BTN0_INTR +}; +sl_button_t const button_btn1 = { + .port = SL_BUTTON_BTN1_PORT, + .pin = SL_BUTTON_BTN1_PIN, + .button_number = SL_BUTTON_BTN1_NUMBER, + #ifdef SL_BUTTON_BTN1_PAD + .pad = SL_BUTTON_BTN1_PAD, + #endif + .interrupt_config = SL_BUTTON_CONFIG_BTN1_INTR +}; -void button_init_instances(void) { +void button_init_instances(void) +{ sl_si91x_button_init(&button_btn0); sl_si91x_button_init(&button_btn1); } diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.h index 2bf0a9f56f..f612ed01bc 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.h +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_button_instances.h @@ -1,32 +1,32 @@ /***************************************************************************/ /** - * @file sl_si91x_button_instances.h.jinja - * @brief Button Driver Instances - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ + * @file sl_si91x_button_instances.h.jinja + * @brief Button Driver Instances + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ #ifndef SL_SI91X_BUTTON_INSTANCES_H #define SL_SI91X_BUTTON_INSTANCES_H @@ -36,6 +36,7 @@ extern const sl_button_t button_btn0; extern const sl_button_t button_btn1; + void button_init_instances(void); void sl_simple_button_init_instances(void); diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.c b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.c index 6b7f2c55ea..04ce6657e2 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.c +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.c @@ -1,5 +1,4 @@ -/***************************************************************************/ -/** +/***************************************************************************/ /** * @file sl_si91x_led_instances.c.jinja * @brief Button Driver Instances ******************************************************************************* @@ -29,21 +28,22 @@ * ******************************************************************************/ -#include "sl_si91x_led_instances.h" #include "sl_si91x_led.h" #include "sl_si91x_led_config.h" +#include "sl_si91x_led_instances.h" sl_led_t const led_led0 = { - .port = SL_LED_LED0_PORT, - .pin = SL_LED_LED0_PIN, - .led_number = SL_LED_LED0_NUMBER, + .port = SL_LED_LED0_PORT, + .pin = SL_LED_LED0_PIN, + .led_number = SL_LED_LED0_NUMBER, }; sl_led_t const led_led1 = { - .port = SL_LED_LED1_PORT, - .pin = SL_LED_LED1_PIN, - .led_number = SL_LED_LED1_NUMBER, + .port = SL_LED_LED1_PORT, + .pin = SL_LED_LED1_PIN, + .led_number = SL_LED_LED1_NUMBER, }; -void led_init_instances(void) { +void led_init_instances(void) +{ sl_si91x_led_init(&led_led0); sl_si91x_led_init(&led_led1); } diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.h index 2d697eaf19..0bbfc7ba4e 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.h +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_led_instances.h @@ -1,5 +1,4 @@ -/***************************************************************************/ -/** +/***************************************************************************/ /** * @file sl_si91x_led_instances.h.jinja * @brief Button Driver Instances ******************************************************************************* @@ -37,6 +36,7 @@ extern const sl_led_t led_led0; extern const sl_led_t led_led1; + void led_init_instances(void); #endif // SL_SI91x_LED_INSTANCES_H diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_ulp_timer_init.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_ulp_timer_init.h deleted file mode 100644 index 6831f4d5c3..0000000000 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_si91x_ulp_timer_init.h +++ /dev/null @@ -1,46 +0,0 @@ -/***************************************************************************/ -/** - * @file sl_si91x_ulp_timer_init.h - * @brief ULP Timer Instances - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SI91X_ULP_TIMER_INIT_H_ -#define SL_SI91X_ULP_TIMER_INIT_H_ - -#include "sl_si91x_ulp_timer.h" -// Include instance config - -#include "sl_si91x_ulp_timer_timer0_config.h" - -#if defined(SL_ULP_TIMER_TIMER0) // To verify UC inputs existance -ulp_timer_config_t sl_timer_handle_timer0 = { - .timer_num = SL_ULP_TIMER_TIMER0, - .timer_mode = SL_ULP_TIMER_MODE, - .timer_type = SL_ULP_TIMER_TYP, - .timer_match_value = SL_TIMER_MATCH_VALUE_DEFAULT, - .timer_direction = SL_ULP_TIMER_DIRECTION, -}; -#endif // SL_ULP_TIMER_INSTANCE - -#if defined(SL_ULP_TIMER_CLK_TYPE) // To verify UC inputs existence -ulp_timer_clk_src_config_t sl_timer_clk_handle = { - .ulp_timer_clk_type = SL_ULP_TIMER_CLK_TYPE, - .ulp_timer_sync_to_ulpss_pclk = SL_ULP_TIMER_SYNC_TO_ULPSS_PCLK, - .ulp_timer_clk_input_src = SL_ULP_TIMER_CLK_INPUT_SOURCE, - .ulp_timer_skip_switch_time = SL_ULP_TIMER_SKIP_SWITCH_TIME, -}; -#endif // SL_ULP_TIMER_CLK_TYPE - -#endif // SL_SI91X_ULP_TIMER_INIT_H_ diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_ulp_timer_init.c b/matter/si91x/siwx917/BRD4338A/autogen/sl_ulp_timer_init.c new file mode 100644 index 0000000000..91a8a01f21 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_ulp_timer_init.c @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file sl_ulp_timer_init.c.jinja + * @brief ULP timer Instance Initialization + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_ulp_timer.h" + +#include "sl_si91x_ulp_timer_init_timer0_config.h" + + +#include "sl_ulp_timer_instances.h" + + + +ulp_timer_config_t sl_timer_handle_timer0 = { + .timer_num = SL_ULP_TIMER_TIMER0, + .timer_mode = SL_ULP_TIMER_TIMER0_MODE, + .timer_type = SL_ULP_TIMER_TIMER0_TYPE, + .timer_match_value = SL_TIMER_MATCH_VALUE_DEFAULT, + .timer_direction = SL_ULP_TIMER_TIMER0_DIRECTION, +}; + + + diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_ulp_timer_instances.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_ulp_timer_instances.h new file mode 100644 index 0000000000..1eb1e971e0 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_ulp_timer_instances.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file sl_ulp_timer_instances.h.jinja + * @brief ULP Timer Instance + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_ULP_TIMER_INSTANCES_H +#define SL_ULP_TIMER_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_ulp_timer.h" +#define SL_ULP_TIMER_TIMER0 0 +#define SL_ULP_TIMER_TIMER1 1 +#define SL_ULP_TIMER_TIMER2 2 +#define SL_ULP_TIMER_TIMER3 3 + + +extern ulp_timer_config_t sl_timer_handle_timer0 ; + + + +#ifdef __cplusplus +} +#endif + +#endif // SL_ULP_TIMER_INSTANCES_H diff --git a/matter/si91x/siwx917/BRD4338A/config/RTE_Device_917.h b/matter/si91x/siwx917/BRD4338A/config/RTE_Device_917.h index 49c9f21bb0..add7bf77a8 100644 --- a/matter/si91x/siwx917/BRD4338A/config/RTE_Device_917.h +++ b/matter/si91x/siwx917/BRD4338A/config/RTE_Device_917.h @@ -27,54 +27,53 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H -#include "pin_config.h" #include "rsi_ccp_user_config.h" +#include "pin_config.h" -#define GPIO_PORT_0 0 // GPIO port 0 -#define ULP_GPIO_MODE_6 6 // ULP GPIO mode 6 +#define GPIO_PORT_0 0 // GPIO port 0 +#define ULP_GPIO_MODE_6 6 // ULP GPIO mode 6 #define HOST_PAD_GPIO_MIN 25 // GPIO host pad minimum pin number #define HOST_PAD_GPIO_MAX 30 // GPIO host pad maximum pin number -#define GPIO_MAX_PIN 64 // GPIO maximum pin number +#define GPIO_MAX_PIN 64 // GPIO maximum pin number #define BUTTON_0_GPIO_PIN 2 -#define RTE_BUTTON0_PORT 0 +#define RTE_BUTTON0_PORT 0 #define RTE_BUTTON0_NUMBER 0 -#define RTE_BUTTON0_PIN (2U) +#define RTE_BUTTON0_PIN (2U) -#define RTE_BUTTON1_PORT 0 +#define RTE_BUTTON1_PORT 0 #define RTE_BUTTON1_NUMBER 1 -#define RTE_BUTTON1_PIN (11U) -#define RTE_BUTTON1_PAD 6 +#define RTE_BUTTON1_PIN (11U) +#define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 0 #define RTE_LED0_NUMBER 0 -#define RTE_LED0_PIN (2U) +#define RTE_LED0_PIN (2U) -#define RTE_LED1_PORT 0 -#define RTE_LED1_NUMBER 1 -#define RTE_LED1_PIN (10U) +#define RTE_LED1_PORT 0 +#define RTE_LED1_NUMBER 1 +#define RTE_LED1_PIN (10U) #define BOARD_ACTIVITY_LED (2U) // LED0 -#define RTE_LED1_PAD 5 +#define RTE_LED1_PAD 5 // USART0 [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS -// Driver:USART +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART #define RTE_ENABLE_FIFO 1 #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_ULPREFCLK +#define RTE_USART0_CLK_SRC USART_INTFPLLCLK #define RTE_USART0_CLK_DIV_FACT 1 -#define RTE_USART0_FRAC_DIV_EN 0 +#define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER -#define RTE_USART_MODE 0 //! Usart mode macros +#define RTE_USART_MODE 0 //!Usart mode macros #define RTE_CONTINUOUS_CLOCK_MODE 0 -#define RTE_USART0_LOOPBACK 0 +#define RTE_USART0_LOOPBACK 0 #define RTE_USART0_DTR_EANBLE 0 -#define RTE_USART0_DMA_MODE1_EN 0 //! dma mode +#define RTE_USART0_DMA_MODE1_EN 0 //!dma mode #define RTE_USART0_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY #define RTE_USART0_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY @@ -93,39 +92,46 @@ #if (RTE_USART0_CLK_PORT_ID == 0) #define RTE_USART0_CLK_PORT 0 -#define RTE_USART0_CLK_PIN 8 -#define RTE_USART0_CLK_MUX 2 -#define RTE_USART0_CLK_PAD 3 +#define RTE_USART0_CLK_PIN 8 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 #elif (RTE_USART0_CLK_PORT_ID == 1) #define RTE_USART0_CLK_PORT 0 -#define RTE_USART0_CLK_PIN 25 -#define RTE_USART0_CLK_MUX 2 -#define RTE_USART0_CLK_PAD 0 // NO PAD +#define RTE_USART0_CLK_PIN 25 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD #elif (RTE_USART0_CLK_PORT_ID == 2) #define RTE_USART0_CLK_PORT 0 -#define RTE_USART0_CLK_PIN 52 -#define RTE_USART0_CLK_MUX 2 -#define RTE_USART0_CLK_PAD 16 +#define RTE_USART0_CLK_PIN 52 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 #else #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_CLK_PORT USART0_CLK_PORT -#define RTE_USART0_CLK_PIN USART0_CLK_PIN #if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 3 #endif #if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 -#define RTE_USART0_CLK_PAD 0 // NO PAD +#define RTE_USART0_CLK_PAD 0 //NO PAD #endif #if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 16 #endif -// Pintool data +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data #endif // USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 @@ -139,51 +145,56 @@ #if (RTE_USART0_TX_PORT_ID == 0) #define RTE_USART0_TX_PORT 0 -#define RTE_USART0_TX_PIN 15 -#define RTE_USART0_TX_MUX 2 -#define RTE_USART0_TX_PAD 8 +#define RTE_USART0_TX_PIN 15 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 #elif (RTE_USART0_TX_PORT_ID == 1) #define RTE_USART0_TX_PORT 0 -#define RTE_USART0_TX_PIN 30 -#define RTE_USART0_TX_MUX 2 -#define RTE_USART0_TX_PAD 0 // NO PAD +#define RTE_USART0_TX_PIN 30 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD #elif (RTE_USART0_TX_PORT_ID == 2) #define RTE_USART0_TX_PORT 0 -#define RTE_USART0_TX_PIN 54 -#define RTE_USART0_TX_MUX 2 -#define RTE_USART0_TX_PAD 18 +#define RTE_USART0_TX_PIN 54 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 #elif (RTE_USART0_TX_PORT_ID == 3) #define RTE_USART0_TX_PORT 0 -#define RTE_USART0_TX_PIN 71 -#define RTE_USART0_TX_MUX 4 -#define RTE_USART0_TX_PAD 29 +#define RTE_USART0_TX_PIN 71 +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 #else #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_TX_PORT USART0_TX_PORT -#if (USART0_TX_LOC == 0) +#if (USART0_TX_LOC == 4) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 8 #endif -#if (USART0_TX_LOC == 1) +#if (USART0_TX_LOC == 5) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 -#define RTE_USART0_TX_PAD 0 // NO PAD +#define RTE_USART0_TX_PAD 0 //NO PAD #endif -#if (USART0_TX_LOC == 2) +#if (USART0_TX_LOC == 6) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 18 #endif -#if (USART0_TX_LOC == 3) +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) #define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) #define RTE_USART0_TX_MUX 4 #define RTE_USART0_TX_PAD 29 #endif -// Pintool data +//Pintool data #endif // USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 @@ -197,61 +208,61 @@ #if (RTE_USART0_RX_PORT_ID == 0) #define RTE_USART0_RX_PORT 0 -#define RTE_USART0_RX_PIN 10 -#define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 5 +#define RTE_USART0_RX_PIN 10 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 #elif (RTE_USART0_RX_PORT_ID == 1) #define RTE_USART0_RX_PORT 0 -#define RTE_USART0_RX_PIN 29 -#define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 0 // no pad +#define RTE_USART0_RX_PIN 29 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad #elif (RTE_USART0_RX_PORT_ID == 2) #define RTE_USART0_RX_PORT 0 -#define RTE_USART0_RX_PIN 55 -#define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 19 +#define RTE_USART0_RX_PIN 55 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 #elif (RTE_USART0_RX_PORT_ID == 3) #define RTE_USART0_RX_PORT 0 -#define RTE_USART0_RX_PIN 65 -#define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PIN 65 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 24 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 -#define RTE_USART0_RX_PIN 70 -#define RTE_USART0_RX_MUX 4 -#define RTE_USART0_RX_PAD 28 +#define RTE_USART0_RX_PIN 70 +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 #else #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_RX_PORT USART0_RX_PORT -#if (USART0_RX_LOC == 0) +#if (USART0_RX_LOC == 9) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 5 #endif -#if (USART0_RX_LOC == 1) +#if (USART0_RX_LOC == 10) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 0 // no pad +#define RTE_USART0_RX_PAD 0 //no pad #endif -#if (USART0_RX_LOC == 2) +#if (USART0_RX_LOC == 11) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 19 #endif -#if (USART0_RX_LOC == 3) +#if (USART0_RX_LOC == 12) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 24 #endif -#if (USART0_RX_LOC == 4) +#if (USART0_RX_LOC == 13) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 4 #define RTE_USART0_RX_PAD 28 #endif -// Pintool data +//Pintool data #endif // USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 @@ -261,51 +272,51 @@ #if (RTE_USART0_CTS_PORT_ID == 0) #define RTE_USART0_CTS_PORT 0 -#define RTE_USART0_CTS_PIN 6 -#define RTE_USART0_CTS_MUX 2 -#define RTE_USART0_CTS_PAD 1 +#define RTE_USART0_CTS_PIN 6 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 #elif (RTE_USART0_CTS_PORT_ID == 1) #define RTE_USART0_CTS_PORT 0 -#define RTE_USART0_CTS_PIN 26 -#define RTE_USART0_CTS_MUX 2 -#define RTE_USART0_CTS_PAD 0 // NO PAD +#define RTE_USART0_CTS_PIN 26 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD #elif (RTE_USART0_CTS_PORT_ID == 2) #define RTE_USART0_CTS_PORT 0 -#define RTE_USART0_CTS_PIN 56 -#define RTE_USART0_CTS_MUX 2 -#define RTE_USART0_CTS_PAD 20 +#define RTE_USART0_CTS_PIN 56 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 #elif (RTE_USART0_CTS_PORT_ID == 3) #define RTE_USART0_CTS_PORT 0 -#define RTE_USART0_CTS_PIN 70 -#define RTE_USART0_CTS_MUX 2 -#define RTE_USART0_CTS_PAD 28 +#define RTE_USART0_CTS_PIN 70 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 #else #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_CTS_PORT USART0_CTS_PORT -#if (USART0_CTS_LOC == 0) +#if (USART0_CTS_LOC == 14) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 1 #endif -#if (USART0_CTS_LOC == 1) +#if (USART0_CTS_LOC == 15) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 -#define RTE_USART0_CTS_PAD 0 // NO PAD +#define RTE_USART0_CTS_PAD 0 //NO PAD #endif -#if (USART0_CTS_LOC == 2) +#if (USART0_CTS_LOC == 16) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 20 #endif -#if (USART0_CTS_LOC == 3) +#if (USART0_CTS_LOC == 17) #define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 28 #endif -// Pintool data +//Pintool data #endif // USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 @@ -315,39 +326,46 @@ #if (RTE_USART0_RTS_PORT_ID == 0) #define RTE_USART0_RTS_PORT 0 -#define RTE_USART0_RTS_PIN 9 -#define RTE_USART0_RTS_MUX 2 -#define RTE_USART0_RTS_PAD 4 +#define RTE_USART0_RTS_PIN 9 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 #elif (RTE_USART0_RTS_PORT_ID == 1) #define RTE_USART0_RTS_PORT 0 -#define RTE_USART0_RTS_PIN 28 -#define RTE_USART0_RTS_MUX 2 -#define RTE_USART0_RTS_PAD 0 // NO PAD +#define RTE_USART0_RTS_PIN 28 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD #elif (RTE_USART0_RTS_PORT_ID == 2) #define RTE_USART0_RTS_PORT 0 -#define RTE_USART0_RTS_PIN 53 -#define RTE_USART0_RTS_MUX 2 -#define RTE_USART0_RTS_PAD 17 +#define RTE_USART0_RTS_PIN 53 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 #else #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) #define RTE_USART0_RTS_PIN USART0_RTS_PIN -#if (USART0_RTS_LOC == 0) #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 4 #endif -#if (USART0_RTS_LOC == 1) +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 -#define RTE_USART0_RTS_PAD 0 // NO PAD +#define RTE_USART0_RTS_PAD 0 //NO PAD #endif -#if (USART0_RTS_LOC == 2) +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 17 #endif -// Pintool data +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data #endif // USART0_IR_TX <0=>P0_48 <1=>P0_72 @@ -360,36 +378,46 @@ #if (RTE_IR_TX_PORT_ID == 0) #define RTE_USART0_IR_TX_PORT 0 -#define RTE_USART0_IR_TX_PIN 48 -#define RTE_USART0_IR_TX_MUX 2 -#define RTE_USART0_IR_TX_PAD 12 +#define RTE_USART0_IR_TX_PIN 48 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 #elif (RTE_IR_TX_PORT_ID == 1) #define RTE_USART0_IR_TX_PORT 0 -#define RTE_USART0_IR_TX_PIN 72 -#define RTE_USART0_IR_TX_MUX 2 -#define RTE_USART0_IR_TX_PAD 30 +#define RTE_USART0_IR_TX_PIN 72 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 #elif (RTE_IR_TX_PORT_ID == 2) #define RTE_USART0_IR_TX_PORT 0 -#define RTE_USART0_IR_TX_PIN 26 -#define RTE_USART0_IR_TX_MUX 13 -#define RTE_USART0_IR_TX_PAD 0 // No pad +#define RTE_USART0_IR_TX_PIN 26 +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad #else #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT -#if (USART0_IRTX_LOC == 0) +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) #define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN #define RTE_USART0_IR_TX_MUX 2 #define RTE_USART0_IR_TX_PAD 12 #endif -#if (USART0_IRTX_LOC == 1) +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) #define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) #define RTE_USART0_IR_TX_MUX 2 #define RTE_USART0_IR_TX_PAD 30 #endif -// Pintool data +//Pintool data #endif // USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 @@ -402,36 +430,46 @@ #if (RTE_IR_RX_PORT_ID == 0) #define RTE_USART0_IR_RX_PORT 0 -#define RTE_USART0_IR_RX_PIN 47 -#define RTE_USART0_IR_RX_MUX 2 -#define RTE_USART0_IR_RX_PAD 11 +#define RTE_USART0_IR_RX_PIN 47 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 #elif (RTE_IR_RX_PORT_ID == 1) #define RTE_USART0_IR_RX_PORT 0 -#define RTE_USART0_IR_RX_PIN 71 -#define RTE_USART0_IR_RX_MUX 2 -#define RTE_USART0_IR_RX_PAD 29 +#define RTE_USART0_IR_RX_PIN 71 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 #elif (RTE_IR_RX_PORT_ID == 2) #define RTE_USART0_IR_RX_PORT 0 -#define RTE_USART0_IR_RX_PIN 25 -#define RTE_USART0_IR_RX_MUX 13 -#define RTE_USART0_IR_RX_PAD 0 // no pad +#define RTE_USART0_IR_RX_PIN 25 +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad #else #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT -#if (USART0_IRRX_LOC == 0) +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) #define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN #define RTE_USART0_IR_RX_MUX 2 #define RTE_USART0_IR_RX_PAD 11 #endif -#if (USART0_IRRX_LOC == 1) +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) #define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) #define RTE_USART0_IR_RX_MUX 2 #define RTE_USART0_IR_RX_PAD 29 #endif -// Pintool data +//Pintool data #endif // USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 @@ -441,30 +479,36 @@ #if (RTE_RI_PORT_ID == 0) #define RTE_USART0_RI_PORT 0 -#define RTE_USART0_RI_PIN 27 -#define RTE_USART0_RI_MUX 2 -#define RTE_USART0_RI_PAD 0 // no pad +#define RTE_USART0_RI_PIN 27 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad #elif (RTE_RI_PORT_ID == 1) #define RTE_USART0_RI_PORT 0 -#define RTE_USART0_RI_PIN 46 -#define RTE_USART0_RI_MUX 2 -#define RTE_USART0_RI_PAD 10 +#define RTE_USART0_RI_PIN 46 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) #define RTE_USART0_RI_PIN USART0_RI_PIN -#if (USART0_RI_LOC == 0) #define RTE_USART0_RI_MUX 2 -#define RTE_USART0_RI_PAD 0 // no pad +#define RTE_USART0_RI_PAD 0 //no pad #endif -#if (USART0_RI_LOC == 1) +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN #define RTE_USART0_RI_MUX 2 #define RTE_USART0_RI_PAD 10 #endif -// Pintool data +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data #endif // USART0_DSR <0=>P0_11 <1=>P0_57 @@ -474,52 +518,57 @@ #if (RTE_DSR_PORT_ID == 0) #define RTE_USART0_DSR_PORT 0 -#define RTE_USART0_DSR_PIN 11 -#define RTE_USART0_DSR_MUX 2 -#define RTE_USART0_DSR_PAD 6 +#define RTE_USART0_DSR_PIN 11 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 #elif (RTE_DSR_PORT_ID == 1) #define RTE_USART0_DSR_PORT 0 -#define RTE_USART0_DSR_PIN 57 -#define RTE_USART0_DSR_MUX 2 -#define RTE_USART0_DSR_PAD 21 +#define RTE_USART0_DSR_PIN 57 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_USART0_DSR_PORT USART0_DSR_PORT -#define RTE_USART0_DSR_PIN USART0_DSR_PIN -#if (USART0_DSR_LOC == 0) +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) #define RTE_USART0_DSR_MUX 2 #define RTE_USART0_DSR_PAD 6 #endif -#if (USART0_DSR_LOC == 1) +#if (USART0_DSR_LOC == 34) #define RTE_USART0_DSR_MUX 2 #define RTE_USART0_DSR_PAD 21 #endif -// Pintool data +//Pintool data #endif // USART0_DCD <0=>P0_12 <1=>P0_29 // DCD for USART0 #ifndef USART0_DCD_LOC #define RTE_USART0_DCD_PORT 0 -#define RTE_USART0_DCD_PIN 12 +#define RTE_USART0_DCD_PIN 12 #else #define RTE_USART0_DCD_PORT USART0_DCD_PORT -#define RTE_USART0_DCD_PIN USART0_DCD_PIN -#endif +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) #define RTE_USART0_DCD_MUX 2 #define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 #ifndef USART0_DTR_LOC #define RTE_USART0_DTR_PORT 0 -#define RTE_USART0_DTR_PIN 7 +#define RTE_USART0_DTR_PIN 7 #else #define RTE_USART0_DTR_PORT USART0_DTR_PORT -#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#define RTE_USART0_DTR_PIN USART0_DTR_PIN #endif #define RTE_USART0_DTR_MUX 2 #define RTE_USART0_DTR_PAD 2 @@ -529,11 +578,11 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_ULPREFCLK +#define RTE_UART1_CLK_SRC USART_INTFPLLCLK #define RTE_UART1_CLK_DIV_FACT 1 -#define RTE_UART1_FRAC_DIV_EN 0 +#define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER -#define RTE_UART1_LOOPBACK 0 +#define RTE_UART1_LOOPBACK 0 #define RTE_UART1_DMA_MODE1_EN 0 #define RTE_UART1_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY @@ -547,11 +596,11 @@ #define RTE_UART1_CHNL_UDMA_RX_CH 26 /*UART1 PINS*/ -// UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 -// <6=>P0_34 TX of UART1 +// UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 +// TX of UART1 #ifndef UART1_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER -#define RTE_UART1_TX_PORT_ID 3 +#define RTE_UART1_TX_PORT_ID 0 #else #define RTE_UART1_TX_PORT_ID 0 @@ -562,34 +611,34 @@ #if (RTE_UART1_TX_PORT_ID == 0) #define RTE_UART1_TX_PORT 0 -#define RTE_UART1_TX_PIN 7 -#define RTE_UART1_TX_MUX 6 -#define RTE_UART1_TX_PAD 2 +#define RTE_UART1_TX_PIN 7 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 #elif (RTE_UART1_TX_PORT_ID == 1) #define RTE_UART1_TX_PORT 0 -#define RTE_UART1_TX_PIN 30 -#define RTE_UART1_TX_MUX 6 -#define RTE_UART1_TX_PAD 0 // no pad +#define RTE_UART1_TX_PIN 30 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad #elif (RTE_UART1_TX_PORT_ID == 2) #define RTE_UART1_TX_PORT 0 -#define RTE_UART1_TX_PIN 67 -#define RTE_UART1_TX_MUX 9 -#define RTE_UART1_TX_PAD 25 +#define RTE_UART1_TX_PIN 67 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 25 #elif (RTE_UART1_TX_PORT_ID == 3) #define RTE_UART1_TX_PORT 0 -#define RTE_UART1_TX_PIN 73 -#define RTE_UART1_TX_MUX 6 -#define RTE_UART1_TX_PAD 31 +#define RTE_UART1_TX_PIN 73 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 #elif (RTE_UART1_TX_PORT_ID == 4) #define RTE_UART1_TX_PORT 0 -#define RTE_UART1_TX_PIN 75 -#define RTE_UART1_TX_MUX 9 -#define RTE_UART1_TX_PAD 33 +#define RTE_UART1_TX_PIN 75 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 #else #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_UART1_TX_PORT UART1_TX_PORT #if (UART1_TX_LOC == 0) #define RTE_UART1_TX_PIN UART1_TX_PIN @@ -599,12 +648,12 @@ #if (UART1_TX_LOC == 1) #define RTE_UART1_TX_PIN UART1_TX_PIN #define RTE_UART1_TX_MUX 6 -#define RTE_UART1_TX_PAD 0 // no pad +#define RTE_UART1_TX_PAD 0 //no pad #endif #if (UART1_TX_LOC == 2) #define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) -#define RTE_UART1_TX_MUX 9 -#define RTE_UART1_TX_PAD 25 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 #endif #if (UART1_TX_LOC == 3) #define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) @@ -616,139 +665,144 @@ #define RTE_UART1_TX_MUX 9 #define RTE_UART1_TX_PAD 33 #endif -// Pintool data +//Pintool data #endif -// UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 -// <6=>P0_33 RX of UART1 +// UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 +// RX of UART1 #ifndef UART1_RX_LOC #define RTE_UART1_RX_PORT_ID 0 #if (RTE_UART1_RX_PORT_ID == 0) #define RTE_UART1_RX_PORT 0 -#define RTE_UART1_RX_PIN 6 -#define RTE_UART1_RX_MUX 6 -#define RTE_UART1_RX_PAD 1 +#define RTE_UART1_RX_PIN 6 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 #elif (RTE_UART1_RX_PORT_ID == 1) #define RTE_UART1_RX_PORT 0 -#define RTE_UART1_RX_PIN 29 -#define RTE_UART1_RX_MUX 6 -#define RTE_UART1_RX_PAD 0 // no pad +#define RTE_UART1_RX_PIN 29 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad #elif (RTE_UART1_RX_PORT_ID == 2) #define RTE_UART1_RX_PORT 0 -#define RTE_UART1_RX_PIN 66 -#define RTE_UART1_RX_MUX 9 -#define RTE_UART1_RX_PAD 24 +#define RTE_UART1_RX_PIN 66 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 24 #elif (RTE_UART1_RX_PORT_ID == 3) #define RTE_UART1_RX_PORT 0 -#define RTE_UART1_RX_PIN 72 -#define RTE_UART1_RX_MUX 6 -#define RTE_UART1_RX_PAD 30 +#define RTE_UART1_RX_PIN 72 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 #elif (RTE_UART1_RX_PORT_ID == 4) #define RTE_UART1_RX_PORT 0 -#define RTE_UART1_RX_PIN 74 -#define RTE_UART1_RX_MUX 9 -#define RTE_UART1_RX_PAD 32 +#define RTE_UART1_RX_PIN 74 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 #else #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_UART1_RX_PORT UART1_RX_PORT -#if (UART1_RX_LOC == 0) +#if (UART1_RX_LOC == 5) #define RTE_UART1_RX_PIN UART1_RX_PIN #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 1 #endif -#if (UART1_RX_LOC == 1) +#if (UART1_RX_LOC == 6) #define RTE_UART1_RX_PIN UART1_RX_PIN #define RTE_UART1_RX_MUX 6 -#define RTE_UART1_RX_PAD 0 // no pad +#define RTE_UART1_RX_PAD 0 //no pad #endif -#if (UART1_RX_LOC == 2) +#if (UART1_RX_LOC == 7) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) -#define RTE_UART1_RX_MUX 9 -#define RTE_UART1_RX_PAD 24 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 #endif -#if (UART1_RX_LOC == 3) +#if (UART1_RX_LOC == 8) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 30 #endif -#if (UART1_RX_LOC == 4) +#if (UART1_RX_LOC == 9) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) #define RTE_UART1_RX_MUX 9 #define RTE_UART1_RX_PAD 32 #endif -// Pintool data +//Pintool data #endif -// UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 -// <6=>P0_32 CTS of UART1 +// UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 +// CTS of UART1 #ifndef UART1_CTS_LOC #define RTE_UART1_CTS_PORT_ID 0 #if (RTE_UART1_CTS_PORT_ID == 0) #define RTE_UART1_CTS_PORT 0 -#define RTE_UART1_CTS_PIN 11 -#define RTE_UART1_CTS_MUX 6 -#define RTE_UART1_CTS_PAD 6 +#define RTE_UART1_CTS_PIN 11 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 #elif (RTE_UART1_CTS_PORT_ID == 1) #define RTE_UART1_CTS_PORT 0 -#define RTE_UART1_CTS_PIN 28 -#define RTE_UART1_CTS_MUX 6 -#define RTE_UART1_CTS_PAD 0 // no pad +#define RTE_UART1_CTS_PIN 28 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad #elif (RTE_UART1_CTS_PORT_ID == 2) #define RTE_UART1_CTS_PORT 0 -#define RTE_UART1_CTS_PIN 51 -#define RTE_UART1_CTS_MUX 9 -#define RTE_UART1_CTS_PAD 15 +#define RTE_UART1_CTS_PIN 51 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 #elif (RTE_UART1_CTS_PORT_ID == 3) #define RTE_UART1_CTS_PORT 0 -#define RTE_UART1_CTS_PIN 65 -#define RTE_UART1_CTS_MUX 9 -#define RTE_UART1_CTS_PAD 23 +#define RTE_UART1_CTS_PIN 65 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 #elif (RTE_UART1_CTS_PORT_ID == 4) #define RTE_UART1_CTS_PORT 0 -#define RTE_UART1_CTS_PIN 71 -#define RTE_UART1_CTS_MUX 6 -#define RTE_UART1_CTS_PAD 29 +#define RTE_UART1_CTS_PIN 71 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 #else #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_UART1_CTS_PORT UART1_CTS_PORT -#if (UART1_CTS_LOC == 0) +#if (UART1_CTS_LOC == 10) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 6 #endif -#if (UART1_CTS_LOC == 1) +#if (UART1_CTS_LOC == 11) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 6 -#define RTE_UART1_CTS_PAD 0 // no pad +#define RTE_UART1_CTS_PAD 0 //no pad #endif -#if (UART1_CTS_LOC == 2) +#if (UART1_CTS_LOC == 12) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 9 #define RTE_UART1_CTS_PAD 15 #endif -#if (UART1_CTS_LOC == 3) +#if (UART1_CTS_LOC == 13) #define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_CTS_MUX 9 #define RTE_UART1_CTS_PAD 23 #endif -#if (UART1_CTS_LOC == 4) +#if (UART1_CTS_LOC == 14) #define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 29 #endif -// Pintool data +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data #endif -// UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 -// <5=>P0_72 <6=>P0_31 RTS of UART1 +// UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 +// RTS of UART1 #ifndef UART1_RTS_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_RTS_PORT_ID 0 @@ -758,75 +812,79 @@ #if (RTE_UART1_RTS_PORT_ID == 0) #define RTE_UART1_RTS_PORT 0 -#define RTE_UART1_RTS_PIN 10 -#define RTE_UART1_RTS_MUX 6 -#define RTE_UART1_RTS_PAD 5 +#define RTE_UART1_RTS_PIN 10 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 #elif (RTE_UART1_RTS_PORT_ID == 1) #define RTE_UART1_RTS_PORT 0 -#define RTE_UART1_RTS_PIN 27 -#define RTE_UART1_RTS_MUX 6 -#define RTE_UART1_RTS_PAD 0 // no pad +#define RTE_UART1_RTS_PIN 27 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad #elif (RTE_UART1_RTS_PORT_ID == 2) #define RTE_UART1_RTS_PORT 0 -#define RTE_UART1_RTS_PIN 50 -#define RTE_UART1_RTS_MUX 9 -#define RTE_UART1_RTS_PAD 14 +#define RTE_UART1_RTS_PIN 50 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 #elif (RTE_UART1_RTS_PORT_ID == 3) #define RTE_UART1_RTS_PORT 0 -#define RTE_UART1_RTS_PIN 70 -#define RTE_UART1_RTS_MUX 6 -#define RTE_UART1_RTS_PAD 28 +#define RTE_UART1_RTS_PIN 70 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 #elif (RTE_UART1_RTS_PORT_ID == 4) #define RTE_UART1_RTS_PORT 0 -#define RTE_UART1_RTS_PIN 72 -#define RTE_UART1_RTS_MUX 9 -#define RTE_UART1_RTS_PAD 30 +#define RTE_UART1_RTS_PIN 72 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 #else #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_UART1_RTS_PORT UART1_RTS_PORT -#if (UART1_RTS_LOC == 0) +#if (UART1_RTS_LOC == 16) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 5 #endif -#if (UART1_RTS_LOC == 1) +#if (UART1_RTS_LOC == 17) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 6 -#define RTE_UART1_RTS_PAD 0 // no pad +#define RTE_UART1_RTS_PAD 0 //no pad #endif -#if (UART1_RTS_LOC == 2) +#if (UART1_RTS_LOC == 18) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 9 #define RTE_UART1_RTS_PAD 14 #endif -#if (UART1_RTS_LOC == 3) +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) #define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 28 #endif -#if (UART1_RTS_LOC == 4) +#if (UART1_RTS_LOC == 21) #define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_RTS_MUX 9 #define RTE_UART1_RTS_PAD 30 #endif -// Pintool data +//Pintool data #endif // // ULP_UART [Driver_ULP_UART] -// Configuration settings for Driver_ULP_UART in component ::CMSIS -// Driver:USART +// Configuration settings for Driver_ULP_UART in component ::CMSIS Driver:USART #define RTE_ULP_UART 1 -#define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK +#define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK #define RTE_ULP_UART_CLK_DIV_FACT 0 -#define RTE_ULP_UART_FRAC_SEL 0 +#define RTE_ULP_UART_FRAC_SEL USART_FRACTIONAL_DIVIDER -#define RTE_ULP_UART_LOOPBACK 0 +#define RTE_ULP_UART_LOOPBACK 0 #define RTE_ULP_UART_DMA_MODE1_EN 0 #define RTE_ULP_UART_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY @@ -846,21 +904,21 @@ #define RTE_ULP_UART_TX_PORT_ID 1 #if (RTE_ULP_UART_TX_PORT_ID == 0) #define RTE_ULP_UART_TX_PORT 0 -#define RTE_ULP_UART_TX_PIN 7 -#define RTE_ULP_UART_TX_MUX 3 +#define RTE_ULP_UART_TX_PIN 7 +#define RTE_ULP_UART_TX_MUX 3 #elif (RTE_ULP_UART_TX_PORT_ID == 1) #define RTE_ULP_UART_TX_PORT 0 -#define RTE_ULP_UART_TX_PIN 11 -#define RTE_ULP_UART_TX_MUX 3 +#define RTE_ULP_UART_TX_PIN 11 +#define RTE_ULP_UART_TX_MUX 3 #else #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT -#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN -#define RTE_ULP_UART_TX_MUX 3 -// Pintool data +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data #endif // UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 @@ -869,25 +927,25 @@ #define RTE_ULP_UART_RX_PORT_ID 2 #if (RTE_ULP_UART_RX_PORT_ID == 0) #define RTE_ULP_UART_RX_PORT 0 -#define RTE_ULP_UART_RX_PIN 2 -#define RTE_ULP_UART_RX_MUX 3 +#define RTE_ULP_UART_RX_PIN 2 +#define RTE_ULP_UART_RX_MUX 3 #elif (RTE_ULP_UART_RX_PORT_ID == 1) #define RTE_ULP_UART_RX_PORT 0 -#define RTE_ULP_UART_RX_PIN 6 -#define RTE_ULP_UART_RX_MUX 3 +#define RTE_ULP_UART_RX_PIN 6 +#define RTE_ULP_UART_RX_MUX 3 #elif (RTE_ULP_UART_RX_PORT_ID == 2) #define RTE_ULP_UART_RX_PORT 0 -#define RTE_ULP_UART_RX_PIN 9 -#define RTE_ULP_UART_RX_MUX 3 +#define RTE_ULP_UART_RX_PIN 9 +#define RTE_ULP_UART_RX_MUX 3 #else #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT -#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN -#define RTE_ULP_UART_RX_MUX 3 -// Pintool data +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data #endif // UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 @@ -896,21 +954,21 @@ #define RTE_ULP_UART_CTS_PORT_ID 0 #if (RTE_ULP_UART_CTS_PORT_ID == 0) #define RTE_ULP_UART_CTS_PORT 0 -#define RTE_ULP_UART_CTS_PIN 1 -#define RTE_ULP_UART_CTS_MUX 3 +#define RTE_ULP_UART_CTS_PIN 1 +#define RTE_ULP_UART_CTS_MUX 3 #elif (RTE_ULP_UART_CTS_PORT_ID == 1) #define RTE_ULP_UART_CTS_PORT 0 -#define RTE_ULP_UART_CTS_PIN 8 -#define RTE_ULP_UART_CTS_MUX 3 +#define RTE_ULP_UART_CTS_PIN 8 +#define RTE_ULP_UART_CTS_MUX 3 #else #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT -#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN -#define RTE_ULP_UART_CTS_MUX 3 -// Pintool data +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data #endif // UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 @@ -919,27 +977,24 @@ #define RTE_ULP_UART_RTS_PORT_ID 0 #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 -#define RTE_ULP_UART_RTS_PIN 10 +#define RTE_ULP_UART_RTS_PIN 10 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif #else #define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT -#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN #endif #define RTE_ULP_UART_RTS_MUX 8 // // SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] -// Configuration settings for Driver_SSI_MASTER in component ::CMSIS -// Driver:SPI +// Configuration settings for Driver_SSI_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_MASTER 1 -#define RTE_SSI_MASTER_INPUT_CLOCK SSI_SOCPLLCLK - // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 -#ifndef SSI_MASTER_MISO_LOC +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -947,85 +1002,85 @@ #endif #if (RTE_SSI_MASTER_MISO_PORT_ID == 0) -#define RTE_SSI_MASTER_MISO 1 -#define RTE_SSI_MASTER_MISO_PORT 0 -#define RTE_SSI_MASTER_MISO_PIN 12 -#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 12 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_MISO_PADSEL 7 #elif (RTE_SSI_MASTER_MISO_PORT_ID == 1) -#define RTE_SSI_MASTER_MISO 1 -#define RTE_SSI_MASTER_MISO_PORT 0 -#define RTE_SSI_MASTER_MISO_PIN 27 -#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_MISO_PADSEL 0 // NO PAD +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 27 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD #elif (RTE_SSI_MASTER_MISO_PORT_ID == 2) -#define RTE_SSI_MASTER_MISO 1 -#define RTE_SSI_MASTER_MISO_PORT 0 -#define RTE_SSI_MASTER_MISO_PIN 57 -#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 57 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_MISO_PADSEL 21 #else #error "Invalid SSI_MASTER_MISO Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_MASTER_MISO 1 -#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_PT_PORT -#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_PT_PIN +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN #define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_MISO_LOC == 0) +#if (SSI_MASTER_DATA1_LOC == 3) #define RTE_SSI_MASTER_MISO_PADSEL 7 #endif -#if (SSI_MASTER_MISO_LOC == 1) -#define RTE_SSI_MASTER_MISO_PADSEL 0 // NO PAD +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_MISO_LOC == 2) +#if (SSI_MASTER_DATA1_LOC == 5) #define RTE_SSI_MASTER_MISO_PADSEL 21 #endif -// Pintool data +//Pintool data #endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 -#ifndef SSI_MASTER_MOSI_LOC +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) -#define RTE_SSI_MASTER_MOSI 1 -#define RTE_SSI_MASTER_MOSI_PORT 0 -#define RTE_SSI_MASTER_MOSI_PIN 11 -#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 11 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_MOSI_PADSEL 6 #elif (RTE_SSI_MASTER_MOSI_PORT_ID == 1) -#define RTE_SSI_MASTER_MOSI 1 -#define RTE_SSI_MASTER_MOSI_PORT 0 -#define RTE_SSI_MASTER_MOSI_PIN 26 -#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_MOSI_PADSEL 0 // NO PAD +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 26 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD #elif (RTE_SSI_MASTER_MOSI_PORT_ID == 2) -#define RTE_SSI_MASTER_MOSI 1 -#define RTE_SSI_MASTER_MOSI_PORT 0 -#define RTE_SSI_MASTER_MOSI_PIN 56 -#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 56 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_MOSI_PADSEL 20 #else #error "Invalid SSI_MASTER_MOSI Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_MASTER_MOSI 1 -#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_PT_PORT -#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_PT_PIN +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN #define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_MOSI_LOC == 0) +#if (SSI_MASTER_DATA0_LOC == 0) #define RTE_SSI_MASTER_MOSI_PADSEL 6 #endif -#if (SSI_MASTER_MOSI_LOC == 1) -#define RTE_SSI_MASTER_MOSI_PADSEL 0 // NO PAD +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_MOSI_LOC == 2) +#if (SSI_MASTER_DATA0_LOC == 2) #define RTE_SSI_MASTER_MOSI_PADSEL 20 #endif -// Pintool data +//Pintool data #endif // SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 @@ -1033,42 +1088,42 @@ #define RTE_SSI_MASTER_SCK_PORT_ID 1 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) -#define RTE_SSI_MASTER_SCK 1 -#define RTE_SSI_MASTER_SCK_PORT 0 -#define RTE_SSI_MASTER_SCK_PIN 8 -#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 8 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_SCK_PADSEL 3 #elif (RTE_SSI_MASTER_SCK_PORT_ID == 1) -#define RTE_SSI_MASTER_SCK 1 -#define RTE_SSI_MASTER_SCK_PORT 0 -#define RTE_SSI_MASTER_SCK_PIN 25 -#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_SCK_PADSEL 0 // NO PAD +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 25 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD #elif (RTE_SSI_MASTER_SCK_PORT_ID == 2) -#define RTE_SSI_MASTER_SCK 1 -#define RTE_SSI_MASTER_SCK_PORT 0 -#define RTE_SSI_MASTER_SCK_PIN 52 -#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 52 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_SCK_PADSEL 16 #else #error "Invalid SSI_MASTER_SCK Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_MASTER_SCK 1 -#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK_PT_PORT -#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK_PT_PIN +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN #define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_SCK_LOC == 0) +#if (SSI_MASTER_SCK_LOC == 6) #define RTE_SSI_MASTER_SCK_PADSEL 3 #endif -#if (SSI_MASTER_SCK_LOC == 1) -#define RTE_SSI_MASTER_SCK_PADSEL 0 // NO PAD +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_SCK_LOC == 2) +#if (SSI_MASTER_SCK_LOC == 8) #define RTE_SSI_MASTER_SCK_PADSEL 16 #endif -// Pintool data +//Pintool data #endif #define M4_SSI_CS0 1 @@ -1076,115 +1131,114 @@ #define M4_SSI_CS2 0 #define M4_SSI_CS3 0 -// SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 -// <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +// SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 #ifndef SSI_MASTER_CS0_LOC #define RTE_SSI_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) -#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 -#define RTE_SSI_MASTER_CS0_PORT 0 -#define RTE_SSI_MASTER_CS0_PIN 9 -#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 9 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_CS0_PADSEL 4 #elif (RTE_SSI_MASTER_CS0_PORT_ID == 1) -#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 -#define RTE_SSI_MASTER_CS0_PORT 0 -#define RTE_SSI_MASTER_CS0_PIN 28 -#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS0_PADSEL 0 // NO PAD +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 28 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD #elif (RTE_SSI_MASTER_CS0_PORT_ID == 2) -#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 -#define RTE_SSI_MASTER_CS0_PORT 0 -#define RTE_SSI_MASTER_CS0_PIN 53 -#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 53 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_CS0_PADSEL 17 #else #error "Invalid SSI_MASTER_CS0 Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 -#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0_PT_PORT -#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0_PT_PIN +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN #define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_CS0_LOC == 0) +#if (SSI_MASTER_CS0_LOC == 9) #define RTE_SSI_MASTER_CS0_PADSEL 4 #endif -#if (SSI_MASTER_CS0_LOC == 1) -#define RTE_SSI_MASTER_CS0_PADSEL 0 // NO PAD +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_CS0_LOC == 2) +#if (SSI_MASTER_CS0_LOC == 11) #define RTE_SSI_MASTER_CS0_PADSEL 17 #endif -// Pintool data +//Pintool data #endif -// CS1 +//CS1 #ifndef SSI_MASTER_CS1_LOC #define RTE_SSI_MASTER_CS1_PORT_ID 0 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) #define RTE_SSI_MASTER_CS1_PORT 0 -#define RTE_SSI_MASTER_CS1_PIN 10 +#define RTE_SSI_MASTER_CS1_PIN 10 #else #error "Invalid SSI_MASTER_CS1 Pin Configuration!" #endif #else -#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1_PT_PORT -#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1_PT_PIN +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN #endif -#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 -#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_CS1_PADSEL 5 -// CS2 +//CS2 #ifndef SSI_MASTER_CS2_LOC #define RTE_SSI_MASTER_CS2_PORT_ID 1 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) -#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 -#define RTE_SSI_MASTER_CS2_PORT 0 -#define RTE_SSI_MASTER_CS2_PIN 15 -#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 15 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_CS2_PADSEL 8 #elif (RTE_SSI_MASTER_CS2_PORT_ID == 1) -#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 -#define RTE_SSI_MASTER_CS2_PORT 0 -#define RTE_SSI_MASTER_CS2_PIN 50 -#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 50 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_CS2_PADSEL 14 #else #error "Invalid SSI_MASTER_CS2 Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 -#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2_PT_PORT -#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2_PT_PIN +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN #define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_CS2_LOC == 0) +#if (SSI_MASTER_CS2_LOC == 13) #define RTE_SSI_MASTER_CS2_PADSEL 8 #endif -#if (SSI_MASTER_CS2_LOC == 1) +#if (SSI_MASTER_CS2_LOC == 14) #define RTE_SSI_MASTER_CS2_PADSEL 14 #endif -// Pintool data +//Pintool data #endif -// CS3 +//CS3 #ifndef SSI_MASTER_CS3_LOC #define RTE_SSI_MASTER_CS3_PORT_ID 0 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) #define RTE_SSI_MASTER_CS3_PORT 0 -#define RTE_SSI_MASTER_CS3_PIN 51 +#define RTE_SSI_MASTER_CS3_PIN 51 #else #error "Invalid SSI_MASTER_CS3 Pin Configuration!" #endif #else -#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3_PT_PORT -#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3_PT_PIN +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN #endif -#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 -#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 #define RTE_SSI_MASTER_CS3_PADSEL 15 // DMA Rx @@ -1201,69 +1255,66 @@ // // SSI_SLAVE (Serial Peripheral Interface 2) [Driver_SSI_SLAVE] -// Configuration settings for Driver_SSI_SLAVE in component ::CMSIS -// Driver:SPI +// Configuration settings for Driver_SSI_SLAVE in component ::CMSIS Driver:SPI #define RTE_SSI_SLAVE 1 #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK -// SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 -// <4=>GPIO_57 +// SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 #ifndef SSI_SLAVE_MISO_LOC #define RTE_SSI_SLAVE_MISO_PORT_ID 2 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) #define RTE_SSI_SLAVE_MISO 0 #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 1) -#define RTE_SSI_SLAVE_MISO 1 -#define RTE_SSI_SLAVE_MISO_PORT 0 -#define RTE_SSI_SLAVE_MISO_PIN 11 -#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 11 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_MISO_PADSEL 6 #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 2) -#define RTE_SSI_SLAVE_MISO 1 -#define RTE_SSI_SLAVE_MISO_PORT 0 -#define RTE_SSI_SLAVE_MISO_PIN 28 -#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 -#define RTE_SSI_SLAVE_MISO_PADSEL 0 // no pad +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 28 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 3) -#define RTE_SSI_SLAVE_MISO 1 -#define RTE_SSI_SLAVE_MISO_PORT 0 -#define RTE_SSI_SLAVE_MISO_PIN 49 -#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 49 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_MISO_PADSEL 13 #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 4) -#define RTE_SSI_SLAVE_MISO 1 -#define RTE_SSI_SLAVE_MISO_PORT 0 -#define RTE_SSI_SLAVE_MISO_PIN 57 -#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 57 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_MISO_PADSEL 21 #else #error "Invalid SSI_SLAVE_MISO Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_SLAVE_MISO 1 -#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO_PT_PORT -#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO_PT_PIN +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN #define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_MISO_LOC == 1) +#if (SSI_SLAVE_MISO_LOC == 5) #define RTE_SSI_SLAVE_MISO_PADSEL 6 #endif -#if (SSI_SLAVE_MISO_LOC == 2) -#define RTE_SSI_SLAVE_MISO_PADSEL 0 // no pad +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_MISO_LOC == 3) +#if (SSI_SLAVE_MISO_LOC == 7) #define RTE_SSI_SLAVE_MISO_PADSEL 13 #endif -#if (SSI_SLAVE_MISO_LOC == 4) +#if (SSI_SLAVE_MISO_LOC == 8) #define RTE_SSI_SLAVE_MISO_PADSEL 21 #endif -// Pintool data +//Pintool data #endif -// SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 -// <4=>GPIO_56 +// SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 #ifndef SSI_SLAVE_MOSI_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 @@ -1274,43 +1325,43 @@ #if (RTE_SSI_SLAVE_MOSI_PORT_ID == 0) #define RTE_SSI_SLAVE_MOSI 0 #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 1) -#define RTE_SSI_SLAVE_MOSI 1 -#define RTE_SSI_SLAVE_MOSI_PORT 0 -#define RTE_SSI_SLAVE_MOSI_PIN 10 -#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 10 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_MOSI_PADSEL 5 #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 2) -#define RTE_SSI_SLAVE_MOSI 1 -#define RTE_SSI_SLAVE_MOSI_PORT 0 -#define RTE_SSI_SLAVE_MOSI_PIN 27 -#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 -#define RTE_SSI_SLAVE_MOSI_PADSEL 0 // no pad +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 27 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 3) -#define RTE_SSI_SLAVE_MOSI 1 -#define RTE_SSI_SLAVE_MOSI_PORT 0 -#define RTE_SSI_SLAVE_MOSI_PIN 48 -#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 48 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_MOSI_PADSEL 12 #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 4) -#define RTE_SSI_SLAVE_MOSI 1 -#define RTE_SSI_SLAVE_MOSI_PORT 0 -#define RTE_SSI_SLAVE_MOSI_PIN 56 -#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 56 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_MOSI_PADSEL 20 #else #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_SLAVE_MOSI 1 -#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI_PT_PORT -#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI_PT_PIN +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN #define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 #if (SSI_SLAVE_MOSI_LOC == 1) #define RTE_SSI_SLAVE_MOSI_PADSEL 5 #endif #if (SSI_SLAVE_MOSI_LOC == 2) -#define RTE_SSI_SLAVE_MOSI_PADSEL 0 // no pad +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad #endif #if (SSI_SLAVE_MOSI_LOC == 3) #define RTE_SSI_SLAVE_MOSI_PADSEL 12 @@ -1318,199 +1369,194 @@ #if (SSI_SLAVE_MOSI_LOC == 4) #define RTE_SSI_SLAVE_MOSI_PADSEL 20 #endif -// Pintool data +//Pintool data #endif -// SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 -// <4=>GPIO_52 +// SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 #ifndef SSI_SLAVE_SCK_LOC #define RTE_SSI_SLAVE_SCK_PORT_ID 2 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) #define RTE_SSI_SLAVE_SCK 0 #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 1) -#define RTE_SSI_SLAVE_SCK 1 -#define RTE_SSI_SLAVE_SCK_PORT 0 -#define RTE_SSI_SLAVE_SCK_PIN 8 -#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 8 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_SCK_PADSEL 3 #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 2) -#define RTE_SSI_SLAVE_SCK 1 -#define RTE_SSI_SLAVE_SCK_PORT 0 -#define RTE_SSI_SLAVE_SCK_PIN 26 -#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 -#define RTE_SSI_SLAVE_SCK_PADSEL 0 // no pad +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 26 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 3) -#define RTE_SSI_SLAVE_SCK 1 -#define RTE_SSI_SLAVE_SCK_PORT 0 -#define RTE_SSI_SLAVE_SCK_PIN 47 -#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 47 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_SCK_PADSEL 11 #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 4) -#define RTE_SSI_SLAVE_SCK 1 -#define RTE_SSI_SLAVE_SCK_PORT 0 -#define RTE_SSI_SLAVE_SCK_PIN 52 -#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 52 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_SCK_PADSEL 16 #else #error "Invalid SSI_SLAVE_SCK Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_SLAVE_SCK 1 -#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK_PT_PORT -#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK_PT_PIN +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN #define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_SCK_LOC == 1) +#if (SSI_SLAVE_SCK_LOC == 9) #define RTE_SSI_SLAVE_SCK_PADSEL 3 #endif -#if (SSI_SLAVE_SCK_LOC == 2) -#define RTE_SSI_SLAVE_SCK_PADSEL 0 // no pad +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_SCK_LOC == 3) +#if (SSI_SLAVE_SCK_LOC == 11) #define RTE_SSI_SLAVE_SCK_PADSEL 11 #endif -#if (SSI_SLAVE_SCK_LOC == 4) +#if (SSI_SLAVE_SCK_LOC == 12) #define RTE_SSI_SLAVE_SCK_PADSEL 16 #endif -// Pintool data +//Pintool data #endif -// SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 -// <4=>GPIO_53 -#ifndef SSI_SLAVE_CS_LOC +// SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC #define RTE_SSI_SLAVE_CS_PORT_ID 1 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) #define RTE_SSI_SLAVE_CS 0 #elif (RTE_SSI_SLAVE_CS_PORT_ID == 1) -#define RTE_SSI_SLAVE_CS 1 -#define RTE_SSI_SLAVE_CS_PORT 0 -#define RTE_SSI_SLAVE_CS_PIN 9 -#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 9 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_CS_PADSEL 4 #elif (RTE_SSI_SLAVE_CS_PORT_ID == 2) -#define RTE_SSI_SLAVE_CS 1 -#define RTE_SSI_SLAVE_CS_PORT 0 -#define RTE_SSI_SLAVE_CS_PIN 25 -#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 -#define RTE_SSI_SLAVE_CS_PADSEL 0 // no pad +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 25 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad #elif (RTE_SSI_SLAVE_CS_PORT_ID == 3) -#define RTE_SSI_SLAVE_CS 1 -#define RTE_SSI_SLAVE_CS_PORT 0 -#define RTE_SSI_SLAVE_CS_PIN 46 -#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 46 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_CS_PADSEL 10 #elif (RTE_SSI_SLAVE_CS_PORT_ID == 4) -#define RTE_SSI_SLAVE_CS 1 -#define RTE_SSI_SLAVE_CS_PORT 0 -#define RTE_SSI_SLAVE_CS_PIN 53 -#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 53 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 #define RTE_SSI_SLAVE_CS_PADSEL 17 #else #error "Invalid SSI_SLAVE_CS Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_SLAVE_CS 1 -#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS_PT_PORT -#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS_PT_PIN +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN #define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_CS_LOC == 1) +#if (SSI_SLAVE_CS0_LOC == 13) #define RTE_SSI_SLAVE_CS_PADSEL 4 #endif -#if (SSI_SLAVE_CS_LOC == 2) -#define RTE_SSI_SLAVE_CS_PADSEL 0 // no pad +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_CS_LOC == 3) +#if (SSI_SLAVE_CS0_LOC == 15) #define RTE_SSI_SLAVE_CS_PADSEL 10 #endif -#if (SSI_SLAVE_CS_LOC == 4) +#if (SSI_SLAVE_CS0_LOC == 16) #define RTE_SSI_SLAVE_CS_PADSEL 17 #endif -// Pintool data +//Pintool data #endif // DMA Rx // Channel <22=>22 // Selects DMA Channel (only Channel 22 can be used) // -#define RTE_SSI_SLAVE_UDMA_RX_CH 22 +#define RTE_SSI_SLAVE_UDMA_RX_CH 22 #define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024 // DMA Tx // Channel <23=>23 // Selects DMA Channel (only Channel 23 can be used) // -#define RTE_SSI_SLAVE_UDMA_TX_CH 23 +#define RTE_SSI_SLAVE_UDMA_TX_CH 23 #define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024 // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] -// Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS -// Driver:SPI +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 -#define RTE_SSI_ULP_MASTER_INPUT_CLOCK ULP_SSI_ULP_32MHZ_RC_CLK - // Enable multiple CSN lines #define ULP_SSI_CS0 1 #define ULP_SSI_CS1 0 #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 -#ifndef SSI_ULP_MASTER_MISO_LOC +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) -#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO 1 #define RTE_SSI_ULP_MASTER_MISO_PORT 0 -#define RTE_SSI_ULP_MASTER_MISO_PIN 2 +#define RTE_SSI_ULP_MASTER_MISO_PIN 2 #define RTE_SSI_ULP_MASTER_MISO_MODE 1 #elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 1) -#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO 1 #define RTE_SSI_ULP_MASTER_MISO_PORT 0 -#define RTE_SSI_ULP_MASTER_MISO_PIN 9 +#define RTE_SSI_ULP_MASTER_MISO_PIN 9 #define RTE_SSI_ULP_MASTER_MISO_MODE 1 #else #error "Invalid SSI_ULP_MISO Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_ULP_MASTER_MISO 1 -#define RTE_SSI_ULP_MASTER_MISO_PORT SSI_ULP_MASTER_MISO_PT_PORT -#define RTE_SSI_ULP_MASTER_MISO_PIN SSI_ULP_MASTER_MISO_PT_PIN +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN #define RTE_SSI_ULP_MASTER_MISO_MODE 1 -// Pintool data +//Pintool data #endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 -#ifndef SSI_ULP_MASTER_MOSI_LOC +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) -#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI 1 #define RTE_SSI_ULP_MASTER_MOSI_PORT 0 -#define RTE_SSI_ULP_MASTER_MOSI_PIN 1 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 1 #define RTE_SSI_ULP_MASTER_MOSI_MODE 1 #elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 1) -#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI 1 #define RTE_SSI_ULP_MASTER_MOSI_PORT 0 -#define RTE_SSI_ULP_MASTER_MOSI_PIN 11 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 11 #define RTE_SSI_ULP_MASTER_MOSI_MODE 1 #else #error "Invalid SSI_ULP_MOSI Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_ULP_MASTER_MOSI 1 -#define RTE_SSI_ULP_MASTER_MOSI_PORT SSI_ULP_MASTER_MOSI_PT_PORT -#define RTE_SSI_ULP_MASTER_MOSI_PIN SSI_ULP_MASTER_MOSI_PT_PIN +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN #define RTE_SSI_ULP_MASTER_MOSI_MODE 1 -// Pintool data +//Pintool data #endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 -#ifndef SSI_ULP_MASTER_SCK_LOC +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -1519,87 +1565,86 @@ #if (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_SCK 0 #elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 1) -#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK 1 #define RTE_SSI_ULP_MASTER_SCK_PORT 0 -#define RTE_SSI_ULP_MASTER_SCK_PIN 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 0 #define RTE_SSI_ULP_MASTER_SCK_MODE 1 #elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 2) -#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK 1 #define RTE_SSI_ULP_MASTER_SCK_PORT 0 -#define RTE_SSI_ULP_MASTER_SCK_PIN 8 +#define RTE_SSI_ULP_MASTER_SCK_PIN 8 #define RTE_SSI_ULP_MASTER_SCK_MODE 1 #else #error "Invalid SSI_ULP_SCK Pin Configuration!" #endif #else -// Pintool data -#define RTE_SSI_ULP_MASTER_SCK 1 -#define RTE_SSI_ULP_MASTER_SCK_PORT SSI_ULP_MASTER_SCK_PT_PORT -#define RTE_SSI_ULP_MASTER_SCK_PIN SSI_ULP_MASTER_SCK_PT_PIN +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN #define RTE_SSI_ULP_MASTER_SCK_MODE 1 -// Pintool data +//Pintool data #endif // CS0 -#ifndef SSI_ULP_MASTER_CS0_LOC +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) -#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 #define RTE_SSI_ULP_MASTER_CS0_PORT 0 -#define RTE_SSI_ULP_MASTER_CS0_PIN 3 +#define RTE_SSI_ULP_MASTER_CS0_PIN 3 #define RTE_SSI_ULP_MASTER_CS0_MODE 1 #elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 1) -#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 #define RTE_SSI_ULP_MASTER_CS0_PORT 0 -#define RTE_SSI_ULP_MASTER_CS0_PIN 10 +#define RTE_SSI_ULP_MASTER_CS0_PIN 10 #define RTE_SSI_ULP_MASTER_CS0_MODE 1 #else -#error \ - "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" +#error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" #endif #else -// Pintool data -#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 -#define RTE_SSI_ULP_MASTER_CS0_PORT SSI_ULP_MASTER_CS0_PT_PORT -#define RTE_SSI_ULP_MASTER_CS0_PIN SSI_ULP_MASTER_CS0_PT_PIN +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN #define RTE_SSI_ULP_MASTER_CS0_MODE 1 -// Pintool data +//Pintool data #endif // CS1 -#ifndef SSI_ULP_MASTER_CS1_LOC +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 -#define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#define RTE_SSI_ULP_MASTER_CS1_PIN 4 #else -#define RTE_SSI_ULP_MASTER_CS1_PORT SSI_ULP_MASTER_CS1_PT_PORT -#define RTE_SSI_ULP_MASTER_CS1_PIN SSI_ULP_MASTER_CS1_PT_PIN +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN #endif -#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#ifndef SSI_ULP_MASTER_CS2_LOC +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 -#define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#define RTE_SSI_ULP_MASTER_CS2_PIN 6 #else -#define RTE_SSI_ULP_MASTER_CS2_PORT SSI_ULP_MASTER_CS2_PT_PORT -#define RTE_SSI_ULP_MASTER_CS2_PIN SSI_ULP_MASTER_CS2_PT_PIN +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN #endif -#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 // DMA Rx // Channel <2=>2 // Selects DMA Channel (only Channel 2 can be used) // -#define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 +#define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 #define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96 // DMA Tx // Channel <3=>3 // Selects DMA Channel (only Channel 3 can be used) // -#define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 +#define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 #define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96 // @@ -1607,25 +1652,25 @@ UDMA Defines ====================================================================*/ // UDMA [Driver_UDMA] -#define DESC_MAX_LEN 0x400 -#define RTE_UDMA0 1 -#define UDMA0_IRQHandler IRQ033_Handler -#define CHNL_MASK_REQ0 0 -#define CHNL_PRIORITY0 0 -#define DMA_PERI_ACK0 0 -#define BURST_REQ0_EN 1 +#define DESC_MAX_LEN 0x400 +#define RTE_UDMA0 1 +#define UDMA0_IRQHandler IRQ033_Handler +#define CHNL_MASK_REQ0 0 +#define CHNL_PRIORITY0 0 +#define DMA_PERI_ACK0 0 +#define BURST_REQ0_EN 1 #define UDMA0_CHNL_PRIO_LVL 1 -#define UDMA0_SRAM_BASE 0x1FC00 - -#define RTE_UDMA1 1 -#define UDMA1_IRQHandler IRQ010_Handler -#define CHNL_MASK_REQ1 0 -#define CHNL_PRIORITY1 0 -#define BURST_REQ1_EN 1 -#define CHNL_HIGH_PRIO_EN1 1 +#define UDMA0_SRAM_BASE 0x1FC00 + +#define RTE_UDMA1 1 +#define UDMA1_IRQHandler IRQ010_Handler +#define CHNL_MASK_REQ1 0 +#define CHNL_PRIORITY1 0 +#define BURST_REQ1_EN 1 +#define CHNL_HIGH_PRIO_EN1 1 #define UDMA1_CHNL_PRIO_LVL 1 #define ULP_SRAM_START_ADDR 0x24060000 -#define ULP_SRAM_END_ADDR 0x24063E00 +#define ULP_SRAM_END_ADDR 0x24063E00 // RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4 #define RTE_UDMA1_BASE_MEM 0 #if (RTE_UDMA1_BASE_MEM == 0) @@ -1640,7 +1685,7 @@ // I2S0 [Driver_I2S0] // Configuration settings for Driver_I2S0 in component ::CMSIS Driver:I2S -#define RTE_I2S0 1 +#define RTE_I2S0 1 #define I2S0_IRQHandler IRQ064_Handler /*I2S0 PINS*/ @@ -1651,37 +1696,37 @@ #if (RTE_I2S0_SCLK_PORT_ID == 0) #define RTE_I2S0_SCLK_PORT 0 -#define RTE_I2S0_SCLK_PIN 8 -#define RTE_I2S0_SCLK_MUX 7 -#define RTE_I2S0_SCLK_PAD 3 +#define RTE_I2S0_SCLK_PIN 8 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 3 #elif (RTE_I2S0_SCLK_PORT_ID == 1) #define RTE_I2S0_SCLK_PORT 0 -#define RTE_I2S0_SCLK_PIN 25 -#define RTE_I2S0_SCLK_MUX 7 -#define RTE_I2S0_SCLK_PAD 0 // no pad +#define RTE_I2S0_SCLK_PIN 25 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 0 //no pad #elif (RTE_I2S0_SCLK_PORT_ID == 2) #define RTE_I2S0_SCLK_PORT 0 -#define RTE_I2S0_SCLK_PIN 46 -#define RTE_I2S0_SCLK_MUX 7 -#define RTE_I2S0_SCLK_PAD 10 +#define RTE_I2S0_SCLK_PIN 46 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 10 #elif (RTE_I2S0_SCLK_PORT_ID == 3) #define RTE_I2S0_SCLK_PORT 0 -#define RTE_I2S0_SCLK_PIN 52 -#define RTE_I2S0_SCLK_MUX 7 -#define RTE_I2S0_SCLK_PAD 16 +#define RTE_I2S0_SCLK_PIN 52 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 16 #else #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT -#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN -#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 #if (I2S0_SCLK_LOC == 0) #define RTE_I2S0_SCLK_PAD 3 #endif #if (I2S0_SCLK_LOC == 1) -#define RTE_I2S0_SCLK_PAD 0 // no pad +#define RTE_I2S0_SCLK_PAD 0 //no pad #endif #if (I2S0_SCLK_LOC == 2) #define RTE_I2S0_SCLK_PAD 10 @@ -1689,7 +1734,7 @@ #if (I2S0_SCLK_LOC == 3) #define RTE_I2S0_SCLK_PAD 16 #endif -// Pintool data +//Pintool data #endif // I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 @@ -1699,45 +1744,45 @@ #if (RTE_I2S0_WSCLK_PORT_ID == 0) #define RTE_I2S0_WSCLK_PORT 0 -#define RTE_I2S0_WSCLK_PIN 9 -#define RTE_I2S0_WSCLK_MUX 7 -#define RTE_I2S0_WSCLK_PAD 4 +#define RTE_I2S0_WSCLK_PIN 9 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 4 #elif (RTE_I2S0_WSCLK_PORT_ID == 1) #define RTE_I2S0_WSCLK_PORT 0 -#define RTE_I2S0_WSCLK_PIN 26 -#define RTE_I2S0_WSCLK_MUX 7 -#define RTE_I2S0_WSCLK_PAD 0 // no pad +#define RTE_I2S0_WSCLK_PIN 26 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 0 //no pad #elif (RTE_I2S0_WSCLK_PORT_ID == 2) #define RTE_I2S0_WSCLK_PORT 0 -#define RTE_I2S0_WSCLK_PIN 47 -#define RTE_I2S0_WSCLK_MUX 7 -#define RTE_I2S0_WSCLK_PAD 11 +#define RTE_I2S0_WSCLK_PIN 47 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 11 #elif (RTE_I2S0_WSCLK_PORT_ID == 3) #define RTE_I2S0_WSCLK_PORT 0 -#define RTE_I2S0_WSCLK_PIN 53 -#define RTE_I2S0_WSCLK_MUX 7 -#define RTE_I2S0_WSCLK_PAD 17 +#define RTE_I2S0_WSCLK_PIN 53 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 17 #else #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT -#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN -#define RTE_I2S0_WSCLK_MUX 7 -#if (I2S0_WSCLK_LOC == 0) +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) #define RTE_I2S0_WSCLK_PAD 4 #endif -#if (I2S0_WSCLK_LOC == 1) +#if (I2S0_WSCLK_LOC == 5) #define RTE_I2S0_WSCLK_PAD 0 #endif -#if (I2S0_WSCLK_LOC == 2) +#if (I2S0_WSCLK_LOC == 6) #define RTE_I2S0_WSCLK_PAD 11 #endif -#if (I2S0_WSCLK_LOC == 3) +#if (I2S0_WSCLK_LOC == 7) #define RTE_I2S0_WSCLK_PAD 17 #endif -// Pintool data +//Pintool data #endif // I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 @@ -1747,45 +1792,45 @@ #if (RTE_I2S0_DOUT0_PORT_ID == 0) #define RTE_I2S0_DOUT0_PORT 0 -#define RTE_I2S0_DOUT0_PIN 11 -#define RTE_I2S0_DOUT0_MUX 7 -#define RTE_I2S0_DOUT0_PAD 6 +#define RTE_I2S0_DOUT0_PIN 11 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 6 #elif (RTE_I2S0_DOUT0_PORT_ID == 1) #define RTE_I2S0_DOUT0_PORT 0 -#define RTE_I2S0_DOUT0_PIN 28 -#define RTE_I2S0_DOUT0_MUX 7 -#define RTE_I2S0_DOUT0_PAD 0 // no pad +#define RTE_I2S0_DOUT0_PIN 28 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 0 // no pad #elif (RTE_I2S0_DOUT0_PORT_ID == 2) #define RTE_I2S0_DOUT0_PORT 0 -#define RTE_I2S0_DOUT0_PIN 49 -#define RTE_I2S0_DOUT0_MUX 7 -#define RTE_I2S0_DOUT0_PAD 13 +#define RTE_I2S0_DOUT0_PIN 49 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 13 #elif (RTE_I2S0_DOUT0_PORT_ID == 3) #define RTE_I2S0_DOUT0_PORT 0 -#define RTE_I2S0_DOUT0_PIN 57 -#define RTE_I2S0_DOUT0_MUX 7 -#define RTE_I2S0_DOUT0_PAD 21 +#define RTE_I2S0_DOUT0_PIN 57 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 21 #else #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT -#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN -#define RTE_I2S0_DOUT0_MUX 7 -#if (I2S0_DOUT0_LOC == 0) +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) #define RTE_I2S0_DOUT0_PAD 6 #endif -#if (I2S0_DOUT0_LOC == 1) +#if (I2S0_DOUT0_LOC == 9) #define RTE_I2S0_DOUT0_PAD 0 #endif -#if (I2S0_DOUT0_LOC == 2) +#if (I2S0_DOUT0_LOC == 10) #define RTE_I2S0_DOUT0_PAD 13 #endif -#if (I2S0_DOUT0_LOC == 3) +#if (I2S0_DOUT0_LOC == 11) #define RTE_I2S0_DOUT0_PAD 21 #endif -// Pintool data +//Pintool data #endif // I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 @@ -1795,45 +1840,45 @@ #if (RTE_I2S0_DIN0_PORT_ID == 0) #define RTE_I2S0_DIN0_PORT 0 -#define RTE_I2S0_DIN0_PIN 10 -#define RTE_I2S0_DIN0_MUX 7 -#define RTE_I2S0_DIN0_PAD 5 +#define RTE_I2S0_DIN0_PIN 10 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 5 #elif (RTE_I2S0_DIN0_PORT_ID == 1) #define RTE_I2S0_DIN0_PORT 0 -#define RTE_I2S0_DIN0_PIN 27 -#define RTE_I2S0_DIN0_MUX 7 -#define RTE_I2S0_DIN0_PAD 0 // no pad +#define RTE_I2S0_DIN0_PIN 27 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 0 // no pad #elif (RTE_I2S0_DIN0_PORT_ID == 2) #define RTE_I2S0_DIN0_PORT 0 -#define RTE_I2S0_DIN0_PIN 48 -#define RTE_I2S0_DIN0_MUX 7 -#define RTE_I2S0_DIN0_PAD 12 +#define RTE_I2S0_DIN0_PIN 48 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 12 #elif (RTE_I2S0_DIN0_PORT_ID == 3) #define RTE_I2S0_DIN0_PORT 0 -#define RTE_I2S0_DIN0_PIN 56 -#define RTE_I2S0_DIN0_MUX 7 -#define RTE_I2S0_DIN0_PAD 20 +#define RTE_I2S0_DIN0_PIN 56 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 20 #else #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT -#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN -#define RTE_I2S0_DIN0_MUX 7 -#if (I2S0_DIN0_LOC == 0) +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) #define RTE_I2S0_DIN0_PAD 5 #endif -#if (I2S0_DIN0_LOC == 1) +#if (I2S0_DIN0_LOC == 13) #define RTE_I2S0_DIN0_PAD 0 #endif -#if (I2S0_DIN0_LOC == 2) +#if (I2S0_DIN0_LOC == 14) #define RTE_I2S0_DIN0_PAD 12 #endif -#if (I2S0_DIN0_LOC == 3) +#if (I2S0_DIN0_LOC == 15) #define RTE_I2S0_DIN0_PAD 20 #endif -// Pintool data +//Pintool data #endif // I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 @@ -1847,45 +1892,45 @@ #if (RTE_I2S0_DOUT1_PORT_ID == 0) #define RTE_I2S0_DOUT1_PORT 0 -#define RTE_I2S0_DOUT1_PIN 7 -#define RTE_I2S0_DOUT1_MUX 7 -#define RTE_I2S0_DOUT1_PAD 2 +#define RTE_I2S0_DOUT1_PIN 7 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 2 #elif (RTE_I2S0_DOUT1_PORT_ID == 1) #define RTE_I2S0_DOUT1_PORT 0 -#define RTE_I2S0_DOUT1_PIN 30 -#define RTE_I2S0_DOUT1_MUX 7 -#define RTE_I2S0_DOUT1_PAD 0 // no pad +#define RTE_I2S0_DOUT1_PIN 30 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 0 //no pad #elif (RTE_I2S0_DOUT1_PORT_ID == 2) #define RTE_I2S0_DOUT1_PORT 0 -#define RTE_I2S0_DOUT1_PIN 51 -#define RTE_I2S0_DOUT1_MUX 7 -#define RTE_I2S0_DOUT1_PAD 15 +#define RTE_I2S0_DOUT1_PIN 51 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 15 #elif (RTE_I2S0_DOUT1_PORT_ID == 3) #define RTE_I2S0_DOUT1_PORT 0 -#define RTE_I2S0_DOUT1_PIN 55 -#define RTE_I2S0_DOUT1_MUX 7 -#define RTE_I2S0_DOUT1_PAD 19 +#define RTE_I2S0_DOUT1_PIN 55 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 19 #else #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT -#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN -#define RTE_I2S0_DOUT1_MUX 7 -#if (I2S0_DOUT1_LOC == 0) +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) #define RTE_I2S0_DOUT1_PAD 2 #endif -#if (I2S0_DOUT1_LOC == 1) +#if (I2S0_DOUT1_LOC == 17) #define RTE_I2S0_DOUT1_PAD 0 #endif -#if (I2S0_DOUT1_LOC == 2) +#if (I2S0_DOUT1_LOC == 18) #define RTE_I2S0_DOUT1_PAD 15 #endif -#if (I2S0_DOUT1_LOC == 3) +#if (I2S0_DOUT1_LOC == 19) #define RTE_I2S0_DOUT1_PAD 19 #endif -// Pintool data +//Pintool data #endif // I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 @@ -1895,48 +1940,48 @@ #if (RTE_I2S0_DIN1_PORT_ID == 0) #define RTE_I2S0_DIN1_PORT 0 -#define RTE_I2S0_DIN1_PIN 6 -#define RTE_I2S0_DIN1_MUX 7 -#define RTE_I2S0_DIN1_PAD 1 +#define RTE_I2S0_DIN1_PIN 6 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 1 #elif (RTE_I2S0_DIN1_PORT_ID == 1) #define RTE_I2S0_DIN1_PORT 0 -#define RTE_I2S0_DIN1_PIN 29 -#define RTE_I2S0_DIN1_MUX 7 -#define RTE_I2S0_DIN1_PAD 0 // no pad +#define RTE_I2S0_DIN1_PIN 29 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 0 //no pad #elif (RTE_I2S0_DIN1_PORT_ID == 2) #define RTE_I2S0_DIN1_PORT 0 -#define RTE_I2S0_DIN1_PIN 50 -#define RTE_I2S0_DIN1_MUX 7 -#define RTE_I2S0_DIN1_PAD 14 +#define RTE_I2S0_DIN1_PIN 50 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 14 #elif (RTE_I2S0_DIN1_PORT_ID == 3) #define RTE_I2S0_DIN1_PORT 0 -#define RTE_I2S0_DIN1_PIN 54 -#define RTE_I2S0_DIN1_MUX 7 -#define RTE_I2S0_DIN1_PAD 18 +#define RTE_I2S0_DIN1_PIN 54 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 18 #else #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT -#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN -#define RTE_I2S0_DIN1_MUX 7 -#if (I2S0_DIN1_LOC == 0) +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) #define RTE_I2S0_DIN1_PAD 1 #endif -#if (I2S0_DIN1_LOC == 1) +#if (I2S0_DIN1_LOC == 21) #define RTE_I2S0_DIN1_PAD 0 #endif -#if (I2S0_DIN1_LOC == 2) +#if (I2S0_DIN1_LOC == 22) #define RTE_I2S0_DIN1_PAD 14 #endif -#if (I2S0_DIN1_LOC == 3) +#if (I2S0_DIN1_LOC == 23) #define RTE_I2S0_DIN1_PAD 18 #endif -// Pintool data +//Pintool data #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1979,23 +2024,19 @@ #define RTE_I2S0_CHNL_UDMA_RX_EN 1 #define RTE_I2S0_CHNL_UDMA_RX_CH 14 -#define RTE_I2S0_CLK_SRC 0 -#define RTE_I2S0_CLK_DIV_FACT 0 -#define RTE_I2S_PLL_FREQ 2000 - #define RTE_I2S0_DMA_TX_LEN_PER_DES 1024 #define RTE_I2S0_DMA_RX_LEN_PER_DES 1024 // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S -#define RTE_I2S1 1 +#define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler // I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ -#ifndef I2S1_SCLK_LOC +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -2003,99 +2044,99 @@ #endif #if (RTE_I2S1_SCLK_PORT_ID == 0) #define RTE_I2S1_SCLK_PORT 0 -#define RTE_I2S1_SCLK_PIN 3 -#define RTE_I2S1_SCLK_MUX 2 +#define RTE_I2S1_SCLK_PIN 3 +#define RTE_I2S1_SCLK_MUX 2 #elif (RTE_I2S1_SCLK_PORT_ID == 1) #define RTE_I2S1_SCLK_PORT 0 -#define RTE_I2S1_SCLK_PIN 7 -#define RTE_I2S1_SCLK_MUX 2 +#define RTE_I2S1_SCLK_PIN 7 +#define RTE_I2S1_SCLK_MUX 2 #elif (RTE_I2S1_SCLK_PORT_ID == 2) #define RTE_I2S1_SCLK_PORT 0 -#define RTE_I2S1_SCLK_PIN 8 -#define RTE_I2S1_SCLK_MUX 2 +#define RTE_I2S1_SCLK_PIN 8 +#define RTE_I2S1_SCLK_MUX 2 #else #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" #endif #else -// Pintool data -#define RTE_I2S1_SCLK_PORT I2S1_SCLK_PORT -#define RTE_I2S1_SCLK_PIN I2S1_SCLK_PIN -#define RTE_I2S1_SCLK_MUX 2 -// Pintool data +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data #endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 -#ifndef I2S1_WSCLK_LOC +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 -#define RTE_I2S1_WSCLK_PIN 2 -#define RTE_I2S1_WSCLK_MUX 2 +#define RTE_I2S1_WSCLK_PIN 2 +#define RTE_I2S1_WSCLK_MUX 2 #elif (RTE_I2S1_WSCLK_PORT_ID == 1) #define RTE_I2S1_WSCLK_PORT 0 -#define RTE_I2S1_WSCLK_PIN 10 -#define RTE_I2S1_WSCLK_MUX 2 +#define RTE_I2S1_WSCLK_PIN 10 +#define RTE_I2S1_WSCLK_MUX 2 #else #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" #endif #else -// Pintool data -#define RTE_I2S1_WSCLK_PORT I2S1_WSCLK_PORT -#define RTE_I2S1_WSCLK_PIN I2S1_WSCLK_PIN -#define RTE_I2S1_WSCLK_MUX 2 -// Pintool data +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data #endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 -#ifndef I2S1_DOUT0_LOC +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 -#define RTE_I2S1_DOUT0_PIN 1 -#define RTE_I2S1_DOUT0_MUX 2 +#define RTE_I2S1_DOUT0_PIN 1 +#define RTE_I2S1_DOUT0_MUX 2 #elif (RTE_I2S1_DOUT0_PORT_ID == 1) #define RTE_I2S1_DOUT0_PORT 0 -#define RTE_I2S1_DOUT0_PIN 11 -#define RTE_I2S1_DOUT0_MUX 2 +#define RTE_I2S1_DOUT0_PIN 11 +#define RTE_I2S1_DOUT0_MUX 2 #else #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" #endif #else -// Pintool data -#define RTE_I2S1_DOUT0_PORT I2S1_DOUT0_PORT -#define RTE_I2S1_DOUT0_PIN I2S1_DOUT0_PIN -#define RTE_I2S1_DOUT0_MUX 2 -// Pintool data +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data #endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 -#ifndef I2S1_DIN0_LOC +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 -#define RTE_I2S1_DIN0_PIN 0 -#define RTE_I2S1_DIN0_MUX 2 +#define RTE_I2S1_DIN0_PIN 0 +#define RTE_I2S1_DIN0_MUX 2 #elif (RTE_I2S1_DIN0_PORT_ID == 1) #define RTE_I2S1_DIN0_PORT 0 -#define RTE_I2S1_DIN0_PIN 6 -#define RTE_I2S1_DIN0_MUX 2 +#define RTE_I2S1_DIN0_PIN 6 +#define RTE_I2S1_DIN0_MUX 2 #elif (RTE_I2S1_DIN0_PORT_ID == 2) #define RTE_I2S1_DIN0_PORT 0 -#define RTE_I2S1_DIN0_PIN 9 -#define RTE_I2S1_DIN0_MUX 2 +#define RTE_I2S1_DIN0_PIN 9 +#define RTE_I2S1_DIN0_MUX 2 #else #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" #endif #else -// Pintool data -#define RTE_I2S1_DIN0_PORT I2S1_DIN0_PORT -#define RTE_I2S1_DIN0_PIN I2S1_DIN0_PIN -#define RTE_I2S1_DIN0_MUX 2 -// Pintool data +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data #endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -2138,39 +2179,6 @@ #define RTE_I2S1_CHNL_UDMA_RX_EN 1 #define RTE_I2S1_CHNL_UDMA_RX_CH 6 -#define I2S1_CLK_DIV_FACT 0 -// I2S1_CLK_SRC <0=>ULP_I2S_REF_CLK -// <1=>ULP_I2S_ULP_32KHZ_RO_CLK -// <2=>ULP_I2S_ULP_32KHZ_RC_CLK -// <3=>ULP_I2S_ULP_32KHZ_XTAL_CLK -// <4=>ULP_I2S_ULP_32MHZ_RC_CLK -// <5=>ULP_I2S_ULP_20MHZ_RO_CLK -// <6=>ULP_I2S_SOC_CLK -// <7=>ULP_I2S_ULP_DOUBLER_CLK -// <8=>ULP_I2S_PLL_CLK - -#define RTE_I2S1_CLK_SEL_ID 5 -#if (RTE_I2S1_CLK_SEL_ID == 0) -#define RTE_I2S1_CLK_SRC ULP_I2S_REF_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 1) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32KHZ_RO_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 2) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32KHZ_RC_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 3) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32KHZ_XTAL_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 4) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32MHZ_RC_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 5) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_20MHZ_RO_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 6) -#define RTE_I2S1_CLK_SRC ULP_I2S_SOC_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 7) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_DOUBLER_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 8) -#define RTE_I2S1_CLK_SRC ULP_I2S_PLL_CLK -#else -#error "Invalid I2S1 Clock source selection!" -#endif #define RTE_I2S1_DMA_TX_LEN_PER_DES 1024 #define RTE_I2S1_DMA_RX_LEN_PER_DES 1024 @@ -2179,7 +2187,7 @@ // I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] // Configuration settings for Driver_I2C0 in component ::Drivers:I2C -#define RTE_I2C0 1 +#define RTE_I2C0 1 #define I2C0_IRQHandler IRQ042_Handler // I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 @@ -2187,60 +2195,54 @@ #define RTE_I2C0_SCL_PORT_ID 1 #if (RTE_I2C0_SCL_PORT_ID == 0) -#define RTE_I2C0_SCL_PORT 0 -#define RTE_I2C0_SCL_PIN 7 -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 7 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 #define RTE_I2C0_SCL_I2C_REN 7 #elif (RTE_I2C0_SCL_PORT_ID == 1) -#define RTE_I2C0_SCL_PORT 0 -#define RTE_I2C0_SCL_PIN 65 -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 65 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 #define RTE_I2C0_SCL_I2C_REN 1 #elif (RTE_I2C0_SCL_PORT_ID == 2) -#define RTE_I2C0_SCL_PORT 0 -#define RTE_I2C0_SCL_PIN 66 -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 24 +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 66 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 24 #define RTE_I2C0_SCL_I2C_REN 2 #elif (RTE_I2C0_SCL_PORT_ID == 3) -#define RTE_I2C0_SCL_PORT 0 -#define RTE_I2C0_SCL_PIN 75 -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 75 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 #define RTE_I2C0_SCL_I2C_REN 11 #else #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2C0_SCL_PORT I2C0_SCL_PORT #if (I2C0_SCL_LOC == 0) -#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 #define RTE_I2C0_SCL_I2C_REN 7 #endif #if (I2C0_SCL_LOC == 1) -#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 #define RTE_I2C0_SCL_I2C_REN 1 #endif #if (I2C0_SCL_LOC == 2) -#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 24 -#define RTE_I2C0_SCL_I2C_REN 2 -#endif -#if (I2C0_SCL_LOC == 3) -#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) -#define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 #define RTE_I2C0_SCL_I2C_REN 11 #endif -// Pintool data +//Pintool data #endif // I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 @@ -2252,48 +2254,48 @@ #endif #if (RTE_I2C0_SDA_PORT_ID == 0) -#define RTE_I2C0_SDA_PORT 0 -#define RTE_I2C0_SDA_PIN 6 -#define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 6 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 #define RTE_I2C0_SDA_I2C_REN 6 #elif (RTE_I2C0_SDA_PORT_ID == 1) -#define RTE_I2C0_SDA_PORT 0 -#define RTE_I2C0_SDA_PIN 67 -#define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 25 +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 67 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 25 #define RTE_I2C0_SDA_I2C_REN 3 #elif (RTE_I2C0_SDA_PORT_ID == 2) -#define RTE_I2C0_SDA_PORT 0 -#define RTE_I2C0_SDA_PIN 74 -#define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 74 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 #define RTE_I2C0_SDA_I2C_REN 10 #else #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2C0_SDA_PORT I2C0_SDA_PORT -#if (I2C0_SDA_LOC == 0) -#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN -#define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 1 +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 #define RTE_I2C0_SDA_I2C_REN 6 #endif -#if (I2C0_SDA_LOC == 1) -#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) -#define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 25 +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 #define RTE_I2C0_SDA_I2C_REN 3 #endif -#if (I2C0_SDA_LOC == 2) -#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) -#define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 32 +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 #define RTE_I2C0_SDA_I2C_REN 10 #endif -// Pintool data +//Pintool data #endif #define IC_SCL_STUCK_TIMEOUT 20 @@ -2304,59 +2306,58 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 1 +#define RTE_I2C1 1 #define I2C1_IRQHandler IRQ061_Handler -// I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 -// <4=>P0_66 <4=>P0_70 <7=>P0_33 +// I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 #ifndef I2C1_SCL_LOC #define RTE_I2C1_SCL_PORT_ID 2 #if (RTE_I2C1_SCL_PORT_ID == 0) #define RTE_I2C1_SCL_PORT 0 -#define RTE_I2C1_SCL_PIN 6 -#define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 1 -#define RTE_I2C1_SCL_REN 6 +#define RTE_I2C1_SCL_PIN 6 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 #elif (RTE_I2C1_SCL_PORT_ID == 1) #define RTE_I2C1_SCL_PORT 0 -#define RTE_I2C1_SCL_PIN 29 -#define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 0 // no pad -#define RTE_I2C1_SCL_REN 29 +#define RTE_I2C1_SCL_PIN 29 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 #elif (RTE_I2C1_SCL_PORT_ID == 2) #define RTE_I2C1_SCL_PORT 0 -#define RTE_I2C1_SCL_PIN 50 -#define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 14 -#define RTE_I2C1_SCL_REN 50 +#define RTE_I2C1_SCL_PIN 50 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 #elif (RTE_I2C1_SCL_PORT_ID == 3) #define RTE_I2C1_SCL_PORT 0 -#define RTE_I2C1_SCL_PIN 54 -#define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 18 -#define RTE_I2C1_SCL_REN 54 +#define RTE_I2C1_SCL_PIN 54 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 #elif (RTE_I2C1_SCL_PORT_ID == 5) #define RTE_I2C1_SCL_PORT 0 -#define RTE_I2C1_SCL_PIN 66 -#define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 24 -#define RTE_I2C1_SCL_REN 2 +#define RTE_I2C1_SCL_PIN 66 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_REN 2 #elif (RTE_I2C1_SCL_PORT_ID == 6) #define RTE_I2C1_SCL_PORT 0 -#define RTE_I2C1_SCL_PIN 70 -#define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 29 -#define RTE_I2C1_SCL_REN 6 +#define RTE_I2C1_SCL_PIN 70 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 #else #error "Invalid I2C1_SCL Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2C1_SCL_PORT I2C1_SCL_PORT #if (I2C1_SCL_LOC == 0) #define RTE_I2C1_SCL_PIN I2C1_SCL_PIN @@ -2367,7 +2368,7 @@ #if (I2C1_SCL_LOC == 1) #define RTE_I2C1_SCL_PIN I2C1_SCL_PIN #define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 0 // no pad +#define RTE_I2C1_SCL_PAD 0 //no pad #define RTE_I2C1_SCL_REN 29 #endif #if (I2C1_SCL_LOC == 2) @@ -2382,117 +2383,110 @@ #define RTE_I2C1_SCL_PAD 18 #define RTE_I2C1_SCL_REN 54 #endif -#if (I2C1_SCL_LOC == 5) +#if (I2C1_SCL_LOC == 4) #define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_PAD 22 #define RTE_I2C1_SCL_REN 2 #endif -#if (I2C1_SCL_LOC == 6) +#if (I2C1_SCL_LOC == 5) #define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SCL_MUX 5 #define RTE_I2C1_SCL_PAD 29 #define RTE_I2C1_SCL_REN 6 #endif -// Pintool data +//Pintool data #endif -// I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 -// <4=>P0_71 <7=>P0_34 +// I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 #ifndef I2C1_SDA_LOC #define RTE_I2C1_SDA_PORT_ID 2 #if (RTE_I2C1_SDA_PORT_ID == 0) #define RTE_I2C1_SDA_PORT 0 -#define RTE_I2C1_SDA_PIN 7 -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 2 -#define RTE_I2C1_SDA_REN 7 +#define RTE_I2C1_SDA_PIN 7 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 #elif (RTE_I2C1_SDA_PORT_ID == 1) #define RTE_I2C1_SDA_PORT 0 -#define RTE_I2C1_SDA_PIN 30 -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 0 // no pad -#define RTE_I2C1_SDA_REN 30 +#define RTE_I2C1_SDA_PIN 30 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 #elif (RTE_I2C1_SDA_PORT_ID == 2) #define RTE_I2C1_SDA_PORT 0 -#define RTE_I2C1_SDA_PIN 51 -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 15 -#define RTE_I2C1_SDA_REN 51 +#define RTE_I2C1_SDA_PIN 51 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 #elif (RTE_I2C1_SDA_PORT_ID == 3) #define RTE_I2C1_SDA_PORT 0 -#define RTE_I2C1_SDA_PIN 55 -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 19 -#define RTE_I2C1_SDA_REN 55 +#define RTE_I2C1_SDA_PIN 55 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 #elif (RTE_I2C1_SDA_PORT_ID == 4) #define RTE_I2C1_SDA_PORT 0 -#define RTE_I2C1_SDA_PIN 65 -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 23 -#define RTE_I2C1_SDA_REN 1 +#define RTE_I2C1_SDA_PIN 65 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 #elif (RTE_I2C1_SDA_PORT_ID == 5) #define RTE_I2C1_SDA_PORT 0 -#define RTE_I2C1_SDA_PIN 67 -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 25 -#define RTE_I2C1_SDA_REN 3 +#define RTE_I2C1_SDA_PIN 67 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 25 +#define RTE_I2C1_SDA_REN 3 #elif (RTE_I2C1_SDA_PORT_ID == 6) #define RTE_I2C1_SDA_PORT 0 -#define RTE_I2C1_SDA_PIN 71 -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 29 -#define RTE_I2C1_SDA_REN 7 +#define RTE_I2C1_SDA_PIN 71 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 #else #error "Invalid I2C1_SDA Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2C1_SDA_PORT I2C1_SDA_PORT -#if (I2C1_SDA_LOC == 0) +#if (I2C1_SDA_LOC == 6) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 2 #define RTE_I2C1_SDA_REN 7 #endif -#if (I2C1_SDA_LOC == 1) +#if (I2C1_SDA_LOC == 7) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 0 // no pad +#define RTE_I2C1_SDA_PAD 0 //no pad #define RTE_I2C1_SDA_REN 30 #endif -#if (I2C1_SDA_LOC == 2) +#if (I2C1_SDA_LOC == 8) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 15 #define RTE_I2C1_SDA_REN 51 #endif -#if (I2C1_SDA_LOC == 3) +#if (I2C1_SDA_LOC == 9) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 19 #define RTE_I2C1_SDA_REN 55 #endif -#if (I2C1_SDA_LOC == 4) +#if (I2C1_SDA_LOC == 10) #define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 23 #define RTE_I2C1_SDA_REN 1 #endif -#if (I2C1_SDA_LOC == 5) -#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 25 -#define RTE_I2C1_SDA_REN 3 -#endif -#if (I2C1_SDA_LOC == 6) +#if (I2C1_SDA_LOC == 11) #define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 29 #define RTE_I2C1_SDA_REN 7 #endif -// Pintool data +//Pintool data #endif #define IC_SCL_STUCK_TIMEOUT 20 @@ -2506,13 +2500,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 1 +#define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 -#ifndef I2C2_SCL_LOC +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -2520,67 +2514,72 @@ #endif #if (RTE_I2C2_SCL_PORT_ID == 0) #define RTE_I2C2_SCL_PORT 0 -#define RTE_I2C2_SCL_PIN 7 -#define RTE_I2C2_SCL_MUX 4 -#define RTE_I2C2_SCL_REN 7 +#define RTE_I2C2_SCL_PIN 7 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 7 #elif (RTE_I2C2_SCL_PORT_ID == 1) #define RTE_I2C2_SCL_PORT 0 -#define RTE_I2C2_SCL_PIN 8 -#define RTE_I2C2_SCL_MUX 4 -#define RTE_I2C2_SCL_REN 8 +#define RTE_I2C2_SCL_PIN 8 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 8 #else #error "Invalid I2C2_SCL Pin Configuration!" #endif #else -// Pintool data -#define RTE_I2C2_SCL_PORT I2C2_SCL_PORT -#define RTE_I2C2_SCL_PIN I2C2_SCL_PIN -#define RTE_I2C2_SCL_MUX 4 -#if (I2C2_SCL_LOC == 0) +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) #define RTE_I2C2_SCL_REN 7 -#endif -#if (I2C2_SCL_LOC == 1) +#elif (ULP_I2C_SCL_LOC == 3) #define RTE_I2C2_SCL_REN 8 #endif -// Pintool data +//Pintool data #endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 -#ifndef I2C2_SDA_LOC +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 6 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_REN 6 +#define RTE_I2C2_SDA_PIN 6 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) #define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 11 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_REN 11 +#define RTE_I2C2_SDA_PIN 11 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 11 #else #error "Invalid I2C2_SDA Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_I2C2_SDA_PORT I2C2_SDA_PORT -#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN -#define RTE_I2C2_SDA_MUX 4 -#if (I2C2_SDA_LOC == 0) +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) #define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 #endif -#if (I2C2_SDA_LOC == 1) -#define RTE_I2C2_SDA_MUX 4 -#endif -#if (I2C2_SDA_LOC == 2) -#define RTE_I2C2_SDA_MUX 4 -#endif -// Pintool data +//Pintool data #endif #define IC_SCL_STUCK_TIMEOUT 20 @@ -2600,50 +2599,50 @@ // GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // CLK of GSPI0 -#ifndef GSPI_MASTER_CLK_LOC +#ifndef GSPI_MASTER_SCK_LOC #define RTE_GSPI_MASTER_CLK_PORT_ID 1 #if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) #define RTE_GSPI_MASTER_CLK_PORT 0 -#define RTE_GSPI_MASTER_CLK_PIN 8 -#define RTE_GSPI_MASTER_CLK_MUX 4 -#define RTE_GSPI_MASTER_CLK_PAD 3 +#define RTE_GSPI_MASTER_CLK_PIN 8 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 3 #elif (RTE_GSPI_MASTER_CLK_PORT_ID == 1) #define RTE_GSPI_MASTER_CLK_PORT 0 -#define RTE_GSPI_MASTER_CLK_PIN 25 -#define RTE_GSPI_MASTER_CLK_MUX 4 -#define RTE_GSPI_MASTER_CLK_PAD 0 // NO PAD +#define RTE_GSPI_MASTER_CLK_PIN 25 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 0 //NO PAD #elif (RTE_GSPI_MASTER_CLK_PORT_ID == 2) #define RTE_GSPI_MASTER_CLK_PORT 0 -#define RTE_GSPI_MASTER_CLK_PIN 46 -#define RTE_GSPI_MASTER_CLK_MUX 4 -#define RTE_GSPI_MASTER_CLK_PAD 10 +#define RTE_GSPI_MASTER_CLK_PIN 46 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 10 #elif (RTE_GSPI_MASTER_CLK_PORT_ID == 3) #define RTE_GSPI_MASTER_CLK_PORT 0 -#define RTE_GSPI_MASTER_CLK_PIN 52 -#define RTE_GSPI_MASTER_CLK_MUX 4 -#define RTE_GSPI_MASTER_CLK_PAD 16 +#define RTE_GSPI_MASTER_CLK_PIN 52 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 16 #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_CLK_PORT -#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_CLK_PIN -#define RTE_GSPI_MASTER_CLK_MUX 4 -#if (GSPI_MASTER_CLK_LOC == 0) +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) #define RTE_GSPI_MASTER_CLK_PAD 3 #endif -#if (GSPI_MASTER_CLK_LOC == 1) +#if (GSPI_MASTER_SCK_LOC == 1) #define RTE_GSPI_MASTER_CLK_PAD 0 #endif -#if (GSPI_MASTER_CLK_LOC == 2) +#if (GSPI_MASTER_SCK_LOC == 2) #define RTE_GSPI_MASTER_CLK_PAD 10 #endif -#if (GSPI_MASTER_CLK_LOC == 3) +#if (GSPI_MASTER_SCK_LOC == 3) #define RTE_GSPI_MASTER_CLK_PAD 16 #endif -// Pintool data +//Pintool data #endif // GSPI_MASTER_CS0 @@ -2651,54 +2650,54 @@ // CS0 of GSPI0 // #ifndef GSPI_MASTER_CS0_LOC -#define RTE_GSPI_MASTER_CS0_PORT_ID 2 +#define RTE_GSPI_MASTER_CS0_PORT_ID 1 #if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) -#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0 1 #define RTE_GSPI_MASTER_CS0_PORT 0 -#define RTE_GSPI_MASTER_CS0_PIN 9 -#define RTE_GSPI_MASTER_CS0_MUX 4 -#define RTE_GSPI_MASTER_CS0_PAD 4 +#define RTE_GSPI_MASTER_CS0_PIN 9 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 4 #elif (RTE_GSPI_MASTER_CS0_PORT_ID == 1) -#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0 1 #define RTE_GSPI_MASTER_CS0_PORT 0 -#define RTE_GSPI_MASTER_CS0_PIN 28 -#define RTE_GSPI_MASTER_CS0_MUX 4 -#define RTE_GSPI_MASTER_CS0_PAD 0 // NO PAD +#define RTE_GSPI_MASTER_CS0_PIN 28 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 0 //NO PAD #elif (RTE_GSPI_MASTER_CS0_PORT_ID == 2) -#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0 1 #define RTE_GSPI_MASTER_CS0_PORT 0 -#define RTE_GSPI_MASTER_CS0_PIN 49 -#define RTE_GSPI_MASTER_CS0_MUX 4 -#define RTE_GSPI_MASTER_CS0_PAD 13 +#define RTE_GSPI_MASTER_CS0_PIN 49 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 13 #elif (RTE_GSPI_MASTER_CS0_PORT_ID == 3) -#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0 1 #define RTE_GSPI_MASTER_CS0_PORT 0 -#define RTE_GSPI_MASTER_CS0_PIN 53 -#define RTE_GSPI_MASTER_CS0_MUX 4 -#define RTE_GSPI_MASTER_CS0_PAD 17 +#define RTE_GSPI_MASTER_CS0_PIN 53 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 17 #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_GSPI_MASTER_CS0 1 -#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0_PORT -#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0_PIN -#define RTE_GSPI_MASTER_CS0_MUX 4 -#if (GSPI_MASTER_CS0_LOC == 0) +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) #define RTE_GSPI_MASTER_CS0_PAD 4 #endif -#if (GSPI_MASTER_CS0_LOC == 1) +#if (GSPI_MASTER_CS0_LOC == 5) #define RTE_GSPI_MASTER_CS0_PAD 0 #endif -#if (GSPI_MASTER_CS0_LOC == 2) +#if (GSPI_MASTER_CS0_LOC == 6) #define RTE_GSPI_MASTER_CS0_PAD 13 #endif -#if (GSPI_MASTER_CS0_LOC == 3) +#if (GSPI_MASTER_CS0_LOC == 7) #define RTE_GSPI_MASTER_CS0_PAD 17 #endif -// Pintool data +//Pintool data #endif // GSPI_MASTER_CS1 @@ -2706,53 +2705,53 @@ // CS1 of GSPI0 // #ifndef GSPI_MASTER_CS1_LOC -#define RTE_GSPI_MASTER_CS1_PORT_ID 2 +#define RTE_GSPI_MASTER_CS1_PORT_ID 1 #if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) -#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1 1 #define RTE_GSPI_MASTER_CS1_PORT 0 -#define RTE_GSPI_MASTER_CS1_PIN 10 -#define RTE_GSPI_MASTER_CS1_MUX 4 -#define RTE_GSPI_MASTER_CS1_PAD 5 +#define RTE_GSPI_MASTER_CS1_PIN 10 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 5 #elif (RTE_GSPI_MASTER_CS1_PORT_ID == 1) -#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1 1 #define RTE_GSPI_MASTER_CS1_PORT 0 -#define RTE_GSPI_MASTER_CS1_PIN 29 -#define RTE_GSPI_MASTER_CS1_MUX 4 -#define RTE_GSPI_MASTER_CS1_PAD 0 // NO PAD +#define RTE_GSPI_MASTER_CS1_PIN 29 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 0 //NO PAD #elif (RTE_GSPI_MASTER_CS1_PORT_ID == 2) -#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1 1 #define RTE_GSPI_MASTER_CS1_PORT 0 -#define RTE_GSPI_MASTER_CS1_PIN 50 -#define RTE_GSPI_MASTER_CS1_MUX 4 -#define RTE_GSPI_MASTER_CS1_PAD 14 +#define RTE_GSPI_MASTER_CS1_PIN 50 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 14 #elif (RTE_GSPI_MASTER_CS1_PORT_ID == 3) -#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1 1 #define RTE_GSPI_MASTER_CS1_PORT 0 -#define RTE_GSPI_MASTER_CS1_PIN 54 -#define RTE_GSPI_MASTER_CS1_MUX 4 -#define RTE_GSPI_MASTER_CS1_PAD 18 +#define RTE_GSPI_MASTER_CS1_PIN 54 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 18 #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_GSPI_MASTER_CS1 1 -#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1_PORT -#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1_PIN -#define RTE_GSPI_MASTER_CS1_MUX 4 -#if (GSPI_MASTER_CS1_LOC == 0) +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) #define RTE_GSPI_MASTER_CS1_PAD 5 #endif -#if (GSPI_MASTER_CS1_LOC == 1) +#if (GSPI_MASTER_CS1_LOC == 9) #define RTE_GSPI_MASTER_CS1_PAD 0 #endif -#if (GSPI_MASTER_CS1_LOC == 2) +#if (GSPI_MASTER_CS1_LOC == 10) #define RTE_GSPI_MASTER_CS1_PAD 14 #endif -#if (GSPI_MASTER_CS1_LOC == 3) +#if (GSPI_MASTER_CS1_LOC == 11) #define RTE_GSPI_MASTER_CS1_PAD 18 #endif -// Pintool data +//Pintool data #endif // GSPI_MASTER_CS2 @@ -2762,107 +2761,111 @@ #ifndef GSPI_MASTER_CS2_LOC #define RTE_GSPI_MASTER_CS2_PORT_ID 1 #if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) -#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2 1 #define RTE_GSPI_MASTER_CS2_PORT 0 -#define RTE_GSPI_MASTER_CS2_PIN 15 -#define RTE_GSPI_MASTER_CS2_MUX 4 -#define RTE_GSPI_MASTER_CS2_PAD 8 +#define RTE_GSPI_MASTER_CS2_PIN 15 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 8 #elif (RTE_GSPI_MASTER_CS2_PORT_ID == 1) -#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2 1 #define RTE_GSPI_MASTER_CS2_PORT 0 -#define RTE_GSPI_MASTER_CS2_PIN 30 -#define RTE_GSPI_MASTER_CS2_MUX 4 -#define RTE_GSPI_MASTER_CS2_PAD 0 // NO PAD +#define RTE_GSPI_MASTER_CS2_PIN 30 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 0 //NO PAD #elif (RTE_GSPI_MASTER_CS2_PORT_ID == 2) -#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2 1 #define RTE_GSPI_MASTER_CS2_PORT 0 -#define RTE_GSPI_MASTER_CS2_PIN 51 -#define RTE_GSPI_MASTER_CS2_MUX 4 -#define RTE_GSPI_MASTER_CS2_PAD 15 +#define RTE_GSPI_MASTER_CS2_PIN 51 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 15 #elif (RTE_GSPI_MASTER_CS2_PORT_ID == 3) -#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2 1 #define RTE_GSPI_MASTER_CS2_PORT 0 -#define RTE_GSPI_MASTER_CS2_PIN 55 -#define RTE_GSPI_MASTER_CS2_MUX 4 -#define RTE_GSPI_MASTER_CS2_PAD 19 +#define RTE_GSPI_MASTER_CS2_PIN 55 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 19 #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_GSPI_MASTER_CS2 1 -#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2_PORT -#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2_PIN -#define RTE_GSPI_MASTER_CS2_MUX 4 -#if (GSPI_MASTER_CS2_LOC == 0) +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) #define RTE_GSPI_MASTER_CS2_PAD 8 #endif -#if (GSPI_MASTER_CS2_LOC == 1) +#if (GSPI_MASTER_CS2_LOC == 13) #define RTE_GSPI_MASTER_CS2_PAD 0 #endif -#if (GSPI_MASTER_CS2_LOC == 2) +#if (GSPI_MASTER_CS2_LOC == 14) #define RTE_GSPI_MASTER_CS2_PAD 15 #endif -#if (GSPI_MASTER_CS2_LOC == 3) +#if (GSPI_MASTER_CS2_LOC == 15) #define RTE_GSPI_MASTER_CS2_PAD 19 #endif -// Pintool data +//Pintool data #endif // GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 // MOSI of GSPI0 #ifndef GSPI_MASTER_MOSI_LOC #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 -#if ((RTE_GSPI_MASTER_MOSI_PORT_ID == 4)) -#error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN pin Configuration!" -#endif #if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) #define RTE_GSPI_MASTER_MOSI_PORT 0 -#define RTE_GSPI_MASTER_MOSI_PIN 12 -#define RTE_GSPI_MASTER_MOSI_MUX 4 -#define RTE_GSPI_MASTER_MOSI_PAD 7 +#define RTE_GSPI_MASTER_MOSI_PIN 12 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 7 #elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 1) #define RTE_GSPI_MASTER_MOSI_PORT 0 -#define RTE_GSPI_MASTER_MOSI_PIN 27 -#define RTE_GSPI_MASTER_MOSI_MUX 4 -#define RTE_GSPI_MASTER_MOSI_PAD 0 // NO PAD +#define RTE_GSPI_MASTER_MOSI_PIN 27 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 //NO PAD #elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 2) #define RTE_GSPI_MASTER_MOSI_PORT 0 -#define RTE_GSPI_MASTER_MOSI_PIN 48 -#define RTE_GSPI_MASTER_MOSI_MUX 4 -#define RTE_GSPI_MASTER_MOSI_PAD 12 +#define RTE_GSPI_MASTER_MOSI_PIN 48 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 #elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 3) #define RTE_GSPI_MASTER_MOSI_PORT 0 -#define RTE_GSPI_MASTER_MOSI_PIN 57 -#define RTE_GSPI_MASTER_MOSI_MUX 4 -#define RTE_GSPI_MASTER_MOSI_PAD 21 +#define RTE_GSPI_MASTER_MOSI_PIN 57 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 #elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 4) #define RTE_GSPI_MASTER_MOSI_PORT 0 -#define RTE_GSPI_MASTER_MOSI_PIN 6 -#define RTE_GSPI_MASTER_MOSI_MUX 12 -#define RTE_GSPI_MASTER_MOSI_PAD 1 +#define RTE_GSPI_MASTER_MOSI_PIN 6 +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI_PORT -#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI_PIN +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) #define RTE_GSPI_MASTER_MOSI_MUX 4 -#if (GSPI_MASTER_MOSI_LOC == 0) #define RTE_GSPI_MASTER_MOSI_PAD 1 #endif -#if (GSPI_MASTER_MOSI_LOC == 1) +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 0 #endif -#if (GSPI_MASTER_MOSI_LOC == 2) +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 12 #endif -#if (GSPI_MASTER_MOSI_LOC == 3) +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 21 #endif -// Pintool data +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data #endif // GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 @@ -2872,45 +2875,45 @@ #if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) #define RTE_GSPI_MASTER_MISO_PORT 0 -#define RTE_GSPI_MASTER_MISO_PIN 11 -#define RTE_GSPI_MASTER_MISO_MUX 4 -#define RTE_GSPI_MASTER_MISO_PAD 6 +#define RTE_GSPI_MASTER_MISO_PIN 11 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 6 #elif (RTE_GSPI_MASTER_MISO_PORT_ID == 1) #define RTE_GSPI_MASTER_MISO_PORT 0 -#define RTE_GSPI_MASTER_MISO_PIN 26 -#define RTE_GSPI_MASTER_MISO_MUX 4 -#define RTE_GSPI_MASTER_MISO_PAD 0 // NO PAD +#define RTE_GSPI_MASTER_MISO_PIN 26 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 0 //NO PAD #elif (RTE_GSPI_MASTER_MISO_PORT_ID == 2) #define RTE_GSPI_MASTER_MISO_PORT 0 -#define RTE_GSPI_MASTER_MISO_PIN 47 -#define RTE_GSPI_MASTER_MISO_MUX 4 -#define RTE_GSPI_MASTER_MISO_PAD 11 +#define RTE_GSPI_MASTER_MISO_PIN 47 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 11 #elif (RTE_GSPI_MASTER_MISO_PORT_ID == 3) #define RTE_GSPI_MASTER_MISO_PORT 0 -#define RTE_GSPI_MASTER_MISO_PIN 56 -#define RTE_GSPI_MASTER_MISO_MUX 4 -#define RTE_GSPI_MASTER_MISO_PAD 20 +#define RTE_GSPI_MASTER_MISO_PIN 56 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 20 #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO_PORT -#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO_PIN -#define RTE_GSPI_MASTER_MISO_MUX 4 -#if (GSPI_MASTER_MISO_LOC == 0) +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) #define RTE_GSPI_MASTER_MISO_PAD 6 #endif -#if (GSPI_MASTER_MISO_LOC == 1) +#if (GSPI_MASTER_MISO_LOC == 22) #define RTE_GSPI_MASTER_MISO_PAD 0 #endif -#if (GSPI_MASTER_MISO_LOC == 2) +#if (GSPI_MASTER_MISO_LOC == 23) #define RTE_GSPI_MASTER_MISO_PAD 11 #endif -#if (GSPI_MASTER_MISO_LOC == 3) +#if (GSPI_MASTER_MISO_LOC == 24) #define RTE_GSPI_MASTER_MISO_PAD 20 #endif -// Pintool data +//Pintool data #endif #if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) @@ -2920,9 +2923,7 @@ #define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 -#define RTE_GSPI_CLOCK_SOURCE GSPI_SOC_PLL_CLK - -#define RTE_FIFO_AFULL_THRLD 3 +#define RTE_FIFO_AFULL_THRLD 3 #define RTE_FIFO_AEMPTY_THRLD 7 #define TX_DMA_ARB_SIZE ARBSIZE_4 @@ -2934,9 +2935,7 @@ #define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 -#define RTE_GSPI_CLOCK_SOURCE GSPI_SOC_PLL_CLK - -#define RTE_FIFO_AFULL_THRLD 0 +#define RTE_FIFO_AFULL_THRLD 0 #define RTE_FIFO_AEMPTY_THRLD 0 #define TX_DMA_ARB_SIZE ARBSIZE_1 @@ -2946,63 +2945,80 @@ // (Generic SPI master)[Driver_GSPI_MASTER] // (State Configurable Timer) Interface -#define SCT_CLOCK_SOURCE M4_SOCCLKFOROTHERCLKSCT +#define SCT_CLOCK_SOURCE M4_SOCCLKFOROTHERCLKSCT #define SCT_CLOCK_DIV_FACT 1 -// SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +//SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 #ifndef SCT_IN0_LOC #define RTE_SCT_IN_0_PORT_ID 0 #if (RTE_SCT_IN_0_PORT_ID == 0) #define RTE_SCT_IN_0_PORT 0 -#define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) #define RTE_SCT_IN_0_PIN SCT_IN0_PIN -// Pintool data -#endif #define RTE_SCT_IN_0_MUX 9 -#define RTE_SCT_IN_0_PAD 0 // no pad +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif -// SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 +//SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 #ifndef SCT_IN1_LOC #define RTE_SCT_IN_1_PORT_ID 1 #if (RTE_SCT_IN_1_PORT_ID == 0) #define RTE_SCT_IN_1_PORT 0 -#define RTE_SCT_IN_1_PIN 26 -#define RTE_SCT_IN_1_MUX 9 -#define RTE_SCT_IN_1_PAD 0 // no pad +#define RTE_SCT_IN_1_PIN 26 +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad #elif (RTE_SCT_IN_1_PORT_ID == 1) #define RTE_SCT_IN_1_PORT 0 -#define RTE_SCT_IN_1_PIN 65 -#define RTE_SCT_IN_1_MUX 7 -#define RTE_SCT_IN_1_PAD 23 +#define RTE_SCT_IN_1_PIN 65 +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 #else #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_SCT_IN_1_PORT SCT_IN1_PORT -#if (SCT_IN1_LOC == 0) +#if (SCT_IN1_LOC == 3) #define RTE_SCT_IN_1_PIN SCT_IN1_PIN #define RTE_SCT_IN_1_MUX 9 -#define RTE_SCT_IN_1_PAD 0 // no pad +#define RTE_SCT_IN_1_PAD 0 //no pad #endif -#if (SCT_IN1_LOC == 1) +#if (SCT_IN1_LOC == 4) #define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_1_MUX 7 #define RTE_SCT_IN_1_PAD 23 #endif -// Pintool data +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data #endif -// SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 +//SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 #ifndef SCT_IN2_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_2_PORT_ID 0 @@ -3012,44 +3028,39 @@ #if (RTE_SCT_IN_2_PORT_ID == 0) #define RTE_SCT_IN_2_PORT 0 -#define RTE_SCT_IN_2_PIN 27 -#define RTE_SCT_IN_2_MUX 9 -#define RTE_SCT_IN_2_PAD 0 // no pad +#define RTE_SCT_IN_2_PIN 27 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad #elif (RTE_SCT_IN_2_PORT_ID == 1) #define RTE_SCT_IN_2_PORT 0 -#define RTE_SCT_IN_2_PIN 66 -#define RTE_SCT_IN_2_MUX 7 -#define RTE_SCT_IN_2_PAD 24 +#define RTE_SCT_IN_2_PIN 66 +#define RTE_SCT_IN_2_MUX 7 +#define RTE_SCT_IN_2_PAD 24 #elif (RTE_SCT_IN_2_PORT_ID == 2) #define RTE_SCT_IN_2_PORT 0 -#define RTE_SCT_IN_2_PIN 70 -#define RTE_SCT_IN_2_MUX 9 -#define RTE_SCT_IN_2_PAD 28 +#define RTE_SCT_IN_2_PIN 70 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_SCT_IN_2_PORT SCT_IN2_PORT -#if (SCT_IN2_LOC == 0) +#if (SCT_IN2_LOC == 6) #define RTE_SCT_IN_2_PIN SCT_IN2_PIN #define RTE_SCT_IN_2_MUX 9 -#define RTE_SCT_IN_2_PAD 0 // no pad +#define RTE_SCT_IN_2_PAD 0 //no pad #endif -#if (SCT_IN2_LOC == 1) -#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) -#define RTE_SCT_IN_2_MUX 7 -#define RTE_SCT_IN_2_PAD 24 -#endif -#if (SCT_IN2_LOC == 2) +#if (SCT_IN2_LOC == 7) #define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_2_MUX 9 #define RTE_SCT_IN_2_PAD 28 #endif -// Pintool data +//Pintool data #endif -// SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 +//SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 #ifndef SCT_IN3_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_3_PORT_ID 0 @@ -3059,41 +3070,36 @@ #if (RTE_SCT_IN_3_PORT_ID == 0) #define RTE_SCT_IN_3_PORT 0 -#define RTE_SCT_IN_3_PIN 28 -#define RTE_SCT_IN_3_MUX 9 -#define RTE_SCT_IN_3_PAD 0 // no pad +#define RTE_SCT_IN_3_PIN 28 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad #elif (RTE_SCT_IN_3_PORT_ID == 1) #define RTE_SCT_IN_3_PORT 0 -#define RTE_SCT_IN_3_PIN 67 -#define RTE_SCT_IN_3_MUX 7 -#define RTE_SCT_IN_3_PAD 25 +#define RTE_SCT_IN_3_PIN 67 +#define RTE_SCT_IN_3_MUX 7 +#define RTE_SCT_IN_3_PAD 25 #elif (RTE_SCT_IN_3_PORT_ID == 2) #define RTE_SCT_IN_3_PORT 0 -#define RTE_SCT_IN_3_PIN 71 -#define RTE_SCT_IN_3_MUX 9 -#define RTE_SCT_IN_3_PAD 29 +#define RTE_SCT_IN_3_PIN 71 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_SCT_IN_3_PORT SCT_IN3_PORT -#if (SCT_IN3_LOC == 0) +#if (SCT_IN3_LOC == 8) #define RTE_SCT_IN_3_PIN SCT_IN3_PIN #define RTE_SCT_IN_3_MUX 9 -#define RTE_SCT_IN_3_PAD 0 // no pad -#endif -#if (SCT_IN3_LOC == 1) -#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) -#define RTE_SCT_IN_3_MUX 7 -#define RTE_SCT_IN_3_PAD 25 +#define RTE_SCT_IN_3_PAD 0 //no pad #endif -#if (SCT_IN3_LOC == 2) +#if (SCT_IN3_LOC == 9) #define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_3_MUX 9 #define RTE_SCT_IN_3_PAD 29 #endif -// Pintool data +//Pintool data #endif // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 @@ -3101,229 +3107,143 @@ #define RTE_SCT_OUT_0_PORT_ID 0 #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 -#define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) #define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN -// Pintool data -#endif #define RTE_SCT_OUT_0_MUX 9 -#define RTE_SCT_OUT_0_PAD 0 // no pad +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 #ifndef SCT_OUT1_LOC #define RTE_SCT_OUT_1_PORT_ID 0 #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 -#define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) #define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN -// Pintool data -#endif #define RTE_SCT_OUT_1_MUX 9 -#define RTE_SCT_OUT_1_PAD 0 // no pad - -/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 -#ifndef SCT_OUT2_LOC -#define RTE_SCT_OUT_2_PORT_ID 0 -#if ((RTE_SCT_OUT_2_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 #endif - -#if (RTE_SCT_OUT_2_PORT_ID == 0) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 70 -#elif (RTE_SCT_OUT_2_PORT_ID == 1) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 8 -#define RTE_SCT_OUT_2_MUX 12 -#define RTE_SCT_OUT_2_PAD 3 -#else -#error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" +//Pintool data #endif -#else -// Pintool data -#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT -#define RTE_SCT_OUT_2_PIN (SCT_OUT2_PIN + GPIO_MAX_PIN) -// Pintool data -#endif -#define RTE_SCT_OUT_2_MUX 7 -#define RTE_SCT_OUT_2_PAD 28 -/**/ -// SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 -#ifndef SCT_OUT3_LOC -#define RTE_SCT_OUT_3_PORT_ID 0 -#if ((RTE_SCT_OUT_3_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" -#endif +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN +#define RTE_SCT_OUT_2_MUX 7 +#define RTE_SCT_OUT_2_PAD 28 +//Pintool data -#if (RTE_SCT_OUT_3_PORT_ID == 0) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 71 -#elif (RTE_SCT_OUT_3_PORT_ID == 1) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 9 -#define RTE_SCT_OUT_3_MUX 12 -#define RTE_SCT_OUT_3_PAD 4 -#else -#error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" -#endif -#else -// Pintool data +//Pintool data #define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT -#define RTE_SCT_OUT_3_PIN (SCT_OUT3_PIN + GPIO_MAX_PIN) -// Pintool data -#endif -#define RTE_SCT_OUT_3_MUX 7 -#define RTE_SCT_OUT_3_PAD 29 - -// SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 -#ifndef SCT_OUT4_LOC -#define RTE_SCT_OUT_4_PORT_ID 0 -#if ((RTE_SCT_OUT_4_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" -#endif +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN +#define RTE_SCT_OUT_3_MUX 7 +#define RTE_SCT_OUT_3_PAD 29 +//Pintool data -#if (RTE_SCT_OUT_4_PORT_ID == 0) -/**/ -#define RTE_SCT_OUT_4_PORT 0 -#define RTE_SCT_OUT_4_PIN 72 -#else -#error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" -#endif -#else -// Pintool data +//Pintool data #define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT -#define RTE_SCT_OUT_4_PIN (SCT_OUT4_PIN + GPIO_MAX_PIN) -// Pintool data -#endif -#define RTE_SCT_OUT_4_MUX 7 -#define RTE_SCT_OUT_4_PAD 30 - -// SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 -#ifndef SCT_OUT5_LOC -#define RTE_SCT_OUT_5_PORT_ID 0 -#if ((RTE_SCT_OUT_5_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" -#endif +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN +#define RTE_SCT_OUT_4_MUX 7 +#define RTE_SCT_OUT_4_PAD 30 +//Pintool data -#if (RTE_SCT_OUT_5_PORT_ID == 0) -#define RTE_SCT_OUT_5_PORT 2 -#define RTE_SCT_OUT_5_PIN 73 -#else -#error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" -#endif -#else -// Pintool data +//Pintool data #define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT -#define RTE_SCT_OUT_5_PIN (SCT_OUT5_PIN + GPIO_MAX_PIN) -// Pintool data -#endif -#define RTE_SCT_OUT_5_MUX 7 -#define RTE_SCT_OUT_5_PAD 31 +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN +#define RTE_SCT_OUT_5_MUX 7 +#define RTE_SCT_OUT_5_PAD 31 +//Pintool data -// SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 -#ifndef SCT_OUT6_LOC -#define RTE_SCT_OUT_6_PORT_ID 0 -#if ((RTE_SCT_OUT_6_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_6_PORT_ID == 0) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 74 -#define RTE_SCT_OUT_6_MUX 7 -#define RTE_SCT_OUT_6_PAD 32 -#elif (RTE_SCT_OUT_6_PORT_ID == 1) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 70 -#define RTE_SCT_OUT_6_MUX 13 -#define RTE_SCT_OUT_6_PAD 28 -#else -#error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" -#endif -#else -// Pintool data +//Pintool data #define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT -#define RTE_SCT_OUT_6_PIN (SCT_OUT6_PIN + GPIO_MAX_PIN) -// Pintool data -#endif -#define RTE_SCT_OUT_6_MUX 7 -#define RTE_SCT_OUT_6_PAD 32 +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN +#define RTE_SCT_OUT_6_MUX 7 +#define RTE_SCT_OUT_6_PAD 32 +//Pintool data -// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 -#ifndef SCT_OUT7_LOC -#define RTE_SCT_OUT_7_PORT_ID 0 - -#if (RTE_SCT_OUT_7_PORT_ID == 0) -#define RTE_SCT_OUT_7_PORT 0 -#define RTE_SCT_OUT_7_PIN 75 -#else -#error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" -#endif -#else -// Pintool data +//Pintool data #define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT -#define RTE_SCT_OUT_7_PIN (SCT_OUT7_PIN + GPIO_MAX_PIN) -// Pintool data -#endif -#define RTE_SCT_OUT_7_MUX 7 -#define RTE_SCT_OUT_7_PAD 33 +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN +#define RTE_SCT_OUT_7_MUX 7 +#define RTE_SCT_OUT_7_PAD 33 +//Pintool data // SIO // //<> Serial Input Output -// SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 +//SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 #ifndef SIO_0_LOC #define RTE_SIO_0_PORT_ID 0 #if (RTE_SIO_0_PORT_ID == 0) #define RTE_SIO_0_PORT 0 -#define RTE_SIO_0_PIN 6 -#define RTE_SIO_0_MUX 1 -#define RTE_SIO_0_PAD 1 +#define RTE_SIO_0_PIN 6 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 1 #elif (RTE_SIO_0_PORT_ID == 1) #define RTE_SIO_0_PORT 0 -#define RTE_SIO_0_PIN 25 -#define RTE_SIO_0_MUX 1 -#define RTE_SIO_0_PAD 0 // no pad +#define RTE_SIO_0_PIN 25 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 0 //no pad #elif (RTE_SIO_0_PORT_ID == 2) #define RTE_SIO_0_PORT 0 -#define RTE_SIO_0_PIN 72 -#define RTE_SIO_0_MUX 1 -#define RTE_SIO_0_PAD 30 +#define RTE_SIO_0_PIN 72 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 30 #else #error "Invalid RTE_SIO_0_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_SIO_0_PORT SIO_0_PORT -#define RTE_SIO_0_MUX 1 +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 #if (SIO_0_LOC == 0) -#define RTE_SIO_0_PIN SIO_0_PIN +#define RTE_SIO_0_PIN SIO_SIO0_PIN #define RTE_SIO_0_PAD 1 #endif #if (SIO_0_LOC == 1) -#define RTE_SIO_0_PIN SIO_0_PIN +#define RTE_SIO_0_PIN SIO_SIO0_PIN #define RTE_SIO_0_PAD 0 #endif #if (SIO_0_LOC == 2) -#define RTE_SIO_0_PIN (SIO_0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) #define RTE_SIO_0_PAD 30 #endif -// Pintool data +//Pintool data #endif -// SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 +//SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 #ifndef SIO_1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_1_PORT_ID 1 @@ -3333,48 +3253,48 @@ #if (RTE_SIO_1_PORT_ID == 0) #define RTE_SIO_1_PORT 0 -#define RTE_SIO_1_PIN 7 -#define RTE_SIO_1_MUX 1 -#define RTE_SIO_1_PAD 2 +#define RTE_SIO_1_PIN 7 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 2 #elif (RTE_SIO_1_PORT_ID == 1) #define RTE_SIO_1_PORT 0 -#define RTE_SIO_1_PIN 26 -#define RTE_SIO_1_MUX 1 -#define RTE_SIO_1_PAD 0 // no pad +#define RTE_SIO_1_PIN 26 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 0 // no pad #elif (RTE_SIO_1_PORT_ID == 2) #define RTE_SIO_1_PORT 0 -#define RTE_SIO_1_PIN 65 -#define RTE_SIO_1_MUX 1 -#define RTE_SIO_1_PAD 23 +#define RTE_SIO_1_PIN 65 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 23 #elif (RTE_SIO_1_PORT_ID == 3) #define RTE_SIO_1_PORT 0 -#define RTE_SIO_1_PIN 73 -#define RTE_SIO_1_MUX 1 -#define RTE_SIO_1_PAD 31 +#define RTE_SIO_1_PIN 73 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 31 #else #error "Invalid RTE_SIO_1_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_SIO_1_PORT SIO_1_PORT -#define RTE_SIO_1_MUX 1 -#if (SIO_1_LOC == 0) -#define RTE_SIO_1_PIN SIO_1_PIN +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN #define RTE_SIO_1_PAD 2 #endif -#if (SIO_1_LOC == 1) -#define RTE_SIO_1_PIN SIO_1_PIN +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN #define RTE_SIO_1_PAD 0 #endif -#if (SIO_1_LOC == 2) -#define RTE_SIO_1_PIN (SIO_1_PIN + GPIO_MAX_PIN) +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) #define RTE_SIO_1_PAD 23 #endif -#if (SIO_1_LOC == 3) -#define RTE_SIO_1_PIN (SIO_1_PIN + GPIO_MAX_PIN) +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) #define RTE_SIO_1_PAD 31 #endif -// Pintool data +//Pintool data #endif // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 @@ -3383,101 +3303,93 @@ #if (RTE_SIO_2_PORT_ID == 0) #define RTE_SIO_2_PORT 0 -#define RTE_SIO_2_PIN 8 -#define RTE_SIO_2_MUX 1 -#define RTE_SIO_2_PAD 3 +#define RTE_SIO_2_PIN 8 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 3 #elif (RTE_SIO_2_PORT_ID == 1) #define RTE_SIO_2_PORT 0 -#define RTE_SIO_2_PIN 27 -#define RTE_SIO_2_MUX 1 -#define RTE_SIO_2_PAD 0 // no pad +#define RTE_SIO_2_PIN 27 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 0 //no pad #elif (RTE_SIO_2_PORT_ID == 2) #define RTE_SIO_2_PORT 0 -#define RTE_SIO_2_PIN 66 -#define RTE_SIO_2_MUX 1 -#define RTE_SIO_2_PAD 24 +#define RTE_SIO_2_PIN 66 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 24 #elif (RTE_SIO_2_PORT_ID == 3) #define RTE_SIO_2_PORT 0 -#define RTE_SIO_2_PIN 74 -#define RTE_SIO_2_MUX 1 -#define RTE_SIO_2_PAD 32 +#define RTE_SIO_2_PIN 74 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 32 #else #error "Invalid RTE_SIO_2_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_SIO_2_PORT SIO_2_PORT -#define RTE_SIO_2_MUX 1 -#if (SIO_2_LOC == 0) -#define RTE_SIO_2_PIN SIO_2_PIN +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN #define RTE_SIO_2_PAD 3 #endif -#if (SIO_2_LOC == 1) -#define RTE_SIO_2_PIN SIO_2_PIN +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN #define RTE_SIO_2_PAD 0 #endif -#if (SIO_2_LOC == 2) -#define RTE_SIO_2_PIN (SIO_2_PIN + GPIO_MAX_PIN) -#define RTE_SIO_2_PAD 24 -#endif -#if (SIO_2_LOC == 3) -#define RTE_SIO_2_PIN (SIO_2_PIN + GPIO_MAX_PIN) +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) #define RTE_SIO_2_PAD 32 #endif -// Pintool data +//Pintool data #endif -// SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 +//SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 #ifndef SIO_3_LOC #define RTE_SIO_3_PORT_ID 1 #if (RTE_SIO_3_PORT_ID == 0) #define RTE_SIO_3_PORT 0 -#define RTE_SIO_3_PIN 9 -#define RTE_SIO_3_MUX 1 -#define RTE_SIO_3_PAD 4 +#define RTE_SIO_3_PIN 9 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 4 #elif (RTE_SIO_3_PORT_ID == 1) #define RTE_SIO_3_PORT 0 -#define RTE_SIO_3_PIN 28 -#define RTE_SIO_3_MUX 1 -#define RTE_SIO_3_PAD 0 // no pad +#define RTE_SIO_3_PIN 28 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 0 //no pad #elif (RTE_SIO_3_PORT_ID == 2) #define RTE_SIO_3_PORT 0 -#define RTE_SIO_3_PIN 67 -#define RTE_SIO_3_MUX 1 -#define RTE_SIO_3_PAD 25 +#define RTE_SIO_3_PIN 67 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 25 #elif (RTE_SIO_3_PORT_ID == 3) #define RTE_SIO_3_PORT 0 -#define RTE_SIO_3_PIN 75 -#define RTE_SIO_3_MUX 1 -#define RTE_SIO_3_PAD 33 +#define RTE_SIO_3_PIN 75 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 33 #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_SIO_3_PORT SIO_3_PORT -#define RTE_SIO_3_MUX 1 -#if (SIO_3_LOC == 0) -#define RTE_SIO_3_PIN SIO_3_PIN +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN #define RTE_SIO_3_PAD 4 #endif -#if (SIO_3_LOC == 1) -#define RTE_SIO_3_PIN SIO_3_PIN +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN #define RTE_SIO_3_PAD 0 #endif -#if (SIO_3_LOC == 2) -#define RTE_SIO_3_PIN (SIO_3_PIN + GPIO_MAX_PIN) -#define RTE_SIO_3_PAD 25 -#endif -#if (SIO_3_LOC == 3) -#define RTE_SIO_3_PIN (SIO_3_PIN + GPIO_MAX_PIN) +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) #define RTE_SIO_3_PAD 33 #endif -// Pintool data +//Pintool data #endif -// SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +//SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 #ifndef SIO_4_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_4_PORT_ID 1 @@ -3486,29 +3398,34 @@ #endif #if (RTE_SIO_4_PORT_ID == 0) #define RTE_SIO_4_PORT 0 -#define RTE_SIO_4_PIN 10 -#define RTE_SIO_4_MUX 1 -#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN 10 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 5 #elif (RTE_SIO_4_PORT_ID == 1) #define RTE_SIO_4_PORT 0 -#define RTE_SIO_4_PIN 29 -#define RTE_SIO_4_MUX 1 -#define RTE_SIO_4_PAD 0 // NO PAD +#define RTE_SIO_4_PIN 29 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 0 //NO PAD #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_SIO_4_PORT SIO_4_PORT -#define RTE_SIO_4_PIN SIO_4_PIN -#define RTE_SIO_4_MUX 1 -#if (SIO_4_LOC == 0) +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) #define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN #endif -#if (SIO_4_LOC == 1) +#if (SIO_4_LOC == 15) #define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) #endif -// Pintool data +//Pintool data #endif // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 @@ -3516,38 +3433,43 @@ #define RTE_SIO_5_PORT_ID 0 #if (RTE_SIO_5_PORT_ID == 0) #define RTE_SIO_5_PORT 0 -#define RTE_SIO_5_PIN 11 -#define RTE_SIO_5_MUX 1 -#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN 11 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 6 #elif (RTE_SIO_5_PORT_ID == 1) #define RTE_SIO_5_PORT 0 -#define RTE_SIO_5_PIN 30 -#define RTE_SIO_5_MUX 1 -#define RTE_SIO_5_PAD 0 // no pad +#define RTE_SIO_5_PIN 30 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 0 //no pad #else #error "Invalid RTE_SIO_5_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_SIO_5_PORT SIO_5_PORT -#define RTE_SIO_5_PIN SIO_5_PIN -#define RTE_SIO_5_MUX 1 -#if (SIO_5_LOC == 0) +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) #define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN #endif -#if (SIO_5_LOC == 1) +#if (SIO_5_LOC == 19) #define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) #endif -// Pintool data +//Pintool data #endif // SIO_6 GPIO_70 #ifndef SIO_6_LOC #define RTE_SIO_6_PORT 0 -#define RTE_SIO_6_PIN 70 +#define RTE_SIO_6_PIN 70 #else -#define RTE_SIO_6_PORT SIO_6_PORT -#define RTE_SIO_6_PIN (SIO_6_PIN + GPIO_MAX_PIN) +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) #endif #define RTE_SIO_6_MUX 1 #define RTE_SIO_6_PAD 28 @@ -3562,35 +3484,35 @@ #if (RTE_SIO_7_PORT_ID == 0) #define RTE_SIO_7_PORT 0 -#define RTE_SIO_7_PIN 15 -#define RTE_SIO_7_MUX 1 -#define RTE_SIO_7_PAD 8 +#define RTE_SIO_7_PIN 15 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 8 #elif (RTE_SIO_7_PORT_ID == 1) #define RTE_SIO_7_PORT 0 -#define RTE_SIO_7_PIN 71 -#define RTE_SIO_7_MUX 1 -#define RTE_SIO_7_PAD 29 +#define RTE_SIO_7_PIN 71 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 29 #else #error "Invalid RTE_SIO_7_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_SIO_7_PORT SIO_6_PORT -#define RTE_SIO_7_MUX 1 -#if (SIO_7_LOC == 0) -#define RTE_SIO_7_PIN SIO_7_PIN +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN #define RTE_SIO_7_PAD 8 #endif -#if (SIO_7_LOC == 1) -#define RTE_SIO_7_PIN (SIO_7_PIN + GPIO_MAX_PIN) +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) #define RTE_SIO_7_PAD 29 #endif -// Pintool data +//Pintool data #endif //<> Pulse Width Modulation -// PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 -#ifndef PWM_H1_LOC +//PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -3599,35 +3521,35 @@ #if (RTE_PWM_1H_PORT_ID == 0) #define RTE_PWM_1H_PORT 0 -#define RTE_PWM_1H_PIN 7 -#define RTE_PWM_1H_MUX 10 -#define RTE_PWM_1H_PAD 2 +#define RTE_PWM_1H_PIN 7 +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 #elif (RTE_PWM_1H_PORT_ID == 1) #define RTE_PWM_1H_PORT 0 -#define RTE_PWM_1H_PIN 65 -#define RTE_PWM_1H_MUX 8 -#define RTE_PWM_1H_PAD 22 +#define RTE_PWM_1H_PIN 65 +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 #else #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_1H_PORT PWM_H1_PORT -#if (PWM_H1_LOC == 0) -#define RTE_PWM_1H_PIN PWM_H1_PIN +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN #define RTE_PWM_1H_MUX 10 #define RTE_PWM_1H_PAD 2 #endif -#if (PWM_H1_LOC == 1) -#define RTE_PWM_1H_PIN (PWM_H1_PIN + GPIO_MAX_PIN) +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) #define RTE_PWM_1H_MUX 8 #define RTE_PWM_1H_PAD 22 #endif -// Pintool data +//Pintool data #endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 -#ifndef PWM_L1_LOC +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -3636,21 +3558,29 @@ #if (RTE_PWM_1L_PORT_ID == 0) #define RTE_PWM_1L_PORT 0 -#define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_1L_PORT PWM_L1_PORT -#define RTE_PWM_1L_PIN PWM_L1_PIN -// Pintool data -#endif +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN #define RTE_PWM_1L_MUX 10 #define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif -// PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 -#ifndef PWM_H2_LOC +//PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -3658,35 +3588,35 @@ #if (RTE_PWM_2H_PORT_ID == 0) #define RTE_PWM_2H_PORT 0 -#define RTE_PWM_2H_PIN 9 -#define RTE_PWM_2H_MUX 10 -#define RTE_PWM_2H_PAD 4 +#define RTE_PWM_2H_PIN 9 +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 #elif (RTE_PWM_2H_PORT_ID == 1) #define RTE_PWM_2H_PORT 0 -#define RTE_PWM_2H_PIN 67 -#define RTE_PWM_2H_MUX 8 -#define RTE_PWM_2H_PAD 25 +#define RTE_PWM_2H_PIN 67 +#define RTE_PWM_2H_MUX 8 +#define RTE_PWM_2H_PAD 25 #else #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_2H_PORT PWM_H2_PORT -#if (PWM_H2_LOC == 0) -#define RTE_PWM_2H_PIN PWM_H2_PIN +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN #define RTE_PWM_2H_MUX 10 #define RTE_PWM_2H_PAD 4 #endif -#if (PWM_H2_LOC == 1) -#define RTE_PWM_2H_PIN (PWM_H2_PIN + GPIO_MAX_PIN) -#define RTE_PWM_2H_MUX 8 -#define RTE_PWM_2H_PAD 25 +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 #endif -// Pintool data +//Pintool data #endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 -#ifndef PWM_L2_LOC +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -3694,72 +3624,93 @@ #if (RTE_PWM_2L_PORT_ID == 0) #define RTE_PWM_2L_PORT 0 -#define RTE_PWM_2L_PIN 8 -#define RTE_PWM_2L_MUX 10 -#define RTE_PWM_2L_PAD 3 +#define RTE_PWM_2L_PIN 8 +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 #elif (RTE_PWM_2L_PORT_ID == 1) #define RTE_PWM_2L_PORT 0 -#define RTE_PWM_2L_PIN 66 -#define RTE_PWM_2L_MUX 8 -#define RTE_PWM_2L_PAD 24 +#define RTE_PWM_2L_PIN 66 +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 #else #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_2L_PORT PWM_L2_PORT -#if (PWM_L2_LOC == 0) -#define RTE_PWM_2L_PIN PWM_L2_PIN +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN #define RTE_PWM_2L_MUX 10 #define RTE_PWM_2L_PAD 3 #endif -#if (PWM_L2_LOC == 1) -#define RTE_PWM_2L_PIN (PWM_L2_PIN + GPIO_MAX_PIN) +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) #define RTE_PWM_2L_MUX 8 #define RTE_PWM_2L_PAD 24 #endif -// Pintool data +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data #endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 -#ifndef PWM_H3_LOC +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 -#define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_3H_PORT PWM_H3_PORT -#define RTE_PWM_3H_PIN PWM_H3_PIN -// Pintool data -#endif +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN #define RTE_PWM_3H_MUX 10 #define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 -#ifndef PWM_L3_LOC +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) #define RTE_PWM_3L_PORT 0 -#define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_3L_PORT PWM_L3_PORT -#define RTE_PWM_3L_PIN PWM_L3_PIN -// Pintool data -#endif +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN #define RTE_PWM_3L_MUX 10 #define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 -#ifndef PWM_H4_LOC +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -3768,35 +3719,28 @@ #if (RTE_PWM_4H_PORT_ID == 0) #define RTE_PWM_4H_PORT 0 -#define RTE_PWM_4H_PIN 15 -#define RTE_PWM_4H_MUX 10 -#define RTE_PWM_4H_PAD 8 +#define RTE_PWM_4H_PIN 15 +#define RTE_PWM_4H_MUX 10 +#define RTE_PWM_4H_PAD 8 #elif (RTE_PWM_4H_PORT_ID == 1) #define RTE_PWM_4H_PORT 0 -#define RTE_PWM_4H_PIN 71 -#define RTE_PWM_4H_MUX 8 -#define RTE_PWM_4H_PAD 29 +#define RTE_PWM_4H_PIN 71 +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 #else #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_4H_PORT PWM_H4_PORT -#if (PWM_H4_LOC == 0) -#define RTE_PWM_4H_PIN PWM_H4_PIN -#define RTE_PWM_4H_MUX 10 -#define RTE_PWM_4H_PAD 8 -#endif -#if (PWM_H4_LOC == 1) -#define RTE_PWM_4H_PIN (PWM_H4_PIN + GPIO_MAX_PIN) -#define RTE_PWM_4H_MUX 8 -#define RTE_PWM_4H_PAD 29 -#endif -// Pintool data +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data #endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 -#ifndef PWM_L4_LOC +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -3805,31 +3749,31 @@ #if (RTE_PWM_4L_PORT_ID == 0) #define RTE_PWM_4L_PORT 0 -#define RTE_PWM_4L_PIN 12 -#define RTE_PWM_4L_MUX 10 -#define RTE_PWM_4L_PAD 7 +#define RTE_PWM_4L_PIN 12 +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 #elif (RTE_PWM_4L_PORT_ID == 1) #define RTE_PWM_4L_PORT 0 -#define RTE_PWM_4L_PIN 70 -#define RTE_PWM_4L_MUX 8 -#define RTE_PWM_4L_PAD 28 +#define RTE_PWM_4L_PIN 70 +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 #else #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" #endif #else -// Pintool data -#define RTE_PWM_4L_PORT PWM_L4_PORT -#if (PWM_L4_LOC == 0) -#define RTE_PWM_4L_PIN PWM_L4_PIN +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN #define RTE_PWM_4L_MUX 10 #define RTE_PWM_4L_PAD 7 #endif -#if (PWM_L4_LOC == 1) -#define RTE_PWM_4L_PIN (PWM_L4_PIN + GPIO_MAX_PIN) +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) #define RTE_PWM_4L_MUX 8 #define RTE_PWM_4L_PAD 28 #endif -// Pintool data +//Pintool data #endif // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 @@ -3838,31 +3782,36 @@ #if (RTE_PWM_FAULTA_PORT_ID == 0) #define RTE_PWM_FAULTA_PORT 0 -#define RTE_PWM_FAULTA_PIN 25 -#define RTE_PWM_FAULTA_MUX 10 -#define RTE_PWM_FAULTA_PAD 0 // no pad +#define RTE_PWM_FAULTA_PIN 25 +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad #elif (RTE_PWM_FAULTA_PORT_ID == 2) #define RTE_PWM_FAULTA_PORT 0 -#define RTE_PWM_FAULTA_PIN 73 -#define RTE_PWM_FAULTA_MUX 8 -#define RTE_PWM_FAULTA_PAD 31 +#define RTE_PWM_FAULTA_PIN 73 +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 #else #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT -#if (PWM_FAULTA_LOC == 0) +#if (PWM_FAULTA_LOC == 16) #define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN #define RTE_PWM_FAULTA_MUX 10 -#define RTE_PWM_FAULTA_PAD 0 // no pad +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 #endif -#if (PWM_FAULTA_LOC == 2) +#if (PWM_FAULTA_LOC == 18) #define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) #define RTE_PWM_FAULTA_MUX 8 #define RTE_PWM_FAULTA_PAD 31 #endif -// Pintool data +//Pintool data #endif // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 @@ -3871,214 +3820,261 @@ #if (RTE_PWM_FAULTB_PORT_ID == 0) #define RTE_PWM_FAULTB_PORT 0 -#define RTE_PWM_FAULTB_PIN 26 -#define RTE_PWM_FAULTB_MUX 10 -#define RTE_PWM_FAULTB_PAD 0 // no pad +#define RTE_PWM_FAULTB_PIN 26 +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad #elif (RTE_PWM_FAULTB_PORT_ID == 2) #define RTE_PWM_FAULTB_PORT 0 -#define RTE_PWM_FAULTB_PIN 74 -#define RTE_PWM_FAULTB_MUX 8 -#define RTE_PWM_FAULTB_PAD 32 +#define RTE_PWM_FAULTB_PIN 74 +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 #else #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT -#if (PWM_FAULTB_LOC == 0) +#if (PWM_FAULTB_LOC == 19) #define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN #define RTE_PWM_FAULTB_MUX 10 -#define RTE_PWM_FAULTB_PAD 0 // no pad +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 #endif -#if (PWM_FAULTB_LOC == 2) +#if (PWM_FAULTB_LOC == 21) #define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) #define RTE_PWM_FAULTB_MUX 8 #define RTE_PWM_FAULTB_PAD 32 #endif -// Pintool data +//Pintool data #endif -// PWM_SLP_EVENT_TRIG GPIO_72 -#ifndef PWM_SLEEPTRIG_LOC +//PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 -#define RTE_PWM_SLP_EVENT_TRIG_PIN 72 +#define RTE_PWM_SLP_EVENT_TRIG_PIN 72 #else -// Pintool data -#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVENT_TRIG_PORT -#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVENT_TRIG_PIN + GPIO_MAX_PIN) -// Pintool data +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data #endif #define RTE_PWM_SLP_EVENT_TRIG_MUX 8 #define RTE_PWM_SLP_EVENT_TRIG_PAD 30 -// PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +//PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 #ifndef PWM_EXTTRIG1_LOC #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 -#define RTE_PWM_TMR_EXT_TRIG_1_PIN 27 -#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 -#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 // no pad +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 27 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad #elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1) #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 -#define RTE_PWM_TMR_EXT_TRIG_1_PIN 51 -#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 -#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 51 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 #elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 2) #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 -#define RTE_PWM_TMR_EXT_TRIG_1_PIN 70 -#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 -#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 70 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 #elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3) #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 -#define RTE_PWM_TMR_EXT_TRIG_1_PIN 75 -#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 -#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 75 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT -#if (PWM_EXTTRIG1_LOC == 0) +#if (PWM_EXTTRIG1_LOC == 22) #define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 -#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 // no pad +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad #endif -#if (PWM_EXTTRIG1_LOC == 1) +#if (PWM_EXTTRIG1_LOC == 23) #define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 #endif -#if (PWM_EXTTRIG1_LOC == 2) +#if (PWM_EXTTRIG1_LOC == 24) #define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 #endif -#if (PWM_EXTTRIG1_LOC == 3) +#if (PWM_EXTTRIG1_LOC == 25) #define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 #endif -// Pintool data +//Pintool data #endif -// PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +//PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 #ifndef PWM_EXTTRIG2_LOC #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) #define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 -#define RTE_PWM_TMR_EXT_TRIG_2_PIN 28 -#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 -#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 // no pad +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 28 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad #elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1) #define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 -#define RTE_PWM_TMR_EXT_TRIG_2_PIN 54 -#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 -#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 54 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 #elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 2) #define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 -#define RTE_PWM_TMR_EXT_TRIG_2_PIN 71 -#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 -#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 71 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" #endif #else -// Pintool data +//Pintool data #define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT -#if (PWM_EXTTRIG2_LOC == 0) +#if (PWM_EXTTRIG2_LOC == 26) #define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 -#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 // no pad +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad #endif -#if (PWM_EXTTRIG2_LOC == 1) +#if (PWM_EXTTRIG2_LOC == 27) #define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN #define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 #endif -#if (PWM_EXTTRIG2_LOC == 2) +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux #define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 #endif -// Pintool data +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 #endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data //<> QEI (Quadrature Encode Interface) -// QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 -// <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 +//QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 #define RTE_QEI_DIR_PORT_ID 4 #if (RTE_QEI_DIR_PORT_ID == 0) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 28 -#define RTE_QEI_DIR_MUX 5 -#define RTE_QEI_DIR_PAD 0 // no pad +#define RTE_QEI_DIR_PIN 28 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 0 //no pad #elif (RTE_QEI_DIR_PORT_ID == 1) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 49 -#define RTE_QEI_DIR_MUX 3 -#define RTE_QEI_DIR_PAD 13 +#define RTE_QEI_DIR_PIN 49 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 13 #elif (RTE_QEI_DIR_PORT_ID == 2) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 57 -#define RTE_QEI_DIR_MUX 5 -#define RTE_QEI_DIR_PAD 21 +#define RTE_QEI_DIR_PIN 57 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 21 #elif (RTE_QEI_DIR_PORT_ID == 3) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 67 -#define RTE_QEI_DIR_MUX 3 -#define RTE_QEI_DIR_PAD 25 +#define RTE_QEI_DIR_PIN 67 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 25 #elif (RTE_QEI_DIR_PORT_ID == 4) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 71 -#define RTE_QEI_DIR_MUX 3 -#define RTE_QEI_DIR_PAD 29 +#define RTE_QEI_DIR_PIN 71 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 29 #elif (RTE_QEI_DIR_PORT_ID == 5) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 73 -#define RTE_QEI_DIR_MUX 3 -#define RTE_QEI_DIR_PAD 31 +#define RTE_QEI_DIR_PIN 73 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 31 #else #error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" #endif -// QEI_IDX <0=>GPIO_25 <1=>GPIO_46 <2=>GPIO_52 <3=>GPIO_64 <4=>GPIO_68 -// <5=>GPIO_72 <6=>GPIO_8 <7=>GPIO_13 +//QEI_IDX <0=>GPIO_25 <1=>GPIO_46 <2=>GPIO_52 <3=>GPIO_64 <4=>GPIO_68 <5=>GPIO_72 <6=>GPIO_8 <7=>GPIO_13 #define RTE_QEI_IDX_PORT_ID 3 #if (RTE_QEI_IDX_PORT_ID == 0) #define RTE_QEI_IDX_PORT 0 -#define RTE_QEI_IDX_PIN 25 -#define RTE_QEI_IDX_MUX 5 -#define RTE_QEI_IDX_PAD 0 // no pad +#define RTE_QEI_IDX_PIN 25 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 0 //no pad #elif (RTE_QEI_IDX_PORT_ID == 1) #define RTE_QEI_IDX_PORT 0 -#define RTE_QEI_IDX_PIN 46 -#define RTE_QEI_IDX_MUX 3 -#define RTE_QEI_IDX_PAD 10 +#define RTE_QEI_IDX_PIN 46 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 10 #elif (RTE_QEI_IDX_PORT_ID == 2) #define RTE_QEI_IDX_PORT 0 -#define RTE_QEI_IDX_PIN 52 -#define RTE_QEI_IDX_MUX 5 -#define RTE_QEI_IDX_PAD 16 +#define RTE_QEI_IDX_PIN 52 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 16 #elif (RTE_QEI_IDX_PORT_ID == 3) #define RTE_QEI_IDX_PORT 0 -#define RTE_QEI_IDX_PIN 72 -#define RTE_QEI_IDX_MUX 3 -#define RTE_QEI_IDX_PAD 30 +#define RTE_QEI_IDX_PIN 72 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 30 #else #error "Invalid RTE_QEI_IDX_PIN Pin Configuration!" #endif -// QEI_PHA <0=>GPIO_26 <1=>GPIO_47 <2=>GPIO_53 <3=>GPIO_65 <4=>GPIO_69 -// <5=>GPIO_73 <6=>GPIO_9 <7=>GPIO_32 +//QEI_PHA <0=>GPIO_26 <1=>GPIO_47 <2=>GPIO_53 <3=>GPIO_65 <4=>GPIO_69 <5=>GPIO_73 <6=>GPIO_9 <7=>GPIO_32 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_QEI_PHA_PORT_ID 3 @@ -4088,35 +4084,34 @@ #if (RTE_QEI_PHA_PORT_ID == 0) #define RTE_QEI_PHA_PORT 0 -#define RTE_QEI_PHA_PIN 26 -#define RTE_QEI_PHA_MUX 5 -#define RTE_QEI_PHA_PAD 0 // no pad +#define RTE_QEI_PHA_PIN 26 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 0 //no pad #elif (RTE_QEI_PHA_PORT_ID == 1) #define RTE_QEI_PHA_PORT 0 -#define RTE_QEI_PHA_PIN 47 -#define RTE_QEI_PHA_MUX 3 -#define RTE_QEI_PHA_PAD 11 +#define RTE_QEI_PHA_PIN 47 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 11 #elif (RTE_QEI_PHA_PORT_ID == 2) #define RTE_QEI_PHA_PORT 0 -#define RTE_QEI_PHA_PIN 53 -#define RTE_QEI_PHA_MUX 5 -#define RTE_QEI_PHA_PAD 17 +#define RTE_QEI_PHA_PIN 53 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 17 #elif (RTE_QEI_PHA_PORT_ID == 3) #define RTE_QEI_PHA_PORT 0 -#define RTE_QEI_PHA_PIN 65 -#define RTE_QEI_PHA_MUX 3 -#define RTE_QEI_PHA_PAD 23 +#define RTE_QEI_PHA_PIN 65 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 23 #elif (RTE_QEI_PHA_PORT_ID == 4) #define RTE_QEI_PHA_PORT 0 -#define RTE_QEI_PHA_PIN 73 -#define RTE_QEI_PHA_MUX 3 -#define RTE_QEI_PHA_PAD 31 +#define RTE_QEI_PHA_PIN 73 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 31 #else #error "Invalid RTE_QEI_PHA_PIN Pin Configuration!" #endif -// QEI_PHB <0=>GPIO_27 <1=>GPIO_48 <1=>GPIO_56 <1=>GPIO_66 <1=>GPIO_70 -// <1=>GPIO_74 <7=>GPIO_33 +//QEI_PHB <0=>GPIO_27 <1=>GPIO_48 <1=>GPIO_56 <1=>GPIO_66 <1=>GPIO_70 <1=>GPIO_74 <7=>GPIO_33 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_QEI_PHB_PORT_ID 5 @@ -4126,515 +4121,515 @@ #if (RTE_QEI_PHB_PORT_ID == 0) #define RTE_QEI_PHB_PORT 0 -#define RTE_QEI_PHB_PIN 27 -#define RTE_QEI_PHB_MUX 5 -#define RTE_QEI_PHB_PAD 0 // no pad +#define RTE_QEI_PHB_PIN 27 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 0 //no pad #elif (RTE_QEI_PHB_PORT_ID == 1) #define RTE_QEI_PHB_PORT 0 -#define RTE_QEI_PHB_PIN 48 -#define RTE_QEI_PHB_MUX 3 -#define RTE_QEI_PHB_PAD 12 +#define RTE_QEI_PHB_PIN 48 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 12 #elif (RTE_QEI_PHB_PORT_ID == 2) #define RTE_QEI_PHB_PORT 0 -#define RTE_QEI_PHB_PIN 56 -#define RTE_QEI_PHB_MUX 5 -#define RTE_QEI_PHB_PAD 20 +#define RTE_QEI_PHB_PIN 56 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 20 #elif (RTE_QEI_PHB_PORT_ID == 3) #define RTE_QEI_PHB_PORT 0 -#define RTE_QEI_PHB_PIN 66 -#define RTE_QEI_PHB_MUX 3 -#define RTE_QEI_PHB_PAD 24 +#define RTE_QEI_PHB_PIN 66 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 24 #elif (RTE_QEI_PHB_PORT_ID == 4) #define RTE_QEI_PHB_PORT 0 -#define RTE_QEI_PHB_PIN 70 -#define RTE_QEI_PHB_MUX 3 -#define RTE_QEI_PHB_PAD 28 +#define RTE_QEI_PHB_PIN 70 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 28 #elif (RTE_QEI_PHB_PORT_ID == 5) #define RTE_QEI_PHB_PORT 0 -#define RTE_QEI_PHB_PIN 74 -#define RTE_QEI_PHB_MUX 3 -#define RTE_QEI_PHB_PAD 32 +#define RTE_QEI_PHB_PIN 74 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 32 #else #error "Invalid RTE_QEI_PHB_PIN Pin Configuration!" #endif #endif -// ADC START +//ADC START #ifndef ADC_P0_LOC #define RTE_ADC_P0_PORT 0 -#define RTE_ADC_P0_PIN 0 +#define RTE_ADC_P0_PIN 0 #else #define RTE_ADC_P0_PORT ADC_P0_PORT -#define RTE_ADC_P0_PIN ADC_P0_PIN +#define RTE_ADC_P0_PIN ADC_P0_PIN #endif #define RTE_ADC_P0_MUX 1 #ifndef ADC_N0_LOC #define RTE_ADC_N0_PORT 0 -#define RTE_ADC_N0_PIN 1 +#define RTE_ADC_N0_PIN 1 #else #define RTE_ADC_N0_PORT ADC_N0_PORT -#define RTE_ADC_N0_PIN ADC_N0_PIN +#define RTE_ADC_N0_PIN ADC_N0_PIN #endif #define RTE_ADC_N0_MUX 1 #ifndef ADC_P1_LOC #define RTE_ADC_P1_PORT 0 -#define RTE_ADC_P1_PIN 2 +#define RTE_ADC_P1_PIN 2 #else #define RTE_ADC_P1_PORT ADC_P1_PORT -#define RTE_ADC_P1_PIN ADC_P1_PIN +#define RTE_ADC_P1_PIN ADC_P1_PIN #endif #define RTE_ADC_P1_MUX 1 #ifndef ADC_N1_LOC #define RTE_ADC_N1_PORT 0 -#define RTE_ADC_N1_PIN 3 +#define RTE_ADC_N1_PIN 3 #else #define RTE_ADC_N1_PORT ADC_N1_PORT -#define RTE_ADC_N1_PIN ADC_N1_PIN +#define RTE_ADC_N1_PIN ADC_N1_PIN #endif #define RTE_ADC_N1_MUX 1 #ifndef ADC_P2_LOC #define RTE_ADC_P2_PORT 0 -#define RTE_ADC_P2_PIN 4 +#define RTE_ADC_P2_PIN 4 #else #define RTE_ADC_P2_PORT ADC_P2_PORT -#define RTE_ADC_P2_PIN ADC_P2_PIN +#define RTE_ADC_P2_PIN ADC_P2_PIN #endif #define RTE_ADC_P2_MUX 1 #ifndef ADC_N2_LOC #define RTE_ADC_N2_PORT 0 -#define RTE_ADC_N2_PIN 5 +#define RTE_ADC_N2_PIN 5 #else #define RTE_ADC_N2_PORT ADC_N2_PORT -#define RTE_ADC_N2_PIN ADC_N2_PIN +#define RTE_ADC_N2_PIN ADC_N2_PIN #endif #define RTE_ADC_N2_MUX 1 #ifndef ADC_P3_LOC #define RTE_ADC_P3_PORT 0 -#define RTE_ADC_P3_PIN 6 +#define RTE_ADC_P3_PIN 6 #else #define RTE_ADC_P3_PORT ADC_P3_PORT -#define RTE_ADC_P3_PIN ADC_P3_PIN +#define RTE_ADC_P3_PIN ADC_P3_PIN #endif #define RTE_ADC_P3_MUX 1 #ifndef ADC_N3_LOC #define RTE_ADC_N3_PORT 0 -#define RTE_ADC_N3_PIN 11 +#define RTE_ADC_N3_PIN 11 #else #define RTE_ADC_N3_PORT ADC_N3_PORT -#define RTE_ADC_N3_PIN ADC_N3_PIN +#define RTE_ADC_N3_PIN ADC_N3_PIN #endif #define RTE_ADC_N3_MUX 1 #ifndef ADC_P4_LOC #define RTE_ADC_P4_PORT 0 -#define RTE_ADC_P4_PIN 8 +#define RTE_ADC_P4_PIN 8 #else #define RTE_ADC_P4_PORT ADC_P4_PORT -#define RTE_ADC_P4_PIN ADC_P4_PIN +#define RTE_ADC_P4_PIN ADC_P4_PIN #endif #define RTE_ADC_P4_MUX 1 #ifndef ADC_N4_LOC #define RTE_ADC_N4_PORT 0 -#define RTE_ADC_N4_PIN 9 +#define RTE_ADC_N4_PIN 9 #else #define RTE_ADC_N4_PORT ADC_N4_PORT -#define RTE_ADC_N4_PIN ADC_N4_PIN +#define RTE_ADC_N4_PIN ADC_N4_PIN #endif #define RTE_ADC_N4_MUX 1 #ifndef ADC_P5_LOC #define RTE_ADC_P5_PORT 0 -#define RTE_ADC_P5_PIN 10 +#define RTE_ADC_P5_PIN 10 #else #define RTE_ADC_P5_PORT ADC_P5_PORT -#define RTE_ADC_P5_PIN ADC_P5_PIN +#define RTE_ADC_P5_PIN ADC_P5_PIN #endif #define RTE_ADC_P5_MUX 1 #ifndef ADC_N5_LOC #define RTE_ADC_N5_PORT 0 -#define RTE_ADC_N5_PIN 7 +#define RTE_ADC_N5_PIN 7 #else #define RTE_ADC_N5_PORT ADC_N5_PORT -#define RTE_ADC_N5_PIN ADC_N5_PIN +#define RTE_ADC_N5_PIN ADC_N5_PIN #endif #define RTE_ADC_N5_MUX 1 #ifndef ADC_P6_LOC #define RTE_ADC_P6_PORT 0 -#define RTE_ADC_P6_PIN 25 +#define RTE_ADC_P6_PIN 25 #else #define RTE_ADC_P6_PORT ADC_P6_PORT -#define RTE_ADC_P6_PIN ADC_P6_PIN +#define RTE_ADC_P6_PIN ADC_P6_PIN #endif #define RTE_ADC_P6_MUX 1 #define RTE_ADC_P6_PAD 0 #ifndef ADC_N6_LOC #define RTE_ADC_N6_PORT 0 -#define RTE_ADC_N6_PIN 26 +#define RTE_ADC_N6_PIN 26 #else #define RTE_ADC_N6_PORT ADC_N6_PORT -#define RTE_ADC_N6_PIN ADC_N6_PIN +#define RTE_ADC_N6_PIN ADC_N6_PIN #endif #define RTE_ADC_N6_MUX 1 #define RTE_ADC_N6_PAD 0 #ifndef ADC_P7_LOC #define RTE_ADC_P7_PORT 0 -#define RTE_ADC_P7_PIN 27 +#define RTE_ADC_P7_PIN 27 #else #define RTE_ADC_P7_PORT ADC_P7_PORT -#define RTE_ADC_P7_PIN ADC_P7_PIN +#define RTE_ADC_P7_PIN ADC_P7_PIN #endif #define RTE_ADC_P7_MUX 1 #define RTE_ADC_P7_PAD 0 #ifndef ADC_N7_LOC #define RTE_ADC_N7_PORT 0 -#define RTE_ADC_N7_PIN 28 +#define RTE_ADC_N7_PIN 28 #else #define RTE_ADC_N7_PORT ADC_N7_PORT -#define RTE_ADC_N7_PIN ADC_N7_PIN +#define RTE_ADC_N7_PIN ADC_N7_PIN #endif #define RTE_ADC_N7_MUX 1 #define RTE_ADC_N7_PAD 0 #ifndef ADC_P8_LOC #define RTE_ADC_P8_PORT 0 -#define RTE_ADC_P8_PIN 29 +#define RTE_ADC_P8_PIN 29 #else #define RTE_ADC_P8_PORT ADC_P8_PORT -#define RTE_ADC_P8_PIN ADC_P8_PIN +#define RTE_ADC_P8_PIN ADC_P8_PIN #endif #define RTE_ADC_P8_MUX 1 #define RTE_ADC_P8_PAD 0 #ifndef ADC_N8_LOC #define RTE_ADC_N8_PORT 0 -#define RTE_ADC_N8_PIN 30 +#define RTE_ADC_N8_PIN 30 #else #define RTE_ADC_N8_PORT ADC_N8_PORT -#define RTE_ADC_N8_PIN ADC_N8_PIN +#define RTE_ADC_N8_PIN ADC_N8_PIN #endif #define RTE_ADC_N8_MUX 1 #define RTE_ADC_N8_PAD 0 #ifndef ADC_P10_LOC #define RTE_ADC_P10_PORT 0 -#define RTE_ADC_P10_PIN 1 +#define RTE_ADC_P10_PIN 1 #else #define RTE_ADC_P10_PORT ADC_P10_PORT -#define RTE_ADC_P10_PIN ADC_P10_PIN +#define RTE_ADC_P10_PIN ADC_P10_PIN #endif #define RTE_ADC_P10_MUX 1 #ifndef ADC_P11_LOC #define RTE_ADC_P11_PORT 0 -#define RTE_ADC_P11_PIN 3 +#define RTE_ADC_P11_PIN 3 #else #define RTE_ADC_P11_PORT ADC_P11_PORT -#define RTE_ADC_P11_PIN ADC_P11_PIN +#define RTE_ADC_P11_PIN ADC_P11_PIN #endif #define RTE_ADC_P11_MUX 1 #ifndef ADC_P12_LOC #define RTE_ADC_P12_PORT 0 -#define RTE_ADC_P12_PIN 5 +#define RTE_ADC_P12_PIN 5 #else #define RTE_ADC_P12_PORT ADC_P12_PORT -#define RTE_ADC_P12_PIN ADC_P12_PIN +#define RTE_ADC_P12_PIN ADC_P12_PIN #endif #define RTE_ADC_P12_MUX 1 #ifndef ADC_P13_LOC #define RTE_ADC_P13_PORT 0 -#define RTE_ADC_P13_PIN 11 +#define RTE_ADC_P13_PIN 11 #else #define RTE_ADC_P13_PORT ADC_P13_PORT -#define RTE_ADC_P13_PIN ADC_P13_PIN +#define RTE_ADC_P13_PIN ADC_P13_PIN #endif #define RTE_ADC_P13_MUX 1 #ifndef ADC_P14_LOC #define RTE_ADC_P14_PORT 0 -#define RTE_ADC_P14_PIN 9 +#define RTE_ADC_P14_PIN 9 #else #define RTE_ADC_P14_PORT ADC_P14_PORT -#define RTE_ADC_P14_PIN ADC_P14_PIN +#define RTE_ADC_P14_PIN ADC_P14_PIN #endif #define RTE_ADC_P14_MUX 1 #ifndef ADC_P15_LOC #define RTE_ADC_P15_PORT 0 -#define RTE_ADC_P15_PIN 7 +#define RTE_ADC_P15_PIN 7 #else #define RTE_ADC_P15_PORT ADC_P15_PORT -#define RTE_ADC_P15_PIN ADC_P15_PIN +#define RTE_ADC_P15_PIN ADC_P15_PIN #endif #define RTE_ADC_P15_MUX 1 #ifndef ADC_P16_LOC #define RTE_ADC_P16_PORT 0 -#define RTE_ADC_P16_PIN 26 +#define RTE_ADC_P16_PIN 26 #else #define RTE_ADC_P16_PORT ADC_P16_PORT -#define RTE_ADC_P16_PIN ADC_P16_PIN +#define RTE_ADC_P16_PIN ADC_P16_PIN #endif #define RTE_ADC_P16_MUX 1 #define RTE_ADC_P16_PAD 0 #ifndef ADC_P17_LOC #define RTE_ADC_P17_PORT 0 -#define RTE_ADC_P17_PIN 28 +#define RTE_ADC_P17_PIN 28 #else #define RTE_ADC_P17_PORT ADC_P17_PORT -#define RTE_ADC_P17_PIN ADC_P17_PIN +#define RTE_ADC_P17_PIN ADC_P17_PIN #endif #define RTE_ADC_P17_MUX 1 #define RTE_ADC_P17_PAD 0 #ifndef ADC_P18_LOC #define RTE_ADC_P18_PORT 0 -#define RTE_ADC_P18_PIN 30 +#define RTE_ADC_P18_PIN 30 #else #define RTE_ADC_P18_PORT ADC_P18_PORT -#define RTE_ADC_P18_PIN ADC_P18_PIN +#define RTE_ADC_P18_PIN ADC_P18_PIN #endif #define RTE_ADC_P18_MUX 1 #define RTE_ADC_P18_PAD 0 -// ADC END +//ADC END -// COMPARATOR START +//COMPARATOR START #ifndef COMP1_P0_LOC #define RTE_COMP1_P0_PORT 0 -#define RTE_COMP1_P0_PIN 0 +#define RTE_COMP1_P0_PIN 0 #else #define RTE_COMP1_P0_PORT COMP1_P0_PORT -#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#define RTE_COMP1_P0_PIN COMP1_P0_PIN #endif #define RTE_COMP1_P0_MUX 0 #ifndef COMP1_N0_LOC #define RTE_COMP1_N0_PORT 0 -#define RTE_COMP1_N0_PIN 1 +#define RTE_COMP1_N0_PIN 1 #else #define RTE_COMP1_N0_PORT COMP1_N0_PORT -#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#define RTE_COMP1_N0_PIN COMP1_N0_PIN #endif #define RTE_COMP1_N0_MUX 0 #ifndef COMP1_P1_LOC #define RTE_COMP1_P1_PORT 0 -#define RTE_COMP1_P1_PIN 5 +#define RTE_COMP1_P1_PIN 5 #else #define RTE_COMP1_P1_PORT COMP1_P1_PORT -#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#define RTE_COMP1_P1_PIN COMP1_P1_PIN #endif #define RTE_COMP1_P1_MUX 0 #ifndef COMP1_N1_LOC #define RTE_COMP1_N1_PORT 0 -#define RTE_COMP1_N1_PIN 4 +#define RTE_COMP1_N1_PIN 4 #else #define RTE_COMP1_N1_PORT COMP1_N1_PORT -#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#define RTE_COMP1_N1_PIN COMP1_N1_PIN #endif #define RTE_COMP1_N1_MUX 0 #ifndef COMP2_P0_LOC #define RTE_COMP2_P0_PORT 0 -#define RTE_COMP2_P0_PIN 2 +#define RTE_COMP2_P0_PIN 2 #else #define RTE_COMP2_P0_PORT COMP2_P0_PORT -#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#define RTE_COMP2_P0_PIN COMP2_P0_PIN #endif #define RTE_COMP2_P0_MUX 0 #ifndef COMP2_N0_LOC #define RTE_COMP2_N0_PORT 0 -#define RTE_COMP2_N0_PIN 3 +#define RTE_COMP2_N0_PIN 3 #else #define RTE_COMP2_N0_PORT COMP2_N0_PORT -#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#define RTE_COMP2_N0_PIN COMP2_N0_PIN #endif #define RTE_COMP2_N0_MUX 0 #ifndef COMP2_P1_LOC #define RTE_COMP2_P1_PORT 0 -#define RTE_COMP2_P1_PIN 27 +#define RTE_COMP2_P1_PIN 27 #else #define RTE_COMP2_P1_PORT COMP2_P1_PORT -#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#define RTE_COMP2_P1_PIN COMP2_P1_PIN #endif #define RTE_COMP2_P1_MUX 0 #define RTE_COMP2_P1_PAD 0 #ifndef COMP2_N1_LOC #define RTE_COMP2_N1_PORT 0 -#define RTE_COMP2_N1_PIN 28 +#define RTE_COMP2_N1_PIN 28 #else #define RTE_COMP2_N1_PORT COMP2_N1_PORT -#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#define RTE_COMP2_N1_PIN COMP2_N1_PIN #endif #define RTE_COMP2_N1_MUX 0 -// COMPARATOR END +//COMPARATOR END #define RTE_GPIO_6_PORT 0 -#define RTE_GPIO_6_PAD 1 -#define RTE_GPIO_6_PIN 6 +#define RTE_GPIO_6_PAD 1 +#define RTE_GPIO_6_PIN 6 #define RTE_GPIO_6_MODE 0 #define RTE_GPIO_7_PORT 0 -#define RTE_GPIO_7_PAD 2 -#define RTE_GPIO_7_PIN 7 +#define RTE_GPIO_7_PAD 2 +#define RTE_GPIO_7_PIN 7 #define RTE_GPIO_7_MODE 0 #define RTE_GPIO_8_PORT 0 -#define RTE_GPIO_8_PAD 3 -#define RTE_GPIO_8_PIN 8 +#define RTE_GPIO_8_PAD 3 +#define RTE_GPIO_8_PIN 8 #define RTE_GPIO_8_MODE 0 #define RTE_GPIO_9_PORT 0 -#define RTE_GPIO_9_PAD 4 -#define RTE_GPIO_9_PIN 9 +#define RTE_GPIO_9_PAD 4 +#define RTE_GPIO_9_PIN 9 #define RTE_GPIO_9_MODE 0 #define RTE_GPIO_10_PORT 0 -#define RTE_GPIO_10_PAD 5 -#define RTE_GPIO_10_PIN 10 +#define RTE_GPIO_10_PAD 5 +#define RTE_GPIO_10_PIN 10 #define RTE_GPIO_10_MODE 0 #define RTE_GPIO_11_PORT 0 -#define RTE_GPIO_11_PAD 6 -#define RTE_GPIO_11_PIN 11 +#define RTE_GPIO_11_PAD 6 +#define RTE_GPIO_11_PIN 11 #define RTE_GPIO_11_MODE 0 #define RTE_GPIO_12_PORT 0 -#define RTE_GPIO_12_PAD 7 -#define RTE_GPIO_12_PIN 12 +#define RTE_GPIO_12_PAD 7 +#define RTE_GPIO_12_PIN 12 #define RTE_GPIO_12_MODE 0 #define RTE_GPIO_15_PORT 0 -#define RTE_GPIO_15_PAD 8 -#define RTE_GPIO_15_PIN 15 +#define RTE_GPIO_15_PAD 8 +#define RTE_GPIO_15_PIN 15 #define RTE_GPIO_15_MODE 0 -#define RTE_GPIO_25_PORT 1 -#define RTE_GPIO_25_PIN 25 +#define RTE_GPIO_25_PORT 0 +#define RTE_GPIO_25_PIN 25 #define RTE_GPIO_25_MODE 0 -#define RTE_GPIO_26_PORT 1 -#define RTE_GPIO_26_PIN 26 +#define RTE_GPIO_26_PORT 0 +#define RTE_GPIO_26_PIN 26 #define RTE_GPIO_26_MODE 0 -#define RTE_GPIO_27_PORT 1 -#define RTE_GPIO_27_PIN 27 +#define RTE_GPIO_27_PORT 0 +#define RTE_GPIO_27_PIN 27 #define RTE_GPIO_27_MODE 0 -#define RTE_GPIO_28_PORT 1 -#define RTE_GPIO_28_PIN 28 +#define RTE_GPIO_28_PORT 0 +#define RTE_GPIO_28_PIN 28 #define RTE_GPIO_28_MODE 0 -#define RTE_GPIO_29_PORT 1 -#define RTE_GPIO_29_PIN 29 +#define RTE_GPIO_29_PORT 0 +#define RTE_GPIO_29_PIN 29 #define RTE_GPIO_29_MODE 0 -#define RTE_GPIO_30_PORT 1 -#define RTE_GPIO_30_PIN 30 +#define RTE_GPIO_30_PORT 0 +#define RTE_GPIO_30_PIN 30 #define RTE_GPIO_30_MODE 0 -#define RTE_GPIO_31_PORT 1 -#define RTE_GPIO_31_PAD 9 -#define RTE_GPIO_31_PIN 31 +#define RTE_GPIO_31_PORT 0 +#define RTE_GPIO_31_PAD 9 +#define RTE_GPIO_31_PIN 31 #define RTE_GPIO_31_MODE 0 -#define RTE_GPIO_32_PORT 2 -#define RTE_GPIO_32_PAD 9 -#define RTE_GPIO_32_PIN 32 +#define RTE_GPIO_32_PORT 0 +#define RTE_GPIO_32_PAD 9 +#define RTE_GPIO_32_PIN 32 #define RTE_GPIO_32_MODE 0 -#define RTE_GPIO_33_PORT 2 -#define RTE_GPIO_33_PAD 9 -#define RTE_GPIO_33_PIN 33 +#define RTE_GPIO_33_PORT 0 +#define RTE_GPIO_33_PAD 9 +#define RTE_GPIO_33_PIN 33 #define RTE_GPIO_33_MODE 0 -#define RTE_GPIO_34_PORT 2 -#define RTE_GPIO_34_PAD 9 -#define RTE_GPIO_34_PIN 34 +#define RTE_GPIO_34_PORT 0 +#define RTE_GPIO_34_PAD 9 +#define RTE_GPIO_34_PIN 34 #define RTE_GPIO_34_MODE 0 -#define RTE_GPIO_46_PORT 2 -#define RTE_GPIO_46_PAD 10 -#define RTE_GPIO_46_PIN 46 +#define RTE_GPIO_46_PORT 0 +#define RTE_GPIO_46_PAD 10 +#define RTE_GPIO_46_PIN 46 #define RTE_GPIO_46_MODE 0 -#define RTE_GPIO_47_PORT 2 -#define RTE_GPIO_47_PAD 11 -#define RTE_GPIO_47_PIN 47 +#define RTE_GPIO_47_PORT 0 +#define RTE_GPIO_47_PAD 11 +#define RTE_GPIO_47_PIN 47 #define RTE_GPIO_47_MODE 0 -#define RTE_GPIO_48_PORT 3 -#define RTE_GPIO_48_PAD 12 -#define RTE_GPIO_48_PIN 48 +#define RTE_GPIO_48_PORT 0 +#define RTE_GPIO_48_PAD 12 +#define RTE_GPIO_48_PIN 48 #define RTE_GPIO_48_MODE 0 -#define RTE_GPIO_49_PORT 3 -#define RTE_GPIO_49_PAD 13 -#define RTE_GPIO_49_PIN 49 +#define RTE_GPIO_49_PORT 0 +#define RTE_GPIO_49_PAD 13 +#define RTE_GPIO_49_PIN 49 #define RTE_GPIO_49_MODE 0 -#define RTE_GPIO_50_PORT 3 -#define RTE_GPIO_50_PAD 14 -#define RTE_GPIO_50_PIN 50 +#define RTE_GPIO_50_PORT 0 +#define RTE_GPIO_50_PAD 14 +#define RTE_GPIO_50_PIN 50 #define RTE_GPIO_50_MODE 0 -#define RTE_GPIO_51_PORT 3 -#define RTE_GPIO_51_PAD 15 -#define RTE_GPIO_51_PIN 51 +#define RTE_GPIO_51_PORT 0 +#define RTE_GPIO_51_PAD 15 +#define RTE_GPIO_51_PIN 51 #define RTE_GPIO_51_MODE 0 -#define RTE_GPIO_52_PORT 3 -#define RTE_GPIO_52_PAD 16 -#define RTE_GPIO_52_PIN 52 +#define RTE_GPIO_52_PORT 0 +#define RTE_GPIO_52_PAD 16 +#define RTE_GPIO_52_PIN 52 #define RTE_GPIO_52_MODE 0 -#define RTE_GPIO_53_PORT 3 -#define RTE_GPIO_53_PAD 17 -#define RTE_GPIO_53_PIN 53 +#define RTE_GPIO_53_PORT 0 +#define RTE_GPIO_53_PAD 17 +#define RTE_GPIO_53_PIN 53 #define RTE_GPIO_53_MODE 0 -#define RTE_GPIO_54_PORT 3 -#define RTE_GPIO_54_PAD 18 -#define RTE_GPIO_54_PIN 54 +#define RTE_GPIO_54_PORT 0 +#define RTE_GPIO_54_PAD 18 +#define RTE_GPIO_54_PIN 54 #define RTE_GPIO_54_MODE 0 -#define RTE_GPIO_55_PORT 3 -#define RTE_GPIO_55_PAD 19 -#define RTE_GPIO_55_PIN 55 +#define RTE_GPIO_55_PORT 0 +#define RTE_GPIO_55_PAD 19 +#define RTE_GPIO_55_PIN 55 #define RTE_GPIO_55_MODE 0 -#define RTE_GPIO_56_PORT 3 -#define RTE_GPIO_56_PAD 20 -#define RTE_GPIO_56_PIN 56 +#define RTE_GPIO_56_PORT 0 +#define RTE_GPIO_56_PAD 20 +#define RTE_GPIO_56_PIN 56 #define RTE_GPIO_56_MODE 0 -#define RTE_GPIO_57_PORT 3 -#define RTE_GPIO_57_PAD 21 -#define RTE_GPIO_57_PIN 57 +#define RTE_GPIO_57_PORT 0 +#define RTE_GPIO_57_PAD 21 +#define RTE_GPIO_57_PIN 57 #define RTE_GPIO_57_MODE 0 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER @@ -4645,12 +4640,12 @@ #if (RTE_ULP_GPIO_0_PORT_ID == 0) #define RTE_ULP_GPIO_0_PORT 0 -#define RTE_ULP_GPIO_0_PAD 22 -#define RTE_ULP_GPIO_0_PIN 64 +#define RTE_ULP_GPIO_0_PAD 22 +#define RTE_ULP_GPIO_0_PIN 64 #define RTE_ULP_GPIO_0_MODE 0 #elif (RTE_ULP_GPIO_0_PORT_ID == 1) #define RTE_ULP_GPIO_0_PORT 4 -#define RTE_ULP_GPIO_0_PIN 0 +#define RTE_ULP_GPIO_0_PIN 0 #define RTE_ULP_GPIO_0_MODE 0 #else #error "Invalid RTE_ULP_GPIO_0_PIN Pin Configuration!" @@ -4664,12 +4659,12 @@ #if (RTE_ULP_GPIO_1_PORT_ID == 0) #define RTE_ULP_GPIO_1_PORT 0 -#define RTE_ULP_GPIO_1_PAD 23 -#define RTE_ULP_GPIO_1_PIN 65 +#define RTE_ULP_GPIO_1_PAD 23 +#define RTE_ULP_GPIO_1_PIN 65 #define RTE_ULP_GPIO_1_MODE 0 #elif (RTE_ULP_GPIO_1_PORT_ID == 1) #define RTE_ULP_GPIO_1_PORT 4 -#define RTE_ULP_GPIO_1_PIN 1 +#define RTE_ULP_GPIO_1_PIN 1 #define RTE_ULP_GPIO_1_MODE 0 #else #error "Invalid RTE_ULP_GPIO_1_PIN Pin Configuration!" @@ -4683,12 +4678,12 @@ #if (RTE_ULP_GPIO_2_PORT_ID == 0) #define RTE_ULP_GPIO_2_PORT 0 -#define RTE_ULP_GPIO_2_PAD 24 -#define RTE_ULP_GPIO_2_PIN 66 +#define RTE_ULP_GPIO_2_PAD 24 +#define RTE_ULP_GPIO_2_PIN 66 #define RTE_ULP_GPIO_2_MODE 0 #elif (RTE_ULP_GPIO_2_PORT_ID == 1) #define RTE_ULP_GPIO_2_PORT 4 -#define RTE_ULP_GPIO_2_PIN 2 +#define RTE_ULP_GPIO_2_PIN 2 #define RTE_ULP_GPIO_2_MODE 0 #else #error "Invalid RTE_ULP_GPIO_2_PIN Pin Configuration!" @@ -4702,12 +4697,12 @@ #if (RTE_ULP_GPIO_3_PORT_ID == 0) #define RTE_ULP_GPIO_3_PORT 0 -#define RTE_ULP_GPIO_3_PAD 25 -#define RTE_ULP_GPIO_3_PIN 67 +#define RTE_ULP_GPIO_3_PAD 25 +#define RTE_ULP_GPIO_3_PIN 67 #define RTE_ULP_GPIO_3_MODE 0 #elif (RTE_ULP_GPIO_3_PORT_ID == 1) #define RTE_ULP_GPIO_3_PORT 4 -#define RTE_ULP_GPIO_3_PIN 3 +#define RTE_ULP_GPIO_3_PIN 3 #define RTE_ULP_GPIO_3_MODE 0 #else #error "Invalid RTE_ULP_GPIO_3_PIN Pin Configuration!" @@ -4721,12 +4716,12 @@ #if (RTE_ULP_GPIO_4_PORT_ID == 0) #define RTE_ULP_GPIO_4_PORT 0 -#define RTE_ULP_GPIO_4_PAD 26 -#define RTE_ULP_GPIO_4_PIN 68 +#define RTE_ULP_GPIO_4_PAD 26 +#define RTE_ULP_GPIO_4_PIN 68 #define RTE_ULP_GPIO_4_MODE 0 #elif (RTE_ULP_GPIO_4_PORT_ID == 1) #define RTE_ULP_GPIO_4_PORT 4 -#define RTE_ULP_GPIO_4_PIN 4 +#define RTE_ULP_GPIO_4_PIN 4 #define RTE_ULP_GPIO_4_MODE 0 #else #error "Invalid RTE_ULP_GPIO_4_PIN Pin Configuration!" @@ -4740,12 +4735,12 @@ #if (RTE_ULP_GPIO_5_PORT_ID == 0) #define RTE_ULP_GPIO_5_PORT 4 -#define RTE_ULP_GPIO_5_PAD 27 -#define RTE_ULP_GPIO_5_PIN 69 +#define RTE_ULP_GPIO_5_PAD 27 +#define RTE_ULP_GPIO_5_PIN 69 #define RTE_ULP_GPIO_5_MODE 0 #elif (RTE_ULP_GPIO_5_PORT_ID == 1) #define RTE_ULP_GPIO_5_PORT 4 -#define RTE_ULP_GPIO_5_PIN 5 +#define RTE_ULP_GPIO_5_PIN 5 #define RTE_ULP_GPIO_5_MODE 0 #else #error "Invalid RTE_ULP_GPIO_5_PIN Pin Configuration!" @@ -4759,12 +4754,12 @@ #if (RTE_ULP_GPIO_6_PORT_ID == 0) #define RTE_ULP_GPIO_6_PORT 4 -#define RTE_ULP_GPIO_6_PAD 28 -#define RTE_ULP_GPIO_6_PIN 70 +#define RTE_ULP_GPIO_6_PAD 28 +#define RTE_ULP_GPIO_6_PIN 70 #define RTE_ULP_GPIO_6_MODE 0 #elif (RTE_ULP_GPIO_6_PORT_ID == 1) #define RTE_ULP_GPIO_6_PORT 4 -#define RTE_ULP_GPIO_6_PIN 6 +#define RTE_ULP_GPIO_6_PIN 6 #define RTE_ULP_GPIO_6_MODE 0 #else #error "Invalid RTE_ULP_GPIO_6_PIN Pin Configuration!" @@ -4778,12 +4773,12 @@ #if (RTE_ULP_GPIO_7_PORT_ID == 0) #define RTE_ULP_GPIO_7_PORT 4 -#define RTE_ULP_GPIO_7_PAD 29 -#define RTE_ULP_GPIO_7_PIN 71 +#define RTE_ULP_GPIO_7_PAD 29 +#define RTE_ULP_GPIO_7_PIN 71 #define RTE_ULP_GPIO_7_MODE 0 #elif (RTE_ULP_GPIO_7_PORT_ID == 1) #define RTE_ULP_GPIO_7_PORT 4 -#define RTE_ULP_GPIO_7_PIN 7 +#define RTE_ULP_GPIO_7_PIN 7 #define RTE_ULP_GPIO_7_MODE 0 #else #error "Invalid RTE_ULP_GPIO_7_PIN Pin Configuration!" @@ -4797,12 +4792,12 @@ #if (RTE_ULP_GPIO_8_PORT_ID == 0) #define RTE_ULP_GPIO_8_PORT 4 -#define RTE_ULP_GPIO_8_PAD 30 -#define RTE_ULP_GPIO_8_PIN 72 +#define RTE_ULP_GPIO_8_PAD 30 +#define RTE_ULP_GPIO_8_PIN 72 #define RTE_ULP_GPIO_8_MODE 0 #elif (RTE_ULP_GPIO_8_PORT_ID == 1) #define RTE_ULP_GPIO_8_PORT 4 -#define RTE_ULP_GPIO_8_PIN 8 +#define RTE_ULP_GPIO_8_PIN 8 #define RTE_ULP_GPIO_8_MODE 0 #else #error "Invalid RTE_ULP_GPIO_8_PIN Pin Configuration!" @@ -4816,12 +4811,12 @@ #if (RTE_ULP_GPIO_9_PORT_ID == 0) #define RTE_ULP_GPIO_9_PORT 4 -#define RTE_ULP_GPIO_9_PAD 31 -#define RTE_ULP_GPIO_9_PIN 73 +#define RTE_ULP_GPIO_9_PAD 31 +#define RTE_ULP_GPIO_9_PIN 73 #define RTE_ULP_GPIO_9_MODE 0 #elif (RTE_ULP_GPIO_9_PORT_ID == 1) #define RTE_ULP_GPIO_9_PORT 4 -#define RTE_ULP_GPIO_9_PIN 9 +#define RTE_ULP_GPIO_9_PIN 9 #define RTE_ULP_GPIO_9_MODE 0 #else #error "Invalid RTE_ULP_GPIO_9_PIN Pin Configuration!" @@ -4835,12 +4830,12 @@ #if (RTE_ULP_GPIO_10_PORT_ID == 0) #define RTE_ULP_GPIO_10_PORT 4 -#define RTE_ULP_GPIO_10_PAD 32 -#define RTE_ULP_GPIO_10_PIN 74 +#define RTE_ULP_GPIO_10_PAD 32 +#define RTE_ULP_GPIO_10_PIN 74 #define RTE_ULP_GPIO_10_MODE 0 #elif (RTE_ULP_GPIO_10_PORT_ID == 1) #define RTE_ULP_GPIO_10_PORT 4 -#define RTE_ULP_GPIO_10_PIN 10 +#define RTE_ULP_GPIO_10_PIN 10 #define RTE_ULP_GPIO_10_MODE 0 #else #error "Invalid RTE_ULP_GPIO_10_PIN Pin Configuration!" @@ -4854,31 +4849,41 @@ #if (RTE_ULP_GPIO_11_PORT_ID == 0) #define RTE_ULP_GPIO_11_PORT 4 -#define RTE_ULP_GPIO_11_PAD 33 -#define RTE_ULP_GPIO_11_PIN 75 +#define RTE_ULP_GPIO_11_PAD 33 +#define RTE_ULP_GPIO_11_PIN 75 #define RTE_ULP_GPIO_11_MODE 0 #elif (RTE_ULP_GPIO_11_PORT_ID == 1) #define RTE_ULP_GPIO_11_PORT 4 -#define RTE_ULP_GPIO_11_PIN 11 +#define RTE_ULP_GPIO_11_PIN 11 #define RTE_ULP_GPIO_11_MODE 0 #else #error "Invalid RTE_ULP_GPIO_11_PIN Pin Configuration!" #endif -#define RTE_UULP_GPIO_0_PIN 0 +// RTE_UULP_GPIO_x_PORT refers to port for UULP GPIO pin x +#define RTE_UULP_GPIO_0_PORT 5 +#define RTE_UULP_GPIO_0_PIN 0 #define RTE_UULP_GPIO_0_MODE 0 -#define RTE_UULP_GPIO_1_PIN 1 +#define RTE_UULP_GPIO_1_PORT 5 +#define RTE_UULP_GPIO_1_PIN 1 #define RTE_UULP_GPIO_1_MODE 0 -#define RTE_UULP_GPIO_2_PIN 2 +#define RTE_UULP_GPIO_2_PORT 5 +#define RTE_UULP_GPIO_2_PIN 2 #define RTE_UULP_GPIO_2_MODE 0 -#define RTE_UULP_GPIO_3_PIN 3 +#define RTE_UULP_GPIO_3_PORT 5 +#define RTE_UULP_GPIO_3_PIN 3 #define RTE_UULP_GPIO_3_MODE 0 -#define RTE_UULP_GPIO_4_PIN 4 +#define RTE_UULP_GPIO_4_PORT 5 +#define RTE_UULP_GPIO_4_PIN 4 #define RTE_UULP_GPIO_4_MODE 0 -#define RTE_UULP_GPIO_5_PIN 5 +#define RTE_UULP_GPIO_5_PIN 5 #define RTE_UULP_GPIO_5_MODE 0 + +// UULP GPIO as enable pin for sensors +#define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP +#define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN diff --git a/matter/si91x/siwx917/BRD4338A/config/SEGGER_RTT_Conf.h b/matter/si91x/siwx917/BRD4338A/config/SEGGER_RTT_Conf.h index 9c9b81a5d3..91283ff736 100644 --- a/matter/si91x/siwx917/BRD4338A/config/SEGGER_RTT_Conf.h +++ b/matter/si91x/siwx917/BRD4338A/config/SEGGER_RTT_Conf.h @@ -3,7 +3,7 @@ * The Embedded Experts * ********************************************************************** * * -* (c) 1995 - 2021 SEGGER Microcontroller GmbH * +* (c) 1995 - 2023 SEGGER Microcontroller GmbH * * * * www.segger.com Support: support@segger.com * * * @@ -42,7 +42,7 @@ * * ********************************************************************** * * -* SystemView version: 3.32 * +* SystemView version: 3.52 * * * ********************************************************************** ---------------------------END-OF-HEADER------------------------------ @@ -58,422 +58,371 @@ Revision: $Rev: 24316 $ #define SEGGER_RTT_CONF_H #ifdef __IAR_SYSTEMS_ICC__ -#include + #include #endif /********************************************************************* - * - * Defines, configurable - * - ********************************************************************** - */ +* +* Defines, configurable +* +********************************************************************** +*/ // // Take in and set to correct values for Cortex-A systems with CPU cache // -//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest -// cache line size (in bytes) in the current system #define -// SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias -// where RTT CB and buffers can be accessed uncached +//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system +//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached // // Most common case: // Up-channel 0: RTT // Up-channel 1: SystemView // -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS -#define SEGGER_RTT_MAX_NUM_UP_BUFFERS \ - (3) // Max. number of up-buffers (T->H) available on this target (Default: - // 3) +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (9) // Max. number of up-buffers (T->H) available on this target (Default: 9) #endif // // Most common case: // Down-channel 0: RTT // Down-channel 1: SystemView // -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS -#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS \ - (3) // Max. number of down-buffers (H->T) available on this target (Default: - // 3) +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (9) // Max. number of down-buffers (H->T) available on this target (Default: 9) #endif -#ifndef BUFFER_SIZE_UP -#define BUFFER_SIZE_UP \ - (1024) // Size of the buffer for terminal output of target, up to host - // (Default: 1k) +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) #endif -#ifndef BUFFER_SIZE_DOWN -#define BUFFER_SIZE_DOWN \ - (1024) // Size of the buffer for terminal input to target from host (Usually - // keyboard input) (Default: 16) +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (1024) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) #endif -#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE -#define SEGGER_RTT_PRINTF_BUFFER_SIZE \ - (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: - // 64) +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) #endif -#ifndef SEGGER_RTT_MODE_DEFAULT -#define SEGGER_RTT_MODE_DEFAULT \ - SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel - // (buffer 0) +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) #endif /********************************************************************* - * - * RTT memcpy configuration - * - * memcpy() is good for large amounts of data, - * but the overhead is big for small amounts, which are usually stored via - * RTT. With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used - * instead. - * - * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT - * functions. This is may be required with memory access restrictions, such as - * on Cortex-A devices with MMU. - */ -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP -#define SEGGER_RTT_MEMCPY_USE_BYTELOOP \ - 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +* +* RTT memcpy configuration +* +* memcpy() is good for large amounts of data, +* but the overhead is big for small amounts, which are usually stored via RTT. +* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. +* +* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. +* This is may be required with memory access restrictions, +* such as on Cortex-A devices with MMU. +*/ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop #endif // -// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC -// toolchains and Cortex-A targets +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets // -//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) -//&& (defined (__ARM_ARCH_7A__)) -// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), -// (pSrc), (NumBytes)) +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) //#endif // -// Target is not allowed to perform other RTT operations while string still has -// not been stored completely. Otherwise we would probably end up with a mixed -// string in the buffer. If using RTT from within interrupts, multiple tasks or -// multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() -// function here. +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. // -// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on -// Cortex-M3/4. Make sure to mask all interrupts which can send RTT data, i.e. -// generate SystemView events, or cause task switches. When high-priority -// interrupts must not be masked while sending RTT data, -// SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. (Higher -// priority = lower priority number) Default value for embOS: 128u Default -// configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( -// configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) In -// case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 -// when 3 bits are implemented in NVIC or define SEGGER_RTT_LOCK() to completely -// disable interrupts. +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. // -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY -#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY \ - (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 - // (Default: 0x20) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) #endif /********************************************************************* - * - * RTT lock configuration for SEGGER Embedded Studio, - * Rowley CrossStudio and GCC - */ -#if ((defined(__SES_ARM) || defined(__SES_RISCV) || \ - defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && \ - !defined(__CC_ARM) && !defined(WIN32)) -#if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile("mrs %0, primask \n\t" \ - "movs r1, #1 \n\t" \ - "msr primask, r1 \n\t" \ - : "=r"(_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc"); - -#define SEGGER_RTT_UNLOCK() \ - __asm volatile("msr primask, %0 \n\t" : : "r"(_SEGGER_RTT__LockState) :); \ - } -#elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || \ - defined(__ARM_ARCH_8M_MAIN__)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY -#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) -#endif -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile("mrs %0, basepri \n\t" \ - "mov r1, %1 \n\t" \ - "msr basepri, r1 \n\t" \ - : "=r"(_SEGGER_RTT__LockState) \ - : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ - : "r1", "cc"); - -#define SEGGER_RTT_UNLOCK() \ - __asm volatile("msr basepri, %0 \n\t" : : "r"(_SEGGER_RTT__LockState) :); \ - } - -#elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r"(_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc"); - -#define SEGGER_RTT_UNLOCK() \ - __asm volatile("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r"(_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc"); \ - } -#elif defined(__riscv) || defined(__riscv_xlen) -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile("csrr %0, mstatus \n\t" \ - "csrci mstatus, 8 \n\t" \ - "andi %0, %0, 8 \n\t" \ - : "=r"(_SEGGER_RTT__LockState) \ - : \ - :); - -#define SEGGER_RTT_UNLOCK() \ - __asm volatile("csrr a1, mstatus \n\t" \ - "or %0, %0, a1 \n\t" \ - "csrs mstatus, %0 \n\t" \ - : \ - : "r"(_SEGGER_RTT__LockState) \ - : "a1"); \ - } -#else -#define SEGGER_RTT_LOCK() -#define SEGGER_RTT_UNLOCK() -#endif +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif #endif /********************************************************************* - * - * RTT lock configuration for IAR EWARM - */ +* +* RTT lock configuration for IAR EWARM +*/ #ifdef __ICCARM__ -#if (defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - -#define SEGGER_RTT_UNLOCK() \ - __set_PRIMASK(_SEGGER_RTT__LockState); \ - } -#elif (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ - (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ - (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ - (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY -#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) -#endif -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_BASEPRI(); \ - __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - -#define SEGGER_RTT_UNLOCK() \ - __set_BASEPRI(_SEGGER_RTT__LockState); \ - } -#elif (defined(__ARM7A__) && (__CORE__ == __ARM7A__)) || \ - (defined(__ARM7R__) && (__CORE__ == __ARM7R__)) -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r"(_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc"); - -#define SEGGER_RTT_UNLOCK() \ - __asm volatile("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r"(_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc"); \ - } -#endif + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ + (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif #endif /********************************************************************* - * - * RTT lock configuration for IAR RX - */ +* +* RTT lock configuration for IAR RX +*/ #ifdef __ICCRX__ -#define SEGGER_RTT_LOCK() \ - { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - -#define SEGGER_RTT_UNLOCK() \ - __set_interrupt_state(_SEGGER_RTT__LockState); \ - } + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } #endif /********************************************************************* - * - * RTT lock configuration for IAR RL78 - */ +* +* RTT lock configuration for IAR RL78 +*/ #ifdef __ICCRL78__ -#define SEGGER_RTT_LOCK() \ - { \ - __istate_t _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - -#define SEGGER_RTT_UNLOCK() \ - __set_interrupt_state(_SEGGER_RTT__LockState); \ - } + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } #endif /********************************************************************* - * - * RTT lock configuration for KEIL ARM - */ +* +* RTT lock configuration for KEIL ARM +*/ #ifdef __CC_ARM -#if (defined __TARGET_ARCH_6S_M) -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char _SEGGER_RTT__PRIMASK __asm("primask"); \ - _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ - _SEGGER_RTT__PRIMASK = 1u; \ - __schedule_barrier(); - -#define SEGGER_RTT_UNLOCK() \ - _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } -#elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY -#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) -#endif -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char BASEPRI __asm("basepri"); \ - _SEGGER_RTT__LockState = BASEPRI; \ - BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ - __schedule_barrier(); - -#define SEGGER_RTT_UNLOCK() \ - BASEPRI = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } -#endif + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif #endif /********************************************************************* - * - * RTT lock configuration for TI ARM - */ +* +* RTT lock configuration for TI ARM +*/ #ifdef __TI_ARM__ -#if defined(__TI_ARM_V6M0__) -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - -#define SEGGER_RTT_UNLOCK() \ - __set_PRIMASK(_SEGGER_RTT__LockState); \ - } -#elif (defined(__TI_ARM_V7M3__) || defined(__TI_ARM_V7M4__)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY -#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) -#endif -#define SEGGER_RTT_LOCK() \ - { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = \ - _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - -#define SEGGER_RTT_UNLOCK() \ - _set_interrupt_priority(_SEGGER_RTT__LockState); \ - } -#endif + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif #endif /********************************************************************* - * - * RTT lock configuration for CCRX - */ +* +* RTT lock configuration for CCRX +*/ #ifdef __RX -#include -#define SEGGER_RTT_LOCK() \ - { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = get_psw() & 0x010000; \ - clrpsw_i(); - -#define SEGGER_RTT_UNLOCK() \ - set_psw(get_psw() | _SEGGER_RTT__LockState); \ - } + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } #endif /********************************************************************* - * - * RTT lock configuration for embOS Simulation on Windows - * (Can also be used for generic RTT locking with embOS) - */ +* +* RTT lock configuration for embOS Simulation on Windows +* (Can also be used for generic RTT locking with embOS) +*/ #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) void OS_SIM_EnterCriticalSection(void); void OS_SIM_LeaveCriticalSection(void); -#define SEGGER_RTT_LOCK() \ - { \ - OS_SIM_EnterCriticalSection(); +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); -#define SEGGER_RTT_UNLOCK() \ - OS_SIM_LeaveCriticalSection(); \ - } +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } #endif /********************************************************************* - * - * RTT lock configuration fallback - */ -#ifndef SEGGER_RTT_LOCK -#define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) #endif -#ifndef SEGGER_RTT_UNLOCK -#define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous - // interrupt lock state) +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) #endif -/********************************************************************* - * - * RTT control block configuration - */ -#define SEGGER_RTT_ALIGNMENT 1024 - #endif /*************************** End of file ****************************/ diff --git a/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h b/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h index 0641552551..13e4b919ea 100644 --- a/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h @@ -1,5 +1,4 @@ -/***************************************************************************/ -/** +/***************************************************************************//** * @file * @brief emlib_core Configuration ******************************************************************************* @@ -36,12 +35,9 @@ // Core Configuration -// Enables measuring of -// interrupt disable time for debugging purposes. +// Enables measuring of interrupt disable time for debugging purposes. // Default: 0 -// If Enabled, -// either cycle_counter or systemview component must be added to project. -#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 // diff --git a/matter/si91x/siwx917/BRD4338A/config/glib_config.h b/matter/si91x/siwx917/BRD4338A/config/glib_config.h index 45b9c32a0d..47c3291015 100644 --- a/matter/si91x/siwx917/BRD4338A/config/glib_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/glib_config.h @@ -1,32 +1,32 @@ -/***************************************************************************/ /** - * @file - * @brief GLIB Config. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ +/***************************************************************************//** + * @file + * @brief GLIB Config. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ #ifndef SL_GLIB_CONFIG_H #define SL_GLIB_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/nvm3_default_config.h b/matter/si91x/siwx917/BRD4338A/config/nvm3_default_config.h new file mode 100644 index 0000000000..7cd7f1f1e4 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/nvm3_default_config.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* @file nvm3_default_config.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef NVM3_DEFAULT_CONFIG_H +#define NVM3_DEFAULT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// NVM3 Default Instance Configuration + +#ifndef NVM3_DEFAULT_CACHE_SIZE +// NVM3 Default Instance Cache Size +// Number of NVM3 objects to cache. To reduce access times this number +// should be equal to or higher than the number of NVM3 objects in the +// default NVM3 instance. +// Default: 200 +#define NVM3_DEFAULT_CACHE_SIZE 200 +#endif + +#ifndef NVM3_DEFAULT_MAX_OBJECT_SIZE +// NVM3 Default Instance Max Object Size +// Max NVM3 object size that can be stored. +// Default: 254 +#define NVM3_DEFAULT_MAX_OBJECT_SIZE 254 +#endif + +#ifndef NVM3_DEFAULT_REPACK_HEADROOM +// NVM3 Default Instance User Repack Headroom +// Headroom determining how many bytes below the forced repack limit the user +// repack limit should be placed. The default is 0, which means the user and +// forced repack limits are equal. +// Default: 0 +#define NVM3_DEFAULT_REPACK_HEADROOM 0 +#endif + +#ifndef NVM3_DEFAULT_NVM_SIZE +// NVM3 Default Instance Size +// Size of the NVM3 storage region in flash. This size should be aligned with +// the flash page size of the device. +// Default: 36864 +#define NVM3_DEFAULT_NVM_SIZE 36864 +#endif + +// + +// <<< end of configuration section >>> + +#endif // NVM3_DEFAULT_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/pin_config.h b/matter/si91x/siwx917/BRD4338A/config/pin_config.h index 32a2f2ffc2..ab6a567430 100644 --- a/matter/si91x/siwx917/BRD4338A/config/pin_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/pin_config.h @@ -16,8 +16,8 @@ // $[I2C1] // [I2C1]$ -// $[I2C2] -// [I2C2]$ +// $[ULP_I2C] +// [ULP_I2C]$ // $[SSI_MASTER] // [SSI_MASTER]$ @@ -25,8 +25,8 @@ // $[SSI_SLAVE] // [SSI_SLAVE]$ -// $[SSI_ULP_MASTER] -// [SSI_ULP_MASTER]$ +// $[ULP_SPI] +// [ULP_SPI]$ // $[GSPI_MASTER] // [GSPI_MASTER]$ @@ -34,8 +34,8 @@ // $[I2S0] // [I2S0]$ -// $[I2S1] -// [I2S1]$ +// $[ULP_I2S] +// [ULP_I2S]$ // $[SCT] // [SCT]$ @@ -46,6 +46,21 @@ // $[PWM] // [PWM]$ +// $[ADC] +// [ADC]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + // $[CUSTOM_PIN_NAME] #ifndef _PORT #define _PORT 0 diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_board_configuration.h b/matter/si91x/siwx917/BRD4338A/config/sl_board_configuration.h index 27d6b722ba..635fe5f8a2 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_board_configuration.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_board_configuration.h @@ -1,23 +1,23 @@ /******************************************************************************* - * @file sl_board_configuration.h - * @brief - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ +* @file sl_board_configuration.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ #pragma once #include -#define DEFAULT_UART NULL +#define DEFAULT_UART NULL #define DEFAULT_UART_PIN_CONFIG NULL diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_board_control.h b/matter/si91x/siwx917/BRD4338A/config/sl_board_control.h index 50876ba47b..8b85d7553a 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_board_control.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_board_control.h @@ -1,19 +1,19 @@ /******************************************************************************* - * @file sl_board_control.h - * @brief - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ +* @file sl_board_control.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ #pragma once diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_core_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_core_config.h new file mode 100644 index 0000000000..27b173d2eb --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_core_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief sl_core Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CORE_CONFIG_H +#define SL_CORE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Abstraction Configuration + +// Enables measurement of interrupt masking time for debugging purposes. +// Default: 0 +#define SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING 0 +// + +// <<< end of configuration section >>> +#endif // SL_CORE_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_mbedtls_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_mbedtls_config.h index 1f99808c88..e4d42433cb 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_mbedtls_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_mbedtls_config.h @@ -107,7 +107,9 @@ // the correct Mbed TLS / PSA Crypto options. #include "sli_mbedtls_config_transform_autogen.h" -#ifndef SL_MBEDTLS_USE_TINYCRYPT +#ifdef SL_MBEDTLS_USE_TINYCRYPT +#include "mbedtls/check_config.h" +#else // Included for backward compatibility reasons. #include "mbedtls/build_info.h" #endif // SL_MBEDTLS_USE_TINYCRYPT diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_memory_manager_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_memory_manager_config.h new file mode 100644 index 0000000000..7e4b056778 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_memory_manager_config.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Memory Heap Allocator configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_MEMORY_MANAGER_CONFIG_H +#define SL_MEMORY_MANAGER_CONFIG_H + +// Memory Manager Configuration + +// Minimum block allocation size +// <32-128:8> +// Minimum block allocation size to avoid creating a block too small while splitting up an allocated block. +// Size expressed in bytes and can only be a multiple of 8 bytes for the proper data alignment management done by the dynamic allocator malloc() function. +// Default: 32 +#define SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE (32) + +// + +// <<< end of configuration section >>> + +#endif /* SL_MEMORY_MANAGER_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_memory_manager_region_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_memory_manager_region_config.h new file mode 100644 index 0000000000..ba02fdd8f3 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_memory_manager_region_config.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Memory Heap and stack size configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_MEMORY_MANAGER_REGION_CONFIG_H +#define SL_MEMORY_MANAGER_REGION_CONFIG_H + +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE +#define SL_STACK_SIZE 4096 +#endif +// + +// <<< end of configuration section >>> + +#endif /* SL_MEMORY_MANAGER_REGION_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_net_default_values.h b/matter/si91x/siwx917/BRD4338A/config/sl_net_default_values.h index eb3ca19e54..d1b7ad08f6 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_net_default_values.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_net_default_values.h @@ -1,27 +1,26 @@ /******************************************************************************* - * @file sl_net_default_values.h - * @brief - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ +* @file sl_net_default_values.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ #pragma once #include "sl_net_wifi_types.h" #if defined(__GNUC__) -// Ignore warning of unused variables. It is expected that some or all of these -// are unused +// Ignore warning of unused variables. It is expected that some or all of these are unused #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-variable" #endif @@ -53,7 +52,7 @@ #endif #ifndef DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE -#define DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE SL_WIFI_CCMP_ENCRYPTION +#define DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE SL_WIFI_DEFAULT_ENCRYPTION #endif //! IP address of the module @@ -74,121 +73,75 @@ #define DEFAULT_WIFI_GATEWAY_ADDRESS 0x0A0AA8C0 #endif -//! Wi-Fi BTR Channel -#define SL_CHANNEL_NO 14 - -//! Wi-Fi BTR default Tx power -#define SL_TX_POWER 127 - -//! Wi-Fi BTR config default values -#define DEFAULT_RETRANSMIT_COUNT 15 -#define DEFAULT_QOS_BE_CWMIN 4 -#define DEFAULT_QOS_BE_CWMAX 6 -#define DEFAULT_QOS_BE_AIFSN 3 -#define DEFAULT_QOS_BK_CWMIN 4 -#define DEFAULT_QOS_BK_CWMAX 10 -#define DEFAULT_QOS_BK_AIFSN 7 -#define DEFAULT_QOS_VI_CWMIN 3 -#define DEFAULT_QOS_VI_CWMAX 4 -#define DEFAULT_QOS_VI_AIFSN 1 -#define DEFAULT_QOS_VO_CWMIN 2 -#define DEFAULT_QOS_VO_CWMAX 3 -#define DEFAULT_QOS_VO_AIFSN 1 - -//! Wi-Fi BTR option to store peer information in MAC layer -#define MAC_PEER_DS_SUPPORT 1 -#define FEAT_BTR_MAC_PEER_DS_SUPPORT BIT(13) - -#define DEFAULT_WIFI_CLIENT_PROFILE \ - (sl_net_wifi_client_profile_t) { \ - .config = \ - { \ - .ssid.value = DEFAULT_WIFI_CLIENT_PROFILE_SSID, \ - .ssid.length = sizeof(DEFAULT_WIFI_CLIENT_PROFILE_SSID) - 1, \ - .channel.channel = SL_WIFI_AUTO_CHANNEL, \ - .channel.band = SL_WIFI_AUTO_BAND, \ - .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ - .bssid = {{0}}, \ - .bss_type = SL_WIFI_BSS_TYPE_INFRASTRUCTURE, \ - .security = DEFAULT_WIFI_CLIENT_SECURITY_TYPE, \ - .encryption = DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE, \ - .client_options = 0, \ - .credential_id = SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID, \ - }, \ - .ip = { \ - .mode = SL_IP_MANAGEMENT_DHCP, \ - .type = REQUIRED_IP_TYPE, \ - .host_name = NULL, \ - .ip = {{{0}}}, \ - } \ +#define DEFAULT_WIFI_CLIENT_PROFILE \ + (sl_net_wifi_client_profile_t) \ + { \ + .config = { \ + .ssid.value = DEFAULT_WIFI_CLIENT_PROFILE_SSID, \ + .ssid.length = sizeof(DEFAULT_WIFI_CLIENT_PROFILE_SSID)-1, \ + .channel.channel = SL_WIFI_AUTO_CHANNEL, \ + .channel.band = SL_WIFI_AUTO_BAND, \ + .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ + .bssid = {{0}}, \ + .bss_type = SL_WIFI_BSS_TYPE_INFRASTRUCTURE, \ + .security = DEFAULT_WIFI_CLIENT_SECURITY_TYPE, \ + .encryption = DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE, \ + .client_options = 0, \ + .credential_id = SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID, \ + }, \ + .ip = { \ + .mode = SL_IP_MANAGEMENT_DHCP, \ + .type = REQUIRED_IP_TYPE, \ + .host_name = NULL, \ + .ip = {{{0}}}, \ + } \ } -#define DEFAULT_WIFI_ACCESS_POINT_PROFILE \ - (sl_net_wifi_ap_profile_t) { \ - .config = \ - { \ - .ssid.value = DEFAULT_WIFI_AP_PROFILE_SSID, \ - .ssid.length = sizeof(DEFAULT_WIFI_AP_PROFILE_SSID) - 1, \ - .channel.channel = SL_WIFI_AUTO_CHANNEL, \ - .channel.band = SL_WIFI_AUTO_BAND, \ - .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ - .security = SL_WIFI_WPA2, \ - .encryption = SL_WIFI_CCMP_ENCRYPTION, \ - .rate_protocol = SL_WIFI_RATE_PROTOCOL_AUTO, \ - .options = 0, \ - .credential_id = SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID, \ - .keepalive_type = SL_SI91X_AP_NULL_BASED_KEEP_ALIVE, \ - .beacon_interval = 100, \ - .client_idle_timeout = 0xFF, \ - .dtim_beacon_count = 3, \ - .maximum_clients = 3, \ - .beacon_stop = 0, \ - .tdi_flags = SL_WIFI_TDI_NONE, \ - .is_11n_enabled = 0, \ - }, \ - .ip = { \ - .mode = SL_IP_MANAGEMENT_STATIC_IP, \ - .type = SL_IPV4, \ - .host_name = NULL, \ - .ip = {.v4.ip_address.value = DEFAULT_WIFI_MODULE_IP_ADDRESS, \ - .v4.gateway.value = DEFAULT_WIFI_GATEWAY_ADDRESS, \ - .v4.netmask.value = DEFAULT_WIFI_SN_MASK_ADDRESS}, \ - } \ - } - -#define DEFAULT_WIFI_BTR_PROFILE \ - (sl_net_wifi_btr_profile_t) { \ - .config = { \ - .btr_chan_info.chan_info = {.channel = SL_CHANNEL_NO, \ - .band = SL_WIFI_BAND_2_4GHZ, \ - .bandwidth = SL_WIFI_BANDWIDTH_20MHz}, \ - .btr_chan_info.tx_power = SL_TX_POWER, \ - .config_params.set = 1, \ - .config_params.retransmit_count = DEFAULT_RETRANSMIT_COUNT, \ - .config_params.cw_params[0] = {.cwmin = DEFAULT_QOS_BE_CWMIN, \ - .cwmax = DEFAULT_QOS_BE_CWMAX, \ - .aifsn = DEFAULT_QOS_BE_AIFSN}, \ - .config_params.cw_params[1] = {.cwmin = DEFAULT_QOS_BK_CWMIN, \ - .cwmax = DEFAULT_QOS_BK_CWMAX, \ - .aifsn = DEFAULT_QOS_BK_AIFSN}, \ - .config_params.cw_params[2] = {.cwmin = DEFAULT_QOS_VI_CWMIN, \ - .cwmax = DEFAULT_QOS_VI_CWMAX, \ - .aifsn = DEFAULT_QOS_VI_AIFSN}, \ - .config_params.cw_params[3] = {.cwmin = DEFAULT_QOS_VO_CWMIN, \ - .cwmax = DEFAULT_QOS_VO_CWMAX, \ - .aifsn = DEFAULT_QOS_VO_AIFSN} \ - } \ +#define DEFAULT_WIFI_ACCESS_POINT_PROFILE \ + (sl_net_wifi_ap_profile_t) \ + { \ + .config = { \ + .ssid.value = DEFAULT_WIFI_AP_PROFILE_SSID, \ + .ssid.length = sizeof(DEFAULT_WIFI_AP_PROFILE_SSID)-1, \ + .channel.channel = SL_WIFI_AUTO_CHANNEL, \ + .channel.band = SL_WIFI_AUTO_BAND, \ + .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ + .security = SL_WIFI_WPA2, \ + .encryption = SL_WIFI_CCMP_ENCRYPTION, \ + .rate_protocol = SL_WIFI_RATE_PROTOCOL_AUTO, \ + .options = 0, \ + .credential_id = SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID, \ + .keepalive_type = SL_SI91X_AP_NULL_BASED_KEEP_ALIVE, \ + .beacon_interval = 100, \ + .client_idle_timeout = 0xFF, \ + .dtim_beacon_count = 3, \ + .maximum_clients = 3, \ + .beacon_stop = 0, \ + .tdi_flags =SL_WIFI_TDI_NONE, \ + .is_11n_enabled = 0, \ + }, \ + .ip = { \ + .mode = SL_IP_MANAGEMENT_STATIC_IP, \ + .type = SL_IPV4, \ + .host_name = NULL, \ + .ip = { \ + .v4.ip_address.value = DEFAULT_WIFI_MODULE_IP_ADDRESS, \ + .v4.gateway.value = DEFAULT_WIFI_GATEWAY_ADDRESS, \ + .v4.netmask.value = DEFAULT_WIFI_SN_MASK_ADDRESS \ + }, \ + } \ } static sl_net_wifi_psk_credential_entry_t default_wifi_client_credential = { - .type = SL_NET_WIFI_PSK, - .data_length = sizeof(DEFAULT_WIFI_CLIENT_CREDENTIAL) - 1, - .data = DEFAULT_WIFI_CLIENT_CREDENTIAL}; - -static sl_net_wifi_psk_credential_entry_t default_wifi_ap_credential = { - .type = SL_NET_WIFI_PSK, - .data_length = sizeof(DEFAULT_WIFI_AP_CREDENTIAL) - 1, - .data = DEFAULT_WIFI_AP_CREDENTIAL}; + .type = SL_NET_WIFI_PSK, + .data_length = sizeof(DEFAULT_WIFI_CLIENT_CREDENTIAL) - 1, + .data = DEFAULT_WIFI_CLIENT_CREDENTIAL +}; + +static sl_net_wifi_psk_credential_entry_t default_wifi_ap_credential = { .type = SL_NET_WIFI_PSK, + .data_length = + sizeof(DEFAULT_WIFI_AP_CREDENTIAL) - 1, + .data = DEFAULT_WIFI_AP_CREDENTIAL }; #if defined(__GNUC__) // Restore GCC diagnostics #pragma GCC diagnostic pop diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn0_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn0_config.h index 4834327983..dac1086d80 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn0_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn0_config.h @@ -1,5 +1,4 @@ -/***************************************************************************/ -/** +/***************************************************************************/ /** * @file sl_si91x_button_config.h * @brief Button Driver Configuration ******************************************************************************* diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn1_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn1_config.h index 230d68eb2f..5f1a9a9a3e 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn1_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_btn1_config.h @@ -1,5 +1,4 @@ -/***************************************************************************/ -/** +/***************************************************************************/ /** * @file sl_si91x_button_config.h * @brief Button Driver Configuration ******************************************************************************* diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_pin_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_pin_config.h index 59a8a07229..b0121118bb 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_pin_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_button_pin_config.h @@ -1,5 +1,4 @@ -/***************************************************************************/ -/** +/***************************************************************************/ /** * @file sl_si91x_button_config.h * @brief Button Driver Configuration ******************************************************************************* @@ -14,13 +13,13 @@ #define SL_SI91x_BUTTON_COUNT (2) -#define SL_BUTTON_BTN0_PIN RTE_BUTTON0_PIN -#define SL_BUTTON_BTN0_PORT RTE_BUTTON0_PORT +#define SL_BUTTON_BTN0_PIN RTE_BUTTON0_PIN +#define SL_BUTTON_BTN0_PORT RTE_BUTTON0_PORT #define SL_BUTTON_BTN0_NUMBER RTE_BUTTON0_NUMBER -#define SL_BUTTON_BTN1_PIN RTE_BUTTON1_PIN -#define SL_BUTTON_BTN1_PORT RTE_BUTTON1_PORT +#define SL_BUTTON_BTN1_PIN RTE_BUTTON1_PIN +#define SL_BUTTON_BTN1_PORT RTE_BUTTON1_PORT #define SL_BUTTON_BTN1_NUMBER RTE_BUTTON1_NUMBER -#define SL_BUTTON_BTN1_PAD RTE_BUTTON1_PAD +#define SL_BUTTON_BTN1_PAD RTE_BUTTON1_PAD #endif // SL_SI91X_BUTTON_PIN_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_dma_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_dma_config.h new file mode 100644 index 0000000000..109df2599c --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_dma_config.h @@ -0,0 +1,52 @@ +/***************************************************************************/ /** + * @file + * @brief SL USART Config. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_DMA_CONFIG_H +#define SL_SI91X_DMA_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +#ifdef __cplusplus +extern "C" { +#endif + +// DMA instance 0 channel count <1-32> +// Default: 32 +#define SL_DMA0_CHANNEL_COUNT 32 + +// ULP DMA instance channel count <1-12> +// Default: 12 +#define SL_ULP_DMA_CHANNEL_COUNT 12 + +// <<< end of configuration section >>> + +#ifdef __cplusplus +} +#endif +#endif //SL_SI91X_DMA_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_led_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_led_config.h index 4f2737660c..e7eaab11a7 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_led_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_led_config.h @@ -1,5 +1,4 @@ -/***************************************************************************/ -/** +/***************************************************************************/ /** * @file RTE_led_config.h * @brief Led Driver Configuration ******************************************************************************* @@ -14,13 +13,13 @@ #define SL_SI91x_LED_COUNT 2 -#define SL_LED_LED0_PIN RTE_LED0_PIN -#define SL_LED_LED0_PORT RTE_LED0_PORT +#define SL_LED_LED0_PIN RTE_LED0_PIN +#define SL_LED_LED0_PORT RTE_LED0_PORT #define SL_LED_LED0_NUMBER RTE_LED0_NUMBER -#define SL_LED_LED1_PIN RTE_LED1_PIN -#define SL_LED_LED1_PORT RTE_LED1_PORT +#define SL_LED_LED1_PIN RTE_LED1_PIN +#define SL_LED_LED1_PORT RTE_LED1_PORT #define SL_LED_LED1_NUMBER RTE_LED1_NUMBER -#define SL_LED_LED1_PAD RTE_LED1_PAD +#define SL_LED_LED1_PAD RTE_LED1_PAD #endif // SL_SI91X_LED_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_stack_size_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_stack_size_config.h new file mode 100644 index 0000000000..c369cf7a7a --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_stack_size_config.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* @file sl_si91x_stack_size_config.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef __SL_SI91X_STACK_SIZE_CONFIG_H_ +#define __SL_SI91X_STACK_SIZE_CONFIG_H_ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory configuration + +// Stack size for the application. +// Default: 12288 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE +#define SL_STACK_SIZE 12288 +#endif + +// +// <<< end of configuration section >>> + +#endif // __SL_SI91X_STACK_SIZE_CONFIG_H_ diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_common_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_common_config.h new file mode 100644 index 0000000000..761d50ed93 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_common_config.h @@ -0,0 +1,84 @@ +/***************************************************************************/ /** + * @file sl_si91x_ulp_timer_common_config.h + * @brief ULP Timer common configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_ULP_TIMER_COMMON_CONFIG_H +#define SL_SI91X_ULP_TIMER_COMMON_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_ulp_timer.h" +/******************************************************************************/ +/******************** ADC Peripheral CommonConfiguration **********************/ + +// <<< Use Configuration Wizard in Context Menu >>> +// ULP Timer Clock Configuration + +// Clock Type +// Static (auto select) +// Dynamic +// Selection of the Timer CLK Type. +#define SL_ULP_TIMER_CLK_TYPE SL_ULP_TIMER_CLK_TYPE_STATIC + +// Sync to ULPSS PCLK +// Enable or disable sync to ULPSS pclock. +// Default: 0 +#define SL_ULP_TIMER_SYNC_TO_ULPSS_PCLK 0 + +// Wait for switching timer clock +// 1 : Enable waiting for switching timer clk & 0 : Skip waiting for switching timer clk. +// Default: 0 +#define SL_ULP_TIMER_SKIP_SWITCH_TIME 0 + +// clock source +// Ref clock +// 32KHZ_RO +// 32KHZ_RC +// 32KHZ_XTAL +// 32MHZ_RC (auto select) +// 20MHZ_RO +// Selection of the Clock source +#define SL_ULP_TIMER_CLK_INPUT_SOURCE ULP_TIMER_32MHZ_RC_CLK_SRC //default timer clock input source is ref clock + +// +// <<< end of configuration section >>> + +ulp_timer_clk_src_config_t sl_timer_clk_handle = { + .ulp_timer_clk_type = SL_ULP_TIMER_CLK_TYPE, + .ulp_timer_sync_to_ulpss_pclk = SL_ULP_TIMER_SYNC_TO_ULPSS_PCLK, + .ulp_timer_clk_input_src = SL_ULP_TIMER_CLK_INPUT_SOURCE, + .ulp_timer_skip_switch_time = SL_ULP_TIMER_SKIP_SWITCH_TIME, +}; + +#ifdef __cplusplus +} +#endif // SL_ULP_TIMER +#endif /* SL_SI91X_ULP_TIMER_COMMON_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_init_timer0_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_init_timer0_config.h new file mode 100644 index 0000000000..09d1badb50 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_init_timer0_config.h @@ -0,0 +1,67 @@ +/***************************************************************************/ /** + * @file sl_si91x_ulp_timer_init_timer0_config.h + * @brief ULP Timer timer0 configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H +#define SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_ulp_timer.h" +/******************************************************************************/ +/******************************* ULP-Timer clock Configuration **************************/ +// timer0 Configuration + +// Timer type +// Down Counter (auto select) +// 1 Micro-Sec +// 256-Micro-Sec +// Selection of the Timer type +#define SL_ULP_TIMER_TIMER0_TYPE ULP_TIMER_TYP_DEFAULT + +// Timer mode +// One-shot +// Periodic (auto select) +// Selection of the Timer mode +#define SL_ULP_TIMER_TIMER0_MODE ULP_TIMER_MODE_PERIODIC + +// Timer direction +// Down (auto select) +// Up +// Selection of the Timer direction +#define SL_ULP_TIMER_TIMER0_DIRECTION DOWN_COUNTER + +// End timer0 Configuration +/******************************************************************************/ +// <<< end of configuration section >>> + +#endif /* SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_inst_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_inst_config.h deleted file mode 100644 index e7882edb1c..0000000000 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_inst_config.h +++ /dev/null @@ -1,124 +0,0 @@ -/***************************************************************************/ /** - * @file sl_si91x_ulp_timer_inst_config.h - * @brief ULP Timer configuration file. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SI91X_ULP_TIMER_INSTANCE_CONFIG_H -#define SL_SI91X_ULP_TIMER_INSTANCE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Clock Configuration -#define SL_ULP_TIMER_CLK_TYPE_STATIC 1 -#define SL_ULP_TIMER_CLK_TYPE_DYNAMIC 0 - -// Clock Type -// Static (auto select) -// Dynamic -// Selection of the Timer CLK Type. -#define SL_ULP_TIMER_CLK_TYPE SL_ULP_TIMER_CLK_TYPE_STATIC - -// Sync to ULPSS PCLK -// Enable or disable sync to ULPSS pclock. -// Default: 0 -#define SL_ULP_TIMER_SYNC_TO_ULPSS_PCLK 0 - -// Wait for switching timer clock -// 1 : Enable waiting for switching timer clk & 0 : Skip waiting for -// switching timer clk. Default: 0 -#define SL_ULP_TIMER_SKIP_SWITCH_TIME 0 - -#define SL_ULP_TIMER_REF_CLK 0 -#define SL_ULP_TIMER_32KHZ_RO_CLK 1 -#define SL_ULP_TIMER_32KHZ_RC_CLK 2 -#define SL_ULP_TIMER_32KHZ_XTAL_CLK 3 -#define SL_ULP_TIMER_32MHZ_RC_CLK 4 -#define SL_ULP_TIMER_20MHZ_RO_CLK 5 -#define SL_ULP_TIMER_ULP_SOC_CLK 6 - -// clock source -// Ref clock -// 32KHZ_RO -// 32KHZ_RC -// 32KHZ_XTAL -// 32MHZ_RC (auto select) -// 20MHZ_RO -// Selection of the Clock source -#define SL_ULP_TIMER_CLK_INPUT_SOURCE \ - SL_ULP_TIMER_32MHZ_RC_CLK // default timer clock input source is ref clock - -// - -// ULP Timer Configuration - -#define SL_ULP_TIMER_TIMER0 0 -#define SL_ULP_TIMER_TIMER1 1 -#define SL_ULP_TIMER_TIMER2 2 -#define SL_ULP_TIMER_TIMER3 3 - -// Timer instance -// Timer 0 -// Timer 1 -// Timer 2 -// Timer 3 -// Selection of the Timer instance -#define SL_ULP_TIMER_DEFAULT SL_ULP_TIMER_INSTANCE - -#define SL_ULP_TIMER_TYP_DOWN_COUNTER 0 -#define SL_ULP_TIMER_TYP_1US 1 -#define SL_ULP_TIMER_TYP_256US 2 - -// Timer type -// Down Counter (auto select) -// 1 Micro-Sec -// 256-Micro-Sec -// Selection of the Timer type -#define SL_ULP_TIMER_TYP SL_ULP_TIMER_TYP_DOWN_COUNTER // default type is 1MS - -#define SL_ULP_TIMER_MODE_ONESHOT 0 -#define SL_ULP_TIMER_MODE_PERIODIC 1 - -// Timer mode -// One-shot -// Periodic (auto select) -// Selection of the Timer mode -#define SL_ULP_TIMER_MODE SL_ULP_TIMER_MODE_PERIODIC // default mode is periodic - -#define SL_ULP_DOWN_COUNTER 0 -#define SL_ULP_UP_COUNTER 1 -// Timer direction -// Down (auto select) -// Up -// Selection of the Timer direction -#define SL_ULP_TIMER_DIRECTION SL_ULP_DOWN_COUNTER - -// - -// <<< end of configuration section >>> - -#endif /* SL_SI91X_ULP_TIMER_INSTANCE_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_timer0_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_timer0_config.h deleted file mode 100644 index 988b9856b1..0000000000 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_timer_timer0_config.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************/ -/** - * @file sl_si91x_ulp_timer_inst_config.h - * @brief ULP Timer configuration file. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H -#define SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Clock Configuration -#define SL_ULP_TIMER_CLK_TYPE_STATIC 1 -#define SL_ULP_TIMER_CLK_TYPE_DYNAMIC 0 - -// Clock Type -// Static (auto select) -// Dynamic -// Selection of the Timer CLK Type. -#define SL_ULP_TIMER_CLK_TYPE SL_ULP_TIMER_CLK_TYPE_STATIC - -// Sync to ULPSS PCLK -// Enable or disable sync to ULPSS pclock. -// Default: 0 -#define SL_ULP_TIMER_SYNC_TO_ULPSS_PCLK 0 - -// Wait for switching timer clock -// 1 : Enable waiting for switching timer clk & 0 : Skip waiting for -// switching timer clk. Default: 0 -#define SL_ULP_TIMER_SKIP_SWITCH_TIME 0 - -#define SL_ULP_TIMER_REF_CLK 0 -#define SL_ULP_TIMER_32KHZ_RO_CLK 1 -#define SL_ULP_TIMER_32KHZ_RC_CLK 2 -#define SL_ULP_TIMER_32KHZ_XTAL_CLK 3 -#define SL_ULP_TIMER_32MHZ_RC_CLK 4 -#define SL_ULP_TIMER_20MHZ_RO_CLK 5 -#define SL_ULP_TIMER_ULP_SOC_CLK 6 - -// clock source -// Ref clock -// 32KHZ_RO -// 32KHZ_RC -// 32KHZ_XTAL -// 32MHZ_RC (auto select) -// 20MHZ_RO -// SOC_CLK -// Selection of the Clock source -#define SL_ULP_TIMER_CLK_INPUT_SOURCE \ - SL_ULP_TIMER_32MHZ_RC_CLK // default timer clock input source is ref clock - -// - -// ULP Timer Configuration - -#define SL_ULP_TIMER_TIMER0 0 -#define SL_ULP_TIMER_TIMER1 1 -#define SL_ULP_TIMER_TIMER2 2 -#define SL_ULP_TIMER_TIMER3 3 - -// Timer instance -// Timer 0 -// Timer 1 -// Timer 2 -// Timer 3 -// Selection of the Timer instance -#define SL_ULP_TIMER_DEFAULT SL_ULP_TIMER_TIMER0 - -#define SL_ULP_TIMER_TYP_DOWN_COUNTER 0 -#define SL_ULP_TIMER_TYP_1US 1 -#define SL_ULP_TIMER_TYP_256US 2 - -// Timer type -// Down Counter (auto select) -// 1 Micro-Sec -// 256-Micro-Sec -// Selection of the Timer type -#define SL_ULP_TIMER_TYP SL_ULP_TIMER_TYP_DOWN_COUNTER // default type is 1MS - -#define SL_ULP_TIMER_MODE_ONESHOT 0 -#define SL_ULP_TIMER_MODE_PERIODIC 1 - -// Timer mode -// One-shot -// Periodic (auto select) -// Selection of the Timer mode -#define SL_ULP_TIMER_MODE SL_ULP_TIMER_MODE_PERIODIC // default mode is periodic - -#define SL_ULP_DOWN_COUNTER 0 -#define SL_ULP_UP_COUNTER 1 -// Timer direction -// Down (auto select) -// Up -// Selection of the Timer direction -#define SL_ULP_TIMER_DIRECTION SL_ULP_DOWN_COUNTER - -// - -// <<< end of configuration section >>> - -#endif /* SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_common_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_common_config.h new file mode 100644 index 0000000000..921e7a507c --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_common_config.h @@ -0,0 +1,43 @@ +/***************************************************************************/ /** + * @file sl_si91x_ulp_uart_common_config.h + * @brief SL SI91X ULP UART Common Config. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_ULP_UART_COMMON_CONFIG_H +#define SL_SI91X_ULP_UART_COMMON_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// DMA Configuration + +// ULP UART DMA +// Default: 1 +#define SL_ULPUART_DMA_CONFIG_ENABLE 0 + +// +// <<< end of configuration section >>> +#endif // SL_SI91X_ULP_UART_COMMON_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_config.h new file mode 100644 index 0000000000..63ef4c9150 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_config.h @@ -0,0 +1,108 @@ +/***************************************************************************/ /** + * @file sl_si91x_ulp_uart_config.h + * @brief SL ULP UART Config. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_ULP_UART_CONFIG_H +#define SL_SI91X_ULP_UART_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_usart.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// ULP UART UC Configuration +// Enable: Peripheral configuration is taken straight from the configuration set in the universal configuration (UC). +// Disable: If the application demands it to be modified during runtime, use the sl_si91x_uart_set_configuration API to modify the peripheral configuration. +// Default: 1 +#define ULP_UART_UC 1 +#define ULPUART_MODULE 2 + +// UART Configuration +#define ENABLE 1 +#define DISABLE 0 + +#if (ULP_UART_UC) +// Baud Rate (Baud/Second) <300-7372800> +// Default: 115200 +#define SL_ULP_UART_BAUDRATE 115200 + +// Parity +// No Parity +// Even +// Odd +// Default: SL_USART_NO_PARITY +#define SL_ULP_UART_PARITY SL_USART_NO_PARITY + +// Stop Bits +// 1 +// 1.5 +// 2 +// Default: USART_STOP_BITS_1 +#define SL_ULP_UART_STOP_BITS SL_USART_STOP_BITS_1 + +// Data Width +// 5 +// 6 +// 7 +// 8 +// 9 +// Default: USART_DATA_BITS_8 +#define SL_ULP_UART_DATA_BITS SL_USART_DATA_BITS_8 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: USART_FLOW_CONTROL_NONE +#define SL_ULP_UART_FLOW_CONTROL_TYPE SL_USART_FLOW_CONTROL_NONE +#endif + +// ULP_UART Configuration +// + +#ifdef __cplusplus +} +#endif +// <<< end of configuration section >>> + +#if (ULP_UART_UC) +sl_si91x_usart_control_config_t ulp_uart_configuration = { .baudrate = SL_ULP_UART_BAUDRATE, + .mode = SL_USART_MODE_ASYNCHRONOUS, + .parity = SL_ULP_UART_PARITY, + .stopbits = SL_ULP_UART_STOP_BITS, + .hwflowcontrol = SL_ULP_UART_FLOW_CONTROL_TYPE, + .databits = SL_ULP_UART_DATA_BITS, + .usart_module = ULPUART_MODULE }; + +#endif //ULP_UART_UC +#endif //SL_SI91X_UART_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_sleeptimer_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_sleeptimer_config.h new file mode 100644 index 0000000000..8344ef5f11 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/sl_sleeptimer_config.h @@ -0,0 +1,82 @@ +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 +#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6 +#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// WTIMER +// TIMER +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals) +// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs. +// Default: 0 +#define SL_SLEEPTIMER_TIMER_INSTANCE 0 + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider (not applicable for WTIMER/TIMER) +// WTIMER/TIMER peripherals are always prescaled to 1024. +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>>