diff --git a/README.md b/README.md index e48cd86c..2555a5f8 100644 --- a/README.md +++ b/README.md @@ -128,34 +128,24 @@ The Zlib library is an optional. If CMake finds libz, OpenSTA can read Liberty, Verilog, SDF, SPF, and SPEF files compressed with gzip. CUDD is a binary decision diageram (BDD) package that is used to -improve conditional timing arc handling. OpenSTA does not require it -to be installed, but it improves constant propagation, power activity propagation -and spice netlist generation if it is installed. +improve conditional timing arc handling, constant propagation, power +activity propagation and spice netlist generation. CUDD is available -[here](https://www.davidkebo.com/source/cudd_versions/cudd-3.0.0.tar.gz) -or [here](https://sourceforge.net/projects/cudd-mirror/). +[here](https://github.com/davidkebo/cudd/blob/main/cudd_versions/cudd-3.0.0.tar.gz). -Use the CUDD_DIR option to set the install directory of the CUDD -library if it is not in one of the normal system install directories. +Unpack and build CUDD. ``` -cmake -DCUDD_DIR=$HOME/stax/cudd-3.0.0 .." -``` - -When building CUDD you may use the `--prefix ` option to `configure` to -install in a location other than the default (`/usr/local/lib`). -``` -cd $HOME/cudd-3.0.0 -mkdir $HOME/cudd -./configure --prefix $HOME/cudd +tar xvfz cudd-3.0.0.tar.gz +cd cudd-3.0.0 +./configure make -make install - -cd /build -cmake .. -DUSE_CUDD=ON -DCUDD_DIR=$HOME/cudd ``` +You can use the "configure --prefix" option and "make install" to install CUDD +in a different directory. + ### Installing with CMake Use the following commands to checkout the git repository and build the @@ -166,7 +156,7 @@ git clone https://github.com/parallaxsw/OpenSTA.git cd OpenSTA mkdir build cd build -cmake .. +cmake -DCUDD_DIR= ,. make ``` The default build type is release to compile optimized code. @@ -180,7 +170,7 @@ CMAKE_BUILD_TYPE DEBUG|RELEASE CMAKE_CXX_FLAGS - additional compiler flags TCL_LIBRARY - path to tcl library TCL_HEADER - path to tcl.h -CUDD - path to cudd installation +CUDD_DIR - path to cudd installation ZLIB_ROOT - path to zlib CMAKE_INSTALL_PREFIX ``` @@ -189,11 +179,7 @@ If `TCL_LIBRARY` is specified the CMake script will attempt to locate the header from the library path. The default install directory is `/usr/local`. -To install in a different directory with CMake use: - -``` -cmake .. -DCMAKE_INSTALL_PREFIX= -``` +To install in a different directory with CMake use the CMAKE_INSTALL_PREFIX option. If you make changes to `CMakeLists.txt` you may need to clean out existing CMake cached variable values by deleting all of the diff --git a/test/get_filter.tcl b/test/get_filter.tcl index e3269754..4bc0f896 100644 --- a/test/get_filter.tcl +++ b/test/get_filter.tcl @@ -1,3 +1,5 @@ +# Test get_* -filter + # Read in design and libraries read_liberty asap7_small.lib.gz read_verilog reg1_asap7.v diff --git a/test/liberty_arcs_one2one.ok b/test/liberty_arcs_one2one.ok deleted file mode 100644 index 22d298ef..00000000 --- a/test/liberty_arcs_one2one.ok +++ /dev/null @@ -1,220 +0,0 @@ -Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes. -Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes. -TEST 1: -Startpoint: a[0] (input port clocked by clk) -Endpoint: y[0] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[0] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_8_to_4) - 0.00 1.00 ^ y[0] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - -Startpoint: a[1] (input port clocked by clk) -Endpoint: y[1] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[1] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_8_to_4) - 0.00 1.00 ^ y[1] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - -Startpoint: a[2] (input port clocked by clk) -Endpoint: y[2] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[2] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_8_to_4) - 0.00 1.00 ^ y[2] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - -Startpoint: a[3] (input port clocked by clk) -Endpoint: y[3] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[3] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_8_to_4) - 0.00 1.00 ^ y[3] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - -TEST 2: -Startpoint: a[0] (input port clocked by clk) -Endpoint: y[0] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[0] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_4_to_8) - 0.00 1.00 ^ y[0] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - -Startpoint: a[1] (input port clocked by clk) -Endpoint: y[1] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[1] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_4_to_8) - 0.00 1.00 ^ y[1] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - -Startpoint: a[2] (input port clocked by clk) -Endpoint: y[2] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[2] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_4_to_8) - 0.00 1.00 ^ y[2] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - -Startpoint: a[3] (input port clocked by clk) -Endpoint: y[3] (output port clocked by clk) -Path Group: clk -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 v input external delay - 0.00 0.00 v a[3] (in) - 1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_4_to_8) - 0.00 1.00 ^ y[3] (out) - 1.00 data arrival time - - 0.00 0.00 clock clk (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 clock reconvergence pessimism - 0.00 0.00 output external delay - 0.00 data required time ---------------------------------------------------------- - 0.00 data required time - -1.00 data arrival time ---------------------------------------------------------- - -1.00 slack (VIOLATED) - - diff --git a/test/liberty_arcs_one2one.tcl b/test/liberty_arcs_one2one.tcl deleted file mode 100644 index 38bac255..00000000 --- a/test/liberty_arcs_one2one.tcl +++ /dev/null @@ -1,17 +0,0 @@ -read_liberty liberty_arcs_one2one.lib - -puts "TEST 1:" -read_verilog liberty_arcs_one2one_1.v -link_design liberty_arcs_one2one_1 -create_clock -name clk -period 0 -set_input_delay -clock clk 0 [all_inputs] -set_output_delay -clock clk 0 [all_outputs] -report_checks -group_count 5 - -puts "TEST 2:" -read_verilog liberty_arcs_one2one_2.v -link_design liberty_arcs_one2one_2 -create_clock -name clk -period 0 -set_input_delay -clock clk 0 [all_inputs] -set_output_delay -clock clk 0 [all_outputs] -report_checks -group_count 5 diff --git a/test/liberty_arcs_one2one.lib b/test/liberty_arcs_one2one_1.lib similarity index 71% rename from test/liberty_arcs_one2one.lib rename to test/liberty_arcs_one2one_1.lib index 7eebe107..4056f6b9 100644 --- a/test/liberty_arcs_one2one.lib +++ b/test/liberty_arcs_one2one_1.lib @@ -1,4 +1,4 @@ -library (one_to_one_mismatched_width) { +library (liberty_arcs_one2one_1) { delay_model : "table_lookup"; simulation : false; capacitive_load_unit (1,pF); @@ -47,34 +47,7 @@ library (one_to_one_mismatched_width) { direction : "output"; timing () { related_pin : "A"; - cell_rise (scalar) { - values ("1"); - } - cell_fall (scalar) { - values ("1"); - } - rise_transition (scalar) { - values ("1"); - } - fall_transition (scalar) { - values ("1"); - } - } - } - } - - cell (inv_4_to_8) { - bus (A) { - capacitance : 1; - bus_type : "bus4"; - direction : "input"; - } - bus (Y) { - function : "!A"; - bus_type : "bus8"; - direction : "output"; - timing () { - related_pin : "A"; + timing_sense : "negative_unate"; cell_rise (scalar) { values ("1"); } diff --git a/test/liberty_arcs_one2one_1.ok b/test/liberty_arcs_one2one_1.ok new file mode 100644 index 00000000..64c906ff --- /dev/null +++ b/test/liberty_arcs_one2one_1.ok @@ -0,0 +1,21 @@ +Warning: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes. +report_edges -from partial_wide_inv_cell/A[0] +A[0] -> Y[0] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -from partial_wide_inv_cell/A[1] +A[1] -> Y[1] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -from partial_wide_inv_cell/A[2] +A[2] -> Y[2] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -from partial_wide_inv_cell/A[3] +A[3] -> Y[3] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -from partial_wide_inv_cell/A[4] +report_edges -from partial_wide_inv_cell/A[5] +report_edges -from partial_wide_inv_cell/A[6] +report_edges -from partial_wide_inv_cell/A[7] diff --git a/test/liberty_arcs_one2one_1.tcl b/test/liberty_arcs_one2one_1.tcl new file mode 100644 index 00000000..6102782b --- /dev/null +++ b/test/liberty_arcs_one2one_1.tcl @@ -0,0 +1,11 @@ +# Test one-to-one functionality with mismatched widths where A width (8) is larger than Y width (4) +read_liberty liberty_arcs_one2one_1.lib +read_verilog liberty_arcs_one2one_1.v +link_design liberty_arcs_one2one_1 +create_clock -name clk -period 0 +set_input_delay -clock clk 0 [all_inputs] +set_output_delay -clock clk 0 [all_outputs] +for {set i 0} {$i < 8} {incr i} { + puts "report_edges -from partial_wide_inv_cell/A[$i]" + report_edges -from partial_wide_inv_cell/A[$i] +} diff --git a/test/liberty_arcs_one2one_2.lib b/test/liberty_arcs_one2one_2.lib new file mode 100644 index 00000000..b15b3b5e --- /dev/null +++ b/test/liberty_arcs_one2one_2.lib @@ -0,0 +1,66 @@ +library (liberty_arcs_one2one_2) { + delay_model : "table_lookup"; + simulation : false; + capacitive_load_unit (1,pF); + leakage_power_unit : "1pW"; + current_unit : "1A"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1v"; + library_features : "report_delay_calculation"; + input_threshold_pct_rise : 50; + input_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + output_threshold_pct_fall : 50; + slew_lower_threshold_pct_rise : 30; + slew_lower_threshold_pct_fall : 30; + slew_upper_threshold_pct_rise : 70; + slew_upper_threshold_pct_fall : 70; + slew_derate_from_library : 1.0; + nom_process : 1.0; + nom_temperature : 85.0; + nom_voltage : 0.75; + type (bus8) { + base_type : "array"; + data_type : "bit"; + bit_width : 8; + bit_from : 7; + bit_to : 0; + } + type (bus4) { + base_type : "array"; + data_type : "bit"; + bit_width : 4; + bit_from : 3; + bit_to : 0; + } + + cell (inv_4_to_8) { + bus (A) { + capacitance : 1; + bus_type : "bus4"; + direction : "input"; + } + bus (Y) { + function : "!A"; + bus_type : "bus8"; + direction : "output"; + timing () { + related_pin : "A"; + timing_sense : "negative_unate"; + cell_rise (scalar) { + values ("1"); + } + cell_fall (scalar) { + values ("1"); + } + rise_transition (scalar) { + values ("1"); + } + fall_transition (scalar) { + values ("1"); + } + } + } + } +} \ No newline at end of file diff --git a/test/liberty_arcs_one2one_2.ok b/test/liberty_arcs_one2one_2.ok new file mode 100644 index 00000000..879b8a74 --- /dev/null +++ b/test/liberty_arcs_one2one_2.ok @@ -0,0 +1,21 @@ +Warning: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes. +report_edges -to partial_wide_inv_cell/Y[0] +A[0] -> Y[0] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -to partial_wide_inv_cell/Y[1] +A[1] -> Y[1] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -to partial_wide_inv_cell/Y[2] +A[2] -> Y[2] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -to partial_wide_inv_cell/Y[3] +A[3] -> Y[3] combinational + ^ -> v 1.00:1.00 + v -> ^ 1.00:1.00 +report_edges -to partial_wide_inv_cell/Y[4] +report_edges -to partial_wide_inv_cell/Y[5] +report_edges -to partial_wide_inv_cell/Y[6] +report_edges -to partial_wide_inv_cell/Y[7] diff --git a/test/liberty_arcs_one2one_2.tcl b/test/liberty_arcs_one2one_2.tcl new file mode 100644 index 00000000..0bd423ad --- /dev/null +++ b/test/liberty_arcs_one2one_2.tcl @@ -0,0 +1,11 @@ +# Test one-to-one functionality with mismatched widths where Y width (8) is larger than A width (4) +read_liberty liberty_arcs_one2one_2.lib +read_verilog liberty_arcs_one2one_2.v +link_design liberty_arcs_one2one_2 +create_clock -name clk -period 0 +set_input_delay -clock clk 0 [all_inputs] +set_output_delay -clock clk 0 [all_outputs] +for {set i 0} {$i < 8} {incr i} { + puts "report_edges -to partial_wide_inv_cell/Y[$i]" + report_edges -to partial_wide_inv_cell/Y[$i] +} diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index b1b34981..984388cb 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -126,7 +126,8 @@ record_sta_tests { verilog_attribute collections extras - liberty_arcs_one2one + liberty_arcs_one2one_1 + liberty_arcs_one2one_2 get_filter get_property_flags } diff --git a/test/verilog_attribute.tcl b/test/verilog_attribute.tcl index 225a0187..f8b88722 100644 --- a/test/verilog_attribute.tcl +++ b/test/verilog_attribute.tcl @@ -1,3 +1,4 @@ +# Tests whether Verilog attributes can be parsed and retrieved correctly read_liberty ../examples/sky130hd_tt.lib read_verilog verilog_attribute.v link_design counter