update .pot files

source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot

@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: SpinalHDL \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"POT-Creation-Date: 2024-07-29 08:01+0000\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <[email protected]>\n"
@@ -100,16 +100,12 @@ msgstr ""
 msgid "``out(T)``"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
-msgid "``out UInt(7 bits)``"
-msgstr ""
-
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:70
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:69
 msgid "For all other data types, you may have to add some brackets around it. Sorry, this is a Scala limitation."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:71
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:77
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:70
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:76
 msgid "T"
 msgstr ""
 
@@ -125,70 +121,70 @@ msgstr ""
 msgid "``master(Bool())``"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:75
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:74
 msgid "This syntax is provided by the ``spinal.lib`` library (If you annotate your object with the ``slave`` syntax, then import ``spinal.lib.slave`` instead). T must extend ``IMasterSlave``. Some documentation is available :ref:`here <interface_example_apb>`. You may not actually need the brackets, so ``master T`` is fine as well."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:80
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:79
 msgid "There are some rules to follow with component interconnection:"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:83
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:82
 msgid "Components can only **read** output and input signals of child components."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:84
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:83
 msgid "Components can read their own output port values (unlike in VHDL)."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:87
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:86
 msgid "If for some reason you need to read signals from far away in the hierarchy (such as for debugging or temporal patches), you can do it by using the value returned by ``some.where.else.theSignal.pull()``"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:91
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:90
 msgid "Pruned signals"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:93
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:92
 msgid "SpinalHDL will generate all the named signals and their depedencies, while all the useless anonymous / zero width ones are removed from the RTL generation."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:96
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:95
 msgid "You can collect the list of all the removed ans useless signals via the ``printPruned`` and the ``printPrunedIo`` functions on the generated ``SpinalReport`` object:"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:126
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:125
 msgid "Parametrized Hardware (\"Generic\" in VHDL, \"Parameter\" in Verilog)"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:128
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:127
 msgid "If you want to parameterize your component, you can give parameters to the constructor of the component as follows:"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:146
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:145
 msgid "If you have several parameters, it is a good practice to give a specific configuration class as follows:"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:159
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:158
 msgid "You can add functions inside the config, along with requirements on the config attributes:"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:173
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:172
 msgid "This parametrization occurs entirely within the SpinalHDL code-generation during elaboration.  This generates non-generic HDL code. The methods described here do not use VHDL generics or Verilog parameters."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:177
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:176
 msgid "See also :ref:`Blackbox <blackbox>` for more information around support for that mechanism."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:182
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:181
 msgid "Synthesized component names"
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:184
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:183
 msgid "Within a module, each component has a name, called a \"partial name\". The \"full\" name is built by joining every component's parent name with \"_\", for example: ``io_clockDomain_reset``. You can use ``setName`` to replace this convention with a custom name. This is especially useful when interfacing with external components. The other methods are called ``getName``, ``setPartialName``, and ``getPartialName`` respectively."
 msgstr ""
 
-#: ../../SpinalHDL/Structuring/components_hierarchy.rst:190
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:189
 msgid "When synthesized, each module gets the name of the Scala class defining it. You can override this as well with ``setDefinitionName``."
 msgstr ""