Merge pull request #265 from mrcmry/fix-spelling-and-typo

Fix spelling, typos, space before {, //

examples/src/main/scala/spinaldoc/examples/advanced/JTAG.scala

@@ -27,7 +27,7 @@ class JtagFsm(jtag: Jtag) extends Area {
     val state = RegNext(stateNext) randBoot()
 
     stateNext := state.mux(
-    default    -> (jtag.tms ? RESET     | IDLE),           //RESET
+    default    -> (jtag.tms ? RESET     | IDLE),           // RESET
     IDLE       -> (jtag.tms ? DR_SELECT | IDLE),
     IR_SELECT  -> (jtag.tms ? RESET     | IR_CAPTURE),
     IR_CAPTURE -> (jtag.tms ? IR_EXIT1  | IR_SHIFT),

examples/src/main/scala/spinaldoc/examples/advanced/MemoryMappedUart.scala

@@ -14,7 +14,7 @@ object Apb3UartCtrl {
 // end object Apb3UartCtrl
 
 case class Apb3UartCtrl(uartCtrlConfig: UartCtrlGenerics, rxFifoDepth: Int) extends Component {
-  val io = new Bundle{
+  val io = new Bundle {
     val bus =  slave(Apb3(Apb3UartCtrl.getApb3Config))
     val uart = master(Uart())
   }

examples/src/main/scala/spinaldoc/examples/advanced/Slots.scala

@@ -5,39 +5,39 @@ import spinal.lib._
 import scala.language.postfixOps
 
 case class SlotsDemo(slotsCount : Int) extends Component {
-  //...
+  // ...
 
 
-  //Create the hardware for each slot
-  //Note each slot is an Area, not a Bundle
-  val slots = for(i <- 0 until slotsCount) yield new Area{
-    //Because the slot is an Area, we can define mix signal, registers, logic definitions
-    //Here are the registers for each slots
+  // Create the hardware for each slot
+  // Note each slot is an Area, not a Bundle
+  val slots = for(i <- 0 until slotsCount) yield new Area {
+    // Because the slot is an Area, we can define mix signal, registers, logic definitions
+    // Here are the registers for each slots
     val valid = RegInit(False)
     val address = Reg(UInt(8 bits))
-    val age = Reg(UInt(16 bits)) //Will count since how many cycles the slot is valid
+    val age = Reg(UInt(16 bits)) // Will count since how many cycles the slot is valid
 
-    //Here is some hardware behaviour for each slots
-    //Implement the age logic
-    when(valid){
+    // Here is some hardware behavior for each slots
+    // Implement the age logic
+    when(valid) {
       age := age + 1
     }
 
-    //removeIt will be used as a slot interface later on
+    // removeIt will be used as a slot interface later on
     val removeIt = False
-    when(removeIt){
+    when(removeIt) {
       valid := False
     }
   }
 
-  //Logic to allocate a new slot
-  val insert = new Area{
-    val cmd = Stream(UInt(8 bits)) //interface to issue requests
+  // Logic to allocate a new slot
+  val insert = new Area {
+    val cmd = Stream(UInt(8 bits)) // interface to issue requests
     val free = slots.map(!_.valid)
-    val freeOh = OHMasking.first(free) //Get the first free slot (on hot mask)
-    cmd.ready := free.orR //Only allow cmd when there is a free slot
-    when(cmd.fire){
-      //slots.onMask(freeOh)(code) will execute the code for each slot where the corresponding freeOh bit is set
+    val freeOh = OHMasking.first(free) // Get the first free slot (on hot mask)
+    cmd.ready := free.orR // Only allow cmd when there is a free slot
+    when(cmd.fire) {
+      // slots.onMask(freeOh)(code) will execute the code for each slot where the corresponding freeOh bit is set
       slots.onMask(freeOh){slot =>
         slot.valid := True
         slot.address := cmd.payload
@@ -46,21 +46,21 @@ case class SlotsDemo(slotsCount : Int) extends Component {
     }
   }
 
-  //Logic to remove the slots which match a given address (assuming there is not more than one match)
-  val remove = new Area{
-    val cmd = Flow(UInt(8 bits))//interface to issue requests
-    val oh = slots.map(s => s.valid && s.address === cmd.payload) //oh meaning "one hot"
-    when(cmd.fire){
+  // Logic to remove the slots which match a given address (assuming there is not more than one match)
+  val remove = new Area {
+    val cmd = Flow(UInt(8 bits)) // interface to issue requests
+    val oh = slots.map(s => s.valid && s.address === cmd.payload) // oh meaning "one hot"
+    when(cmd.fire) {
       slots.onMask(oh){ slot =>
         slot.removeIt := True
       }
     }
 
-    val reader = slots.reader(oh) //Create a facility to read the slots using "oh" as index
-    val age = reader(_.age) //Age of the slot which is selected by "oh"
+    val reader = slots.reader(oh) // Create a facility to read the slots using "oh" as index
+    val age = reader(_.age) // Age of the slot which is selected by "oh"
   }
 
-  //...
+  // ...
 }
 
 object SlotsDemo extends App {

examples/src/main/scala/spinaldoc/examples/advanced/Timer.scala

@@ -63,7 +63,7 @@ case class ApbTimer() extends Component {
     }
   }
 
-  //Prescaler is very similar to the timer, it mainly integrates a piece of auto reload logic.
+  // Prescaler is very similar to the timer, it mainly integrates a piece of auto reload logic.
   val prescaler = Prescaler(width = 16)
 
   val timerA = Timer(width = 32)

examples/src/main/scala/spinaldoc/examples/intermediate/Fractal.scala

@@ -28,32 +28,32 @@ case class PixelResult(g: PixelSolverGenerics) extends Bundle {
 // end bundles
 
 case class PixelSolver(g: PixelSolverGenerics) extends Component {
-  val io = new Bundle{
+  val io = new Bundle {
     val cmd = slave  Stream(PixelTask(g))
     val rsp = master Stream(PixelResult(g))
   }
 
   import g._
 
-  //Define states
+  // Define states
   val x, y = Reg(fixType) init(0)
   val iteration = Reg(iterationType) init(0)
 
-  //Do some shared calculation
+  // Do some shared calculation
   val xx = x*x
   val yy = y*y
   val xy = x*y
 
-  //Apply default assignment
+  // Apply default assignment
   io.cmd.ready := False
   io.rsp.valid := False
   io.rsp.iteration := iteration
 
   when(io.cmd.valid) {
-    //Is the mandelbrot iteration done ?
+    // Is the mandelbrot iteration done ?
     when(xx + yy >= 4.0 || iteration === iterationLimit) {
       io.rsp.valid := True
-      when(io.rsp.ready){
+      when(io.rsp.ready) {
         io.cmd.ready := True
         x := 0
         y := 0

examples/src/main/scala/spinaldoc/examples/intermediate/Uart.scala

@@ -41,14 +41,14 @@ object UartStopType extends SpinalEnum(binarySequential) {
 
 // begin internal bundles
 case class UartCtrlFrameConfig(g: UartCtrlGenerics) extends Bundle {
-  val dataLength = UInt(log2Up(g.dataWidthMax) bits) //Bit count = dataLength + 1
+  val dataLength = UInt(log2Up(g.dataWidthMax) bits) // Bit count = dataLength + 1
   val stop       = UartStopType()
   val parity     = UartParityType()
 }
 
 case class UartCtrlConfig(g: UartCtrlGenerics) extends Bundle {
   val frame        = UartCtrlFrameConfig(g)
-  val clockDivider = UInt(g.clockDividerWidth bits) //see UartCtrlGenerics.clockDividerWidth for calculation
+  val clockDivider = UInt(g.clockDividerWidth bits) // see UartCtrlGenerics.clockDividerWidth for calculation
 
   def setClockDivider(baudrate: Double, clkFrequency: HertzNumber = ClockDomain.current.frequency.getValue): Unit = {
     clockDivider := (clkFrequency.toDouble / baudrate / g.rxSamplePerBit).toInt
@@ -105,8 +105,8 @@ class UartCtrlTx(g : UartCtrlGenerics) extends Component {
 
     io.write.ready := False
     switch(state) {
-      is(IDLE){
-        when(io.write.valid && clockDivider.tick){
+      is(IDLE) {
+        when(io.write.valid && clockDivider.tick) {
           state := START
         }
       }
@@ -206,7 +206,7 @@ class UartCtrlRx(g : UartCtrlGenerics) extends Component {
     val parity  = Reg(Bool())
     val shifter = Reg(io.read.payload)
 
-    //Parity calculation
+    // Parity calculation
     when(bitTimer.tick) {
       parity := parity ^ sampler.value
     }
@@ -279,7 +279,7 @@ class UartCtrl(g: UartCtrlGenerics=UartCtrlGenerics()) extends Component {
   val tx = new UartCtrlTx(g)
   val rx = new UartCtrlRx(g)
 
-  //Clock divider used by RX and TX
+  // Clock divider used by RX and TX
   val clockDivider = new Area {
     val counter = Reg(UInt(g.clockDividerWidth bits)) init 0
     val tick = counter === 0
@@ -397,8 +397,8 @@ case class UartRx() extends Component {
   io.read <> uartCtrl.io.read
 }
 
-case class UartCtrlUsageExample() extends Component{
-  val io = new Bundle{
+case class UartCtrlUsageExample() extends Component {
+  val io = new Bundle {
     val uart = master(Uart())
     val switches = in Bits(8 bits)
     val leds = out Bits(8 bits)
@@ -407,15 +407,15 @@ case class UartCtrlUsageExample() extends Component{
   val uartCtrl = new UartCtrl()
   // set config manually to show that this is still OK
   uartCtrl.io.config.setClockDivider(921600)
-  uartCtrl.io.config.frame.dataLength := 7  //8 bits
+  uartCtrl.io.config.frame.dataLength := 7  // 8 bits
   uartCtrl.io.config.frame.parity := UartParityType.NONE
   uartCtrl.io.config.frame.stop := UartStopType.ONE
   uartCtrl.io.uart <> io.uart
 
-  //Assign io.led with a register loaded each time a byte is received
+  // Assign io.led with a register loaded each time a byte is received
   io.leds := uartCtrl.io.read.toReg()
 
-  //Write the value of switch on the uart each 2000 cycles
+  // Write the value of switch on the uart each 2000 cycles
   val write = Stream(Bits(8 bits))
   write.valid := CounterFreeRun(2000).willOverflow
   write.payload := io.switches
@@ -431,7 +431,7 @@ object UartCtrlUsageExample extends App {
 
 case class UartQueued() extends Component {
   val g = UartCtrlGenerics()
-  val io = new Bundle{
+  val io = new Bundle {
     val uart = master(Uart())
     val uartConfig = in(UartCtrlConfig(g))
     val rx = master(Stream(Bits(8 bit)))
@@ -458,7 +458,7 @@ case class UartQueued() extends Component {
 }
 
 case class UartWithHeader() extends Component {
-  val io = new Bundle{
+  val io = new Bundle {
     val uart = master(Uart())
     val switches = in Bits(8 bits)
     val leds = out Bits(8 bits)
@@ -474,7 +474,7 @@ case class UartWithHeader() extends Component {
   )
   io.uart <> uartCtrl.io.uart
 
-  //Assign io.led with a register loaded each time a byte is received
+  // Assign io.led with a register loaded each time a byte is received
   io.leds := uartCtrl.io.read.toReg()
 
   // start with header

examples/src/main/scala/spinaldoc/examples/intermediate/VGA.scala

@@ -111,19 +111,19 @@ case class VgaCtrl(rgbConfig: RgbConfig, timingsWidth: Int = 12) extends Compone
   io.vga.colorEn := colorEn
   io.vga.color := io.pixels.payload
   // end VgaCtrl connections
-  def feedWith(that : Stream[Fragment[Rgb]]): Unit ={
+  def feedWith(that : Stream[Fragment[Rgb]]): Unit = {
     io.pixels << that.toStreamOfFragment
 
     val error = RegInit(False)
-    when(io.error){
+    when(io.error) {
       error := True
     }
-    when(that.isLast){
+    when(that.isLast) {
       error := False
     }
 
     io.softReset := error
-    when(error){
+    when(error) {
       that.ready := True
     }
   }

examples/src/main/scala/spinaldoc/examples/simple/CarryAdder.scala

@@ -4,22 +4,22 @@ import spinal.core._
 
 import scala.language.postfixOps
 
-case class CarryAdder(size : Int) extends Component{
+case class CarryAdder(size : Int) extends Component {
   val io = new Bundle {
     val a = in UInt(size bits)
     val b = in UInt(size bits)
-    val result = out UInt(size bits)      //result = a + b
+    val result = out UInt(size bits)  // result = a + b
   }
 
-  var c = False                   //Carry, like a VHDL variable
+  var c = False   // Carry, like a VHDL variable
   for (i <- 0 until size) {
-    //Create some intermediate value in the loop scope.
+    // Create some intermediate value in the loop scope.
     val a = io.a(i)
     val b = io.b(i)
 
-    //The carry adder's asynchronous logic
+    // The carry adder's asynchronous logic
     io.result(i) := a ^ b ^ c
-    c \= (a & b) | (a & c) | (b & c);    //variable assignment
+    c \= (a & b) | (a & c) | (b & c); // variable assignment
   }
 }
 

examples/src/main/scala/spinaldoc/examples/simple/PLL.scala

@@ -28,23 +28,23 @@ case class TopLevel() extends Component {
     val pll = new PLL
     pll.io.clkIn := io.clk100Mhz
 
-    //Create a new clock domain named 'core'
+    // Create a new clock domain named 'core'
     val coreClockDomain = ClockDomain.internal(
       name = "core",
       frequency = FixedFrequency(200 MHz)  // This frequency specification can be used
     )                                      // by coreClockDomain users to do some calculations
 
-    //Drive clock and reset signals of the coreClockDomain previously created
+    // Drive clock and reset signals of the coreClockDomain previously created
     coreClockDomain.clock := pll.io.clkOut
     coreClockDomain.reset := ResetCtrl.asyncAssertSyncDeassert(
       input = io.aReset || ! pll.io.isLocked,
       clockDomain = coreClockDomain
     )
   }
 
-  //Create a ClockingArea which will be under the effect of the clkCtrl.coreClockDomain
+  // Create a ClockingArea which will be under the effect of the clkCtrl.coreClockDomain
   val core = new ClockingArea(clkCtrl.coreClockDomain) {
-    //Do your stuff which use coreClockDomain here
+    // Do your stuff which use coreClockDomain here
     val counter = Reg(UInt(4 bits)) init 0
     counter := counter + 1
     io.result := counter

examples/src/main/scala/spinaldoc/examples/simple/RgbToGray.scala

@@ -6,7 +6,7 @@ import spinal.lib.CounterFreeRun
 import scala.language.postfixOps
 
 case class RgbToGray() extends Component {
-  val io = new Bundle{
+  val io = new Bundle {
     val clear = in Bool()
     val r,g,b = in UInt(8 bits)
 
@@ -28,7 +28,7 @@ case class RgbToGray() extends Component {
   io.wr := True
   io.data := gray
 
-  when(io.clear){
+  when(io.clear) {
     gray := 0
     address.clear()
     io.wr := False

examples/src/main/scala/spinaldoc/libraries/sim/DualSimExample.scala

@@ -4,7 +4,7 @@ import spinal.core._
 import spinal.core.sim._
 import spinal.lib.misc.test.DualSimTracer
 
-class Toplevel extends Component{
+class Toplevel extends Component {
   val counter = out(Reg(UInt(16 bits))) init(0)
   counter := counter + 1
 }
@@ -14,15 +14,15 @@ object Example extends App {
 
   DualSimTracer(compiled, window = 10000, seed = 42){dut=>
     dut.clockDomain.forkStimulus(10)
-    dut.clockDomain.onSamplings{
+    dut.clockDomain.onSamplings {
       val value = dut.counter.toInt
 
-      if(value % 0x1000 == 0){
+      if(value % 0x1000 == 0) {
         println(f"Value=0x$value%x at ${simTime()}")
       }
 
       // Throw a simulation failure after 64K cycles
-      if(value == 0xFFFF){
+      if(value == 0xFFFF) {
         simFailure()
       }
     }

source/SpinalHDL/Data types/Int.rst

@@ -139,7 +139,7 @@ Logic
 
 .. note::
 
-   Notice the difference in behaviour between ``x >> 2`` (result 2 bit narrower than x) and ``x >> U(2)`` (keeping width)
+   Notice the difference in behavior between ``x >> 2`` (result 2 bit narrower than x) and ``x >> U(2)`` (keeping width)
    due to the Scala type of :code:`y`.
 
    In the first case "2" is an ``Int`` (which can be seen as an