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source/locale/es/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po

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+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: Automatically generated\n"
+"Language-Team: none\n"
+"Language: es\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:2
+msgid "Parametrization"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:4
+msgid "There are multiple aspects to parametrization :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:6
+msgid "Providing and the management of, elaboration time parameters provided to SpinalHDL during elaboration of the design"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:8
+msgid "Using the parameter data to allow the designer to perform any kind of hardware construction, configuration and interconnection task needed in the design.  Such as optional component generation within the hardware design."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:13
+msgid "Parallels exist with the aims of HDL features such as Verilog module parameters and VHDL generics.  SpinalHDL brings a far richer and more powerful set of capabilities into this area with the additional protection of Scala type safety and SpinalHDL built in HDL design rule checking."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:19
+msgid "The SpinalHDL mechanisms for parameterization of components is not built on top of any native HDL mechanism and so is not impeded by HDL language level/version support or restrictions about what can be achieved in hand written HDL."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:24
+msgid "For readers looking to interoperate with parameterized Verilog or genericized VHDL using SpinalHDL, please see the section on :ref:`BlackBox <BlackBox>` IP for those scenarios your project requires."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:31
+msgid "Elaboration time parameters"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:33
+msgid "You can use the whole Scala syntax to provide elaboration time parameters."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:35
+msgid "The whole syntax means you have the entire power and feature set of the Scala language at your disposal to solve parameterization requirements for your project at the level of complexity you choose."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:39
+msgid "SpinalHDL does not place any opinionated restrictions on how to achieve your parameterization goals.  As such there are many Scala design patterns and a few SpinalHDL helpers that can be used to manage parameters that are suited to different parameter management scenarios."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:44
+msgid "Here are some examples and ideas of the possibilities:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:46
+msgid "Hardwired code and constants (not strictly parameter management at all but serves to hilight the most basic mechanism, a code change, not a parameter data change)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:49
+msgid "Constant values provided from a companion object that are static constants in Scala."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:51
+msgid "Values provided to Scala class constructor, often a ``case class`` that causes Scala to capture those constructor argument values as constants."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:53
+msgid "Regular Scala flow-control syntax, not limited to but including conditionals, looping, lambdas/monads, everything."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:55
+msgid "Config class pattern (examples exist in library items such as UartCtrlConfig_, SpiMasterCtrlConfig)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:57
+msgid "Project defined 'Plugin' pattern (examples exist in the VexRiscV_ project to configure the feature set the resulting CPU IP core is built with)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:59
+msgid "Values and information loaded from a file or network based source, using standard Scala/JVM libraries and APIs."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:61
+msgid "`any mechanism you can create`"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:63
+msgid "All of the mechanisms result in a change in resulting elaborated HDL output."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:65
+msgid "This could vary from a single constant value change all the way through to describing the entire bus and interconnection architecture of an entire SoC all without leaving the Scala programming paradigm."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:70
+msgid "Here is an example of class parameters"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:84
+msgid "You can also use global variable defined in Scala objects (companion object pattern)."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:87
+msgid "A :ref:`ScopeProperty <scopeproperty>` can also be used for configuration."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:90
+msgid "Optional hardware"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:92
+msgid "So here there is more possibilities."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:96
+msgid "For optional signal :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:106
+msgid "The ``generate`` method is a mechanism to evaluate the expression that follows for an optional value.  If the predicate is true, generate will evaluate the given expression and return the result, otherwise it returns null."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:111
+msgid "This may be used in cases to help parameterize the SpinalHDL hardware description using an elaboration-time conditional expression.  Causing HDL constructs to be emitted or not-emitted in the resulting HDL. The generate method can be seen as SpinalHDL syntatic sugar reducing language clutter."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:116
+msgid "Project SpinalHDL code referencing ``mySignal`` would need to ensure it handles the possiblity of null gracefully.  This is usually not a problem as those parts of the design can also be omitted dependant on the ``flag`` value.  Thus the feature of parameterizing this component is demonstrated."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:122
+msgid "You can do the same in Bundle."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:124
+msgid "Note that you can also use scala Option."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:126
+msgid "If you want to disable the generation of a chunk of hardware :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:136
+msgid "You can also use scala for loops :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:146
+msgid "So, you can extends those scala usages at elaboration time as much as you want, including using the whole scala collections (List, Set, Map, ...) to build some data model and then converting them into hardware in a procedural way (ex iterating over those list elements)."
+msgstr ""