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conv33_naive_compute.json
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{"top":"global.conv33_naive_compute",
"namespaces":{
"global":{
"modules":{
"buf_inst_ub":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["reset","BitIn"],
["input_write",["Array",1,["Array",16,"BitIn"]]],
["output_read",["Array",9,["Array",16,"Bit"]]]
]],
"instances":{
"d_reg__U10":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U11":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U12":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U13":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U8":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U9":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"ub_buf_inst_input_10_to_buf_inst_output_3":{
"genref":"cwlib.Mem",
"genargs":{"config":["Json",null], "has_flush":["Bool",true], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "num_input":["Int",1], "num_output":["Int",2], "width":["Int",16]},
"modargs":{"mode":["String","lake"]}
},
"ub_buf_inst_input_10_to_buf_inst_output_3_clk_en_const":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
}
},
"connections":[
["self.clk","d_reg__U10.clk"],
["ub_buf_inst_input_10_to_buf_inst_output_3.data_out_1","d_reg__U10.in"],
["d_reg__U11.in","d_reg__U10.out"],
["self.output_read.4","d_reg__U10.out"],
["self.clk","d_reg__U11.clk"],
["self.output_read.3","d_reg__U11.out"],
["self.clk","d_reg__U12.clk"],
["ub_buf_inst_input_10_to_buf_inst_output_3.data_out_0","d_reg__U12.in"],
["d_reg__U13.in","d_reg__U12.out"],
["self.output_read.1","d_reg__U12.out"],
["self.clk","d_reg__U13.clk"],
["self.output_read.0","d_reg__U13.out"],
["self.clk","d_reg__U8.clk"],
["self.input_write.0","d_reg__U8.in"],
["d_reg__U9.in","d_reg__U8.out"],
["self.output_read.7","d_reg__U8.out"],
["self.clk","d_reg__U9.clk"],
["self.output_read.6","d_reg__U9.out"],
["ub_buf_inst_input_10_to_buf_inst_output_3.clk","self.clk"],
["self.output_read.8","self.input_write.0"],
["ub_buf_inst_input_10_to_buf_inst_output_3.data_in_0","self.input_write.0"],
["ub_buf_inst_input_10_to_buf_inst_output_3.data_out_0","self.output_read.2"],
["ub_buf_inst_input_10_to_buf_inst_output_3.data_out_1","self.output_read.5"],
["ub_buf_inst_input_10_to_buf_inst_output_3.flush","self.reset"],
["ub_buf_inst_input_10_to_buf_inst_output_3_clk_en_const.out","ub_buf_inst_input_10_to_buf_inst_output_3.clk_en"]
]
},
"conv33_naive_compute":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["reset","BitIn"],
["in_inst_input_read_en","Bit"],
["in_inst_input_read",["Array",1,["Array",16,"BitIn"]]],
["out_inst_output_write_valid","Bit"],
["out_inst_output_write",["Array",1,["Array",16,"Bit"]]]
]],
"instances":{
"_U14":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"buf_inst":{
"modref":"global.buf_inst_ub"
},
"input":{
"modref":"global.cu_input"
},
"output":{
"modref":"global.cu_output"
}
},
"connections":[
["self.clk","_U14.clk"],
["self.in_inst_input_read.0","_U14.in"],
["self.clk","buf_inst.clk"],
["input.buf_inst_input_write","buf_inst.input_write"],
["output.buf_inst_output_read","buf_inst.output_read"],
["self.reset","buf_inst.reset"],
["self.clk","input.clk"],
["self.in_inst_input_read.0","input.in_inst_input_read.0"],
["self.clk","output.clk"],
["self.out_inst_output_write","output.out_inst_output_write"]
]
},
"cu_input":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["in_inst_input_read",["Array",1,["Array",16,"BitIn"]]],
["buf_inst_input_write",["Array",1,["Array",16,"Bit"]]]
]],
"connections":[
["self.in_inst_input_read.0","self.buf_inst_input_write.0"]
]
},
"cu_output":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["buf_inst_output_read",["Array",9,["Array",16,"BitIn"]]],
["out_inst_output_write",["Array",1,["Array",16,"Bit"]]]
]],
"instances":{
"add_all__U0":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U1":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U2":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U3":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U4":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U5":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U6":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U7":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
}
},
"connections":[
["self.buf_inst_output_read.0","add_all__U0.in0"],
["self.buf_inst_output_read.1","add_all__U0.in1"],
["add_all__U1.in0","add_all__U0.out"],
["self.buf_inst_output_read.2","add_all__U1.in1"],
["add_all__U2.in0","add_all__U1.out"],
["self.buf_inst_output_read.3","add_all__U2.in1"],
["add_all__U3.in0","add_all__U2.out"],
["self.buf_inst_output_read.4","add_all__U3.in1"],
["add_all__U4.in0","add_all__U3.out"],
["self.buf_inst_output_read.5","add_all__U4.in1"],
["add_all__U5.in0","add_all__U4.out"],
["self.buf_inst_output_read.6","add_all__U5.in1"],
["add_all__U6.in0","add_all__U5.out"],
["self.buf_inst_output_read.7","add_all__U6.in1"],
["add_all__U7.in0","add_all__U6.out"],
["self.buf_inst_output_read.8","add_all__U7.in1"],
["self.out_inst_output_write.0","add_all__U7.out"]
]
}
},
"generators":{
"delay_tile":{
"typegen":"global.delay_tile_TG",
"genparams":{"delay":"Int"}
},
"raw_dual_port_sram_tile":{
"typegen":"global.raw_dual_port_sram_TG",
"genparams":{"depth":"Int"}
},
"raw_quad_port_memtile":{
"typegen":"global.raw_quad_port_memtile_TG",
"genparams":{"depth":"Int"}
},
"tahoe":{
"typegen":"global.tahoe_TG",
"genparams":{"depth":"Int"}
}
},
"typegens":{
"delay_tile_TG":[{"delay":"Int"},"implicit"],
"raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"],
"raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"],
"tahoe_TG":[{"depth":"Int"},"implicit"]
}
}
}
}