1.13.0

New Features

• Implement Verilog Preprocessor. (#41, #59)
• Drop support for Python v3.4 (#61)
• Implement better source reference tracking for property assignments.
• Refactored source reference infrastructure.

Bug Fixes

• Fix missing inferred address placement of registers inside mem. (#52)
• Misc error handling bugs/quirks.

1.12.0

New Features

• Add include_native and include_udp options to Node.list_properties(). (#45)
• Add RDLCompiler.list_udps(). (#45)
• Add Node.owning_addrmap property.
• Add ability to use parent operators in Node.find_by_path(). (Related to #48)

Bug Fixes

• Fix validation bug when assigning a signal to the reset value. (#44)
• Fix interaction of swwe and swwel properties with sw property. (#43)
• Fix propagation of boolean type in UDP default. (#45)
• Make littleendian and bigendian properties logically exclusive.
• Add hierarchy separator between parent operators when getting relative path. (#48)
• Fix Component.get_scope_path() to return None if scope is not known.

1.11.0

New Features

• ⚡ Performance update! ⚡
  • Implemented parse accelerator extension using speedy-antlr-tool
  • 5x-10x performance improvement of compile phase.
• Update lexer/parser to use latest Antlr 4.8 runtime.

Bug Fixes

• Fix grammar to allow comment on last line of file. (#39)
• Add missing validation check for meaningless combinations of singlepulse and onwrite properties. (#40)

1.10.0

New Features

• Add perl_safe_opcodes compiler flag to allow user to override. Added more default opcodes (#37).

1.9.0

New Features

• Add extended type name generation based on dynamic property assignments (#29).
• Pull forward more utilities to the Node api: type_name, orig_type_name, external

Bug Fixes

• Fix missing warning check for implicit array stride.
• Fix type cast issue when assigning properties (#35)
• Fix error hint underline if snippet contains tabs. (#36)
• Fix property alias assignments in some counter properties: threshold & incrthreshold, saturate & incrsaturate.

1.8.0

New Features

• Implement RDLFormatCode processing for name properties
• Add RDL expression evaluation helper function: RDLCompiler.eval()
• Add Node.get_rel_path() function to compute relative path strings between nodes.
• Add signal/field reference width validation checks.
• Automatically remove common indentation from desc properties.
  • Can be disabled if needed via compiler setting

Bug Fixes

• Fix assignment type-cast when using top-level parameter override
• Fix missing address collision check for insufficient array stride (#32)
• Allow references to signals in several field properties (#31).

1.7.2

Bug Fixes

• Fix boolean validation of donttest and dontcompare properties (#27)

1.7.1

Bug Fixes

• Fix singlepulse property validation (#23)

1.7.0

New Features

• Add is_msb0_order marker to Reg component
• Add array index zero/clear methods to Node
• Add raw_absolute_address to Node

Bug Fixes

• Fix enum entry ordering

1.6.0

New Features

• Expose markdown processor class to user when generating HTML descriptions
• Semantic checks for virtual registers
• Additional semantic checks for properties: dontcompare, donttest, onread, onwrite, singlepulse, we, wel, encode
• Add debug and info message severities. (#22)

Bug Fixes

• Fix derivation of default memwidth
• Fix a few missed scenarios in FieldNode.implements_storage meta-property