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I would like to write a bit of Verilog that prints out the names of the modules that were kept after hierarchical synthesis.
The code below lists both the modules as well as their instantiations for MegaBoom:
set db [ord::get_db]
set chip [$db getChip]
set block [$chip getBlock]
set modules [$block getModules]
# get set of names of masters of modulesset masters [dict create]
foreach module $modules {
#set master [$module getMaster]
dict set masters [$module getName] 1
}
# get list of names sorted to make it predictableset masters [dict keys $masters]
set masters [lsort$masters]
set f [open [file join $::env(WORK_HOME)"kept.bzl"] "w"]
puts$f"KEPT_MODULES = \["foreach master $masters {
puts$f"\"$master\","
}
puts$f"\]"close$f
We can see these names in the Verilog code, the module as well as instances of it, whereas I expected getModules would have returned only the modules, not the instances.
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I would like to write a bit of Verilog that prints out the names of the modules that were kept after hierarchical synthesis.
The code below lists both the modules as well as their instantiations for MegaBoom:
Outputs:
We can see these names in the Verilog code, the module as well as instances of it, whereas I expected getModules would have returned only the modules, not the instances.
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