diff --git a/ol2/tt_top/build.py b/ol2/tt_top/build.py
index 03bde8d..2128a7d 100755
--- a/ol2/tt_top/build.py
+++ b/ol2/tt_top/build.py
@@ -166,6 +166,8 @@ class TopFlow(SequentialFlow):
 			"../../rtl/tt_user_module.v",
 		],
 
+		"VERILOG_POWER_DEFINE": "USE_POWER_PINS",
+
 		# Macros
 		"EXTRA_VERILOG_MODELS": macros_models,
 		"MACROS": macros,
diff --git a/ol2/tt_top/user_project_wrapper.v b/ol2/tt_top/user_project_wrapper.v
index 13f2a83..5e72eb4 100644
--- a/ol2/tt_top/user_project_wrapper.v
+++ b/ol2/tt_top/user_project_wrapper.v
@@ -89,6 +89,10 @@ module user_project_wrapper (
 
 	// Main core
 	tt_top top_I (
+`ifdef USE_POWER_PINS
+		.VPWR        (vccd1),
+		.VGND        (vssd1),
+`endif
 		.io_ana      (io_ana),
 		.io_in       (io_in),
 		.io_out      (io_out),
diff --git a/rtl/tt_top.v b/rtl/tt_top.v
index 481d7e4..a3877a9 100644
--- a/rtl/tt_top.v
+++ b/rtl/tt_top.v
@@ -19,6 +19,12 @@ module tt_top #(
 	parameter integer N_O  = `TT_N_O,
 	parameter integer N_I  = `TT_N_I
 )(
+	// Power
+`ifdef USE_POWER_PINS
+	input wire VPWR,
+	input wire VGND,
+`endif
+
 	// IOs
 	inout  wire [N_PADS-1:0] io_ana,
 	input  wire [N_PADS-1:0] io_in,
@@ -143,6 +149,10 @@ module tt_top #(
 	)
 `endif
 	ctrl_I (
+`ifdef USE_POWER_PINS
+		.VPWR           (VPWR),
+		.VGND           (VGND),
+`endif
 		.pad_uio_in     (pad_uio_in),
 		.pad_uio_out    (pad_uio_out),
 		.pad_uio_oe_n   (pad_uio_oe_n),
@@ -204,6 +214,10 @@ module tt_top #(
 			)
 `endif
 			mux_I (
+`ifdef USE_POWER_PINS
+				.VPWR      (VPWR),
+				.VGND      (VGND),
+`endif
 				.um_ow     (l_um_ow),
 				.um_iw     (l_um_iw),
 				.um_ena    (l_um_ena),
@@ -234,6 +248,10 @@ module tt_top #(
 					.N_O   (N_O),
 					.N_IO  (N_IO)
 				) um_I (
+`ifdef USE_POWER_PINS
+					.VPWR   (VPWR),
+					.VGND   (VGND),
+`endif
 					.ana    (l_um_ana[j*N_A+:N_A]),
 					.ow     (l_um_ow[j*U_OW+:U_OW]),
 					.iw     (l_um_iw[j*U_IW+:U_IW]),
diff --git a/rtl/tt_user_module.v.mak b/rtl/tt_user_module.v.mak
index a3a96a3..9c9bd6f 100644
--- a/rtl/tt_user_module.v.mak
+++ b/rtl/tt_user_module.v.mak
@@ -27,6 +27,10 @@ module tt_user_module #(
 	parameter integer N_OW = N_O + N_IO * 2 ,
 	parameter integer N_IW = N_I + N_IO
 )(
+`ifdef USE_POWER_PINS
+	input  wire VPWR,
+	input  wire VGND,
+`endif
 	inout  wire   [N_A-1:0] ana,
 	output wire  [N_OW-1:0] ow,
 	input  wire  [N_IW-1:0] iw,
@@ -50,7 +54,14 @@ module tt_user_module #(
 % for (mux_id, blk_id), mod in grid.items():
 		if ((MUX_ID == ${mux_id}) && (BLK_ID == ${blk_id}))
 		begin : block_${mux_id}_${blk_id}
+`ifdef USE_POWER_PINS
+			wire l_vpwr;
+`endif
 			tt_um_${mod.name} tt_um_I (
+`ifdef USE_POWER_PINS
+				.VPWR    (l_vpwr),
+				.VGND    (VGND),
+`endif
 % if mod.analog:
 				.ua      (ana),
 % endif
@@ -65,8 +76,17 @@ module tt_user_module #(
 			);
 % if mod.pg_vdd:
 			tt_pg_vdd_${mod.height} tt_pg_vdd_I (
+`ifdef USE_POWER_PINS
+				.GPWR    (l_vpwr),
+				.VPWR    (VPWR),
+				.VGND    (VGND),
+`endif
 				.ctrl    (pg_vdd)
 			);
+% else:
+`ifdef USE_POWER_PINS
+			assign l_vpwr = VPWR;
+`endif
 % endif
 		end
 % endfor