diff --git a/ol2/tt_top/base.sdc b/ol2/tt_top/base.sdc
new file mode 100644
index 0000000..8a76a40
--- /dev/null
+++ b/ol2/tt_top/base.sdc
@@ -0,0 +1,81 @@
+#
+# TT top level STA
+#
+
+
+# Segment signals
+# ---------------
+
+# Port: Control inputs
+set all_ctl      [ get_ports { "io_in[36]" "io_in[34]" "io_in[32]" }  ]
+
+# Port: User IO
+set all_pads_in  [list]
+set all_pads_out [list]
+
+	# UIO
+for {set i 0} {$i < 8} {incr i} {
+	set j [expr $i+24]
+	lappend all_pads_in  [ get_ports "io_in[$j]" ]
+	lappend all_pads_out [ get_ports "io_out[$j]" ]
+	lappend all_pads_out [ get_ports "io_oeb[$j]" ]
+}
+
+	# UO
+for {set i 0} {$i < 8} {incr i} {
+	set j [expr $i+16]
+	lappend all_pads_out [ get_ports "io_out[$j]" ]
+}
+
+	# UI
+for {set i 0} {$i < 10} {incr i} {
+	set j [expr $i+6]
+	lappend all_pads_in  [ get_ports "io_in[$j]" ]
+}
+
+# Pins:
+set all_pins_um_ctl [ get_pins {*/um_ena*} ]
+set all_pins_um_iw  [ get_pins {*/um_iw*}  ]
+set all_pins_um_ow  [ get_pins {*/um_ow*}  ]
+
+
+# Inputs
+# ------
+
+# All `io_in` come from strong buffer in the gpio_control_block
+set_driving_cell -lib_cell sky130_fd_sc_hd__buf_16 -pin X [all_inputs]
+
+
+# Loads
+# -----
+
+# All `io_out` & `io_oeb` go to gpio_control_block and have a bit
+# of capacitance (estimates from lib and gpio_control_block.spef)
+set_load 0.03 [all_outputs]
+
+
+# Clock
+# -----
+
+# Only clock is the ctrl_sel_inc
+# The internal sub-divided clocks are checked internally when
+# hardening tt_ctrl itself so don't bother here
+create_clock -name ctrl_inc -period 10 [ get_ports "io_in[34]" ]
+
+
+# Max delays
+# ----------
+
+# No artifical delays
+set_input_delay  0 [all_inputs]
+set_output_delay 0 [all_outputs]
+
+# Control delays
+set_max_delay -from $all_ctl -to $all_pads_out    10.0
+
+set_max_delay -from $all_ctl -to $all_pins_um_ctl 10.0
+set_max_delay -from $all_ctl -to $all_pins_um_iw  10.0
+
+# User IO
+set_max_delay -from $all_pads_in    -to $all_pins_um_iw  10.0
+set_max_delay -from $all_pins_um_ow -to $all_pads_out    10.0
diff --git a/ol2/tt_top/build.py b/ol2/tt_top/build.py
index 29b466b..307acd4 100755
--- a/ol2/tt_top/build.py
+++ b/ol2/tt_top/build.py
@@ -70,7 +70,7 @@ class TopFlow(SequentialFlow):
 		Odb.ReportWireLength,
 		Checker.WireLength,
 		OpenROAD.RCX,
-#		OpenROAD.STAPostPNR,	# FIXME
+		OpenROAD.STAPostPNR,
 		OpenROAD.IRDropReport,
 		Magic.StreamOut,
 		Magic.WriteLEF,
@@ -133,6 +133,9 @@ class TopFlow(SequentialFlow):
 			"orientation": m.orient,
 		}
 
+	# Check that macros_models have '/// sta-blackbox' marker
+	# FIXME
+
 	# Custom config
 	flow_cfg = {
 		# Main design properties
@@ -150,6 +153,9 @@ class TopFlow(SequentialFlow):
 		"EXTRA_VERILOG_MODELS": macros_models,
 		"MACROS": macros,
 
+		# Constraints
+		"BASE_SDC_FILE" : "base.sdc",
+
 		# Synthesis
 		"SYNTH_ELABORATE_ONLY"      : True,
 		"SYNTH_EXCLUSION_CELL_LIST" : "no_synth_cells.txt",