From 23bb99f42d3a07568c997e5bba42779ddfc05aea Mon Sep 17 00:00:00 2001 From: Valerio Setti Date: Tue, 14 Nov 2023 16:34:33 +0100 Subject: [PATCH 1/4] spider: build: remove pedantic flag Pedantic build flag provides useless warnings about unnamed structures when building the ethernet drivers in spider platform. Let's remove this flag since it does not provide any benefit in this case. Signed-off-by: Valerio Setti --- goil/templates/config/cortex-a-r/armv8/spider/buildOptions.oil | 1 - 1 file changed, 1 deletion(-) diff --git a/goil/templates/config/cortex-a-r/armv8/spider/buildOptions.oil b/goil/templates/config/cortex-a-r/armv8/spider/buildOptions.oil index 3a42e5490..bd09cdcb9 100755 --- a/goil/templates/config/cortex-a-r/armv8/spider/buildOptions.oil +++ b/goil/templates/config/cortex-a-r/armv8/spider/buildOptions.oil @@ -9,7 +9,6 @@ CPU buildOptions { */ // COMMONFLAGS = "-g"; // Produce debugging information COMMONFLAGS = "-Wall"; // All warnings on - COMMONFLAGS = "-pedantic"; COMMONFLAGS = "-Wformat"; COMMONFLAGS = "-std=c99"; COMMONFLAGS = "-mcpu=cortex-r52"; // Compile for arm r52 From c45d215fc79d5789a9cbc1018e44415723d704c6 Mon Sep 17 00:00:00 2001 From: Valerio Setti Date: Tue, 14 Nov 2023 10:51:40 +0100 Subject: [PATCH 2/4] spider: ethernet: fix for using ports TSN1 and TSN2 Previous implementation had some hard coded initialization for only TSN0 which, of course, made it impossible to use also TSN1 and TSN2. This commit fix this limitation. Now the desired TSN port can be selected at build time by properly setting the TSN_PORT_IN_USE symbol in rswitch.c source file. It should be noted that only 1 single port can be used at a time and it must be selected while building the firmware. There is no auto detection feature or similar supported so far. Signed-off-by: Valerio Setti --- .../drivers/ethernet/renesas/eth_serdes.c | 48 ++++++++++++------- libraries/drivers/ethernet/renesas/rswitch.c | 18 +++---- 2 files changed, 40 insertions(+), 26 deletions(-) diff --git a/libraries/drivers/ethernet/renesas/eth_serdes.c b/libraries/drivers/ethernet/renesas/eth_serdes.c index d83ea9ad1..d65ffdf52 100644 --- a/libraries/drivers/ethernet/renesas/eth_serdes.c +++ b/libraries/drivers/ethernet/renesas/eth_serdes.c @@ -86,7 +86,7 @@ static int eth_serdes_wait_reset(void) { int ch, ret; - for (ch = 0; ch < ETH_SERDES_CH_NUM; ch++) { + for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) { ETH_SERDES_SEL_BANK(ch, 0x0180U); ret = eth_serdes_wait_for_update(ch, 0x026C, BIT(0), BIT(0), ETH_TIMEOUT_COUNT); if (ret != 0) { @@ -105,8 +105,10 @@ static int eth_serdes_initialize_SRAM(void) return ret; } - ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0180); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x026C, 0x3); + for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) { + ETH_SERDES_SEL_BANK(ch, 0x0180); + ETH_SERDES_REG_WRITE(ch, 0x026C, 0x3); + } for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) { ETH_SERDES_SEL_BANK(ch, 0x0300U); @@ -121,22 +123,27 @@ static int eth_serdes_initialize_SRAM(void) static void eth_serdes_set_SGMII_common_settings(void) { + int ch; /* Steps S.4.1 to S.4.5 */ - ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0180); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x0244, 0x97); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01D0, 0x60); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01D8, 0x2200); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01D4, 0x0); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01E0, 0x3D); + for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) { + ETH_SERDES_SEL_BANK(ch, 0x0180); + ETH_SERDES_REG_WRITE(ch, 0x0244, 0x97); + ETH_SERDES_REG_WRITE(ch, 0x01D0, 0x60); + ETH_SERDES_REG_WRITE(ch, 0x01D8, 0x2200); + ETH_SERDES_REG_WRITE(ch, 0x01D4, 0x0); + ETH_SERDES_REG_WRITE(ch, 0x01E0, 0x3D); + } } static int eth_serdes_PHY_soft_reset(void) { - int ret; + int ch, ret; /* Step:5 */ - ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0380); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x0000, 0x8000); + for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) { + ETH_SERDES_SEL_BANK(ch, 0x0380); + ETH_SERDES_REG_WRITE(ch, 0x0000, 0x8000); + } /* Step:6 */ ret = eth_serdes_wait_reset(); @@ -145,14 +152,21 @@ static int eth_serdes_PHY_soft_reset(void) } /* Step:7 */ - ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0180U); - ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x026CU, 0x00000003UL); + for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) { + ETH_SERDES_SEL_BANK(ch, 0x0180U); + ETH_SERDES_REG_WRITE(ch, 0x026CU, 0x00000003UL); + } /* Step:8 */ - ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0380U); - ret = eth_serdes_wait_for_update(ETH_SERDES_XPCS_CH0, 0x0000U, BIT(15), 0UL, ETH_TIMEOUT_COUNT); + for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) { + ETH_SERDES_SEL_BANK(ch, 0x0380U); + ret = eth_serdes_wait_for_update(ch, 0x0000U, BIT(15), 0UL, ETH_TIMEOUT_COUNT); + if (ret != 0) { + return ret; + } + } - return ret; + return 0; } static int eth_serdes_channel_SGMII_common_configuration(uint32 ch) diff --git a/libraries/drivers/ethernet/renesas/rswitch.c b/libraries/drivers/ethernet/renesas/rswitch.c index d8be1aec2..d634104f3 100644 --- a/libraries/drivers/ethernet/renesas/rswitch.c +++ b/libraries/drivers/ethernet/renesas/rswitch.c @@ -778,31 +778,31 @@ static int rswitch_phy_init(struct rswitch_etha *etha) int ret; /* Reset */ - CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0xC04A, ®_data)); + CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0xC04A, ®_data)); reg_data |= BIT(15); - CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0xC04A, ®_data)); - CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0xC04A, ®_data)); /* MCAL does it twice... */ + CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0xC04A, ®_data)); + CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0xC04A, ®_data)); /* MCAL does it twice... */ /* Check mode */ - CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0xC04A, ®_data)); + CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0xC04A, ®_data)); if ((reg_data & 0x7) != 0x4 ) { /* 4 stands for SGMII */ reg_data &= ~0x7; reg_data |= BIT(15) | 0x4; - CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0xC04A, ®_data)); + CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0xC04A, ®_data)); /* Run SERDES Init */ - CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0x800F, ®_data)); + CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0x800F, ®_data)); reg_data |= BIT(15) | BIT(13); - CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0x800F, ®_data)); + CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0x800F, ®_data)); reg_data = 0x0U; do { - CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0x800F, ®_data)); + CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0x800F, ®_data)); } while (reg_data & BIT(15)); /* Auto SERDES Init Disable */ reg_data &= ~BIT(13); - CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0x800F, ®_data)); + CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0x800F, ®_data)); } return 0; From 14085bf4be8789628fb5f0a6352e697af5b6d550 Mon Sep 17 00:00:00 2001 From: Valerio Setti Date: Wed, 22 Nov 2023 15:46:49 +0100 Subject: [PATCH 3/4] spider: core: add L1 cache clearing function Signed-off-by: Valerio Setti --- .../config/cortex-a-r/armv8/spider/config.oil | 1 + .../cortex-a-r/armv8/spider/spider_utils.c | 22 +++++++++++++++++++ .../cortex-a-r/armv8/spider/spider_utils.h | 3 +++ 3 files changed, 26 insertions(+) create mode 100644 machines/cortex-a-r/armv8/spider/spider_utils.c create mode 100644 machines/cortex-a-r/armv8/spider/spider_utils.h diff --git a/goil/templates/config/cortex-a-r/armv8/spider/config.oil b/goil/templates/config/cortex-a-r/armv8/spider/config.oil index 3f2c057e7..77f093e17 100755 --- a/goil/templates/config/cortex-a-r/armv8/spider/config.oil +++ b/goil/templates/config/cortex-a-r/armv8/spider/config.oil @@ -56,6 +56,7 @@ CPU spider { CFILE = "tpl_stubs.c"; CFILE = "tpl_irq.c"; CFILE = "tpl_vector_table_ns.s"; + CFILE = "spider_utils.c"; }; LIBRARY serial { diff --git a/machines/cortex-a-r/armv8/spider/spider_utils.c b/machines/cortex-a-r/armv8/spider/spider_utils.c new file mode 100644 index 000000000..93038237b --- /dev/null +++ b/machines/cortex-a-r/armv8/spider/spider_utils.c @@ -0,0 +1,22 @@ +#include "emblib.h" + +#define DCACHE_LINE_SIZE 64 + +void invalidate_data_cache_by_address(volatile void *addr, sint32 dsize) +{ + if ( dsize > 0 ) { + sint32 op_size = dsize + (((uint32)addr) & (DCACHE_LINE_SIZE - 1U)); + uint32 op_addr = (uint32)addr; + + __asm__ volatile ("dsb"); + + do { + cp15_write32(0, 7, 6, 1, op_addr); + op_addr += DCACHE_LINE_SIZE; + op_size -= DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __asm__ volatile ("dsb"); + __asm__ volatile ("isb"); + } +} \ No newline at end of file diff --git a/machines/cortex-a-r/armv8/spider/spider_utils.h b/machines/cortex-a-r/armv8/spider/spider_utils.h new file mode 100644 index 000000000..c57778bea --- /dev/null +++ b/machines/cortex-a-r/armv8/spider/spider_utils.h @@ -0,0 +1,3 @@ + + +void invalidate_data_cache_by_address(volatile void *addr, sint32 dsize); \ No newline at end of file From d2ec66cc09d77075029c47ad4f5a4835c2b491c7 Mon Sep 17 00:00:00 2001 From: Valerio Setti Date: Wed, 22 Nov 2023 15:47:38 +0100 Subject: [PATCH 4/4] spider: ethernet: clear L1 cache before reading RX descriptors Without this fix it can happen that the descriptors read from CR52 are not aligned with the RAM content which results in no operation on the received data. This is of course not correct and due to a misalignment between the RAM content and L1 cache. This commits resolves this issue by invalidating L1 cache before reading descriptors. Signed-off-by: Valerio Setti --- libraries/drivers/ethernet/renesas/rswitch.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/drivers/ethernet/renesas/rswitch.c b/libraries/drivers/ethernet/renesas/rswitch.c index d634104f3..c1613bfac 100644 --- a/libraries/drivers/ethernet/renesas/rswitch.c +++ b/libraries/drivers/ethernet/renesas/rswitch.c @@ -3,6 +3,7 @@ #include "rswitch.h" #include "rswitch_regs.h" #include "err_codes.h" +#include "spider_utils.h" #include #define PORT_TSNA_N 3 @@ -929,6 +930,7 @@ TASK(gwca1_rx_tx_task) { if (chain->irq_triggered != 0) { /* Go through the descriptors chain to parse received data */ while (1) { + invalidate_data_cache_by_address(rx_ring, sizeof(rx_ring)); ts_desc = &(chain->ts_ring[chain->next_index]); /* Stop once we get to a descriptor that was not modified */ if (ts_desc->die_dt == (DT_FEMPTY | DIE)) {