NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL

[umarcor]

ref: https://neorv32.org/
tags: [neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD]
repo: stnolting/neorv32

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz.

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.

⁉️ Want to know more? Check out the project's rationale.

📚 For detailed information take a look at the NEORV32 documentation (online at GitHub-pages).

🏷️ The project's change log is available in CHANGELOG.md. To see the changes between official releases visit the project's release page.

📦 Exemplary setups targeting various FPGA boards and toolchains to get you started.

🪁 Supported by upstream Zephyr OS and FreeRTOS.

💡 Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel. See how to contribute.

🚀 Check out the quick links or directly jump to the User Guide to get started setting up your NEORV32 setup!