Generating XSA for KV260 returns issue

[kalvin66rocks]

Hi, I'm following instructions from the Xilinx docs for the KV260 Defect Detect application here, and can't get through the vivado flow, running the following command as per the doc page make xsa

Which then produces the following error:
ERROR: unexpected exception when evaluating tcl command
while executing
"generate_target all [get_files $proj_dir/${proj_name}.srcs/sources_1/bd/$proj_name/${proj_name}.bd]"
(file "scripts/main.tcl" line 60)

The same result occurs when attempting to create the XSA for the other applications and the error doesn't really provide any insight as to a root cause.

Pleas advise?

[sweatharao]

Can you look at vivado.log and see if there are any other messages?

[kalvin66rocks]

There isn't anything in here that looks suspect to me. There are 4 critical warnings about width mismatches, which I have seen cause no issues using the block designer in the past, this is just a flavor of 4 critical warnings CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/display_pipeline/xlconcat_0/In2'(4) to pin '/display_pipeline/xlconstant_2/dout'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected

The regular warnings are also of this nature (width mismatch)

The only info comment looks interesting is the following one that appears 9 times INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI

The last commands the execute before this error pops up are:
INFO: [BD 41-1029] Generation completed for the IP Integrator block PS_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ic_ctrl_100Mhz/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ic_ctrl_100Mhz/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ic_ctrl_275Mhz/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ic_ctrl_275Mhz/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_vip_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline/axis_data_fifo_cap .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline/axis_subset_converter_0 .
Then the error message that I originally posted.

Looking into the sub-block of capture_pipeline, one of the blocks Video Frame Buffer Write or MIPI CSI-2 Rx Subsystem is to cause? I am just not getting any indicator as such.

[sweatharao]

Can you browse into the following directories and check the runme.log file to figure out if it is MIPI or Frame buffer write that failed.

platforms\vivado\kv260_ispMipiRx_vmixDP\project\kv260_ispMipiRx_vmixDP.runs\kv260_ispMipiRx_vmixDP_mipi_csi2_rx_subsyst_0_0_synth_1

platforms\vivado\kv260_ispMipiRx_vmixDP\project\kv260_ispMipiRx_vmixDP.runs\kv260_ispMipiRx_vmixDP_v_frmbuf_wr_0_0_synth_1

[kalvin66rocks]

so whatever is happening, I don't actually end up with a *.runs folder. Running the script that make invokes from within Vivado, I get the same error. Then if I try to "generate output products" for the block design, the same error pops up, but it doesn't seem to be generating an error log or a useful error log from what I can find.

[sweatharao]

Not sure if you are running into this issue with Vitis HLS (Frame Buffer Write IP is an HLS IP) which had a timestamp issue
https://support.xilinx.com/s/article/76960?language=en_US

Can you check if you have this patch?

[kalvin66rocks]

From reading the app notes, and trying to install the patch, it doesn't apply to 2022.x versions, only previous.

It appears to be a windows/linux thing. I spun up an Ubuntu VM and installed the same version of Vitis/Vivado on it, and made it past this step without issue. I wish the error log in windows gave me some better sense of what it is having issue with.

Thanks for the help