diff --git a/llvm/lib/Target/AIE/AIE2Schedule.td b/llvm/lib/Target/AIE/AIE2Schedule.td
index 90a0478000fe..a5ad1023e4eb 100644
--- a/llvm/lib/Target/AIE/AIE2Schedule.td
+++ b/llvm/lib/Target/AIE/AIE2Schedule.td
@@ -441,11 +441,11 @@ InstrItinData<II_ADD, [InstrStage<1,  [R_WX_PORT]>],
 InstrItinData<II_ADD_NC, [PrefixCycle<P_WM_PORT>, PrefixCycle<M_WM_PORT>, PrefixCycle<DJ_WM_PORT>,
                          PrefixCycle<DN_WM_PORT>, PrefixCycle<DC_WM_PORT>, SimpleCycle<RS_WM_PORT>],
                          [1,1,1]>,
-InstrItinData<II_ADD_NC_DC, [SimpleCycle<DC_WM_PORT>], [1,1,1]>,
-InstrItinData<II_ADD_NC_DJ, [SimpleCycle<DJ_WM_PORT>], [1,1,1]>,			  
-InstrItinData<II_ADD_NC_DN, [SimpleCycle<DN_WM_PORT>], [1,1,1]>,
-InstrItinData<II_ADD_NC_M, [SimpleCycle<M_WM_PORT>], [1,1,1]>,
-InstrItinData<II_ADD_NC_P, [SimpleCycle<P_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_DC, [PrefixCycle<RS_WM_PORT>, SimpleCycle<DC_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_DJ, [PrefixCycle<RS_WM_PORT>, SimpleCycle<DJ_WM_PORT>], [1,1,1]>,			  
+InstrItinData<II_ADD_NC_DN, [PrefixCycle<RS_WM_PORT>, SimpleCycle<DN_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_M, [PrefixCycle<RS_WM_PORT>, SimpleCycle<M_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_P, [PrefixCycle<RS_WM_PORT>, SimpleCycle<P_WM_PORT>], [1,1,1]>,
 InstrItinData<II_ADD_NC_RS, [SimpleCycle<RS_WM_PORT>], [1,1,1]>,	                         
 InstrItinData<II_AND, [InstrStage<1,  [R_WX_PORT]>], [1,1,1,1]>,
 InstrItinData<II_ASHL, [InstrStage<1,  [R_WX_PORT]>], [1,1,1,1]>,
@@ -600,11 +600,11 @@ InstrItinData<II_LT, [InstrStage<1,  [R_WX_PORT]>], [1,1,1,1]>,
 InstrItinData<II_LTU, [InstrStage<1,  [R_WX_PORT]>], [1,1,1,1]>,
 InstrItinData<II_MOV, [PrefixCycle<P_WM_PORT>, PrefixCycle<M_WM_PORT>, PrefixCycle<DJ_WM_PORT>,
                        PrefixCycle<DN_WM_PORT>, PrefixCycle<DC_WM_PORT>, SimpleCycle<RS_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_DC, [SimpleCycle<DC_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_DJ, [SimpleCycle<DJ_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_DN, [SimpleCycle<DN_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_M, [SimpleCycle<M_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_P, [SimpleCycle<P_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_DC, [PrefixCycle<RS_WM_PORT>, SimpleCycle<DC_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_DJ, [PrefixCycle<RS_WM_PORT>, SimpleCycle<DJ_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_DN, [PrefixCycle<RS_WM_PORT>, SimpleCycle<DN_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_M, [PrefixCycle<RS_WM_PORT>, SimpleCycle<M_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_P, [PrefixCycle<RS_WM_PORT>, SimpleCycle<P_WM_PORT>], [1,1]>,
 InstrItinData<II_MOV_RS, [SimpleCycle<RS_WM_PORT>], [1,1]>,
 InstrItinData<II_MOVA, [PrefixCycle<P_WM_PORT>, PrefixCycle<M_WM_PORT>, PrefixCycle<DJ_WM_PORT>,
                         PrefixCycle<DN_WM_PORT>, PrefixCycle<DC_WM_PORT>, SimpleCycle<R_WA_PORT>], [1,1]>,
@@ -618,11 +618,11 @@ InstrItinData<II_MOVX, [SimpleCycle<R_WX_PORT>], [1,1]>,
 InstrItinData<II_MOV_SCL, [PrefixCycle<P_RM_PORT>, PrefixCycle<RS_WM_PORT>, PrefixCycle<P_WM_PORT>, PrefixCycle<M_WM_PORT>,
                            PrefixCycle<DJ_WM_PORT>, PrefixCycle<DN_WM_PORT>, SimpleCycle<DC_WM_PORT>],
                            [1,1]>,
-InstrItinData<II_MOV_SCL_DC, [PrefixCycle<P_RM_PORT>, SimpleCycle<DC_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_SCL_DJ, [PrefixCycle<P_RM_PORT>, SimpleCycle<DJ_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_SCL_DN, [PrefixCycle<P_RM_PORT>, SimpleCycle<DN_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_SCL_M, [PrefixCycle<P_RM_PORT>, SimpleCycle<M_WM_PORT>], [1,1]>,
-InstrItinData<II_MOV_SCL_P, [PrefixCycle<P_RM_PORT>, SimpleCycle<P_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_SCL_DC, [PrefixCycle<P_RM_PORT>,PrefixCycle<RS_WM_PORT>,  SimpleCycle<DC_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_SCL_DJ, [PrefixCycle<P_RM_PORT>,PrefixCycle<RS_WM_PORT>,  SimpleCycle<DJ_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_SCL_DN, [PrefixCycle<P_RM_PORT>,PrefixCycle<RS_WM_PORT>,  SimpleCycle<DN_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_SCL_M, [PrefixCycle<P_RM_PORT>,PrefixCycle<RS_WM_PORT>,  SimpleCycle<M_WM_PORT>], [1,1]>,
+InstrItinData<II_MOV_SCL_P, [PrefixCycle<P_RM_PORT>,PrefixCycle<RS_WM_PORT>,  SimpleCycle<P_WM_PORT>], [1,1]>,
 InstrItinData<II_MOV_SCL_RS, [PrefixCycle<P_RM_PORT>, SimpleCycle<RS_WM_PORT>], [1,1]>,
 InstrItinData<II_MOV_SS, [AvoidSemaphore<7>, EmptyCycles<6>, SimpleCycle<R_WA_PORT>], [7,/*def:srSS0*/8]>,
 InstrItinData<II_MOVd1, [SimpleCycle<P_RM_PORT>, SimpleCycle<RS_WM_PORT>], [2,1]>,
@@ -790,15 +790,15 @@ InstrItinData<II_VEXTBCST, [EmptyCycles<1>, InstrStage<1,  [W_WM_PORT]>],
 InstrItinData<II_VEXTRACT, [EmptyCycles<1>, PrefixCycle<RS_WM_PORT>, PrefixCycle<P_WM_PORT>, PrefixCycle<M_WM_PORT>,
                             PrefixCycle<DJ_WM_PORT>, PrefixCycle<DN_WM_PORT>, SimpleCycle<DC_WM_PORT>],
               [2,1,1,/*crVaddSign*/1], [NoBypass,MOV_Bypass,NoBypass]>,
-InstrItinData<II_VEXTRACT_DC, [EmptyCycles<1>, SimpleCycle<DC_WM_PORT>],
+InstrItinData<II_VEXTRACT_DC, [EmptyCycles<1>, PrefixCycle<RS_WM_PORT>, SimpleCycle<DC_WM_PORT>],
               [2,1,1,/*crVaddSign*/1], [NoBypass,MOV_Bypass,NoBypass]>,
-InstrItinData<II_VEXTRACT_DJ, [EmptyCycles<1>, SimpleCycle<DJ_WM_PORT>],
+InstrItinData<II_VEXTRACT_DJ, [EmptyCycles<1>, PrefixCycle<RS_WM_PORT>, SimpleCycle<DJ_WM_PORT>],
               [2,1,1,/*crVaddSign*/1], [NoBypass,MOV_Bypass,NoBypass]>,
-InstrItinData<II_VEXTRACT_DN, [EmptyCycles<1>, SimpleCycle<DN_WM_PORT>],
+InstrItinData<II_VEXTRACT_DN, [EmptyCycles<1>, PrefixCycle<RS_WM_PORT>, SimpleCycle<DN_WM_PORT>],
               [2,1,1,/*crVaddSign*/1], [NoBypass,MOV_Bypass,NoBypass]>,
-InstrItinData<II_VEXTRACT_M, [EmptyCycles<1>, SimpleCycle<M_WM_PORT>],
+InstrItinData<II_VEXTRACT_M, [EmptyCycles<1>, PrefixCycle<RS_WM_PORT>, SimpleCycle<M_WM_PORT>],
               [2,1,1,/*crVaddSign*/1], [NoBypass,MOV_Bypass,NoBypass]>,
-InstrItinData<II_VEXTRACT_P, [EmptyCycles<1>, SimpleCycle<P_WM_PORT>],
+InstrItinData<II_VEXTRACT_P, [EmptyCycles<1>, PrefixCycle<RS_WM_PORT>, SimpleCycle<P_WM_PORT>],
               [2,1,1,/*crVaddSign*/1], [NoBypass,MOV_Bypass,NoBypass]>,
 InstrItinData<II_VEXTRACT_RS, [EmptyCycles<1>, SimpleCycle<RS_WM_PORT>],
               [2,1,1,/*crVaddSign*/1], [NoBypass,MOV_Bypass,NoBypass]>,
diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/resource/r_wm.mir b/llvm/test/CodeGen/AIE/aie2/schedule/resource/r_wm.mir
index fc8f10d5bf79..953d308e8d6f 100644
--- a/llvm/test/CodeGen/AIE/aie2/schedule/resource/r_wm.mir
+++ b/llvm/test/CodeGen/AIE/aie2/schedule/resource/r_wm.mir
@@ -23,6 +23,19 @@ body:             |
     $r3 = MOV_mv_scl $r4
 ...
 
+---
+name:            E2_VEXTRACT_E1_MOV_mv_scl_P
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: E2_VEXTRACT_E1_MOV_mv_scl_P
+    ; CHECK: $r2 = VEXTRACT_S32 killed $x2, killed $r16
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: $p1 = MOV_mv_scl killed $p0
+    $r2 = VEXTRACT_S32 $x2, $r16
+    $p1 = MOV_mv_scl $p0
+...
+
 ---
 name:            E2_VEXTRACT_E1_MOV_mv_cg
 alignment:       16
@@ -36,6 +49,19 @@ body:             |
     $r3 = MOV_mv_cg 0
 ...
 
+---
+name:            E2_VEXTRACT_E1_MOV_mv_cg_D
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: E2_VEXTRACT_E1_MOV_mv_cg_D
+    ; CHECK: $r2 = VEXTRACT_S32 killed $x2, killed $r16
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: $dc0 = MOV_mv_cg 0
+    $r2 = VEXTRACT_S32 $x2, $r16
+    $dc0 = MOV_mv_cg 0
+...
+
 ---
 name:            E2_VEXTRACT_E1_ADD_NC
 alignment:       16
@@ -50,16 +76,16 @@ body:             |
 ...
 
 ---
-name:            E2_VEXTRACT_E1_ADD_NC_R
+name:            E2_VEXTRACT_E1_ADD_NC_S
 alignment:       16
 body:             |
   bb.0.entry:
-    ; CHECK-LABEL: name: E2_VEXTRACT_E1_ADD_NC_R
+    ; CHECK-LABEL: name: E2_VEXTRACT_E1_ADD_NC_S
     ; CHECK: $r2 = VEXTRACT_S32 killed $x2, killed $r16
     ; CHECK-NEXT: NOP
-    ; CHECK-NEXT: $r3 = ADD_NC killed $r4, -32
+    ; CHECK-NEXT: $s0 = ADD_NC killed $r4, -32
     $r2 = VEXTRACT_S32 $x2, $r16
-    $r3 = ADD_NC $r4, -32
+    $s0 = ADD_NC $r4, -32
 ...
 
 ---