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Hi @wnew, I'll just quickly comment that the implementation settings are the ones that would have more timing impact rather than the synthesis settings. For example, I can imagine that setting to one of the PerformanceExplore ... or Performance related ones with high efforts might give the best timing results. Yes, I think for some of the boards that it is necessary to go and adjust/manually modify the implementation strategy in order to meet timing. Thanks, |
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Thanks, I'll get back to you after I try the pull request. Unfortunately, I have a message to convey regarding Vivado versions below. In terms of Vivado support, right now v2022.1 is the best version to use, and the reason for this is the QDMA IP. In Vivado v2022.2 there was a new major release of QDMA (v5.0), it changed its register interface for memory-mapped control registers to support wider values for certain fields. Effectively, the QDMA team reorganized the register mapping. (In doing so that broke compatibility with the earlier versions of any QDMA-related software). open-nic-shell and open-nic-driver were written against earlier versions of QDMA. As it stands currently, open-nic-driver hasn't been updated for QDMA v5.0. However, the official Xilinx QDMA driver repo on github contains updates for QDMA v5.0. So, depending on what you need on the software side, you might see DPDK work, but the separate Linux kernel driver can have issues. More specifically, open-nic-driver can stop responding at high throughput due to the differences in QDMA v5.0 register interface, but still works properly with QDMA v4.0. For now, it's probably easiest to stick to using Vivado 2022.1 or earlier. Or if necessary to generate the QDMA IP using an earlier version, and then not to upgrade that indivdual IP, when switching/using the design with newer versions of Vivado. This is a rather long message, but hopefully I've explained this issue clearly. |
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Hi @cneely-amd, I am running to a very frustrating issue with 2022.1 version of Vivado. I chose it specifically based on your recommendation above to @wnew, who referred me to this thread. I have installed the Vivado Standard edition and when I build opennic-shell it gets stuck on not being able to generate clk IP.
So I opened Vivado GUI and checked if the clocking wizard can even be opened and I run into this error. This specifically happen when I target opennic shell to U50 or U55C board with this version of Vivado 2022.1. Any suggestions? |
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I have built the AU50 design without any user design and am getting intra-clock timing issues within the CMAC tx clock domain. Is to be expected without user logic?
I have however managed to get it to make timing with synthesis strategy of FlowAreaOptimized_high and implementation strategy congestion_Spreadlogic_high.
Any suggestions here?
Regards
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