diff --git a/drivers/misc/mediatek/accdet/Makefile b/drivers/misc/mediatek/accdet/Makefile index 35999689e..476888025 100644 --- a/drivers/misc/mediatek/accdet/Makefile +++ b/drivers/misc/mediatek/accdet/Makefile @@ -1,5 +1,8 @@ subdir-ccflags-y += -Werror -I$(srctree)/drivers/misc/mediatek/accdet/$(MTK_PLATFORM) subdir-ccflags-y += -Werror -I$(srctree)/drivers/misc/mediatek/include/mt-plat/ +ifeq ($(CONFIG_MTK_PMIC_CHIP_MT6355),y) +subdir-ccflags-y += -Werror -I$(srctree)/sound/soc/mediatek/codec/mt6355/ +endif obj-$(CONFIG_MTK_ACCDET) := accdet_drv.o obj-$(CONFIG_MTK_ACCDET) += $(subst ",,$(CONFIG_MTK_PLATFORM))/ diff --git a/drivers/misc/mediatek/accdet/mt6757/accdet.c b/drivers/misc/mediatek/accdet/mt6757/accdet.c index 6b013f0aa..8db4a637e 100644 --- a/drivers/misc/mediatek/accdet/mt6757/accdet.c +++ b/drivers/misc/mediatek/accdet/mt6757/accdet.c @@ -33,7 +33,15 @@ #include #include +#ifdef CONFIG_MTK_PMIC_CHIP_MT6355 +/* just use on kibo+ */ +/* fix record no voice when press key */ +#include "mtk-soc-codec-63xx.h" +#endif + + #define DEBUG_THREAD 1 +#define HW_MODE_SUPPORT 0/* HW path */ /* * static variable defination @@ -46,7 +54,7 @@ static int button_press_debounce = 0x400; int cur_key; struct head_dts_data accdet_dts_data; -s8 accdet_auxadc_offset; +int accdet_auxadc_offset; int accdet_irq; unsigned int gpiopin, headsetdebounce; unsigned int accdet_eint_type = IRQ_TYPE_LEVEL_LOW;/* default low_level trigger */ @@ -241,12 +249,15 @@ static void pmic_pwrap_write(unsigned int addr, unsigned int wdata) static int Accdet_PMIC_IMM_GetOneChannelValue(int deCount) { + unsigned int reg_val = 0; unsigned int vol_val = 0; pmic_pwrap_write(ACCDET_AUXADC_CTL_SET, ACCDET_CH_REQ_EN); mdelay(3); - while ((pmic_pwrap_read(ACCDET_AUXADC_REG) & ACCDET_DATA_READY) != ACCDET_DATA_READY) - ; + reg_val = pmic_pwrap_read(ACCDET_AUXADC_REG); + while ((reg_val & ACCDET_DATA_READY) != ACCDET_DATA_READY) + reg_val = pmic_pwrap_read(ACCDET_AUXADC_REG); + /* wait AUXADC data ready */ vol_val = (pmic_pwrap_read(ACCDET_AUXADC_REG) & ACCDET_DATA_MASK); vol_val = (vol_val * 1800) / 4096; /* mv */ @@ -404,8 +415,11 @@ static void accdet_eint_work_callback(struct work_struct *work) pmic_pwrap_write(ACCDET_PWM_THRESH, cust_headset_settings->pwm_width); ACCDET_DEBUG("[Accdet]pin recog start! micbias always on!\n"); #endif + #if HW_MODE_SUPPORT + #else /* set PWM IDLE on */ pmic_pwrap_write(ACCDET_STATE_SWCTRL, (pmic_pwrap_read(ACCDET_STATE_SWCTRL) | ACCDET_SWCTRL_IDLE_EN)); + #endif /* enable ACCDET unit */ enable_accdet(ACCDET_SWCTRL_EN); } else { @@ -765,8 +779,10 @@ int accdet_irq_handler(void) } accdet_workqueue_func(); while (((pmic_pwrap_read(ACCDET_IRQ_STS) & IRQ_STATUS_BIT) - && (accdet_timeout_ns(cur_time, ACCDET_TIME_OUT)))) - ; + && (accdet_timeout_ns(cur_time, ACCDET_TIME_OUT)))); + /* clear accdet int, modify for fix interrupt trigger twice error */ + pmic_pwrap_write(ACCDET_IRQ_STS, pmic_pwrap_read(ACCDET_IRQ_STS) & (~IRQ_CLR_BIT)); + pmic_pwrap_write(INT_STATUS_ACCDET, RG_INT_STATUS_ACCDET); #endif #ifdef ACCDET_NEGV_IRQ cur_time = accdet_get_current_time(); @@ -1014,6 +1030,13 @@ static inline void check_cable_type(void) #endif /* solution: reduce hook switch debounce time to 0x400 */ pmic_pwrap_write(ACCDET_DEBOUNCE0, button_press_debounce); +#ifdef CONFIG_MTK_PMIC_CHIP_MT6355 + /* just use on kibo+ */ + /* fix record no voice when press key */ + /* notify audio when bit0=1,bit1=1,bit6=0,bit7=1 */ + if ((0xC3 & (pmic_pwrap_read(0x361E))) == 0x83) + mtk_audio_reset_input_precharge();/* call audio to reset record */ +#endif } else if (current_status == 3) { #ifdef CONFIG_ACCDET_PIN_RECOGNIZATION @@ -1174,12 +1197,54 @@ int accdet_get_dts_data(void) } void accdet_pmic_Read_Efuse_HPOffset(void) { - s16 efusevalue; + unsigned int efusevalue = 0; + unsigned int tmp_val = 0; - efusevalue = (s16) pmic_Read_Efuse_HPOffset(RG_OTP_PA_ADDR_WORD_INDEX); - accdet_auxadc_offset = (efusevalue >> RG_OTP_PA_ACCDET_BIT_SHIFT) & 0xFF; + efusevalue = 0; + tmp_val = 0; + +#if defined(CONFIG_MTK_PMIC_CHIP_MT6355)/* support mt6355, default open HW mode */ +#ifdef CONFIG_FOUR_KEY_HEADSET/* Just for 4-key, 2.7V, internal bias for mt6337*/ + /* [Notice] must confirm the bias vol is 2.7v */ + /* get 8bit from efuse rigister, so need extend to 12bit, shift right 2*/ + /* AD */ + tmp_val = pmic_pwrap_read(REG_ACCDET_AD_CALI_1); + efusevalue = (tmp_val>>RG_ACCDET_BIT_SHIFT)&ACCDET_CALI_MASK2; + tmp_val = pmic_pwrap_read(REG_ACCDET_AD_CALI_2); + efusevalue = efusevalue | ((tmp_val & 0x01) << RG_ACCDET_HIGH_BIT_SHIFT); + accdet_dts_data.four_key.mid_key_four = efusevalue; + + /* DB */ + tmp_val = pmic_pwrap_read(REG_ACCDET_AD_CALI_2); + efusevalue = (tmp_val>>0x01)&ACCDET_CALI_MASK3; + accdet_dts_data.four_key.voice_key_four = efusevalue; + + /* BC */ + tmp_val = pmic_pwrap_read(REG_ACCDET_AD_CALI_2); + efusevalue = (tmp_val>>RG_ACCDET_BIT_SHIFT)&ACCDET_CALI_MASK4; + tmp_val = pmic_pwrap_read(REG_ACCDET_AD_CALI_3); + efusevalue = efusevalue | ((tmp_val & 0x01) << RG_ACCDET_HIGH_BIT_SHIFT); + accdet_dts_data.four_key.up_key_four = efusevalue; + accdet_dts_data.four_key.down_key_four = 1000;/* ?? need check */ + accdet_auxadc_offset = 0; +#else/* 3-key, not same with mt6351 */ + tmp_val = pmic_pwrap_read(REG_ACCDET_AD_CALI_0);/* read HW reg */ + efusevalue = (int)((tmp_val>>RG_ACCDET_BIT_SHIFT)&ACCDET_CALI_MASK0); + tmp_val = pmic_pwrap_read(REG_ACCDET_AD_CALI_1);/* read HW reg */ + accdet_auxadc_offset = efusevalue | ((tmp_val & 0x01) << RG_ACCDET_HIGH_BIT_SHIFT); + if (accdet_auxadc_offset > 128) + accdet_auxadc_offset -= 256; + accdet_auxadc_offset = (accdet_auxadc_offset / 2); + ACCDET_INFO("[accdet_Efuse]--efuse=0x%x,auxadc_value=%d mv\n", efusevalue, accdet_auxadc_offset); +#endif +#else/* used on mt6351 */ + efusevalue = pmic_Read_Efuse_HPOffset(RG_OTP_PA_ADDR_WORD_INDEX); + accdet_auxadc_offset = (int)((efusevalue >> RG_OTP_PA_ACCDET_BIT_SHIFT) & 0xFF); + if (accdet_auxadc_offset > 128)/* modify to solve the sign data issue */ + accdet_auxadc_offset -= 256; accdet_auxadc_offset = (accdet_auxadc_offset / 2); ACCDET_INFO(" efusevalue = 0x%x, accdet_auxadc_offset = %d\n", efusevalue, accdet_auxadc_offset); +#endif } static inline void accdet_init(void) @@ -1284,10 +1349,13 @@ static inline void accdet_init(void) } #if defined(CONFIG_MTK_PMIC_CHIP_MT6355)/* support mt6355, default open HW mode */ - /* HW path */ +#if HW_MODE_SUPPORT/* HW path */ pmic_pwrap_write(ACCDET_HW_MODE_DFF, 0x8000|ACCDET_HWMODE_SEL|ACCDET_EINT_DEB_OUT_DFF); - /* pmic_pwrap_write(ACCDET_HW_MODE_DFF, 0x8000); *//* SW path, */ +#else + pmic_pwrap_write(ACCDET_HW_MODE_DFF, 0x8000);/* SW path */ #endif +#endif + #if defined CONFIG_ACCDET_EINT /* disable ACCDET unit */ diff --git a/drivers/misc/mediatek/accdet/mt6757/reg_accdet.h b/drivers/misc/mediatek/accdet/mt6757/reg_accdet.h index 7f2eb6f0c..4385f1595 100644 --- a/drivers/misc/mediatek/accdet/mt6757/reg_accdet.h +++ b/drivers/misc/mediatek/accdet/mt6757/reg_accdet.h @@ -73,6 +73,12 @@ #define ACCDET_ADC_REG ((unsigned int)(ACCDET_BASE+0x3636)) #define ACCDET_MICBIAS_REG ((unsigned int)(ACCDET_BASE+0x3634)) +#define REG_ACCDET_AD_CALI_0 ((unsigned int)(ACCDET_BASE+0x1E84)) +#define REG_ACCDET_AD_CALI_1 ((unsigned int)(ACCDET_BASE+0x1E86)) +#define REG_ACCDET_AD_CALI_2 ((unsigned int)(ACCDET_BASE+0x1E88)) +#define REG_ACCDET_AD_CALI_3 ((unsigned int)(ACCDET_BASE+0x1E8A)) + + #define PMIC_REG_BASE_START (0x0000)/* MT6355 register base address start */ #define PMIC_REG_BASE_END (0x380A)/* MT6355 register base address end */ @@ -121,6 +127,16 @@ #define ACCDET_HWMODE_SEL (0x01<<0)/* Enable HW mode */ #define ACCDET_EINT_DEB_OUT_DFF (0x01<<1)/* 1, modified for path mt6355;0,path to mt6337 */ +/* [0x1E84]--[0x1E8A] */ +#define RG_ACCDET_BIT_SHIFT (0x09) +#define RG_ACCDET_HIGH_BIT_SHIFT (0x07) + +#define ACCDET_CALI_MASK0 (0x7F)/* offset mask */ +#define ACCDET_CALI_MASK1 (0xFF)/* reserve */ +#define ACCDET_CALI_MASK2 (0x7F)/* AD efuse mask */ +#define ACCDET_CALI_MASK3 (0xFF)/* DB efuse mask */ +#define ACCDET_CALI_MASK4 (0x7F)/* BC efuse mask */ + #else/* support mt6351 */ /* Register address define */ #define ACCDET_BASE 0x00000000