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The actual "bug" is the VVAR macro expansion. At one time, that worked to access values internal to the design.
Shame on me for using references to Verilator's internal data structures. Verilator changed the name(s) to those structures, and now they are more challenging to access from a C++ program trying to peek at those internals.
There are a couple of approaches to fixing this. I could ...
Look to remove all references to internal variables.
Create a test bench wrapper with access to those values via Verilog "dot-notation", and export them as proper outputs to the module
Continue the VVAR expansion, but just use a quick bash script to determine which version of Verilator is being used, and direct them as appropriate.
Setup:
How to reproduce:
make all
Make output:
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