From 93a9f8171c941173a5148098ec7d46184ee67992 Mon Sep 17 00:00:00 2001 From: Alexandra Sidorova Date: Thu, 14 Nov 2024 12:13:57 +0100 Subject: [PATCH] [snippets][CPU] Fixes --- .../emitters/snippets/x64/kernel_executors/brgemm_base.hpp | 1 + .../x64/lowered/buffer_allocation.cpp | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/src/plugins/intel_cpu/src/emitters/snippets/x64/kernel_executors/brgemm_base.hpp b/src/plugins/intel_cpu/src/emitters/snippets/x64/kernel_executors/brgemm_base.hpp index 9ddc8a8beee37e..294521d0b7fb9d 100644 --- a/src/plugins/intel_cpu/src/emitters/snippets/x64/kernel_executors/brgemm_base.hpp +++ b/src/plugins/intel_cpu/src/emitters/snippets/x64/kernel_executors/brgemm_base.hpp @@ -53,6 +53,7 @@ struct BrgemmBaseKernelConfig { protected: struct StaticBaseParams { StaticBaseParams(const element::Type& in0_dtype, const element::Type& in1_dtype, dnnl::impl::cpu::x64::cpu_isa_t primitive_isa); + virtual ~StaticBaseParams() = default; const dnnl_data_type_t dt_in0 {dnnl_f32}, dt_in1 {dnnl_f32}; const dnnl::impl::cpu::x64::cpu_isa_t isa {dnnl::impl::cpu::x64::isa_undef}; diff --git a/src/plugins/intel_cpu/tests/unit/snippets_transformations/x64/lowered/buffer_allocation.cpp b/src/plugins/intel_cpu/tests/unit/snippets_transformations/x64/lowered/buffer_allocation.cpp index 201f1dce87371a..51092135db2df1 100644 --- a/src/plugins/intel_cpu/tests/unit/snippets_transformations/x64/lowered/buffer_allocation.cpp +++ b/src/plugins/intel_cpu/tests/unit/snippets_transformations/x64/lowered/buffer_allocation.cpp @@ -3,6 +3,7 @@ // #include "openvino/opsets/opset.hpp" +#include "openvino/runtime/system_conf.hpp" #include "snippets/snippets_isa.hpp" #include "snippets/lowered/linear_ir.hpp" #include "snippets/lowered/pass/mark_loops.hpp" @@ -255,6 +256,11 @@ TEST_P(MHAFP32BufferAllocationTest, BufferAllocationCPU) { } TEST_P(MHABF16AMXBufferAllocationTest, BufferAllocationCPU) { + // Scratchpad memory for AMX with CopyA (dynamic case) has allocation size which depends on element count in vector register. + // So the current `expected_allocation_size` in the test is targeted on real AVX512 platforms with vector registers with 512 bits. + // If the test infrastructure has AVX2, the allocation size will not be matched. + if (m_linear_ir.is_dynamic() && !with_cpu_x86_avx512_core()) + GTEST_SKIP(); Validate(); }