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Bootstrapped in 2014 as a Google Summer of Code Project under BeagleBoard.org.
NEWS (July 2020) : BeagleLogic is out of limbo and has successfully been ported to the 5.4-ti kernel. More info and document reorganisation in the coming weeks.
NEWS (October 2017) : Announcing BeagleLogic Standalone - a turnkey logic analyzer based on BeagleLogic NEWS (July 2016) : Introducing analog sampling in BeagleLogic through PRUDAQ. Read here.
BeagleLogic now has a forum at https://groups.google.com/forum/#!forum/beaglelogic . Please use this discussions related to the BeagleLogic project. If you find a bug in the code, please open a GitHub issue.
BeagleLogic "no-setup-required" setup - get the SD Card image now!
The BeagleLogic cape. Click here for more details.
Want to know the internals of BeagleLogic?
Please consider filling up this short survey if you are interested to be a part of the batch of assembled capes when it becomes available.
BeagleLogic turns your BeagleBone [Black] into a 14-channel, 100Msps Logic Analyzer. Once loaded, it presents itself as a character device node /dev/beaglelogic.
The core of the logic analyzer is the 'beaglelogic' kernel module that reserves memory for and drives the two Programmable Real-Time Units (PRU) via the remoteproc interface wherein the PRU directly writes logic samples to the System Memory (DDR RAM) at the configured sample rate one-shot or continuously without intervention from the ARM core.
BeagleLogic can be used stand-alone for doing binary captures without any special client software.
dd if=/dev/beaglelogic of=mydump bs=1M count=1
is sufficient to grab a binary dump, once sample rate has been configured via sysfs.
When used in conjunction with the sigrok library, BeagleLogic supports software triggers and decoding over 30 different digital protocols. Since the BeagleLogic bindings for libsigrok have been merged upstream, the latest built-from-source sigrok libraries and tools support capturing from BeagleLogic.
BeagleLogic also offers a web interface (demo) which, once installed on the BeagleBone, can be accessed from port 4000 and can be used for low-volume captures (upto 3K samples). It makes BeagleLogic a useful tool for beginners as a learning tool to learn about digital protocols.
Core Specifications:
- Sample Rate: 10 Hz to 100 MHz [(100/N) MHz; integer N]
- Sample Size: 8-bit or 16-bit [a maximum of 14 inputs: P8_39 to P8_46, P8_27 to P8_30, P8_20 and P8_21 (after disabling the eMMC)]
- Sample Depth: Depends on the free RAM in the system. Starting from a minimum of 8 MB upto 320 MB of the system RAM can be reserved for BeagleLogic operation.
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Sampling Mode: One-Shot or Continuous Sampling, software-triggered [in conjunction with sigrok]
Please Note: Continuous Sampling is subject to constraints on the link between the RAM and secondary storage/PC and CPU processing time before buffers begin to be dropped.