-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathTest1.qsf
91 lines (89 loc) · 4.28 KB
/
Test1.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition
# Date created = 16:03:37 October 04, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Test1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5T144C8
set_global_assignment -name TOP_LEVEL_ENTITY Test1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:03:37 OCTOBER 04, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "12.0 SP2"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name VHDL_FILE Test1.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_144 -to PB
set_location_assignment PIN_9 -to LED3
set_location_assignment PIN_3 -to LED1
set_location_assignment PIN_7 -to LED2
set_location_assignment PIN_132 -to HEX0[0]
set_location_assignment PIN_126 -to HEX0[1]
set_location_assignment PIN_122 -to HEX0[2]
set_location_assignment PIN_120 -to HEX0[3]
set_location_assignment PIN_118 -to HEX0[4]
set_location_assignment PIN_114 -to HEX0[5]
set_location_assignment PIN_112 -to HEX0[6]
set_location_assignment PIN_96 -to BCD0[0]
set_location_assignment PIN_99 -to BCD0[1]
set_location_assignment PIN_101 -to BCD0[2]
set_location_assignment PIN_104 -to BCD0[3]
set_global_assignment -name VHDL_FILE seg_display.vhd
set_location_assignment PIN_71 -to STB
set_location_assignment PIN_41 -to SRV0
set_global_assignment -name VHDL_FILE angle_selector.vhd
set_location_assignment PIN_133 -to HEX1[0]
set_location_assignment PIN_129 -to HEX1[1]
set_location_assignment PIN_125 -to HEX1[2]
set_location_assignment PIN_121 -to HEX1[3]
set_location_assignment PIN_119 -to HEX1[4]
set_location_assignment PIN_115 -to HEX1[5]
set_location_assignment PIN_113 -to HEX1[6]
set_location_assignment PIN_94 -to BCD1[0]
set_location_assignment PIN_97 -to BCD1[1]
set_location_assignment PIN_100 -to BCD1[2]
set_location_assignment PIN_103 -to BCD1[3]
set_location_assignment PIN_134 -to LEDN
set_location_assignment PIN_93 -to NEG
set_location_assignment PIN_40 -to SRV1
set_global_assignment -name VHDL_FILE pwm_clock.vhd
set_location_assignment PIN_17 -to CLK_50
set_global_assignment -name MISC_FILE "G:/Workspaces/Quartus/Miniboard/Test/Test1.dpf"
set_global_assignment -name VHDL_FILE sampling_clock.vhd
set_global_assignment -name VHDL_FILE delay_clock.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top