From 01111c512ced3faaeae12a875e7a21f115580c63 Mon Sep 17 00:00:00 2001 From: alaindargelas <63669492+alaindargelas@users.noreply.github.com> Date: Thu, 26 Oct 2023 21:28:51 -0700 Subject: [PATCH] Fix bug with typespecs declared in package (#2097) Co-authored-by: Krzysztof Bieganski --- tests/formal/passlist.txt | 1 + tests/simple_tests/PackageLogicTypespec/Makefile.in | 2 ++ tests/simple_tests/PackageLogicTypespec/dut.sv | 9 +++++++++ tests/simple_tests/PackageLogicTypespec/yosys_script.tcl | 6 ++++++ 4 files changed, 18 insertions(+) create mode 100644 tests/simple_tests/PackageLogicTypespec/Makefile.in create mode 100644 tests/simple_tests/PackageLogicTypespec/dut.sv create mode 100644 tests/simple_tests/PackageLogicTypespec/yosys_script.tcl diff --git a/tests/formal/passlist.txt b/tests/formal/passlist.txt index 696e82fff..bb6657703 100644 --- a/tests/formal/passlist.txt +++ b/tests/formal/passlist.txt @@ -156,6 +156,7 @@ simple:OneReplicate/dut.v simple:OneStruct/dut.sv simple:OneSysFunc/dut.v simple:PackageCast/dut.v +simple:PackageLogicTypespec/dut.sv simple:PackedArray/top.sv simple:PackedArrayPort/top.sv simple:ParameterColonReference/top.sv diff --git a/tests/simple_tests/PackageLogicTypespec/Makefile.in b/tests/simple_tests/PackageLogicTypespec/Makefile.in new file mode 100644 index 000000000..a1e826ead --- /dev/null +++ b/tests/simple_tests/PackageLogicTypespec/Makefile.in @@ -0,0 +1,2 @@ +TEST_FILES := $(TEST_DIR)/dut.sv +TOP_MODULE := dut diff --git a/tests/simple_tests/PackageLogicTypespec/dut.sv b/tests/simple_tests/PackageLogicTypespec/dut.sv new file mode 100644 index 000000000..41f4d84e7 --- /dev/null +++ b/tests/simple_tests/PackageLogicTypespec/dut.sv @@ -0,0 +1,9 @@ +package my_pkg; + + typedef logic [31:0] my_type_t; + +endpackage + +module dut (input wire clk, input my_pkg::my_type_t my_in, output logic [31:0] my_out); + assign my_out = my_in; +endmodule diff --git a/tests/simple_tests/PackageLogicTypespec/yosys_script.tcl b/tests/simple_tests/PackageLogicTypespec/yosys_script.tcl new file mode 100644 index 000000000..1de368c43 --- /dev/null +++ b/tests/simple_tests/PackageLogicTypespec/yosys_script.tcl @@ -0,0 +1,6 @@ +source ../yosys_common.tcl + +prep -top \\dut +write_verilog +write_verilog yosys.sv +sim -clock clk -rstlen 10 -vcd dump.vcd