A few questions about the 4004..

[veniamin-ilmer]

The instructions SRC and DCL save an io address / bank to read/write from the rom/ram.
Where is this address saved to?
Are there extra registers on the 4004 where the SRC address and DCL bank gets saved? Or is this save handled by the RAM or ROM chips? Or is it saved on the board somehow?

The WPM instruction is the most confusing to me. Where is the "Program RAM" stored? Is it ultimately writing to the RAM, or the ROM or someplace else? Why use this instruction instead of WRM for example?

Thank you!

[alshapton]

Hi there @veniamin-ilmer .

I hope I can answer your questions, and thanks so much for being interested in Pyntel4004 !

For the SRC command, what is needed as a prerequisite is for an 8 bit address to be stored in a register pair (say RP2 - that is registers 2 and 3). The 8 bits contained in the register pair specified by RP are then used in conjunction with the previous DCL instruction (which selects the designated RAM Bank) to apply the address in the way the programmer wishes to that specified RAM Bank.

For reference, these instructions are explained in the documentation source here and here

In terms of where those values are saved i.e. where is the RAM Bank value saved and where is the address saved ? The answers to those questions lie in the hardware of the 4004 and supporting chipset.

Looking here at the pins marked CM0 - CM3, when a DCL instruction is issued, any one of the 16 RAM Banks can be selected, then the four pins representing the binary value of that RAM Bank are set to high (i.e. with a voltage). This selects the desired RAM Bank. The value is also stored in the 4004s "CM-RAM register" (implemented in the code by the class property "CURRENT_RAM_BANK". The CM-RAM register (a hardware non-directly accessible register to the user, but only settable by the DCL instruction) can be seen in the "including external image" on this [page[(https://pyntel4004.readthedocs.io/en/latest/intro/4004.html) (description of the i4004's hardware).

Or, put another way, both the DCL and SRC instructions don't technically "save" the data anywhere, they lift address line voltages (which stay until other DCL/SRC instructions change them) on address lines on specific RAM chips - the DCL will use the 4 output selector lines CM0-CM3 on the i4004 to select the current RAM Bank, and the selected Bank will have its' CM pin (or it's P0 pin) used to select it's "current-ness" - see here for the different methods to select an active i4002 chip. For transmission of the 8-bit address to the chip , the clock cycles 2 and 3 are used (again - see the previous link for information).

Section 4, Page 13 of this document may also help.

On to "WPM" now. I must confess when I started writing Pyntel4004 I kinda struggled to understand this concept too. I understand that there are two types of RAM available to the i4004 (actually, the MCS-4, which is a fully-loaded 400x computer). What I didn't realise early on was that there were expansion modules available, for which memory could be extended (program RAM and data RAM).

First of all, you need to remember that the WPM instruction is only used (and indeed, only valid) with an MCS-4 setup that. includes an additional i4008/i4009 OR an additional i4289.(The i4008 is an 8-bit address latch for access to standard memory chips, and one built-in 4-bit chip select and I/O port and the i4009 is a program and I/O access converter to standard memory and I/O chips, whereas the i4289 is a so-called "Standard Memory Interface").

Why the difference then ? simply because the chips as mentioned allow extending the memory available to the i4004 to a bigger addressable size (and then using a different set of data lines, the i4004 needs to "know" what to trigger to select, store, etc, the data from the accumulator to a memory location).

Perhaps this will help:

"The MCS-4 can have up to 4K x 8-bit ROM words, 1280 x 4-bit RAM characters and 128 I/O lines, without requiring any interface logic. By adding a few extra gates, the MCS-4 can have up to 48 RAM and ROM packages in any combination and 192 I/O lines."

This is an extract from here which specified at a high level the basic i4004/MCS-4 setup.

Please reach out if the explanation isn't sufficient, or (maybe) raises more questions. If you like, I/we can come up for some wording to include in the documentation for this project a FAQ to answer these and possibly more questions.

REALLY pleased you have taken the time !

Andrew