From d986b60e032f9b79f15c008fe3ae786f9cba7ce7 Mon Sep 17 00:00:00 2001 From: bunnie Date: Thu, 9 Aug 2018 03:04:34 +0800 Subject: [PATCH 1/2] add 400MHz tap setting (valid for -3 and -2/2E speed grades) --- litedram/phy/s7ddrphy.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index 4e945878..7a27dace 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -76,7 +76,9 @@ def __init__(self, pads, with_odelay, memtype="DDR3", nphases=4, sys_clk_freq=10 iodelay_tap_average = { 200e6: 78e-12, 300e6: 52e-12, + 400e6: 39e-12, } + half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq])) self._half_sys8x_taps = CSRStorage(4, reset=half_sys8x_taps) From 48230583b992e5269af19ef6d90fc60c04471efa Mon Sep 17 00:00:00 2001 From: Tim Ansell Date: Wed, 8 Aug 2018 13:31:11 -0700 Subject: [PATCH 2/2] Adding comment to iodelay_tap_average dictionary. --- litedram/phy/s7ddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index 7a27dace..4f39a20d 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -76,7 +76,7 @@ def __init__(self, pads, with_odelay, memtype="DDR3", nphases=4, sys_clk_freq=10 iodelay_tap_average = { 200e6: 78e-12, 300e6: 52e-12, - 400e6: 39e-12, + 400e6: 39e-12, # Only valid for -3 and -2/2E speed grades } half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))