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raveline-camera.dtsi
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#include <dt-bindings/msm-camera.h>
&tlmm {
cci_sda0_active: cci_sda0_active {
mux {
/* CLK, DATA */
pins = "gpio44";
function = "cci_i2c_sda0";
};
config {
pins = "gpio44";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci_sda0_suspend: cci_sda0_suspend {
mux {
/* CLK, DATA */
pins = "gpio44";
function = "cci_i2c_sda0";
};
config {
pins = "gpio44";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_scl0_active: cci_scl0_active {
mux {
/* CLK, DATA */
pins = "gpio45";
function = "cci_i2c_scl0";
};
config {
pins = "gpio45";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci_scl0_suspend: cci_scl0_suspend {
mux {
/* CLK, DATA */
pins = "gpio45";
function = "cci_i2c_scl0";
};
config {
pins = "gpio45";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_sda1_active: cci_sda1_active {
mux {
/* CLK, DATA */
pins = "gpio46";
function = "cci_i2c_sda1";
};
config {
pins = "gpio46";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci_sda1_suspend: cci_sda1_suspend {
mux {
/* CLK, DATA */
pins = "gpio46";
function = "cci_i2c_sda1";
};
config {
pins = "gpio46";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_scl1_active: cci_scl1_active {
mux {
/* CLK, DATA */
pins = "gpio47";
function = "cci_i2c_scl1";
};
config {
pins = "gpio47";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci_scl1_suspend: cci_scl1_suspend {
mux {
/* CLK, DATA */
pins = "gpio47";
function = "cci_i2c_scl1";
};
config {
pins = "gpio47";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_sda2_active: cci_sda2_active {
mux {
/* CLK, DATA */
pins = "gpio48";
function = "cci_i2c_sda2";
};
config {
pins = "gpio48";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci_sda2_suspend: cci_sda2_suspend {
mux {
/* CLK, DATA */
pins = "gpio48";
function = "cci_i2c_sda2";
};
config {
pins = "gpio48";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_scl2_active: cci_scl2_active {
mux {
/* CLK, DATA */
pins = "gpio49";
function = "cci_i2c_scl2";
};
config {
pins = "gpio49";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci_scl2_suspend: cci_scl2_suspend {
mux {
/* CLK, DATA */
pins = "gpio49";
function = "cci_i2c_scl2";
};
config {
pins = "gpio49";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk0_active: cam_sensor_mclk0_active {
/* MCLK0 */
mux {
pins = "gpio36";
function = "cam_mclk";
};
config {
pins = "gpio36";
bias-disable; /* No PULL */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
/* MCLK0 */
mux {
pins = "gpio36";
function = "cam_mclk";
};
config {
pins = "gpio36";
bias-pull-down; /* PULL DOWN */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_mclk1_active: cam_sensor_mclk1_active {
/* MCLK1 */
mux {
pins = "gpio37";
function = "cam_mclk";
};
config {
pins = "gpio37";
bias-disable; /* No PULL */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
/* MCLK1 */
mux {
pins = "gpio37";
function = "cam_mclk";
};
config {
pins = "gpio37";
bias-pull-down; /* PULL DOWN */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_mclk2_active: cam_sensor_mclk2_active {
/* MCLK2 */
mux {
pins = "gpio38";
function = "cam_mclk";
};
config {
pins = "gpio38";
bias-disable; /* No PULL */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
/* MCLK2 */
mux {
pins = "gpio38";
function = "cam_mclk";
};
config {
pins = "gpio38";
bias-pull-down; /* PULL DOWN */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_mclk3_active: cam_sensor_mclk3_active {
/* MCLK3 */
mux {
pins = "gpio39";
function = "cam_mclk";
};
config {
pins = "gpio39";
bias-disable; /* No PULL */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
/* MCLK3 */
mux {
pins = "gpio39";
function = "cam_mclk";
};
config {
pins = "gpio39";
bias-pull-down; /* PULL DOWN */
drive-strength = <6>; /* 6 MA */
};
};
cam_sensor_active_rst0: cam_sensor_active_rst0 {
/* RESET REAR */
mux {
pins = "gpio40";
function = "gpio";
};
config {
pins = "gpio40";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 {
/* RESET REAR */
mux {
pins = "gpio40";
function = "gpio";
};
config {
pins = "gpio40";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst1: cam_sensor_active_rst1 {
/* RESET REARAUX */
mux {
pins = "gpio41";
function = "gpio";
};
config {
pins = "gpio41";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 {
/* RESET REARAUX */
mux {
pins = "gpio41";
function = "gpio";
};
config {
pins = "gpio41";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst2: cam_sensor_active_rst2 {
/* RESET 2 */
mux {
pins = "gpio42";
function = "gpio";
};
config {
pins = "gpio42";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 {
/* RESET 2 */
mux {
pins = "gpio42";
function = "gpio";
};
config {
pins = "gpio42";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst3: cam_sensor_active_rst3 {
/* RESET 3 */
mux {
pins = "gpio43";
function = "gpio";
};
config {
pins = "gpio43";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 {
/* RESET 3 */
mux {
pins = "gpio43";
function = "gpio";
};
config {
pins = "gpio43";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active {
/* CSIMUX_SEL */
mux {
pins = "gpio106";
function = "gpio";
};
config {
pins = "gpio106";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend {
/* CSIMUX_SEL */
mux {
pins = "gpio106";
function = "gpio";
};
config {
pins = "gpio106";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
qcom,cam-req-mgr {
compatible = "qcom,cam-req-mgr";
status = "ok";
};
qcom,cam-sync {
compatible = "qcom,cam-sync";
status = "ok";
};
cam_csiphy0: qcom,csiphy0@ace4000 {
cell-index = <0>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = < 0x0ace4000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xe4000>;
interrupt-names = "CSIPHY0";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "csi-vdd-1p2", "csi-vdd-0p9";
camss-supply = <&cam_cc_camss_top_gdsc>;
csi-vdd-1p2-supply = <&L16B>;
csi-vdd-0p9-supply = <&L5B>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
rgltr-min-voltage = <0 1140000 830000>;
rgltr-max-voltage = <0 1260000 920000>;
rgltr-load-current = <0 26940 48210>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
"csi0phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>;
src-clock-name = "csi0phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
clock-rates =
<300000000 0 300000000 0>,
<400000000 0 300000000 0>,
<400000000 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy1: qcom,csiphy1@ace6000 {
cell-index = <1>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0xace6000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xe6000>;
interrupt-names = "CSIPHY1";
interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "csi-vdd-1p2", "csi-vdd-0p9";
camss-supply = <&cam_cc_camss_top_gdsc>;
csi-vdd-1p2-supply = <&L16B>;
csi-vdd-0p9-supply = <&L5B>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
rgltr-min-voltage = <0 1140000 830000>;
rgltr-max-voltage = <0 1260000 920000>;
rgltr-load-current = <0 26940 48210>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
"csi1phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>;
src-clock-name = "csi1phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
clock-rates =
<300000000 0 300000000 0>,
<400000000 0 300000000 0>,
<400000000 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy2: qcom,csiphy2@ace8000 {
cell-index = <2>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0xace8000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xe8000>;
interrupt-names = "CSIPHY2";
interrupts = <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "csi-vdd-1p2", "csi-vdd-0p9";
camss-supply = <&cam_cc_camss_top_gdsc>;
csi-vdd-1p2-supply = <&L16B>;
csi-vdd-0p9-supply = <&L5B>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
rgltr-min-voltage = <0 1140000 830000>;
rgltr-max-voltage = <0 1260000 920000>;
rgltr-load-current = <0 26940 48210>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy2_clk",
"csi2phytimer_clk_src",
"csi2phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY2_CLK>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK>;
src-clock-name = "csi2phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
clock-rates =
<300000000 0 300000000 0>,
<400000000 0 300000000 0>,
<400000000 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_cci0: qcom,cci0@ac15000 {
cell-index = <0>;
compatible = "qcom,cci", "simple-bus";
reg = <0xac15000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x15000>;
interrupt-names = "cci0";
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_camss_top_gdsc>;
clock-names = "cci_0_clk_src",
"cci_0_clk";
clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK>;
clock-rates = <37500000 0>;
clock-cntl-level = "lowsvs";
src-clock-name = "cci_0_clk_src";
pctrl-idx-mapping = <CCI_MASTER_0 CCI_MASTER_1>;
pctrl-map-names = "m0", "m1";
pinctrl-names = "m0_active", "m0_suspend",
"m1_active", "m1_suspend";
pinctrl-0 = <&cci_sda0_active
&cci_scl0_active>;
pinctrl-1 = <&cci_sda0_suspend
&cci_scl0_suspend>;
pinctrl-2 = <&cci_sda1_active
&cci_scl1_active>;
pinctrl-3 = <&cci_sda1_suspend
&cci_scl1_suspend>;
status = "ok";
i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci0: qcom,i2c_custom_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <1>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
cam_cci1: qcom,cci1@ac16000 {
cell-index = <1>;
compatible = "qcom,cci", "simple-bus";
reg = <0xac16000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x16000>;
interrupt-names = "cci1";
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_camss_top_gdsc>;
clock-names = "cci_1_clk_src",
"cci_1_clk";
clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK>;
clock-rates = <37500000 0>;
clock-cntl-level = "lowsvs";
src-clock-name = "cci_1_clk_src";
pctrl-idx-mapping = <CCI_MASTER_0>;
pctrl-map-names = "m0";
pinctrl-names = "m0_active", "m0_suspend";
pinctrl-0 = <&cci_sda2_active
&cci_scl2_active>;
pinctrl-1 = <&cci_sda2_suspend
&cci_scl2_suspend>;
status = "ok";
i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci1: qcom,i2c_custom_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <1>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu", "simple-bus";
status = "ok";
force_cache_allocs;
need_shared_buffer_padding;
msm_cam_smmu_tfe {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x8A0 0x420>,
<&apps_smmu 0x880 0x420>,
<&apps_smmu 0xCA0 0x420>,
<&apps_smmu 0xC80 0x420>;
qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
dma-coherent;
cam-smmu-label = "tfe";
tfe_iova_mem_map: iova-mem-map {
/* IO region is approximately 3.4 GB */
iova-mem-region-io {
iova-region-name = "io";
/* 1 MB pad for start */
iova-region-start = <0x100000>;
/* 1 MB pad for end */
iova-region-len = <0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_icp {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1840 0x00A0>,
<&apps_smmu 0x1860 0x00A0>,
<&apps_smmu 0x18E0 0x00A0>,
<&apps_smmu 0x1900 0x0000>,
<&apps_smmu 0x1820 0x0000>;
cam-smmu-label = "icp";
qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
iova-region-discard = <0xe0000000 0x800000>;
dma-coherent;
icp_iova_mem_map: iova-mem-map {
iova-mem-region-shared {
/* Shared region is ~250MB long */
iova-region-name = "shared";
iova-region-start = <0x800000>;
iova-region-len = <0xFC00000>;
iova-region-id = <0x1>;
status = "ok";
};
iova-mem-region-fwuncached-region {
/* FW uncached region is 7MB long */
iova-region-name = "fw_uncached";
iova-region-start = <0x10400000>;
iova-region-len = <0x700000>;
iova-region-id = <0x6>;
status = "ok";
};
iova-mem-region-io {
/* IO region is approximately 3.8 GB */
iova-region-name = "io";
iova-region-start = <0x10c00000>;
iova-region-len = <0xee300000>;
iova-region-id = <0x3>;
iova-region-discard = <0xe0000000 0x800000>;
status = "ok";
};
iova-mem-qdss-region {
/* QDSS region is appropriate 1MB */
iova-region-name = "qdss";
iova-region-start = <0x10b00000>;
iova-region-len = <0x100000>;
iova-region-id = <0x5>;
qdss-phy-addr = <0x16790000>;
status = "ok";
};
};
};
msm_cam_smmu_cre {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1920 0x0000>,
<&apps_smmu 0x1940 0x0000>;
multiple-client-devices;
qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
cam-smmu-label = "cre";
dma-coherent;
cre_iova_mem_map: iova-mem-map {
/* IO region is approximately 3.4 GB */
iova-mem-region-io {
iova-region-name = "io";
/* 1 MB pad for start */
iova-region-start = <0x100000>;
/* 1 MB pad for end */
iova-region-len = <0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_cpas_cdm {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1800 0x0000>;
cam-smmu-label = "cpas-cdm";
qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
dma-coherent;
multiple-client-devices;
cpas_cdm_iova_mem_map: iova-mem-map {
iova-mem-region-io {
iova-region-name = "io";
/* 1 MB pad for start */
iova-region-start = <0x100000>;
/* 1 MB pad for end */
iova-region-len = <0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_secure {
compatible = "qcom,msm-cam-smmu-cb";
cam-smmu-label = "cam-secure";
qcom,secure-cb;
};
};
qcom,cam-cpas@ac13000 {
cell-index = <0>;
compatible = "qcom,cam-cpas";
label = "cpas";
arch-compat = "cpas_top";
reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh";
reg = <0xac13000 0x1000>,
<0xac19000 0x8000>,
<0xbbf0000 0x1F00>;
reg-cam-base = <0x13000 0x19000 0x0bbf0000>;
interrupt-names = "cpas_camnoc";
interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>;
camnoc-axi-min-ib-bw = <3000000000>;
regulator-names = "camss";
camss-supply = <&cam_cc_camss_top_gdsc>;
clock-names =
"sys_tmr_clk",
"soc_ahb_clk",
"slow_ahb_clk_src",
"cpas_ahb_clk",
"core_ahb_clk",
"fast_ahb_clk_src",
"camnoc_axi_clk_src",
"camnoc_axi_clk",
"camnoc_axi_hf_clk",
"camnoc_axi_sf_clk";
clocks =
<&camcc CAM_CC_SYS_TMR_CLK>,
<&camcc CAM_CC_SOC_AHB_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CORE_AHB_CLK>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_CAMNOC_AXI_HF_CLK>,
<&camcc CAM_CC_CAMNOC_AXI_SF_CLK>;
clock-rates =
<0 0 0 0 0 0 0 0 0 0>,
<0 0 80000000 0 0 100000000 150000000 0 0 0>,
<0 0 80000000 0 0 150000000 240000000 0 0 0>,
<0 0 80000000 0 0 200000000 300000000 0 0 0>,
<0 0 80000000 0 0 240000000 400000000 0 0 0>,
<0 0 80000000 0 0 240000000 400000000 0 0 0>;
clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1",
"nominal", "turbo";
src-clock-name = "camnoc_axi_clk_src";
control-camnoc-axi-clk;
camnoc-bus-width = <32>;
camnoc-axi-clk-bw-margin-perc = <20>;
interconnect-names = "cam_ahb";
interconnects =<&gem_noc MASTER_APPSS_PROC
&cnoc2 SLAVE_CAMERA_CFG>;
rpmh-bcm-info = <12 0x4 0x800 0 4>;
cam-ahb-num-cases = <8>;
cam-ahb-bw-KBps =
<0 0>, <0 133320>, <0 150000>, <0 150000>,<0 150000>,
<0 300000>, <0 300000>, <0 300000>;
vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
RPMH_REGULATOR_LEVEL_MIN_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_SVS
RPMH_REGULATOR_LEVEL_SVS_L1
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM_L1
RPMH_REGULATOR_LEVEL_NOM_L2
RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_TURBO_L1>;
vdd-corner-ahb-mapping = "suspend", "lowsvs",
"lowsvs", "svs", "svs_l1",
"nominal", "nominal", "nominal",
"turbo", "turbo";
client-id-based;
client-names =
"csiphy0", "csiphy1", "csiphy2", "cci0", "cci1",
"csid0", "csid1", "tfe0", "tfe1", "ipe0",
"cpas-cdm0-top", "cpas-cdm0-ope", "cpas-cdm0-bps", "cam-cdm-intf0", "bps0",
"icp0", "tpg13", "tpg14", "cre0";
status = "ok";
camera-bus-nodes {
level3-nodes {
level-index = <3>;
level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum {
cell-index = <0>;
node-name = "level3-rt0-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
ib-bw-voting-needed;
qcom,axi-port-mnoc {
interconnect-names = "cam_hf_0";
interconnects =
<&mmss_noc MASTER_CAMNOC_HF
&mc_virt SLAVE_EBI1>;
};
};
level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
cell-index = <1>;
node-name = "level3-nrt0-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
qcom,axi-port-mnoc {
interconnect-names = "cam_sf_0";
interconnects =
<&mmss_noc MASTER_CAMNOC_SF
&mc_virt SLAVE_EBI1>;
};
};
level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
cell-index = <2>;
node-name = "level3-nrt1-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
qcom,axi-port-mnoc {
interconnect-names =
"cam_sf_icp";
interconnects =
<&mmss_noc MASTER_CAMNOC_ICP
&mc_virt SLAVE_EBI1>;
};
};
};
level2-nodes {
level-index = <2>;
camnoc-max-needed;
level2_rt0_wr: level2-rt0-wr {
cell-index = <3>;
node-name = "level2-rt0-wr";
parent-node = <&level3_rt0_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_rt0_rd: level2-rt0-rd {