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shima-camera.dtsi
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#include <dt-bindings/msm/msm-camera.h>
&soc {
qcom,cam-req-mgr {
compatible = "qcom,cam-req-mgr";
status = "ok";
};
qcom,cam-sync {
compatible = "qcom,cam-sync";
status = "ok";
};
cam_csiphy0: qcom,csiphy0 {
cell-index = <0>;
compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
reg = <0x0ac6a000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x6a000>;
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-1p2-supply = <&L6B>;
csi-vdd-0p9-supply = <&L10C>;
regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
"csi-vdd-0p9";
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 1200000 880000>;
rgltr-max-voltage = <0 0 1260000 1050000>;
rgltr-load-current = <0 0 54000 96400>;
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
"csi0phytimer_clk";
src-clock-name = "csi0phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs";
clock-rates =
<266666667 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy1: qcom,csiphy1 {
cell-index = <1>;
compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
reg = <0xac6c000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x6c000>;
interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy1";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-1p2-supply = <&L6B>;
csi-vdd-0p9-supply = <&L10C>;
regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
"csi-vdd-0p9";
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 1200000 880000>;
rgltr-max-voltage = <0 0 1260000 1050000>;
rgltr-load-current = <0 0 54000 96400>;
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
"csi1phytimer_clk";
src-clock-name = "csi1phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs";
clock-rates =
<266666667 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy2: qcom,csiphy2 {
cell-index = <2>;
compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
reg = <0xac6e000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x6e000>;
interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy2";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-1p2-supply = <&L6B>;
csi-vdd-0p9-supply = <&L10C>;
regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
"csi-vdd-0p9";
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 1200000 880000>;
rgltr-max-voltage = <0 0 1260000 1050000>;
rgltr-load-current = <0 0 54000 96400>;
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY2_CLK>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy2_clk",
"csi2phytimer_clk_src",
"csi2phytimer_clk";
src-clock-name = "csi2phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs";
clock-rates =
<266666667 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy3: qcom,csiphy3 {
cell-index = <3>;
compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
reg = <0xac70000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x70000>;
interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy3";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-1p2-supply = <&L6B>;
csi-vdd-0p9-supply = <&L10C>;
regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
"csi-vdd-0p9";
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 1200000 880000>;
rgltr-max-voltage = <0 0 1260000 1050000>;
rgltr-load-current = <0 0 54000 96400>;
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY3_CLK>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy3_clk",
"csi3phytimer_clk_src",
"csi3phytimer_clk";
src-clock-name = "csi3phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs";
clock-rates =
<266666667 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy4: qcom,csiphy4 {
cell-index = <4>;
compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
reg = <0xac72000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x72000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy4";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-1p2-supply = <&L6B>;
csi-vdd-0p9-supply = <&L10C>;
regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
"csi-vdd-0p9";
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 1200000 880000>;
rgltr-max-voltage = <0 0 1260000 1050000>;
rgltr-load-current = <0 0 54000 96400>;
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY4_CLK>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy4_clk",
"csi4phytimer_clk_src",
"csi4phytimer_clk";
src-clock-name = "csi4phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs";
clock-rates =
<266666667 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy5: qcom,csiphy5 {
cell-index = <5>;
compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";
reg = <0xac74000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x74000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy5";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-1p2-supply = <&L6B>;
csi-vdd-0p9-supply = <&L10C>;
regulator-names = "gdscr", "refgen", "csi-vdd-1p2",
"csi-vdd-0p9";
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 1200000 880000>;
rgltr-max-voltage = <0 0 1260000 1050000>;
rgltr-load-current = <0 0 54000 96400>;
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY5_CLK>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy5_clk",
"csi5phytimer_clk_src",
"csi5phytimer_clk";
src-clock-name = "csi5phytimer_clk_src";
clock-cntl-level = "lowsvs", "svs";
clock-rates =
<266666667 0 300000000 0>,
<400000000 0 300000000 0>;
status = "ok";
};
cam_cci0: qcom,cci0 {
cell-index = <0>;
compatible = "qcom,cci", "simple-bus";
reg = <0xac4f000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x4f000>;
interrupt-names = "cci";
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
status = "ok";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
regulator-names = "gdscr";
clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK>;
clock-names = "cci_0_clk_src",
"cci_0_clk";
src-clock-name = "cci_0_clk_src";
clock-cntl-level = "lowsvs";
clock-rates = <37500000 0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cci0_active &cci1_active>;
pinctrl-1 = <&cci0_suspend &cci1_suspend>;
gpios = <&tlmm 107 0>,
<&tlmm 108 0>,
<&tlmm 109 0>,
<&tlmm 110 0>;
gpio-req-tbl-num = <0 1 2 3>;
gpio-req-tbl-flags = <1 1 1 1>;
gpio-req-tbl-label = "CCI_I2C_DATA0",
"CCI_I2C_CLK0",
"CCI_I2C_DATA1",
"CCI_I2C_CLK1";
i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci0: qcom,i2c_custom_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <1>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
cam_cci1: qcom,cci1 {
cell-index = <1>;
compatible = "qcom,cci", "simple-bus";
reg = <0xac50000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x50000>;
interrupt-names = "cci";
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
status = "ok";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
regulator-names = "gdscr";
clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK>;
clock-names = "cci_1_clk_src",
"cci_1_clk";
src-clock-name = "cci_1_clk_src";
clock-cntl-level = "lowsvs";
clock-rates = <37500000 0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cci2_active &cci3_active>;
pinctrl-1 = <&cci2_suspend &cci3_suspend>;
gpios = <&tlmm 111 0>,
<&tlmm 112 0>,
<&tlmm 113 0>,
<&tlmm 114 0>;
gpio-req-tbl-num = <0 1 2 3>;
gpio-req-tbl-flags = <1 1 1 1>;
gpio-req-tbl-label = "CCI_I2C_DATA2",
"CCI_I2C_CLK2",
"CCI_I2C_DATA3",
"CCI_I2C_CLK3";
i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci1: qcom,i2c_custom_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <1>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu", "simple-bus";
status = "ok";
msm_cam_smmu_ife {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1000 0x440>,
<&apps_smmu 0x1040 0x440>,
<&apps_smmu 0x1400 0x440>,
<&apps_smmu 0x1440 0x440>;
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
dma-coherent-hint-cached;
cam-smmu-label = "ife", "ife-cdm";
multiple-client-devices;
ife_iova_mem_map: iova-mem-map {
/* IO region is approximately 3.4 GB */
iova-mem-region-io {
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_jpeg {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x2840 0x400>,
<&apps_smmu 0x2C40 0x400>;
cam-smmu-label = "jpeg";
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
dma-coherent-hint-cached;
jpeg_iova_mem_map: iova-mem-map {
/* IO region is approximately 3.4 GB */
iova-mem-region-io {
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_icp_fw {
compatible = "qcom,msm-cam-smmu-fw-dev";
label="icp";
memory-region = <&pil_camera_mem>;
};
msm_cam_smmu_icp {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x28E2 0x400>,
<&apps_smmu 0x2CE2 0x400>,
<&apps_smmu 0x2800 0x400>,
<&apps_smmu 0x2C00 0x400>,
<&apps_smmu 0x2860 0x400>,
<&apps_smmu 0x2C60 0x400>,
<&apps_smmu 0x2820 0x400>,
<&apps_smmu 0x2C20 0x400>;
qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
dma-coherent-hint-cached;
iova-region-discard = <0xdff00000 0x300000>;
cam-smmu-label = "icp";
icp_iova_mem_map: iova-mem-map {
iova-mem-region-firmware {
/* Firmware region is 5MB */
iova-region-name = "firmware";
iova-region-start = <0x0>;
iova-region-len = <0x500000>;
iova-region-id = <0x0>;
status = "ok";
};
iova-mem-region-shared {
/* Shared region is 150MB long */
iova-region-name = "shared";
iova-region-start = <0x7400000>;
iova-region-len = <0x9600000>;
iova-region-id = <0x1>;
status = "ok";
};
iova-mem-region-secondary-heap {
/* Secondary heap region is 1MB long */
iova-region-name = "secheap";
iova-region-start = <0x10a00000>;
iova-region-len = <0x100000>;
iova-region-id = <0x4>;
status = "ok";
};
iova-mem-region-io {
/* IO region is approximately 3.7 GB */
iova-region-name = "io";
iova-region-start = <0x10c00000>;
iova-region-len = <0xee300000>;
iova-region-discard = <0xdff00000 0x300000>;
iova-region-id = <0x3>;
status = "ok";
};
iova-mem-qdss-region {
/* QDSS region is appropriate 1MB */
iova-region-name = "qdss";
iova-region-start = <0x10b00000>;
iova-region-len = <0x100000>;
iova-region-id = <0x5>;
qdss-phy-addr = <0x16790000>;
status = "ok";
};
};
};
msm_cam_smmu_cpas_cdm {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x28C0 0x400>,
<&apps_smmu 0x2CC0 0x400>;
cam-smmu-label = "cpas-cdm";
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
dma-coherent-hint-cached;
cpas_cdm_iova_mem_map: iova-mem-map {
iova-mem-region-io {
/* IO region is approximately 3.4 GB */
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_secure {
compatible = "qcom,msm-cam-smmu-cb";
cam-smmu-label = "cam-secure";
qcom,secure-cb;
};
};
qcom,cam-cdm-intf {
compatible = "qcom,cam-cdm-intf";
cell-index = <0>;
label = "cam-cdm-intf";
num-hw-cdm = <1>;
cdm-client-names = "vfe",
"jpegdma",
"jpegenc";
status = "ok";
};
qcom,cpas-cdm0 {
cell-index = <0>;
compatible = "qcom,cam-cpas-cdm1_2";
label = "cpas-cdm";
reg = <0xac4d000 0x1000>;
reg-names = "cpas-cdm";
reg-cam-base = <0x4d000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "cpas-cdm";
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cam_cc_cpas_slow_ahb_clk",
"cam_cc_cpas_ahb_clk";
clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates = <0 0>;
clock-cntl-level = "svs";
cdm-client-names = "ife3", "ife4", "dualife";
status = "ok";
};
qcom,ife-cdm0 {
cell-index = <0>;
compatible = "qcom,cam-ife-cdm1_2";
label = "ife-cdm";
reg = <0xacb4200 0x1000>;
reg-names = "ife-cdm0";
reg-cam-base = <0xb4200>;
interrupts = <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ife-cdm0";
regulator-names = "camss","ife0";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife0-supply = <&cam_cc_ife_0_gdsc>;
clock-names = "ife_0_ahb",
"ife_0_areg",
"ife_clk",
"ife_axi_clk",
"cam_cc_cpas_ahb_clk";
clocks =
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates =
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
cdm-client-names = "ife0";
status = "ok";
};
qcom,ife-cdm1 {
cell-index = <1>;
compatible = "qcom,cam-ife-cdm1_2";
label = "ife-cdm";
reg = <0xacc3200 0x1000>;
reg-names = "ife-cdm1";
reg-cam-base = <0xc3200>;
interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ife-cdm1";
regulator-names = "camss","ife1";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife1-supply = <&cam_cc_ife_1_gdsc>;
clock-names = "ife_1_ahb",
"ife_1_areg",
"ife_clk",
"ife_axi_clk",
"cam_cc_cpas_ahb_clk";
clocks =
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates =
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
cdm-client-names = "ife1";
status = "ok";
};
qcom,ife-cdm2 {
cell-index = <2>;
compatible = "qcom,cam-ife-cdm1_2";
label = "ife-cdm";
reg = <0xacef200 0x1000>;
reg-names = "ife-cdm2";
reg-cam-base = <0xef200>;
interrupts = <GIC_SPI 642 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ife-cdm2";
regulator-names = "camss","ife2";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife2-supply = <&cam_cc_ife_2_gdsc>;
clock-names = "ife_2_ahb",
"ife_2_areg",
"ife_clk",
"ife_axi_clk",
"cam_cc_cpas_ahb_clk";
clocks =
<&camcc CAM_CC_IFE_2_AHB_CLK>,
<&camcc CAM_CC_IFE_2_AREG_CLK>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates =
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
cdm-client-names = "ife2";
status = "ok";
};
qcom,cam-isp {
compatible = "qcom,cam-isp";
arch-compat = "ife";
status = "ok";
};
cam_csid0: qcom,csid0 {
cell-index = <0>;
compatible = "qcom,csid580";
reg-names = "csid";
reg = <0xacb5200 0x1000>;
reg-cam-base = <0xb5200>;
interrupt-names = "csid0";
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife0";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife0-supply = <&cam_cc_ife_0_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_clk",
"ife_0_areg",
"ife_0_ahb",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>;
clock-rates =
<400000000 0 0 0 338000000 0 100000000 0 0>,
<400000000 0 0 0 475000000 0 200000000 0 0>,
<400000000 0 0 0 600000000 0 300000000 0 0>,
<400000000 0 0 0 720000000 0 400000000 0 0>,
<400000000 0 0 0 720000000 0 400000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe0: qcom,ife0 {
cell-index = <0>;
compatible = "qcom,vfe580";
reg-names = "ife", "cam_camnoc";
reg = <0xacb4000 0xd000>,
<0xac42000 0x8000>;
reg-cam-base = <0xb4000 0x42000>;
interrupt-names = "ife0";
interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife0";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife0-supply = <&cam_cc_ife_0_gdsc>;
clock-names =
"ife_0_ahb",
"ife_0_areg",
"ife_clk_src",
"ife_clk",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>;
clock-rates =
<0 100000000 338000000 0 0>,
<0 200000000 475000000 0 0>,
<0 300000000 600000000 0 0>,
<0 400000000 720000000 0 0>,
<0 400000000 720000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
scl-clk-names = "ife_0_areg";
clock-control-debugfs = "true";
clock-names-option = "ife_dsp_clk";
clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>;
clock-rates-option = <720000000>;
ubwc-static-cfg = <0x1016 0x1026>;
cam_hw_pid = < 28 4 16 8 >;
status = "ok";
};
cam_csid1: qcom,csid1 {
cell-index = <1>;
compatible = "qcom,csid580";
reg-names = "csid";
reg = <0xacc4200 0x1000>;
reg-cam-base = <0xc4200>;
interrupt-names = "csid1";
interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife1";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife1-supply = <&cam_cc_ife_1_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_clk",
"ife_1_areg",
"ife_1_ahb",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>;
clock-rates =
<400000000 0 0 0 338000000 0 100000000 0 0>,
<400000000 0 0 0 475000000 0 200000000 0 0>,
<400000000 0 0 0 600000000 0 300000000 0 0>,
<400000000 0 0 0 720000000 0 400000000 0 0>,
<400000000 0 0 0 720000000 0 400000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe1: qcom,ife1 {
cell-index = <1>;
compatible = "qcom,vfe580";
reg-names = "ife", "cam_camnoc";
reg = <0xacc3000 0xd000>,
<0xac42000 0x8000>;
reg-cam-base = <0xc3000 0x42000>;
interrupt-names = "ife1";
interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife1";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife1-supply = <&cam_cc_ife_1_gdsc>;
clock-names =
"ife_1_ahb",
"ife_1_areg",
"ife_clk_src",
"ife_clk",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>;
clock-rates =
<0 100000000 338000000 0 0>,
<0 200000000 475000000 0 0>,
<0 300000000 600000000 0 0>,
<0 400000000 720000000 0 0>,
<0 400000000 720000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
scl-clk-names = "ife_1_areg";
clock-control-debugfs = "true";
clock-names-option = "ife_dsp_clk";
clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>;
clock-rates-option = <720000000>;
ubwc-static-cfg = <0x1016 0x1026>;
cam_hw_pid = < 29 5 17 9 >;
status = "ok";
};
cam_csid2: qcom,csid2 {
cell-index = <2>;
compatible = "qcom,csid580";
reg-names = "csid";
reg = <0xacf0200 0x1000>;
reg-cam-base = <0xf0200>;
interrupt-names = "csid2";
interrupts = <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife2";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife2-supply = <&cam_cc_ife_2_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_clk",
"ife_2_areg",
"ife_2_ahb",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_2_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_AREG_CLK>,
<&camcc CAM_CC_IFE_2_AHB_CLK>,
<&camcc CAM_CC_IFE_2_AXI_CLK>;
clock-rates =
<400000000 0 0 0 338000000 0 100000000 0 0>,
<400000000 0 0 0 475000000 0 200000000 0 0>,
<400000000 0 0 0 600000000 0 300000000 0 0>,
<400000000 0 0 0 720000000 0 400000000 0 0>,
<400000000 0 0 0 720000000 0 400000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe2: qcom,ife2 {
cell-index = <2>;
compatible = "qcom,vfe580";
reg-names = "ife", "cam_camnoc";
reg = <0xacef000 0xd000>,
<0xac42000 0x8000>;
reg-cam-base = <0xef000 0x42000>;
interrupt-names = "ife2";
interrupts = <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife2";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife2-supply = <&cam_cc_ife_2_gdsc>;
clock-names =
"ife_2_ahb",
"ife_2_areg",
"ife_clk_src",
"ife_clk",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_2_AHB_CLK>,
<&camcc CAM_CC_IFE_2_AREG_CLK>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_AXI_CLK>;
clock-rates =
<0 100000000 338000000 0 0>,
<0 200000000 475000000 0 0>,
<0 300000000 600000000 0 0>,
<0 400000000 720000000 0 0>,
<0 400000000 720000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
scl-clk-names = "ife_2_areg";
clock-control-debugfs = "true";
ubwc-static-cfg = <0x1016 0x1026>;
cam_hw_pid = < 30 6 18 10>;
status = "ok";
};
cam_csid_lite0: qcom,csid-lite0 {
cell-index = <3>;
compatible = "qcom,csid-lite580";
reg-names = "csid-lite";
reg = <0xacd9200 0x1000>;
reg-cam-base = <0xd9200>;
interrupt-names = "csid-lite0";
interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_lite_ahb",
"ife_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>;
clock-rates =
<400000000 0 0 0 400000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe_lite0: qcom,ife-lite0 {
cell-index = <3>;
compatible = "qcom,vfe-lite580";
reg-names = "ife-lite";
reg = <0xacd9000 0x2200>;
reg-cam-base = <0xd9000>;
interrupt-names = "ife-lite0";
interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"ife_lite_ahb",
"ife_lite_axi",
"ife_clk_src",
"ife_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_AXI_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK>;
clock-rates =
<0 0 400000000 0>,