arm: remove up_set_current_regs/up_current_regs

arch/arm/include/arm/irq.h

@@ -156,17 +156,9 @@ struct xcptcontext
  * Public Data
  ****************************************************************************/
 
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure.  If is non-NULL only during interrupt
- * processing.  Access to g_current_regs[] must be through the
- * [get/set]_current_regs for portability.
- */
-
-/* For the case of architectures with multiple CPUs, then there must be one
- * such value for each processor that can receive an interrupt.
- */
+/* g_interrupt_context store irq status */
 
-extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
+extern volatile bool g_interrupt_context[CONFIG_SMP_NCPUS];
 
 /****************************************************************************
  * Inline functions
@@ -239,40 +231,17 @@ static inline irqstate_t up_irq_enable(void)
 int up_cpu_index(void) noinstrument_function;
 #endif /* CONFIG_ARCH_HAVE_MULTICPU */
 
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-#ifdef CONFIG_SMP
-  return (uint32_t *)g_current_regs[up_cpu_index()];
-#else
-  return (uint32_t *)g_current_regs[0];
-#endif
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-#ifdef CONFIG_SMP
-  g_current_regs[up_cpu_index()] = regs;
-#else
-  g_current_regs[0] = regs;
-#endif
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {
 #ifdef CONFIG_SMP
   irqstate_t flags = up_irq_save();
-#endif
-
-  bool ret = up_current_regs() != NULL;
-
-#ifdef CONFIG_SMP
+  bool ret = g_interrupt_context[up_cpu_index()];
   up_irq_restore(flags);
-#endif
-
   return ret;
+#else
+  return g_interrupt_context[0];
+#endif
 }
 
 /****************************************************************************

arch/arm/include/armv6-m/irq.h

@@ -192,18 +192,6 @@ struct xcptcontext
  * Public Data
  ****************************************************************************/
 
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure.  If is non-NULL only during interrupt
- * processing.  Access to g_current_regs[] must be through the
- * [get/set]_current_regs for portability.
- */
-
-/* For the case of architectures with multiple CPUs, then there must be one
- * such value for each processor that can receive an interrupt.
- */
-
-extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-
 /****************************************************************************
  * Inline functions
  ****************************************************************************/
@@ -367,26 +355,6 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-#ifdef CONFIG_SMP
-  return (uint32_t *)g_current_regs[up_cpu_index()];
-#else
-  return (uint32_t *)g_current_regs[0];
-#endif
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-#ifdef CONFIG_SMP
-  g_current_regs[up_cpu_index()] = regs;
-#else
-  g_current_regs[0] = regs;
-#endif
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {

arch/arm/include/armv7-a/irq.h

@@ -470,35 +470,10 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
-/****************************************************************************
- * Name:
- *   up_current_regs/up_set_current_regs
- *
- * Description:
- *   We use the following code to manipulate the TPIDRPRW register,
- *   which exists uniquely for each CPU and is primarily designed to store
- *   current thread information. Currently, we leverage it to store interrupt
- *   information, with plans to further optimize its use for storing both
- *   thread and interrupt information in the future.
- *
- ****************************************************************************/
-
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-  return (uint32_t *)CP15_GET(TPIDRPRW);
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-  CP15_SET(TPIDRPRW, regs);
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {
-  return up_current_regs() != NULL;
+  return (bool)CP15_GET(TPIDRPRW);
 }
 
 /****************************************************************************

arch/arm/include/armv7-m/irq.h

@@ -254,18 +254,6 @@ struct xcptcontext
  * Public Data
  ****************************************************************************/
 
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure.  If is non-NULL only during interrupt
- * processing.  Access to g_current_regs[] must be through the
- * [get/set]_current_regs for portability.
- */
-
-/* For the case of architectures with multiple CPUs, then there must be one
- * such value for each processor that can receive an interrupt.
- */
-
-extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-
 /****************************************************************************
  * Inline functions
  ****************************************************************************/
@@ -572,26 +560,6 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-#ifdef CONFIG_SMP
-  return (uint32_t *)g_current_regs[up_cpu_index()];
-#else
-  return (uint32_t *)g_current_regs[0];
-#endif
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-#ifdef CONFIG_SMP
-  g_current_regs[up_cpu_index()] = regs;
-#else
-  g_current_regs[0] = regs;
-#endif
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {

arch/arm/include/armv7-r/irq.h

@@ -465,35 +465,10 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
-/****************************************************************************
- * Name:
- *   up_current_regs/up_set_current_regs
- *
- * Description:
- *   We use the following code to manipulate the TPIDRPRW register,
- *   which exists uniquely for each CPU and is primarily designed to store
- *   current thread information. Currently, we leverage it to store interrupt
- *   information, with plans to further optimize its use for storing both
- *   thread and interrupt information in the future.
- *
- ****************************************************************************/
-
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-  return (uint32_t *)CP15_GET(TPIDRPRW);
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-  CP15_SET(TPIDRPRW, regs);
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {
-  return up_current_regs() != NULL;
+  return (bool)CP15_GET(TPIDRPRW);
 }
 
 /****************************************************************************

arch/arm/include/armv8-m/irq.h

@@ -265,18 +265,6 @@ struct xcptcontext
  * Public Data
  ****************************************************************************/
 
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure.  If is non-NULL only during interrupt
- * processing.  Access to g_current_regs[] must be through the
- * [get/set]_current_regs for portability.
- */
-
-/* For the case of architectures with multiple CPUs, then there must be one
- * such value for each processor that can receive an interrupt.
- */
-
-extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-
 /****************************************************************************
  * Inline functions
  ****************************************************************************/
@@ -545,26 +533,6 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-#ifdef CONFIG_SMP
-  return (uint32_t *)g_current_regs[up_cpu_index()];
-#else
-  return (uint32_t *)g_current_regs[0];
-#endif
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-#ifdef CONFIG_SMP
-  g_current_regs[up_cpu_index()] = regs;
-#else
-  g_current_regs[0] = regs;
-#endif
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {

arch/arm/include/armv8-r/irq.h

@@ -465,35 +465,10 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
-/****************************************************************************
- * Name:
- *   up_current_regs/up_set_current_regs
- *
- * Description:
- *   We use the following code to manipulate the TPIDRPRW register,
- *   which exists uniquely for each CPU and is primarily designed to store
- *   current thread information. Currently, we leverage it to store interrupt
- *   information, with plans to further optimize its use for storing both
- *   thread and interrupt information in the future.
- *
- ****************************************************************************/
-
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-  return (uint32_t *)CP15_GET(TPIDRPRW);
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-  CP15_SET(TPIDRPRW, regs);
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {
-  return up_current_regs() != NULL;
+  return (bool)CP15_GET(TPIDRPRW);
 }
 
 /****************************************************************************

arch/arm/include/irq.h

@@ -105,7 +105,7 @@ extern "C"
  ****************************************************************************/
 
 #define up_getusrpc(regs) \
-    (((uint32_t *)((regs) ? (regs) : up_current_regs()))[REG_PC])
+    (((uint32_t *)((regs) ? (regs) : running_regs()))[REG_PC])
 
 #endif /* __ASSEMBLY__ */
 

arch/arm/include/tlsr82/irq.h

@@ -173,17 +173,9 @@ struct xcptcontext
  * Public Data
  ****************************************************************************/
 
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure.  If is non-NULL only during interrupt
- * processing.  Access to g_current_regs[] must be through the
- * [get/set]_current_regs for portability.
- */
-
-/* For the case of architectures with multiple CPUs, then there must be one
- * such value for each processor that can receive an interrupt.
- */
+/* g_interrupt_context store irq status */
 
-extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
+extern volatile bool g_interrupt_context[CONFIG_SMP_NCPUS];
 
 /****************************************************************************
  * Inline functions
@@ -268,40 +260,17 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
-noinstrument_function
-static inline_function uint32_t *up_current_regs(void)
-{
-#ifdef CONFIG_SMP
-  return (uint32_t *)g_current_regs[up_cpu_index()];
-#else
-  return (uint32_t *)g_current_regs[0];
-#endif
-}
-
-noinstrument_function
-static inline_function void up_set_current_regs(uint32_t *regs)
-{
-#ifdef CONFIG_SMP
-  g_current_regs[up_cpu_index()] = regs;
-#else
-  g_current_regs[0] = regs;
-#endif
-}
-
 noinstrument_function
 static inline_function bool up_interrupt_context(void)
 {
 #ifdef CONFIG_SMP
   irqstate_t flags = up_irq_save();
-#endif
-
-  bool ret = up_current_regs() != NULL;
-
-#ifdef CONFIG_SMP
+  bool ret = g_interrupt_context[up_cpu_index()];
   up_irq_restore(flags);
-#endif
-
   return ret;
+#else
+  return g_interrupt_context[0];
+#endif
 }
 
 #define up_switch_context(tcb, rtcb)                        \