Cargo.toml

[package]
name = "axhal_cpu"
version = "0.1.0"
description = "Unified operations for various CPU architectures"
documentation = "https://docs.rs/axhal_cpu"
keywords = ["arceos", "hal", "hardware-abstraction-layer", "x86_64", "aarch64", "riscv"]
categories = ["embedded", "no-std", "hardware-support", "os"]
edition.workspace = true
authors.workspace = true
license.workspace = true
homepage.workspace = true
repository.workspace = true

[features]
default = []
fp_simd = []
tls = []

[dependencies]
linkme = "0.3"
log = "=0.4.21"
cfg-if = "1.0"
memory_addr = "0.3"
page_table_entry = "0.5"
static_assertions = "1.1.0"

[target.'cfg(target_arch = "x86_64")'.dependencies]
x86 = "0.52"
x86_64 = "0.15.2"

[target.'cfg(target_arch = "aarch64")'.dependencies]
aarch64-cpu = "10.0"
tock-registers = "0.9"

[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
riscv = "0.12"

[lints.clippy]
new_without_default = "allow"