From 06f2c1d517973e4893f16c9fe10c0250f7d8279f Mon Sep 17 00:00:00 2001 From: itlhd Date: Wed, 18 Sep 2024 19:33:43 +0800 Subject: [PATCH] Added device tree overlays files for armsom-sige7 board:two OV13850 cameras --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 2 + .../armsom-sige7-camera-ov13850-csi0.dts | 203 +++++++++++++++++ .../armsom-sige7-camera-ov13850-csi1.dts | 205 ++++++++++++++++++ 3 files changed, 410 insertions(+) create mode 100755 arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi0.dts create mode 100755 arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi1.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index 1ad5c584b5569..0327eb8babcad 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ armsom-sige7-camera-imx415-4k.dtbo \ + armsom-sige7-camera-ov13850-csi0.dtbo \ + armsom-sige7-camera-ov13850-csi1.dtbo \ armsom-sige7-display-10hd.dtbo \ orangepi-5-lcd1.dtbo \ orangepi-5-lcd2.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi0.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi0.dts new file mode 100755 index 0000000000000..d9c08a4763917 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi0.dts @@ -0,0 +1,203 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov13850: ov13850@10{ + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2 3 4>; + }; + + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir2>; + }; + }; + }; + }; + + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir2>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi1.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi1.dts new file mode 100755 index 0000000000000..c0b8983138a8a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi1.dts @@ -0,0 +1,205 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + + fragment@0 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + ov13850_1: ov13850_1@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out1: endpoint { + remote-endpoint = <&mipidphy3_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy1_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy3>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out1>; + data-lanes = <1 2 3 4>; + }; + + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi4_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds4>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds4_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; + + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp1_vir1>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; + }; + }; + +}; \ No newline at end of file