From 20ee0e6e0ec51c05f0309a9b98899ea567641295 Mon Sep 17 00:00:00 2001 From: Joshua-Riek Date: Tue, 12 Dec 2023 16:48:17 -0500 Subject: [PATCH] arm64: dts: Add overlays for the ROCK 5 ITX --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 5 + ...-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts | 222 ++++++++++++++++++ .../rock-5-itx-radxa-camera-4k-on-cam0.dts | 208 ++++++++++++++++ .../rock-5-itx-radxa-camera-4k-on-cam1.dts | 209 +++++++++++++++++ .../rock-5-itx-radxa-display-8hd-on-lcd0.dts | 219 +++++++++++++++++ .../rock-5-itx-radxa-display-8hd-on-lcd1.dts | 219 +++++++++++++++++ 6 files changed, 1082 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam0.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam1.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd0.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd1.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index 36fb6fd79f8cc..6a96fefdf3b7a 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -30,6 +30,11 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ rock-5b-rpi-camera-v2.dtbo \ rock-5b-radxa-camera-4k.dtbo \ rock-5b-sata.dtbo \ + rock-5-itx-radxa-camera-4k-on-cam0.dtbo \ + rock-5-itx-radxa-camera-4k-on-cam1.dtbo \ + rock-5-itx-radxa-display-8hd-on-lcd0.dtbo \ + rock-5-itx-radxa-display-8hd-on-lcd1.dtbo \ + rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dtbo \ radxa-cm5-io-radxa-camera-4k.dtbo \ radxa-cm5-io-raspi-7inch-touchscreen.dtbo \ radxa-cm5-io-radxa-display-10hd.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts new file mode 100644 index 0000000000000..94744af220076 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts @@ -0,0 +1,222 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable Sharp LQ133T1JW01 Display on eDP"; + compatible = "radxa,rock-5-itx"; + category = "display"; + exclusive = "dp1", "edp0", "vp2"; + description = "Enable Sharp LQ133T1JW01 display on eDP.\nThis will disable DP1."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_edp0: backlight-edp0 { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm8 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_lcd_edp0: vcc3v3-lcd-edp0 { + status = "okay"; + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "vcc3v3_lcd_edp0"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + edp0_panel: edp0-panel { + status = "okay"; + compatible = "simple-panel"; + backlight = <&backlight_edp0>; + power-supply = <&vcc3v3_lcd_edp0>; + pinctrl-names = "default"; + prepare-delay-ms = <100>; + enable-delay-ms = <100>; + bpc = <8>; + width-mm = <305>; + height-mm = <107>; + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <241500000>; + hactive = <2560>; + vactive = <1440>; + hfront-porch = <80>; + hsync-len = <32>; + hback-porch = <48>; + vfront-porch = <31>; + vsync-len = <5>; + vback-porch = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&pwm8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + + }; + }; + + fragment@2 { + target = <&edp0>; + + __overlay__ { + force-hpd; + disable-audio; + status = "okay"; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&hdptxphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&edp0_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&edp0_in_vp0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&edp0_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&route_edp0>; + + __overlay__ { + status = "okay"; + connect = <&vp2_out_edp0>; + }; + }; + + fragment@8 { + target = <&dp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&dp1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&route_dp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&dp1_sound>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam0.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam0.dts new file mode 100644 index 0000000000000..60772887e009b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam0.dts @@ -0,0 +1,208 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM0"; + compatible = "radxa,rock-5-itx"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 4K on CAM0."; + }; + + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415_0: imx415-0@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam1.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam1.dts new file mode 100644 index 0000000000000..27bfcc581377d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam1.dts @@ -0,0 +1,209 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM1"; + compatible = "radxa,rock-5-itx"; + category = "camera"; + exclusive = "csi2_dphy3"; + description = "Enable Radxa Camera 4K on CAM1."; + }; + + fragment@0 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415_1: imx415-1@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out1: endpoint { + remote-endpoint = <&mipidphy1_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy1_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + /* dphy1 full mode */ + target = <&csi2_dphy3>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy1_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input_1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi4_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output_1: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in1>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds4>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi4_in1: endpoint { + remote-endpoint = <&mipi4_csi2_output_1>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds4_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi4_lvds2_sditf_1: endpoint { + remote-endpoint = <&isp1_vir2>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp1_vir2>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds2_sditf_1>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd0.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd0.dts new file mode 100644 index 0000000000000..d94afb23e5cbd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd0.dts @@ -0,0 +1,219 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD on LCD0"; + compatible = "radxa,rock-5-itx"; + category = "display"; + exclusive = "dsi0", "vp3"; + description = "Enable Radxa Display 8HD on LCD0."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi0_backlight: dsi0-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + backlight = <&dsi0_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi0-lcd { + dsi0_lcd_rst_gpio: dsi0-lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi0_backlight_en: dsi0-backlight-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd1.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd1.dts new file mode 100644 index 0000000000000..555b9b909d030 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd1.dts @@ -0,0 +1,219 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD on LCD1"; + compatible = "radxa,rock-5-itx"; + category = "display"; + exclusive = "dsi1", "vp3"; + description = "Enable Radxa Display 8HD on LCD1."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m4_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +};