From 31f914389de26d8684ebfa05e02a6c3fdaa64292 Mon Sep 17 00:00:00 2001 From: "jack@armsom.org" Date: Fri, 22 Nov 2024 19:52:45 +0800 Subject: [PATCH] armsom-sige5&armsom-cm5-io camera display --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 6 + .../armsom-cm5-io-camera-imx219-cs0.dts | 223 ++++++++++++ .../armsom-cm5-io-camera-ov13850-cs1.dts | 220 ++++++++++++ .../overlay/armsom-cm5-io-display-10hd.dts | 318 +++++++++++++++++ .../armsom-sige5-camera-ov13850-cs0.dts | 188 ++++++++++ .../armsom-sige5-camera-ov13850-cs1.dts | 188 ++++++++++ .../overlay/armsom-sige5-display-10hd.dts | 333 ++++++++++++++++++ 7 files changed, 1476 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-imx219-cs0.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-ov13850-cs1.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-display-10hd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs0.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs1.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-display-10hd.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index f3fc426ec76f0..153c781a84881 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -1,8 +1,14 @@ # SPDX-License-Identifier: GPL-2.0 dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + armsom-cm5-io-camera-imx219-cs0.dtbo \ + armsom-cm5-io-camera-ov13850-cs1.dtbo \ + armsom-cm5-io-display-10hd.dtbo \ armsom-cm5-rpi-cm4-io-camera0.dtbo \ armsom-cm5-rpi-cm4-io-camera1.dtbo \ armsom-cm5-rpi-cm4-io-display.dtbo \ + armsom-sige5-camera-ov13850-cs0.dtbo \ + armsom-sige5-camera-ov13850-cs1.dtbo \ + armsom-sige5-display-10hd.dtbo \ armsom-sige7-camera-imx415-4k.dtbo \ armsom-sige7-camera-ov13850-csi0.dtbo \ armsom-sige7-camera-ov13850-csi1.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-imx219-cs0.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-imx219-cs0.dts new file mode 100644 index 0000000000000..75cae58d6c7ad --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-imx219-cs0.dts @@ -0,0 +1,223 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + imx219: imx219@10 { + status = "okay"; + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cam_clk1m1_clk1>; + VANA-supply = <&vcc_3v3_s0>; /* 2.8v */ + VDIG-supply = <&vcc_3v3_s0>; /* 1.8v */ + VDDL-supply = <&vcc_3v3_s0>; /* 1.2v */ + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + imx219_out: endpoint { + remote-endpoint = <&mipidphy3_in_ucam3>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&csi2_dphy4>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx219_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&mipi3_csi2>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds3>; + __overlay__ { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mipi_lvds3_sditf>; + __overlay__ { + status = "okay"; + + port { + mipi_lvds3_sditf: endpoint { + remote-endpoint = <&isp_vir0_in1>; + }; + }; + }; + }; + + fragment@9 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&rkisp_vir0>; + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds3_sditf>; + }; + }; + }; + }; + + fragment@13 { + target = <&pinctrl>; + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-ov13850-cs1.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-ov13850-cs1.dts new file mode 100644 index 0000000000000..0bc0b04d42e04 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-ov13850-cs1.dts @@ -0,0 +1,220 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + camera1_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera1_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam1_pwdn_gpio>; + }; + }; + }; + + fragment@1 { + target = <&i2c5>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + ov13850: ov13850@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk1m0_clk1>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&csi2_dphy0>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&mipi1_csi2>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds1>; + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi_csi2_output>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mipi_lvds1_sditf>; + __overlay__ { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp_vir0_in0>; + }; + }; + }; + }; + + fragment@9 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&rkisp_vir1>; + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; + }; + }; + + fragment@13 { + target = <&pinctrl>; + __overlay__ { + camera { + cam1_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-display-10hd.dts new file mode 100644 index 0000000000000..aff568b9a89df --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-display-10hd.dts @@ -0,0 +1,318 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1_6ch_1 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&pwm1_6ch_1>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm1m0_ch1>; + }; + }; + + fragment@2 { + target = <&dsi>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc_lcd_mipi1>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + backlight = <&dsi1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 B0 01 + 15 00 02 C0 26 + 15 00 02 C1 10 + 15 00 02 C2 0E + 15 00 02 C3 00 + 15 00 02 C4 00 + 15 00 02 C5 23 + 15 00 02 C6 11 + 15 00 02 C7 22 + 15 00 02 C8 20 + 15 00 02 C9 1E + 15 00 02 CA 1C + 15 00 02 CB 0C + 15 00 02 CC 0A + 15 00 02 CD 08 + 15 00 02 CE 06 + 15 00 02 CF 18 + 15 00 02 D0 02 + 15 00 02 D1 00 + 15 00 02 D2 00 + 15 00 02 D3 00 + 15 00 02 D4 26 + 15 00 02 D5 0F + 15 00 02 D6 0D + 15 00 02 D7 00 + 15 00 02 D8 00 + 15 00 02 D9 23 + 15 00 02 DA 11 + 15 00 02 DB 21 + 15 00 02 DC 1F + 15 00 02 DD 1D + 15 00 02 DE 1B + 15 00 02 DF 0B + 15 00 02 E0 09 + 15 00 02 E1 07 + 15 00 02 E2 05 + 15 00 02 E3 17 + 15 00 02 E4 01 + 15 00 02 E5 00 + 15 00 02 E6 00 + 15 00 02 E7 00 + 15 00 02 B0 03 + 15 00 02 BE 04 + 15 00 02 B9 40 + 15 00 02 CC 88 + 15 00 02 C8 0C + 15 00 02 C9 07 + 15 00 02 CD 01 + 15 00 02 CA 40 + 15 00 02 CE 1A + 15 00 02 CF 60 + 15 00 02 D2 08 + 15 00 02 D3 08 + 15 00 02 DB 01 + 15 00 02 D9 06 + 15 00 02 D4 00 + 15 00 02 D5 01 + 15 00 02 D6 04 + 15 00 02 D7 03 + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 B0 06 + 15 00 02 C0 A5 + 15 00 02 D5 1C + 15 00 02 C0 00 + 15 00 02 B0 00 + 15 00 02 BD 30 + + 15 00 02 F9 5C + 15 00 02 C2 14 + 15 00 02 C4 14 + 15 00 02 BF 15 + 15 00 02 C0 0C + + + 15 00 02 B0 00 + 15 00 02 B1 79 + 15 00 02 BA 8F + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 32 01 28 + 05 78 01 10 + ]; + disp_timings0: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hfront-porch = <80>; + hsync-len = <1>; + hback-porch = <60>; + vfront-porch = <35>; + vsync-len = <1>; + vback-porch = <25>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipidcphy0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&dsi_in_vp1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&vp1>; + __overlay__ { + assigned-clocks = <&cru DCLK_VP1_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; + }; + }; + + fragment@7 { + target = <&i2c0>; + __overlay__ { + pinctrl-0 = <&i2c0m1_xfer>; + status = "okay"; + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <9271>; + tp-supply = <&vcc_lcd_mipi1>; + configfile-num = <1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs0.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs0.dts new file mode 100644 index 0000000000000..397aeccef60f6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs0.dts @@ -0,0 +1,188 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c5>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + ov13850: ov13850@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk1m0_clk1>; + pwdn-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi1_csi2>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds1>; + __overlay__ { + status = "okay"; + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds1_sditf>; + __overlay__ { + status = "okay"; + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp_vir0_in0>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_vir1>; + __overlay__ { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs1.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs1.dts new file mode 100644 index 0000000000000..2d3720643791e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs1.dts @@ -0,0 +1,188 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c4>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + ov13850_1: ov13850_1@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2m0_clk2>; + pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out1: endpoint { + remote-endpoint = <&mipidphy3_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy3>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi3_csi2>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in3>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds3>; + __overlay__ { + status = "okay"; + port { + cif_mipi_in3: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds3_sditf>; + __overlay__ { + status = "okay"; + port { + mipi_lvds3_sditf: endpoint { + remote-endpoint = <&isp_vir0_in1>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_vir0>; + __overlay__ { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds3_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-display-10hd.dts new file mode 100644 index 0000000000000..24be21e542a12 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-display-10hd.dts @@ -0,0 +1,333 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_bl_n: vcc3v3-bl-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bl_n"; + regulator-boot-on; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1_6ch_1 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&pwm1_6ch_1>; + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm1m0_ch1>; + }; + }; + + fragment@2 { + target = <&dsi>; + __overlay__ { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc_lcd_mipi1>; + reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + backlight = <&dsi1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 B0 01 + 15 00 02 C0 26 + 15 00 02 C1 10 + 15 00 02 C2 0E + 15 00 02 C3 00 + 15 00 02 C4 00 + 15 00 02 C5 23 + 15 00 02 C6 11 + 15 00 02 C7 22 + 15 00 02 C8 20 + 15 00 02 C9 1E + 15 00 02 CA 1C + 15 00 02 CB 0C + 15 00 02 CC 0A + 15 00 02 CD 08 + 15 00 02 CE 06 + 15 00 02 CF 18 + 15 00 02 D0 02 + 15 00 02 D1 00 + 15 00 02 D2 00 + 15 00 02 D3 00 + 15 00 02 D4 26 + 15 00 02 D5 0F + 15 00 02 D6 0D + 15 00 02 D7 00 + 15 00 02 D8 00 + 15 00 02 D9 23 + 15 00 02 DA 11 + 15 00 02 DB 21 + 15 00 02 DC 1F + 15 00 02 DD 1D + 15 00 02 DE 1B + 15 00 02 DF 0B + 15 00 02 E0 09 + 15 00 02 E1 07 + 15 00 02 E2 05 + 15 00 02 E3 17 + 15 00 02 E4 01 + 15 00 02 E5 00 + 15 00 02 E6 00 + 15 00 02 E7 00 + 15 00 02 B0 03 + 15 00 02 BE 04 + 15 00 02 B9 40 + 15 00 02 CC 88 + 15 00 02 C8 0C + 15 00 02 C9 07 + 15 00 02 CD 01 + 15 00 02 CA 40 + 15 00 02 CE 1A + 15 00 02 CF 60 + 15 00 02 D2 08 + 15 00 02 D3 08 + 15 00 02 DB 01 + 15 00 02 D9 06 + 15 00 02 D4 00 + 15 00 02 D5 01 + 15 00 02 D6 04 + 15 00 02 D7 03 + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 B0 06 + 15 00 02 C0 A5 + 15 00 02 D5 1C + 15 00 02 C0 00 + 15 00 02 B0 00 + 15 00 02 BD 30 + + 15 00 02 F9 5C + 15 00 02 C2 14 + 15 00 02 C4 14 + 15 00 02 BF 15 + 15 00 02 C0 0C + + + 15 00 02 B0 00 + 15 00 02 B1 79 + 15 00 02 BA 8F + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 32 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hfront-porch = <80>; + hsync-len = <1>; + hback-porch = <60>; + vfront-porch = <35>; + vsync-len = <1>; + vback-porch = <25>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipidcphy0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&dsi_in_vp1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&vp1>; + __overlay__ { + assigned-clocks = <&cru DCLK_VP1_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; + }; + }; + + fragment@7 { + target = <&i2c0>; + __overlay__ { + pinctrl-0 = <&i2c0m1_xfer>; + status = "okay"; + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD1 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <89>; + tp-supply = <&vcc_lcd_mipi1>; + + configfile-num = <1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = + <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +};