diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 673ec4307f6b..bf5b64cebf73 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
+	armsom-sige3-camera-ov13850.dtbo \
+	armsom-sige3-display-10hd.dtbo \
 	armsom-sige7-camera-imx415-4k.dtbo \
 	armsom-sige7-camera-ov13850-csi0.dtbo \
 	armsom-sige7-camera-ov13850-csi1.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige3-camera-ov13850.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige3-camera-ov13850.dts
new file mode 100755
index 000000000000..bae18548cf8f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige3-camera-ov13850.dts
@@ -0,0 +1,114 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&i2c2>;
+
+		__overlay__ {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2m1_xfer>;
+
+			ov13850: ov13850@10 {
+				status = "okay";
+				compatible = "ovti,ov13850";
+				reg = <0x10>;
+				clocks = <&cru CLK_CIF_OUT>;
+				clock-names = "xvclk";
+				power-domains = <&power RK3568_PD_VI>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&cif_clk>;
+				pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+				reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+				rockchip,camera-module-index = <0>;
+				rockchip,camera-module-facing = "back";
+				rockchip,camera-module-name = "ZC-OV13850R2A-V1";
+				rockchip,camera-module-lens-name = "Largan-50064B31";
+				port {
+					ucam_out0: endpoint {
+						remote-endpoint = <&mipi_in_ucam0>;
+						data-lanes = <1 2 3 4>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&csi2_dphy_hw>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@2 {
+		target = <&csi2_dphy0>;
+
+		__overlay__ {
+			status = "okay";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mipi_in_ucam0: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&ucam_out0>;
+						data-lanes = <1 2 3 4>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					csidphy_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&isp0_in>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&isp_mmu>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@4 {
+		target = <&rkisp>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@10 {
+		target = <&rkisp_vir0>;
+
+		__overlay__ {
+			status = "okay";
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				isp0_in: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&csidphy_out>;
+				};
+			};
+		};
+	};
+	
+};
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige3-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige3-display-10hd.dts
new file mode 100755
index 000000000000..4ae45da42558
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige3-display-10hd.dts
@@ -0,0 +1,330 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			vcc_lcd_mipi1: vcc-lcd-mipi1 {
+				status = "okay";
+				compatible = "regulator-fixed";
+				regulator-name = "vcc_lcd_mipi1";
+				gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			dsi1_backlight: dsi1-backlight {
+				status = "okay";
+				compatible = "pwm-backlight";
+				pwms = <&pwm1 0 25000 0>;
+				brightness-levels = <
+					0  20  20  21  21  22  22  23
+					23  24  24  25  25  26  26  27
+					27  28  28  29  29  30  30  31
+					31  32  32  33  33  34  34  35
+					35  36  36  37  37  38  38  39
+					40  41  42  43  44  45  46  47
+					48  49  50  51  52  53  54  55
+					56  57  58  59  60  61  62  63
+					64  65  66  67  68  69  70  71
+					72  73  74  75  76  77  78  79
+					80  81  82  83  84  85  86  87
+					88  89  90  91  92  93  94  95
+					96  97  98  99 100 101 102 103
+					104 105 106 107 108 109 110 111
+					112 113 114 115 116 117 118 119
+					120 121 122 123 124 125 126 127
+					128 129 130 131 132 133 134 135
+					136 137 138 139 140 141 142 143
+					144 145 146 147 148 149 150 151
+					152 153 154 155 156 157 158 159
+					160 161 162 163 164 165 166 167
+					168 169 170 171 172 173 174 175
+					176 177 178 179 180 181 182 183
+					184 185 186 187 188 189 190 191
+					192 193 194 195 196 197 198 199
+					200 201 202 203 204 205 206 207
+					208 209 210 211 212 213 214 215
+					216 217 218 219 220 221 222 223
+					224 225 226 227 228 229 230 231
+					232 233 234 235 236 237 238 239
+					240 241 242 243 244 245 246 247
+					248 249 250 251 252 253 254 255
+				>;
+				default-brightness-level = <200>;
+				enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&dsi1_backlight_en>;
+			};			
+		};
+	};
+
+	fragment@1 {
+		target = <&pwm1>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm1m1_pins>;	
+		};
+	};
+
+	fragment@2 {
+		target = <&dsi1>;
+
+		__overlay__ {
+			status = "okay";
+			dsi1_panel: panel@0 {
+				status = "okay";
+				compatible = "simple-panel-dsi";
+				reg = <0>;
+				power-supply = <&vcc_lcd_mipi1>;
+				reset-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&dsi1_lcd_rst_gpio>;
+				backlight = <&dsi1_backlight>;
+				reset-delay-ms = <10>;
+				enable-delay-ms = <10>;
+				prepare-delay-ms = <10>;
+				unprepare-delay-ms = <10>;
+				disable-delay-ms = <10>;
+				dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+					MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
+				dsi,format = <MIPI_DSI_FMT_RGB888>;
+				dsi,lanes  = <4>;
+				panel-init-sequence = [
+					15 00 02 B0 01
+					15 00 02 C0 26
+					15 00 02 C1 10
+					15 00 02 C2 0E
+					15 00 02 C3 00
+					15 00 02 C4 00
+					15 00 02 C5 23
+					15 00 02 C6 11
+					15 00 02 C7 22
+					15 00 02 C8 20
+					15 00 02 C9 1E
+					15 00 02 CA 1C
+					15 00 02 CB 0C
+					15 00 02 CC 0A
+					15 00 02 CD 08
+					15 00 02 CE 06
+					15 00 02 CF 18
+					15 00 02 D0 02
+					15 00 02 D1 00
+					15 00 02 D2 00
+					15 00 02 D3 00
+					15 00 02 D4 26
+					15 00 02 D5 0F
+					15 00 02 D6 0D
+					15 00 02 D7 00
+					15 00 02 D8 00
+					15 00 02 D9 23
+					15 00 02 DA 11
+					15 00 02 DB 21
+					15 00 02 DC 1F
+					15 00 02 DD 1D
+					15 00 02 DE 1B
+					15 00 02 DF 0B
+					15 00 02 E0 09
+					15 00 02 E1 07
+					15 00 02 E2 05
+					15 00 02 E3 17
+					15 00 02 E4 01
+					15 00 02 E5 00
+					15 00 02 E6 00
+					15 00 02 E7 00
+					15 00 02 B0 03
+					15 00 02 BE 04
+					15 00 02 B9 40
+					15 00 02 CC 88
+					15 00 02 C8 0C
+					15 00 02 C9 07
+					15 00 02 CD 01
+					15 00 02 CA 40
+					15 00 02 CE 1A
+					15 00 02 CF 60
+					15 00 02 D2 08
+					15 00 02 D3 08
+					15 00 02 DB 01
+					15 00 02 D9 06
+					15 00 02 D4 00
+					15 00 02 D5 01
+					15 00 02 D6 04
+					15 00 02 D7 03
+					15 00 02 C2 00
+					15 00 02 C3 0E
+					15 00 02 C4 00
+					15 00 02 C5 0E
+					15 00 02 DD 00
+					15 00 02 DE 0E
+					15 00 02 E6 00
+					15 00 02 E7 0E
+					15 00 02 C2 00
+					15 00 02 C3 0E
+					15 00 02 C4 00
+					15 00 02 C5 0E
+					15 00 02 DD 00
+					15 00 02 DE 0E
+					15 00 02 E6 00
+					15 00 02 E7 0E
+					15 00 02 B0 06
+					15 00 02 C0 A5
+					15 00 02 D5 1C
+					15 00 02 C0 00
+					15 00 02 B0 00
+					15 00 02 BD 30
+
+					15 00 02 F9 5C
+					15 00 02 C2 14
+					15 00 02 C4 14
+					15 00 02 BF 15
+					15 00 02 C0 0C
+
+
+					15 00 02 B0 00
+					15 00 02 B1 79
+					15 00 02 BA 8F
+
+					05 78 01 11
+					05 78 01 29
+				];
+
+				panel-exit-sequence = [
+					05 32 01 28
+					05 78 01 10
+				];
+
+				disp_timings1: display-timings {
+					native-mode = <&dsi1_timing0>;
+					dsi1_timing0: timing0 {
+						clock-frequency = <160000000>;
+						hactive = <1200>;
+						vactive = <1920>;
+						hfront-porch = <80>;
+						hsync-len = <1>;
+						hback-porch = <60>;
+						vfront-porch = <35>;
+						vsync-len = <1>;
+						vback-porch = <25>;
+						hsync-active = <0>;
+						vsync-active = <0>;
+						de-active = <0>;
+						pixelclk-active = <1>;
+					};
+				};
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						panel_in_dsi1: endpoint {
+							remote-endpoint = <&dsi1_out_panel>;
+						};
+					};
+				};
+			};
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+					dsi1_out_panel: endpoint {
+						remote-endpoint = <&panel_in_dsi1>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&video_phy1>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+
+	fragment@4 {
+		target = <&route_dsi1>;
+
+		__overlay__ {
+			status = "okay";
+			connect = <&vp1_out_dsi1>;
+		};
+	};
+
+	fragment@5 {
+		target = <&dsi1_in_vp0>;
+
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@6 {
+		target = <&dsi1_in_vp1>;
+
+		__overlay__ {
+			status = "okay";
+		
+		};
+	};
+
+	fragment@7 {
+		target = <&i2c1>;
+
+		__overlay__ {
+			status = "okay";
+
+			gt9xx: gt9xx@14 {
+				status = "okay";
+				compatible = "goodix,gt9xx";
+				reg = <0x14>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&gt9xx_gpio>;
+				touch-gpio = <&gpio3 RK_PD0 IRQ_TYPE_LEVEL_HIGH>;
+				reset-gpio = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+				max-x = <1200>;
+				max-y = <1920>;
+				tp-size = <89>;
+				tp-supply = <&vcc_lcd_mipi1>;
+
+				configfile-num = <1>;  
+			};
+		
+		};
+	};
+
+	fragment@8 {
+		target = <&pinctrl>;
+
+		__overlay__ {
+			dsi1-lcd {
+				dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio {
+					rockchip,pins =
+						<3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+				};
+				dsi1_backlight_en: dsi1-backlight-en {
+					rockchip,pins =
+						<3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+				};
+			};
+
+			gt9xx {
+				gt9xx_gpio: gt9xx-gpio {
+					rockchip,pins =
+						<3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
+						<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+				};
+			};
+		};
+	};
+};
\ No newline at end of file