From 8895a647397d2b41e4aee8f23478d2caae3f1a5f Mon Sep 17 00:00:00 2001 From: SuperKali Date: Wed, 2 Oct 2024 21:09:26 +0200 Subject: [PATCH 01/13] Remove duplicated items on youyeetoo r1 dts file (#255) --- arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts b/arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts index cfcdd9bff639e..a80e8ce0dc5c1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts @@ -34,12 +34,10 @@ "Speaker", "LOUT1", "Speaker", "ROUT1", "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", + "LINPUT1", "Headset Mic", + "RINPUT1", "Headset Mic", "LINPUT2", "Main Mic", - "RINPUT1", "Main Mic", "RINPUT2", "Main Mic"; pinctrl-names = "default"; pinctrl-0 = <&hp_det>; From 4f66346f76aafa711b0c3daa2a46f50ee1cdd83b Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sun, 29 Sep 2024 19:00:47 +0200 Subject: [PATCH 02/13] arm64: dts: rk3588-blade3-v101-linux: pwm-fan cooling-levels and temp-trips so fan doesn't go full blast all the time (6.1-rkr3) --- .../boot/dts/rockchip/rk3588-blade3-v101-linux.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts index c088773b90578..59efad7975270 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts @@ -222,7 +222,15 @@ pulses-per-revolution = <2>; #cooling-cells = <2>; - pwms = <&pwm8 0 50000 0>; + pwms = <&pwm8 0 250000 0>; + cooling-levels = <0 35 70 100 125 150>; + rockchip,temp-trips = < + 30000 1 + 45000 2 + 50000 3 + 55000 4 + 60000 5 + >; }; }; From dd6ea78616a42b5f4a0286a018101a177aa53876 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sun, 29 Sep 2024 19:02:27 +0200 Subject: [PATCH 03/13] arm64: dts: rk3588-blade3-v101-linux: faster-pd-negotiation for fusb302's usb_con1 --- arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts index 59efad7975270..6c578dbd00440 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts @@ -801,6 +801,7 @@ data-role = "dual"; power-role = "dual"; try-power-role = "sink"; + faster-pd-negotiation; op-sink-microwatt = <15000000>; sink-pdos = // ; From 7ffa015211c3fe342a36110b94deb64dc097d114 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sun, 29 Sep 2024 19:03:09 +0200 Subject: [PATCH 04/13] arm64: dts: rk3588-blade3-v101-linux: clock-rate and clocks ACLK_VOP for vop --- arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts index 6c578dbd00440..79ffed34912af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts @@ -617,6 +617,8 @@ }; &vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; status = "okay"; }; From f6e7b84761372abc8b6f0a94e25246b9fd6a85e3 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sun, 29 Sep 2024 19:04:06 +0200 Subject: [PATCH 05/13] arm64: dts: rk3588-blade3-v101-linux: enable hdptxphy_hdmi0/1 and set &display_subsystem clocks --- .../boot/dts/rockchip/rk3588-blade3-v101-linux.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts index 79ffed34912af..16285cf744365 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts @@ -1032,3 +1032,16 @@ status = "okay"; &sata0 { status = "okay"; }; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; From e7adeed3859eba61c80cc285a019635171916e4b Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Tue, 1 Oct 2024 19:38:58 +0200 Subject: [PATCH 06/13] arm64: dts: rk3588-blade3-v101-linux: add cec-enable to &hdmi0 - thanks Meko @ armbian-rockchip Discord --- arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts index 16285cf744365..e90aad5665c03 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts @@ -690,6 +690,7 @@ &hdmi0 { enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; status = "okay"; + cec-enable = "true"; }; &hdmi0_in_vp0 { From 9680c56a0804b400d92df783009459ccee05b027 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Mon, 30 Sep 2024 00:52:58 +0200 Subject: [PATCH 07/13] vop2 rbga2101010 capability fix (6.1-rkr3 adapted version) - from https://raw.githubusercontent.com/wiki/hbiyik/ffmpeg-rockchip/patches/rockchip-kernel/0002-vop2_rgba2101010_capability_fix.patch --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 31691b910fc6e..3e2fc783639c8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -31,8 +31,6 @@ _VOP_REG(off, _mask, s, true) static const uint32_t formats_for_cluster[] = { - DRM_FORMAT_XRGB2101010, - DRM_FORMAT_XBGR2101010, DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888, From 235b3fa0412974ecff9302315bff2ddee456aad1 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Fri, 4 Oct 2024 18:53:59 +0300 Subject: [PATCH 08/13] arm64: dts: rockchip: add support for NanoPi M6 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-nanopi-m6.dts | 380 ++++++++++++++++++ 2 files changed, 381 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index cc385a51b10e0..751795a142e85 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -392,6 +392,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-lubancat-4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-m6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts new file mode 100644 index 0000000000000..0ad31a236b323 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3588s-nanopi-r6-common.dtsi" + +/ { + model = "FriendlyElec NanoPi M6"; + compatible = "friendlyelec,nanopi-m6", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac1; + }; + + rt5616_sound: rt5616-sound { + status = "okay"; + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphone Jack"; + + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + fan: pwm-fan { + status = "okay"; + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm5 0 50000 0>; + cooling-levels = <0 35 64 100 150 255>; + rockchip,hold-time-ms = <2000>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + user_led: led-1 { + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "user_led"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_pin>; + }; + }; + + vcc3v3_pcie_m2: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_pwren>; + regulator-name = "vcc3v3_pcie_m2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host_20: vcc5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_prsnt>; + prsnt-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + vpcie3v3-supply = <&vcc3v3_pcie_m2>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&sata0 { + phys = <&combphy0_ps PHY_TYPE_SATA>; + target-supply = <&vcc3v3_pcie_m2>; + status = "disabled"; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + /omit-if-no-ref/ + lcd_rst0_gpio: lcd-rst0-gpio { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcd_rst1_gpio: lcd-rst1-gpio { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi0_gpio: touch-dsi0-gpio { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi1_gpio: touch-dsi1-gpio { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_m2_0_pwren: pcie-m20-pwren { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_m2_0_prsnt: pcie-m20-prsnt { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +// DSI0 I2C +&i2c4 { + clock-frequency = <200000>; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +// DSI1 I2C +&i2c5 { + clock-frequency = <200000>; + pinctrl-0 = <&i2c5m2_xfer>; +}; + +// EEPROM is not mounted by default. +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: rt5616@1b { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "rt5616"; + reg = <0x1b>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + /* connected with MIPI-CSI1 */ +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + rockchip,trcm-sync-tx-only; +}; + +&pwm5 { + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +// DSI0 PWM +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; +}; + +// DSI1 PWM +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/* GPIO Connector */ +&i2c1 { + pinctrl-0 = <&i2c1m2_xfer>; + status = "disabled"; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; + status = "disabled"; + + spidev0: spidev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "disabled"; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; +}; + +&uart4 { + pinctrl-0 = <&uart4m2_xfer>; + status = "disabled"; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; + status = "okay"; +}; + +&uart6 { + pinctrl-0 = <&uart6m1_xfer>; + status = "okay"; +}; + +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +&uart8 { + pinctrl-0 = <&uart8m0_xfer>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; \ No newline at end of file From 3dc3af3ec0a161e8694ea0dc80757837d9f7dafb Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Sun, 6 Oct 2024 22:06:12 +0300 Subject: [PATCH 09/13] arm64: rockchip: add YX35 LCD overlays for NanoPi M6 --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 2 + .../overlay/nanopi-m6-display-dsi0-yx35.dts | 249 ++++++++++++++++++ .../overlay/nanopi-m6-display-dsi1-yx35.dts | 249 ++++++++++++++++++ .../boot/dts/rockchip/rk3588s-nanopi-m6.dts | 27 +- 4 files changed, 505 insertions(+), 22 deletions(-) create mode 100755 arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi0-yx35.dts create mode 100755 arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi1-yx35.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index 0327eb8babcad..03b2a87ab6efa 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -71,6 +71,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ khadas-edge2-cam1.dtbo \ khadas-edge2-cam2.dtbo \ khadas-edge2-cam3.dtbo \ + nanopi-m6-display-dsi0-yx35.dtbo \ + nanopi-m6-display-dsi1-yx35.dtbo \ rockchip-rk3588-opp-oc-24ghz.dtbo \ rockchip-rk3588-panthor-gpu.dtbo \ rk3566-roc-pc-sata2.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi0-yx35.dts b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi0-yx35.dts new file mode 100755 index 0000000000000..c3ec4c91e0a59 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi0-yx35.dts @@ -0,0 +1,249 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&pwm_backlight>; + + __overlay__ { + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm10 0 25000 0>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&pwm10>; + + __overlay__ { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c4>; + + __overlay__ { + clock-frequency = <200000>; + pinctrl-0 = <&i2c4m3_xfer>; + status = "okay"; + + dsi0_gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_dsi0_gpio>; + interrupt-parent = <&gpio3>; + interrupts = ; + goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_EDGE_FALLING>; + goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + keep-otp-config; + status = "okay"; + }; + + dsi0_e2prom: eeprom@50 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x50>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + status = "okay"; + }; + }; + }; + + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + connect = <&vp2_out_dsi0>; + status = "okay"; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + dsi0_panel: panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + + backlight = <&pwm_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst0_gpio>; + reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + panel-name = "yx35,210dpi"; + nvmems = <&dsi0_i2c 0x50 0xe0 0x10>; + nvmem-status = <1>; + + reset-delay-ms = <20>; + init-delay-ms = <120>; + enable-delay-ms = <5>; + prepare-delay-ms = <0>; + unprepare-delay-ms = <10>; + disable-delay-ms = <5>; + width-mm = <45>; + height-mm = <75>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <2>; + panel-init-sequence = [ + 15 0A 02 01 00 + 15 7D 02 11 00 + 39 00 06 FF 77 01 00 00 13 + 15 00 02 EF 08 + 39 00 06 FF 77 01 00 00 10 + 39 00 03 C0 63 00 + 39 00 03 C1 14 14 + 39 00 03 C2 37 02 + 15 00 02 CC 10 + 39 00 11 B0 C5 11 1B 0D 11 07 0A 09 08 24 05 12 10 A9 32 DF + 39 00 11 B1 C5 19 21 0B 0E 03 0C 07 07 26 04 12 11 AA 32 DF + 39 00 06 FF 77 01 00 00 11 + 15 00 02 B0 4D + 15 00 02 B1 59 + 15 00 02 B2 81 + 15 00 02 B3 80 + 15 00 02 B5 4E + 15 00 02 B7 85 + 15 00 02 B8 32 + 15 00 02 BB 03 + 15 00 02 C1 08 + 15 00 02 C2 08 + 15 00 02 D0 88 + 39 00 04 E0 00 00 02 + 39 00 0C E1 06 28 08 28 05 28 07 28 0E 33 33 + 39 00 0D E2 30 30 33 33 34 00 00 00 34 00 00 00 + 39 00 05 E3 00 00 33 33 + 39 00 03 E4 44 44 + 39 00 11 E5 09 2F 2C 8C 0B 31 2C 8C 0D 33 2C 8C 0F 35 2C 8C + 39 00 05 E6 00 00 33 33 + 39 00 03 E7 44 44 + 39 00 11 E8 08 2E 2C 8C 0A 30 2C 8C 0C 32 2C 8C 0E 34 2C 8C + 39 00 03 E9 36 00 + 39 00 08 EB 00 01 E4 E4 44 88 40 + 39 00 11 ED FF FC B2 45 67 FA 01 FF FF 10 AF 76 54 2B CF FF + 39 00 07 EF 08 08 08 45 3F 54 + 39 00 06 FF 77 01 00 00 13 + 39 00 03 E8 00 0E + 15 78 02 11 00 + 39 0A 03 E8 00 0C + 39 00 03 E8 00 00 + 39 00 06 FF 77 01 00 00 00 + 15 00 02 36 00 + 15 00 02 29 00 + ]; + + panel-exit-sequence = [ + 15 00 02 28 00 + 15 3C 02 10 00 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <29700000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <40>; + hsync-len = <32>; + hback-porch = <30>; + vfront-porch = <20>; + vsync-len = <10>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi1-yx35.dts b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi1-yx35.dts new file mode 100755 index 0000000000000..96670975e5b59 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi1-yx35.dts @@ -0,0 +1,249 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&pwm_backlight>; + + __overlay__ { + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm11 0 25000 0>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&pwm11>; + + __overlay__ { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c5>; + + __overlay__ { + clock-frequency = <200000>; + pinctrl-0 = <&i2c5m2_xfer>; + status = "okay"; + + dsi1_gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_dsi1_gpio>; + interrupt-parent = <&gpio4>; + interrupts = ; + goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>; + goodix,rst-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + keep-otp-config; + status = "okay"; + }; + + dsi1_e2prom: eeprom@50 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x50>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + status = "okay"; + }; + }; + }; + + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + connect = <&vp2_out_dsi1>; + status = "okay"; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + dsi1_panel: panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + + backlight = <&pwm_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst1_gpio>; + reset-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + panel-name = "yx35,210dpi"; + nvmems = <&i2c5 0x50 0xe0 0x10>; + nvmem-status = <1>; + + reset-delay-ms = <20>; + init-delay-ms = <120>; + enable-delay-ms = <5>; + prepare-delay-ms = <0>; + unprepare-delay-ms = <10>; + disable-delay-ms = <5>; + width-mm = <45>; + height-mm = <75>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <2>; + panel-init-sequence = [ + 15 0A 02 01 00 + 15 7D 02 11 00 + 39 00 06 FF 77 01 00 00 13 + 15 00 02 EF 08 + 39 00 06 FF 77 01 00 00 10 + 39 00 03 C0 63 00 + 39 00 03 C1 14 14 + 39 00 03 C2 37 02 + 15 00 02 CC 10 + 39 00 11 B0 C5 11 1B 0D 11 07 0A 09 08 24 05 12 10 A9 32 DF + 39 00 11 B1 C5 19 21 0B 0E 03 0C 07 07 26 04 12 11 AA 32 DF + 39 00 06 FF 77 01 00 00 11 + 15 00 02 B0 4D + 15 00 02 B1 59 + 15 00 02 B2 81 + 15 00 02 B3 80 + 15 00 02 B5 4E + 15 00 02 B7 85 + 15 00 02 B8 32 + 15 00 02 BB 03 + 15 00 02 C1 08 + 15 00 02 C2 08 + 15 00 02 D0 88 + 39 00 04 E0 00 00 02 + 39 00 0C E1 06 28 08 28 05 28 07 28 0E 33 33 + 39 00 0D E2 30 30 33 33 34 00 00 00 34 00 00 00 + 39 00 05 E3 00 00 33 33 + 39 00 03 E4 44 44 + 39 00 11 E5 09 2F 2C 8C 0B 31 2C 8C 0D 33 2C 8C 0F 35 2C 8C + 39 00 05 E6 00 00 33 33 + 39 00 03 E7 44 44 + 39 00 11 E8 08 2E 2C 8C 0A 30 2C 8C 0C 32 2C 8C 0E 34 2C 8C + 39 00 03 E9 36 00 + 39 00 08 EB 00 01 E4 E4 44 88 40 + 39 00 11 ED FF FC B2 45 67 FA 01 FF FF 10 AF 76 54 2B CF FF + 39 00 07 EF 08 08 08 45 3F 54 + 39 00 06 FF 77 01 00 00 13 + 39 00 03 E8 00 0E + 15 78 02 11 00 + 39 0A 03 E8 00 0C + 39 00 03 E8 00 00 + 39 00 06 FF 77 01 00 00 00 + 15 00 02 36 00 + 15 00 02 29 00 + ]; + + panel-exit-sequence = [ + 15 00 02 28 00 + 15 3C 02 10 00 + ]; + + display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <29700000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <40>; + hsync-len = <32>; + hback-porch = <30>; + vfront-porch = <20>; + vsync-len = <10>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts index 0ad31a236b323..4ad1229ab338e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts @@ -133,6 +133,11 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_usb>; }; + + pwm_backlight: pwm-backlight { + status = "disabled"; + compatible = "pwm-backlight"; + }; }; @@ -220,18 +225,6 @@ }; }; -// DSI0 I2C -&i2c4 { - clock-frequency = <200000>; - pinctrl-0 = <&i2c4m3_xfer>; -}; - -// DSI1 I2C -&i2c5 { - clock-frequency = <200000>; - pinctrl-0 = <&i2c5m2_xfer>; -}; - // EEPROM is not mounted by default. &i2c6 { clock-frequency = <200000>; @@ -285,16 +278,6 @@ status = "okay"; }; -// DSI0 PWM -&pwm10 { - pinctrl-0 = <&pwm10m2_pins>; -}; - -// DSI1 PWM -&pwm11 { - pinctrl-0 = <&pwm11m3_pins>; -}; - &u2phy0_otg { phy-supply = <&vbus5v0_typec>; status = "okay"; From 87ce5f6b063e72cb024f839b92fbc46ea1b675ad Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Sun, 6 Oct 2024 23:27:49 +0300 Subject: [PATCH 10/13] drm/rockchip: Fix logo aspect ratio calculation --- drivers/gpu/drm/rockchip/rockchip_drm_logo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_logo.c b/drivers/gpu/drm/rockchip/rockchip_drm_logo.c index ef7467ac8430f..de79238911992 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_logo.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_logo.c @@ -909,6 +909,11 @@ static int setup_initial_state(struct drm_device *drm_dev, primary_state->crtc_y = (vdisplay - fb_height) / 2; primary_state->crtc_h = fb_height; } + + if (set->fb->width > hdisplay) { + primary_state->crtc_h = (set->fb->height * hdisplay) / set->fb->width; + primary_state->crtc_y = (vdisplay - primary_state->crtc_h) / 2; + } } else { primary_state->crtc_x = 0; primary_state->crtc_y = 0; From e221d5dd7b91465e4e9c8fe34f498621e1742c0d Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Sun, 6 Oct 2024 23:28:52 +0300 Subject: [PATCH 11/13] drm/rockchip: vop2: demote invalid size error for cursor plane --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 0e1d6563ff4bd..ad2952318fb8c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -5373,9 +5373,10 @@ static int vop2_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_st if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { - DRM_ERROR("Invalid size: %dx%d->%dx%d, min size is 4x4\n", - drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, - drm_rect_width(dest), drm_rect_height(dest)); + if (plane->type != DRM_PLANE_TYPE_CURSOR) + DRM_ERROR("Invalid size: %dx%d->%dx%d, min size is 4x4\n", + drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, + drm_rect_width(dest), drm_rect_height(dest)); pstate->visible = false; return 0; } From 967f38bdbe5ffc147eec4536a2a3736ebed51077 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Sun, 6 Oct 2024 23:52:41 +0300 Subject: [PATCH 12/13] input: touchscreen: gt1x: support to keep otp config --- drivers/input/touchscreen/gt1x/gt1x.c | 6 ++++ drivers/input/touchscreen/gt1x/gt1x_generic.c | 29 ++++++++++++++----- drivers/input/touchscreen/gt1x/gt1x_generic.h | 1 + 3 files changed, 29 insertions(+), 7 deletions(-) diff --git a/drivers/input/touchscreen/gt1x/gt1x.c b/drivers/input/touchscreen/gt1x/gt1x.c index 7d54cd651ea2a..8f714f30f154d 100644 --- a/drivers/input/touchscreen/gt1x/gt1x.c +++ b/drivers/input/touchscreen/gt1x/gt1x.c @@ -364,6 +364,12 @@ static int gt1x_parse_dt(struct device *dev) } #endif +#if GTP_DRIVER_SEND_CFG + gt1x_keep_otp_config = of_property_read_bool(dev->of_node, "keep-otp-config"); +#else + gt1x_keep_otp_config = true; +#endif + return 0; } diff --git a/drivers/input/touchscreen/gt1x/gt1x_generic.c b/drivers/input/touchscreen/gt1x/gt1x_generic.c index 132fabdd6f9fd..cd137346c475f 100644 --- a/drivers/input/touchscreen/gt1x/gt1x_generic.c +++ b/drivers/input/touchscreen/gt1x/gt1x_generic.c @@ -73,6 +73,7 @@ u32 gt1x_abs_x_max; u32 gt1x_abs_y_max; int gt1x_halt; bool gt1x_ics_slot_report; +bool gt1x_keep_otp_config; #if GTP_DEBUG_NODE static ssize_t gt1x_debug_read_proc(struct file *, char __user *, size_t, loff_t *); @@ -629,14 +630,26 @@ s32 gt1x_init_panel(void) } set_reg_bit(gt1x_config[MODULE_SWITCH3_LOC], 5, !gt1x_wakeup_level); #endif /* END GTP_CUSTOM_CFG */ +#endif /* END GTP_DRIVER_SEND_CFG */ -#else /* DRIVER NOT SEND CONFIG */ - cfg_len = GTP_CONFIG_MAX_LENGTH; - ret = gt1x_i2c_read(GTP_REG_CONFIG_DATA, gt1x_config, cfg_len); - if (ret < 0) { - return ret; + if (gt1x_keep_otp_config) { + cfg_len = GTP_CONFIG_MAX_LENGTH; + ret = gt1x_i2c_read(GTP_REG_CONFIG_DATA, gt1x_config, cfg_len); + if (ret < 0) { + GTP_ERROR("Failed to read CONFIG data, sensor_id %d", gt1x_version.sensor_id); + return ret; + } else { + int i; + u16 checksum = 0; + for (i = 0; i < cfg_len - 4; i += 2) { + checksum += (gt1x_config[i] << 8) + gt1x_config[i + 1]; + } + checksum = 0 - checksum; + if (!checksum || checksum != ((gt1x_config[i] << 8) + gt1x_config[i + 1])) { + GTP_ERROR("Invalid config data, checksum %04x", checksum); + } + } } -#endif /* END GTP_DRIVER_SEND_CFG */ GTP_DEBUG_FUNC(); /* match resolution when gt1x_abs_x_max & gt1x_abs_y_max have been set already */ @@ -657,7 +670,9 @@ s32 gt1x_init_panel(void) GTP_INFO("X_MAX=%d,Y_MAX=%d,TRIGGER=0x%02x,WAKEUP_LEVEL=%d", gt1x_abs_x_max, gt1x_abs_y_max, gt1x_int_type, gt1x_wakeup_level); gt1x_cfg_length = cfg_len; - ret = gt1x_send_cfg(gt1x_config, gt1x_cfg_length); + if (!gt1x_keep_otp_config) { + ret = gt1x_send_cfg(gt1x_config, gt1x_cfg_length); + } return ret; } diff --git a/drivers/input/touchscreen/gt1x/gt1x_generic.h b/drivers/input/touchscreen/gt1x/gt1x_generic.h index f73e18283ea71..ac77f05df1aab 100644 --- a/drivers/input/touchscreen/gt1x/gt1x_generic.h +++ b/drivers/input/touchscreen/gt1x/gt1x_generic.h @@ -534,6 +534,7 @@ extern s32 gt1x_i2c_read(u16 addr, u8 *buffer, s32 len); extern s32 gt1x_i2c_read_dbl_check(u16 addr, u8 *buffer, s32 len); extern bool gt1x_ics_slot_report; +extern bool gt1x_keep_otp_config; extern u8 gt1x_config[]; extern u32 gt1x_cfg_length; extern u8 gt1x_int_type; From fbb6d426c9356de5c2b07bad1b090e545888d86f Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Sun, 6 Oct 2024 23:54:43 +0300 Subject: [PATCH 13/13] input: touchscreen: gt1x: add gt911 support --- drivers/input/touchscreen/gt1x/gt1x_generic.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/input/touchscreen/gt1x/gt1x_generic.c b/drivers/input/touchscreen/gt1x/gt1x_generic.c index cd137346c475f..d10d280bf6290 100644 --- a/drivers/input/touchscreen/gt1x/gt1x_generic.c +++ b/drivers/input/touchscreen/gt1x/gt1x_generic.c @@ -74,6 +74,7 @@ u32 gt1x_abs_y_max; int gt1x_halt; bool gt1x_ics_slot_report; bool gt1x_keep_otp_config; +static bool gtp_is_gt911; #if GTP_DEBUG_NODE static ssize_t gt1x_debug_read_proc(struct file *, char __user *, size_t, loff_t *); @@ -633,12 +634,14 @@ s32 gt1x_init_panel(void) #endif /* END GTP_DRIVER_SEND_CFG */ if (gt1x_keep_otp_config) { + u16 cfg_reg = gtp_is_gt911 ? 0x8047 : GTP_REG_CONFIG_DATA; + cfg_len = GTP_CONFIG_MAX_LENGTH; - ret = gt1x_i2c_read(GTP_REG_CONFIG_DATA, gt1x_config, cfg_len); + ret = gt1x_i2c_read(cfg_reg, gt1x_config, cfg_len); if (ret < 0) { GTP_ERROR("Failed to read CONFIG data, sensor_id %d", gt1x_version.sensor_id); return ret; - } else { + } else if (!gtp_is_gt911) { int i; u16 checksum = 0; for (i = 0; i < cfg_len - 4; i += 2) { @@ -874,7 +877,8 @@ s32 gt1x_read_version(struct gt1x_version_info *ver_info) memcpy(product_id, buf, 4); sensor_id = buf[10] & 0x0F; match_opt = (buf[10] >> 4) & 0x0F; - + + gtp_is_gt911 = !strncmp(product_id, "911", 3); GTP_INFO("IC VERSION:GT%s_%06X(Patch)_%04X(Mask)_%02X(SensorID)", product_id, patch_id, mask_id >> 8, sensor_id); if (ver_info != NULL) { @@ -1184,6 +1188,9 @@ s32 gt1x_touch_event_handler(u8 *data, struct input_dev *dev, struct input_dev * return ret; } + if (gtp_is_gt911) + goto skip_checksum; + for (i = 0, check_sum = 0; i < 3 + 8 * touch_num; i++) { check_sum += touch_data[i]; } @@ -1192,6 +1199,8 @@ s32 gt1x_touch_event_handler(u8 *data, struct input_dev *dev, struct input_dev * return ERROR_VALUE; } } + +skip_checksum: /* * cur_event , pre_event bit defination * bits: bit4 bit3 bit2 bit1 bit0