From 4e2f62354845759816d6a82f030ff090c48f8f57 Mon Sep 17 00:00:00 2001 From: Stephen Chen Date: Wed, 9 Nov 2022 20:59:16 +0800 Subject: [PATCH 001/249] scripts: install dtbo files to kernel packages Signed-off-by: Stephen Chen --- arch/arm/boot/.gitignore | 2 ++ arch/arm64/boot/.gitignore | 2 ++ scripts/Makefile.dtbinst | 7 ++++++- scripts/Makefile.lib | 14 ++++++++++++++ 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore index 8c759326baf44..7ced212024ca0 100644 --- a/arch/arm/boot/.gitignore +++ b/arch/arm/boot/.gitignore @@ -4,3 +4,5 @@ zImage xipImage bootpImage uImage +*.dtb* +*.scr \ No newline at end of file diff --git a/arch/arm64/boot/.gitignore b/arch/arm64/boot/.gitignore index af5dc61f8b438..1f74929d6f8ec 100644 --- a/arch/arm64/boot/.gitignore +++ b/arch/arm64/boot/.gitignore @@ -2,3 +2,5 @@ Image Image.gz vmlinuz* +*.dtb* +*.scr \ No newline at end of file diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index 190d781e84f4b..675fba9d6595b 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -18,9 +18,11 @@ include $(srctree)/scripts/Kbuild.include include $(src)/Makefile dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) +dtbos := $(addprefix $(dst)/, $(dtbo-y)) +readmes := $(addprefix $(dst)/, $(dtbotxt-y)) subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) -__dtbs_install: $(dtbs) $(subdirs) +__dtbs_install: $(dtbs) $(dtbos) $(readmes) $(subdirs) @: quiet_cmd_dtb_install = INSTALL $@ @@ -32,6 +34,9 @@ $(dst)/%.dtb: $(obj)/%.dtb $(dst)/%.dtbo: $(obj)/%.dtbo $(call cmd,dtb_install) +$(dst)/README.rockchip-overlays: $(src)/README.rockchip-overlays + $(call cmd,dtb_install) + PHONY += $(subdirs) $(subdirs): $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 21e8525b16742..7646ebf9d552a 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -349,6 +349,9 @@ ifeq ($(CONFIG_DTC_OMIT_EMPTY),y) DTC_FLAGS += -Wnode_empty endif +# Overlay support +DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg + # Disable noisy checks by default ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) DTC_FLAGS += -Wno-unit_address_vs_reg \ @@ -421,6 +424,17 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE $(call if_changed_dep,dtc) +quiet_cmd_dtco = DTCO $@ +cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ + $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ + $(DTC) -O dtb -o $@ -b 0 \ + -i $(dir $<) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) + +$(obj)/%.dtbo: $(src)/%.dts FORCE + $(call if_changed_dep,dtco) + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) # Bzip2 From 5a209b89fd5914797cb731e957c8715f1ee5b48a Mon Sep 17 00:00:00 2001 From: amazingfate Date: Wed, 1 Mar 2023 14:26:59 +0800 Subject: [PATCH 002/249] add device tree of rock-5b and orangepi-5/5b --- arch/arm64/boot/dts/rockchip/Makefile | 3 + .../dts/rockchip/rk3588-rock-5b-camera.dtsi | 208 ++++ .../dts/rockchip/rk3588-rock-5b-display.dtsi | 193 +++ .../boot/dts/rockchip/rk3588-rock-5b.dts | 1083 +++++++++++++++++ .../rockchip/rk3588s-orangepi-5-camera1.dtsi | 170 +++ .../rockchip/rk3588s-orangepi-5-camera2.dtsi | 182 +++ .../rockchip/rk3588s-orangepi-5-camera3.dtsi | 179 +++ .../dts/rockchip/rk3588s-orangepi-5-lcd.dtsi | 101 ++ .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 426 +++++++ .../boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 387 ++++++ .../boot/dts/rockchip/rk3588s-orangepi-5b.dts | 412 +++++++ .../boot/dts/rockchip/rk3588s-orangepi.dtsi | 606 +++++++++ 12 files changed, 3950 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-camera.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-display.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts create mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi create mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi create mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi create mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts create mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi create mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts create mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 4a8f5e8c89cce..3c6246917291b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -315,6 +315,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo3-v10-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-pcie-ep-demo-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-pcie-ep-demo-v11-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v10.dtb @@ -334,6 +335,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb8-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-camera.dtsi new file mode 100644 index 0000000000000..aff5628db5ea3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-camera.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + camera_pwdn_gpio: camera-pwdn-gpio { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + status = "disabled"; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "disabled"; + + imx415: imx415@1a { + status = "disabled"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + camera_imx219: camera-imx219@10 { + status = "disabled"; + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "disabled"; +}; + +&rkcif_mipi_lvds2 { + status = "disabled"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "disabled"; +}; + +&rkisp0 { + status = "disabled"; +}; + +&isp0_mmu { + status = "disabled"; +}; + +&rkisp0_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-display.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-display.dtsi new file mode 100644 index 0000000000000..e91a778cae88b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-display.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited. + * + */ + +/ { + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "disabled"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; +}; + +&pwm2 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; +}; + +&dsi1 { + status = "disabled"; + rockchip,lane-rate = <480>; + + dsi1_panel: panel@0 { + status = "disabled"; + compatible ="chongzhou,cz101b4001"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + + gt9xx: gt9xx@14 { + status = "disabled"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; + + focaltech: focaltech@38 { + status = "disabled"; + compatible = "focaltech,fts"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&focaltech_gpio>; + focaltech,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + focaltech,display-coords = <0 0 799 1279>; + }; +}; + +&pinctrl { + + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = + <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + focaltech { + focaltech_gpio: focaltech-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts new file mode 100644 index 0000000000000..e3e694e793c84 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -0,0 +1,1083 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588-rock-5b-display.dtsi" +#include "rk3588-rock-5b-camera.dtsi" + +/ { + model = "Radxa ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + bt_uart6: wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip,dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-es8316"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8316>; + }; + }; + }; + + rk_headset: rk-headset { + status = "okay"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_b>; + + led_rgb_b { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + //mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; + + route { + route_hdmi0: route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi0>; + }; + + route_hdmi1: route-hdmi1 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_hdmi1>; + }; + }; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + cec-enable = "true"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + //cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + //cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + //cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + //cursor-win-id = ; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc12v_dcin>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "sink"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&pinctrl { + leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi new file mode 100755 index 0000000000000..f87e5567d378f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy0_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out2>; + data-lanes = <1 2>; + }; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + vm149c_p1: vm149c-p1@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_1: ov13850-1@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p1>; + port { + ov13850_out2: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p1: dw9714-p1@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855-1@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p1>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "disabled"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0_vir1 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi new file mode 100755 index 0000000000000..2ae9ac623b938 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_cam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out>; + data-lanes = <1 2>; + }; + + mipi_in_cam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + vm149c_p2: vm149c-p2@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_2: ov13850-2@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p2>; + port { + ov13850_out: endpoint { + remote-endpoint = <&mipi_in_cam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p2: dw9714-p2@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_2: ov13855-2@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p2>; + port { + ov13855_out: endpoint { + remote-endpoint = <&mipi_in_cam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "disabled"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "disabled"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + +&rkisp0_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi new file mode 100755 index 0000000000000..c1d6f49dc6e96 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy1 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_dcphy0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out1>; + data-lanes = <1 2>; + }; + + mipi_in_dcphy1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vm149cp1: vm149c@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + }; + + ov13850_3: ov13850@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149cp1>; + port { + ov13850_out1: endpoint { + remote-endpoint = <&mipi_in_dcphy0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_3: ov13855@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipi_in_dcphy1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "disabled"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "disabled"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in0>; + }; + }; +}; + +&rkisp1_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi new file mode 100644 index 0000000000000..27a9a2cde5669 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&dsi0 { + status = "disabled"; +}; + +&dsi0_panel { + status = "disabled"; + reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp3_out_dsi0>; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + gt9xx_1: touchscreen@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + //touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + status = "okay"; + }; +}; + + + +&dsi1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "disabled"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + gt9xx_0: touchscreen@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PA7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + //touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file mode 100755 index 0000000000000..9f8bff1ee4701 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-orangepi-5.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588s-orangepi-5-lcd.dtsi" + +#include "rk3588s-orangepi-5-camera1.dtsi" +#include "rk3588s-orangepi-5-camera2.dtsi" +#include "rk3588s-orangepi-5-camera3.dtsi" + +/ { + model = "Orange Pi 5"; + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + enable-active-low; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + status = "okay"; + + led@1 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + cec-enable; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0{ + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,i2s-tx-route = <3 2 1 0>; + rockchip,i2s-rx-route = <1 3 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_lrck + &i2s1m0_sdi1 + &i2s1m0_sdo3>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +/* + pin3: GPIO1_B7 + pin5: GPIO1_B6 +*/ +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&uart1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; +}; + +&pwm13 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; +}; + +/* + pin7: GPIO1_C6 +*/ +&pwm15 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m2_pins>; +}; + +/* + pin11: GPIO4_B2 + pin13: GPIO4_B3 +*/ +&pwm14 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m1_pins>; +}; + +&can1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; +}; + +/* + pin15: GPIO0_D4 + pin12: GPIO0_D5 +*/ +&can2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <200000000>; +}; + +/* + pin19: GPIO1_C1 + pin21: GPIO1_C0 + pin23: GPIO1_C2 + pin24: GPIO1_C4 +*/ +&spi4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + spi_dev@1 { + compatible = "rockchip,spidev"; + reg = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&uart3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&pwm3 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m2_pins>; + //pinctrl-0 = <&pwm3m0_pins>; +}; + +/* + pin8: GPIO4_A3 + pin10: GPIO4_A4 +*/ +&uart0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +/* + pin16: GPIO1_D3 + pin18: GPIO1_D2 +*/ +&uart4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + //pinctrl-0 = <&i2c1m4_xfer>; + pinctrl-0 = <&i2c1m2_xfer>; +}; + +&pwm0 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +/* + pin26: GPIO1_A3 +*/ +&pwm1 { + status = "disabled"; + pinctrl-names = "active"; + //pinctrl-0 = <&pwm1m2_pins>; + pinctrl-0 = <&pwm1m1_pins>; +}; + +/* watchdog */ +&wdt { + status = "okay"; +}; + +&sfc { + status = "okay"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&sata0 { + pinctrl-names = "default"; + pinctrl-0 = <&sata_reset>; + status = "disabled"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi new file mode 100755 index 0000000000000..0aab227fe9823 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588s-orangepi.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + +&pwm6 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; +}; + +&backlight_1 { + pwms = <&pwm6 0 25000 0>; + status = "okay"; +}; + +&backlight { + pwms = <&pwm2 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&spdif_tx2{ + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pcie2x1l1 { + status = "disabled"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "disabled"; +}; + +&pinctrl { + sata { + sata_reset:sata-reset{ + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-func { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&usbhost3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts new file mode 100755 index 0000000000000..66305a01e4d44 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-orangepi-5.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588s-orangepi-5-lcd.dtsi" + +#include "rk3588s-orangepi-5-camera1.dtsi" +#include "rk3588s-orangepi-5-camera2.dtsi" +#include "rk3588s-orangepi-5-camera3.dtsi" + +/ { + model = "Orange Pi 5"; + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + enable-active-low; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + status = "okay"; + + led@1 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + cec-enable; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0{ + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,i2s-tx-route = <3 2 1 0>; + rockchip,i2s-rx-route = <1 3 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_lrck + &i2s1m0_sdi1 + &i2s1m0_sdo3>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +/* + pin3: GPIO1_B7 + pin5: GPIO1_B6 +*/ +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&uart1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; +}; + +&pwm13 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; +}; + +/* + pin7: GPIO1_C6 +*/ +&pwm15 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m2_pins>; +}; + +/* + pin11: GPIO4_B2 + pin13: GPIO4_B3 +*/ +&pwm14 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m1_pins>; +}; + +&can1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; +}; + +/* + pin15: GPIO0_D4 + pin12: GPIO0_D5 +*/ +&can2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <200000000>; +}; + +/* + pin19: GPIO1_C1 + pin21: GPIO1_C0 + pin23: GPIO1_C2 + pin24: GPIO1_C4 +*/ +&spi4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + spi_dev@1 { + compatible = "rockchip,spidev"; + reg = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&uart3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&pwm3 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m2_pins>; + //pinctrl-0 = <&pwm3m0_pins>; +}; + +/* + pin8: GPIO4_A3 + pin10: GPIO4_A4 +*/ +&uart0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +/* + pin16: GPIO1_D3 + pin18: GPIO1_D2 +*/ +&uart4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + //pinctrl-0 = <&i2c1m4_xfer>; + pinctrl-0 = <&i2c1m2_xfer>; +}; + +&pwm0 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +/* + pin26: GPIO1_A3 +*/ +&pwm1 { + status = "disabled"; + pinctrl-names = "active"; + //pinctrl-0 = <&pwm1m2_pins>; + pinctrl-0 = <&pwm1m1_pins>; +}; + +/* watchdog */ +&wdt { + status = "okay"; +}; + +&sfc { + status = "disabled"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&wireless_bluetooth { + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_wlan { + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl +{ + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi new file mode 100755 index 0000000000000..af25013fcbe8d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi @@ -0,0 +1,606 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight_1: backlight_1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight_1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +/* Fix tty terminal out of screen, and most dclk of resolutions was not supported in hdmiphy clock from parent clock by default */ +&display_subsystem { + clocks = <&hdptxphy_hdmi_clk0>; + clock-names = "hdmi0_phy_pll"; +}; From 5ac7ae2f02ac2f4fd5b542862e0b5fbf128e4bb4 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Wed, 1 Mar 2023 14:28:16 +0800 Subject: [PATCH 003/249] add dtb overlay for rock5b and orangepi5 --- arch/arm64/boot/dts/rockchip/Makefile | 2 + arch/arm64/boot/dts/rockchip/overlay/Makefile | 38 ++ .../rockchip/overlay/README.rockchip-overlays | 1 + .../dts/rockchip/overlay/orangepi-5-lcd1.dts | 88 +++++ .../dts/rockchip/overlay/orangepi-5-lcd2.dts | 88 +++++ .../dts/rockchip/overlay/orangepi-5-sata.dts | 20 + .../overlay/rock-4-okdo-5mp-camera.dts | 145 +++++++ .../overlay/rock-4-rpi-camera-v1p3.dts | 145 +++++++ .../rockchip/overlay/rock-4-rpi-camera-v2.dts | 145 +++++++ .../rock-4ab-raspi-7inch-touchscreen.dts | 103 +++++ .../rock-4c-plus-radxa-display-10fhd.dts | 270 +++++++++++++ .../rock-4c-plus-radxa-display-10hd.dts | 254 +++++++++++++ .../rock-4c-plus-radxa-display-8hd.dts | 255 +++++++++++++ .../rock-4c-plus-raspi-7inch-touchscreen.dts | 142 +++++++ .../dts/rockchip/overlay/rock-5a-hdmi-8k.dts | 21 ++ .../overlay/rock-5a-i2c5-rtc-hym8563.dts | 51 +++ .../overlay/rock-5a-radxa-camera-4k.dts | 207 ++++++++++ .../overlay/rock-5a-radxa-display-10hd.dts | 227 +++++++++++ .../overlay/rock-5a-radxa-display-8hd.dts | 230 ++++++++++++ .../overlay/rock-5a-spi-nor-flash.dts | 54 +++ .../dts/rockchip/overlay/rock-5a-usb-otg.dts | 21 ++ .../overlay/rock-5ab-camera-imx415.dts | 101 +++++ .../dts/rockchip/overlay/rock-5b-hdmi1-8k.dts | 63 ++++ .../dts/rockchip/overlay/rock-5b-hdmi2-8k.dts | 79 ++++ .../overlay/rock-5b-pd-max-voltage-12v.dts | 24 ++ .../overlay/rock-5b-radxa-display-10hd.dts | 101 +++++ .../overlay/rock-5b-radxa-display-8hd.dts | 101 +++++ .../overlay/rock-5b-rpi-camera-v2.dts | 123 ++++++ .../dts/rockchip/overlay/rock-5b-sata.dts | 37 ++ .../overlay/rockchip-rk3588-opp-oc-24ghz.dts | 355 ++++++++++++++++++ 30 files changed, 3491 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/Makefile create mode 100644 arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays create mode 100644 arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd1.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/orangepi-5-sata.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4-okdo-5mp-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v1p3.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4ab-raspi-7inch-touchscreen.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10fhd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10hd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-8hd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-raspi-7inch-touchscreen.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5a-hdmi-8k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5a-i2c5-rtc-hym8563.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-camera-4k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10hd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-8hd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5a-spi-nor-flash.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5a-usb-otg.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5ab-camera-imx415.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi1-8k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi2-8k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-pd-max-voltage-12v.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10hd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-8hd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-sata.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-opp-oc-24ghz.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3c6246917291b..c68b6f4d70238 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -340,3 +340,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb + +subdir-y := $(dts-dirs) overlay diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile new file mode 100644 index 0000000000000..6e1eaa892d17b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + orangepi-5-lcd1.dtbo \ + orangepi-5-lcd2.dtbo \ + orangepi-5-sata.dtbo \ + rock-4ab-raspi-7inch-touchscreen.dtbo \ + rock-4c-plus-radxa-display-10fhd.dtbo \ + rock-4c-plus-radxa-display-10hd.dtbo \ + rock-4c-plus-radxa-display-8hd.dtbo \ + rock-4c-plus-raspi-7inch-touchscreen.dtbo \ + rock-4-okdo-5mp-camera.dtbo \ + rock-4-rpi-camera-v1p3.dtbo \ + rock-4-rpi-camera-v2.dtbo \ + rock-5ab-camera-imx415.dtbo \ + rock-5a-hdmi-8k.dtbo \ + rock-5a-i2c5-rtc-hym8563.dtbo \ + rock-5a-radxa-camera-4k.dtbo \ + rock-5a-radxa-display-10hd.dtbo \ + rock-5a-radxa-display-8hd.dtbo \ + rock-5a-spi-nor-flash.dtbo \ + rock-5a-usb-otg.dtbo \ + rock-5b-hdmi1-8k.dtbo \ + rock-5b-hdmi2-8k.dtbo \ + rock-5b-pd-max-voltage-12v.dtbo \ + rock-5b-radxa-display-10hd.dtbo \ + rock-5b-radxa-display-8hd.dtbo \ + rock-5b-rpi-camera-v2.dtbo \ + rock-5b-sata.dtbo \ + rockchip-rk3588-opp-oc-24ghz.dtbo + +dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \ + README.rockchip-overlays + +targets += $(dtbo-y) $(dtbotxt-y) + +always-y := $(dtbo-y) $(dtbotxt-y) +clean-files := *.dtbo + diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays new file mode 100644 index 0000000000000..491c78cb7addf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays @@ -0,0 +1 @@ +## Introduction \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd1.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd1.dts new file mode 100644 index 0000000000000..04ece31f0970b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd1.dts @@ -0,0 +1,88 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&dsi1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&dsi1_panel>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi1_in_vp3>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@4 { + target = <&hdmi0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&hdptxphy_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&route_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&dp0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dp0_in_vp1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&dp0_in_vp2>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&dp0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&spdif_tx2>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd2.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd2.dts new file mode 100644 index 0000000000000..30765cc8f87d5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd2.dts @@ -0,0 +1,88 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&dsi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&dsi0_panel>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi0_in_vp2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@4 { + target = <&hdmi0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&hdptxphy_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&route_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&dp0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dp0_in_vp1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&dp0_in_vp2>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&dp0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&spdif_tx2>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-sata.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-sata.dts new file mode 100644 index 0000000000000..2ec37defd3185 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-sata.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&sata0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&pcie2x1l2>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4-okdo-5mp-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4-okdo-5mp-camera.dts new file mode 100644 index 0000000000000..65b1a3b1838f1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4-okdo-5mp-camera.dts @@ -0,0 +1,145 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable OKDO 5MP Camera on ROCK 4"; + compatible = "rockchip,rk3399"; + category = "camera"; + description = "Enable OKDO 5MP Camera on ROCK 4"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_ov5647: camera-ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + + clocks = <&clk_cam_25m>; + clock-names = "xclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "OKDO-5MP"; + rockchip,camera-module-lens-name = "default"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi_dphy_rx0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp1_0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; + }; + }; + + fragment@5 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v1p3.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v1p3.dts new file mode 100644 index 0000000000000..c61db0de7546a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v1p3.dts @@ -0,0 +1,145 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera V1.3 on ROCK 4"; + compatible = "rockchip,rk3399"; + category = "camera"; + description = "Enable Raspberry Pi Camera V1.3 on ROCK 4"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_ov5647: camera-ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + + clocks = <&clk_cam_25m>; + clock-names = "xclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v1p3"; + rockchip,camera-module-lens-name = "default"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi_dphy_rx0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp1_0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; + }; + }; + + fragment@5 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v2.dts new file mode 100644 index 0000000000000..597ae0f3c0dbf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4-rpi-camera-v2.dts @@ -0,0 +1,145 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2 on ROCK 4"; + compatible = "rockchip,rk3399"; + category = "camera"; + description = "Enable Raspberry Pi Camera V2 on ROCK 4"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + status = "okay"; + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi_dphy_rx0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp1_0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; + }; + }; + + fragment@5 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4ab-raspi-7inch-touchscreen.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4ab-raspi-7inch-touchscreen.dts new file mode 100644 index 0000000000000..4fe1822595714 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4ab-raspi-7inch-touchscreen.dts @@ -0,0 +1,103 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Enable Raspberry Pi 7-inch Touchscreen on ROCK 4 A/B/SE"; + compatible = "rockchip,rk3399"; + category = "display"; + description = "Enable Raspberry Pi 7-inch Touchscreen on ROCK 4 A/B/SE"; + }; + + fragment@0 { + target = <&dsi>; + + __overlay__ { + dsi1-only; + status = "okay"; + }; + }; + + fragment@1 { + target = <&dsi1>; + + __overlay__ { + rockchip,dsi-dsi0 = <&dsi>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + rockchip,lane-rate = <696>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + raspits_panel: raspits-panel@45 { + compatible = "raspberrypi,7inch-touchscreen-panel"; + reg = <0x45>; + + port { + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + raspits_touch_ft5426: raspits-touch-ft5426@38 { + compatible = "raspits_ft5426"; + reg = <0x38>; + }; + }; + }; + + fragment@3 { + target = <&vopl_out_dsi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi1_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&dsi1_in_vopl>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&route_dsi>; + + __overlay__ { + status = "disabled"; + connect = <&vopl_out_dsi>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10fhd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10fhd.dts new file mode 100644 index 0000000000000..a1cdc581598e5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10fhd.dts @@ -0,0 +1,270 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title = "Enable Radxa Display 10FHD"; + compatible = "radxa,rock-4c-plus"; + category = "display"; + description = "Enable Radxa Display 10FHD"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi>; + + __overlay__ { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + + dsi_panel: dsi-panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + backlight = <&backlight>; + power-supply = <&lcd_3v3>; + + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_panel_reset>; + + prepare-delay-ms = <120>; + reset-delay-ms = <120>; + init-delay-ms = <120>; + enable-delay-ms = <100>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + + width-mm = <62>; + height-mm = <110>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 + 05 00 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + + vback-porch = <25>; + vfront-porch = <35>; + + hback-porch = <60>; + hfront-porch = <80>; + + hsync-len = <4>; + vsync-len = <4>; + + vsync-active = <0>; + hsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&vopl_out_dsi>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi_in_vopl>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&dsi_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&route_dsi>; + + __overlay__ { + status = "disabled"; + connect = <&vopl_out_dsi>; + }; + }; + + fragment@7 { + target = <&vcc3v3_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&virtual_pd>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&tcphy0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&cdn_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&tcphy0_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@12 { + target = <&dp_in_vopl>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@13 { + target = <&dp_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@14 { + target = <&pinctrl>; + + __overlay__ { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10hd.dts new file mode 100644 index 0000000000000..3e831863d4ce7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-10hd.dts @@ -0,0 +1,254 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable Radxa Display 10HD"; + compatible = "radxa,rock-4c-plus"; + category = "display"; + description = "Enable Radxa Display 10HD"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi>; + + __overlay__ { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + rockchip,lane-rate = <480>; + + dsi_panel: panel@0 { + status = "okay"; + compatible = "chongzhou,cz101b4001"; + reg = <0>; + + backlight = <&backlight>; + power-supply = <&lcd_3v3>; + + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_panel_reset>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&vopl_out_dsi>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi_in_vopl>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&dsi_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&route_dsi>; + + __overlay__ { + status = "disabled"; + connect = <&vopl_out_dsi>; + }; + }; + + fragment@7 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech: focaltech@38 { + status = "okay"; + compatible = "focaltech,fts"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&focaltech_gpio>; + focaltech,irq-gpio = <&gpio1 RK_PD0 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + focaltech,display-coords = <0 0 799 1279>; + tp-supply = <&vcc_mipi>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + focaltech { + focaltech_gpio: focaltech-gpio { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; + + fragment@9 { + target = <&vcc3v3_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&virtual_pd>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&tcphy0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@12 { + target = <&cdn_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@13 { + target = <&tcphy0_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@14 { + target = <&dp_in_vopl>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@15 { + target = <&dp_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-8hd.dts new file mode 100644 index 0000000000000..32325c51ac14b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-radxa-display-8hd.dts @@ -0,0 +1,255 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable Radxa Display 8HD"; + compatible = "radxa,rock-4c-plus"; + category = "display"; + description = "Enable Radxa Display 8HD"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi>; + + __overlay__ { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + rockchip,lane-rate = <480>; + + dsi_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + + backlight = <&backlight>; + power-supply = <&lcd_3v3>; + + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_panel_reset>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&vopl_out_dsi>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi_in_vopl>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&dsi_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&route_dsi>; + + __overlay__ { + status = "disabled"; + connect = <&vopl_out_dsi>; + }; + }; + + fragment@7 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio1 RK_PD0 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_mipi>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; + + fragment@9 { + target = <&vcc3v3_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&virtual_pd>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&tcphy0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@12 { + target = <&cdn_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@13 { + target = <&tcphy0_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@14 { + target = <&dp_in_vopl>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@15 { + target = <&dp_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-raspi-7inch-touchscreen.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-raspi-7inch-touchscreen.dts new file mode 100644 index 0000000000000..1f12af4c38b97 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-4c-plus-raspi-7inch-touchscreen.dts @@ -0,0 +1,142 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable Raspberry Pi 7-inch Touchscreen"; + compatible = "radxa,rock-4c-plus"; + category = "display"; + description = "Enable Raspberry Pi 7-inch Touchscreen"; + }; + + fragment@0 { + target = <&dsi>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + rockchip,lane-rate = <696>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + raspits_panel: raspits-panel@45 { + compatible = "raspberrypi,7inch-touchscreen-panel"; + reg = <0x45>; + + port { + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + raspits_touch_ft5426: raspits-touch-ft5426@38 { + compatible = "raspits_ft5426"; + reg = <0x38>; + }; + }; + }; + + fragment@2 { + target = <&vopl_out_dsi>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi_in_vopl>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi>; + + __overlay__ { + status = "okay"; + connect = <&vopl_out_dsi>; + }; + }; + + fragment@5 { + target = <&vcc3v3_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&virtual_pd>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&tcphy0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&cdn_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&tcphy0_dp>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&dp_in_vopl>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&dp_in_vopb>; + + __overlay__ { + status = "disabled"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-hdmi-8k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-hdmi-8k.dts new file mode 100644 index 0000000000000..5337d42112b5e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-hdmi-8k.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; +#include + +/ { + metadata { + title ="Enable 8K output on ROCK 5A"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "display"; + description = "Enable 8K output on ROCK 5A"; + }; + + fragment@0 { + target = <&vop>; + + __overlay__ { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-i2c5-rtc-hym8563.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-i2c5-rtc-hym8563.dts new file mode 100644 index 0000000000000..e4fedcd48381b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-i2c5-rtc-hym8563.dts @@ -0,0 +1,51 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable RTC Hym8563 on I2C-5 bus on ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "misc"; + description = "Enable RTC Hym8563 on I2C-5 bus on ROCK 5A"; + }; + + fragment@0 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + }; + }; + }; + + fragment@1 { + target = <&pinctrl>; + + __overlay__ { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-camera-4k.dts new file mode 100644 index 0000000000000..92c927a39ff94 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-camera-4k.dts @@ -0,0 +1,207 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "camera"; + description = "Enable Radxa Camera 4K on ROCK 5A"; + }; + + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10hd.dts new file mode 100644 index 0000000000000..cf20e0fee81d8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10hd.dts @@ -0,0 +1,227 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD on ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "display"; + description = "Enable Radxa Display 8HD on ROCK 5A"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_tp: vcc-tp { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_tp"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + enable-active-low; + regulator-boot-on; + regulator-always-on; + }; + + vcc_lcd_mipi0: vcc-lcd-mipi0 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi0"; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi0_backlight: dsi0-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm10 0 25000 0>; + brightness-levels = < + 255 254 253 252 251 250 249 248 + 247 246 245 244 243 242 241 240 + 239 238 237 236 235 234 233 232 + 231 230 229 228 227 226 225 224 + 223 222 221 220 219 218 217 216 + 215 214 213 212 211 210 209 208 + 207 206 205 204 203 202 201 200 + 199 198 197 196 195 194 193 192 + 191 190 189 188 187 186 185 184 + 183 182 181 180 179 178 177 176 + 175 174 173 172 171 170 169 168 + 167 166 165 164 163 162 161 160 + 159 158 157 156 155 154 153 152 + 151 150 149 148 147 146 145 144 + 143 142 141 140 139 138 137 136 + 135 134 133 132 131 130 129 128 + 127 126 125 124 123 122 121 120 + 119 118 117 116 115 114 113 112 + 111 110 109 108 107 106 105 104 + 103 102 101 100 99 98 97 96 + 95 94 93 92 91 90 89 88 + 87 86 85 84 83 82 81 80 + 79 78 77 76 75 74 73 72 + 71 70 69 68 67 66 65 64 + 63 62 61 60 59 58 57 56 + 55 54 53 52 51 50 49 48 + 47 46 45 44 43 42 41 40 + 39 38 38 37 37 36 36 35 + 35 34 34 33 33 32 32 31 + 31 30 30 29 29 28 28 27 + 27 26 26 25 25 24 24 23 + 23 22 22 21 21 20 20 0 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm10>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-10hd-ad001"; + reg = <0>; + backlight = <&dsi0_backlight>; + + vdd-supply = <&vcc_lcd_mipi0>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech: focaltech@38 { + status = "okay"; + compatible = "focaltech,fts"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&focaltech_gpio>; + focaltech,irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + focaltech,display-coords = <0 0 799 1279>; + }; + }; + }; + + fragment@10 { + target = <&pinctrl>; + + __overlay__ { + dsi0-lcd { + dsi0_lcd_rst_gpio: dsi0-lcd-rst-gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi0_backlight_en: dsi0-backlight-en { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + focaltech { + focaltech_gpio: focaltech-gpio { + rockchip,pins = + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-8hd.dts new file mode 100644 index 0000000000000..787e8186c694f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-8hd.dts @@ -0,0 +1,230 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD on ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "display"; + description = "Enable Radxa Display 8HD on ROCK 5A"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_tp: vcc-tp { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_tp"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + enable-active-low; + regulator-boot-on; + regulator-always-on; + }; + + vcc_lcd_mipi0: vcc-lcd-mipi0 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi0"; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi0_backlight: dsi0-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm10 0 25000 0>; + brightness-levels = < + 255 254 253 252 251 250 249 248 + 247 246 245 244 243 242 241 240 + 239 238 237 236 235 234 233 232 + 231 230 229 228 227 226 225 224 + 223 222 221 220 219 218 217 216 + 215 214 213 212 211 210 209 208 + 207 206 205 204 203 202 201 200 + 199 198 197 196 195 194 193 192 + 191 190 189 188 187 186 185 184 + 183 182 181 180 179 178 177 176 + 175 174 173 172 171 170 169 168 + 167 166 165 164 163 162 161 160 + 159 158 157 156 155 154 153 152 + 151 150 149 148 147 146 145 144 + 143 142 141 140 139 138 137 136 + 135 134 133 132 131 130 129 128 + 127 126 125 124 123 122 121 120 + 119 118 117 116 115 114 113 112 + 111 110 109 108 107 106 105 104 + 103 102 101 100 99 98 97 96 + 95 94 93 92 91 90 89 88 + 87 86 85 84 83 82 81 80 + 79 78 77 76 75 74 73 72 + 71 70 69 68 67 66 65 64 + 63 62 61 60 59 58 57 56 + 55 54 53 52 51 50 49 48 + 47 46 45 44 43 42 41 40 + 39 38 38 37 37 36 36 35 + 35 34 34 33 33 32 32 31 + 31 30 30 29 29 28 28 27 + 27 26 26 25 25 24 24 23 + 23 22 22 21 21 20 20 0 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm10>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible ="radxa,display-8hd"; + reg = <0>; + backlight = <&dsi0_backlight>; + + vdd-supply = <&vcc_lcd_mipi0>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_tp>; + }; + }; + }; + + fragment@10 { + target = <&pinctrl>; + + __overlay__ { + dsi0-lcd { + dsi0_lcd_rst_gpio: dsi0-lcd-rst-gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi0_backlight_en: dsi0-backlight-en { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-spi-nor-flash.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-spi-nor-flash.dts new file mode 100644 index 0000000000000..6d7723747a82a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-spi-nor-flash.dts @@ -0,0 +1,54 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Enable SPI Nor Flash on ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "misc"; + description = "Enable SPI Nor Flash on ROCK 5A"; + }; + + fragment@0 { + target = <&sfc>; + + __overlay__ { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&sdhci>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-usb-otg.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-usb-otg.dts new file mode 100644 index 0000000000000..50ce0dd7e2142 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-usb-otg.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Set Type-A OTG port in OTG mode for ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "misc"; + description = "Set Type-A OTG port in OTG mode for ROCK 5A"; + }; + + fragment@0 { + target = <&usbdrd_dwc3_0>; + + __overlay__ { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5ab-camera-imx415.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5ab-camera-imx415.dts new file mode 100644 index 0000000000000..fbe851017f6a5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5ab-camera-imx415.dts @@ -0,0 +1,101 @@ +// ROCK 5A/5B Camera IMX415 +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&imx415>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi1-8k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi1-8k.dts new file mode 100644 index 0000000000000..0f02f383cc0bc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi1-8k.dts @@ -0,0 +1,63 @@ +/dts-v1/; +/plugin/; +#include + +/ { + metadata { + title ="Enable 8K output on HDMI1"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "display"; + description = "Enable 8K output on HDMI1. Note: 8K cannot be enabled on HDMI1 and HDMI2 at the same time."; + }; + + fragment@0 { + target = <&route_hdmi1>; + + __overlay__ { + connect = <&vp2_out_hdmi1>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&hdmi1_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&hdmi1_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&route_hdmi0>; + + __overlay__ { + connect = <&vp0_out_hdmi0>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi0_in_vp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&vop>; + + __overlay__ { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi2-8k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi2-8k.dts new file mode 100644 index 0000000000000..f6562881462a5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi2-8k.dts @@ -0,0 +1,79 @@ +/dts-v1/; +/plugin/; +#include + +/ { + metadata { + title ="Enable 8K output on HDMI2"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "display"; + description = "Enable 8K output on HDMI2. Note: 8K cannot be enabled on HDMI1 and HDMI2 at the same time."; + }; + + fragment@0 { + target = <&route_hdmi1>; + + __overlay__ { + connect = <&vp0_out_hdmi1>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&hdmi1_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&hdmi1_in_vp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&route_hdmi0>; + + __overlay__ { + connect = <&vp2_out_hdmi0>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi0_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&hdmi0_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&hdmi0_in_vp0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&vop>; + + __overlay__ { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-pd-max-voltage-12v.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-pd-max-voltage-12v.dts new file mode 100644 index 0000000000000..5ebf037028204 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-pd-max-voltage-12v.dts @@ -0,0 +1,24 @@ +/dts-v1/; +/plugin/; + +#include "dt-bindings/usb/pd.h" + +/ { + metadata { + title ="Power Supply PD 12V on ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "misc"; + description = "Power Supply PD 12V on ROCK 5B."; + }; + + fragment@0 { + target = <&usb_con>; + + __overlay__ { + sink-pdos = + ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10hd.dts new file mode 100644 index 0000000000000..ca838253c8e92 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10hd.dts @@ -0,0 +1,101 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Enable Radxa Display 10HD on ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "display"; + description = "Enable Radxa Display 10HD on ROCK 5B"; + }; + + fragment@0 { + target = <&vcc_lcd_mipi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&dsi1_backlight>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi1_panel>; + + __overlay__ { + status = "okay"; + compatible ="chongzhou,cz101b4001"; + }; + }; + + fragment@5 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@7 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&focaltech>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-8hd.dts new file mode 100644 index 0000000000000..03fbfaa779c33 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-8hd.dts @@ -0,0 +1,101 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Enable Radxa Display 8HD on ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "display"; + description = "Enable Radxa Display 8HD on ROCK 5B"; + }; + + fragment@0 { + target = <&vcc_lcd_mipi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&dsi1_backlight>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi1_panel>; + + __overlay__ { + status = "okay"; + compatible ="radxa,display-8hd"; + }; + }; + + fragment@5 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@7 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <>9xx>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v2.dts new file mode 100644 index 0000000000000..f02a659a14c48 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v2.dts @@ -0,0 +1,123 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2 on ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "camera"; + description = "Enable Raspberry Pi Camera V2 on ROCK 5B"; + }; + + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&camera_imx219>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&camera_pwdn_gpio>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@13 { + target = <&clk_cam_24m>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-sata.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-sata.dts new file mode 100644 index 0000000000000..2f38b7c0fcf8d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-sata.dts @@ -0,0 +1,37 @@ +// ROCK 5B Pcie M.2 to sata +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&wifi_disable>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&bt_wake>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&pcie2x1l0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&sata1>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-opp-oc-24ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-opp-oc-24ghz.dts new file mode 100644 index 0000000000000..d329e22a3f612 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-opp-oc-24ghz.dts @@ -0,0 +1,355 @@ +// RK3588 CPU Overclock to 2.4 GHz + +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Overclock Big Cores to 2.4 GHz on RK3588/RK3588S boards"; + compatible = "rockchip,rk3588"; + category = "misc"; + description = "Overclock Big Cores to 2.4 GHz on RK3588/RK3588S boards"; + }; + + fragment@0 { + target = <&cluster1_opp_table>; + __overlay__ { + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L2 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L3 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L4 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L5 = <687500 687500 1050000>, + <687500 687500 1050000>; + opp-microvolt-L6 = <675000 675000 1050000>, + <675000 675000 1050000>; + opp-microvolt-L7 = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1050000>, + <762500 762500 1050000>; + opp-microvolt-L2 = <750000 750000 1050000>, + <750000 750000 1050000>; + opp-microvolt-L3 = <737500 737500 1050000>, + <737500 737500 1050000>; + opp-microvolt-L4 = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L5 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L6 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L7 = <700000 700000 1050000>, + <700000 700000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L1 = <837500 837500 1050000>, + <837500 837500 1050000>; + opp-microvolt-L2 = <825000 825000 1050000>, + <825000 825000 1050000>; + opp-microvolt-L3 = <812500 812500 1050000>, + <812500 812500 1050000>; + opp-microvolt-L4 = <800000 800000 1050000>, + <800000 800000 1050000>; + opp-microvolt-L5 = <787500 787500 1050000>, + <787500 787500 1050000>; + opp-microvolt-L6 = <775000 775000 1050000>, + <775000 775000 1050000>; + opp-microvolt-L7 = <762500 762500 1050000>, + <762500 762500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L1 = <912500 912500 1050000>, + <912500 912500 1050000>; + opp-microvolt-L2 = <900000 900000 1050000>, + <900000 900000 1050000>; + opp-microvolt-L3 = <887500 887500 1050000>, + <887500 887500 1050000>; + opp-microvolt-L4 = <875000 875000 1050000>, + <875000 875000 1050000>; + opp-microvolt-L5 = <862500 862500 1050000>, + <862500 862500 1050000>; + opp-microvolt-L6 = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L7 = <837500 837500 1050000>, + <837500 837500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1050000>, + <987500 987500 1050000>; + opp-microvolt-L1 = <975000 975000 1050000>, + <975000 975000 1050000>; + opp-microvolt-L2 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L3 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L4 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L5 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L6 = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L7 = <912500 912500 1050000>, + <912500 912500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1050000>, + <1000000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1030000 1000000 1050000>, + <1030000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1040000 1010000 1050000>, + <1040000 1010000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1050000 1020000 1050000>, + <1050000 1020000 1050000>; + clock-latency-ns = <40000>; + }; + }; + }; + + fragment@1 { + target = <&cluster2_opp_table>; + __overlay__ { + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L2 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L3 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L4 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L5 = <687500 687500 1050000>, + <687500 687500 1050000>; + opp-microvolt-L6 = <675000 675000 1050000>, + <675000 675000 1050000>; + opp-microvolt-L7 = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1050000>, + <762500 762500 1050000>; + opp-microvolt-L2 = <750000 750000 1050000>, + <750000 750000 1050000>; + opp-microvolt-L3 = <737500 737500 1050000>, + <737500 737500 1050000>; + opp-microvolt-L4 = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L5 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L6 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L7 = <700000 700000 1050000>, + <700000 700000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L1 = <837500 837500 1050000>, + <837500 837500 1050000>; + opp-microvolt-L2 = <825000 825000 1050000>, + <825000 825000 1050000>; + opp-microvolt-L3 = <812500 812500 1050000>, + <812500 812500 1050000>; + opp-microvolt-L4 = <800000 800000 1050000>, + <800000 800000 1050000>; + opp-microvolt-L5 = <787500 787500 1050000>, + <787500 787500 1050000>; + opp-microvolt-L6 = <775000 775000 1050000>, + <775000 775000 1050000>; + opp-microvolt-L7 = <762500 762500 1050000>, + <762500 762500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L1 = <912500 912500 1050000>, + <912500 912500 1050000>; + opp-microvolt-L2 = <900000 900000 1050000>, + <900000 900000 1050000>; + opp-microvolt-L3 = <887500 887500 1050000>, + <887500 887500 1050000>; + opp-microvolt-L4 = <875000 875000 1050000>, + <875000 875000 1050000>; + opp-microvolt-L5 = <862500 862500 1050000>, + <862500 862500 1050000>; + opp-microvolt-L6 = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L7 = <837500 837500 1050000>, + <837500 837500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1050000>, + <987500 987500 1050000>; + opp-microvolt-L1 = <975000 975000 1050000>, + <975000 975000 1050000>; + opp-microvolt-L2 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L3 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L4 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L5 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L6 = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L7 = <912500 912500 1050000>, + <912500 912500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1050000>, + <1000000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1030000 1000000 1050000>, + <1030000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1040000 1010000 1050000>, + <1040000 1010000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1050000 1020000 1050000>, + <1050000 1020000 1050000>; + clock-latency-ns = <40000>; + }; + }; + }; +}; From 28ba80185597798df966692329fff279885d01d7 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Thu, 2 Mar 2023 14:49:14 +0800 Subject: [PATCH 004/249] bluetooth: add Realtek HCI USB driver support --- drivers/bluetooth/Kconfig | 11 + drivers/bluetooth/Makefile | 3 + drivers/bluetooth/rtk_bt.c | 1899 +++++++++++++++++++++ drivers/bluetooth/rtk_bt.h | 148 ++ drivers/bluetooth/rtk_coex.c | 3069 ++++++++++++++++++++++++++++++++++ drivers/bluetooth/rtk_coex.h | 373 +++++ drivers/bluetooth/rtk_misc.c | 2108 +++++++++++++++++++++++ drivers/bluetooth/rtk_misc.h | 95 ++ 8 files changed, 7706 insertions(+) create mode 100644 drivers/bluetooth/rtk_bt.c create mode 100644 drivers/bluetooth/rtk_bt.h create mode 100644 drivers/bluetooth/rtk_coex.c create mode 100644 drivers/bluetooth/rtk_coex.h create mode 100644 drivers/bluetooth/rtk_misc.c create mode 100644 drivers/bluetooth/rtk_misc.h diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig index e307074054553..ec9f6401e835b 100644 --- a/drivers/bluetooth/Kconfig +++ b/drivers/bluetooth/Kconfig @@ -442,4 +442,15 @@ config BT_VIRTIO Say Y here to compile support for HCI over Virtio into the kernel or say M to compile as a module. +config BT_HCIBTUSB_RTLBTUSB + tristate "Realtek HCI USB driver support" + depends on USB + help + Realtek Bluetooth HCI USB driver. + This driver is required if you want to use Realtek Bluetooth + device with USB interface. + + Say Y here to compile support for Bluetooth USB devices into the + kernel or say M to compile it as module (rtk_btusb). + endmenu diff --git a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile index 3321a8aea4a06..1552090be54cd 100644 --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@ -49,3 +49,6 @@ hci_uart-$(CONFIG_BT_HCIUART_QCA) += hci_qca.o hci_uart-$(CONFIG_BT_HCIUART_AG6XX) += hci_ag6xx.o hci_uart-$(CONFIG_BT_HCIUART_MRVL) += hci_mrvl.o hci_uart-objs := $(hci_uart-y) + +obj-$(CONFIG_BT_HCIBTUSB_RTLBTUSB) += rtk_btusb.o +rtk_btusb-objs := rtk_bt.o rtk_misc.o rtk_coex.o diff --git a/drivers/bluetooth/rtk_bt.c b/drivers/bluetooth/rtk_bt.c new file mode 100644 index 0000000000000..60ec72a4ae24e --- /dev/null +++ b/drivers/bluetooth/rtk_bt.c @@ -0,0 +1,1899 @@ +/* + * + * Realtek Bluetooth USB driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtk_bt.h" +#include "rtk_misc.h" + +#define VERSION "3.1.6d45ddf.20220519-142432" + +#ifdef BTCOEX +#include "rtk_coex.h" +#endif + +#ifdef RTKBT_SWITCH_PATCH +#include +#include +DEFINE_SEMAPHORE(switch_sem); +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 7, 1) +static bool reset = 0; +#endif + +static struct usb_driver btusb_driver; +static struct usb_device_id btusb_table[] = { + { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0bda, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x13d3, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0489, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x1358, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x04ca, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x2ff8, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0b05, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0930, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x10ec, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x04c5, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0cb5, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0cb8, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { } +}; + +static void rtk_free(struct btusb_data *data) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 1) + kfree(data); +#endif + return; +} + +static struct btusb_data *rtk_alloc(struct usb_interface *intf) +{ + struct btusb_data *data; +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 1) + data = kzalloc(sizeof(*data), GFP_KERNEL); +#else + data = devm_kzalloc(&intf->dev, sizeof(*data), GFP_KERNEL); +#endif + return data; +} + +MODULE_DEVICE_TABLE(usb, btusb_table); + +static int inc_tx(struct btusb_data *data) +{ + unsigned long flags; + int rv; + + spin_lock_irqsave(&data->txlock, flags); + rv = test_bit(BTUSB_SUSPENDING, &data->flags); + if (!rv) + data->tx_in_flight++; + spin_unlock_irqrestore(&data->txlock, flags); + + return rv; +} + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) +static inline void btusb_free_frags(struct btusb_data *data) +{ + unsigned long flags; + + spin_lock_irqsave(&data->rxlock, flags); + + kfree_skb(data->evt_skb); + data->evt_skb = NULL; + + kfree_skb(data->acl_skb); + data->acl_skb = NULL; + + kfree_skb(data->sco_skb); + data->sco_skb = NULL; + + spin_unlock_irqrestore(&data->rxlock, flags); +} + +static int btusb_recv_intr(struct btusb_data *data, void *buffer, int count) +{ + struct sk_buff *skb; + int err = 0; + + spin_lock(&data->rxlock); + skb = data->evt_skb; + + while (count) { + int len; + + if (!skb) { + skb = bt_skb_alloc(HCI_MAX_EVENT_SIZE, GFP_ATOMIC); + if (!skb) { + err = -ENOMEM; + break; + } + + bt_cb(skb)->pkt_type = HCI_EVENT_PKT; + bt_cb(skb)->expect = HCI_EVENT_HDR_SIZE; + } + + len = min_t(uint, bt_cb(skb)->expect, count); + memcpy(skb_put(skb, len), buffer, len); + + count -= len; + buffer += len; + bt_cb(skb)->expect -= len; + + if (skb->len == HCI_EVENT_HDR_SIZE) { + /* Complete event header */ + bt_cb(skb)->expect = hci_event_hdr(skb)->plen; + + if (skb_tailroom(skb) < bt_cb(skb)->expect) { + kfree_skb(skb); + skb = NULL; + + err = -EILSEQ; + break; + } + } + + if (bt_cb(skb)->expect == 0) { + /* Complete frame */ + hci_recv_frame(data->hdev, skb); + skb = NULL; + } + } + + data->evt_skb = skb; + spin_unlock(&data->rxlock); + + return err; +} + +static int btusb_recv_bulk(struct btusb_data *data, void *buffer, int count) +{ + struct sk_buff *skb; + int err = 0; + + spin_lock(&data->rxlock); + skb = data->acl_skb; + + while (count) { + int len; + + if (!skb) { + skb = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC); + if (!skb) { + err = -ENOMEM; + break; + } + + bt_cb(skb)->pkt_type = HCI_ACLDATA_PKT; + bt_cb(skb)->expect = HCI_ACL_HDR_SIZE; + } + + len = min_t(uint, bt_cb(skb)->expect, count); + memcpy(skb_put(skb, len), buffer, len); + + count -= len; + buffer += len; + bt_cb(skb)->expect -= len; + + if (skb->len == HCI_ACL_HDR_SIZE) { + __le16 dlen = hci_acl_hdr(skb)->dlen; + + /* Complete ACL header */ + bt_cb(skb)->expect = __le16_to_cpu(dlen); + + if (skb_tailroom(skb) < bt_cb(skb)->expect) { + kfree_skb(skb); + skb = NULL; + + err = -EILSEQ; + break; + } + } + + if (bt_cb(skb)->expect == 0) { + /* Complete frame */ + hci_recv_frame(data->hdev, skb); + skb = NULL; + } + } + + data->acl_skb = skb; + spin_unlock(&data->rxlock); + + return err; +} + +static int btusb_recv_isoc(struct btusb_data *data, void *buffer, int count) +{ + struct sk_buff *skb; + int err = 0; + + spin_lock(&data->rxlock); + skb = data->sco_skb; + + while (count) { + int len; + + if (!skb) { + skb = bt_skb_alloc(HCI_MAX_SCO_SIZE, GFP_ATOMIC); + if (!skb) { + err = -ENOMEM; + break; + } + + bt_cb(skb)->pkt_type = HCI_SCODATA_PKT; + bt_cb(skb)->expect = HCI_SCO_HDR_SIZE; + } + + len = min_t(uint, bt_cb(skb)->expect, count); + memcpy(skb_put(skb, len), buffer, len); + + count -= len; + buffer += len; + bt_cb(skb)->expect -= len; + + if (skb->len == HCI_SCO_HDR_SIZE) { + /* Complete SCO header */ + bt_cb(skb)->expect = hci_sco_hdr(skb)->dlen; + + if (skb_tailroom(skb) < bt_cb(skb)->expect) { + kfree_skb(skb); + skb = NULL; + + err = -EILSEQ; + break; + } + } + + if (bt_cb(skb)->expect == 0) { + /* Complete frame */ + hci_recv_frame(data->hdev, skb); + skb = NULL; + } + } + + data->sco_skb = skb; + spin_unlock(&data->rxlock); + + return err; +} +#endif + +static void btusb_intr_complete(struct urb *urb) +{ + struct hci_dev *hdev = urb->context; + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + + //RTKBT_DBG("%s: urb %p status %d count %d ", __func__, + //urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + return; + + if (urb->status == 0) { + hdev->stat.byte_rx += urb->actual_length; + +#ifdef BTCOEX + rtk_btcoex_parse_event(urb->transfer_buffer, + urb->actual_length); +#endif +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 18, 0) + if (hci_recv_fragment(hdev, HCI_EVENT_PKT, + urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s: Corrupted event packet", __func__); + hdev->stat.err_rx++; + } +#else + if (btusb_recv_intr(data, urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s corrupted event packet", hdev->name); + hdev->stat.err_rx++; + } +#endif + } + /* Avoid suspend failed when usb_kill_urb */ + else if (urb->status == -ENOENT) { + return; + } + + if (!test_bit(BTUSB_INTR_RUNNING, &data->flags)) + return; + + usb_mark_last_busy(data->udev); + usb_anchor_urb(urb, &data->intr_anchor); + + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + /* -EPERM: urb is being killed; + * -ENODEV: device got disconnected */ + if (err != -EPERM && err != -ENODEV) + RTKBT_ERR("%s: Failed to re-submit urb %p, err %d", + __func__, urb, err); + usb_unanchor_urb(urb); + } +} + +static int btusb_submit_intr_urb(struct hci_dev *hdev, gfp_t mem_flags) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct urb *urb; + unsigned char *buf; + unsigned int pipe; + int err, size; + + //RTKBT_DBG("%s", hdev->name); + + if (!data->intr_ep) + return -ENODEV; + + urb = usb_alloc_urb(0, mem_flags); + if (!urb) + return -ENOMEM; + + size = le16_to_cpu(data->intr_ep->wMaxPacketSize); + + buf = kmalloc(size, mem_flags); + if (!buf) { + usb_free_urb(urb); + return -ENOMEM; + } + + pipe = usb_rcvintpipe(data->udev, data->intr_ep->bEndpointAddress); + + usb_fill_int_urb(urb, data->udev, pipe, buf, size, + btusb_intr_complete, hdev, data->intr_ep->bInterval); + + urb->transfer_flags |= URB_FREE_BUFFER; + + usb_anchor_urb(urb, &data->intr_anchor); + + err = usb_submit_urb(urb, mem_flags); + if (err < 0) { + RTKBT_ERR + ("btusb_submit_intr_urb %s urb %p submission failed (%d)", + hdev->name, urb, -err); + usb_unanchor_urb(urb); + } + + usb_free_urb(urb); + + return err; +} + +static void btusb_bulk_complete(struct urb *urb) +{ + struct hci_dev *hdev = urb->context; + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + + //RTKBT_DBG("%s: urb %p status %d count %d", + //__func__, urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + return; + +#ifdef BTCOEX + if (urb->status == 0) + rtk_btcoex_parse_l2cap_data_rx(urb->transfer_buffer, + urb->actual_length); +#endif + + if (urb->status == 0) { + hdev->stat.byte_rx += urb->actual_length; + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 18, 0) + if (hci_recv_fragment(hdev, HCI_ACLDATA_PKT, + urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s: Corrupted ACL packet", __func__); + hdev->stat.err_rx++; + } +#else + if (data->recv_bulk(data, urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s corrupted ACL packet", hdev->name); + hdev->stat.err_rx++; + } +#endif + } + /* Avoid suspend failed when usb_kill_urb */ + else if (urb->status == -ENOENT) { + return; + } + + if (!test_bit(BTUSB_BULK_RUNNING, &data->flags)) + return; + + usb_anchor_urb(urb, &data->bulk_anchor); + usb_mark_last_busy(data->udev); + + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + /* -EPERM: urb is being killed; + * -ENODEV: device got disconnected */ + if (err != -EPERM && err != -ENODEV) + RTKBT_ERR + ("btusb_bulk_complete %s urb %p failed to resubmit (%d)", + hdev->name, urb, -err); + usb_unanchor_urb(urb); + } +} + +static int btusb_submit_bulk_urb(struct hci_dev *hdev, gfp_t mem_flags) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct urb *urb; + unsigned char *buf; + unsigned int pipe; + int err, size = HCI_MAX_FRAME_SIZE; + + //RTKBT_DBG("%s: hdev name %s", __func__, hdev->name); + + if (!data->bulk_rx_ep) + return -ENODEV; + + urb = usb_alloc_urb(0, mem_flags); + if (!urb) + return -ENOMEM; + + buf = kmalloc(size, mem_flags); + if (!buf) { + usb_free_urb(urb); + return -ENOMEM; + } + + pipe = usb_rcvbulkpipe(data->udev, data->bulk_rx_ep->bEndpointAddress); + + usb_fill_bulk_urb(urb, data->udev, pipe, + buf, size, btusb_bulk_complete, hdev); + + urb->transfer_flags |= URB_FREE_BUFFER; + + usb_mark_last_busy(data->udev); + usb_anchor_urb(urb, &data->bulk_anchor); + + err = usb_submit_urb(urb, mem_flags); + if (err < 0) { + RTKBT_ERR("%s: Failed to submit urb %p, err %d", __func__, urb, + err); + usb_unanchor_urb(urb); + } + + usb_free_urb(urb); + + return err; +} + +static void btusb_isoc_complete(struct urb *urb) +{ + struct hci_dev *hdev = urb->context; + struct btusb_data *data = GET_DRV_DATA(hdev); + int i, err; + + /* + RTKBT_DBG("%s urb %p status %d count %d", hdev->name, + urb, urb->status, urb->actual_length); + */ + if (!test_bit(HCI_RUNNING, &hdev->flags)) + return; + + if (urb->status == 0) { + for (i = 0; i < urb->number_of_packets; i++) { + unsigned int offset = urb->iso_frame_desc[i].offset; + unsigned int length = + urb->iso_frame_desc[i].actual_length; + + if (urb->iso_frame_desc[i].status) + continue; + + hdev->stat.byte_rx += length; + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 18, 0) + if (hci_recv_fragment(hdev, HCI_SCODATA_PKT, + urb->transfer_buffer + offset, + length) < 0) { + RTKBT_ERR("%s: Corrupted SCO packet", __func__); + hdev->stat.err_rx++; + } +#else + if (btusb_recv_isoc(data, urb->transfer_buffer + offset, + length) < 0) { + RTKBT_ERR("%s corrupted SCO packet", + hdev->name); + hdev->stat.err_rx++; + } +#endif + } + } + /* Avoid suspend failed when usb_kill_urb */ + else if (urb->status == -ENOENT) { + return; + } + + if (!test_bit(BTUSB_ISOC_RUNNING, &data->flags)) + return; + + usb_anchor_urb(urb, &data->isoc_anchor); + i = 0; +retry: + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + /* -EPERM: urb is being killed; + * -ENODEV: device got disconnected */ + if (err != -EPERM && err != -ENODEV) + RTKBT_ERR + ("%s: Failed to re-sumbit urb %p, retry %d, err %d", + __func__, urb, i, err); + if (i < 10) { + i++; + mdelay(1); + goto retry; + } + + usb_unanchor_urb(urb); + } +} + +static inline void __fill_isoc_descriptor(struct urb *urb, int len, int mtu) +{ + int i, offset = 0; + + //RTKBT_DBG("len %d mtu %d", len, mtu); + + for (i = 0; i < BTUSB_MAX_ISOC_FRAMES && len >= mtu; + i++, offset += mtu, len -= mtu) { + urb->iso_frame_desc[i].offset = offset; + urb->iso_frame_desc[i].length = mtu; + } + + if (len && i < BTUSB_MAX_ISOC_FRAMES) { + urb->iso_frame_desc[i].offset = offset; + urb->iso_frame_desc[i].length = len; + i++; + } + + urb->number_of_packets = i; +} + +static int btusb_submit_isoc_urb(struct hci_dev *hdev, gfp_t mem_flags) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct urb *urb; + unsigned char *buf; + unsigned int pipe; + int err, size; + + //RTKBT_DBG("%s", hdev->name); + + if (!data->isoc_rx_ep) + return -ENODEV; + + urb = usb_alloc_urb(BTUSB_MAX_ISOC_FRAMES, mem_flags); + if (!urb) + return -ENOMEM; + + size = le16_to_cpu(data->isoc_rx_ep->wMaxPacketSize) * + BTUSB_MAX_ISOC_FRAMES; + + buf = kmalloc(size, mem_flags); + if (!buf) { + usb_free_urb(urb); + return -ENOMEM; + } + + pipe = usb_rcvisocpipe(data->udev, data->isoc_rx_ep->bEndpointAddress); + + urb->dev = data->udev; + urb->pipe = pipe; + urb->context = hdev; + urb->complete = btusb_isoc_complete; + urb->interval = data->isoc_rx_ep->bInterval; + + urb->transfer_flags = URB_FREE_BUFFER | URB_ISO_ASAP; + urb->transfer_buffer = buf; + urb->transfer_buffer_length = size; + + __fill_isoc_descriptor(urb, size, + le16_to_cpu(data->isoc_rx_ep->wMaxPacketSize)); + + usb_anchor_urb(urb, &data->isoc_anchor); + + err = usb_submit_urb(urb, mem_flags); + if (err < 0) { + RTKBT_ERR("%s %s urb %p submission failed (%d)", + __func__, hdev->name, urb, err); + usb_unanchor_urb(urb); + } + + usb_free_urb(urb); + + return err; +} + +static void btusb_tx_complete(struct urb *urb) +{ + struct sk_buff *skb = urb->context; + struct hci_dev *hdev = (struct hci_dev *)skb->dev; + struct btusb_data *data = GET_DRV_DATA(hdev); + +// RTKBT_DBG("btusb_tx_complete %s urb %p status %d count %d", hdev->name, +// urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + goto done; + + if (!urb->status) + hdev->stat.byte_tx += urb->transfer_buffer_length; + else + hdev->stat.err_tx++; + +done: + spin_lock(&data->txlock); + data->tx_in_flight--; + spin_unlock(&data->txlock); + + kfree(urb->setup_packet); + + kfree_skb(skb); +} + +static void btusb_isoc_tx_complete(struct urb *urb) +{ + struct sk_buff *skb = urb->context; + struct hci_dev *hdev = (struct hci_dev *)skb->dev; + + RTKBT_DBG("%s: urb %p status %d count %d",__func__, + urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + goto done; + + if (!urb->status) + hdev->stat.byte_tx += urb->transfer_buffer_length; + else + hdev->stat.err_tx++; + +done: + kfree(urb->setup_packet); + + kfree_skb(skb); +} + +static int btusb_open(struct hci_dev *hdev) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + + err = usb_autopm_get_interface(data->intf); + if (err < 0) + return err; + + data->intf->needs_remote_wakeup = 1; + RTKBT_DBG("%s start", __func__); + + /*******************************/ + if (0 == atomic_read(&hdev->promisc)) { + RTKBT_ERR("btusb_open hdev->promisc ==0"); + //err = -1; + //goto failed; + } + + err = download_patch(data->intf); + if (err < 0) + goto failed; + /*******************************/ + + RTKBT_INFO("%s set HCI_RUNNING", __func__); + if (test_and_set_bit(HCI_RUNNING, &hdev->flags)) + goto done; + + if (test_and_set_bit(BTUSB_INTR_RUNNING, &data->flags)) + goto done; + + err = btusb_submit_intr_urb(hdev, GFP_KERNEL); + if (err < 0) + goto failed; + + err = btusb_submit_bulk_urb(hdev, GFP_KERNEL); + if (err < 0) { + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->intr_anchor); + goto failed; + } + + set_bit(BTUSB_BULK_RUNNING, &data->flags); + btusb_submit_bulk_urb(hdev, GFP_KERNEL); + +done: + usb_autopm_put_interface(data->intf); + +#ifdef BTCOEX + rtk_btcoex_open(hdev); +#endif + RTKBT_DBG("%s end", __FUNCTION__); + + return 0; + +failed: + clear_bit(BTUSB_INTR_RUNNING, &data->flags); + clear_bit(HCI_RUNNING, &hdev->flags); + usb_autopm_put_interface(data->intf); + RTKBT_ERR("%s failed", __FUNCTION__); + return err; +} + +static void btusb_stop_traffic(struct btusb_data *data) +{ + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->intr_anchor); + usb_kill_anchored_urbs(&data->bulk_anchor); + usb_kill_anchored_urbs(&data->isoc_anchor); +} + +static int btusb_close(struct hci_dev *hdev) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 1, 0) + int i; +#endif + + /* When in kernel 4.4.0 and greater, the HCI_RUNNING bit is + * cleared in hci_dev_do_close(). */ +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 4, 0) + if (!test_and_clear_bit(HCI_RUNNING, &hdev->flags)) + return 0; +#else + if (test_bit(HCI_RUNNING, &hdev->flags)) { + RTKBT_ERR("HCI_RUNNING is not cleared before."); + return -1; + } +#endif + + RTKBT_DBG("btusb_close"); +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 1, 0) + /*******************************/ + for (i = 0; i < NUM_REASSEMBLY; i++) { + if (hdev->reassembly[i]) { + kfree_skb(hdev->reassembly[i]); + hdev->reassembly[i] = NULL; + RTKBT_DBG("%s free ressembly i=%d", __FUNCTION__, i); + } + } + /*******************************/ +#endif + cancel_work_sync(&data->work); + cancel_work_sync(&data->waker); + + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + clear_bit(BTUSB_BULK_RUNNING, &data->flags); + clear_bit(BTUSB_INTR_RUNNING, &data->flags); + + btusb_stop_traffic(data); +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + btusb_free_frags(data); +#endif + + err = usb_autopm_get_interface(data->intf); + if (err < 0) + goto failed; + + data->intf->needs_remote_wakeup = 0; + usb_autopm_put_interface(data->intf); + +#ifdef BTCOEX + rtk_btcoex_close(); +#endif + +failed: + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_scuttle_anchored_urbs(&data->deferred); + +#ifdef RTKBT_SWITCH_PATCH + down(&switch_sem); + if (data->context) { + struct api_context *ctx = data->context; + + if (ctx->flags & RTLBT_CLOSE) { + ctx->flags &= ~RTLBT_CLOSE; + ctx->status = 0; + complete(&ctx->done); + } + } + up(&switch_sem); +#endif + + return 0; +} + +static int btusb_flush(struct hci_dev *hdev) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + + RTKBT_DBG("%s add delay ", __FUNCTION__); + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->tx_anchor); +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + btusb_free_frags(data); +#endif + + return 0; +} + +const char pkt_ind[][8] = { + [HCI_COMMAND_PKT] = "cmd", + [HCI_ACLDATA_PKT] = "acl", + [HCI_SCODATA_PKT] = "sco", +}; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) +int btusb_send_frame(struct hci_dev *hdev, struct sk_buff *skb) +{ +#else +int btusb_send_frame(struct sk_buff *skb) +{ + struct hci_dev *hdev = (struct hci_dev *)skb->dev; +#endif + + struct btusb_data *data = GET_DRV_DATA(hdev); + struct usb_ctrlrequest *dr; + struct urb *urb; + unsigned int pipe; + int err; + + //RTKBT_DBG("%s", hdev->name); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) { + /* If the parameter is wrong, the hdev isn't the correct + * one. Then no HCI commands can be sent. + * This issue is related to the wrong HCI_VERSION_CODE set */ + RTKBT_ERR("HCI is not running"); + return -EBUSY; + } + + /* Before kernel/hci version 3.13.0, the skb->dev is set before + * entering btusb_send_frame(). So there is no need to set it here. + * + * The skb->dev will be used in the callbacks when urb transfer + * completes. See btusb_tx_complete() and btusb_isoc_tx_complete() */ +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) + skb->dev = (void *)hdev; +#endif + + switch (bt_cb(skb)->pkt_type) { + case HCI_COMMAND_PKT: + print_command(skb); + +#ifdef BTCOEX + rtk_btcoex_parse_cmd(skb->data, skb->len); +#endif + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) + return -ENOMEM; + + dr = kmalloc(sizeof(*dr), GFP_ATOMIC); + if (!dr) { + usb_free_urb(urb); + return -ENOMEM; + } + + dr->bRequestType = data->cmdreq_type; + dr->bRequest = 0; + dr->wIndex = 0; + dr->wValue = 0; + dr->wLength = __cpu_to_le16(skb->len); + + pipe = usb_sndctrlpipe(data->udev, 0x00); + + usb_fill_control_urb(urb, data->udev, pipe, (void *)dr, + skb->data, skb->len, btusb_tx_complete, + skb); + + hdev->stat.cmd_tx++; + break; + + case HCI_ACLDATA_PKT: + print_acl(skb, 1); +#ifdef BTCOEX + rtk_btcoex_parse_l2cap_data_tx(skb->data, skb->len); +#endif + if (!data->bulk_tx_ep) + return -ENODEV; + + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) + return -ENOMEM; + + pipe = usb_sndbulkpipe(data->udev, + data->bulk_tx_ep->bEndpointAddress); + + usb_fill_bulk_urb(urb, data->udev, pipe, + skb->data, skb->len, btusb_tx_complete, skb); + + hdev->stat.acl_tx++; + break; + + case HCI_SCODATA_PKT: + if (!data->isoc_tx_ep || SCO_NUM < 1) + return -ENODEV; + + urb = usb_alloc_urb(BTUSB_MAX_ISOC_FRAMES, GFP_ATOMIC); + if (!urb) + return -ENOMEM; + + pipe = usb_sndisocpipe(data->udev, + data->isoc_tx_ep->bEndpointAddress); + + usb_fill_int_urb(urb, data->udev, pipe, + skb->data, skb->len, btusb_isoc_tx_complete, + skb, data->isoc_tx_ep->bInterval); + + urb->transfer_flags = URB_ISO_ASAP; + + __fill_isoc_descriptor(urb, skb->len, + le16_to_cpu(data->isoc_tx_ep-> + wMaxPacketSize)); + + hdev->stat.sco_tx++; + goto skip_waking; + + default: + return -EILSEQ; + } + + err = inc_tx(data); + if (err) { + usb_anchor_urb(urb, &data->deferred); + schedule_work(&data->waker); + err = 0; + goto done; + } + +skip_waking: + usb_anchor_urb(urb, &data->tx_anchor); + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + RTKBT_ERR("%s %s urb %p submission for %s failed, err %d", + __func__, hdev->name, urb, + pkt_ind[bt_cb(skb)->pkt_type], err); + kfree(urb->setup_packet); + usb_unanchor_urb(urb); + } else { + usb_mark_last_busy(data->udev); + } + usb_free_urb(urb); + +done: + return err; +} + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 4, 0) +static void btusb_destruct(struct hci_dev *hdev) +{ + RTKBT_DBG("btusb_destruct %s", hdev->name); + hci_free_dev(hdev); +} +#endif + +static void btusb_notify(struct hci_dev *hdev, unsigned int evt) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + + RTKBT_DBG("%s: %s evt %d", __func__, hdev->name, evt); + + if (SCO_NUM != data->sco_num) { + data->sco_num = SCO_NUM; + RTKBT_DBG("%s: Update sco num %d", __func__, data->sco_num); +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) + data->air_mode = evt; +#endif + schedule_work(&data->work); + } +} + +static inline int __set_isoc_interface(struct hci_dev *hdev, int altsetting) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct usb_interface *intf = data->isoc; + struct usb_endpoint_descriptor *ep_desc; + int i, err; + + if (!data->isoc) + return -ENODEV; + + RTKBT_INFO("set isoc interface: alt %d", altsetting); + + err = usb_set_interface(data->udev, 1, altsetting); + if (err < 0) { + RTKBT_ERR("%s setting interface failed (%d)", hdev->name, -err); + return err; + } + + data->isoc_altsetting = altsetting; + + data->isoc_tx_ep = NULL; + data->isoc_rx_ep = NULL; + + for (i = 0; i < intf->cur_altsetting->desc.bNumEndpoints; i++) { + ep_desc = &intf->cur_altsetting->endpoint[i].desc; + + if (!data->isoc_tx_ep && usb_endpoint_is_isoc_out(ep_desc)) { + data->isoc_tx_ep = ep_desc; + continue; + } + + if (!data->isoc_rx_ep && usb_endpoint_is_isoc_in(ep_desc)) { + data->isoc_rx_ep = ep_desc; + continue; + } + } + + if (!data->isoc_tx_ep || !data->isoc_rx_ep) { + RTKBT_ERR("%s invalid SCO descriptors", hdev->name); + return -ENODEV; + } + + return 0; +} + +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) +static int btusb_switch_alt_setting(struct hci_dev *hdev, int new_alts) +{ + struct btusb_data *data = hci_get_drvdata(hdev); + int err; + + if (data->isoc_altsetting != new_alts) { + unsigned long flags; + + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + usb_kill_anchored_urbs(&data->isoc_anchor); + + /* When isochronous alternate setting needs to be + * changed, because SCO connection has been added + * or removed, a packet fragment may be left in the + * reassembling state. This could lead to wrongly + * assembled fragments. + * + * Clear outstanding fragment when selecting a new + * alternate setting. + */ + spin_lock_irqsave(&data->rxlock, flags); + kfree_skb(data->sco_skb); + data->sco_skb = NULL; + spin_unlock_irqrestore(&data->rxlock, flags); + + err = __set_isoc_interface(hdev, new_alts); + if (err < 0) + return err; + } + + if (!test_and_set_bit(BTUSB_ISOC_RUNNING, &data->flags)) { + if (btusb_submit_isoc_urb(hdev, GFP_KERNEL) < 0) + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + else + btusb_submit_isoc_urb(hdev, GFP_KERNEL); + } + + return 0; +} + +static struct usb_host_interface *btusb_find_altsetting(struct btusb_data *data, + int alt) +{ + struct usb_interface *intf = data->isoc; + int i; + + BT_DBG("Looking for Alt no :%d", alt); + + for (i = 0; i < intf->num_altsetting; i++) { + if (intf->altsetting[i].desc.bAlternateSetting == alt) + return &intf->altsetting[i]; + } + + return NULL; +} +#endif + +static void btusb_work(struct work_struct *work) +{ + struct btusb_data *data = container_of(work, struct btusb_data, work); + struct hci_dev *hdev = data->hdev; + int err; + int new_alts = 0; + + RTKBT_DBG("%s: sco num %d", __func__, data->sco_num); + if (data->sco_num > 0) { + if (!test_bit(BTUSB_DID_ISO_RESUME, &data->flags)) { + err = + usb_autopm_get_interface(data->isoc ? data-> + isoc : data->intf); + if (err < 0) { + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + mdelay(URB_CANCELING_DELAY_MS); + usb_kill_anchored_urbs(&data->isoc_anchor); + return; + } + + set_bit(BTUSB_DID_ISO_RESUME, &data->flags); + } +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) + if (data->air_mode == HCI_NOTIFY_ENABLE_SCO_CVSD) { + if (hdev->voice_setting & 0x0020) { + static const int alts[3] = { 2, 4, 5 }; + new_alts = alts[data->sco_num - 1]; + } else { + new_alts = data->sco_num; + } + } else if (data->air_mode == HCI_NOTIFY_ENABLE_SCO_TRANSP) { + new_alts = btusb_find_altsetting(data, 6) ? 6 : 1; + } + + if (btusb_switch_alt_setting(hdev, new_alts) < 0) + RTKBT_ERR("set USB alt:(%d) failed!", new_alts); +#else +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 5, 0) + if (hdev->voice_setting & 0x0020) { + static const int alts[3] = { 2, 4, 5 }; + new_alts = alts[data->sco_num - 1]; + } else { + new_alts = data->sco_num; + } + if (data->isoc_altsetting != new_alts) { +#else + if (data->isoc_altsetting != 2) { + new_alts = 2; +#endif + + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + mdelay(URB_CANCELING_DELAY_MS); + usb_kill_anchored_urbs(&data->isoc_anchor); + + if (__set_isoc_interface(hdev, new_alts) < 0) + return; + } + + if (!test_and_set_bit(BTUSB_ISOC_RUNNING, &data->flags)) { + RTKBT_INFO("submit SCO RX urb."); + if (btusb_submit_isoc_urb(hdev, GFP_KERNEL) < 0) + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + else + btusb_submit_isoc_urb(hdev, GFP_KERNEL); + } +#endif + } else { + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + mdelay(URB_CANCELING_DELAY_MS); + usb_kill_anchored_urbs(&data->isoc_anchor); + + __set_isoc_interface(hdev, 0); + if (test_and_clear_bit(BTUSB_DID_ISO_RESUME, &data->flags)) + usb_autopm_put_interface(data->isoc ? data-> + isoc : data->intf); + } +} + +static void btusb_waker(struct work_struct *work) +{ + struct btusb_data *data = container_of(work, struct btusb_data, waker); + int err; + + err = usb_autopm_get_interface(data->intf); + RTKBT_DBG("%s start", __FUNCTION__); + if (err < 0) + return; + + usb_autopm_put_interface(data->intf); + RTKBT_DBG("%s end", __FUNCTION__); +} + +#ifdef RTKBT_TV_POWERON_WHITELIST +static int rtkbt_lookup_le_device_poweron_whitelist(struct hci_dev *hdev, + struct usb_device *udev) +{ + struct hci_conn_params *p; + u8 *cmd; + int result = 0; + + hci_dev_lock(hdev); + list_for_each_entry(p, &hdev->le_conn_params, list) { +#if 0 // for debug message + RTKBT_DBG("%s(): auto_connect = %d", __FUNCTION__, p->auto_connect); + RTKBT_DBG("%s(): addr_type = 0x%02x", __FUNCTION__, p->addr_type); + RTKBT_DBG("%s(): addr=%02x:%02x:%02x:%02x:%02x:%02x", __FUNCTION__, + p->addr.b[5], p->addr.b[4], p->addr.b[3], + p->addr.b[2], p->addr.b[1], p->addr.b[0]); +#endif + if ( p->auto_connect == HCI_AUTO_CONN_ALWAYS && + p->addr_type == ADDR_LE_DEV_PUBLIC ) { + + RTKBT_DBG("%s(): Set RTKBT LE Power-on Whitelist for " + "%02x:%02x:%02x:%02x:%02x:%02x", __FUNCTION__, + p->addr.b[5], p->addr.b[4], p->addr.b[3], + p->addr.b[2], p->addr.b[1], p->addr.b[0]); + + cmd = kzalloc(16, GFP_ATOMIC); + if (!cmd) { + RTKBT_ERR("Can't allocate memory for cmd"); + return -ENOMEM; + } + cmd[0] = 0x7b; + cmd[1] = 0xfc; + cmd[2] = 0x07; + cmd[3] = 0x00; + cmd[4] = p->addr.b[0]; + cmd[5] = p->addr.b[1]; + cmd[6] = p->addr.b[2]; + cmd[7] = p->addr.b[3]; + cmd[8] = p->addr.b[4]; + cmd[9] = p->addr.b[5]; + + result = __rtk_send_hci_cmd(udev, cmd, 10); + kfree(cmd); + } + } + hci_dev_unlock(hdev); + + return result; +} +#endif + +int rtkbt_pm_notify(struct notifier_block *notifier, + ulong pm_event, void *unused) +{ + struct btusb_data *data; + struct usb_device *udev; + struct usb_interface *intf; + struct hci_dev *hdev; + /* int err; */ +#if defined RTKBT_SWITCH_PATCH || defined RTKBT_TV_POWERON_WHITELIST + int result = 0; +#endif +#ifdef RTKBT_SWITCH_PATCH + u8 *cmd; + static u8 hci_state = 0; + struct api_context ctx; +#endif + + data = container_of(notifier, struct btusb_data, pm_notifier); + udev = data->udev; + intf = data->intf; + hdev = data->hdev; + + RTKBT_DBG("%s: pm_event %ld", __func__, pm_event); + switch (pm_event) { + case PM_SUSPEND_PREPARE: + case PM_HIBERNATION_PREPARE: + /* No need to load firmware because the download firmware + * process is deprecated in resume. + * We use rebind after resume instead */ + /* err = usb_autopm_get_interface(data->intf); + * if (err < 0) + * return err; + * patch_entry->fw_len = + * load_firmware(dev_entry, &patch_entry->fw_cache); + * usb_autopm_put_interface(data->intf); + * if (patch_entry->fw_len <= 0) { + * RTKBT_DBG("rtkbt_pm_notify return NOTIFY_BAD"); + * return NOTIFY_BAD; + * } */ + + RTKBT_DBG("%s: suspend prepare", __func__); + + if (!device_may_wakeup(&udev->dev)) { +#ifdef CONFIG_NEEDS_BINDING + intf->needs_binding = 1; + RTKBT_DBG("Remote wakeup not support, set " + "intf->needs_binding = 1"); +#else + RTKBT_DBG("Remote wakeup not support, no needs binding"); +#endif + } + +#ifdef RTKBT_SWITCH_PATCH + if (test_bit(HCI_UP, &hdev->flags)) { + unsigned long expire; + + init_completion(&ctx.done); + hci_state = 1; + + down(&switch_sem); + data->context = &ctx; + ctx.flags = RTLBT_CLOSE; + queue_work(hdev->req_workqueue, &hdev->power_off.work); + up(&switch_sem); + + expire = msecs_to_jiffies(1000); + if (!wait_for_completion_timeout(&ctx.done, expire)) + RTKBT_ERR("hdev close timeout"); + + down(&switch_sem); + data->context = NULL; + up(&switch_sem); + } + + cmd = kzalloc(16, GFP_ATOMIC); + if (!cmd) { + RTKBT_ERR("Can't allocate memory for cmd"); + return -ENOMEM; + } + + /* Clear patch */ + cmd[0] = 0x66; + cmd[1] = 0xfc; + cmd[2] = 0x00; + + result = __rtk_send_hci_cmd(udev, cmd, 3); + kfree(cmd); + msleep(100); /* From FW colleague's recommendation */ + result = download_lps_patch(intf); + + /* Tell the controller to wake up host if received special + * advertising packet + */ + set_scan(intf); + + /* Send special vendor commands */ +#endif + +#ifdef RTKBT_TV_POWERON_WHITELIST + result = rtkbt_lookup_le_device_poweron_whitelist(hdev, udev); + if (result < 0) { + RTKBT_ERR("rtkbt_lookup_le_device_poweron_whitelist error: %d", result); + } +#endif + break; + + case PM_POST_SUSPEND: + case PM_POST_HIBERNATION: + case PM_POST_RESTORE: + /* if (patch_entry->fw_len > 0) { + * kfree(patch_entry->fw_cache); + * patch_entry->fw_cache = NULL; + * patch_entry->fw_len = 0; + * } */ + +#ifdef RTKBT_SWITCH_PATCH + cmd = kzalloc(16, GFP_ATOMIC); + if (!cmd) { + RTKBT_ERR("Can't allocate memory for cmd"); + return -ENOMEM; + } + + /* Clear patch */ + cmd[0] = 0x66; + cmd[1] = 0xfc; + cmd[2] = 0x00; + + result = __rtk_send_hci_cmd(udev, cmd, 3); + kfree(cmd); + msleep(100); /* From FW colleague's recommendation */ + result = download_patch(intf); + if (hci_state) { + hci_state = 0; + queue_work(hdev->req_workqueue, &hdev->power_on); + } +#endif + +#ifdef BTUSB_RPM + RTKBT_DBG("%s: Re-enable autosuspend", __func__); + /* pm_runtime_use_autosuspend(&udev->dev); + * pm_runtime_set_autosuspend_delay(&udev->dev, 2000); + * pm_runtime_set_active(&udev->dev); + * pm_runtime_allow(&udev->dev); + * pm_runtime_mark_last_busy(&udev->dev); + * pm_runtime_autosuspend(&udev->dev); + * pm_runtime_put_autosuspend(&udev->dev); + * usb_disable_autosuspend(udev); */ + /* FIXME: usb_enable_autosuspend(udev) is useless here. + * Because it is always enabled after enabled in btusb_probe() + */ + usb_enable_autosuspend(udev); + pm_runtime_mark_last_busy(&udev->dev); +#endif + break; + + default: + break; + } + + return NOTIFY_DONE; +} + + +static int btusb_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + struct usb_endpoint_descriptor *ep_desc; + struct btusb_data *data; + struct hci_dev *hdev; + int i, err, flag1, flag2; + struct usb_device *udev; + udev = interface_to_usbdev(intf); + + RTKBT_DBG("btusb_probe intf->cur_altsetting->desc.bInterfaceNumber %d", + intf->cur_altsetting->desc.bInterfaceNumber); + + /* interface numbers are hardcoded in the spec */ + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return -ENODEV; + + /*******************************/ + flag1 = device_can_wakeup(&udev->dev); + flag2 = device_may_wakeup(&udev->dev); + RTKBT_DBG("btusb_probe can_wakeup %x, may wakeup %x", flag1, flag2); +#ifdef BTUSB_WAKEUP_HOST + device_wakeup_enable(&udev->dev); +#endif + //device_wakeup_enable(&udev->dev); + /*device_wakeup_disable(&udev->dev); + flag1=device_can_wakeup(&udev->dev); + flag2=device_may_wakeup(&udev->dev); + RTKBT_DBG("btusb_probe can_wakeup=%x flag2=%x",flag1,flag2); + */ + err = patch_add(intf); + if (err < 0) + return -1; + /*******************************/ + + data = rtk_alloc(intf); + if (!data) + return -ENOMEM; + + for (i = 0; i < intf->cur_altsetting->desc.bNumEndpoints; i++) { + ep_desc = &intf->cur_altsetting->endpoint[i].desc; + + if (!data->intr_ep && usb_endpoint_is_int_in(ep_desc)) { + data->intr_ep = ep_desc; + continue; + } + + if (!data->bulk_tx_ep && usb_endpoint_is_bulk_out(ep_desc)) { + data->bulk_tx_ep = ep_desc; + continue; + } + + if (!data->bulk_rx_ep && usb_endpoint_is_bulk_in(ep_desc)) { + data->bulk_rx_ep = ep_desc; + continue; + } + } + + if (!data->intr_ep || !data->bulk_tx_ep || !data->bulk_rx_ep) { + rtk_free(data); + return -ENODEV; + } + + data->cmdreq_type = USB_TYPE_CLASS; + + data->udev = interface_to_usbdev(intf); + data->intf = intf; + + spin_lock_init(&data->lock); + + INIT_WORK(&data->work, btusb_work); + INIT_WORK(&data->waker, btusb_waker); + spin_lock_init(&data->txlock); + + init_usb_anchor(&data->tx_anchor); + init_usb_anchor(&data->intr_anchor); + init_usb_anchor(&data->bulk_anchor); + init_usb_anchor(&data->isoc_anchor); + init_usb_anchor(&data->deferred); + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + spin_lock_init(&data->rxlock); + data->recv_bulk = btusb_recv_bulk; +#endif + + hdev = hci_alloc_dev(); + if (!hdev) { + rtk_free(data); + return -ENOMEM; + } + + HDEV_BUS = HCI_USB; + + data->hdev = hdev; + + SET_HCIDEV_DEV(hdev, &intf->dev); + + hdev->open = btusb_open; + hdev->close = btusb_close; + hdev->flush = btusb_flush; + hdev->send = btusb_send_frame; + hdev->notify = btusb_notify; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 4, 0) + hci_set_drvdata(hdev, data); +#else + hdev->driver_data = data; + hdev->destruct = btusb_destruct; + hdev->owner = THIS_MODULE; +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 7, 1) + if (!reset) + set_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks); + RTKBT_DBG("set_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks);"); +#endif + + /* Interface numbers are hardcoded in the specification */ + data->isoc = usb_ifnum_to_if(data->udev, 1); + + if (data->isoc) { + err = usb_driver_claim_interface(&btusb_driver, + data->isoc, data); + if (err < 0) { + hci_free_dev(hdev); + rtk_free(data); + return err; + } + } + +#if HCI_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) + set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks); +#endif + + err = hci_register_dev(hdev); + if (err < 0) { + hci_free_dev(hdev); + rtk_free(data); + return err; + } + + usb_set_intfdata(intf, data); + + /* Register PM notifier */ + data->pm_notifier.notifier_call = rtkbt_pm_notify; + register_pm_notifier(&data->pm_notifier); + +#ifdef BTCOEX + rtk_btcoex_probe(hdev); +#endif + + RTKBT_DBG("%s: done", __func__); + + return 0; +} + +static void btusb_disconnect(struct usb_interface *intf) +{ + struct btusb_data *data = usb_get_intfdata(intf); + struct hci_dev *hdev; + struct usb_device *udev; + udev = interface_to_usbdev(intf); + + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return; + + if (!data) + return; + + RTKBT_DBG("btusb_disconnect"); + + /* Un-register PM notifier */ + unregister_pm_notifier(&data->pm_notifier); + + /*******************************/ + patch_remove(intf); + /*******************************/ + + hdev = data->hdev; + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 4, 0) + __hci_dev_hold(hdev); +#endif + + usb_set_intfdata(data->intf, NULL); + + if (data->isoc) + usb_set_intfdata(data->isoc, NULL); + + hci_unregister_dev(hdev); + + if (intf == data->isoc) + usb_driver_release_interface(&btusb_driver, data->intf); + else if (data->isoc) + usb_driver_release_interface(&btusb_driver, data->isoc); + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 4, 0) + __hci_dev_put(hdev); +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + btusb_free_frags(data); +#endif + + hci_free_dev(hdev); + rtk_free(data); +} + +#ifdef CONFIG_PM +static int btusb_suspend(struct usb_interface *intf, pm_message_t message) +{ + struct btusb_data *data = usb_get_intfdata(intf); + + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return 0; + + /*******************************/ + RTKBT_DBG("btusb_suspend message.event 0x%x, data->suspend_count %d", + message.event, data->suspend_count); + if (!test_bit(HCI_RUNNING, &data->hdev->flags)) { + RTKBT_INFO("%s: hdev is not HCI_RUNNING", __func__); + /* set_scan(data->intf); */ + } + /*******************************/ + + if (data->suspend_count++) + return 0; + + spin_lock_irq(&data->txlock); + if (!((message.event & PM_EVENT_AUTO) && data->tx_in_flight)) { + set_bit(BTUSB_SUSPENDING, &data->flags); + spin_unlock_irq(&data->txlock); + RTKBT_INFO("%s: suspending...", __func__); + } else { + spin_unlock_irq(&data->txlock); + data->suspend_count--; + return -EBUSY; + } + + cancel_work_sync(&data->work); + + btusb_stop_traffic(data); + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->tx_anchor); + + return 0; +} + +static void play_deferred(struct btusb_data *data) +{ + struct urb *urb; + int err; + + while ((urb = usb_get_from_anchor(&data->deferred))) { + /************************************/ + usb_anchor_urb(urb, &data->tx_anchor); + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + RTKBT_ERR("play_deferred urb %p submission failed", + urb); + kfree(urb->setup_packet); + usb_unanchor_urb(urb); + } else { + usb_mark_last_busy(data->udev); + } + usb_free_urb(urb); + /************************************/ + data->tx_in_flight++; + } + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_scuttle_anchored_urbs(&data->deferred); +} + +static int btusb_resume(struct usb_interface *intf) +{ + struct btusb_data *data = usb_get_intfdata(intf); + struct hci_dev *hdev = data->hdev; + int err = 0; + + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return 0; + + /*******************************/ + RTKBT_DBG("%s: data->suspend_count %d", __func__, data->suspend_count); + + /* if intf->needs_binding is set, driver will be rebind. + * The probe will be called instead of resume */ + /* if (!test_bit(HCI_RUNNING, &hdev->flags)) { + * RTKBT_DBG("btusb_resume-----bt is off,download patch"); + * download_patch(intf); + * } else + * RTKBT_DBG("btusb_resume,----bt is on"); + */ + /*******************************/ + if (--data->suspend_count) + return 0; + + if (test_bit(BTUSB_INTR_RUNNING, &data->flags)) { + err = btusb_submit_intr_urb(hdev, GFP_NOIO); + if (err < 0) { + clear_bit(BTUSB_INTR_RUNNING, &data->flags); + goto failed; + } + } + + if (test_bit(BTUSB_BULK_RUNNING, &data->flags)) { + err = btusb_submit_bulk_urb(hdev, GFP_NOIO); + if (err < 0) { + clear_bit(BTUSB_BULK_RUNNING, &data->flags); + goto failed; + } + + btusb_submit_bulk_urb(hdev, GFP_NOIO); + } + + if (test_bit(BTUSB_ISOC_RUNNING, &data->flags)) { + if (btusb_submit_isoc_urb(hdev, GFP_NOIO) < 0) + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + else + btusb_submit_isoc_urb(hdev, GFP_NOIO); + } + + spin_lock_irq(&data->txlock); + play_deferred(data); + clear_bit(BTUSB_SUSPENDING, &data->flags); + spin_unlock_irq(&data->txlock); + schedule_work(&data->work); + + RTKBT_DBG("%s: data->suspend_count %d, done", __func__, + data->suspend_count); + + return 0; + +failed: + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_scuttle_anchored_urbs(&data->deferred); +//done: + spin_lock_irq(&data->txlock); + clear_bit(BTUSB_SUSPENDING, &data->flags); + spin_unlock_irq(&data->txlock); + RTKBT_DBG("%s: data->suspend_count %d, fail", __func__, + data->suspend_count); + + return err; +} +#endif + +static struct usb_driver btusb_driver = { + .name = "rtk_btusb", + .probe = btusb_probe, + .disconnect = btusb_disconnect, +#ifdef CONFIG_PM + .suspend = btusb_suspend, + .resume = btusb_resume, +#ifdef RTKBT_SWITCH_PATCH + .reset_resume = btusb_resume, +#endif +#endif + .id_table = btusb_table, + .supports_autosuspend = 1, +#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 7, 1) + .disable_hub_initiated_lpm = 1, +#endif +}; + +static int __init btusb_init(void) +{ + RTKBT_DBG("Realtek Bluetooth USB driver ver %s", VERSION); +#ifdef BTCOEX + rtk_btcoex_init(); +#endif + return usb_register(&btusb_driver); +} + +static void __exit btusb_exit(void) +{ + RTKBT_DBG("rtk_btusb: btusb_exit"); + usb_deregister(&btusb_driver); + +#ifdef BTCOEX + rtk_btcoex_exit(); +#endif +} + +module_init(btusb_init); +module_exit(btusb_exit); + +MODULE_AUTHOR(""); +MODULE_DESCRIPTION("Realtek Bluetooth USB driver ver " VERSION); +MODULE_VERSION(VERSION); +MODULE_LICENSE("GPL"); diff --git a/drivers/bluetooth/rtk_bt.h b/drivers/bluetooth/rtk_bt.h new file mode 100644 index 0000000000000..9d23b7fa2c312 --- /dev/null +++ b/drivers/bluetooth/rtk_bt.h @@ -0,0 +1,148 @@ +/* + * + * Realtek Bluetooth USB driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* #define HCI_VERSION_CODE KERNEL_VERSION(3, 14, 41) */ +#define HCI_VERSION_CODE LINUX_VERSION_CODE + +#ifdef CONFIG_BTCOEX +#define BTCOEX +#endif + +/*********************************** +** Realtek - For rtk_btusb driver ** +***********************************/ +#ifdef CONFIG_BTUSB_WAKEUP_HOST +#define BTUSB_WAKEUP_HOST +#endif + +#define URB_CANCELING_DELAY_MS 10 // Added by Realtek +#if HCI_VERSION_CODE > KERNEL_VERSION(2, 6, 33) +#define HDEV_BUS hdev->bus +#else +#define HDEV_BUS hdev->type +#endif + +#if HCI_VERSION_CODE < KERNEL_VERSION(2, 6, 36) +#define NUM_REASSEMBLY 3 +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 4, 0) +#define GET_DRV_DATA(x) hci_get_drvdata(x) +#else +#define GET_DRV_DATA(x) x->driver_data +#endif + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 13, 0) +#define SCO_NUM hdev->conn_hash.sco_num +#else +#define SCO_NUM hci_conn_num(hdev, SCO_LINK) +#endif + +int patch_add(struct usb_interface *intf); +void patch_remove(struct usb_interface *intf); +int download_patch(struct usb_interface *intf); +int set_btoff(struct usb_interface *intf); +void print_event(struct sk_buff *skb); +void print_command(struct sk_buff *skb); +void print_acl(struct sk_buff *skb, int dataOut); + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) +int btusb_send_frame(struct hci_dev *hdev, struct sk_buff *skb); +#else +int btusb_send_frame(struct sk_buff *skb); +#endif + +#define BTUSB_MAX_ISOC_FRAMES 10 +#define BTUSB_INTR_RUNNING 0 +#define BTUSB_BULK_RUNNING 1 +#define BTUSB_ISOC_RUNNING 2 +#define BTUSB_SUSPENDING 3 +#define BTUSB_DID_ISO_RESUME 4 + +struct btusb_data { + struct hci_dev *hdev; + struct usb_device *udev; + struct usb_interface *intf; + struct usb_interface *isoc; + + spinlock_t lock; + + unsigned long flags; + + struct work_struct work; + struct work_struct waker; + + struct usb_anchor tx_anchor; + struct usb_anchor intr_anchor; + struct usb_anchor bulk_anchor; + struct usb_anchor isoc_anchor; + struct usb_anchor deferred; + int tx_in_flight; + spinlock_t txlock; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + spinlock_t rxlock; + struct sk_buff *evt_skb; + struct sk_buff *acl_skb; + struct sk_buff *sco_skb; +#endif + + struct usb_endpoint_descriptor *intr_ep; + struct usb_endpoint_descriptor *bulk_tx_ep; + struct usb_endpoint_descriptor *bulk_rx_ep; + struct usb_endpoint_descriptor *isoc_tx_ep; + struct usb_endpoint_descriptor *isoc_rx_ep; + + __u8 cmdreq_type; + + unsigned int sco_num; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) + unsigned int air_mode; +#endif + int isoc_altsetting; + int suspend_count; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + int (*recv_bulk) (struct btusb_data * data, void *buffer, int count); +#endif + struct notifier_block pm_notifier; + void *context; +}; diff --git a/drivers/bluetooth/rtk_coex.c b/drivers/bluetooth/rtk_coex.c new file mode 100644 index 0000000000000..6f05723b39887 --- /dev/null +++ b/drivers/bluetooth/rtk_coex.c @@ -0,0 +1,3069 @@ +/* +* +* Realtek Bluetooth USB driver +* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +* +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtk_coex.h" + +/* Software coex message can be sent to and receive from WiFi driver by + * UDP socket or exported symbol */ +/* #define RTK_COEX_OVER_SYMBOL */ + +#if BTRTL_HCI_IF == BTRTL_HCIUSB +#include +#include "rtk_bt.h" +#undef RTKBT_DBG +#undef RTKBT_INFO +#undef RTKBT_WARN +#undef RTKBT_ERR + +#elif BTRTL_HCI_IF == BTRTL_HCIUART +/* #define HCI_VERSION_CODE KERNEL_VERSION(3, 14, 41) */ +#define HCI_VERSION_CODE LINUX_VERSION_CODE + +#else +#error "Please set type of HCI interface" +#endif + +#define RTK_VERSION "1.2" + +#define RTKBT_DBG(fmt, arg...) printk(KERN_INFO "rtk_btcoex: " fmt "\n" , ## arg) +#define RTKBT_INFO(fmt, arg...) printk(KERN_INFO "rtk_btcoex: " fmt "\n" , ## arg) +#define RTKBT_WARN(fmt, arg...) printk(KERN_WARNING "rtk_btcoex: " fmt "\n", ## arg) +#define RTKBT_ERR(fmt, arg...) printk(KERN_WARNING "rtk_btcoex: " fmt "\n", ## arg) + +static struct rtl_coex_struct btrtl_coex; + +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL +static struct sk_buff_head rtw_q; +static struct workqueue_struct *rtw_wq; +static struct work_struct rtw_work; +static u8 rtw_coex_on; +#endif +#endif + +#define is_profile_connected(profile) ((btrtl_coex.profile_bitmap & BIT(profile)) > 0) +#define is_profile_busy(profile) ((btrtl_coex.profile_status & BIT(profile)) > 0) + +#ifdef RTB_SOFTWARE_MAILBOX +static void rtk_handle_event_from_wifi(uint8_t * msg); +#endif + +static int rtl_alloc_buff(struct rtl_coex_struct *coex) +{ + struct rtl_hci_ev *ev; + struct rtl_l2_buff *l2; + int i; + int order; + unsigned long addr; + unsigned long addr2; + int ev_size; + int l2_size; + int n; + + spin_lock_init(&coex->buff_lock); + + INIT_LIST_HEAD(&coex->ev_used_list); + INIT_LIST_HEAD(&coex->ev_free_list); + + INIT_LIST_HEAD(&coex->l2_used_list); + INIT_LIST_HEAD(&coex->l2_free_list); + + n = NUM_RTL_HCI_EV * sizeof(struct rtl_hci_ev); + ev_size = ALIGN(n, sizeof(unsigned long)); + + n = L2_MAX_PKTS * sizeof(struct rtl_l2_buff); + l2_size = ALIGN(n, sizeof(unsigned long)); + + RTKBT_DBG("alloc buffers %d, %d for ev and l2", ev_size, l2_size); + + order = get_order(ev_size + l2_size); + addr = __get_free_pages(GFP_KERNEL, order); + if (!addr) { + RTKBT_ERR("failed to alloc buffers for ev and l2."); + return -ENOMEM; + } + memset((void *)addr, 0, ev_size + l2_size); + + coex->pages_addr = addr; + coex->buff_size = ev_size + l2_size; + + ev = (struct rtl_hci_ev *)addr; + for (i = 0; i < NUM_RTL_HCI_EV; i++) { + list_add_tail(&ev->list, &coex->ev_free_list); + ev++; + } + + addr2 = addr + ev_size; + l2 = (struct rtl_l2_buff *)addr2; + for (i = 0; i < L2_MAX_PKTS; i++) { + list_add_tail(&l2->list, &coex->l2_free_list); + l2++; + } + + return 0; +} + +static void rtl_free_buff(struct rtl_coex_struct *coex) +{ + struct rtl_hci_ev *ev; + struct rtl_l2_buff *l2; + unsigned long flags; + + spin_lock_irqsave(&coex->buff_lock, flags); + + while (!list_empty(&coex->ev_used_list)) { + ev = list_entry(coex->ev_used_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + } + + while (!list_empty(&coex->ev_free_list)) { + ev = list_entry(coex->ev_free_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + } + + while (!list_empty(&coex->l2_used_list)) { + l2 = list_entry(coex->l2_used_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + } + + while (!list_empty(&coex->l2_free_list)) { + l2 = list_entry(coex->l2_free_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + } + + spin_unlock_irqrestore(&coex->buff_lock, flags); + + if (coex->buff_size > 0) { + free_pages(coex->pages_addr, get_order(coex->buff_size)); + coex->pages_addr = 0; + coex->buff_size = 0; + } +} + +static struct rtl_hci_ev *rtl_ev_node_get(struct rtl_coex_struct *coex) +{ + struct rtl_hci_ev *ev; + unsigned long flags; + + if (!coex->buff_size) + return NULL; + + spin_lock_irqsave(&coex->buff_lock, flags); + if (!list_empty(&coex->ev_free_list)) { + ev = list_entry(coex->ev_free_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + } else + ev = NULL; + spin_unlock_irqrestore(&coex->buff_lock, flags); + return ev; +} + +static int rtl_ev_node_to_used(struct rtl_coex_struct *coex, + struct rtl_hci_ev *ev) +{ + unsigned long flags; + + spin_lock_irqsave(&coex->buff_lock, flags); + list_add_tail(&ev->list, &coex->ev_used_list); + spin_unlock_irqrestore(&coex->buff_lock, flags); + + return 0; +} + +static struct rtl_l2_buff *rtl_l2_node_get(struct rtl_coex_struct *coex) +{ + struct rtl_l2_buff *l2; + unsigned long flags; + + if (!coex->buff_size) + return NULL; + + spin_lock_irqsave(&coex->buff_lock, flags); + + if(!list_empty(&coex->l2_free_list)) { + l2 = list_entry(coex->l2_free_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + } else + l2 = NULL; + + spin_unlock_irqrestore(&coex->buff_lock, flags); + return l2; +} + +static int rtl_l2_node_to_used(struct rtl_coex_struct *coex, + struct rtl_l2_buff *l2) +{ + unsigned long flags; + + spin_lock_irqsave(&coex->buff_lock, flags); + list_add_tail(&l2->list, &coex->l2_used_list); + spin_unlock_irqrestore(&coex->buff_lock, flags); + + return 0; +} + +static int8_t psm_to_profile_index(uint16_t psm) +{ + switch (psm) { + case PSM_AVCTP: + case PSM_SDP: + return -1; //ignore + + case PSM_HID: + case PSM_HID_INT: + return profile_hid; + + case PSM_AVDTP: + return profile_a2dp; + + case PSM_PAN: + case PSM_OPP: + case PSM_FTP: + case PSM_BIP: + case PSM_RFCOMM: + return profile_pan; + + default: + return profile_pan; + } +} + +static rtk_prof_info *find_by_psm(u16 psm) +{ + struct list_head *head = &btrtl_coex.profile_list; + struct list_head *iter = NULL; + struct list_head *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (desc->psm == psm) + return desc; + } + + return NULL; +} + +static void rtk_check_setup_timer(int8_t profile_index) +{ + if (profile_index == profile_a2dp) { + btrtl_coex.a2dp_packet_count = 0; + btrtl_coex.a2dp_count_timer.expires = + jiffies + msecs_to_jiffies(1000); + mod_timer(&btrtl_coex.a2dp_count_timer, + btrtl_coex.a2dp_count_timer.expires); + } + + if (profile_index == profile_pan) { + btrtl_coex.pan_packet_count = 0; + btrtl_coex.pan_count_timer.expires = + jiffies + msecs_to_jiffies(1000); + mod_timer(&btrtl_coex.pan_count_timer, + btrtl_coex.pan_count_timer.expires); + } + + /* hogp & voice share one timer now */ + if ((profile_index == profile_hogp) || (profile_index == profile_voice)) { + if ((0 == btrtl_coex.profile_refcount[profile_hogp]) + && (0 == btrtl_coex.profile_refcount[profile_voice])) { + btrtl_coex.hogp_packet_count = 0; + btrtl_coex.voice_packet_count = 0; + btrtl_coex.hogp_count_timer.expires = + jiffies + msecs_to_jiffies(1000); + mod_timer(&btrtl_coex.hogp_count_timer, + btrtl_coex.hogp_count_timer.expires); + } + } +} + +static void rtk_check_del_timer(int8_t profile_index) +{ + if (profile_a2dp == profile_index) { + btrtl_coex.a2dp_packet_count = 0; + del_timer_sync(&btrtl_coex.a2dp_count_timer); + } + if (profile_pan == profile_index) { + btrtl_coex.pan_packet_count = 0; + del_timer_sync(&btrtl_coex.pan_count_timer); + } + if (profile_hogp == profile_index) { + btrtl_coex.hogp_packet_count = 0; + if (btrtl_coex.profile_refcount[profile_voice] == 0) { + del_timer_sync(&btrtl_coex.hogp_count_timer); + } + } + if (profile_voice == profile_index) { + btrtl_coex.voice_packet_count = 0; + if (btrtl_coex.profile_refcount[profile_hogp] == 0) { + del_timer_sync(&btrtl_coex.hogp_count_timer); + } + } +} + + + +static rtk_conn_prof *find_connection_by_handle(struct rtl_coex_struct * coex, + uint16_t handle) +{ + struct list_head *head = &coex->conn_hash; + struct list_head *iter = NULL, *temp = NULL; + rtk_conn_prof *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_conn_prof, list); + if ((handle & 0xEFF) == desc->handle) { + return desc; + } + } + return NULL; +} + +static rtk_conn_prof *allocate_connection_by_handle(uint16_t handle) +{ + rtk_conn_prof *phci_conn = NULL; + phci_conn = kmalloc(sizeof(rtk_conn_prof), GFP_ATOMIC); + if (phci_conn) + phci_conn->handle = handle; + + return phci_conn; +} + +static void init_connection_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->conn_hash; + INIT_LIST_HEAD(head); +} + +static void add_connection_to_hash(struct rtl_coex_struct * coex, + rtk_conn_prof * desc) +{ + struct list_head *head = &coex->conn_hash; + list_add_tail(&desc->list, head); +} + +static void delete_connection_from_hash(rtk_conn_prof * desc) +{ + if (desc) { + list_del(&desc->list); + kfree(desc); + } +} + +static void flush_connection_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->conn_hash; + struct list_head *iter = NULL, *temp = NULL; + rtk_conn_prof *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_conn_prof, list); + if (desc) { + list_del(&desc->list); + kfree(desc); + } + } + //INIT_LIST_HEAD(head); +} + +static void init_profile_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->profile_list; + INIT_LIST_HEAD(head); +} + +static uint8_t list_allocate_add(uint16_t handle, uint16_t psm, + int8_t profile_index, uint16_t dcid, + uint16_t scid) +{ + rtk_prof_info *pprof_info = NULL; + + if (profile_index < 0) { + RTKBT_ERR("PSM 0x%x do not need parse", psm); + return FALSE; + } + + pprof_info = kmalloc(sizeof(rtk_prof_info), GFP_ATOMIC); + + if (NULL == pprof_info) { + RTKBT_ERR("list_allocate_add: allocate error"); + return FALSE; + } + + /* Check if it is the second l2cap connection for a2dp + * a2dp signal channel will be created first than media channel. + */ + if (psm == PSM_AVDTP) { + rtk_prof_info *pinfo = find_by_psm(psm); + if (!pinfo) { + pprof_info->flags = A2DP_SIGNAL; + RTKBT_INFO("%s: Add a2dp signal channel", __func__); + } else { + pprof_info->flags = A2DP_MEDIA; + RTKBT_INFO("%s: Add a2dp media channel", __func__); + } + } + + pprof_info->handle = handle; + pprof_info->psm = psm; + pprof_info->scid = scid; + pprof_info->dcid = dcid; + pprof_info->profile_index = profile_index; + list_add_tail(&(pprof_info->list), &(btrtl_coex.profile_list)); + + return TRUE; +} + +static void delete_profile_from_hash(rtk_prof_info * desc) +{ + if (desc) { + RTKBT_DBG("Delete profile: hndl 0x%04x, psm 0x%04x, dcid 0x%04x, " + "scid 0x%04x", desc->handle, desc->psm, desc->dcid, + desc->scid); + + list_del(&desc->list); + kfree(desc); + desc = NULL; + } +} + +static void flush_profile_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + spin_lock(&btrtl_coex.spin_lock_profile); + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + delete_profile_from_hash(desc); + } + //INIT_LIST_HEAD(head); + spin_unlock(&btrtl_coex.spin_lock_profile); +} + +static rtk_prof_info *find_profile_by_handle_scid(struct rtl_coex_struct * + coex, uint16_t handle, + uint16_t scid) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (((handle & 0xFFF) == desc->handle) && (scid == desc->scid)) { + return desc; + } + } + return NULL; +} + +static rtk_prof_info *find_profile_by_handle_dcid(struct rtl_coex_struct * + coex, uint16_t handle, + uint16_t dcid) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (((handle & 0xFFF) == desc->handle) && (dcid == desc->dcid)) { + return desc; + } + } + return NULL; +} + +static rtk_prof_info *find_profile_by_handle_dcid_scid(struct rtl_coex_struct + * coex, uint16_t handle, + uint16_t dcid, + uint16_t scid) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (((handle & 0xFFF) == desc->handle) && (dcid == desc->dcid) + && (scid == desc->scid)) { + return desc; + } + } + return NULL; +} + +static void rtk_vendor_cmd_to_fw(uint16_t opcode, uint8_t parameter_len, + uint8_t * parameter) +{ + int len = HCI_CMD_PREAMBLE_SIZE + parameter_len; + uint8_t *p; + struct sk_buff *skb; + struct hci_dev *hdev = btrtl_coex.hdev; + + if (!hdev) { + RTKBT_ERR("No HCI device"); + return; + } else if (!test_bit(HCI_UP, &hdev->flags)) { + RTKBT_WARN("HCI device is down"); + return; + } + + skb = bt_skb_alloc(len, GFP_ATOMIC); + if (!skb) { + RTKBT_DBG("there is no room for cmd 0x%x", opcode); + return; + } + + p = (uint8_t *) skb_put(skb, HCI_CMD_PREAMBLE_SIZE); + UINT16_TO_STREAM(p, opcode); + *p++ = parameter_len; + + if (parameter_len) + memcpy(skb_put(skb, parameter_len), parameter, parameter_len); + + bt_cb(skb)->pkt_type = HCI_COMMAND_PKT; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 4, 0) + bt_cb(skb)->opcode = opcode; +#else + bt_cb(skb)->hci.opcode = opcode; +#endif +#endif + + /* Stand-alone HCI commands must be flagged as + * single-command requests. + */ +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 10, 0) +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 4, 0) + bt_cb(skb)->req.start = true; +#else + +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 5, 0) + bt_cb(skb)->hci.req_start = true; +#else + + bt_cb(skb)->hci.req_flags |= HCI_REQ_START; +#endif + +#endif /* 4.4.0 */ +#endif /* 3.10.0 */ + RTKBT_DBG("%s: opcode 0x%x", __func__, opcode); + + /* It is harmless if set skb->dev twice. The dev will be used in + * btusb_send_frame() after or equal to kernel/hci 3.13.0, + * the hdev will not come from skb->dev. */ +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 13, 0) + skb->dev = (void *)btrtl_coex.hdev; +#endif + /* Put the skb to the global hdev->cmd_q */ + skb_queue_tail(&hdev->cmd_q, skb); + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 3, 0) + tasklet_schedule(&hdev->cmd_task); +#else + queue_work(hdev->workqueue, &hdev->cmd_work); +#endif + + return; +} + +static void rtk_notify_profileinfo_to_fw(void) +{ + struct list_head *head = NULL; + struct list_head *iter = NULL; + struct list_head *temp = NULL; + rtk_conn_prof *hci_conn = NULL; + uint8_t handle_number = 0; + uint32_t buffer_size = 0; + uint8_t *p_buf = NULL; + uint8_t *p = NULL; + + head = &btrtl_coex.conn_hash; + list_for_each_safe(iter, temp, head) { + hci_conn = list_entry(iter, rtk_conn_prof, list); + if (hci_conn && hci_conn->profile_bitmap) + handle_number++; + } + + buffer_size = 1 + handle_number * 3 + 1; + + p_buf = kmalloc(buffer_size, GFP_ATOMIC); + + if (NULL == p_buf) { + RTKBT_ERR("%s: alloc error", __func__); + return; + } + p = p_buf; + + RTKBT_DBG("%s: BufferSize %u", __func__, buffer_size); + *p++ = handle_number; + RTKBT_DBG("%s: NumberOfHandles %u", __func__, handle_number); + head = &btrtl_coex.conn_hash; + list_for_each(iter, head) { + hci_conn = list_entry(iter, rtk_conn_prof, list); + if (hci_conn && hci_conn->profile_bitmap) { + UINT16_TO_STREAM(p, hci_conn->handle); + RTKBT_DBG("%s: handle 0x%04x", __func__, + hci_conn->handle); + *p++ = hci_conn->profile_bitmap; + RTKBT_DBG("%s: profile_bitmap 0x%02x", __func__, + hci_conn->profile_bitmap); + handle_number--; + } + if (0 == handle_number) + break; + } + + *p++ = btrtl_coex.profile_status; + RTKBT_DBG("%s: profile_status 0x%02x", __func__, + btrtl_coex.profile_status); + + rtk_vendor_cmd_to_fw(HCI_VENDOR_SET_PROFILE_REPORT_COMMAND, buffer_size, + p_buf); + + kfree(p_buf); + return; +} + +static void update_profile_state(uint8_t profile_index, uint8_t is_busy) +{ + uint8_t need_update = FALSE; + + if ((btrtl_coex.profile_bitmap & BIT(profile_index)) == 0) { + RTKBT_ERR("%s: : ERROR!!! profile(Index: %x) does not exist", + __func__, profile_index); + return; + } + + if (is_busy) { + if ((btrtl_coex.profile_status & BIT(profile_index)) == 0) { + need_update = TRUE; + btrtl_coex.profile_status |= BIT(profile_index); + } + } else { + if ((btrtl_coex.profile_status & BIT(profile_index)) > 0) { + need_update = TRUE; + btrtl_coex.profile_status &= ~(BIT(profile_index)); + } + } + + if (need_update) { + RTKBT_DBG("%s: btrtl_coex.profie_bitmap = %x", + __func__, btrtl_coex.profile_bitmap); + RTKBT_DBG("%s: btrtl_coex.profile_status = %x", + __func__, btrtl_coex.profile_status); + rtk_notify_profileinfo_to_fw(); + } +} + +static void update_profile_connection(rtk_conn_prof * phci_conn, + int8_t profile_index, uint8_t is_add) +{ + uint8_t need_update = FALSE; + uint8_t kk; + + RTKBT_DBG("%s: is_add %d, profile_index %x", __func__, + is_add, profile_index); + if (profile_index < 0) + return; + + if (is_add) { + if (btrtl_coex.profile_refcount[profile_index] == 0) { + need_update = TRUE; + btrtl_coex.profile_bitmap |= BIT(profile_index); + + /* SCO is always busy */ + if (profile_index == profile_sco) + btrtl_coex.profile_status |= + BIT(profile_index); + + rtk_check_setup_timer(profile_index); + } + btrtl_coex.profile_refcount[profile_index]++; + + if (0 == phci_conn->profile_refcount[profile_index]) { + need_update = TRUE; + phci_conn->profile_bitmap |= BIT(profile_index); + } + phci_conn->profile_refcount[profile_index]++; + } else { + if (!btrtl_coex.profile_refcount[profile_index]) { + RTKBT_WARN("profile %u refcount is already zero", + profile_index); + return; + } + btrtl_coex.profile_refcount[profile_index]--; + RTKBT_DBG("%s: btrtl_coex.profile_refcount[%x] = %x", + __func__, profile_index, + btrtl_coex.profile_refcount[profile_index]); + if (btrtl_coex.profile_refcount[profile_index] == 0) { + need_update = TRUE; + btrtl_coex.profile_bitmap &= ~(BIT(profile_index)); + + /* if profile does not exist, status is meaningless */ + btrtl_coex.profile_status &= ~(BIT(profile_index)); + rtk_check_del_timer(profile_index); + } + + phci_conn->profile_refcount[profile_index]--; + if (0 == phci_conn->profile_refcount[profile_index]) { + need_update = TRUE; + phci_conn->profile_bitmap &= ~(BIT(profile_index)); + + /* clear profile_hid_interval if need */ + if ((profile_hid == profile_index) + && (phci_conn-> + profile_bitmap & (BIT(profile_hid_interval)))) { + phci_conn->profile_bitmap &= + ~(BIT(profile_hid_interval)); + btrtl_coex. + profile_refcount[profile_hid_interval]--; + } + } + } + + RTKBT_DBG("%s: btrtl_coex.profile_bitmap 0x%02x", __func__, + btrtl_coex.profile_bitmap); + for (kk = 0; kk < 8; kk++) + RTKBT_DBG("%s: btrtl_coex.profile_refcount[%d] = %d", + __func__, kk, + btrtl_coex.profile_refcount[kk]); + + if (need_update) + rtk_notify_profileinfo_to_fw(); +} + +static void update_hid_active_state(uint16_t handle, uint16_t interval) +{ + uint8_t need_update = 0; + rtk_conn_prof *phci_conn = + find_connection_by_handle(&btrtl_coex, handle); + + if (phci_conn == NULL) + return; + + RTKBT_DBG("%s: handle 0x%04x, interval %u", __func__, handle, interval); + if (((phci_conn->profile_bitmap) & (BIT(profile_hid))) == 0) { + RTKBT_DBG("HID not connected, nothing to be down"); + return; + } + + if (interval < 60) { + if ((phci_conn->profile_bitmap & (BIT(profile_hid_interval))) == + 0) { + need_update = 1; + phci_conn->profile_bitmap |= BIT(profile_hid_interval); + + btrtl_coex.profile_refcount[profile_hid_interval]++; + if (btrtl_coex. + profile_refcount[profile_hid_interval] == 1) + btrtl_coex.profile_status |= + BIT(profile_hid); + } + } else { + if ((phci_conn->profile_bitmap & (BIT(profile_hid_interval)))) { + need_update = 1; + phci_conn->profile_bitmap &= + ~(BIT(profile_hid_interval)); + + btrtl_coex.profile_refcount[profile_hid_interval]--; + if (btrtl_coex. + profile_refcount[profile_hid_interval] == 0) + btrtl_coex.profile_status &= + ~(BIT(profile_hid)); + } + } + + if (need_update) + rtk_notify_profileinfo_to_fw(); +} + +static uint8_t handle_l2cap_con_req(uint16_t handle, uint16_t psm, + uint16_t scid, uint8_t direction) +{ + uint8_t status = FALSE; + rtk_prof_info *prof_info = NULL; + int8_t profile_index = psm_to_profile_index(psm); + + if (profile_index < 0) { + RTKBT_DBG("PSM(0x%04x) do not need parse", psm); + return status; + } + + spin_lock(&btrtl_coex.spin_lock_profile); + if (direction) //1: out + prof_info = + find_profile_by_handle_scid(&btrtl_coex, handle, scid); + else // 0:in + prof_info = + find_profile_by_handle_dcid(&btrtl_coex, handle, scid); + + if (prof_info) { + RTKBT_DBG("%s: this profile is already exist!", __func__); + spin_unlock(&btrtl_coex.spin_lock_profile); + return status; + } + + if (direction) //1: out + status = list_allocate_add(handle, psm, profile_index, 0, scid); + else // 0:in + status = list_allocate_add(handle, psm, profile_index, scid, 0); + + spin_unlock(&btrtl_coex.spin_lock_profile); + + if (!status) + RTKBT_ERR("%s: list_allocate_add failed!", __func__); + + return status; +} + +static uint8_t handle_l2cap_con_rsp(uint16_t handle, uint16_t dcid, + uint16_t scid, uint8_t direction, + uint8_t result) +{ + rtk_prof_info *prof_info = NULL; + rtk_conn_prof *phci_conn = NULL; + + spin_lock(&btrtl_coex.spin_lock_profile); + if (!direction) //0, in + prof_info = + find_profile_by_handle_scid(&btrtl_coex, handle, scid); + else //1, out + prof_info = + find_profile_by_handle_dcid(&btrtl_coex, handle, scid); + + if (!prof_info) { + //RTKBT_DBG("handle_l2cap_con_rsp: prof_info Not Find!!"); + spin_unlock(&btrtl_coex.spin_lock_profile); + return FALSE; + } + + if (!result) { //success + RTKBT_DBG("l2cap connection success, update connection"); + if (!direction) //0, in + prof_info->dcid = dcid; + else //1, out + prof_info->scid = dcid; + + phci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (phci_conn) + update_profile_connection(phci_conn, + prof_info->profile_index, + TRUE); + } + + spin_unlock(&btrtl_coex.spin_lock_profile); + return TRUE; +} + +static uint8_t handle_l2cap_discon_req(uint16_t handle, uint16_t dcid, + uint16_t scid, uint8_t direction) +{ + rtk_prof_info *prof_info = NULL; + rtk_conn_prof *phci_conn = NULL; + RTKBT_DBG("%s: handle 0x%04x, dcid 0x%04x, scid 0x%04x, dir %u", + __func__, handle, dcid, scid, direction); + + spin_lock(&btrtl_coex.spin_lock_profile); + if (!direction) //0: in + prof_info = + find_profile_by_handle_dcid_scid(&btrtl_coex, handle, + scid, dcid); + else //1: out + prof_info = + find_profile_by_handle_dcid_scid(&btrtl_coex, handle, + dcid, scid); + + if (!prof_info) { + //LogMsg("handle_l2cap_discon_req: prof_info Not Find!"); + spin_unlock(&btrtl_coex.spin_lock_profile); + return 0; + } + + phci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (!phci_conn) { + spin_unlock(&btrtl_coex.spin_lock_profile); + return 0; + } + + update_profile_connection(phci_conn, prof_info->profile_index, FALSE); + if (prof_info->profile_index == profile_a2dp && + (phci_conn->profile_bitmap & BIT(profile_sink))) + update_profile_connection(phci_conn, profile_sink, FALSE); + + delete_profile_from_hash(prof_info); + spin_unlock(&btrtl_coex.spin_lock_profile); + + return 1; +} + +static const char sample_freqs[4][8] = { + "16", "32", "44.1", "48" +}; + +static const uint8_t sbc_blocks[4] = { 4, 8, 12, 16 }; + +static const char chan_modes[4][16] = { + "MONO", "DUAL_CHANNEL", "STEREO", "JOINT_STEREO" +}; + +static const char alloc_methods[2][12] = { + "LOUDNESS", "SNR" +}; + +static const uint8_t subbands[2] = { 4, 8 }; + +void print_sbc_header(struct sbc_frame_hdr *hdr) +{ + RTKBT_DBG("syncword: %02x", hdr->syncword); + RTKBT_DBG("freq %skHz", sample_freqs[hdr->sampling_frequency]); + RTKBT_DBG("blocks %u", sbc_blocks[hdr->blocks]); + RTKBT_DBG("channel mode %s", chan_modes[hdr->channel_mode]); + RTKBT_DBG("allocation method %s", + alloc_methods[hdr->allocation_method]); + RTKBT_DBG("subbands %u", subbands[hdr->subbands]); +} + +static void packets_count(uint16_t handle, uint16_t scid, uint16_t length, + uint8_t direction, u8 *user_data) +{ + rtk_prof_info *prof_info = NULL; + + rtk_conn_prof *hci_conn = + find_connection_by_handle(&btrtl_coex, handle); + if (NULL == hci_conn) + return; + + if (0 == hci_conn->type) { + if (!direction) //0: in + prof_info = + find_profile_by_handle_scid(&btrtl_coex, handle, + scid); + else //1: out + prof_info = + find_profile_by_handle_dcid(&btrtl_coex, handle, + scid); + + if (!prof_info) { + //RTKBT_DBG("packets_count: prof_info Not Find!"); + return; + } + + /* avdtp media data */ + if (prof_info->profile_index == profile_a2dp && + prof_info->flags == A2DP_MEDIA) { + if (!is_profile_busy(profile_a2dp)) { + struct sbc_frame_hdr *sbc_header; + struct rtp_header *rtph; + u8 bitpool; + + update_profile_state(profile_a2dp, TRUE); + if (!direction) { + if (!(hci_conn->profile_bitmap & BIT(profile_sink))) { + btrtl_coex.profile_bitmap |= BIT(profile_sink); + hci_conn->profile_bitmap |= BIT(profile_sink); + update_profile_connection(hci_conn, profile_sink, 1); + } + update_profile_state(profile_sink, TRUE); + } + + /* We assume it is SBC if the packet length + * is bigger than 100 bytes + */ + if (length > 100) { + RTKBT_INFO("Length %u", length); + rtph = (struct rtp_header *)user_data; + + RTKBT_DBG("rtp: v %u, cc %u, pt %u", + rtph->v, rtph->cc, rtph->pt); + /* move forward */ + user_data += sizeof(struct rtp_header) + + rtph->cc * 4 + 1; + + /* point to the sbc frame header */ + sbc_header = (struct sbc_frame_hdr *)user_data; + bitpool = sbc_header->bitpool; + + print_sbc_header(sbc_header); + + RTKBT_DBG("bitpool %u", bitpool); + + rtk_vendor_cmd_to_fw(HCI_VENDOR_SET_BITPOOL, + 1, &bitpool); + } + } + btrtl_coex.a2dp_packet_count++; + } + + if (prof_info->profile_index == profile_pan) + btrtl_coex.pan_packet_count++; + } +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void count_a2dp_packet_timeout(struct timer_list *unused) +#else +static void count_a2dp_packet_timeout(unsigned long data) +#endif +{ + if (btrtl_coex.a2dp_packet_count) + RTKBT_DBG("%s: a2dp_packet_count %d", __func__, + btrtl_coex.a2dp_packet_count); + if (btrtl_coex.a2dp_packet_count == 0) { + if (is_profile_busy(profile_a2dp)) { + RTKBT_DBG("%s: a2dp busy->idle!", __func__); + update_profile_state(profile_a2dp, FALSE); + if (btrtl_coex.profile_bitmap & BIT(profile_sink)) + update_profile_state(profile_sink, FALSE); + } + } + btrtl_coex.a2dp_packet_count = 0; + mod_timer(&btrtl_coex.a2dp_count_timer, + jiffies + msecs_to_jiffies(1000)); +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void count_pan_packet_timeout(struct timer_list *unused) +#else +static void count_pan_packet_timeout(unsigned long data) +#endif +{ + if (btrtl_coex.pan_packet_count) + RTKBT_DBG("%s: pan_packet_count %d", __func__, + btrtl_coex.pan_packet_count); + if (btrtl_coex.pan_packet_count < PAN_PACKET_COUNT) { + if (is_profile_busy(profile_pan)) { + RTKBT_DBG("%s: pan busy->idle!", __func__); + update_profile_state(profile_pan, FALSE); + } + } else { + if (!is_profile_busy(profile_pan)) { + RTKBT_DBG("timeout_handler: pan idle->busy!"); + update_profile_state(profile_pan, TRUE); + } + } + btrtl_coex.pan_packet_count = 0; + mod_timer(&btrtl_coex.pan_count_timer, + jiffies + msecs_to_jiffies(1000)); +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void count_hogp_packet_timeout(struct timer_list *unused) +#else +static void count_hogp_packet_timeout(unsigned long data) +#endif +{ + if (btrtl_coex.hogp_packet_count) + RTKBT_DBG("%s: hogp_packet_count %d", __func__, + btrtl_coex.hogp_packet_count); + if (btrtl_coex.hogp_packet_count == 0) { + if (is_profile_busy(profile_hogp)) { + RTKBT_DBG("%s: hogp busy->idle!", __func__); + update_profile_state(profile_hogp, FALSE); + } + } + btrtl_coex.hogp_packet_count = 0; + + if (btrtl_coex.voice_packet_count) + RTKBT_DBG("%s: voice_packet_count %d", __func__, + btrtl_coex.voice_packet_count); + if (btrtl_coex.voice_packet_count == 0) { + if (is_profile_busy(profile_voice)) { + RTKBT_DBG("%s: voice busy->idle!", __func__); + update_profile_state(profile_voice, FALSE); + } + } + btrtl_coex.voice_packet_count = 0; + mod_timer(&btrtl_coex.hogp_count_timer, + jiffies + msecs_to_jiffies(1000)); +} + +#ifdef RTB_SOFTWARE_MAILBOX + +#ifndef RTK_COEX_OVER_SYMBOL +static int udpsocket_send(char *tx_msg, int msg_size) +{ + u8 error = 0; + struct msghdr udpmsg; + mm_segment_t oldfs; + struct iovec iov; + + RTKBT_DBG("send msg %s with len:%d", tx_msg, msg_size); + + if (btrtl_coex.sock_open) { + iov.iov_base = (void *)tx_msg; + iov.iov_len = msg_size; + udpmsg.msg_name = &btrtl_coex.wifi_addr; + udpmsg.msg_namelen = sizeof(struct sockaddr_in); +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0) + udpmsg.msg_iov = &iov; + udpmsg.msg_iovlen = 1; +#else + iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size); +#endif + udpmsg.msg_control = NULL; + udpmsg.msg_controllen = 0; + udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL; + oldfs = get_fs(); + set_fs(KERNEL_DS); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0) + error = sock_sendmsg(btrtl_coex.udpsock, &udpmsg, msg_size); +#else + error = sock_sendmsg(btrtl_coex.udpsock, &udpmsg); +#endif + set_fs(oldfs); + + if (error < 0) + RTKBT_DBG("Error when sendimg msg, error:%d", error); + } + + return error; +} +#endif + +#ifdef RTK_COEX_OVER_SYMBOL +/* Receive message from WiFi */ +u8 rtw_btcoex_wifi_to_bt(u8 *msg, u8 msg_size) +{ + struct sk_buff *nskb; + + if (!rtw_coex_on) { + RTKBT_WARN("Bluetooth is closed"); + return 0; + } + + nskb = alloc_skb(msg_size, GFP_ATOMIC); + if (!nskb) { + RTKBT_ERR("Couldnt alloc skb for WiFi coex message"); + return 0; + } + + memcpy(skb_put(nskb, msg_size), msg, msg_size); + skb_queue_tail(&rtw_q, nskb); + + queue_work(rtw_wq, &rtw_work); + + return 1; +} +EXPORT_SYMBOL(rtw_btcoex_wifi_to_bt); + +static int rtk_send_coexmsg2wifi(u8 *msg, u8 size) +{ + u8 result; + u8 (*btmsg_to_wifi)(u8 *, u8); + + btmsg_to_wifi = __symbol_get(VMLINUX_SYMBOL_STR(rtw_btcoex_bt_to_wifi)); + + if (!btmsg_to_wifi) { + /* RTKBT_ERR("Couldnt get symbol"); */ + return -1; + } + + result = btmsg_to_wifi(msg, size); + __symbol_put(VMLINUX_SYMBOL_STR(rtw_btcoex_bt_to_wifi)); + if (!result) { + RTKBT_ERR("Couldnt send coex msg to WiFi"); + return -1; + } else if (result == 1){ + /* successful to send message */ + return 0; + } else { + RTKBT_ERR("Unknown result %d", result); + return -1; + } +} + +static int rtkbt_process_coexskb(struct sk_buff *skb) +{ + rtk_handle_event_from_wifi(skb->data); + return 0; +} + +static void rtw_work_func(struct work_struct *work) +{ + struct sk_buff *skb; + + while ((skb = skb_dequeue(&rtw_q))) { + rtkbt_process_coexskb(skb); + kfree_skb(skb); + } +} + +#endif + +static int rtkbt_coexmsg_send(char *tx_msg, int msg_size) +{ +#ifdef RTK_COEX_OVER_SYMBOL + return rtk_send_coexmsg2wifi((uint8_t *)tx_msg, (u8)msg_size); +#else + return udpsocket_send(tx_msg, msg_size); +#endif +} + +#ifndef RTK_COEX_OVER_SYMBOL +static void udpsocket_recv_data(void) +{ + u8 recv_data[512]; + u32 len = 0; + u16 recv_length; + struct sk_buff *skb; + + RTKBT_DBG("-"); + + spin_lock(&btrtl_coex.spin_lock_sock); + len = skb_queue_len(&btrtl_coex.sk->sk_receive_queue); + + while (len > 0) { + skb = skb_dequeue(&btrtl_coex.sk->sk_receive_queue); + + /*important: cut the udp header from skb->data! header length is 8 byte */ + recv_length = skb->len - 8; + memset(recv_data, 0, sizeof(recv_data)); + memcpy(recv_data, skb->data + 8, recv_length); + //RTKBT_DBG("received data: %s :with len %u", recv_data, recv_length); + + rtk_handle_event_from_wifi(recv_data); + + len--; + kfree_skb(skb); + } + + spin_unlock(&btrtl_coex.spin_lock_sock); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0) +static void udpsocket_recv(struct sock *sk, int bytes) +#else +static void udpsocket_recv(struct sock *sk) +#endif +{ + spin_lock(&btrtl_coex.spin_lock_sock); + btrtl_coex.sk = sk; + spin_unlock(&btrtl_coex.spin_lock_sock); + queue_delayed_work(btrtl_coex.sock_wq, &btrtl_coex.sock_work, 0); +} + +static void create_udpsocket(void) +{ + int err; + RTKBT_DBG("%s: connect_port: %d", __func__, CONNECT_PORT); + btrtl_coex.sock_open = 0; + + err = sock_create(AF_INET, SOCK_DGRAM, IPPROTO_UDP, + &btrtl_coex.udpsock); + if (err < 0) { + RTKBT_ERR("%s: sock create error, err = %d", __func__, err); + return; + } + + memset(&btrtl_coex.addr, 0, sizeof(struct sockaddr_in)); + btrtl_coex.addr.sin_family = AF_INET; + btrtl_coex.addr.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + btrtl_coex.addr.sin_port = htons(CONNECT_PORT); + + memset(&btrtl_coex.wifi_addr, 0, sizeof(struct sockaddr_in)); + btrtl_coex.wifi_addr.sin_family = AF_INET; + btrtl_coex.wifi_addr.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + btrtl_coex.wifi_addr.sin_port = htons(CONNECT_PORT_WIFI); + + err = + btrtl_coex.udpsock->ops->bind(btrtl_coex.udpsock, + (struct sockaddr *)&btrtl_coex. + addr, sizeof(struct sockaddr)); + if (err < 0) { + sock_release(btrtl_coex.udpsock); + RTKBT_ERR("%s: sock bind error, err = %d",__func__, err); + return; + } + + btrtl_coex.sock_open = 1; + btrtl_coex.udpsock->sk->sk_data_ready = udpsocket_recv; +} +#endif /* !RTK_COEX_OVER_SYMBOL */ + +static void rtk_notify_extension_version_to_wifi(void) +{ + uint8_t para_length = 2; + char p_buf[2 + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_EXTENSION_VERSION_NOTIFY); + *p++ = para_length; + UINT16_TO_STREAM(p, HCI_EXTENSION_VERSION); + RTKBT_DBG("extension version is 0x%x", HCI_EXTENSION_VERSION); + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_btpatch_version_to_wifi(void) +{ + uint8_t para_length = 4; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_PATCH_VER_NOTIFY); + *p++ = para_length; + UINT16_TO_STREAM(p, btrtl_coex.hci_reversion); + UINT16_TO_STREAM(p, btrtl_coex.lmp_subversion); + RTKBT_DBG("btpatch ver: len %u, hci_rev 0x%04x, lmp_subver 0x%04x", + para_length, btrtl_coex.hci_reversion, + btrtl_coex.lmp_subversion); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_afhmap_to_wifi(void) +{ + uint8_t para_length = 13; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + uint8_t kk = 0; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_AFH_MAP_NOTIFY); + *p++ = para_length; + *p++ = btrtl_coex.piconet_id; + *p++ = btrtl_coex.mode; + *p++ = 10; + memcpy(p, btrtl_coex.afh_map, 10); + + RTKBT_DBG("afhmap, piconet_id is 0x%x, map type is 0x%x", + btrtl_coex.piconet_id, btrtl_coex.mode); + for (kk = 0; kk < 10; kk++) + RTKBT_DBG("afhmap data[%d] is 0x%x", kk, + btrtl_coex.afh_map[kk]); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_btcoex_to_wifi(uint8_t opcode, uint8_t status) +{ + uint8_t para_length = 2; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_COEX_NOTIFY); + *p++ = para_length; + *p++ = opcode; + if (!status) + *p++ = 0; + else + *p++ = 1; + + RTKBT_DBG("btcoex, opcode is 0x%x, status is 0x%x", opcode, status); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_btoperation_to_wifi(uint8_t operation, + uint8_t append_data_length, + uint8_t * append_data) +{ + uint8_t para_length = 3 + append_data_length; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + uint8_t kk = 0; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_BT_OPERATION_NOTIFY); + *p++ = para_length; + *p++ = operation; + *p++ = append_data_length; + if (append_data_length) + memcpy(p, append_data, append_data_length); + + RTKBT_DBG("btoperation: op 0x%02x, append_data_length %u", + operation, append_data_length); + if (append_data_length) { + for (kk = 0; kk < append_data_length; kk++) + RTKBT_DBG("append data is 0x%x", *(append_data + kk)); + } + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_info_to_wifi(uint8_t reason, uint8_t length, + uint8_t *report_info) +{ + uint8_t para_length = 4 + length; + char buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = buf; + struct rtl_btinfo *report = (struct rtl_btinfo *)report_info; + + if (length) { + RTKBT_DBG("bt info: cmd %2.2X", report->cmd); + RTKBT_DBG("bt info: len %2.2X", report->len); + RTKBT_DBG("bt info: data %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X", + report->data[0], report->data[1], report->data[2], + report->data[3], report->data[4], report->data[5]); + } + RTKBT_DBG("bt info: reason 0x%2x, length 0x%2x", reason, length); + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_INFO_NOTIFY); + *p++ = para_length; + *p++ = btrtl_coex.polling_enable; + *p++ = btrtl_coex.polling_interval; + *p++ = reason; + *p++ = length; + + if (length) + memcpy(p, report_info, length); + + RTKBT_DBG("para length %2x, polling_enable %u, poiiling_interval %u", + para_length, btrtl_coex.polling_enable, + btrtl_coex.polling_interval); + /* send BT INFO to Wi-Fi driver */ + if (rtkbt_coexmsg_send(buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_regester_to_wifi(uint8_t * reg_value) +{ + uint8_t para_length = 9; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + hci_mailbox_register *reg = (hci_mailbox_register *) reg_value; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_REGISTER_VALUE_NOTIFY); + *p++ = para_length; + memcpy(p, reg_value, para_length); + + RTKBT_DBG("bt register, register type is %x", reg->type); + RTKBT_DBG("bt register, register offset is %x", reg->offset); + RTKBT_DBG("bt register, register value is %x", reg->value); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +#endif + +void rtk_btcoex_parse_cmd(uint8_t *buffer, int count) +{ + u16 opcode = (buffer[0]) + (buffer[1] << 8); + + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_INFO("%s: Coex is closed, ignore", __func__); + return; + } + + switch (opcode) { + case HCI_OP_INQUIRY: + case HCI_OP_PERIODIC_INQ: + if (!btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci (periodic)inq, notify wifi " + "inquiry start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_START, + 0, NULL); +#else + RTKBT_INFO("hci (periodic)inq start"); +#endif + } + break; + case HCI_OP_INQUIRY_CANCEL: + case HCI_OP_EXIT_PERIODIC_INQ: + if (btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci (periodic)inq cancel/exit, notify wifi " + "inquiry stop"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, + NULL); +#else + RTKBT_INFO("hci (periodic)inq cancel/exit"); +#endif + } + break; + case HCI_OP_ACCEPT_CONN_REQ: + if (!btrtl_coex.ispaging) { + btrtl_coex.ispaging = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci accept connreq, notify wifi page start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_START, 0, + NULL); +#else + RTKBT_INFO("hci accept conn req"); +#endif + } + break; + case HCI_OP_DISCONNECT: + RTKBT_INFO("HCI Disconnect, handle %04x, reason 0x%02x", + ((u16)buffer[4] << 8 | buffer[3]), buffer[5]); + break; + default: + break; + } +} + +static void rtk_handle_inquiry_complete(void) +{ + if (btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("inq complete, notify wifi inquiry end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, NULL); +#else + RTKBT_INFO("inquiry complete"); +#endif + } +} + +static void rtk_handle_pin_code_req(void) +{ + if (!btrtl_coex.ispairing) { + btrtl_coex.ispairing = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("pin code req, notify wifi pair start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_START, 0, NULL); +#else + RTKBT_INFO("pin code request"); +#endif + } +} + +static void rtk_handle_io_capa_req(void) +{ + if (!btrtl_coex.ispairing) { + btrtl_coex.ispairing = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("io cap req, notify wifi pair start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_START, 0, NULL); +#else + RTKBT_INFO("io capability request"); +#endif + } +} + +static void rtk_handle_auth_request(void) +{ + if (btrtl_coex.ispairing) { + btrtl_coex.ispairing = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("auth req, notify wifi pair end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_END, 0, NULL); +#else + RTKBT_INFO("authentication request"); +#endif + } +} + +static void rtk_handle_link_key_notify(void) +{ + if (btrtl_coex.ispairing) { + btrtl_coex.ispairing = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("link key notify, notify wifi pair end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_END, 0, NULL); +#else + RTKBT_INFO("link key notify"); +#endif + } +} + +static void rtk_handle_mode_change_evt(u8 * p) +{ + u16 mode_change_handle, mode_interval; + + p++; + STREAM_TO_UINT16(mode_change_handle, p); + p++; + STREAM_TO_UINT16(mode_interval, p); + update_hid_active_state(mode_change_handle, mode_interval); +} + +#ifdef RTB_SOFTWARE_MAILBOX +static void rtk_parse_vendor_mailbox_cmd_evt(u8 * p, u8 total_len) +{ + u8 status, subcmd; + u8 temp_cmd[10]; + + status = *p++; + if (total_len <= 4) { + RTKBT_DBG("receive mailbox cmd from fw, total length <= 4"); + return; + } + subcmd = *p++; + RTKBT_DBG("receive mailbox cmd from fw, subcmd is 0x%x, status is 0x%x", + subcmd, status); + + switch (subcmd) { + case HCI_VENDOR_SUB_CMD_BT_REPORT_CONN_SCO_INQ_INFO: + if (status == 0) //success + rtk_notify_info_to_wifi(POLLING_RESPONSE, + RTL_BTINFO_LEN, (uint8_t *)p); + break; + + case HCI_VENDOR_SUB_CMD_WIFI_CHANNEL_AND_BANDWIDTH_CMD: + rtk_notify_btcoex_to_wifi(WIFI_BW_CHNL_NOTIFY, status); + break; + + case HCI_VENDOR_SUB_CMD_WIFI_FORCE_TX_POWER_CMD: + rtk_notify_btcoex_to_wifi(BT_POWER_DECREASE_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_BT_ENABLE_IGNORE_WLAN_ACT_CMD: + rtk_notify_btcoex_to_wifi(IGNORE_WLAN_ACTIVE_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_SET_BT_PSD_MODE: + rtk_notify_btcoex_to_wifi(BT_PSD_MODE_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_SET_BT_LNA_CONSTRAINT: + rtk_notify_btcoex_to_wifi(LNA_CONSTRAIN_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_ENABLE: + break; + + case HCI_VENDOR_SUB_CMD_BT_SET_TXRETRY_REPORT_PARAM: + break; + + case HCI_VENDOR_SUB_CMD_BT_SET_PTATABLE: + break; + + case HCI_VENDOR_SUB_CMD_GET_AFH_MAP_L: + if (status == 0) { + memcpy(btrtl_coex.afh_map, p + 4, 4); /* cmd_idx, length, piconet_id, mode */ + temp_cmd[0] = HCI_VENDOR_SUB_CMD_GET_AFH_MAP_M; + temp_cmd[1] = 2; + temp_cmd[2] = btrtl_coex.piconet_id; + temp_cmd[3] = btrtl_coex.mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 4, + temp_cmd); + } else { + memset(btrtl_coex.afh_map, 0, 10); + rtk_notify_afhmap_to_wifi(); + } + break; + + case HCI_VENDOR_SUB_CMD_GET_AFH_MAP_M: + if (status == 0) { + memcpy(btrtl_coex.afh_map + 4, p + 4, 4); + temp_cmd[0] = HCI_VENDOR_SUB_CMD_GET_AFH_MAP_H; + temp_cmd[1] = 2; + temp_cmd[2] = btrtl_coex.piconet_id; + temp_cmd[3] = btrtl_coex.mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 4, + temp_cmd); + } else { + memset(btrtl_coex.afh_map, 0, 10); + rtk_notify_afhmap_to_wifi(); + } + break; + + case HCI_VENDOR_SUB_CMD_GET_AFH_MAP_H: + if (status == 0) + memcpy(btrtl_coex.afh_map + 8, p + 4, 2); + else + memset(btrtl_coex.afh_map, 0, 10); + + rtk_notify_afhmap_to_wifi(); + break; + + case HCI_VENDOR_SUB_CMD_RD_REG_REQ: + if (status == 0) + rtk_notify_regester_to_wifi(p + 3); /* cmd_idx,length,regist type */ + break; + + case HCI_VENDOR_SUB_CMD_WR_REG_REQ: + rtk_notify_btcoex_to_wifi(BT_REGISTER_ACCESS, status); + break; + + default: + break; + } +} +#endif /* RTB_SOFTWARE_MAILBOX */ + +static void rtk_handle_cmd_complete_evt(u8 total_len, u8 * p) +{ + u16 opcode; + + p++; + STREAM_TO_UINT16(opcode, p); + //RTKBT_DBG("cmd_complete, opcode is 0x%x", opcode); + + if (opcode == HCI_OP_PERIODIC_INQ) { + if (*p++ && btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci period inq, start error, notify wifi " + "inquiry stop"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, + NULL); +#else + RTKBT_INFO("hci period inquiry start error"); +#endif + } + } + + if (opcode == HCI_OP_READ_LOCAL_VERSION) { + if (!(*p++)) { + p++; + STREAM_TO_UINT16(btrtl_coex.hci_reversion, p); + p += 3; + STREAM_TO_UINT16(btrtl_coex.lmp_subversion, p); + RTKBT_DBG("BTCOEX hci_rev 0x%04x", + btrtl_coex.hci_reversion); + RTKBT_DBG("BTCOEX lmp_subver 0x%04x", + btrtl_coex.lmp_subversion); + } + } + +#ifdef RTB_SOFTWARE_MAILBOX + if (opcode == HCI_VENDOR_MAILBOX_CMD) { + rtk_parse_vendor_mailbox_cmd_evt(p, total_len); + } +#endif +} + +static void rtk_handle_cmd_status_evt(u8 * p) +{ + u16 opcode; + u8 status; + + status = *p++; + p++; + STREAM_TO_UINT16(opcode, p); + //RTKBT_DBG("cmd_status, opcode is 0x%x", opcode); + if ((opcode == HCI_OP_INQUIRY) && (status)) { + if (btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci inq, start error, notify wifi inq stop"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, + NULL); +#else + RTKBT_INFO("hci inquiry start error"); +#endif + } + } + + if (opcode == HCI_OP_CREATE_CONN) { + if (!status && !btrtl_coex.ispaging) { + btrtl_coex.ispaging = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci create conn, notify wifi start page"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_START, 0, + NULL); +#else + RTKBT_INFO("hci create connection, start paging"); +#endif + } + } +} + +static void rtk_handle_connection_complete_evt(u8 * p) +{ + u16 handle; + u8 status, link_type; + rtk_conn_prof *hci_conn = NULL; + + status = *p++; + STREAM_TO_UINT16(handle, p); + p += 6; + link_type = *p++; + + RTKBT_INFO("connected, handle %04x, status 0x%02x", handle, status); + + if (status == 0) { + if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page success end"); + rtk_notify_btoperation_to_wifi + (BT_OPCODE_PAGE_SUCCESS_END, 0, NULL); +#else + RTKBT_INFO("Page success"); +#endif + } + + hci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (hci_conn == NULL) { + hci_conn = allocate_connection_by_handle(handle); + if (hci_conn) { + add_connection_to_hash(&btrtl_coex, + hci_conn); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + if ((0 == link_type) || (2 == link_type)) { //sco or esco + hci_conn->type = 1; + update_profile_connection(hci_conn, + profile_sco, + TRUE); + } else + hci_conn->type = 0; + } else { + RTKBT_ERR("hci connection allocate fail"); + } + } else { + RTKBT_DBG("hci conn handle 0x%04x already existed!", + handle); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + if ((0 == link_type) || (2 == link_type)) { //sco or esco + hci_conn->type = 1; + update_profile_connection(hci_conn, profile_sco, + TRUE); + } else + hci_conn->type = 0; + } + } else if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page unsuccess end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_UNSUCCESS_END, 0, + NULL); +#else + RTKBT_INFO("Page failed"); +#endif + } +} + +static void rtk_handle_le_connection_complete_evt(u8 enhanced, u8 * p) +{ + u16 handle, interval; + u8 status; + rtk_conn_prof *hci_conn = NULL; + + status = *p++; + STREAM_TO_UINT16(handle, p); + if (!enhanced) + p += 8; /* role, address type, address */ + else + p += (8 + 12); /* plus two bluetooth addresses */ + STREAM_TO_UINT16(interval, p); + + RTKBT_INFO("LE connected, handle %04x, status 0x%02x, interval %u", + handle, status, interval); + + if (status == 0) { + if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page success end"); + rtk_notify_btoperation_to_wifi + (BT_OPCODE_PAGE_SUCCESS_END, 0, NULL); +#else + RTKBT_INFO("Page success end"); +#endif + } + + hci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (hci_conn == NULL) { + hci_conn = allocate_connection_by_handle(handle); + if (hci_conn) { + add_connection_to_hash(&btrtl_coex, + hci_conn); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + hci_conn->type = 2; + update_profile_connection(hci_conn, profile_hid, TRUE); //for coex, le is the same as hid + update_hid_active_state(handle, interval); + } else { + RTKBT_ERR("hci connection allocate fail"); + } + } else { + RTKBT_DBG("hci conn handle 0x%04x already existed!", + handle); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + hci_conn->type = 2; + update_profile_connection(hci_conn, profile_hid, TRUE); + update_hid_active_state(handle, interval); + } + } else if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page unsuccess end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_UNSUCCESS_END, 0, + NULL); +#else + RTKBT_INFO("Page failed"); +#endif + } +} + +static void rtk_handle_le_connection_update_complete_evt(u8 * p) +{ + u16 handle, interval; + /* u8 status; */ + + /* status = *p++; */ + p++; + + STREAM_TO_UINT16(handle, p); + STREAM_TO_UINT16(interval, p); + update_hid_active_state(handle, interval); +} + +static void rtk_handle_le_meta_evt(u8 * p) +{ + u8 sub_event = *p++; + switch (sub_event) { + case HCI_EV_LE_CONN_COMPLETE: + rtk_handle_le_connection_complete_evt(0, p); + break; + case HCI_EV_LE_ENHANCED_CONN_COMPLETE: + rtk_handle_le_connection_complete_evt(1, p); + break; + + case HCI_EV_LE_CONN_UPDATE_COMPLETE: + rtk_handle_le_connection_update_complete_evt(p); + break; + + default: + break; + } +} + +static u8 disconn_profile(struct rtl_hci_conn *conn, u8 pfe_index) +{ + u8 need_update = 0; + + if (!btrtl_coex.profile_refcount[pfe_index]) { + RTKBT_WARN("profile %u ref is 0", pfe_index); + return 0; + } + + btrtl_coex.profile_refcount[pfe_index]--; + RTKBT_INFO("%s: profile_ref[%u] %u", __func__, pfe_index, + btrtl_coex.profile_refcount[pfe_index]); + + if (!btrtl_coex.profile_refcount[pfe_index]) { + need_update = 1; + btrtl_coex.profile_bitmap &= ~(BIT(pfe_index)); + + /* if profile does not exist, status is meaningless */ + btrtl_coex.profile_status &= ~(BIT(pfe_index)); + rtk_check_del_timer(pfe_index); + } + + if (conn->profile_refcount[pfe_index]) + conn->profile_refcount[pfe_index]--; + else + RTKBT_INFO("%s: conn pfe ref[%u] is 0", __func__, + conn->profile_refcount[pfe_index]); + if (!conn->profile_refcount[pfe_index]) { + need_update = 1; + conn->profile_bitmap &= ~(BIT(pfe_index)); + + /* clear profile_hid_interval if need */ + if ((profile_hid == pfe_index) && + (conn->profile_bitmap & (BIT(profile_hid_interval)))) { + conn->profile_bitmap &= ~(BIT(profile_hid_interval)); + if (btrtl_coex.profile_refcount[profile_hid_interval]) + btrtl_coex.profile_refcount[profile_hid_interval]--; + } + } + + return need_update; +} + +static void disconn_acl(u16 handle, struct rtl_hci_conn *conn) +{ + struct rtl_coex_struct *coex = &btrtl_coex; + rtk_prof_info *prof_info = NULL; + struct list_head *iter = NULL, *temp = NULL; + u8 need_update = 0; + + spin_lock(&coex->spin_lock_profile); + + list_for_each_safe(iter, temp, &coex->profile_list) { + prof_info = list_entry(iter, rtk_prof_info, list); + if (handle == prof_info->handle) { + RTKBT_DBG("hci disconn, hndl %x, psm %x, dcid %x, " + "scid %x, profile %u", prof_info->handle, + prof_info->psm, prof_info->dcid, + prof_info->scid, prof_info->profile_index); + //If both scid and dcid > 0, L2cap connection is exist. + need_update |= disconn_profile(conn, + prof_info->profile_index); + if ((prof_info->flags & A2DP_MEDIA) && + (conn->profile_bitmap & BIT(profile_sink))) + need_update |= disconn_profile(conn, + profile_sink); + delete_profile_from_hash(prof_info); + } + } + if (need_update) + rtk_notify_profileinfo_to_fw(); + spin_unlock(&coex->spin_lock_profile); +} + +static void rtk_handle_disconnect_complete_evt(u8 * p) +{ + u16 handle; + u8 status; + u8 reason; + rtk_conn_prof *hci_conn = NULL; + + if (btrtl_coex.ispairing) { //for slave: connection will be disconnected if authentication fail + btrtl_coex.ispairing = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci disc complete, notify wifi pair end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_END, 0, NULL); +#else + RTKBT_INFO("hci disconnection complete"); +#endif + } + + status = *p++; + STREAM_TO_UINT16(handle, p); + reason = *p; + + RTKBT_INFO("disconn cmpl evt: status 0x%02x, handle %04x, reason 0x%02x", + status, handle, reason); + + if (status == 0) { + RTKBT_DBG("process disconn complete event."); + hci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (hci_conn) { + switch (hci_conn->type) { + case 0: + /* FIXME: If this is interrupted by l2cap rx, + * there may be deadlock on spin_lock_profile */ + disconn_acl(handle, hci_conn); + break; + + case 1: + update_profile_connection(hci_conn, profile_sco, + FALSE); + break; + + case 2: + update_profile_connection(hci_conn, profile_hid, + FALSE); + break; + + default: + break; + } + delete_connection_from_hash(hci_conn); + } else + RTKBT_ERR("hci conn handle 0x%04x not found", handle); + } +} + +static void rtk_handle_specific_evt(u8 * p) +{ + u16 subcode; + + STREAM_TO_UINT16(subcode, p); + if (subcode == HCI_VENDOR_PTA_AUTO_REPORT_EVENT) { +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi driver with autoreport data"); + rtk_notify_info_to_wifi(AUTO_REPORT, RTL_BTINFO_LEN, + (uint8_t *)p); +#else + RTKBT_INFO("auto report data"); +#endif + } +} + +static void rtk_parse_event_data(struct rtl_coex_struct *coex, + u8 *data, u16 len) +{ + u8 *p = data; + u8 event_code = *p++; + u8 total_len = *p++; + + (void)coex; + (void)&len; + + switch (event_code) { + case HCI_EV_INQUIRY_COMPLETE: + rtk_handle_inquiry_complete(); + break; + + case HCI_EV_PIN_CODE_REQ: + rtk_handle_pin_code_req(); + break; + + case HCI_EV_IO_CAPA_REQUEST: + rtk_handle_io_capa_req(); + break; + + case HCI_EV_AUTH_COMPLETE: + rtk_handle_auth_request(); + break; + + case HCI_EV_LINK_KEY_NOTIFY: + rtk_handle_link_key_notify(); + break; + + case HCI_EV_MODE_CHANGE: + rtk_handle_mode_change_evt(p); + break; + + case HCI_EV_CMD_COMPLETE: + rtk_handle_cmd_complete_evt(total_len, p); + break; + + case HCI_EV_CMD_STATUS: + rtk_handle_cmd_status_evt(p); + break; + + case HCI_EV_CONN_COMPLETE: + case HCI_EV_SYNC_CONN_COMPLETE: + rtk_handle_connection_complete_evt(p); + break; + + case HCI_EV_DISCONN_COMPLETE: + rtk_handle_disconnect_complete_evt(p); + break; + + case HCI_EV_LE_META: + rtk_handle_le_meta_evt(p); + break; + + case HCI_EV_VENDOR_SPECIFIC: + rtk_handle_specific_evt(p); + break; + + default: + break; + } +} + +const char l2_dir_str[][4] = { + "RX", "TX", +}; + +void rtl_process_l2_sig(struct rtl_l2_buff *l2) +{ + /* u8 flag; */ + u8 code; + /* u8 identifier; */ + u16 handle; + /* u16 total_len; */ + /* u16 pdu_len, channel_id; */ + /* u16 command_len; */ + u16 psm, scid, dcid, result; + /* u16 status; */ + u8 *pp = l2->data; + + STREAM_TO_UINT16(handle, pp); + /* flag = handle >> 12; */ + handle = handle & 0x0FFF; + /* STREAM_TO_UINT16(total_len, pp); */ + pp += 2; /* data total length */ + + /* STREAM_TO_UINT16(pdu_len, pp); + * STREAM_TO_UINT16(channel_id, pp); */ + pp += 4; /* l2 len and channel id */ + + code = *pp++; + switch (code) { + case L2CAP_CONN_REQ: + /* identifier = *pp++; */ + pp++; + /* STREAM_TO_UINT16(command_len, pp); */ + pp += 2; + STREAM_TO_UINT16(psm, pp); + STREAM_TO_UINT16(scid, pp); + RTKBT_DBG("%s l2cap conn req, hndl 0x%04x, PSM 0x%04x, " + "scid 0x%04x", l2_dir_str[l2->out], handle, psm, + scid); + handle_l2cap_con_req(handle, psm, scid, l2->out); + break; + + case L2CAP_CONN_RSP: + /* identifier = *pp++; */ + pp++; + /* STREAM_TO_UINT16(command_len, pp); */ + pp += 2; + STREAM_TO_UINT16(dcid, pp); + STREAM_TO_UINT16(scid, pp); + STREAM_TO_UINT16(result, pp); + /* STREAM_TO_UINT16(status, pp); */ + pp += 2; + RTKBT_DBG("%s l2cap conn rsp, hndl 0x%04x, dcid 0x%04x, " + "scid 0x%04x, result 0x%04x", l2_dir_str[l2->out], + handle, dcid, scid, result); + handle_l2cap_con_rsp(handle, dcid, scid, l2->out, result); + break; + + case L2CAP_DISCONN_REQ: + /* identifier = *pp++; */ + pp++; + /* STREAM_TO_UINT16(command_len, pp); */ + pp += 2; + STREAM_TO_UINT16(dcid, pp); + STREAM_TO_UINT16(scid, pp); + RTKBT_DBG("%s l2cap disconn req, hndl 0x%04x, dcid 0x%04x, " + "scid 0x%04x", l2_dir_str[l2->out], handle, dcid, scid); + handle_l2cap_discon_req(handle, dcid, scid, l2->out); + break; + default: + RTKBT_DBG("undesired l2 command %u", code); + break; + } +} + +static void rtl_l2_data_process(u8 *pp, u16 len, int dir) +{ + u8 code; + u8 flag; + u16 handle, pdu_len, channel_id; + /* u16 total_len; */ + struct rtl_l2_buff *l2 = NULL; + u8 *hd = pp; + + /* RTKBT_DBG("l2 sig data %p, len %u, dir %d", pp, len, dir); */ + + STREAM_TO_UINT16(handle, pp); + flag = handle >> 12; + handle = handle & 0x0FFF; + /* STREAM_TO_UINT16(total_len, pp); */ + pp += 2; /* data total length */ + + STREAM_TO_UINT16(pdu_len, pp); + STREAM_TO_UINT16(channel_id, pp); + + if (channel_id == 0x0001) { + code = *pp++; + switch (code) { + case L2CAP_CONN_REQ: + case L2CAP_CONN_RSP: + case L2CAP_DISCONN_REQ: + RTKBT_DBG("l2cap op %u, len %u, out %d", code, len, + dir); + l2 = rtl_l2_node_get(&btrtl_coex); + if (l2) { + u16 n; + n = min_t(uint, len, L2_MAX_SUBSEC_LEN); + memcpy(l2->data, hd, n); + l2->out = dir; + rtl_l2_node_to_used(&btrtl_coex, l2); + queue_delayed_work(btrtl_coex.fw_wq, + &btrtl_coex.l2_work, 0); + } else + RTKBT_ERR("%s: failed to get l2 node", + __func__); + break; + case L2CAP_DISCONN_RSP: + break; + default: + break; + } + } else { + if ((flag != 0x01) && (is_profile_connected(profile_a2dp) || + is_profile_connected(profile_pan))) + /* Do not count the continuous packets */ + packets_count(handle, channel_id, pdu_len, dir, pp); + } + return; +} + + +static void rtl_l2_work(struct work_struct *work) +{ + struct rtl_coex_struct *coex; + struct rtl_l2_buff *l2; + unsigned long flags; + + coex = container_of(work, struct rtl_coex_struct, l2_work.work); + + spin_lock_irqsave(&coex->buff_lock, flags); + while (!list_empty(&coex->l2_used_list)) { + l2 = list_entry(coex->l2_used_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + + spin_unlock_irqrestore(&coex->buff_lock, flags); + + rtl_process_l2_sig(l2); + + spin_lock_irqsave(&coex->buff_lock, flags); + + list_add_tail(&l2->list, &coex->l2_free_list); + } + spin_unlock_irqrestore(&coex->buff_lock, flags); + + return; +} + +static void rtl_ev_work(struct work_struct *work) +{ + struct rtl_coex_struct *coex; + struct rtl_hci_ev *ev; + unsigned long flags; + + coex = container_of(work, struct rtl_coex_struct, fw_work.work); + + spin_lock_irqsave(&coex->buff_lock, flags); + while (!list_empty(&coex->ev_used_list)) { + ev = list_entry(coex->ev_used_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + spin_unlock_irqrestore(&coex->buff_lock, flags); + + rtk_parse_event_data(coex, ev->data, ev->len); + + spin_lock_irqsave(&coex->buff_lock, flags); + list_add_tail(&ev->list, &coex->ev_free_list); + } + spin_unlock_irqrestore(&coex->buff_lock, flags); +} + +static inline int cmd_cmplt_filter_out(u8 *buf) +{ + u16 opcode; + + opcode = buf[3] | (buf[4] << 8); + switch (opcode) { + case HCI_OP_PERIODIC_INQ: + case HCI_OP_READ_LOCAL_VERSION: +#ifdef RTB_SOFTWARE_MAILBOX + case HCI_VENDOR_MAILBOX_CMD: +#endif + return 0; + default: + return 1; + } +} + +static inline int cmd_status_filter_out(u8 *buf) +{ + u16 opcode; + + opcode = buf[4] | (buf[5] << 8); + switch (opcode) { + case HCI_OP_INQUIRY: + case HCI_OP_CREATE_CONN: + return 0; + default: + return 1; + } +} + +int ev_filter_out(u8 *buf) +{ + switch (buf[0]) { + case HCI_EV_INQUIRY_COMPLETE: + case HCI_EV_PIN_CODE_REQ: + case HCI_EV_IO_CAPA_REQUEST: + case HCI_EV_AUTH_COMPLETE: + case HCI_EV_LINK_KEY_NOTIFY: + case HCI_EV_MODE_CHANGE: + case HCI_EV_CONN_COMPLETE: + case HCI_EV_SYNC_CONN_COMPLETE: + case HCI_EV_DISCONN_COMPLETE: + case HCI_EV_VENDOR_SPECIFIC: + return 0; + case HCI_EV_LE_META: + /* Ignore frequent but not useful events that result in + * costing too much space. + */ + switch (buf[2]) { + case HCI_EV_LE_CONN_COMPLETE: + case HCI_EV_LE_ENHANCED_CONN_COMPLETE: + case HCI_EV_LE_CONN_UPDATE_COMPLETE: + return 0; + } + return 1; + case HCI_EV_CMD_COMPLETE: + return cmd_cmplt_filter_out(buf); + case HCI_EV_CMD_STATUS: + return cmd_status_filter_out(buf); + default: + return 1; + } +} + +static void rtk_btcoex_evt_enqueue(__u8 *s, __u16 count) +{ + struct rtl_hci_ev *ev; + + if (ev_filter_out(s)) + return; + + ev = rtl_ev_node_get(&btrtl_coex); + if (!ev) { + RTKBT_ERR("%s: no free ev node.", __func__); + return; + } + + if (count > MAX_LEN_OF_HCI_EV) { + memcpy(ev->data, s, MAX_LEN_OF_HCI_EV); + ev->len = MAX_LEN_OF_HCI_EV; + } else { + memcpy(ev->data, s, count); + ev->len = count; + } + + rtl_ev_node_to_used(&btrtl_coex, ev); + + queue_delayed_work(btrtl_coex.fw_wq, &btrtl_coex.fw_work, 0); +} + +/* Context: in_interrupt() */ +void rtk_btcoex_parse_event(uint8_t *buffer, int count) +{ + struct rtl_coex_struct *coex = &btrtl_coex; + __u8 *tbuff; + __u16 elen = 0; + + /* RTKBT_DBG("%s: parse ev.", __func__); */ + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + /* RTKBT_INFO("%s: Coex is closed, ignore", __func__); */ + RTKBT_INFO("%s: Coex is closed, ignore %x, %x", + __func__, buffer[0], buffer[1]); + return; + } + + spin_lock(&coex->rxlock); + + /* coex->tbuff will be set to NULL when initializing or + * there is a complete frame or there is start of a frame */ + tbuff = coex->tbuff; + + while (count) { + int len; + + /* Start of a frame */ + if (!tbuff) { + tbuff = coex->back_buff; + coex->tbuff = NULL; + coex->elen = 0; + + coex->pkt_type = HCI_EVENT_PKT; + coex->expect = HCI_EVENT_HDR_SIZE; + } + + len = min_t(uint, coex->expect, count); + memcpy(tbuff, buffer, len); + tbuff += len; + coex->elen += len; + + count -= len; + buffer += len; + coex->expect -= len; + + if (coex->elen == HCI_EVENT_HDR_SIZE) { + /* Complete event header */ + coex->expect = + ((struct hci_event_hdr *)coex->back_buff)->plen; + if (coex->expect > HCI_MAX_EVENT_SIZE - coex->elen) { + tbuff = NULL; + coex->elen = 0; + RTKBT_ERR("tbuff room is not enough"); + break; + } + } + + if (coex->expect == 0) { + /* Complete frame */ + elen = coex->elen; + spin_unlock(&coex->rxlock); + rtk_btcoex_evt_enqueue(coex->back_buff, elen); + spin_lock(&coex->rxlock); + + tbuff = NULL; + coex->elen = 0; + } + } + + /* coex->tbuff would be non-NULL if there isn't a complete frame + * And it will be updated next time */ + coex->tbuff = tbuff; + spin_unlock(&coex->rxlock); +} + + +void rtk_btcoex_parse_l2cap_data_tx(uint8_t *buffer, int count) +{ + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_INFO("%s: Coex is closed, ignore", __func__); + return; + } + + rtl_l2_data_process(buffer, count, 1); + //u16 handle, total_len, pdu_len, channel_ID, command_len, psm, scid, + // dcid, result, status; + //u8 flag, code, identifier; + //u8 *pp = (u8 *) (skb->data); + //STREAM_TO_UINT16(handle, pp); + //flag = handle >> 12; + //handle = handle & 0x0FFF; + //STREAM_TO_UINT16(total_len, pp); + //STREAM_TO_UINT16(pdu_len, pp); + //STREAM_TO_UINT16(channel_ID, pp); + + //if (channel_ID == 0x0001) { + // code = *pp++; + // switch (code) { + // case L2CAP_CONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(psm, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("TX l2cap conn req, hndl %x, PSM %x, scid=%x", + // handle, psm, scid); + // handle_l2cap_con_req(handle, psm, scid, 1); + // break; + + // case L2CAP_CONN_RSP: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // STREAM_TO_UINT16(result, pp); + // STREAM_TO_UINT16(status, pp); + // RTKBT_DBG("TX l2cap conn rsp, hndl %x, dcid %x, " + // "scid %x, result %x", + // handle, dcid, scid, result); + // handle_l2cap_con_rsp(handle, dcid, scid, 1, result); + // break; + + // case L2CAP_DISCONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("TX l2cap disconn req, hndl %x, dcid %x, " + // "scid %x", handle, dcid, scid); + // handle_l2cap_discon_req(handle, dcid, scid, 1); + // break; + + // case L2CAP_DISCONN_RSP: + // break; + + // default: + // break; + // } + //} else { + // if ((flag != 0x01) && (is_profile_connected(profile_a2dp) || is_profile_connected(profile_pan))) //Do not count the continuous packets + // packets_count(handle, channel_ID, pdu_len, 1, pp); + //} +} + +void rtk_btcoex_parse_l2cap_data_rx(uint8_t *buffer, int count) +{ + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_INFO("%s: Coex is closed, ignore", __func__); + return; + } + + rtl_l2_data_process(buffer, count, 0); + //u16 handle, total_len, pdu_len, channel_ID, command_len, psm, scid, + // dcid, result, status; + //u8 flag, code, identifier; + //u8 *pp = urb->transfer_buffer; + //STREAM_TO_UINT16(handle, pp); + //flag = handle >> 12; + //handle = handle & 0x0FFF; + //STREAM_TO_UINT16(total_len, pp); + //STREAM_TO_UINT16(pdu_len, pp); + //STREAM_TO_UINT16(channel_ID, pp); + + //if (channel_ID == 0x0001) { + // code = *pp++; + // switch (code) { + // case L2CAP_CONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(psm, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("RX l2cap conn req, hndl %x, PSM %x, scid %x", + // handle, psm, scid); + // handle_l2cap_con_req(handle, psm, scid, 0); + // break; + + // case L2CAP_CONN_RSP: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // STREAM_TO_UINT16(result, pp); + // STREAM_TO_UINT16(status, pp); + // RTKBT_DBG("RX l2cap conn rsp, hndl %x, dcid %x, " + // "scid %x, result %x", + // handle, dcid, scid, result); + // handle_l2cap_con_rsp(handle, dcid, scid, 0, result); + // break; + + // case L2CAP_DISCONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("RX l2cap disconn req, hndl %x, dcid %x, " + // "scid %x", handle, dcid, scid); + // handle_l2cap_discon_req(handle, dcid, scid, 0); + // break; + + // case L2CAP_DISCONN_RSP: + // break; + + // default: + // break; + // } + //} else { + // if ((flag != 0x01) && (is_profile_connected(profile_a2dp) || is_profile_connected(profile_pan))) //Do not count the continuous packets + // packets_count(handle, channel_ID, pdu_len, 0, pp); + //} +} + +#ifdef RTB_SOFTWARE_MAILBOX + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void polling_bt_info(struct timer_list *unused) +#else +static void polling_bt_info(unsigned long data) +#endif +{ + uint8_t temp_cmd[1]; + RTKBT_DBG("polling timer"); + if (btrtl_coex.polling_enable) { + //temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_REPORT_CONN_SCO_INQ_INFO; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_STATUS_INFO; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 1, temp_cmd); + } + mod_timer(&btrtl_coex.polling_timer, + jiffies + msecs_to_jiffies(1000 * btrtl_coex.polling_interval)); +} + +static void rtk_handle_bt_info_control(uint8_t *p) +{ + uint8_t temp_cmd[20]; + struct rtl_btinfo_ctl *ctl = (struct rtl_btinfo_ctl*)p; + RTKBT_DBG("Received polling_enable %u, polling_time %u, " + "autoreport_enable %u", ctl->polling_enable, + ctl->polling_time, ctl->autoreport_enable); + RTKBT_DBG("coex: original polling_enable %u", + btrtl_coex.polling_enable); + + if (ctl->polling_enable && !btrtl_coex.polling_enable) { + /* setup polling timer for getting bt info from firmware */ + btrtl_coex.polling_timer.expires = + jiffies + msecs_to_jiffies(ctl->polling_time * 1000); + mod_timer(&btrtl_coex.polling_timer, + btrtl_coex.polling_timer.expires); + } + + /* Close bt info polling timer */ + if (!ctl->polling_enable && btrtl_coex.polling_enable) + del_timer(&btrtl_coex.polling_timer); + + if (btrtl_coex.autoreport != ctl->autoreport_enable) { + temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_ENABLE; + temp_cmd[1] = 1; + temp_cmd[2] = ctl->autoreport_enable; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + } + + btrtl_coex.polling_enable = ctl->polling_enable; + btrtl_coex.polling_interval = ctl->polling_time; + btrtl_coex.autoreport = ctl->autoreport_enable; + + rtk_notify_info_to_wifi(HOST_RESPONSE, 0, NULL); +} + +static void rtk_handle_bt_coex_control(uint8_t * p) +{ + uint8_t temp_cmd[20]; + uint8_t opcode, opcode_len, value, power_decrease, psd_mode, + access_type; + + opcode = *p++; + RTKBT_DBG("receive bt coex control event from wifi, op 0x%02x", opcode); + + switch (opcode) { + case BT_PATCH_VERSION_QUERY: + rtk_notify_btpatch_version_to_wifi(); + break; + + case IGNORE_WLAN_ACTIVE_CONTROL: + opcode_len = *p++; + value = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_ENABLE_IGNORE_WLAN_ACT_CMD; + temp_cmd[1] = 1; + temp_cmd[2] = value; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case LNA_CONSTRAIN_CONTROL: + opcode_len = *p++; + value = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_SET_BT_LNA_CONSTRAINT; + temp_cmd[1] = 1; + temp_cmd[2] = value; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case BT_POWER_DECREASE_CONTROL: + opcode_len = *p++; + power_decrease = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_WIFI_FORCE_TX_POWER_CMD; + temp_cmd[1] = 1; + temp_cmd[2] = power_decrease; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case BT_PSD_MODE_CONTROL: + opcode_len = *p++; + psd_mode = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_SET_BT_PSD_MODE; + temp_cmd[1] = 1; + temp_cmd[2] = psd_mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case WIFI_BW_CHNL_NOTIFY: + opcode_len = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_WIFI_CHANNEL_AND_BANDWIDTH_CMD; + temp_cmd[1] = 3; + memcpy(temp_cmd + 2, p, 3); //wifi_state, wifi_centralchannel, chnnels_btnotuse + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 5, temp_cmd); + break; + + case QUERY_BT_AFH_MAP: + opcode_len = *p++; + btrtl_coex.piconet_id = *p++; + btrtl_coex.mode = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_GET_AFH_MAP_L; + temp_cmd[1] = 2; + temp_cmd[2] = btrtl_coex.piconet_id; + temp_cmd[3] = btrtl_coex.mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 4, temp_cmd); + break; + + case BT_REGISTER_ACCESS: + opcode_len = *p++; + access_type = *p++; + if (access_type == 0) { //read + temp_cmd[0] = HCI_VENDOR_SUB_CMD_RD_REG_REQ; + temp_cmd[1] = 5; + temp_cmd[2] = *p++; + memcpy(temp_cmd + 3, p, 4); + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 7, + temp_cmd); + } else { //write + temp_cmd[0] = HCI_VENDOR_SUB_CMD_RD_REG_REQ; + temp_cmd[1] = 5; + temp_cmd[2] = *p++; + memcpy(temp_cmd + 3, p, 8); + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 11, + temp_cmd); + } + break; + + default: + break; + } +} + +static void rtk_handle_event_from_wifi(uint8_t * msg) +{ + uint8_t *p = msg; + uint8_t event_code = *p++; + uint8_t total_length; + uint8_t extension_event; + uint8_t operation; + uint16_t wifi_opcode; + uint8_t op_status; + + if (memcmp(msg, invite_rsp, sizeof(invite_rsp)) == 0) { + RTKBT_DBG("receive invite rsp from wifi, wifi is already on"); + btrtl_coex.wifi_on = 1; + rtk_notify_extension_version_to_wifi(); + } + + if (memcmp(msg, attend_req, sizeof(attend_req)) == 0) { + RTKBT_DBG("receive attend req from wifi, wifi turn on"); + btrtl_coex.wifi_on = 1; + rtkbt_coexmsg_send(attend_ack, sizeof(attend_ack)); + rtk_notify_extension_version_to_wifi(); + } + + if (memcmp(msg, wifi_leave, sizeof(wifi_leave)) == 0) { + RTKBT_DBG("receive wifi leave from wifi, wifi turn off"); + btrtl_coex.wifi_on = 0; + rtkbt_coexmsg_send(leave_ack, sizeof(leave_ack)); + if (btrtl_coex.polling_enable) { + btrtl_coex.polling_enable = 0; + del_timer(&btrtl_coex.polling_timer); + } + } + + if (memcmp(msg, leave_ack, sizeof(leave_ack)) == 0) { + RTKBT_DBG("receive leave ack from wifi"); + } + + if (event_code == 0xFE) { + total_length = *p++; + extension_event = *p++; + switch (extension_event) { + case RTK_HS_EXTENSION_EVENT_WIFI_SCAN: + operation = *p; + RTKBT_DBG("Recv WiFi scan notify event from WiFi, " + "op 0x%02x", operation); + break; + + case RTK_HS_EXTENSION_EVENT_HCI_BT_INFO_CONTROL: + rtk_handle_bt_info_control(p); + break; + + case RTK_HS_EXTENSION_EVENT_HCI_BT_COEX_CONTROL: + rtk_handle_bt_coex_control(p); + break; + + default: + break; + } + } + + if (event_code == 0x0E) { + p += 2; //length, number of complete packets + STREAM_TO_UINT16(wifi_opcode, p); + op_status = *p; + RTKBT_DBG("Recv cmd complete event from WiFi, op 0x%02x, " + "status 0x%02x", wifi_opcode, op_status); + } +} +#endif /* RTB_SOFTWARE_MAILBOX */ + +static inline void rtl_free_frags(struct rtl_coex_struct *coex) +{ + unsigned long flags; + + spin_lock_irqsave(&coex->rxlock, flags); + + coex->elen = 0; + coex->tbuff = NULL; + + spin_unlock_irqrestore(&coex->rxlock, flags); +} + +void rtk_btcoex_open(struct hci_dev *hdev) +{ + if (test_and_set_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_WARN("RTL COEX is already running."); + return; + } + + RTKBT_INFO("Open BTCOEX"); + + /* Just for test */ + //struct rtl_btinfo_ctl ctl; + + INIT_DELAYED_WORK(&btrtl_coex.fw_work, (void *)rtl_ev_work); +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL + INIT_WORK(&rtw_work, rtw_work_func); + skb_queue_head_init(&rtw_q); + rtw_coex_on = 1; +#else + INIT_DELAYED_WORK(&btrtl_coex.sock_work, + (void *)udpsocket_recv_data); +#endif +#endif /* RTB_SOFTWARE_MAILBOX */ + INIT_DELAYED_WORK(&btrtl_coex.l2_work, (void *)rtl_l2_work); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +#ifdef RTB_SOFTWARE_MAILBOX + timer_setup(&btrtl_coex.polling_timer, polling_bt_info, 0); +#endif + timer_setup(&btrtl_coex.a2dp_count_timer, count_a2dp_packet_timeout, 0); + timer_setup(&btrtl_coex.pan_count_timer, count_pan_packet_timeout, 0); + timer_setup(&btrtl_coex.hogp_count_timer, count_hogp_packet_timeout, 0); +#else +#ifdef RTB_SOFTWARE_MAILBOX + setup_timer(&btrtl_coex.polling_timer, polling_bt_info, 0); +#endif + setup_timer(&btrtl_coex.a2dp_count_timer, count_a2dp_packet_timeout, 0); + setup_timer(&btrtl_coex.pan_count_timer, count_pan_packet_timeout, 0); + setup_timer(&btrtl_coex.hogp_count_timer, count_hogp_packet_timeout, 0); +#endif + + btrtl_coex.hdev = hdev; +#ifdef RTB_SOFTWARE_MAILBOX + btrtl_coex.wifi_on = 0; +#endif + + init_profile_hash(&btrtl_coex); + init_connection_hash(&btrtl_coex); + + btrtl_coex.pkt_type = 0; + btrtl_coex.expect = 0; + btrtl_coex.elen = 0; + btrtl_coex.tbuff = NULL; + +#ifdef RTB_SOFTWARE_MAILBOX +#ifndef RTK_COEX_OVER_SYMBOL + create_udpsocket(); +#endif + rtkbt_coexmsg_send(invite_req, sizeof(invite_req)); +#endif + + /* Just for test */ + //ctl.polling_enable = 1; + //ctl.polling_time = 1; + //ctl.autoreport_enable = 1; + //rtk_handle_bt_info_control((u8 *)&ctl); +} + +void rtk_btcoex_close(void) +{ + int kk = 0; + + if (!test_and_clear_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_WARN("RTL COEX is already closed."); + return; + } + + RTKBT_INFO("Close BTCOEX"); + +#ifdef RTB_SOFTWARE_MAILBOX + /* Close coex socket */ + if (btrtl_coex.wifi_on) + rtkbt_coexmsg_send(bt_leave, sizeof(bt_leave)); +#ifdef RTK_COEX_OVER_SYMBOL + rtw_coex_on = 0; + skb_queue_purge(&rtw_q); + cancel_work_sync(&rtw_work); +#else + cancel_delayed_work_sync(&btrtl_coex.sock_work); + if (btrtl_coex.sock_open) { + btrtl_coex.sock_open = 0; + RTKBT_DBG("release udp socket"); + sock_release(btrtl_coex.udpsock); + } +#endif + + /* Delete all timers */ + if (btrtl_coex.polling_enable) { + btrtl_coex.polling_enable = 0; + del_timer_sync(&(btrtl_coex.polling_timer)); + } +#endif /* RTB_SOFTWARE_MAILBOX */ + + del_timer_sync(&btrtl_coex.a2dp_count_timer); + del_timer_sync(&btrtl_coex.pan_count_timer); + del_timer_sync(&btrtl_coex.hogp_count_timer); + + cancel_delayed_work_sync(&btrtl_coex.fw_work); + cancel_delayed_work_sync(&btrtl_coex.l2_work); + + flush_connection_hash(&btrtl_coex); + flush_profile_hash(&btrtl_coex); + btrtl_coex.profile_bitmap = 0; + btrtl_coex.profile_status = 0; + for (kk = 0; kk < 8; kk++) + btrtl_coex.profile_refcount[kk] = 0; + + rtl_free_frags(&btrtl_coex); + RTKBT_DBG("-x"); +} + +void rtk_btcoex_probe(struct hci_dev *hdev) +{ + btrtl_coex.hdev = hdev; + spin_lock_init(&btrtl_coex.spin_lock_sock); + spin_lock_init(&btrtl_coex.spin_lock_profile); +} + +void rtk_btcoex_init(void) +{ + RTKBT_DBG("%s: version: %s", __func__, RTK_VERSION); + RTKBT_DBG("create workqueue"); +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL + RTKBT_INFO("Coex over Symbol"); + rtw_wq = create_workqueue("btcoexwork"); + skb_queue_head_init(&rtw_q); +#else + RTKBT_INFO("Coex over UDP"); + btrtl_coex.sock_wq = create_workqueue("btudpwork"); +#endif +#endif /* RTB_SOFTWARE_MAILBOX */ + btrtl_coex.fw_wq = create_workqueue("btfwwork"); + rtl_alloc_buff(&btrtl_coex); + spin_lock_init(&btrtl_coex.rxlock); +} + +void rtk_btcoex_exit(void) +{ + RTKBT_DBG("%s: destroy workqueue", __func__); +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL + flush_workqueue(rtw_wq); + destroy_workqueue(rtw_wq); +#else + flush_workqueue(btrtl_coex.sock_wq); + destroy_workqueue(btrtl_coex.sock_wq); +#endif +#endif + flush_workqueue(btrtl_coex.fw_wq); + destroy_workqueue(btrtl_coex.fw_wq); + rtl_free_buff(&btrtl_coex); +} diff --git a/drivers/bluetooth/rtk_coex.h b/drivers/bluetooth/rtk_coex.h new file mode 100644 index 0000000000000..5b0ec85f0c60e --- /dev/null +++ b/drivers/bluetooth/rtk_coex.h @@ -0,0 +1,373 @@ +/* +* +* Realtek Bluetooth USB driver +* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +* +*/ +#include +#include + +/*********************************** +** Realtek - For coexistence ** +***********************************/ +#define BTRTL_HCIUSB 0 +#define BTRTL_HCIUART 1 + +#define BTRTL_HCI_IF BTRTL_HCIUSB + +#define TRUE 1 +#define FALSE 0 + +#define CONNECT_PORT 30001 +#define CONNECT_PORT_WIFI 30000 + +#define invite_req "INVITE_REQ" +#define invite_rsp "INVITE_RSP" +#define attend_req "ATTEND_REQ" +#define attend_ack "ATTEND_ACK" +#define wifi_leave "WIFI_LEAVE" +#define leave_ack "LEAVE_ACK" +#define bt_leave "BT_LEAVE" + +#define HCI_OP_PERIODIC_INQ 0x0403 +#define HCI_EV_LE_META 0x3e +#define HCI_EV_LE_CONN_COMPLETE 0x01 +#define HCI_EV_LE_CONN_UPDATE_COMPLETE 0x03 +#define HCI_EV_LE_ENHANCED_CONN_COMPLETE 0x0a + +//vendor cmd to fw +#define HCI_VENDOR_ENABLE_PROFILE_REPORT_COMMAND 0xfc18 +#define HCI_VENDOR_SET_PROFILE_REPORT_COMMAND 0xfc19 +#define HCI_VENDOR_MAILBOX_CMD 0xfc8f +#define HCI_VENDOR_SET_BITPOOL 0xfc51 + +//subcmd to fw +#define HCI_VENDOR_SUB_CMD_WIFI_CHANNEL_AND_BANDWIDTH_CMD 0x11 +#define HCI_VENDOR_SUB_CMD_WIFI_FORCE_TX_POWER_CMD 0x17 +#define HCI_VENDOR_SUB_CMD_BT_ENABLE_IGNORE_WLAN_ACT_CMD 0x1B +#define HCI_VENDOR_SUB_CMD_BT_REPORT_CONN_SCO_INQ_INFO 0x23 +#define HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_STATUS_INFO 0x27 +#define HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_ENABLE 0x28 +#define HCI_VENDOR_SUB_CMD_BT_SET_TXRETRY_REPORT_PARAM 0x29 +#define HCI_VENDOR_SUB_CMD_BT_SET_PTATABLE 0x2A +#define HCI_VENDOR_SUB_CMD_SET_BT_PSD_MODE 0x31 +#define HCI_VENDOR_SUB_CMD_SET_BT_LNA_CONSTRAINT 0x32 +#define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_L 0x40 +#define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_M 0x41 +#define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_H 0x42 +#define HCI_VENDOR_SUB_CMD_RD_REG_REQ 0x43 +#define HCI_VENDOR_SUB_CMD_WR_REG_REQ 0x44 + +#define HCI_EV_VENDOR_SPECIFIC 0xff + +//sub event from fw start +#define HCI_VENDOR_PTA_REPORT_EVENT 0x24 +#define HCI_VENDOR_PTA_AUTO_REPORT_EVENT 0x25 + +//vendor cmd to wifi driver +#define HCI_GRP_VENDOR_SPECIFIC (0x3f << 10) +#define HCI_OP_HCI_EXTENSION_VERSION_NOTIFY (0x0100 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_BT_OPERATION_NOTIFY (0x0102 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_INFO_NOTIFY (0x0106 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_COEX_NOTIFY (0x0107 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_PATCH_VER_NOTIFY (0x0108 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_AFH_MAP_NOTIFY (0x0109 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_REGISTER_VALUE_NOTIFY (0x010a | HCI_GRP_VENDOR_SPECIFIC) + +//bt info reason to wifi +#define HOST_RESPONSE 0 //Host response when receive the BT Info Control Event +#define POLLING_RESPONSE 1 //The BT Info response for polling by BT firmware. +#define AUTO_REPORT 2 //BT auto report by BT firmware. +#define STACK_REPORT_WHILE_DEVICE_D2 3 //Stack report when BT firmware is under power save state(ex:D2) + +// vendor event from wifi +#define RTK_HS_EXTENSION_EVENT_WIFI_SCAN 0x01 +#define RTK_HS_EXTENSION_EVENT_RADIO_STATUS_NOTIFY 0x02 +#define RTK_HS_EXTENSION_EVENT_HCI_BT_INFO_CONTROL 0x03 +#define RTK_HS_EXTENSION_EVENT_HCI_BT_COEX_CONTROL 0x04 + +//op code from wifi +#define BT_PATCH_VERSION_QUERY 0x00 +#define IGNORE_WLAN_ACTIVE_CONTROL 0x01 +#define LNA_CONSTRAIN_CONTROL 0x02 +#define BT_POWER_DECREASE_CONTROL 0x03 +#define BT_PSD_MODE_CONTROL 0x04 +#define WIFI_BW_CHNL_NOTIFY 0x05 +#define QUERY_BT_AFH_MAP 0x06 +#define BT_REGISTER_ACCESS 0x07 + +//bt operation to notify +#define BT_OPCODE_NONE 0 +#define BT_OPCODE_INQUIRY_START 1 +#define BT_OPCODE_INQUIRY_END 2 +#define BT_OPCODE_PAGE_START 3 +#define BT_OPCODE_PAGE_SUCCESS_END 4 +#define BT_OPCODE_PAGE_UNSUCCESS_END 5 +#define BT_OPCODE_PAIR_START 6 +#define BT_OPCODE_PAIR_END 7 +#define BT_OPCODE_ENABLE_BT 8 +#define BT_OPCODE_DISABLE_BT 9 + +#define HCI_EXTENSION_VERSION 0x0004 +#define HCI_CMD_PREAMBLE_SIZE 3 +#define PAN_PACKET_COUNT 5 + +#define STREAM_TO_UINT16(u16, p) {u16 = ((uint16_t)(*(p)) + (((uint16_t)(*((p) + 1))) << 8)); (p) += 2;} +#define UINT16_TO_STREAM(p, u16) {*(p)++ = (uint8_t)(u16); *(p)++ = (uint8_t)((u16) >> 8);} + +#define PSM_SDP 0x0001 +#define PSM_RFCOMM 0x0003 +#define PSM_PAN 0x000F +#define PSM_HID 0x0011 +#define PSM_HID_INT 0x0013 +#define PSM_AVCTP 0x0017 +#define PSM_AVDTP 0x0019 +#define PSM_FTP 0x1001 +#define PSM_BIP 0x1003 +#define PSM_OPP 0x1015 +//--add more if needed--// + +enum { + profile_sco = 0, + profile_hid = 1, + profile_a2dp = 2, + profile_pan = 3, + profile_hid_interval = 4, + profile_hogp = 5, + profile_voice = 6, + profile_sink = 7, + profile_max = 8 +}; + +#define A2DP_SIGNAL 0x01 +#define A2DP_MEDIA 0x02 +//profile info data +typedef struct { + struct list_head list; + uint16_t handle; + uint16_t psm; + uint16_t dcid; + uint16_t scid; + uint8_t profile_index; + uint8_t flags; +} rtk_prof_info, *prtk_prof_info; + +//profile info for each connection +typedef struct rtl_hci_conn { + struct list_head list; + uint16_t handle; + uint8_t type; // 0:l2cap, 1:sco/esco, 2:le + uint8_t profile_bitmap; + int8_t profile_refcount[8]; +} rtk_conn_prof, *prtk_conn_prof; + +#ifdef RTB_SOFTWARE_MAILBOX + +struct rtl_btinfo { + u8 cmd; + u8 len; + u8 data[6]; +}; +#define RTL_BTINFO_LEN (sizeof(struct rtl_btinfo)) +/* typedef struct { + * uint8_t cmd_index; + * uint8_t cmd_length; + * uint8_t link_status; + * uint8_t retry_cnt; + * uint8_t rssi; + * uint8_t mailbox_info; + * uint16_t acl_throughput; + * } hci_linkstatus_report; */ + +typedef struct { + uint8_t type; + uint32_t offset; + uint32_t value; +} hci_mailbox_register; + +struct rtl_btinfo_ctl { + uint8_t polling_enable; + uint8_t polling_time; + uint8_t autoreport_enable; +}; +#endif /* RTB_SOFTWARE_MAILBOX */ + +#define MAX_LEN_OF_HCI_EV 32 +#define NUM_RTL_HCI_EV 32 +struct rtl_hci_ev { + __u8 data[MAX_LEN_OF_HCI_EV]; + __u16 len; + struct list_head list; +}; + +#define L2_MAX_SUBSEC_LEN 128 +#define L2_MAX_PKTS 16 +struct rtl_l2_buff { + __u8 data[L2_MAX_SUBSEC_LEN]; + __u16 len; + __u16 out; + struct list_head list; +}; + +struct rtl_coex_struct { + struct list_head conn_hash; //hash for connections + struct list_head profile_list; //hash for profile info + struct hci_dev *hdev; +#ifdef RTB_SOFTWARE_MAILBOX + struct socket *udpsock; + struct sockaddr_in addr; + struct sockaddr_in wifi_addr; + struct timer_list polling_timer; +#endif + struct timer_list a2dp_count_timer; + struct timer_list pan_count_timer; + struct timer_list hogp_count_timer; +#ifdef RTB_SOFTWARE_MAILBOX + struct workqueue_struct *sock_wq; + struct delayed_work sock_work; +#endif + struct workqueue_struct *fw_wq; + struct delayed_work fw_work; + struct delayed_work l2_work; +#ifdef RTB_SOFTWARE_MAILBOX + struct sock *sk; +#endif + struct urb *urb; + spinlock_t spin_lock_sock; + spinlock_t spin_lock_profile; + uint32_t a2dp_packet_count; + uint32_t pan_packet_count; + uint32_t hogp_packet_count; + uint32_t voice_packet_count; + uint8_t profile_bitmap; + uint8_t profile_status; + int8_t profile_refcount[8]; + uint8_t ispairing; + uint8_t isinquirying; + uint8_t ispaging; +#ifdef RTB_SOFTWARE_MAILBOX + uint8_t wifi_state; + uint8_t autoreport; + uint8_t polling_enable; + uint8_t polling_interval; + uint8_t piconet_id; + uint8_t mode; + uint8_t afh_map[10]; +#endif + uint16_t hci_reversion; + uint16_t lmp_subversion; +#ifdef RTB_SOFTWARE_MAILBOX + uint8_t wifi_on; + uint8_t sock_open; +#endif + unsigned long cmd_last_tx; + + /* hci ev buff */ + struct list_head ev_used_list; + struct list_head ev_free_list; + + spinlock_t rxlock; + __u8 pkt_type; + __u16 expect; + __u8 *tbuff; + __u16 elen; + __u8 back_buff[HCI_MAX_EVENT_SIZE]; + + /* l2cap rx buff */ + struct list_head l2_used_list; + struct list_head l2_free_list; + + /* buff addr and size */ + spinlock_t buff_lock; + unsigned long pages_addr; + unsigned long buff_size; + +#define RTL_COEX_RUNNING (1 << 0) + unsigned long flags; + +}; + +#ifdef __LITTLE_ENDIAN +struct sbc_frame_hdr { + uint8_t syncword:8; /* Sync word */ + uint8_t subbands:1; /* Subbands */ + uint8_t allocation_method:1; /* Allocation method */ + uint8_t channel_mode:2; /* Channel mode */ + uint8_t blocks:2; /* Blocks */ + uint8_t sampling_frequency:2; /* Sampling frequency */ + uint8_t bitpool:8; /* Bitpool */ + uint8_t crc_check:8; /* CRC check */ +} __attribute__ ((packed)); + +/* NOTE: The code is copied from pa. + * only the bit field in 8-bit is affected by endian, not the 16-bit or 32-bit. + * why? + */ +struct rtp_header { + unsigned cc:4; + unsigned x:1; + unsigned p:1; + unsigned v:2; + + unsigned pt:7; + unsigned m:1; + + uint16_t sequence_number; + uint32_t timestamp; + uint32_t ssrc; + uint32_t csrc[0]; +} __attribute__ ((packed)); + +#else +/* big endian */ +struct sbc_frame_hdr { + uint8_t syncword:8; /* Sync word */ + uint8_t sampling_frequency:2; /* Sampling frequency */ + uint8_t blocks:2; /* Blocks */ + uint8_t channel_mode:2; /* Channel mode */ + uint8_t allocation_method:1; /* Allocation method */ + uint8_t subbands:1; /* Subbands */ + uint8_t bitpool:8; /* Bitpool */ + uint8_t crc_check:8; /* CRC check */ +} __attribute__ ((packed)); + +struct rtp_header { + unsigned v:2; + unsigned p:1; + unsigned x:1; + unsigned cc:4; + + unsigned m:1; + unsigned pt:7; + + uint16_t sequence_number; + uint32_t timestamp; + uint32_t ssrc; + uint32_t csrc[0]; +} __attribute__ ((packed)); +#endif /* __LITTLE_ENDIAN */ + +void rtk_btcoex_parse_event(uint8_t *buffer, int count); +void rtk_btcoex_parse_cmd(uint8_t *buffer, int count); +void rtk_btcoex_parse_l2cap_data_tx(uint8_t *buffer, int count); +void rtk_btcoex_parse_l2cap_data_rx(uint8_t *buffer, int count); + +void rtk_btcoex_open(struct hci_dev *hdev); +void rtk_btcoex_close(void); +void rtk_btcoex_probe(struct hci_dev *hdev); +void rtk_btcoex_init(void); +void rtk_btcoex_exit(void); diff --git a/drivers/bluetooth/rtk_misc.c b/drivers/bluetooth/rtk_misc.c new file mode 100644 index 0000000000000..54684de24212e --- /dev/null +++ b/drivers/bluetooth/rtk_misc.c @@ -0,0 +1,2108 @@ +/* + * + * Realtek Bluetooth USB download firmware driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32) +#include +#endif + +#include +#include +#include +#include +#include + +#include "rtk_misc.h" + +#include +#include +#define BDADDR_STRING_LEN 17 +#define BDADDR_FILE "/opt/bdaddr" + +struct cfg_list_item { + struct list_head list; + u16 offset; + u8 len; + u8 data[0]; +}; + +static struct list_head list_configs; + +#define EXTRA_CONFIG_FILE "/opt/rtk_btconfig.txt" +static struct list_head list_extracfgs; + +#define CMD_CMP_EVT 0x0e +#define PKT_LEN 300 +#define MSG_TO 1000 //us +#define PATCH_SEG_MAX 252 +#define DATA_END 0x80 +#define DOWNLOAD_OPCODE 0xfc20 +/* This command is used only for TV patch + * if host is going to suspend state, it should send this command to + * Controller. Controller will scan the special advertising packet + * which indicates Controller to wake up host */ +#define STARTSCAN_OPCODE 0xfc28 +#define TRUE 1 +#define FALSE 0 +#define CMD_HDR_LEN sizeof(struct hci_command_hdr) +#define EVT_HDR_LEN sizeof(struct hci_event_hdr) +#define CMD_CMP_LEN sizeof(struct hci_ev_cmd_complete) + +#define HCI_CMD_READ_BD_ADDR 0x1009 +#define HCI_VENDOR_CHANGE_BDRATE 0xfc17 +#define HCI_VENDOR_READ_RTK_ROM_VERISION 0xfc6d +#define HCI_VENDOR_READ_LMP_VERISION 0x1001 + +#define ROM_LMP_NONE 0x0000 +#define ROM_LMP_8723a 0x1200 +#define ROM_LMP_8723b 0x8723 +#define ROM_LMP_8821a 0X8821 +#define ROM_LMP_8761a 0X8761 +#define ROM_LMP_8822b 0X8822 +#define ROM_LMP_8852a 0x8852 + +struct rtk_eversion_evt { + uint8_t status; + uint8_t version; +} __attribute__ ((packed)); + +struct rtk_epatch_entry { + uint16_t chipID; + uint16_t patch_length; + uint32_t start_offset; +} __attribute__ ((packed)); + +struct rtk_epatch { + uint8_t signature[8]; + uint32_t fw_version; + uint16_t number_of_total_patch; + struct rtk_epatch_entry entry[0]; +} __attribute__ ((packed)); + +struct rtk_extension_entry { + uint8_t opcode; + uint8_t length; + uint8_t *data; +} __attribute__ ((packed)); + +//signature: Realtech +const uint8_t RTK_EPATCH_SIGNATURE[8] = + { 0x52, 0x65, 0x61, 0x6C, 0x74, 0x65, 0x63, 0x68 }; +//Extension Section IGNATURE:0x77FD0451 +const uint8_t Extension_Section_SIGNATURE[4] = { 0x51, 0x04, 0xFD, 0x77 }; + +uint16_t project_id[] = { + ROM_LMP_8723a, + ROM_LMP_8723b, + ROM_LMP_8821a, + ROM_LMP_8761a, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8822b, + ROM_LMP_8723b, /* RTL8723DU */ + ROM_LMP_8821a, /* RTL8821CU */ + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8822b, /* RTL8822CU */ + ROM_LMP_8761a, /* index 14 for 8761BU */ + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8852a, /* index 18 for 8852AU */ + ROM_LMP_8723b, /* index 19 for 8723FU */ + ROM_LMP_8852a, /* index 20 for 8852BU */ + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8852a, /* index 25 for 8852CU */ +}; + +enum rtk_endpoit { + CTRL_EP = 0, + INTR_EP = 1, + BULK_EP = 2, + ISOC_EP = 3 +}; + +/* software id */ +#define RTLPREVIOUS 0x00 +#define RTL8822BU 0x70 +#define RTL8723DU 0x71 +#define RTL8821CU 0x72 +#define RTL8822CU 0x73 +#define RTL8761BU 0x74 +#define RTL8852AU 0x75 +#define RTL8723FU 0x76 +#define RTL8852BU 0x77 +#define RTL8852CU 0x78 + +typedef struct { + uint16_t prod_id; + uint16_t lmp_sub; + char * mp_patch_name; + char * patch_name; + char * config_name; + u8 chip_type; +} patch_info; + +typedef struct { + struct list_head list_node; + struct usb_interface *intf; + struct usb_device *udev; + patch_info *patch_entry; +} dev_data; + +typedef struct { + dev_data *dev_entry; + int pipe_in, pipe_out; + uint8_t *send_pkt; + uint8_t *rcv_pkt; + struct hci_command_hdr *cmd_hdr; + struct hci_event_hdr *evt_hdr; + struct hci_ev_cmd_complete *cmd_cmp; + uint8_t *req_para, *rsp_para; + uint8_t *fw_data; + int pkt_len, fw_len; +} xchange_data; + +typedef struct { + uint8_t index; + uint8_t data[PATCH_SEG_MAX]; +} __attribute__ ((packed)) download_cp; + +typedef struct { + uint8_t status; + uint8_t index; +} __attribute__ ((packed)) download_rp; + +#define RTK_VENDOR_CONFIG_MAGIC 0x8723ab55 +const u8 cfg_magic[4] = { 0x55, 0xab, 0x23, 0x87 }; +struct rtk_bt_vendor_config_entry { + uint16_t offset; + uint8_t entry_len; + uint8_t entry_data[0]; +} __attribute__ ((packed)); + +struct rtk_bt_vendor_config { + uint32_t signature; + uint16_t data_len; + struct rtk_bt_vendor_config_entry entry[0]; +} __attribute__ ((packed)); +#define BT_CONFIG_HDRLEN sizeof(struct rtk_bt_vendor_config) + +static uint8_t gEVersion = 0xFF; + +static dev_data *dev_data_find(struct usb_interface *intf); +static patch_info *get_patch_entry(struct usb_device *udev); +static int load_firmware(dev_data * dev_entry, uint8_t ** buff); +static void init_xdata(xchange_data * xdata, dev_data * dev_entry); +static int check_fw_version(xchange_data * xdata); +static int download_data(xchange_data * xdata); +static int send_hci_cmd(xchange_data * xdata); +static int rcv_hci_evt(xchange_data * xdata); +static uint8_t rtk_get_eversion(dev_data * dev_entry); + +static patch_info fw_patch_table[] = { +/* { pid, lmp_sub, mp_fw_name, fw_name, config_name, chip_type } */ + {0x1724, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* RTL8723A */ + {0x8723, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE */ + {0xA723, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE for LI */ + {0x0723, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE */ + {0x3394, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE for Azurewave */ + + {0x0724, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + {0x8725, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + {0x872A, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + {0x872B, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + + {0xb720, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BU */ + {0xb72A, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BU */ + {0xb728, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for LC */ + {0xb723, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb72B, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb001, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for HP */ + {0xb002, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb003, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb004, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb005, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + + {0x3410, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Azurewave */ + {0x3416, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Azurewave */ + {0x3459, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Azurewave */ + {0xE085, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Foxconn */ + {0xE08B, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Foxconn */ + {0xE09E, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Foxconn */ + + {0xA761, 0x8761, "mp_rtl8761a_fw", "rtl8761au_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU only */ + {0x818B, 0x8761, "mp_rtl8761a_fw", "rtl8761aw_fw", "rtl8761aw_config", RTLPREVIOUS}, /* RTL8761AW + 8192EU */ + {0x818C, 0x8761, "mp_rtl8761a_fw", "rtl8761aw_fw", "rtl8761aw_config", RTLPREVIOUS}, /* RTL8761AW + 8192EU */ + {0x8760, 0x8761, "mp_rtl8761a_fw", "rtl8761au8192ee_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8192EE */ + {0xB761, 0x8761, "mp_rtl8761a_fw", "rtl8761au_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AUV only */ + {0x8761, 0x8761, "mp_rtl8761a_fw", "rtl8761au8192ee_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8192EE for LI */ + {0x8A60, 0x8761, "mp_rtl8761a_fw", "rtl8761au8812ae_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8812AE */ + {0x3527, 0x8761, "mp_rtl8761a_fw", "rtl8761au8192ee_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8814AE */ + + {0x8821, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x0821, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x0823, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AU */ + {0x3414, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x3458, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x3461, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x3462, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + + {0xb82c, 0x8822, "mp_rtl8822bu_fw", "rtl8822bu_fw", "rtl8822bu_config", RTL8822BU}, /* RTL8822BU */ + + {0xd720, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0xd723, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0xd739, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0xb009, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0x0231, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU for LiteOn */ + + {0xb820, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CU */ + {0xc820, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CU */ + {0xc821, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc823, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc824, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc825, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc827, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc025, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc024, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc030, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xb00a, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xb00e, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc032, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0x4000, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for LiteOn */ + {0x4001, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for LiteOn */ + {0x3529, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3530, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3532, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3533, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3538, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3539, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3558, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3559, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3581, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3540, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0x3541, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for GSD */ + {0x3543, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for GSD */ + {0xc80c, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CUH */ + + {0xc82c, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CU */ + {0xc82e, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CU */ + {0xc81d, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CU */ + {0xd820, 0x8822, "mp_rtl8821du_fw", "rtl8821du_fw", "rtl8821du_config", RTL8822CU}, /* RTL8821DU */ + + {0xc822, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc82b, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xb00c, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xb00d, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc123, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc126, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc127, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc128, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc129, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc131, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc136, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3549, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for Azurewave */ + {0x3548, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for Azurewave */ + {0xc125, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x4005, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for LiteOn */ + {0x3051, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for LiteOn */ + {0x18ef, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x161f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3053, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc547, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3553, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3555, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc82f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE-VS */ + {0xc02f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE-VS */ + {0xc03f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE-VS */ + + {0x8771, 0x8761, "mp_rtl8761b_fw", "rtl8761bu_fw", "rtl8761bu_config", RTL8761BU}, /* RTL8761BU only */ + {0xa725, 0x8761, "mp_rtl8761b_fw", "rtl8725au_fw", "rtl8725au_config", RTL8761BU}, /* RTL8725AU */ + {0xa72A, 0x8761, "mp_rtl8761b_fw", "rtl8725au_fw", "rtl8725au_config", RTL8761BU}, /* RTL8725AU BT only */ + + {0x885a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AU */ + {0x8852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xa852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x2852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x385a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x1852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x4852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x4006, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3561, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3562, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x588a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x589a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x590a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc125, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xe852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + //{0xb852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc549, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc127, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3565, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + + {0xb733, 0x8723, "mp_rtl8723fu_fw", "rtl8723fu_fw", "rtl8723fu_config", RTL8723FU}, /* RTL8723FU */ + {0xb73a, 0x8723, "mp_rtl8723fu_fw", "rtl8723fu_fw", "rtl8723fu_config", RTL8723FU}, /* RTL8723FU */ + {0xf72b, 0x8723, "mp_rtl8723fu_fw", "rtl8723fu_fw", "rtl8723fu_config", RTL8723FU}, /* RTL8723FU */ + + {0x8851, 0x8852, "mp_rtl8851au_fw", "rtl8851au_fw", "rtl8851au_config", RTL8852BU}, /* RTL8851AU */ + {0xa85b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BU */ + {0xb852, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BU */ + {0xb85b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb85c, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x3571, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x3570, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x3572, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x4b06, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x885b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x886b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x887b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xc559, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb052, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb152, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb252, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x4853, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x1670, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + + {0xc85a, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CU */ + {0x0852, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x5852, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0xc85c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x885c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x886c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x887c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x4007, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + +/* NOTE: must append patch entries above the null entry */ + {0, 0, NULL, NULL, NULL, 0} +}; + +static LIST_HEAD(dev_data_list); + +void util_hexdump(const u8 *buf, size_t len) +{ + static const char hexdigits[] = "0123456789abcdef"; + char str[16 * 3]; + size_t i; + + if (!buf || !len) + return; + + for (i = 0; i < len; i++) { + str[((i % 16) * 3)] = hexdigits[buf[i] >> 4]; + str[((i % 16) * 3) + 1] = hexdigits[buf[i] & 0xf]; + str[((i % 16) * 3) + 2] = ' '; + if ((i + 1) % 16 == 0) { + str[16 * 3 - 1] = '\0'; + RTKBT_DBG("%s", str); + } + } + + if (i % 16 > 0) { + str[(i % 16) * 3 - 1] = '\0'; + RTKBT_DBG("%s", str); + } +} + +#if defined RTKBT_SWITCH_PATCH || defined RTKBT_TV_POWERON_WHITELIST +int __rtk_send_hci_cmd(struct usb_device *udev, u8 *buf, u16 size) +{ + int result; + unsigned int pipe = usb_sndctrlpipe(udev, 0); + + result = usb_control_msg(udev, pipe, 0, USB_TYPE_CLASS, 0, 0, + buf, size, 1000); /* 1000 msecs */ + + if (result < 0) + RTKBT_ERR("%s: Couldn't send hci cmd, err %d", + __func__, result); + + return result; +} + +int __rtk_recv_hci_evt(struct usb_device *udev, u8 *buf, u8 len, u16 opcode) +{ + int recv_length = 0; + int result = 0; + int i; + unsigned int pipe = usb_rcvintpipe(udev, 1); + struct hci_event_hdr *hdr; + struct hci_ev_cmd_complete *cmd_cmpl; + + if (len < sizeof(*hdr) + sizeof(*cmd_cmpl)) { + RTKBT_ERR("%s: Invalid buf length %u", __func__, len); + return -1; + } + + while (1) { + for (i = 0; i < 5; i++) { + result = usb_interrupt_msg(udev, pipe, + (void *)buf, PKT_LEN, + &recv_length, MSG_TO); + if (result >= 0) + break; + } + + if (result < 0) { + RTKBT_ERR("%s; Couldn't receive HCI event, err %d", + __func__, result); + return result; + } + + /* Ignore the event which is not command complete event */ + if (recv_length < sizeof(*hdr) + sizeof(*cmd_cmpl)) + continue; + + hdr = (struct hci_event_hdr *)buf; + cmd_cmpl = (struct hci_ev_cmd_complete *)(buf + sizeof(*hdr)); + if (hdr->evt == 0x0e) { + if (opcode == cmd_cmpl->opcode) + return recv_length; + } + } +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0) +static inline struct inode *file_inode(const struct file *f) +{ + return f->f_path.dentry->d_inode; +} +#endif + +static int config_lists_init(void) +{ + INIT_LIST_HEAD(&list_configs); + INIT_LIST_HEAD(&list_extracfgs); + + return 0; +} + +static void config_lists_free(void) +{ + struct list_head *iter; + struct list_head *tmp; + struct list_head *head; + struct cfg_list_item *n; + + if (!list_empty(&list_extracfgs)) + list_splice_tail(&list_extracfgs, &list_configs); + head = &list_configs; + list_for_each_safe(iter, tmp, head) { + n = list_entry(iter, struct cfg_list_item, list); + if (n) { + list_del(&n->list); + kfree(n); + } + } + + INIT_LIST_HEAD(&list_configs); + INIT_LIST_HEAD(&list_extracfgs); +} + +static void line_process(char *buf, int len) +{ + char *argv[32]; + int argc = 0; + unsigned long offset; + u8 l; + u8 i = 0; + char *ptr = buf; + char *head = buf; + struct cfg_list_item *item; + + while ((ptr = strsep(&head, ", \t")) != NULL) { + if (!ptr[0]) + continue; + argv[argc++] = ptr; + if (argc >= 32) { + RTKBT_WARN("%s: Config item is too long", __func__); + break; + } + } + + if (argc < 4) { + RTKBT_WARN("%s: Invalid Config item, ignore", __func__); + return; + } + + offset = simple_strtoul(argv[0], NULL, 16); + offset = offset | (simple_strtoul(argv[1], NULL, 16) << 8); + l = (u8)simple_strtoul(argv[2], NULL, 16); + if (l != (u8)(argc - 3)) { + RTKBT_ERR("invalid len %u", l); + return; + } + + item = kzalloc(sizeof(*item) + l, GFP_KERNEL); + if (!item) { + RTKBT_WARN("%s: Cannot alloc mem for item, %04lx, %u", __func__, + offset, l); + return; + } + + item->offset = (u16)offset; + item->len = l; + for (i = 0; i < l; i++) + item->data[i] = (u8)simple_strtoul(argv[3 + i], NULL, 16); + list_add_tail(&item->list, &list_extracfgs); +} + +static void config_process(u8 *buff, int len) +{ + char *head = (void *)buff; + char *ptr = (void *)buff; + + while ((ptr = strsep(&head, "\n\r")) != NULL) { + if (!ptr[0]) + continue; + line_process(ptr, strlen(ptr) + 1); + } +} + +static void config_file_proc(const char *path) +{ + int size; + int rc; + struct file *file; + u8 tbuf[256]; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + loff_t pos = 0; +#endif + + file = filp_open(path, O_RDONLY, 0); + if (IS_ERR(file)) + return; + + if (!S_ISREG(file_inode(file)->i_mode)) + return; + size = i_size_read(file_inode(file)); + if (size <= 0) + return; + + memset(tbuf, 0, sizeof(tbuf)); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + rc = kernel_read(file, tbuf, size, &pos); +#else + rc = kernel_read(file, 0, tbuf, size); +#endif + fput(file); + if (rc != size) { + if (rc >= 0) + rc = -EIO; + return; + } + + tbuf[rc++] = '\n'; + tbuf[rc++] = '\0'; + config_process(tbuf, rc); +} + +int patch_add(struct usb_interface *intf) +{ + dev_data *dev_entry; + struct usb_device *udev; + + RTKBT_DBG("patch_add"); + dev_entry = dev_data_find(intf); + if (NULL != dev_entry) { + return -1; + } + + udev = interface_to_usbdev(intf); +#ifdef BTUSB_RPM + RTKBT_DBG("auto suspend is enabled"); + usb_enable_autosuspend(udev); + pm_runtime_set_autosuspend_delay(&(udev->dev), 2000); +#else + RTKBT_DBG("auto suspend is disabled"); + usb_disable_autosuspend(udev); +#endif + + dev_entry = kzalloc(sizeof(dev_data), GFP_KERNEL); + dev_entry->intf = intf; + dev_entry->udev = udev; + dev_entry->patch_entry = get_patch_entry(udev); + if (NULL == dev_entry->patch_entry) { + kfree(dev_entry); + return -1; + } + list_add(&dev_entry->list_node, &dev_data_list); + + /* Should reset the gEVersion to 0xff, otherwise the stored gEVersion + * would cause rtk_get_eversion() returning previous gEVersion if + * change to different ECO chip. + * This would cause downloading wrong patch, and the controller can't + * work. */ + RTKBT_DBG("%s: Reset gEVersion to 0xff", __func__); + gEVersion = 0xff; + + return 0; +} + +void patch_remove(struct usb_interface *intf) +{ + dev_data *dev_entry; + struct usb_device *udev; + + udev = interface_to_usbdev(intf); +#ifdef BTUSB_RPM + usb_disable_autosuspend(udev); +#endif + + dev_entry = dev_data_find(intf); + if (NULL == dev_entry) { + return; + } + + RTKBT_DBG("patch_remove"); + list_del(&dev_entry->list_node); + kfree(dev_entry); +} + +static int send_reset_command(xchange_data *xdata) +{ + int ret_val; + + RTKBT_DBG("HCI reset."); + + xdata->cmd_hdr->opcode = cpu_to_le16(HCI_OP_RESET); + xdata->cmd_hdr->plen = 0; + xdata->pkt_len = CMD_HDR_LEN; + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + RTKBT_ERR("failed to send hci cmd."); + return ret_val; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + RTKBT_ERR("failed to recv hci event."); + return ret_val; + } + + return 0; +} + +static inline int get_max_patch_size(u8 chip_type) +{ + int max_patch_size = 0; + + switch (chip_type) { + case RTLPREVIOUS: + max_patch_size = 24 * 1024; + break; + case RTL8822BU: + max_patch_size = 25 * 1024; + break; + case RTL8723DU: + case RTL8822CU: + case RTL8761BU: + case RTL8821CU: + max_patch_size = 40 * 1024; + break; + case RTL8852AU: + max_patch_size = 0x114D0 + 529; /* 69.2KB */ + break; + case RTL8723FU: + max_patch_size = 0xC4Cf + 529; /* 49.2KB */ + break; + case RTL8852BU: + max_patch_size = 0x104D0 + 529; /* 65KB */ + break; + case RTL8852CU: + max_patch_size = 0x130D0 + 529; /* 76.2KB */ + break; + default: + max_patch_size = 40 * 1024; + break; + } + + return max_patch_size; +} + +int download_patch(struct usb_interface *intf) +{ + dev_data *dev_entry; + patch_info *pinfo; + xchange_data *xdata = NULL; + uint8_t *fw_buf; + int ret_val; + int max_patch_size = 0; + + RTKBT_DBG("download_patch start"); + dev_entry = dev_data_find(intf); + if (NULL == dev_entry) { + ret_val = -1; + RTKBT_ERR("NULL == dev_entry"); + goto patch_end; + } + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (NULL == xdata) { + ret_val = -1; + RTKBT_DBG("NULL == xdata"); + goto patch_end; + } + + init_xdata(xdata, dev_entry); + + ret_val = check_fw_version(xdata); + if (ret_val < 0) { + RTKBT_ERR("Failed to get Local Version Information"); + goto patch_end; + + } else if (ret_val > 0) { + RTKBT_DBG("Firmware already exists"); + /* Patch alread exists, just return */ + if (gEVersion == 0xff) { + RTKBT_DBG("global_version is not set, get it!"); + gEVersion = rtk_get_eversion(dev_entry); + } + goto patch_end; + } + + xdata->fw_len = load_firmware(dev_entry, &xdata->fw_data); + if (xdata->fw_len <= 0) { + RTKBT_ERR("load firmware failed!"); + ret_val = -1; + goto patch_end; + } + + fw_buf = xdata->fw_data; + + pinfo = dev_entry->patch_entry; + if (!pinfo) { + RTKBT_ERR("%s: No patch entry", __func__); + ret_val = -1; + goto patch_fail; + } + max_patch_size = get_max_patch_size(pinfo->chip_type); + if (xdata->fw_len > max_patch_size) { + RTKBT_ERR("FW/CONFIG total length larger than allowed %d", + max_patch_size); + ret_val = -1; + goto patch_fail; + } + + ret_val = download_data(xdata); + if (ret_val < 0) { + RTKBT_ERR("download_data failed, err %d", ret_val); + goto patch_fail; + } + + ret_val = check_fw_version(xdata); + if (ret_val <= 0) { + RTKBT_ERR("%s: Read Local Version Info failure after download", + __func__); + ret_val = -1; + goto patch_fail; + } + + ret_val = 0; +patch_fail: + kfree(fw_buf); +patch_end: + if (xdata != NULL) { + if (xdata->send_pkt) + kfree(xdata->send_pkt); + if (xdata->rcv_pkt) + kfree(xdata->rcv_pkt); + kfree(xdata); + } + RTKBT_DBG("Rtk patch end %d", ret_val); + return ret_val; +} + +#ifdef RTKBT_SWITCH_PATCH +/* @return: + * -1: error + * 0: download patch successfully + * >0: patch already exists */ +int download_lps_patch(struct usb_interface *intf) +{ + dev_data *dev_entry; + xchange_data *xdata = NULL; + uint8_t *fw_buf; + int result; + char name1[64]; + char *origin_name1; + char name2[64]; + char *origin_name2; + + RTKBT_DBG("Download LPS Patch start"); + dev_entry = dev_data_find(intf); + if (!dev_entry) { + RTKBT_ERR("No Patch found"); + return -1; + } + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (!xdata) { + RTKBT_ERR("Couldn't alloc xdata"); + return -1; + } + + init_xdata(xdata, dev_entry); + + result = check_fw_version(xdata); + if (result < 0) { + RTKBT_ERR("Failed to get Local Version Information"); + goto patch_end; + + } else if (result > 0) { + RTKBT_DBG("Firmware already exists"); + /* Patch alread exists, just return */ + if (gEVersion == 0xff) { + RTKBT_DBG("global_version is not set, get it!"); + gEVersion = rtk_get_eversion(dev_entry); + } + goto patch_end; + } + + origin_name1 = dev_entry->patch_entry->patch_name; + origin_name2 = dev_entry->patch_entry->config_name; + snprintf(name1, sizeof(name1), "lps_%s", origin_name1); + snprintf(name2, sizeof(name2), "lps_%s", origin_name2); + dev_entry->patch_entry->patch_name = name1; + dev_entry->patch_entry->config_name = name2; + RTKBT_INFO("Loading %s and %s", name1, name2); + xdata->fw_len = load_firmware(dev_entry, &xdata->fw_data); + dev_entry->patch_entry->patch_name = origin_name1; + dev_entry->patch_entry->config_name = origin_name2; + if (xdata->fw_len <= 0) { + result = -1; + RTKBT_ERR("load firmware failed!"); + goto patch_end; + } + + fw_buf = xdata->fw_data; + + pinfo = dev_entry->patch_entry; + if (!pinfo) { + RTKBT_ERR("%s: No patch entry", __func__); + result = -1; + goto patch_fail; + } + max_patch_size = get_max_patch_size(pinfo->chip_type); + if (xdata->fw_len > max_patch_size) { + result = -1; + RTKBT_ERR("FW/CONFIG total length larger than allowed %d", + max_patch_size); + goto patch_fail; + } + + result = download_data(xdata); + if (result < 0) { + RTKBT_ERR("download_data failed, err %d", result); + goto patch_fail; + } + + result = check_fw_version(xdata); + if (result <= 0) { + RTKBT_ERR("%s: Read Local Version Info failure after download", + __func__); + result = -1; + goto patch_fail; + } + + result = 0; + +patch_fail: + kfree(fw_buf); +patch_end: + if (xdata->send_pkt) + kfree(xdata->send_pkt); + if (xdata->rcv_pkt) + kfree(xdata->rcv_pkt); + kfree(xdata); + RTKBT_DBG("Download LPS Patch end %d", result); + + return result; +} +#endif + +int set_scan(struct usb_interface *intf) +{ + dev_data *dev_entry; + xchange_data *xdata = NULL; + int result; + + RTKBT_DBG("%s", __func__); + dev_entry = dev_data_find(intf); + if (!dev_entry) + return -1; + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (!xdata) { + RTKBT_ERR("Could not alloc xdata"); + return -1; + } + + init_xdata(xdata, dev_entry); + + if ( !xdata->send_pkt || !xdata->rcv_pkt ){ + result = -1; + goto end; + } + + xdata->cmd_hdr->opcode = cpu_to_le16(STARTSCAN_OPCODE); + xdata->cmd_hdr->plen = 1; + xdata->pkt_len = CMD_HDR_LEN + 1; + xdata->send_pkt[CMD_HDR_LEN] = 1; + + result = send_hci_cmd(xdata); + if (result < 0) + goto end; + + result = rcv_hci_evt(xdata); +end: + kfree(xdata->send_pkt); + kfree(xdata->rcv_pkt); + kfree(xdata); + + RTKBT_DBG("%s done", __func__); + + return result; +} + +dev_data *dev_data_find(struct usb_interface * intf) +{ + dev_data *dev_entry; + + list_for_each_entry(dev_entry, &dev_data_list, list_node) { + if (dev_entry->intf == intf) { + patch_info *patch = dev_entry->patch_entry; + if (!patch) + return NULL; + + RTKBT_INFO("chip type value: 0x%02x", patch->chip_type); + return dev_entry; + } + } + + return NULL; +} + +patch_info *get_patch_entry(struct usb_device * udev) +{ + patch_info *patch_entry; + uint16_t pid; + + patch_entry = fw_patch_table; + pid = le16_to_cpu(udev->descriptor.idProduct); + RTKBT_DBG("pid = 0x%x", pid); + while (pid != patch_entry->prod_id) { + if (0 == patch_entry->prod_id) { + RTKBT_DBG + ("get_patch_entry =NULL, can not find device pid in patch_table"); + return NULL; //break; + } + patch_entry++; + } + + return patch_entry; +} + +static int is_mac(u8 chip_type, u16 offset) +{ + int result = 0; + + switch (chip_type) { + case RTL8822BU: + case RTL8723DU: + case RTL8821CU: + if (offset == 0x0044) + return 1; + break; + case RTL8822CU: + case RTL8761BU: + case RTL8852AU: + case RTL8723FU: + case RTL8852BU: + case RTL8852CU: + if (offset == 0x0030) + return 1; + break; + case RTLPREVIOUS: + if (offset == 0x003c) + return 1; + break; + } + + return result; +} + +static uint16_t get_mac_offset(u8 chip_type) +{ + switch (chip_type) { + case RTL8822BU: + case RTL8723DU: + case RTL8821CU: + return 0x0044; + case RTL8822CU: + case RTL8761BU: + case RTL8852AU: + case RTL8723FU: + case RTL8852BU: + case RTL8852CU: + return 0x0030; + case RTLPREVIOUS: + return 0x003c; + default: + return 0x003c; + } +} + +static void merge_configs(struct list_head *head, struct list_head *head2) +{ + struct list_head *epos, *enext; + struct list_head *pos, *next; + struct cfg_list_item *n; + struct cfg_list_item *extra; + + if (!head || !head2) + return; + + if (list_empty(head2)) + return; + + if (list_empty(head)) { + list_splice_tail(head2, head); + INIT_LIST_HEAD(head2); + return; + } + + /* Add or update & replace */ + list_for_each_safe(epos, enext, head2) { + extra = list_entry(epos, struct cfg_list_item, list); + + list_for_each_safe(pos, next, head) { + n = list_entry(pos, struct cfg_list_item, list); + if (extra->offset == n->offset) { + if (extra->len < n->len) { + /* Update the cfg data */ + RTKBT_INFO("Update cfg: ofs %04x len %u", + n->offset, n->len); + memcpy(n->data, extra->data, + extra->len); + list_del(epos); + kfree(extra); + break; + } else { + /* Replace the item */ + list_del(epos); + list_replace_init(pos, epos); + /* free the old item */ + kfree(n); + } + } + + } + + } + + if (list_empty(head2)) + return; + list_for_each_safe(epos, enext, head2) { + extra = list_entry(epos, struct cfg_list_item, list); + RTKBT_INFO("Add new cfg: ofs %04x, len %u", extra->offset, + extra->len); + /* Add the item to list */ + list_del(epos); + list_add_tail(epos, head); + } +} + +int rtk_parse_config_file(u8 *config_buf, int filelen) +{ + struct rtk_bt_vendor_config *config = (void *)config_buf; + u16 config_len = 0, temp = 0; + struct rtk_bt_vendor_config_entry *entry = NULL; + u32 i = 0; + struct cfg_list_item *item; + + if (!config_buf) + return -EINVAL; + + config_len = le16_to_cpu(config->data_len); + entry = config->entry; + + if (le32_to_cpu(config->signature) != RTK_VENDOR_CONFIG_MAGIC) { + RTKBT_ERR("sig magic num %08x, not rtk vendor magic %08x", + config->signature, RTK_VENDOR_CONFIG_MAGIC); + return -1; + } + + if (config_len != filelen - BT_CONFIG_HDRLEN) { + RTKBT_ERR("config length %u is not right %u", config_len, + (u16)(filelen - BT_CONFIG_HDRLEN)); + return -1; + } + + for (i = 0; i < config_len;) { + /* Add config item to list */ + item = kzalloc(sizeof(*item) + entry->entry_len, GFP_KERNEL); + if (item) { + item->offset = le16_to_cpu(entry->offset); + item->len = entry->entry_len; + memcpy(item->data, entry->entry_data, item->len); + list_add_tail(&item->list, &list_configs); + } else { + RTKBT_ERR("Cannot alloc mem for entry %04x, %u", + entry->offset, entry->entry_len); + break; + } + + temp = entry->entry_len + + sizeof(struct rtk_bt_vendor_config_entry); + i += temp; + entry = + (struct rtk_bt_vendor_config_entry *)((uint8_t *) entry + + temp); + } + + return 0;; +} + +uint8_t rtk_get_fw_project_id(uint8_t * p_buf) +{ + uint8_t opcode; + uint8_t len; + uint8_t data = 0; + + do { + opcode = *p_buf; + len = *(p_buf - 1); + if (opcode == 0x00) { + if (len == 1) { + data = *(p_buf - 2); + RTKBT_DBG + ("rtk_get_fw_project_id: opcode %d, len %d, data %d", + opcode, len, data); + break; + } else { + RTKBT_ERR + ("rtk_get_fw_project_id: invalid len %d", + len); + } + } + p_buf -= len + 2; + } while (*p_buf != 0xFF); + + return data; +} + +static void rtk_get_patch_entry(uint8_t * epatch_buf, + struct rtk_epatch_entry *entry) +{ + uint32_t svn_ver; + uint32_t coex_ver; + uint32_t tmp; + uint16_t i; + struct rtk_epatch *epatch_info = (struct rtk_epatch *)epatch_buf; + + epatch_info->number_of_total_patch = + le16_to_cpu(epatch_info->number_of_total_patch); + RTKBT_DBG("fw_version = 0x%x", le32_to_cpu(epatch_info->fw_version)); + RTKBT_DBG("number_of_total_patch = %d", + epatch_info->number_of_total_patch); + + /* get right epatch entry */ + for (i = 0; i < epatch_info->number_of_total_patch; i++) { + if (get_unaligned_le16(epatch_buf + 14 + 2 * i) == + gEVersion + 1) { + entry->chipID = gEVersion + 1; + entry->patch_length = get_unaligned_le16(epatch_buf + + 14 + + 2 * epatch_info->number_of_total_patch + + 2 * i); + entry->start_offset = get_unaligned_le32(epatch_buf + + 14 + + 4 * epatch_info-> number_of_total_patch + + 4 * i); + break; + } + } + + if (i >= epatch_info->number_of_total_patch) { + entry->patch_length = 0; + entry->start_offset = 0; + RTKBT_ERR("No corresponding patch found\n"); + return; + } + + svn_ver = get_unaligned_le32(epatch_buf + + entry->start_offset + + entry->patch_length - 8); + coex_ver = get_unaligned_le32(epatch_buf + + entry->start_offset + + entry->patch_length - 12); + + RTKBT_DBG("chipID %d", entry->chipID); + RTKBT_DBG("patch_length 0x%04x", entry->patch_length); + RTKBT_DBG("start_offset 0x%08x", entry->start_offset); + + RTKBT_DBG("Svn version: %8d", svn_ver); + tmp = ((coex_ver >> 16) & 0x7ff) + (coex_ver >> 27) * 10000; + RTKBT_DBG("Coexistence: BTCOEX_20%06d-%04x", + tmp, (coex_ver & 0xffff)); +} + +int bachk(const char *str) +{ + if (!str) + return -1; + + if (strlen(str) != 17) + return -1; + + while (*str) { + if (!isxdigit(*str++)) + return -1; + + if (!isxdigit(*str++)) + return -1; + + if (*str == 0) + break; + + if (*str++ != ':') + return -1; + } + + return 0; +} + +static int request_bdaddr(u8 *buf) +{ + int size; + int rc; + struct file *file; + u8 tbuf[BDADDR_STRING_LEN + 1]; + char *str; + int i; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + loff_t pos = 0; +#endif + + if (!buf) + return -EINVAL; + + file = filp_open(BDADDR_FILE, O_RDONLY, 0); + if (IS_ERR(file)) + return -ENOENT; + + if (!S_ISREG(file_inode(file)->i_mode)) + return -EINVAL; + size = i_size_read(file_inode(file)); + if (size <= 0) + return -EINVAL; + + if (size > BDADDR_STRING_LEN) + size = BDADDR_STRING_LEN; + + memset(tbuf, 0, sizeof(tbuf)); + RTKBT_INFO("size = %d", size); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + rc = kernel_read(file, tbuf, size, &pos); +#else + rc = kernel_read(file, 0, tbuf, size); +#endif + fput(file); + if (rc != size) { + if (rc >= 0) + rc = -EIO; + goto fail; + } + + if (bachk(tbuf) < 0) { + rc = -EINVAL; + goto fail; + } + + str = tbuf; + for (i = 5; i >= 0; i--) { + buf[i] = simple_strtol(str, NULL, 16); + str += 3; + } + + return size; +fail: + return rc; +} + +static u8 *load_config(dev_data *dev_entry, int *length) +{ + patch_info *patch_entry; + const char *config_name; + const struct firmware *fw; + struct usb_device *udev; + int result; + u8 *buf; + u8 *p; + u16 config_len; + u16 dlen; + u8 tmp_buf[32]; + int file_sz; + struct cfg_list_item *n; + struct list_head *pos, *next; + u8 chip_type; + + config_lists_init(); + patch_entry = dev_entry->patch_entry; + config_name = patch_entry->config_name; + udev = dev_entry->udev; + chip_type = patch_entry->chip_type; + + RTKBT_INFO("config filename %s", config_name); + result = request_firmware(&fw, config_name, &udev->dev); + if (result < 0) + return 0; + + file_sz = fw->size; + buf = (u8 *)fw->data; + + /* Load extra configs */ + config_file_proc(EXTRA_CONFIG_FILE); + list_for_each_safe(pos, next, &list_extracfgs) { + n = list_entry(pos, struct cfg_list_item, list); + RTKBT_INFO("extra cfg: ofs %04x, len %u", n->offset, n->len); + } + + /* Load extra bdaddr config */ + memset(tmp_buf, 0, sizeof(tmp_buf)); + result = request_bdaddr(tmp_buf); + if (result > 0) { + n = kzalloc(sizeof(*n) + 6, GFP_KERNEL); + if (n) { + n->offset = get_mac_offset(patch_entry->chip_type); + n->len = 6; + memcpy(n->data, tmp_buf, 6); + list_add_tail(&n->list, &list_extracfgs); + } else { + RTKBT_WARN("Couldn't alloc mem for bdaddr"); + } + } else { + if (result == -ENOENT) + RTKBT_WARN("no bdaddr file %s", BDADDR_FILE); + else + RTKBT_WARN("invalid customer bdaddr %d", result); + } + + RTKBT_INFO("Origin cfg len %u", (u16)file_sz); + util_hexdump((const u8 *)buf, file_sz); + + result = rtk_parse_config_file(buf, file_sz); + if (result < 0) { + RTKBT_ERR("Parse config file error"); + buf = NULL; + goto done; + } + + merge_configs(&list_configs, &list_extracfgs); + + /* Calculate the config_len */ + config_len = 4; /* magic word length */ + config_len += 2; /* data length field */ + dlen = 0; + list_for_each_safe(pos, next, &list_configs) { + n = list_entry(pos, struct cfg_list_item, list); + switch (n->offset) { + case 0x003c: + case 0x0030: + case 0x0044: + if (is_mac(chip_type, n->offset) && n->len == 6) { + char s[18]; + sprintf(s, "%2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X", + n->data[5], n->data[4], + n->data[3], n->data[2], + n->data[1], n->data[0]); + RTKBT_INFO("bdaddr ofs %04x, %s", n->offset, s); + } + break; + default: + break; + } + + config_len += (3 + n->len); + dlen += (3 + n->len); + } + + + buf = kzalloc(config_len, GFP_KERNEL); + if (!buf) { + RTKBT_ERR("Couldn't alloc buf for configs"); + goto done; + } + + /* Save configs to a buffer */ + memcpy(buf, cfg_magic, 4); + buf[4] = dlen & 0xff; + buf[5] = (dlen >> 8) & 0xff; + p = buf + 6; + list_for_each_safe(pos, next, &list_configs) { + n = list_entry(pos, struct cfg_list_item, list); + p[0] = n->offset & 0xff; + p[1] = (n->offset >> 8) & 0xff; + p[2] = n->len; + memcpy(p + 3, n->data, n->len); + p += (3 + n->len); + } + + RTKBT_INFO("New cfg len %u", config_len); + util_hexdump((const u8 *)buf, config_len); + + *length = config_len; + +done: + config_lists_free(); + release_firmware(fw); + + return buf; +} + +int load_firmware(dev_data * dev_entry, uint8_t ** buff) +{ + const struct firmware *fw; + struct usb_device *udev; + patch_info *patch_entry; + char *fw_name; + int fw_len = 0, ret_val = 0, config_len = 0, buf_len = -1; + uint8_t *buf = NULL, *config_file_buf = NULL, *epatch_buf = NULL; + uint8_t proj_id = 0; + uint8_t need_download_fw = 1; + uint16_t lmp_version; + struct rtk_epatch_entry current_entry = { 0 }; + + RTKBT_DBG("load_firmware start"); + udev = dev_entry->udev; + patch_entry = dev_entry->patch_entry; + lmp_version = patch_entry->lmp_sub; + RTKBT_DBG("lmp_version = 0x%04x", lmp_version); + + config_file_buf = load_config(dev_entry, &config_len); + + fw_name = patch_entry->patch_name; + RTKBT_ERR("fw name is %s", fw_name); + ret_val = request_firmware(&fw, fw_name, &udev->dev); + if (ret_val < 0) { + fw_len = 0; + kfree(config_file_buf); + config_file_buf = NULL; + goto fw_fail; + } + + epatch_buf = kzalloc(fw->size, GFP_KERNEL); + if (NULL == epatch_buf) + goto alloc_fail; + + memcpy(epatch_buf, fw->data, fw->size); + buf_len = fw->size + config_len; + + if (lmp_version == ROM_LMP_8723a) { + RTKBT_DBG("This is 8723a, use old patch style!"); + + if (memcmp(epatch_buf, RTK_EPATCH_SIGNATURE, 8) == 0) { + RTKBT_ERR("8723a Check signature error!"); + need_download_fw = 0; + } else { + if (!(buf = kzalloc(buf_len, GFP_KERNEL))) { + RTKBT_ERR("Can't alloc memory for fw&config"); + buf_len = -1; + } else { + RTKBT_DBG("8723a, fw copy direct"); + memcpy(buf, epatch_buf, fw->size); + if (config_len) { + memcpy(&buf[buf_len - config_len], + config_file_buf, config_len); + } + } + } + } else { + RTKBT_ERR("This is not 8723a, use new patch style!"); + + /* Get version from ROM */ + gEVersion = rtk_get_eversion(dev_entry); + RTKBT_DBG("%s: New gEVersion %d", __func__, gEVersion); + if (gEVersion == 0xFE) { + RTKBT_ERR("%s: Read ROM version failure", __func__); + need_download_fw = 0; + fw_len = 0; + goto alloc_fail; + } + + /* check Signature and Extension Section Field */ + if ((memcmp(epatch_buf, RTK_EPATCH_SIGNATURE, 8) != 0) || + memcmp(epatch_buf + buf_len - config_len - 4, + Extension_Section_SIGNATURE, 4) != 0) { + RTKBT_ERR("Check SIGNATURE error! do not download fw"); + need_download_fw = 0; + } else { + proj_id = + rtk_get_fw_project_id(epatch_buf + buf_len - + config_len - 5); + + if (lmp_version != project_id[proj_id]) { + RTKBT_ERR + ("lmp_version is %x, project_id is %x, does not match!!!", + lmp_version, project_id[proj_id]); + need_download_fw = 0; + } else { + RTKBT_DBG + ("lmp_version is %x, project_id is %x, match!", + lmp_version, project_id[proj_id]); + rtk_get_patch_entry(epatch_buf, ¤t_entry); + + if (current_entry.patch_length == 0) + goto alloc_fail; + + buf_len = + current_entry.patch_length + config_len; + RTKBT_DBG("buf_len = 0x%x", buf_len); + + if (!(buf = kzalloc(buf_len, GFP_KERNEL))) { + RTKBT_ERR + ("Can't alloc memory for multi fw&config"); + buf_len = -1; + } else { + memcpy(buf, + epatch_buf + + current_entry.start_offset, + current_entry.patch_length); + memcpy(buf + current_entry.patch_length - 4, epatch_buf + 8, 4); /*fw version */ + if (config_len) { + memcpy(&buf + [buf_len - config_len], + config_file_buf, + config_len); + } + } + } + } + } + + RTKBT_DBG("fw:%s exists, config file:%s exists", + (buf_len > 0) ? "" : "not", (config_len > 0) ? "" : "not"); + if (buf && (buf_len > 0) && (need_download_fw)) { + fw_len = buf_len; + *buff = buf; + } + + RTKBT_DBG("load_firmware done"); + +alloc_fail: + release_firmware(fw); + + if (epatch_buf) + kfree(epatch_buf); + + if (config_file_buf) + kfree(config_file_buf); +fw_fail: + if (fw_len == 0) + kfree(buf); + + return fw_len; +} + +void init_xdata(xchange_data * xdata, dev_data * dev_entry) +{ + memset(xdata, 0, sizeof(xchange_data)); + xdata->dev_entry = dev_entry; + xdata->pipe_in = usb_rcvintpipe(dev_entry->udev, INTR_EP); + xdata->pipe_out = usb_sndctrlpipe(dev_entry->udev, CTRL_EP); + xdata->send_pkt = kzalloc(PKT_LEN, GFP_KERNEL); + xdata->rcv_pkt = kzalloc(PKT_LEN, GFP_KERNEL); + xdata->cmd_hdr = (struct hci_command_hdr *)(xdata->send_pkt); + xdata->evt_hdr = (struct hci_event_hdr *)(xdata->rcv_pkt); + xdata->cmd_cmp = + (struct hci_ev_cmd_complete *)(xdata->rcv_pkt + EVT_HDR_LEN); + xdata->req_para = xdata->send_pkt + CMD_HDR_LEN; + xdata->rsp_para = xdata->rcv_pkt + EVT_HDR_LEN + CMD_CMP_LEN; +} + +int check_fw_version(xchange_data * xdata) +{ + struct hci_rp_read_local_version *read_ver_rsp; + patch_info *patch_entry; + int ret_val; + int retry = 0; + + /* Ensure that the first cmd is hci reset after system suspend + * or system reboot */ + send_reset_command(xdata); + +get_ver: + xdata->cmd_hdr->opcode = cpu_to_le16(HCI_OP_READ_LOCAL_VERSION); + xdata->cmd_hdr->plen = 0; + xdata->pkt_len = CMD_HDR_LEN; + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + RTKBT_ERR("%s: Failed to send HCI command.", __func__); + goto version_end; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + RTKBT_ERR("%s: Failed to receive HCI event.", __func__); + goto version_end; + } + + patch_entry = xdata->dev_entry->patch_entry; + read_ver_rsp = (struct hci_rp_read_local_version *)(xdata->rsp_para); + read_ver_rsp->lmp_subver = le16_to_cpu(read_ver_rsp->lmp_subver); + read_ver_rsp->hci_rev = le16_to_cpu(read_ver_rsp->hci_rev); + read_ver_rsp->manufacturer = le16_to_cpu(read_ver_rsp->manufacturer); + + RTKBT_DBG("read_ver_rsp->lmp_subver = 0x%x", read_ver_rsp->lmp_subver); + RTKBT_DBG("read_ver_rsp->hci_rev = 0x%x", read_ver_rsp->hci_rev); + RTKBT_DBG("patch_entry->lmp_sub = 0x%x", patch_entry->lmp_sub); + if (patch_entry->lmp_sub != read_ver_rsp->lmp_subver) { + return 1; + } + + ret_val = 0; +version_end: + if (ret_val) { + send_reset_command(xdata); + retry++; + if (retry < 2) + goto get_ver; + } + + return ret_val; +} + +uint8_t rtk_get_eversion(dev_data * dev_entry) +{ + struct rtk_eversion_evt *eversion; + patch_info *patch_entry; + int ret_val = 0; + xchange_data *xdata = NULL; + + RTKBT_DBG("%s: gEVersion %d", __func__, gEVersion); + if (gEVersion != 0xFF && gEVersion != 0xFE) { + RTKBT_DBG("gEVersion != 0xFF, return it directly!"); + return gEVersion; + } + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (NULL == xdata) { + ret_val = 0xFE; + RTKBT_DBG("NULL == xdata"); + return ret_val; + } + + init_xdata(xdata, dev_entry); + + xdata->cmd_hdr->opcode = cpu_to_le16(HCI_VENDOR_READ_RTK_ROM_VERISION); + xdata->cmd_hdr->plen = 0; + xdata->pkt_len = CMD_HDR_LEN; + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + RTKBT_ERR("Failed to send read RTK rom version cmd."); + ret_val = 0xFE; + goto version_end; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + RTKBT_ERR("Failed to receive HCI event for rom version."); + ret_val = 0xFE; + goto version_end; + } + + patch_entry = xdata->dev_entry->patch_entry; + eversion = (struct rtk_eversion_evt *)(xdata->rsp_para); + RTKBT_DBG("eversion->status = 0x%x, eversion->version = 0x%x", + eversion->status, eversion->version); + if (eversion->status) { + ret_val = 0; + //global_eversion = 0; + } else { + ret_val = eversion->version; + //global_eversion = eversion->version; + } + +version_end: + if (xdata != NULL) { + if (xdata->send_pkt) + kfree(xdata->send_pkt); + if (xdata->rcv_pkt) + kfree(xdata->rcv_pkt); + kfree(xdata); + } + return ret_val; +} + +int download_data(xchange_data * xdata) +{ + download_cp *cmd_para; + download_rp *evt_para; + uint8_t *pcur; + int pkt_len, frag_num, frag_len; + int i, ret_val; + int j; + + RTKBT_DBG("download_data start"); + + cmd_para = (download_cp *) xdata->req_para; + evt_para = (download_rp *) xdata->rsp_para; + pcur = xdata->fw_data; + pkt_len = CMD_HDR_LEN + sizeof(download_cp); + frag_num = xdata->fw_len / PATCH_SEG_MAX + 1; + frag_len = PATCH_SEG_MAX; + + for (i = 0; i < frag_num; i++) { + if (i > 0x7f) + j = (i & 0x7f) + 1; + else + j = i; + + cmd_para->index = j; + if (i == (frag_num - 1)) { + cmd_para->index |= DATA_END; + frag_len = xdata->fw_len % PATCH_SEG_MAX; + pkt_len -= (PATCH_SEG_MAX - frag_len); + } + xdata->cmd_hdr->opcode = cpu_to_le16(DOWNLOAD_OPCODE); + xdata->cmd_hdr->plen = sizeof(uint8_t) + frag_len; + xdata->pkt_len = pkt_len; + memcpy(cmd_para->data, pcur, frag_len); + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + return ret_val; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + return ret_val; + } + + if (0 != evt_para->status) { + return -1; + } + + pcur += PATCH_SEG_MAX; + } + + RTKBT_DBG("download_data done"); + return xdata->fw_len; +} + +int send_hci_cmd(xchange_data * xdata) +{ + int ret_val; + + ret_val = usb_control_msg(xdata->dev_entry->udev, xdata->pipe_out, + 0, USB_TYPE_CLASS, 0, 0, + (void *)(xdata->send_pkt), + xdata->pkt_len, MSG_TO); + + if (ret_val < 0) + RTKBT_ERR("%s; failed to send ctl msg for hci cmd, err %d", + __func__, ret_val); + + return ret_val; +} + +int rcv_hci_evt(xchange_data * xdata) +{ + int ret_len = 0, ret_val = 0; + int i; // Added by Realtek + + while (1) { + // **************************** Modifed by Realtek (begin) + for (i = 0; i < 5; i++) // Try to send USB interrupt message 5 times. + { + ret_val = + usb_interrupt_msg(xdata->dev_entry->udev, + xdata->pipe_in, + (void *)(xdata->rcv_pkt), PKT_LEN, + &ret_len, MSG_TO); + if (ret_val >= 0) + break; + } + // **************************** Modifed by Realtek (end) + + if (ret_val < 0) { + RTKBT_ERR("%s; no usb intr msg for hci event, err %d", + __func__, ret_val); + return ret_val; + } + + if (CMD_CMP_EVT == xdata->evt_hdr->evt) { + if (xdata->cmd_hdr->opcode == xdata->cmd_cmp->opcode) + return ret_len; + } + } +} + +void print_acl(struct sk_buff *skb, int dataOut) +{ +#if PRINT_ACL_DATA + uint wlength = skb->len; + uint icount = 0; + u16 *handle = (u16 *) (skb->data); + u16 dataLen = *(handle + 1); + u8 *acl_data = (u8 *) (skb->data); +//if (0==dataOut) + printk("%d handle:%04x,len:%d,", dataOut, *handle, dataLen); +//else +// printk("In handle:%04x,len:%d,",*handle,dataLen); +/* for(icount=4;(icountlen; + uint icount = 0; + u16 *opcode = (u16 *) (skb->data); + u8 *cmd_data = (u8 *) (skb->data); + u8 paramLen = *(cmd_data + 2); + + switch (*opcode) { + case HCI_OP_INQUIRY: + printk("HCI_OP_INQUIRY"); + break; + case HCI_OP_INQUIRY_CANCEL: + printk("HCI_OP_INQUIRY_CANCEL"); + break; + case HCI_OP_EXIT_PERIODIC_INQ: + printk("HCI_OP_EXIT_PERIODIC_INQ"); + break; + case HCI_OP_CREATE_CONN: + printk("HCI_OP_CREATE_CONN"); + break; + case HCI_OP_DISCONNECT: + printk("HCI_OP_DISCONNECT"); + break; + case HCI_OP_CREATE_CONN_CANCEL: + printk("HCI_OP_CREATE_CONN_CANCEL"); + break; + case HCI_OP_ACCEPT_CONN_REQ: + printk("HCI_OP_ACCEPT_CONN_REQ"); + break; + case HCI_OP_REJECT_CONN_REQ: + printk("HCI_OP_REJECT_CONN_REQ"); + break; + case HCI_OP_AUTH_REQUESTED: + printk("HCI_OP_AUTH_REQUESTED"); + break; + case HCI_OP_SET_CONN_ENCRYPT: + printk("HCI_OP_SET_CONN_ENCRYPT"); + break; + case HCI_OP_REMOTE_NAME_REQ: + printk("HCI_OP_REMOTE_NAME_REQ"); + break; + case HCI_OP_READ_REMOTE_FEATURES: + printk("HCI_OP_READ_REMOTE_FEATURES"); + break; + case HCI_OP_SNIFF_MODE: + printk("HCI_OP_SNIFF_MODE"); + break; + case HCI_OP_EXIT_SNIFF_MODE: + printk("HCI_OP_EXIT_SNIFF_MODE"); + break; + case HCI_OP_SWITCH_ROLE: + printk("HCI_OP_SWITCH_ROLE"); + break; + case HCI_OP_SNIFF_SUBRATE: + printk("HCI_OP_SNIFF_SUBRATE"); + break; + case HCI_OP_RESET: + printk("HCI_OP_RESET"); + break; + default: + printk("CMD"); + break; + } + printk(":%04x,len:%d,", *opcode, paramLen); + for (icount = 3; (icount < wlength) && (icount < 24); icount++) { + printk("%02x ", *(cmd_data + icount)); + } + printk("\n"); + +#endif +} + +void print_event(struct sk_buff *skb) +{ +#if PRINT_CMD_EVENT + uint wlength = skb->len; + uint icount = 0; + u8 *opcode = (u8 *) (skb->data); + u8 paramLen = *(opcode + 1); + + switch (*opcode) { + case HCI_EV_INQUIRY_COMPLETE: + printk("HCI_EV_INQUIRY_COMPLETE"); + break; + case HCI_EV_INQUIRY_RESULT: + printk("HCI_EV_INQUIRY_RESULT"); + break; + case HCI_EV_CONN_COMPLETE: + printk("HCI_EV_CONN_COMPLETE"); + break; + case HCI_EV_CONN_REQUEST: + printk("HCI_EV_CONN_REQUEST"); + break; + case HCI_EV_DISCONN_COMPLETE: + printk("HCI_EV_DISCONN_COMPLETE"); + break; + case HCI_EV_AUTH_COMPLETE: + printk("HCI_EV_AUTH_COMPLETE"); + break; + case HCI_EV_REMOTE_NAME: + printk("HCI_EV_REMOTE_NAME"); + break; + case HCI_EV_ENCRYPT_CHANGE: + printk("HCI_EV_ENCRYPT_CHANGE"); + break; + case HCI_EV_CHANGE_LINK_KEY_COMPLETE: + printk("HCI_EV_CHANGE_LINK_KEY_COMPLETE"); + break; + case HCI_EV_REMOTE_FEATURES: + printk("HCI_EV_REMOTE_FEATURES"); + break; + case HCI_EV_REMOTE_VERSION: + printk("HCI_EV_REMOTE_VERSION"); + break; + case HCI_EV_QOS_SETUP_COMPLETE: + printk("HCI_EV_QOS_SETUP_COMPLETE"); + break; + case HCI_EV_CMD_COMPLETE: + printk("HCI_EV_CMD_COMPLETE"); + break; + case HCI_EV_CMD_STATUS: + printk("HCI_EV_CMD_STATUS"); + break; + case HCI_EV_ROLE_CHANGE: + printk("HCI_EV_ROLE_CHANGE"); + break; + case HCI_EV_NUM_COMP_PKTS: + printk("HCI_EV_NUM_COMP_PKTS"); + break; + case HCI_EV_MODE_CHANGE: + printk("HCI_EV_MODE_CHANGE"); + break; + case HCI_EV_PIN_CODE_REQ: + printk("HCI_EV_PIN_CODE_REQ"); + break; + case HCI_EV_LINK_KEY_REQ: + printk("HCI_EV_LINK_KEY_REQ"); + break; + case HCI_EV_LINK_KEY_NOTIFY: + printk("HCI_EV_LINK_KEY_NOTIFY"); + break; + case HCI_EV_CLOCK_OFFSET: + printk("HCI_EV_CLOCK_OFFSET"); + break; + case HCI_EV_PKT_TYPE_CHANGE: + printk("HCI_EV_PKT_TYPE_CHANGE"); + break; + case HCI_EV_PSCAN_REP_MODE: + printk("HCI_EV_PSCAN_REP_MODE"); + break; + case HCI_EV_INQUIRY_RESULT_WITH_RSSI: + printk("HCI_EV_INQUIRY_RESULT_WITH_RSSI"); + break; + case HCI_EV_REMOTE_EXT_FEATURES: + printk("HCI_EV_REMOTE_EXT_FEATURES"); + break; + case HCI_EV_SYNC_CONN_COMPLETE: + printk("HCI_EV_SYNC_CONN_COMPLETE"); + break; + case HCI_EV_SYNC_CONN_CHANGED: + printk("HCI_EV_SYNC_CONN_CHANGED"); + break; + case HCI_EV_SNIFF_SUBRATE: + printk("HCI_EV_SNIFF_SUBRATE"); + break; + case HCI_EV_EXTENDED_INQUIRY_RESULT: + printk("HCI_EV_EXTENDED_INQUIRY_RESULT"); + break; + case HCI_EV_IO_CAPA_REQUEST: + printk("HCI_EV_IO_CAPA_REQUEST"); + break; + case HCI_EV_SIMPLE_PAIR_COMPLETE: + printk("HCI_EV_SIMPLE_PAIR_COMPLETE"); + break; + case HCI_EV_REMOTE_HOST_FEATURES: + printk("HCI_EV_REMOTE_HOST_FEATURES"); + break; + default: + printk("event"); + break; + } + printk(":%02x,len:%d,", *opcode, paramLen); + for (icount = 2; (icount < wlength) && (icount < 24); icount++) { + printk("%02x ", *(opcode + icount)); + } + printk("\n"); + +#endif +} diff --git a/drivers/bluetooth/rtk_misc.h b/drivers/bluetooth/rtk_misc.h new file mode 100644 index 0000000000000..048d34eb7b114 --- /dev/null +++ b/drivers/bluetooth/rtk_misc.h @@ -0,0 +1,95 @@ +/* + * + * Realtek Bluetooth USB download firmware driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +/* Download LPS patch when host suspends or power off + * LPS patch name: lps_rtl8xxx_fw + * LPS config name: lps_rtl8xxx_config + * Download normal patch when host resume or power on */ +/* #define RTKBT_SWITCH_PATCH */ + +/* RTKBT Power-on Whitelist for sideband wake-up by LE Advertising from Remote. + * Note that it's necessary to apply TV FW Patch. */ +/* #define RTKBT_TV_POWERON_WHITELIST */ + +#if 1 +#define RTKBT_DBG(fmt, arg...) printk(KERN_INFO "rtk_btusb: " fmt "\n" , ## arg) +#define RTKBT_INFO(fmt, arg...) printk(KERN_INFO "rtk_btusb: " fmt "\n" , ## arg) +#define RTKBT_WARN(fmt, arg...) printk(KERN_WARNING "rtk_btusb: " fmt "\n", ## arg) +#else +#define RTKBT_DBG(fmt, arg...) +#endif + +#if 1 +#define RTKBT_ERR(fmt, arg...) printk(KERN_ERR "rtk_btusb: " fmt "\n" , ## arg) +#else +#define RTKBT_ERR(fmt, arg...) +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 33) +#define USB_RPM +#endif + +#define CONFIG_NEEDS_BINDING + +/* If module is still powered when kernel suspended, there is no re-binding. */ +#ifdef RTKBT_SWITCH_PATCH +#undef CONFIG_NEEDS_BINDING +#endif + +/* USB SS */ +#if (defined CONFIG_BTUSB_AUTOSUSPEND) && (defined USB_RPM) +#define BTUSB_RPM +#endif + +#define PRINT_CMD_EVENT 0 +#define PRINT_ACL_DATA 0 + +extern int patch_add(struct usb_interface *intf); +extern void patch_remove(struct usb_interface *intf); +extern int download_patch(struct usb_interface *intf); +extern void print_event(struct sk_buff *skb); +extern void print_command(struct sk_buff *skb); +extern void print_acl(struct sk_buff *skb, int dataOut); + +#if defined RTKBT_SWITCH_PATCH || defined RTKBT_TV_POWERON_WHITELIST +int __rtk_send_hci_cmd(struct usb_device *udev, u8 *buf, u16 size); +int __rtk_recv_hci_evt(struct usb_device *udev, u8 *buf, u8 len, u16 opcode); +#endif + +#ifdef RTKBT_SWITCH_PATCH +#define RTLBT_CLOSE (1 << 0) +struct api_context { + u32 flags; + struct completion done; + int status; +}; + +int download_lps_patch(struct usb_interface *intf); +int set_scan(struct usb_interface *intf); + +#endif From f4860c206760e4f986d9911de45a0fdd39fe4a66 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Thu, 2 Mar 2023 15:09:15 +0800 Subject: [PATCH 005/249] input: touchscreen: focaltech touch: modified by radxa --- .../touchscreen/focaltech_touch/Makefile | 2 +- .../focaltech_touch/focaltech_core.c | 30 +++++++------------ .../focaltech_touch/focaltech_core.h | 4 +-- 3 files changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/input/touchscreen/focaltech_touch/Makefile b/drivers/input/touchscreen/focaltech_touch/Makefile index fbf30651f2f8c..9d022eb01a841 100644 --- a/drivers/input/touchscreen/focaltech_touch/Makefile +++ b/drivers/input/touchscreen/focaltech_touch/Makefile @@ -15,5 +15,5 @@ focaltech-ts-y += focaltech_esdcheck.o focaltech-ts-y += focaltech_i2c.o focaltech-ts-y += focaltech_point_report_check.o focaltech-ts-y += focaltech_upgrade_ft8201.o -focaltech-ts-y += focaltech_test/ +#focaltech-ts-y += focaltech_test/ diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_core.c b/drivers/input/touchscreen/focaltech_touch/focaltech_core.c index 98ef3fae7607a..0586b01c7dd39 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_core.c +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_core.c @@ -1114,20 +1114,13 @@ static int fts_gpio_configure(struct fts_ts_data *data) static int fts_get_dt_coords(struct device *dev, char *name, struct fts_ts_platform_data *pdata) { - //int ret = 0; - //u32 coords[FTS_COORDS_ARR_SIZE] = { 0 }; - //struct property *prop; - //struct device_node *np = dev->of_node; - //int coords_size; - - pdata->x_min = FTS_X_MIN_DISPLAY_DEFAULT; - pdata->y_min = FTS_Y_MIN_DISPLAY_DEFAULT; - pdata->x_max = FTS_X_MAX_DISPLAY_DEFAULT; - pdata->y_max = FTS_Y_MAX_DISPLAY_DEFAULT; - - - - /*prop = of_find_property(np, name, NULL); + int ret = 0; + u32 coords[FTS_COORDS_ARR_SIZE] = { 0 }; + struct property *prop; + struct device_node *np = dev->of_node; + int coords_size; + + prop = of_find_property(np, name, NULL); if (!prop) return -EINVAL; if (!prop->value) @@ -1156,12 +1149,11 @@ static int fts_get_dt_coords(struct device *dev, char *name, pdata->y_min = FTS_Y_MIN_DISPLAY_DEFAULT; pdata->x_max = FTS_X_MAX_DISPLAY_DEFAULT; pdata->y_max = FTS_Y_MAX_DISPLAY_DEFAULT; - // return -EINVAL; + return -EINVAL; } -*/ - printk("display x(%d %d) y(%d %d)", pdata->x_min, pdata->x_max, pdata->y_min, pdata->y_max); - /*FTS_INFO("display x(%d %d) y(%d %d)", pdata->x_min, pdata->x_max, - pdata->y_min, pdata->y_max);*/ + + FTS_INFO("display x(%d %d) y(%d %d)", pdata->x_min, pdata->x_max, + pdata->y_min, pdata->y_max); return 0; } diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_core.h b/drivers/input/touchscreen/focaltech_touch/focaltech_core.h index 6547719b94a97..63bac38b0ae07 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_core.h +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_core.h @@ -88,8 +88,8 @@ #define FTS_COORDS_ARR_SIZE 4 #define FTS_X_MIN_DISPLAY_DEFAULT 0 #define FTS_Y_MIN_DISPLAY_DEFAULT 0 -#define FTS_X_MAX_DISPLAY_DEFAULT 1600 -#define FTS_Y_MAX_DISPLAY_DEFAULT 2176 +#define FTS_X_MAX_DISPLAY_DEFAULT 799 +#define FTS_Y_MAX_DISPLAY_DEFAULT 1279 #define FTS_TOUCH_DOWN 0 #define FTS_TOUCH_UP 1 From 8cba6c52b1f169a7427049a01bce527b6c03bbca Mon Sep 17 00:00:00 2001 From: Stephen Chen Date: Fri, 3 Feb 2023 16:35:47 +0800 Subject: [PATCH 006/249] input: touchscreen: add Raspberry Pi touchscreen IC FT5426 driver Signed-off-by: Stephen Chen --- drivers/input/touchscreen/Kconfig | 6 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/raspits_ft5426.c | 309 +++++++++++++++++++++ drivers/input/touchscreen/raspits_ft5426.h | 64 +++++ 4 files changed, 380 insertions(+) create mode 100644 drivers/input/touchscreen/raspits_ft5426.c create mode 100644 drivers/input/touchscreen/raspits_ft5426.h diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 99994ceb3a3db..8f5ea2ac79247 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -829,6 +829,12 @@ config TOUCHSCREEN_RASPBERRYPI_FW To compile this driver as a module, choose M here: the module will be called raspberrypi-ts. +config TOUCHSCREEN_RASPITS_FT5426 + tristate "Raspberry Pi 7 inch touchscreen touch control IC FT5426" + depends on I2C + help + Control FT5426 touch IC. + config TOUCHSCREEN_MIGOR tristate "Renesas MIGO-R touchscreen" depends on (SH_MIGOR || COMPILE_TEST) && I2C diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 6cd2a56f5bd0c..5b5abdb6e11b2 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -129,5 +129,6 @@ obj-$(CONFIG_TOUCHSCREEN_ZFORCE) += zforce_ts.o obj-$(CONFIG_TOUCHSCREEN_COLIBRI_VF50) += colibri-vf50-ts.o obj-$(CONFIG_TOUCHSCREEN_ROHM_BU21023) += rohm_bu21023.o obj-$(CONFIG_TOUCHSCREEN_RASPBERRYPI_FW) += raspberrypi-ts.o +obj-$(CONFIG_TOUCHSCREEN_RASPITS_FT5426) += raspits_ft5426.o obj-$(CONFIG_TOUCHSCREEN_IQS5XX) += iqs5xx.o obj-$(CONFIG_TOUCHSCREEN_ZINITIX) += zinitix.o diff --git a/drivers/input/touchscreen/raspits_ft5426.c b/drivers/input/touchscreen/raspits_ft5426.c new file mode 100644 index 0000000000000..fa2edcb2995b6 --- /dev/null +++ b/drivers/input/touchscreen/raspits_ft5426.c @@ -0,0 +1,309 @@ +/* + * + * Raspberry Pi 7 inch Touchscreen FT5426 touch driver. + * + * Copyright (c) 2016 ASUSTek Computer Inc. + * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "raspits_ft5426.h" + +static int fts_i2c_read(struct i2c_client *client, char *writebuf, + int writelen, char *readbuf, int readlen) +{ + int ret; + + if (writelen > 0) { + struct i2c_msg msgs[] = { + { + .addr = client->addr, + .flags = 0, + .len = writelen, + .buf = writebuf, + }, + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = readlen, + .buf = readbuf, + }, + }; + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret < 0) + LOG_ERR("i2c read error, %d\n", ret); + } else { + struct i2c_msg msgs[] = { + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = readlen, + .buf = readbuf, + }, + }; + ret = i2c_transfer(client->adapter, msgs, 1); + if (ret < 0) + LOG_ERR("i2c read error, %d\n", ret); + } + + return ret; +} + +static int fts_read_reg(struct i2c_client *client, u8 addr, u8 *val) +{ + return fts_i2c_read(client, &addr, 1, val, 1); +} + +static int fts_check_fw_ver(struct i2c_client *client) +{ + u8 reg_addr, fw_ver[3]; + int ret; + + reg_addr = FT_REG_FW_VER; + ret = fts_i2c_read(client, ®_addr, 1, &fw_ver[0], 1); + if (ret < 0) + goto error; + + reg_addr = FT_REG_FW_MIN_VER; + ret = fts_i2c_read(client, ®_addr, 1, &fw_ver[1], 1); + if (ret < 0) + goto error; + + reg_addr = FT_REG_FW_SUB_MIN_VER; + ret = fts_i2c_read(client, ®_addr, 1, &fw_ver[2], 1); + if (ret < 0) + goto error; + + LOG_INFO("Firmware version = %d.%d.%d\n", fw_ver[0], fw_ver[1], fw_ver[2]); + return 0; + +error: + return ret; +} + +static int fts_read_td_status(struct raspits_ft5426_data *ts_data) +{ + u8 td_status; + int ret = -1; + ret = fts_read_reg(ts_data->client, FT_TD_STATUS_REG, &td_status); + if (ret < 0) { + LOG_ERR("get reg td_status failed, %d\n", ret); + return ret; + } + return (int)td_status; +} + +static int fts_read_touchdata(struct raspits_ft5426_data *ts_data) +{ + struct ts_event *event = &ts_data->event; + int ret = -1, i; + u8 buf[FT_ONE_TCH_LEN-2] = { 0 }; + u8 reg_addr, pointid = FT_MAX_ID; + + for (i = 0; i < event->touch_point && i < MAX_TOUCH_POINTS; i++) { + reg_addr = FT_TOUCH_X_H_REG + (i * FT_ONE_TCH_LEN); + ret = fts_i2c_read(ts_data->client, ®_addr, 1, buf, FT_ONE_TCH_LEN-2); + if (ret < 0) { + LOG_ERR("read touchdata failed.\n"); + return ret; + } + + pointid = (buf[FT_TOUCH_ID]) >> 4; + if (pointid >= MAX_TOUCH_POINTS) + break; + event->au8_finger_id[i] = pointid; + event->au16_x[i] = (s16) (buf[FT_TOUCH_X_H] & 0x0F) << 8 | (s16) buf[FT_TOUCH_X_L]; + event->au16_y[i] = (s16) (buf[FT_TOUCH_Y_H] & 0x0F) << 8 | (s16) buf[FT_TOUCH_Y_L]; + event->au8_touch_event[i] = buf[FT_TOUCH_EVENT] >> 6; + +#if XY_REVERSE + event->au16_x[i] = SCREEN_WIDTH - event->au16_x[i] - 1; + event->au16_y[i] = SCREEN_HEIGHT - event->au16_y[i] - 1; +#endif + } + event->pressure = FT_PRESS; + + return 0; +} + +static void fts_report_value(struct raspits_ft5426_data *ts_data) +{ + struct ts_event *event = &ts_data->event; + int i, modified_ids = 0, released_ids; + + for (i = 0; i < event->touch_point && i < MAX_TOUCH_POINTS; i++) { + if (event->au8_touch_event[i]== FT_TOUCH_DOWN + || event->au8_touch_event[i] == FT_TOUCH_CONTACT) + { + modified_ids |= 1 << event->au8_finger_id[i]; + input_mt_slot(ts_data->input_dev, event->au8_finger_id[i]); + input_mt_report_slot_state(ts_data->input_dev, MT_TOOL_FINGER, + true); + input_report_abs(ts_data->input_dev, ABS_MT_TOUCH_MAJOR, + event->pressure); + input_report_abs(ts_data->input_dev, ABS_MT_POSITION_X, + event->au16_x[i]); + input_report_abs(ts_data->input_dev, ABS_MT_POSITION_Y, + event->au16_y[i]); + + if(!((1 << event->au8_finger_id[i]) & ts_data->known_ids)) + LOG_DBG("Touch id-%d: x = %d, y = %d\n", + event->au8_finger_id[i], event->au16_x[i], event->au16_y[i]); + } + } + + released_ids = ts_data->known_ids & ~modified_ids; + for(i = 0; released_ids && i < MAX_TOUCH_POINTS; i++) { + if(released_ids & (1<known_ids, modified_ids); + input_mt_slot(ts_data->input_dev, i); + input_mt_report_slot_state(ts_data->input_dev, MT_TOOL_FINGER, false); + modified_ids &= ~(1 << i); + } + } + ts_data->known_ids = modified_ids; + input_mt_report_pointer_emulation(ts_data->input_dev, true); + input_sync(ts_data->input_dev); +} + +static void raspits_ft5426_work(struct work_struct *work) +{ + struct raspits_ft5426_data *ts_data + = container_of(work, struct raspits_ft5426_data, ft5426_work); + struct ts_event *event = &ts_data->event; + int ret = 0, count = 8, td_status; + + while(count > 0) { + ret = fts_check_fw_ver(ts_data->client); + if (ret == 0) + break; + LOG_INFO("checking touch ic, countdown: %d\n", count); + msleep(1000); + count--; + } + if (!count) { + LOG_ERR("checking touch ic timeout, %d\n", ret); + return; + } + + //polling 60fps + while(1) { + td_status = fts_read_td_status(ts_data); + if (td_status < VALID_TD_STATUS_VAL+1 && (td_status > 0 || ts_data->known_ids != 0)) { + memset(event, -1, sizeof(struct ts_event)); + event->touch_point = td_status; + ret = fts_read_touchdata(ts_data); + if (ret == 0) + fts_report_value(ts_data); + } + msleep_interruptible(17); + } +} + +static int raspits_ft5426_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct raspits_ft5426_data *ts_data; + struct input_dev *input_dev; + int ret = 0;//, timeout = 10; + + LOG_INFO("address = 0x%x\n", client->addr); + + ts_data = kzalloc(sizeof(struct raspits_ft5426_data), GFP_KERNEL); + if (ts_data == NULL) { + LOG_ERR("no memory for device\n"); + return -ENOMEM; + } + + ts_data->client = client; + i2c_set_clientdata(client, ts_data); + + input_dev = input_allocate_device(); + if (!input_dev) { + LOG_ERR("failed to allocate input device\n"); + goto input_allocate_failed; + } + input_dev->name = "fts_ts"; + input_dev->id.bustype = BUS_I2C; + input_dev->dev.parent = &ts_data->client->dev; + + ts_data->input_dev = input_dev; + input_set_drvdata(input_dev, ts_data); + + __set_bit(EV_SYN, input_dev->evbit); + __set_bit(EV_KEY, input_dev->evbit); + __set_bit(EV_ABS, input_dev->evbit); + __set_bit(BTN_TOUCH, input_dev->keybit); + + input_mt_init_slots(input_dev, MAX_TOUCH_POINTS, 0); + input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, + SCREEN_WIDTH, 0, 0); + input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0, + SCREEN_HEIGHT, 0, 0); + + ret = input_register_device(input_dev); + if (ret) { + LOG_ERR("Input device registration failed\n"); + goto input_register_failed; + } + + INIT_WORK(&ts_data->ft5426_work, raspits_ft5426_work); + schedule_work(&ts_data->ft5426_work); + + return 0; + +input_register_failed: + input_free_device(input_dev); +input_allocate_failed: + kfree(ts_data); + return ret; +} + +static int raspits_ft5426_remove(struct i2c_client *client) +{ + struct raspits_ft5426_data *ts_data = i2c_get_clientdata(client); + + cancel_work_sync(&ts_data->ft5426_work); + if (ts_data->input_dev) { + input_unregister_device(ts_data->input_dev); + input_free_device(ts_data->input_dev); + } + kfree(ts_data); + return 0; +} + +static const struct i2c_device_id raspits_ft5426_id[] = { + { "raspits_ft5426", 0 }, + { }, +}; + +static struct i2c_driver raspits_ft5426_driver = { + .driver = { + .name = "raspits_ft5426", + }, + .probe = raspits_ft5426_probe, + .remove = raspits_ft5426_remove, + .id_table = raspits_ft5426_id, +}; +module_i2c_driver(raspits_ft5426_driver); + +MODULE_DESCRIPTION("Raspberry Pi 7 inch Touchscreen FT5426 Touch driver"); +MODULE_LICENSE("GPL v2"); + diff --git a/drivers/input/touchscreen/raspits_ft5426.h b/drivers/input/touchscreen/raspits_ft5426.h new file mode 100644 index 0000000000000..b6e6e4da36ce4 --- /dev/null +++ b/drivers/input/touchscreen/raspits_ft5426.h @@ -0,0 +1,64 @@ +#ifndef _RASPITS_FT5426_H_ +#define _RASPITS_FT5426_H_ + +#define LOG_DBG(fmt,arg...) pr_debug("raspits-ft5426: %s: "fmt, __func__, ##arg); +#define LOG_INFO(fmt,arg...) pr_info("raspits-ft5426: %s: "fmt, __func__, ##arg); +#define LOG_ERR(fmt,arg...) pr_err("raspits-ft5426: %s: "fmt, __func__, ##arg); + +#define XY_REVERSE 1 + +#define SCREEN_WIDTH 800 +#define SCREEN_HEIGHT 480 + +#define FT_ONE_TCH_LEN 6 + +#define FT_REG_FW_VER 0xA6 +#define FT_REG_FW_MIN_VER 0xB2 +#define FT_REG_FW_SUB_MIN_VER 0xB3 + +#define VALID_TD_STATUS_VAL 10 +#define MAX_TOUCH_POINTS 1 + +#define FT_PRESS 0x7F +#define FT_MAX_ID 0x0F + +#define FT_TOUCH_X_H 0 +#define FT_TOUCH_X_L 1 +#define FT_TOUCH_Y_H 2 +#define FT_TOUCH_Y_L 3 +#define FT_TOUCH_EVENT 0 +#define FT_TOUCH_ID 2 + +#define FT_TOUCH_X_H_REG 3 +#define FT_TOUCH_X_L_REG 4 +#define FT_TOUCH_Y_H_REG 5 +#define FT_TOUCH_Y_L_REG 6 +#define FT_TD_STATUS_REG 2 +#define FT_TOUCH_EVENT_REG 3 +#define FT_TOUCH_ID_REG 5 + +#define FT_TOUCH_DOWN 0 +#define FT_TOUCH_CONTACT 2 + +struct ts_event { + u16 au16_x[MAX_TOUCH_POINTS]; /*x coordinate */ + u16 au16_y[MAX_TOUCH_POINTS]; /*y coordinate */ + u8 au8_touch_event[MAX_TOUCH_POINTS]; /*touch event: 0:down; 1:up; 2:contact */ + u8 au8_finger_id[MAX_TOUCH_POINTS]; /*touch ID */ + u16 pressure; + u8 touch_point; + u8 point_num; +}; + +struct raspits_ft5426_data { + struct device *dev; + struct i2c_client *client; + struct input_dev *input_dev; + struct ts_event event; + struct work_struct ft5426_work; + + int known_ids; +}; + +#endif + From 2b808eef920e833cbdd3e36a33636dfe5b7a08b1 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Thu, 2 Mar 2023 15:14:31 +0800 Subject: [PATCH 007/249] drm: panel: Add Jadard JD9365DA-H3 DSI panel --- drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 691 ++++++++++++++++++ 3 files changed, 702 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 3cd592dc91c76..8820fca12f217 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -202,6 +202,16 @@ config DRM_PANEL_INNOLUX_P079ZCA 24 bit RGB per pixel. It provides a MIPI DSI interface to the host and has a built-in LED backlight. +config DRM_PANEL_JADARD_JD9365DA_H3 + tristate "Jadard JD9365DA-H3 WXGA DSI panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Jadard JD9365DA-H3 + WXGA MIPI DSI panel. The panel support TFT dot matrix LCD with + 800RGBx1280 dots at maximum. + config DRM_PANEL_JDI_LT070ME05000 tristate "JDI LT070ME05000 WUXGA DSI panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 98e0a86a2004e..0b622ddb5d211 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o +obj-$(CONFIG_DRM_PANEL_JADARD_JD9365DA_H3) += panel-jadard-jd9365da-h3.o obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c new file mode 100644 index 0000000000000..6d9cd18af8e80 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + * + * Author: + * - Jagan Teki + * - Stephen Chen + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define JD9365DA_INIT_CMD_LEN 2 + +struct jadard_init_cmd { + u8 data[JD9365DA_INIT_CMD_LEN]; +}; + +struct jadard_panel_desc { + const struct drm_display_mode mode; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + const struct jadard_init_cmd *init_cmds; + u32 num_init_cmds; +}; + +struct jadard { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + const struct jadard_panel_desc *desc; + + struct regulator *vdd; + struct regulator *vccio; + struct gpio_desc *reset; +}; + +static inline struct jadard *panel_to_jadard(struct drm_panel *panel) +{ + return container_of(panel, struct jadard, panel); +} + +static int jadard_enable(struct drm_panel *panel) +{ + struct device *dev = panel->dev; + struct jadard *jadard = panel_to_jadard(panel); + const struct jadard_panel_desc *desc = jadard->desc; + struct mipi_dsi_device *dsi = jadard->dsi; + unsigned int i; + int err; + + msleep(10); + + for (i = 0; i < desc->num_init_cmds; i++) { + const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; + + err = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); + if (err < 0) + return err; + } + + msleep(120); + + err = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (err < 0) + DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err); + + err = mipi_dsi_dcs_set_display_on(dsi); + if (err < 0) + DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err); + + return 0; +} + +static int jadard_disable(struct drm_panel *panel) +{ + struct device *dev = panel->dev; + struct jadard *jadard = panel_to_jadard(panel); + int ret; + + ret = mipi_dsi_dcs_set_display_off(jadard->dsi); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); + + ret = mipi_dsi_dcs_enter_sleep_mode(jadard->dsi); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); + + return 0; +} + +static int jadard_prepare(struct drm_panel *panel) +{ + struct jadard *jadard = panel_to_jadard(panel); + int ret; + + ret = regulator_enable(jadard->vccio); + if (ret) + return ret; + + ret = regulator_enable(jadard->vdd); + if (ret) + return ret; + + gpiod_set_value(jadard->reset, 1); + msleep(120); + + return 0; +} + +static int jadard_unprepare(struct drm_panel *panel) +{ + struct jadard *jadard = panel_to_jadard(panel); + + gpiod_set_value(jadard->reset, 1); + msleep(120); + + regulator_disable(jadard->vdd); + regulator_disable(jadard->vccio); + + return 0; +} + +static int jadard_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct jadard *jadard = panel_to_jadard(panel); + const struct drm_display_mode *desc_mode = &jadard->desc->mode; + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, desc_mode); + if (!mode) { + DRM_DEV_ERROR(&jadard->dsi->dev, "failed to add mode %ux%ux@%u\n", + desc_mode->hdisplay, desc_mode->vdisplay, + drm_mode_vrefresh(desc_mode)); + return -ENOMEM; + } + + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + + return 1; +} + +static const struct drm_panel_funcs jadard_funcs = { + .disable = jadard_disable, + .unprepare = jadard_unprepare, + .prepare = jadard_prepare, + .enable = jadard_enable, + .get_modes = jadard_get_modes, +}; + +static const struct jadard_init_cmd cz101b4001_init_cmds[] = { + { .data = { 0xE0, 0x00 } }, + { .data = { 0xE1, 0x93 } }, + { .data = { 0xE2, 0x65 } }, + { .data = { 0xE3, 0xF8 } }, + { .data = { 0x80, 0x03 } }, + { .data = { 0xE0, 0x01 } }, + { .data = { 0x00, 0x00 } }, + { .data = { 0x01, 0x3B } }, + { .data = { 0x0C, 0x74 } }, + { .data = { 0x17, 0x00 } }, + { .data = { 0x18, 0xAF } }, + { .data = { 0x19, 0x00 } }, + { .data = { 0x1A, 0x00 } }, + { .data = { 0x1B, 0xAF } }, + { .data = { 0x1C, 0x00 } }, + { .data = { 0x35, 0x26 } }, + { .data = { 0x37, 0x09 } }, + { .data = { 0x38, 0x04 } }, + { .data = { 0x39, 0x00 } }, + { .data = { 0x3A, 0x01 } }, + { .data = { 0x3C, 0x78 } }, + { .data = { 0x3D, 0xFF } }, + { .data = { 0x3E, 0xFF } }, + { .data = { 0x3F, 0x7F } }, + { .data = { 0x40, 0x06 } }, + { .data = { 0x41, 0xA0 } }, + { .data = { 0x42, 0x81 } }, + { .data = { 0x43, 0x14 } }, + { .data = { 0x44, 0x23 } }, + { .data = { 0x45, 0x28 } }, + { .data = { 0x55, 0x02 } }, + { .data = { 0x57, 0x69 } }, + { .data = { 0x59, 0x0A } }, + { .data = { 0x5A, 0x2A } }, + { .data = { 0x5B, 0x17 } }, + { .data = { 0x5D, 0x7F } }, + { .data = { 0x5E, 0x6B } }, + { .data = { 0x5F, 0x5C } }, + { .data = { 0x60, 0x4F } }, + { .data = { 0x61, 0x4D } }, + { .data = { 0x62, 0x3F } }, + { .data = { 0x63, 0x42 } }, + { .data = { 0x64, 0x2B } }, + { .data = { 0x65, 0x44 } }, + { .data = { 0x66, 0x43 } }, + { .data = { 0x67, 0x43 } }, + { .data = { 0x68, 0x63 } }, + { .data = { 0x69, 0x52 } }, + { .data = { 0x6A, 0x5A } }, + { .data = { 0x6B, 0x4F } }, + { .data = { 0x6C, 0x4E } }, + { .data = { 0x6D, 0x20 } }, + { .data = { 0x6E, 0x0F } }, + { .data = { 0x6F, 0x00 } }, + { .data = { 0x70, 0x7F } }, + { .data = { 0x71, 0x6B } }, + { .data = { 0x72, 0x5C } }, + { .data = { 0x73, 0x4F } }, + { .data = { 0x74, 0x4D } }, + { .data = { 0x75, 0x3F } }, + { .data = { 0x76, 0x42 } }, + { .data = { 0x77, 0x2B } }, + { .data = { 0x78, 0x44 } }, + { .data = { 0x79, 0x43 } }, + { .data = { 0x7A, 0x43 } }, + { .data = { 0x7B, 0x63 } }, + { .data = { 0x7C, 0x52 } }, + { .data = { 0x7D, 0x5A } }, + { .data = { 0x7E, 0x4F } }, + { .data = { 0x7F, 0x4E } }, + { .data = { 0x80, 0x20 } }, + { .data = { 0x81, 0x0F } }, + { .data = { 0x82, 0x00 } }, + { .data = { 0xE0, 0x02 } }, + { .data = { 0x00, 0x02 } }, + { .data = { 0x01, 0x02 } }, + { .data = { 0x02, 0x00 } }, + { .data = { 0x03, 0x00 } }, + { .data = { 0x04, 0x1E } }, + { .data = { 0x05, 0x1E } }, + { .data = { 0x06, 0x1F } }, + { .data = { 0x07, 0x1F } }, + { .data = { 0x08, 0x1F } }, + { .data = { 0x09, 0x17 } }, + { .data = { 0x0A, 0x17 } }, + { .data = { 0x0B, 0x37 } }, + { .data = { 0x0C, 0x37 } }, + { .data = { 0x0D, 0x47 } }, + { .data = { 0x0E, 0x47 } }, + { .data = { 0x0F, 0x45 } }, + { .data = { 0x10, 0x45 } }, + { .data = { 0x11, 0x4B } }, + { .data = { 0x12, 0x4B } }, + { .data = { 0x13, 0x49 } }, + { .data = { 0x14, 0x49 } }, + { .data = { 0x15, 0x1F } }, + { .data = { 0x16, 0x01 } }, + { .data = { 0x17, 0x01 } }, + { .data = { 0x18, 0x00 } }, + { .data = { 0x19, 0x00 } }, + { .data = { 0x1A, 0x1E } }, + { .data = { 0x1B, 0x1E } }, + { .data = { 0x1C, 0x1F } }, + { .data = { 0x1D, 0x1F } }, + { .data = { 0x1E, 0x1F } }, + { .data = { 0x1F, 0x17 } }, + { .data = { 0x20, 0x17 } }, + { .data = { 0x21, 0x37 } }, + { .data = { 0x22, 0x37 } }, + { .data = { 0x23, 0x46 } }, + { .data = { 0x24, 0x46 } }, + { .data = { 0x25, 0x44 } }, + { .data = { 0x26, 0x44 } }, + { .data = { 0x27, 0x4A } }, + { .data = { 0x28, 0x4A } }, + { .data = { 0x29, 0x48 } }, + { .data = { 0x2A, 0x48 } }, + { .data = { 0x2B, 0x1F } }, + { .data = { 0x2C, 0x01 } }, + { .data = { 0x2D, 0x01 } }, + { .data = { 0x2E, 0x00 } }, + { .data = { 0x2F, 0x00 } }, + { .data = { 0x30, 0x1F } }, + { .data = { 0x31, 0x1F } }, + { .data = { 0x32, 0x1E } }, + { .data = { 0x33, 0x1E } }, + { .data = { 0x34, 0x1F } }, + { .data = { 0x35, 0x17 } }, + { .data = { 0x36, 0x17 } }, + { .data = { 0x37, 0x37 } }, + { .data = { 0x38, 0x37 } }, + { .data = { 0x39, 0x08 } }, + { .data = { 0x3A, 0x08 } }, + { .data = { 0x3B, 0x0A } }, + { .data = { 0x3C, 0x0A } }, + { .data = { 0x3D, 0x04 } }, + { .data = { 0x3E, 0x04 } }, + { .data = { 0x3F, 0x06 } }, + { .data = { 0x40, 0x06 } }, + { .data = { 0x41, 0x1F } }, + { .data = { 0x42, 0x02 } }, + { .data = { 0x43, 0x02 } }, + { .data = { 0x44, 0x00 } }, + { .data = { 0x45, 0x00 } }, + { .data = { 0x46, 0x1F } }, + { .data = { 0x47, 0x1F } }, + { .data = { 0x48, 0x1E } }, + { .data = { 0x49, 0x1E } }, + { .data = { 0x4A, 0x1F } }, + { .data = { 0x4B, 0x17 } }, + { .data = { 0x4C, 0x17 } }, + { .data = { 0x4D, 0x37 } }, + { .data = { 0x4E, 0x37 } }, + { .data = { 0x4F, 0x09 } }, + { .data = { 0x50, 0x09 } }, + { .data = { 0x51, 0x0B } }, + { .data = { 0x52, 0x0B } }, + { .data = { 0x53, 0x05 } }, + { .data = { 0x54, 0x05 } }, + { .data = { 0x55, 0x07 } }, + { .data = { 0x56, 0x07 } }, + { .data = { 0x57, 0x1F } }, + { .data = { 0x58, 0x40 } }, + { .data = { 0x5B, 0x30 } }, + { .data = { 0x5C, 0x16 } }, + { .data = { 0x5D, 0x34 } }, + { .data = { 0x5E, 0x05 } }, + { .data = { 0x5F, 0x02 } }, + { .data = { 0x63, 0x00 } }, + { .data = { 0x64, 0x6A } }, + { .data = { 0x67, 0x73 } }, + { .data = { 0x68, 0x1D } }, + { .data = { 0x69, 0x08 } }, + { .data = { 0x6A, 0x6A } }, + { .data = { 0x6B, 0x08 } }, + { .data = { 0x6C, 0x00 } }, + { .data = { 0x6D, 0x00 } }, + { .data = { 0x6E, 0x00 } }, + { .data = { 0x6F, 0x88 } }, + { .data = { 0x75, 0xFF } }, + { .data = { 0x77, 0xDD } }, + { .data = { 0x78, 0x3F } }, + { .data = { 0x79, 0x15 } }, + { .data = { 0x7A, 0x17 } }, + { .data = { 0x7D, 0x14 } }, + { .data = { 0x7E, 0x82 } }, + { .data = { 0xE0, 0x04 } }, + { .data = { 0x00, 0x0E } }, + { .data = { 0x02, 0xB3 } }, + { .data = { 0x09, 0x61 } }, + { .data = { 0x0E, 0x48 } }, + { .data = { 0xE0, 0x00 } }, + { .data = { 0xE6, 0x02 } }, + { .data = { 0xE7, 0x0C } }, +}; + +static const struct jadard_panel_desc cz101b4001_desc = { + .mode = { + .clock = 70000, + + .hdisplay = 800, + .hsync_start = 800 + 40, + .hsync_end = 800 + 40 + 18, + .htotal = 800 + 40 + 18 + 20, + + .vdisplay = 1280, + .vsync_start = 1280 + 20, + .vsync_end = 1280 + 20 + 4, + .vtotal = 1280 + 20 + 4 + 20, + + .width_mm = 62, + .height_mm = 110, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .init_cmds = cz101b4001_init_cmds, + .num_init_cmds = ARRAY_SIZE(cz101b4001_init_cmds), +}; + +static const struct jadard_init_cmd radxa_display_10hd_ad001_init_cmds[] = { + { .data = { 0xE0, 0x00 } }, + { .data = { 0xE1, 0x93 } }, + { .data = { 0xE2, 0x65 } }, + { .data = { 0xE3, 0xF8 } }, + { .data = { 0x80, 0x03 } }, + { .data = { 0xE0, 0x01 } }, + { .data = { 0x00, 0x00 } }, + { .data = { 0x01, 0x3B } }, + { .data = { 0x0C, 0x74 } }, + { .data = { 0x17, 0x00 } }, + { .data = { 0x18, 0xAF } }, + { .data = { 0x19, 0x00 } }, + { .data = { 0x1A, 0x00 } }, + { .data = { 0x1B, 0xAF } }, + { .data = { 0x1C, 0x00 } }, + { .data = { 0x35, 0x26 } }, + { .data = { 0x37, 0x09 } }, + { .data = { 0x38, 0x04 } }, + { .data = { 0x39, 0x00 } }, + { .data = { 0x3A, 0x01 } }, + { .data = { 0x3C, 0x78 } }, + { .data = { 0x3D, 0xFF } }, + { .data = { 0x3E, 0xFF } }, + { .data = { 0x3F, 0x7F } }, + { .data = { 0x40, 0x06 } }, + { .data = { 0x41, 0xA0 } }, + { .data = { 0x42, 0x81 } }, + { .data = { 0x43, 0x14 } }, + { .data = { 0x44, 0x23 } }, + { .data = { 0x45, 0x28 } }, + { .data = { 0x55, 0x02 } }, + { .data = { 0x57, 0x69 } }, + { .data = { 0x59, 0x0A } }, + { .data = { 0x5A, 0x2A } }, + { .data = { 0x5B, 0x17 } }, + { .data = { 0x5D, 0x7F } }, + { .data = { 0x5E, 0x6B } }, + { .data = { 0x5F, 0x5C } }, + { .data = { 0x60, 0x4F } }, + { .data = { 0x61, 0x4D } }, + { .data = { 0x62, 0x3F } }, + { .data = { 0x63, 0x42 } }, + { .data = { 0x64, 0x2B } }, + { .data = { 0x65, 0x44 } }, + { .data = { 0x66, 0x43 } }, + { .data = { 0x67, 0x43 } }, + { .data = { 0x68, 0x63 } }, + { .data = { 0x69, 0x52 } }, + { .data = { 0x6A, 0x5A } }, + { .data = { 0x6B, 0x4F } }, + { .data = { 0x6C, 0x4E } }, + { .data = { 0x6D, 0x20 } }, + { .data = { 0x6E, 0x0F } }, + { .data = { 0x6F, 0x00 } }, + { .data = { 0x70, 0x7F } }, + { .data = { 0x71, 0x6B } }, + { .data = { 0x72, 0x5C } }, + { .data = { 0x73, 0x4F } }, + { .data = { 0x74, 0x4D } }, + { .data = { 0x75, 0x3F } }, + { .data = { 0x76, 0x42 } }, + { .data = { 0x77, 0x2B } }, + { .data = { 0x78, 0x44 } }, + { .data = { 0x79, 0x43 } }, + { .data = { 0x7A, 0x43 } }, + { .data = { 0x7B, 0x63 } }, + { .data = { 0x7C, 0x52 } }, + { .data = { 0x7D, 0x5A } }, + { .data = { 0x7E, 0x4F } }, + { .data = { 0x7F, 0x4E } }, + { .data = { 0x80, 0x20 } }, + { .data = { 0x81, 0x0F } }, + { .data = { 0x82, 0x00 } }, + { .data = { 0xE0, 0x02 } }, + { .data = { 0x00, 0x02 } }, + { .data = { 0x01, 0x02 } }, + { .data = { 0x02, 0x00 } }, + { .data = { 0x03, 0x00 } }, + { .data = { 0x04, 0x1E } }, + { .data = { 0x05, 0x1E } }, + { .data = { 0x06, 0x1F } }, + { .data = { 0x07, 0x1F } }, + { .data = { 0x08, 0x1F } }, + { .data = { 0x09, 0x17 } }, + { .data = { 0x0A, 0x17 } }, + { .data = { 0x0B, 0x37 } }, + { .data = { 0x0C, 0x37 } }, + { .data = { 0x0D, 0x47 } }, + { .data = { 0x0E, 0x47 } }, + { .data = { 0x0F, 0x45 } }, + { .data = { 0x10, 0x45 } }, + { .data = { 0x11, 0x4B } }, + { .data = { 0x12, 0x4B } }, + { .data = { 0x13, 0x49 } }, + { .data = { 0x14, 0x49 } }, + { .data = { 0x15, 0x1F } }, + { .data = { 0x16, 0x01 } }, + { .data = { 0x17, 0x01 } }, + { .data = { 0x18, 0x00 } }, + { .data = { 0x19, 0x00 } }, + { .data = { 0x1A, 0x1E } }, + { .data = { 0x1B, 0x1E } }, + { .data = { 0x1C, 0x1F } }, + { .data = { 0x1D, 0x1F } }, + { .data = { 0x1E, 0x1F } }, + { .data = { 0x1F, 0x17 } }, + { .data = { 0x20, 0x17 } }, + { .data = { 0x21, 0x37 } }, + { .data = { 0x22, 0x37 } }, + { .data = { 0x23, 0x46 } }, + { .data = { 0x24, 0x46 } }, + { .data = { 0x25, 0x44 } }, + { .data = { 0x26, 0x44 } }, + { .data = { 0x27, 0x4A } }, + { .data = { 0x28, 0x4A } }, + { .data = { 0x29, 0x48 } }, + { .data = { 0x2A, 0x48 } }, + { .data = { 0x2B, 0x1F } }, + { .data = { 0x2C, 0x01 } }, + { .data = { 0x2D, 0x01 } }, + { .data = { 0x2E, 0x00 } }, + { .data = { 0x2F, 0x00 } }, + { .data = { 0x30, 0x1F } }, + { .data = { 0x31, 0x1F } }, + { .data = { 0x32, 0x1E } }, + { .data = { 0x33, 0x1E } }, + { .data = { 0x34, 0x1F } }, + { .data = { 0x35, 0x17 } }, + { .data = { 0x36, 0x17 } }, + { .data = { 0x37, 0x37 } }, + { .data = { 0x38, 0x37 } }, + { .data = { 0x39, 0x08 } }, + { .data = { 0x3A, 0x08 } }, + { .data = { 0x3B, 0x0A } }, + { .data = { 0x3C, 0x0A } }, + { .data = { 0x3D, 0x04 } }, + { .data = { 0x3E, 0x04 } }, + { .data = { 0x3F, 0x06 } }, + { .data = { 0x40, 0x06 } }, + { .data = { 0x41, 0x1F } }, + { .data = { 0x42, 0x02 } }, + { .data = { 0x43, 0x02 } }, + { .data = { 0x44, 0x00 } }, + { .data = { 0x45, 0x00 } }, + { .data = { 0x46, 0x1F } }, + { .data = { 0x47, 0x1F } }, + { .data = { 0x48, 0x1E } }, + { .data = { 0x49, 0x1E } }, + { .data = { 0x4A, 0x1F } }, + { .data = { 0x4B, 0x17 } }, + { .data = { 0x4C, 0x17 } }, + { .data = { 0x4D, 0x37 } }, + { .data = { 0x4E, 0x37 } }, + { .data = { 0x4F, 0x09 } }, + { .data = { 0x50, 0x09 } }, + { .data = { 0x51, 0x0B } }, + { .data = { 0x52, 0x0B } }, + { .data = { 0x53, 0x05 } }, + { .data = { 0x54, 0x05 } }, + { .data = { 0x55, 0x07 } }, + { .data = { 0x56, 0x07 } }, + { .data = { 0x57, 0x1F } }, + { .data = { 0x58, 0x40 } }, + { .data = { 0x5B, 0x30 } }, + { .data = { 0x5C, 0x16 } }, + { .data = { 0x5D, 0x34 } }, + { .data = { 0x5E, 0x05 } }, + { .data = { 0x5F, 0x02 } }, + { .data = { 0x63, 0x00 } }, + { .data = { 0x64, 0x6A } }, + { .data = { 0x67, 0x73 } }, + { .data = { 0x68, 0x1D } }, + { .data = { 0x69, 0x08 } }, + { .data = { 0x6A, 0x6A } }, + { .data = { 0x6B, 0x08 } }, + { .data = { 0x6C, 0x00 } }, + { .data = { 0x6D, 0x00 } }, + { .data = { 0x6E, 0x00 } }, + { .data = { 0x6F, 0x88 } }, + { .data = { 0x75, 0xFF } }, + { .data = { 0x77, 0xDD } }, + { .data = { 0x78, 0x3F } }, + { .data = { 0x79, 0x15 } }, + { .data = { 0x7A, 0x17 } }, + { .data = { 0x7D, 0x14 } }, + { .data = { 0x7E, 0x82 } }, + { .data = { 0xE0, 0x04 } }, + { .data = { 0x00, 0x0E } }, + { .data = { 0x02, 0xB3 } }, + { .data = { 0x09, 0x61 } }, + { .data = { 0x0E, 0x48 } }, + { .data = { 0xE0, 0x00 } }, + { .data = { 0xE6, 0x02 } }, + { .data = { 0xE7, 0x0C } }, +}; + +static const struct jadard_panel_desc radxa_display_10hd_ad001_desc = { + .mode = { + .clock = 70000, + + .hdisplay = 800, + .hsync_start = 800 + 40, + .hsync_end = 800 + 40 + 18, + .htotal = 800 + 40 + 18 + 20, + + .vdisplay = 1280, + .vsync_start = 1280 + 20, + .vsync_end = 1280 + 20 + 4, + .vtotal = 1280 + 20 + 4 + 20, + + .width_mm = 135, + .height_mm = 216, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .init_cmds = cz101b4001_init_cmds, + .num_init_cmds = ARRAY_SIZE(radxa_display_10hd_ad001_init_cmds), +}; + +static int jadard_dsi_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + const struct jadard_panel_desc *desc; + struct jadard *jadard; + int ret; + + jadard = devm_kzalloc(&dsi->dev, sizeof(*jadard), GFP_KERNEL); + if (!jadard) + return -ENOMEM; + + desc = of_device_get_match_data(dev); + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_EOT_PACKET; + dsi->format = desc->format; + dsi->lanes = desc->lanes; + + jadard->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(jadard->reset)) { + DRM_DEV_ERROR(&dsi->dev, "failed to get our reset GPIO\n"); + return PTR_ERR(jadard->reset); + } + + jadard->vdd = devm_regulator_get(dev, "vdd"); + if (IS_ERR(jadard->vdd)) { + DRM_DEV_ERROR(&dsi->dev, "failed to get vdd regulator\n"); + return PTR_ERR(jadard->vdd); + } + + jadard->vccio = devm_regulator_get(dev, "vccio"); + if (IS_ERR(jadard->vccio)) { + DRM_DEV_ERROR(&dsi->dev, "failed to get vccio regulator\n"); + return PTR_ERR(jadard->vccio); + } + + drm_panel_init(&jadard->panel, dev, &jadard_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret = drm_panel_of_backlight(&jadard->panel); + if (ret) + return ret; + + drm_panel_add(&jadard->panel); + + mipi_dsi_set_drvdata(dsi, jadard); + jadard->dsi = dsi; + jadard->desc = desc; + + ret = mipi_dsi_attach(dsi); + if (ret < 0) + drm_panel_remove(&jadard->panel); + + return ret; +} + +static int jadard_dsi_remove(struct mipi_dsi_device *dsi) +{ + struct jadard *jadard = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&jadard->panel); + + return 0; +} + +static const struct of_device_id jadard_of_match[] = { + { .compatible = "chongzhou,cz101b4001", .data = &cz101b4001_desc }, + { .compatible = "radxa,display-10hd-ad001", .data = &radxa_display_10hd_ad001_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jadard_of_match); + +static struct mipi_dsi_driver jadard_driver = { + .probe = jadard_dsi_probe, + .remove = jadard_dsi_remove, + .driver = { + .name = "jadard-jd9365da", + .of_match_table = jadard_of_match, + }, +}; +module_mipi_dsi_driver(jadard_driver); + +MODULE_AUTHOR("Jagan Teki "); +MODULE_AUTHOR("Stephen Chen "); +MODULE_DESCRIPTION("Jadard JD9365DA-H3 WXGA DSI panel"); +MODULE_LICENSE("GPL"); From 5a3c86c527ae19ff2403fced6ff57d4dc3b3608e Mon Sep 17 00:00:00 2001 From: Stephen Chen Date: Fri, 18 Nov 2022 18:15:09 +0800 Subject: [PATCH 008/249] drm: panel: add radxa display 8hd panel Signed-off-by: Stephen Chen --- drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-radxa-display-8hd.c | 441 ++++++++++++++++++ 3 files changed, 451 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-radxa-display-8hd.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 8820fca12f217..0cd428ad5c675 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -434,6 +434,15 @@ config DRM_PANEL_PANASONIC_VVX10F034N00 WUXGA (1920x1200) Novatek NT1397-based DSI panel as found in some Xperia Z2 tablets +config DRM_PANEL_RADXA_DISPLAY_8HD + tristate "Radxa Display 8HD panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Radxa Display 8HD panel. + The panel support TFT dot matrix LCD with 800RGBx1280 dots at maximum. + config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN tristate "Raspberry Pi 7-inch touchscreen panel" depends on DRM_MIPI_DSI diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 0b622ddb5d211..61d09b6420398 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o obj-$(CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS) += panel-osd-osd101t2587-53ts.o obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o +obj-$(CONFIG_DRM_PANEL_RADXA_DISPLAY_8HD) += panel-radxa-display-8hd.o obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o diff --git a/drivers/gpu/drm/panel/panel-radxa-display-8hd.c b/drivers/gpu/drm/panel/panel-radxa-display-8hd.c new file mode 100644 index 0000000000000..ef3b8fb6d463d --- /dev/null +++ b/drivers/gpu/drm/panel/panel-radxa-display-8hd.c @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Radxa Limited + * + * Author: + * - Stephen Chen + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define JADARD_JD9365DA_INIT_CMD_LEN 2 + +struct jadard_jd9365da_init_cmd { + u8 data[JADARD_JD9365DA_INIT_CMD_LEN]; +}; + +struct jadard_jd9365da_panel_desc { + const struct drm_display_mode mode; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + const struct jadard_jd9365da_init_cmd *init_cmds; + u32 num_init_cmds; +}; + +struct jadard_jd9365da { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + const struct jadard_jd9365da_panel_desc *desc; + + struct regulator *vdd; + struct regulator *vccio; + struct gpio_desc *reset; +}; + +static inline struct jadard_jd9365da *panel_to_jadard_jd9365da(struct drm_panel *panel) +{ + return container_of(panel, struct jadard_jd9365da, panel); +} + +static int jadard_jd9365da_prepare(struct drm_panel *panel) +{ + struct jadard_jd9365da *jadard_jd9365da = panel_to_jadard_jd9365da(panel); + int ret; + + ret = regulator_enable(jadard_jd9365da->vccio); + if (ret) + return ret; + + ret = regulator_enable(jadard_jd9365da->vdd); + if (ret) + return ret; + + gpiod_set_value(jadard_jd9365da->reset, 1); + msleep(120); + + return 0; +} + +static int jadard_jd9365da_enable(struct drm_panel *panel) +{ + struct device *dev = panel->dev; + struct jadard_jd9365da *jadard_jd9365da = panel_to_jadard_jd9365da(panel); + const struct jadard_jd9365da_panel_desc *desc = jadard_jd9365da->desc; + struct mipi_dsi_device *dsi = jadard_jd9365da->dsi; + unsigned int i; + int err; + + msleep(10); + + for (i = 0; i < desc->num_init_cmds; i++) { + const struct jadard_jd9365da_init_cmd *cmd = &desc->init_cmds[i]; + + err = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JADARD_JD9365DA_INIT_CMD_LEN); + if (err < 0) + return err; + } + + msleep(120); + + err = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (err < 0) + DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err); + + err = mipi_dsi_dcs_set_display_on(dsi); + if (err < 0) + DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err); + + return 0; +} + +static int jadard_jd9365da_disable(struct drm_panel *panel) +{ + struct device *dev = panel->dev; + struct jadard_jd9365da *jadard_jd9365da = panel_to_jadard_jd9365da(panel); + int ret; + + ret = mipi_dsi_dcs_set_display_off(jadard_jd9365da->dsi); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); + + ret = mipi_dsi_dcs_enter_sleep_mode(jadard_jd9365da->dsi); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); + + return 0; +} + +static int jadard_jd9365da_unprepare(struct drm_panel *panel) +{ + struct jadard_jd9365da *jadard_jd9365da = panel_to_jadard_jd9365da(panel); + + gpiod_set_value(jadard_jd9365da->reset, 1); + msleep(120); + + regulator_disable(jadard_jd9365da->vdd); + regulator_disable(jadard_jd9365da->vccio); + + return 0; +} + +static int jadard_jd9365da_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct jadard_jd9365da *jadard_jd9365da = panel_to_jadard_jd9365da(panel); + const struct drm_display_mode *desc_mode = &jadard_jd9365da->desc->mode; + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, desc_mode); + if (!mode) { + DRM_DEV_ERROR(&jadard_jd9365da->dsi->dev, "failed to add mode %ux%ux@%u\n", + desc_mode->hdisplay, desc_mode->vdisplay, + drm_mode_vrefresh(desc_mode)); + return -ENOMEM; + } + + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + + return 1; +} + +static const struct drm_panel_funcs jadard_jd9365da_funcs = { + .prepare = jadard_jd9365da_prepare, + .enable = jadard_jd9365da_enable, + .disable = jadard_jd9365da_disable, + .unprepare = jadard_jd9365da_unprepare, + .get_modes = jadard_jd9365da_get_modes, +}; + +static const struct jadard_jd9365da_init_cmd radxa_display_8hd_init_cmds[] = { + { .data = { 0xE0, 0x00 } }, + { .data = { 0xE1, 0x93 } }, + { .data = { 0xE2, 0x65 } }, + { .data = { 0xE3, 0xF8 } }, + { .data = { 0x80, 0x03 } }, + { .data = { 0xE0, 0x01 } }, + { .data = { 0x00, 0x00 } }, + { .data = { 0x01, 0x7E } }, + { .data = { 0x03, 0x00 } }, + { .data = { 0x04, 0x65 } }, + { .data = { 0x0C, 0x74 } }, + { .data = { 0x17, 0x00 } }, + { .data = { 0x18, 0xB7 } }, + { .data = { 0x19, 0x00 } }, + { .data = { 0x1A, 0x00 } }, + { .data = { 0x1B, 0xB7 } }, + { .data = { 0x1C, 0x00 } }, + { .data = { 0x24, 0xFE } }, + { .data = { 0x37, 0x19 } }, + { .data = { 0x38, 0x05 } }, + { .data = { 0x39, 0x00 } }, + { .data = { 0x3A, 0x01 } }, + { .data = { 0x3B, 0x01 } }, + { .data = { 0x3C, 0x70 } }, + { .data = { 0x3D, 0xFF } }, + { .data = { 0x3E, 0xFF } }, + { .data = { 0x3F, 0xFF } }, + { .data = { 0x40, 0x06 } }, + { .data = { 0x41, 0xA0 } }, + { .data = { 0x43, 0x1E } }, + { .data = { 0x44, 0x0F } }, + { .data = { 0x45, 0x28 } }, + { .data = { 0x4B, 0x04 } }, + { .data = { 0x55, 0x02 } }, + { .data = { 0x56, 0x01 } }, + { .data = { 0x57, 0xA9 } }, + { .data = { 0x58, 0x0A } }, + { .data = { 0x59, 0x0A } }, + { .data = { 0x5A, 0x37 } }, + { .data = { 0x5B, 0x19 } }, + { .data = { 0x5D, 0x78 } }, + { .data = { 0x5E, 0x63 } }, + { .data = { 0x5F, 0x54 } }, + { .data = { 0x60, 0x49 } }, + { .data = { 0x61, 0x45 } }, + { .data = { 0x62, 0x38 } }, + { .data = { 0x63, 0x3D } }, + { .data = { 0x64, 0x28 } }, + { .data = { 0x65, 0x43 } }, + { .data = { 0x66, 0x41 } }, + { .data = { 0x67, 0x43 } }, + { .data = { 0x68, 0x62 } }, + { .data = { 0x69, 0x50 } }, + { .data = { 0x6A, 0x57 } }, + { .data = { 0x6B, 0x49 } }, + { .data = { 0x6C, 0x44 } }, + { .data = { 0x6D, 0x37 } }, + { .data = { 0x6E, 0x23 } }, + { .data = { 0x6F, 0x10 } }, + { .data = { 0x70, 0x78 } }, + { .data = { 0x71, 0x63 } }, + { .data = { 0x72, 0x54 } }, + { .data = { 0x73, 0x49 } }, + { .data = { 0x74, 0x45 } }, + { .data = { 0x75, 0x38 } }, + { .data = { 0x76, 0x3D } }, + { .data = { 0x77, 0x28 } }, + { .data = { 0x78, 0x43 } }, + { .data = { 0x79, 0x41 } }, + { .data = { 0x7A, 0x43 } }, + { .data = { 0x7B, 0x62 } }, + { .data = { 0x7C, 0x50 } }, + { .data = { 0x7D, 0x57 } }, + { .data = { 0x7E, 0x49 } }, + { .data = { 0x7F, 0x44 } }, + { .data = { 0x80, 0x37 } }, + { .data = { 0x81, 0x23 } }, + { .data = { 0x82, 0x10 } }, + { .data = { 0xE0, 0x02 } }, + { .data = { 0x00, 0x47 } }, + { .data = { 0x01, 0x47 } }, + { .data = { 0x02, 0x45 } }, + { .data = { 0x03, 0x45 } }, + { .data = { 0x04, 0x4B } }, + { .data = { 0x05, 0x4B } }, + { .data = { 0x06, 0x49 } }, + { .data = { 0x07, 0x49 } }, + { .data = { 0x08, 0x41 } }, + { .data = { 0x09, 0x1F } }, + { .data = { 0x0A, 0x1F } }, + { .data = { 0x0B, 0x1F } }, + { .data = { 0x0C, 0x1F } }, + { .data = { 0x0D, 0x1F } }, + { .data = { 0x0E, 0x1F } }, + { .data = { 0x0F, 0x5F } }, + { .data = { 0x10, 0x5F } }, + { .data = { 0x11, 0x57 } }, + { .data = { 0x12, 0x77 } }, + { .data = { 0x13, 0x35 } }, + { .data = { 0x14, 0x1F } }, + { .data = { 0x15, 0x1F } }, + { .data = { 0x16, 0x46 } }, + { .data = { 0x17, 0x46 } }, + { .data = { 0x18, 0x44 } }, + { .data = { 0x19, 0x44 } }, + { .data = { 0x1A, 0x4A } }, + { .data = { 0x1B, 0x4A } }, + { .data = { 0x1C, 0x48 } }, + { .data = { 0x1D, 0x48 } }, + { .data = { 0x1E, 0x40 } }, + { .data = { 0x1F, 0x1F } }, + { .data = { 0x20, 0x1F } }, + { .data = { 0x21, 0x1F } }, + { .data = { 0x22, 0x1F } }, + { .data = { 0x23, 0x1F } }, + { .data = { 0x24, 0x1F } }, + { .data = { 0x25, 0x5F } }, + { .data = { 0x26, 0x5F } }, + { .data = { 0x27, 0x57 } }, + { .data = { 0x28, 0x77 } }, + { .data = { 0x29, 0x35 } }, + { .data = { 0x2A, 0x1F } }, + { .data = { 0x2B, 0x1F } }, + { .data = { 0x58, 0x40 } }, + { .data = { 0x59, 0x00 } }, + { .data = { 0x5A, 0x00 } }, + { .data = { 0x5B, 0x10 } }, + { .data = { 0x5C, 0x06 } }, + { .data = { 0x5D, 0x40 } }, + { .data = { 0x5E, 0x01 } }, + { .data = { 0x5F, 0x02 } }, + { .data = { 0x60, 0x30 } }, + { .data = { 0x61, 0x01 } }, + { .data = { 0x62, 0x02 } }, + { .data = { 0x63, 0x03 } }, + { .data = { 0x64, 0x6B } }, + { .data = { 0x65, 0x05 } }, + { .data = { 0x66, 0x0C } }, + { .data = { 0x67, 0x73 } }, + { .data = { 0x68, 0x09 } }, + { .data = { 0x69, 0x03 } }, + { .data = { 0x6A, 0x56 } }, + { .data = { 0x6B, 0x08 } }, + { .data = { 0x6C, 0x00 } }, + { .data = { 0x6D, 0x04 } }, + { .data = { 0x6E, 0x04 } }, + { .data = { 0x6F, 0x88 } }, + { .data = { 0x70, 0x00 } }, + { .data = { 0x71, 0x00 } }, + { .data = { 0x72, 0x06 } }, + { .data = { 0x73, 0x7B } }, + { .data = { 0x74, 0x00 } }, + { .data = { 0x75, 0xF8 } }, + { .data = { 0x76, 0x00 } }, + { .data = { 0x77, 0xD5 } }, + { .data = { 0x78, 0x2E } }, + { .data = { 0x79, 0x12 } }, + { .data = { 0x7A, 0x03 } }, + { .data = { 0x7B, 0x00 } }, + { .data = { 0x7C, 0x00 } }, + { .data = { 0x7D, 0x03 } }, + { .data = { 0x7E, 0x7B } }, + { .data = { 0xE0, 0x04 } }, + { .data = { 0x00, 0x0E } }, + { .data = { 0x02, 0xB3 } }, + { .data = { 0x09, 0x60 } }, + { .data = { 0x0E, 0x2A } }, + { .data = { 0x36, 0x59 } }, + { .data = { 0xE0, 0x00 } }, +}; + +static const struct jadard_jd9365da_panel_desc radxa_display_8hd_desc = { + .mode = { + .clock = 70000, + + .hdisplay = 800, + .hsync_start = 800 + 40, + .hsync_end = 800 + 40 + 18, + .htotal = 800 + 40 + 18 + 20, + + .vdisplay = 1280, + .vsync_start = 1280 + 20, + .vsync_end = 1280 + 20 + 4, + .vtotal = 1280 + 20 + 4 + 20, + + .width_mm = 127, + .height_mm = 199, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .init_cmds = radxa_display_8hd_init_cmds, + .num_init_cmds = ARRAY_SIZE(radxa_display_8hd_init_cmds), +}; + +static int radxa_display_8hd_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + const struct jadard_jd9365da_panel_desc *desc; + struct jadard_jd9365da *jadard_jd9365da; + int ret; + + jadard_jd9365da = devm_kzalloc(&dsi->dev, sizeof(jadard_jd9365da), GFP_KERNEL); + if (!jadard_jd9365da) + return -ENOMEM; + + desc = of_device_get_match_data(dev); + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_EOT_PACKET; + dsi->format = desc->format; + dsi->lanes = desc->lanes; + + jadard_jd9365da->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(jadard_jd9365da->reset)) { + DRM_DEV_ERROR(&dsi->dev, "failed to get reset GPIO\n"); + return PTR_ERR(jadard_jd9365da->reset); + } + + jadard_jd9365da->vdd = devm_regulator_get(dev, "vdd"); + if (IS_ERR(jadard_jd9365da->vdd)) { + DRM_DEV_ERROR(&dsi->dev, "failed to get vdd regulator\n"); + return PTR_ERR(jadard_jd9365da->vdd); + } + + jadard_jd9365da->vccio = devm_regulator_get(dev, "vccio"); + if (IS_ERR(jadard_jd9365da->vccio)) { + DRM_DEV_ERROR(&dsi->dev, "failed to get vccio regulator"); + return PTR_ERR(jadard_jd9365da->vccio); + } + + drm_panel_init(&jadard_jd9365da->panel, dev, &jadard_jd9365da_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret = drm_panel_of_backlight(&jadard_jd9365da->panel); + if (ret) + return ret; + + drm_panel_add(&jadard_jd9365da->panel); + + mipi_dsi_set_drvdata(dsi, jadard_jd9365da); + jadard_jd9365da->dsi = dsi; + jadard_jd9365da->desc = desc; + + ret = mipi_dsi_attach(dsi); + if (ret < 0) + drm_panel_remove(&jadard_jd9365da->panel); + + return ret; +} + +static int radxa_display_8hd_remove(struct mipi_dsi_device *dsi) +{ + struct jadard_jd9365da *jadard_jd9365da = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&jadard_jd9365da->panel); + + return 0; +} + +static const struct of_device_id radxa_display_8hd_of_match[] = { + { .compatible = "radxa,display-8hd", .data = &radxa_display_8hd_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, radxa_display_8hd_of_match); + +static struct mipi_dsi_driver radxa_display_8hd_driver = { + .probe = radxa_display_8hd_probe, + .remove = radxa_display_8hd_remove, + .driver = { + .name = "radxa_display_8hd", + .of_match_table = radxa_display_8hd_of_match, + }, +}; +module_mipi_dsi_driver(radxa_display_8hd_driver); + +MODULE_AUTHOR("Stephen Chen "); +MODULE_DESCRIPTION("Radxa Display 8HD panel driver"); +MODULE_LICENSE("GPL v2"); From c48dfdbcd4e5dd9a1dcb42d75feeed42db3772a7 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Thu, 2 Mar 2023 15:17:31 +0800 Subject: [PATCH 009/249] drm/panel/raspberrypi-touchscreen: modified by radxa --- .../drm/panel/panel-raspberrypi-touchscreen.c | 43 +++++++++++-------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c index 79f852465a846..fdf3ec84d3e58 100644 --- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c +++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c @@ -201,15 +201,16 @@ static const struct drm_display_mode rpi_touchscreen_modes[] = { /* Modeline comes from the Raspberry Pi firmware, with HFP=1 * plugged in and clock re-computed from that. */ - .clock = 25979400 / 1000, + .clock = 26000000 / 1000, .hdisplay = 800, .hsync_start = 800 + 1, - .hsync_end = 800 + 1 + 2, - .htotal = 800 + 1 + 2 + 46, + .hsync_end = 800 + 1 + 5, + .htotal = 800 + 1 + 5 + 48, .vdisplay = 480, .vsync_start = 480 + 7, - .vsync_end = 480 + 7 + 2, - .vtotal = 480 + 7 + 2 + 21, + .vsync_end = 480 + 7 + 1, + .vtotal = 480 + 7 + 1 + 21, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, }, }; @@ -255,7 +256,7 @@ static int rpi_touchscreen_disable(struct drm_panel *panel) rpi_touchscreen_i2c_write(ts, REG_PWM, 0); - rpi_touchscreen_i2c_write(ts, REG_POWERON, 0); + //rpi_touchscreen_i2c_write(ts, REG_POWERON, 0); udelay(1); return 0; @@ -278,17 +279,22 @@ static int rpi_touchscreen_prepare(struct drm_panel *panel) break; } - rpi_touchscreen_write(ts, DSI_LANEENABLE, - DSI_LANEENABLE_CLOCK | - DSI_LANEENABLE_D0); - rpi_touchscreen_write(ts, PPI_D0S_CLRSIPOCOUNT, 0x05); - rpi_touchscreen_write(ts, PPI_D1S_CLRSIPOCOUNT, 0x05); + rpi_touchscreen_write(ts, DSI_LANEENABLE, 0x03); + rpi_touchscreen_write(ts, PPI_D0S_CLRSIPOCOUNT, 0x0c); + rpi_touchscreen_write(ts, PPI_D1S_CLRSIPOCOUNT, 0x0c); rpi_touchscreen_write(ts, PPI_D0S_ATMR, 0x00); rpi_touchscreen_write(ts, PPI_D1S_ATMR, 0x00); - rpi_touchscreen_write(ts, PPI_LPTXTIMECNT, 0x03); + rpi_touchscreen_write(ts, PPI_LPTXTIMECNT, 0x15); + + rpi_touchscreen_write(ts, SPICMR, 0x60); + rpi_touchscreen_write(ts, LCDCTRL, 0x00100152); + + rpi_touchscreen_write(ts, HSR, 0x001a0014); + rpi_touchscreen_write(ts, HDISPR, 0x00690320); + rpi_touchscreen_write(ts, VSR, 0x00150002); + rpi_touchscreen_write(ts, VDISPR, 0x000701e0); + rpi_touchscreen_write(ts, VFUEN, 0x01); - rpi_touchscreen_write(ts, SPICMR, 0x00); - rpi_touchscreen_write(ts, LCDCTRL, 0x00100150); rpi_touchscreen_write(ts, SYSCTRL, 0x040f); msleep(100); @@ -346,8 +352,8 @@ static int rpi_touchscreen_get_modes(struct drm_panel *panel, } connector->display_info.bpc = 8; - connector->display_info.width_mm = 154; - connector->display_info.height_mm = 86; + connector->display_info.width_mm = 217; + connector->display_info.height_mm = 136; drm_display_info_set_bus_formats(&connector->display_info, &bus_format, 1); @@ -462,8 +468,9 @@ static int rpi_touchscreen_dsi_probe(struct mipi_dsi_device *dsi) int ret; dsi->mode_flags = (MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM); + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_NO_HBP); + dsi->format = MIPI_DSI_FMT_RGB888; dsi->lanes = 1; From 0ff98cdbecdd406ebab31a42f594224de9643554 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Thu, 2 Mar 2023 15:19:48 +0800 Subject: [PATCH 010/249] extcon: Add Type-C Virtual PD driver --- drivers/extcon/Kconfig | 10 + drivers/extcon/Makefile | 1 + drivers/extcon/extcon-pd-virtual.c | 429 +++++++++++++++++++++++++++++ 3 files changed, 440 insertions(+) create mode 100644 drivers/extcon/extcon-pd-virtual.c diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index 4dd52a6a5b48d..f6941353b58e7 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -190,4 +190,14 @@ config EXTCON_USBC_TUSB320 Say Y here to enable support for USB Type C cable detection extcon support using a TUSB320. +config EXTCON_USBC_VIRTUAL_PD + tristate "Virtual Type-C PD EXTCON support" + depends on GPIOLIB || COMPILE_TEST + help + Say Y here to enable Virtual Type-C PD extcon driver support, if + hardware platform designed Type-C modes separately. + + Example, of designing Display Port separately from Type-C Altmode + instead of accessing Altmode Display Port in Type-C connector. + endif diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile index 1b390d934ca92..306019ae9c37b 100644 --- a/drivers/extcon/Makefile +++ b/drivers/extcon/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_EXTCON_SM5502) += extcon-sm5502.o obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o +obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-pd-virtual.o \ No newline at end of file diff --git a/drivers/extcon/extcon-pd-virtual.c b/drivers/extcon/extcon-pd-virtual.c new file mode 100644 index 0000000000000..b186ea5eb2850 --- /dev/null +++ b/drivers/extcon/extcon-pd-virtual.c @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct virtual_pd { + struct extcon_dev *extcon; + struct gpio_desc *gpio_irq; + struct regulator *dp_pwr; + struct device *dev; + bool flip; + bool usb_ss; + bool enable; + u8 mode; + int irq; + int enable_irq; + u8 plug_state; + struct workqueue_struct *virtual_pd_wq; + spinlock_t irq_lock; + struct delayed_work irq_work; + int shake_lev; +}; + +static const unsigned int vpd_cable[] = { + EXTCON_USB, + EXTCON_USB_HOST, + EXTCON_USB_VBUS_EN, + EXTCON_CHG_USB_SDP, + EXTCON_CHG_USB_CDP, + EXTCON_CHG_USB_DCP, +/* + FIXME: There's no real pd phy, control the charging is very + dangerous, just rely on the BC detection. We don't use slow + and fast. +*/ + EXTCON_CHG_USB_SLOW, + EXTCON_CHG_USB_FAST, + EXTCON_DISP_DP, + EXTCON_NONE, +}; + +enum vpd_mode { + VPD_DFP = 0, + VPD_UFP, + VPD_DP, + VPD_DP_UFP, +}; + +static void vpd_set_vbus_enable(struct virtual_pd *vpd, bool enable) +{ + extcon_set_state(vpd->extcon, EXTCON_USB_VBUS_EN, enable); + extcon_sync(vpd->extcon, EXTCON_USB_VBUS_EN); +} + +static void vpd_extcon_notify(struct virtual_pd *vpd, bool flip, bool usb_ss, + bool dfp, bool ufp, bool dp) +{ + union extcon_property_value property; + + property.intval = flip; + extcon_set_property(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_TYPEC_POLARITY, property); + extcon_set_property(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_TYPEC_POLARITY, property); + extcon_set_property(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_TYPEC_POLARITY, property); + + property.intval = usb_ss; + extcon_set_property(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_SS, property); + extcon_set_property(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_SS, property); + extcon_set_property(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_SS, property); + extcon_set_state(vpd->extcon, EXTCON_USB, ufp); + extcon_set_state(vpd->extcon, EXTCON_USB_HOST, dfp); + extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp); + extcon_sync(vpd->extcon, EXTCON_USB); + extcon_sync(vpd->extcon, EXTCON_USB_HOST); + extcon_sync(vpd->extcon, EXTCON_DISP_DP); +} + +static void vpd_extcon_notify_set(struct virtual_pd *vpd) +{ + bool flip = vpd->flip, usb_ss = vpd->usb_ss; + bool dfp = 0, ufp = 0, dp = 0; + + switch (vpd->mode) { + case VPD_DFP: + dfp = 1; + break; + case VPD_DP: + dp = 1; + dfp = 1; + break; + case VPD_DP_UFP: + dp = 1; + ufp = 1; + break; + case VPD_UFP: + /* fall through */ + default: + ufp = 1; + break; + } + + vpd_set_vbus_enable(vpd, !ufp); + vpd_extcon_notify(vpd, flip, usb_ss, dfp, ufp, dp); +} + +static void vpd_extcon_notify_clr(struct virtual_pd *vpd) +{ + vpd_set_vbus_enable(vpd, 0); + vpd_extcon_notify(vpd, vpd->flip, vpd->usb_ss, 0, 0, 0); +} + +void vpd_irq_disable(struct virtual_pd *vpd) +{ + unsigned long irqflags = 0; + + spin_lock_irqsave(&vpd->irq_lock, irqflags); + if (!vpd->enable_irq) { + disable_irq_nosync(vpd->irq); + vpd->enable_irq = 1; + } else { + dev_warn(vpd->dev, "irq have already disabled\n"); + } + spin_unlock_irqrestore(&vpd->irq_lock, irqflags); +} + +void vpd_irq_enable(struct virtual_pd *vpd) +{ + unsigned long irqflags = 0; + + spin_lock_irqsave(&vpd->irq_lock, irqflags); + if (vpd->enable_irq) { + enable_irq(vpd->irq); + vpd->enable_irq = 0; + } + spin_unlock_irqrestore(&vpd->irq_lock, irqflags); +} + +static void extcon_pd_delay_irq_work(struct work_struct *work) +{ + struct virtual_pd *vpd = + container_of(work, struct virtual_pd, irq_work.work); + int lev; + + lev = gpiod_get_raw_value(vpd->gpio_irq); + + if (vpd->shake_lev != lev) { + vpd_irq_enable(vpd); + return; + } + + switch (vpd->plug_state) { + case 1: + if (lev == 0) { + vpd->enable = false; + vpd_extcon_notify_clr(vpd); + vpd->plug_state=0; + } + break; + case 0: + if (lev == 1) { + vpd->enable = true; + vpd_extcon_notify_set(vpd); + vpd->plug_state=1; + } + break; + default: + break; + } + vpd_irq_enable(vpd); +} + +static irqreturn_t dp_det_irq_handler(int irq, void *dev_id) +{ + struct virtual_pd *vpd = dev_id; + int lev; + lev = gpiod_get_raw_value(vpd->gpio_irq); + vpd->shake_lev = lev; + schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10)); + vpd_irq_disable(vpd); + return IRQ_HANDLED; +} + +static void vpd_extcon_init(struct virtual_pd *vpd) +{ + struct device *dev = vpd->dev; + u32 tmp = 0; + int ret = 0; + + ret = device_property_read_u32(dev, "vpd,init-flip", &tmp); + if (ret < 0) + vpd->flip = 0; + else + vpd->flip = tmp; + dev_dbg(dev, "init-flip = %d\n", vpd->flip); + + ret = device_property_read_u32(dev, "vpd,init-ss", &tmp); + if (ret < 0) + vpd->usb_ss = 0; + else + vpd->usb_ss = tmp; + dev_dbg(dev, "init-ss = %d\n", vpd->usb_ss); + + ret = device_property_read_u32(dev, "vpd,init-mode", &tmp); + if (ret < 0) + vpd->mode = 0; + else + vpd->mode = tmp; + dev_dbg(dev, "init-mode = %d\n", vpd->mode); + + if(gpiod_get_raw_value(vpd->gpio_irq)) { + vpd_extcon_notify_set(vpd); + vpd->plug_state=1; + } +} + +static int vpd_extcon_probe(struct platform_device *pdev) +{ + struct virtual_pd *vpd; + struct device *dev = &pdev->dev; + int ret = 0; + + dev_info(dev, "probe start\n"); + + vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL); + if (!vpd) + return -ENOMEM; + + vpd->dev = dev; + dev_set_drvdata(dev, vpd); + vpd->enable = 1; + + vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable); + if (IS_ERR(vpd->extcon)) { + dev_err(dev, "allocat extcon failed\n"); + return PTR_ERR(vpd->extcon); + } + + ret = devm_extcon_dev_register(dev, vpd->extcon); + if (ret) { + dev_err(dev, "register extcon failed: %d\n", ret); + return ret; + } + + vpd->gpio_irq = devm_gpiod_get_optional(dev,"hpd", GPIOD_IN); + if (IS_ERR(vpd->gpio_irq)) { + dev_warn(dev, "maybe miss named GPIO for hpd\n"); + vpd->gpio_irq = NULL; + } + + vpd->dp_pwr = devm_regulator_get_optional(dev, "dp-pwr"); + if (IS_ERR(vpd->dp_pwr)) { + dev_warn(dev, "failed to get dp-pwr\n"); + vpd->dp_pwr = NULL; + } + + ret = regulator_enable(vpd->dp_pwr); + if (ret) + dev_warn(dev, "failed to enable dp-pwr\n"); + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set USB property capability failed: %d\n", ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set USB_HOST property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set DISP_DP property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_SS); + if (ret) { + dev_err(dev, + "set USB USB_SS property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_SS); + if (ret) { + dev_err(dev, + "set USB_HOST USB_SS property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_SS); + if (ret) { + dev_err(dev, + "set DISP_DP USB_SS property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_CHG_USB_FAST, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set USB_PD property capability failed: %d\n", ret); + return ret; + } + + vpd_extcon_init(vpd); + INIT_DELAYED_WORK(&vpd->irq_work, extcon_pd_delay_irq_work); + + vpd->irq=gpiod_to_irq(vpd->gpio_irq); + if (vpd->irq){ + ret = devm_request_threaded_irq(dev, + vpd->irq, + NULL, + dp_det_irq_handler, + IRQF_TRIGGER_FALLING |IRQF_TRIGGER_RISING | IRQF_ONESHOT , + NULL, + vpd); + } + else + dev_err(dev,"gpio can not be irq !\n"); + + vpd->virtual_pd_wq = create_workqueue("virtual_pd_wq"); + + dev_info(dev, "probe success\n"); + + return 0; +} + +static int vpd_extcon_remove(struct platform_device *pdev) +{ + struct virtual_pd *vpd = platform_get_drvdata(pdev); + + regulator_disable(vpd->dp_pwr); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int vpd_extcon_suspend(struct device *dev) +{ + struct virtual_pd *vpd = dev_get_drvdata(dev); + + int lev=0; + lev = gpiod_get_raw_value(vpd->gpio_irq); + cancel_delayed_work_sync(&vpd->irq_work); + vpd_irq_disable(vpd); + return 0; +} + +static int vpd_extcon_resume(struct device *dev) +{ + struct virtual_pd *vpd = dev_get_drvdata(dev); + vpd_irq_enable(vpd); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops, + vpd_extcon_suspend, vpd_extcon_resume); + +static const struct of_device_id vpd_extcon_dt_match[] = { + { .compatible = "linux,extcon-pd-virtual", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vpd_extcon_dt_match); + +static struct platform_driver vpd_extcon_driver = { + .probe = vpd_extcon_probe, + .remove = vpd_extcon_remove, + .driver = { + .name = "extcon-pd-virtual", + .pm = &vpd_extcon_pm_ops, + .of_match_table = vpd_extcon_dt_match, + }, +}; + +static int __init __vpd_extcon_init(void) +{ + return platform_driver_register(&vpd_extcon_driver); +} + +static void __exit __vpd_extcon_exit(void) +{ + platform_driver_unregister(&vpd_extcon_driver); +} + +module_init(__vpd_extcon_init); +module_exit(__vpd_extcon_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("rockchip"); +MODULE_DESCRIPTION("Virtual Typec-pd extcon driver"); \ No newline at end of file From 13d77b3a538e3b5eb6146c71e06ec131e5c81481 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Mon, 13 Mar 2023 14:22:55 +0800 Subject: [PATCH 011/249] rk_headset: change "get pin level again" log to debug --- drivers/headset_observe/rk_headset_irq_hook_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/headset_observe/rk_headset_irq_hook_adc.c b/drivers/headset_observe/rk_headset_irq_hook_adc.c index d3756430a1aa5..828a026ec34e6 100644 --- a/drivers/headset_observe/rk_headset_irq_hook_adc.c +++ b/drivers/headset_observe/rk_headset_irq_hook_adc.c @@ -122,7 +122,7 @@ static irqreturn_t headset_interrupt(int irq, void *dev_id) for (i = 0; i < 3; i++) { level = gpio_get_value(pdata->headset_gpio); if (level < 0) { - pr_err("%s:get pin level again,pin=%d,i=%d\n", + pr_debug("%s:get pin level again,pin=%d,i=%d\n", __func__, pdata->headset_gpio, i); msleep(1); continue; @@ -133,7 +133,7 @@ static irqreturn_t headset_interrupt(int irq, void *dev_id) pr_err("%s:get pin level err!\n", __func__); goto out; } else { - pr_err("%s:get pin level again, pin=%d,i=%d\n", + pr_debug("%s:get pin level again, pin=%d,i=%d\n", __func__, pdata->headset_gpio, i); } From a2778720bcfcbcc8b5939ce47e7f423453e854e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=91=9E?= Date: Sun, 19 Mar 2023 12:54:42 -0400 Subject: [PATCH 012/249] cma: Enable reserved-memory on orangepi5 Signed-off-by: Zhang Rui --- .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts index 9f8bff1ee4701..0307c1c45aa97 100755 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -69,6 +69,21 @@ linux,default-trigger-delay-ms = <0>; }; }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; }; &gmac1 { From 3c4008cc170210e96e136f6544386015b2a523a5 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Fri, 31 Mar 2023 23:49:38 +0200 Subject: [PATCH 013/249] mekotronics: stmmac: hack LED_FIX --- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index a6310d96b0d41..6c2cad01a6af7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -146,6 +146,14 @@ static void stmmac_exit_fs(struct net_device *dev); #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) +#define LED_FIX 1 +#ifdef LED_FIX +#define RTL_8201F_PHY_ID 0x001cc816 +#define RTL_8211E_PHY_ID 0x001cc915 +#define RTL_8211F_PHY_ID 0x001cc916 +#define DP_83848_PHY_ID 0x20005c90 +#endif + int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) { int ret = 0; @@ -7097,6 +7105,112 @@ void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) } } +#ifdef LED_FIX +static int phy_dp83848_led_fixup(struct phy_device *phydev) +{ + int value; + + if (phydev->phy_id != DP_83848_PHY_ID) + return 0; + + printk("%s in\n", __func__); + + value = phy_read(phydev, 0x18); + value &= ~(1<<2); + phy_write(phydev, 0x18, value); + + value = phy_read(phydev, 0x19); + value &= ~(1<<5); + phy_write(phydev, 0x19, value); + + return 0; +} + +static int phy_rtl8201f_led_fixup(struct phy_device *phydev) +{ + int value; + + printk("%s in\n", __func__); + + /* switch to page 7 */ + value = phy_read(phydev, 31); + value &= 0xff00; + value |= 0x0007; + value = phy_write(phydev, 31, value); + + /* set customized led enable */ + value = phy_read(phydev, 19); + value |= (0x1<<3); + phy_write(phydev, 19, value); + + value &= 0x0000; + value |= (0x1<<1); + value |= (0x1<<7); + phy_write(phydev, 17, value); + + /* back to page 0 */ + value = phy_read(phydev, 31); + value &= 0x0000; + value = phy_write(phydev, 31, value); + + return 0; +} + +static int phy_rtl8211e_led_fixup(struct phy_device *phydev) +{ + int val; + + printk("%s in\n", __func__); + val = phy_read(phydev, 3); + printk("%s in val=0x%04x\n", __func__, val); + + /*switch to extension page44*/ + phy_write(phydev, 31, 0x07); + phy_write(phydev, 30, 0x2c); + + /*set led1(yellow) act*/ + val = phy_read(phydev, 26); + val &= (~(1<<4));// bit4=0 + val |= (1<<5);// bit5=1 + val &= (~(1<<6));// bit6=0 + phy_write(phydev, 26, val); + + /*set led0(green) link*/ + val = phy_read(phydev, 28); + val |= (7<<0);// bit0,1,2=1 + val &= (~(7<<4));// bit4,5,6=0 + val &= (~(7<<8));// bit8,9,10=0 + phy_write(phydev, 28, val); + + /*switch back to page0*/ + phy_write(phydev,31,0x00); + + return 0; +} + +static int phy_rtl8211f_led_fixup(struct phy_device *phydev) +{ + int val; + + printk("%s in\n", __func__); + + val = phy_read(phydev, 31); + printk("%s in val=0x%04x\n", __func__, val); + + /*switch to extension page31*/ + phy_write(phydev, 31, 0xd04); + + //phy_write(phydev, 0x10, 0x6d60); /*led1-green led2-yellow */ + phy_write(phydev, 0x10, 0xc160); /*led1-green led2-yellow */ + phy_write(phydev, 0x11, 0x8); + + /*switch back to page0*/ + phy_write(phydev,31,0x0); + + return 0; +} +#endif + /** * stmmac_dvr_probe * @device: device pointer @@ -7366,6 +7480,22 @@ int stmmac_dvr_probe(struct device *device, goto error_netdev_register; } +#ifdef LED_FIX +/* register the PHY board fixup */ +ret = phy_register_fixup_for_uid(RTL_8211E_PHY_ID, 0xffffffff, phy_rtl8211e_led_fixup); +if (ret) + pr_warn("Cannot register PHY board fixup.\n"); +ret = phy_register_fixup_for_uid(RTL_8211F_PHY_ID, 0xffffffff, phy_rtl8211f_led_fixup); +if (ret) + pr_warn("Cannot register PHY board fixup.\n"); +ret = phy_register_fixup_for_uid(RTL_8201F_PHY_ID, 0xffffffff, phy_rtl8201f_led_fixup); +if (ret) + pr_warn("Cannot register PHY board fixup.\n"); +ret = phy_register_fixup_for_uid(DP_83848_PHY_ID, 0xffffffff, phy_dp83848_led_fixup); +if (ret) + pr_warn("Cannot register PHY board fixup.\n"); +#endif + #ifdef CONFIG_DEBUG_FS stmmac_init_fs(ndev); #endif From b939c10e479da406b36fc5939821d2be5a73d271 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Fri, 31 Mar 2023 23:51:23 +0200 Subject: [PATCH 014/249] mekotronics: rk3588-blueberry: DTS's for Mekotronics R58's (via @monkaBlyat) --- .../rk3588-blueberry-edge-v10-linux.dts | 119 +++ .../rockchip/rk3588-blueberry-edge-v10.dtsi | 860 +++++++++++++++++ .../rk3588-blueberry-edge-v12-linux.dts | 119 +++ .../rockchip/rk3588-blueberry-edge-v12.dtsi | 886 ++++++++++++++++++ .../rk3588-blueberry-minipc-linux.dts | 119 +++ .../dts/rockchip/rk3588-blueberry-minipc.dtsi | 756 +++++++++++++++ .../boot/dts/rockchip/rk3588-blueberry.dtsi | 324 +++++++ 7 files changed, 3183 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blueberry.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts new file mode 100644 index 0000000000000..b1e4b961c7864 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-edge-v10.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "RK3588 EDGE LP4x V1.0 BlueBerry Board"; + compatible = "rockchip,rk3588-hugsun-edge-v10-linux", "rockchip,rk3588"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xd8 KEY_BACK>, + <0xc7 KEY_UP>, + <0xbf KEY_DOWN>, + <0xc8 KEY_LEFT>, + <0xc6 KEY_RIGHT>, + <0x8c KEY_HOME>, + <0x78 KEY_VOLUMEUP>, + <0x76 KEY_VOLUMEDOWN>, + <0x7e KEY_POWER>, + <0xed KEY_POWER>, //20171123 + <0x7c KEY_MENU>, + <0xb7 388>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi new file mode 100644 index 0000000000000..d8b9b4a070145 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-blueberry.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + i2s0_sound: i2s0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8311"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8311>; + }; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + wifi_led: wifi-led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_led: eth-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + //gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + vk2c21_lcd { + compatible = "lcd_vk2c21"; + i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + + status = "disabled"; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 + startup-delay-us = <10000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&dp1 { + pinctrl-0 = <&dp1m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&dp1_sound{ + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; //gpio1_d5 +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8311: es8311@18 { + status = "okay"; + compatible = "everest,es8311"; + reg = <0x18>; + #sound-dai-cells = <0>; + adc-pga-gain = <6>; /* 18dB */ + adc-volume = <0xbf>; /* 0dB */ + dac-volume = <0xbf>; /* 0dB */ + aec-mode = "adc left, adc right"; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +//hdmi01 sound +&i2s5_8ch { + status = "okay"; +}; + +//hdmi02 sound +&i2s6_8ch { + status = "okay"; +}; + +//hdmiin sound +&i2s7_8ch { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_dp1 { + status = "okay"; + connect = <&vp2_out_dp1>; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&sata0 { + status = "okay"; +}; + +//rs485 +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +//rs232 +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + + +&pinctrl { + + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + //rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; +}; + +//type-c0 +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +//usb2.0 host0 +&u2phy2 { + status = "okay"; +}; + +//usb2.0 host1 +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts new file mode 100644 index 0000000000000..d31efbcc57902 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-edge-v12.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "RK3588 EDGE LP4x V1.2 BlueBerry Board"; + compatible = "rockchip,rk3588-hugsun-edge-v12-linux", "rockchip,rk3588"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xd8 KEY_BACK>, + <0xc7 KEY_UP>, + <0xbf KEY_DOWN>, + <0xc8 KEY_LEFT>, + <0xc6 KEY_RIGHT>, + <0x8c KEY_HOME>, + <0x78 KEY_VOLUMEUP>, + <0x76 KEY_VOLUMEDOWN>, + <0x7e KEY_POWER>, + <0xed KEY_POWER>, //20171123 + <0x7c KEY_MENU>, + <0xb7 388>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi new file mode 100644 index 0000000000000..7d2f58af5ee34 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi @@ -0,0 +1,886 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-blueberry.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + wifi_led: wifi-led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_led: eth-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + //linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + //gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + vk2c21_lcd { + compatible = "lcd_vk2c21"; + i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + + status = "disabled";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 + startup-delay-us = <10000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "disable"; +}; + +//&dp0_in_vp2 { +// status = "okay"; +//}; + +&dp1 { + pinctrl-0 = <&dp1m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&dp1_sound{ + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; //gpio1_d5 +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +//hdmi01 sound +&i2s5_8ch { + status = "okay"; +}; + +//hdmi02 sound +&i2s6_8ch { + status = "okay"; +}; + +//hdmiin sound +&i2s7_8ch { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_dp1 { + status = "okay"; + connect = <&vp2_out_dp1>; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&sata0 { + status = "okay"; +}; + +//rs485 +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +//rs232 +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + + +&pinctrl { + + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + //rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; +}; + +//type-c0 +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +//usb2.0 host0 +&u2phy2 { + status = "okay"; +}; + +//usb2.0 host1 +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts new file mode 100644 index 0000000000000..e10f05eefb57c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-minipc.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "RK3588 MINIPC LP4x V1.0 BlueBerry Board"; + compatible = "rockchip,rk3588-hugsun-minipc-linux", "rockchip,rk3588"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xd8 KEY_BACK>, + <0xc7 KEY_UP>, + <0xbf KEY_DOWN>, + <0xc8 KEY_LEFT>, + <0xc6 KEY_RIGHT>, + <0x8c KEY_HOME>, + <0x78 KEY_VOLUMEUP>, + <0x76 KEY_VOLUMEDOWN>, + <0x7e KEY_POWER>, + <0xed KEY_POWER>, //20171123 + <0x7c KEY_MENU>, + <0xb7 388>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc.dtsi new file mode 100644 index 0000000000000..77cba74edf706 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc.dtsi @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-blueberry.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + wifi_led: wifi-led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_led: eth-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "disable"; +}; + +//&dp0_in_vp1 { +// status = "okay"; +//}; + +&dp1 { + pinctrl-0 = <&dp1m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp1 { + status = "okay"; +}; + +&dp1_sound{ + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + hdcp1x-enable; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + hdcp1x-enable; + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; //gpio1_d5 +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +//hdmi01 sound +&i2s5_8ch { + status = "okay"; +}; + +//hdmi02 sound +&i2s6_8ch { + status = "okay"; +}; + +//hdmiin sound +&i2s7_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&route_hdmi1 { + status = "okay"; + connect = <&vp2_out_hdmi1>; +}; + +&sata0 { + status = "okay"; +}; + +//rs485 +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +//rs232 +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + + +&pinctrl { + + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +//type-c0 +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +//usb2.0 host0 +&u2phy2 { + status = "okay"; +}; + +//usb2.0 host1 +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry.dtsi new file mode 100644 index 0000000000000..314245082aa3a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rk3588-cpu-swap.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip,dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip,dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + test-power { + status = "okay"; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&CPU_SLEEP { + status = "disabled"; +}; + +&cluster0_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cluster1_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cluster2_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&gpu_opp_table { + /delete-node/ opp-198000000; + /delete-node/ opp-297000000; + /delete-node/ opp-396000000; + /delete-node/ opp-500000000; + /delete-node/ opp-1000000000; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; From 3f42cf5f62ecdee61c9b31f4cd7da32b2ac0542c Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Fri, 31 Mar 2023 23:53:36 +0200 Subject: [PATCH 015/249] mekotronics: dts: add actual Mekotronics board names to DT model --- .../arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts | 2 +- .../arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts index b1e4b961c7864..79dcd3ec3ad1e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts @@ -10,7 +10,7 @@ #include "rk3588-linux.dtsi" / { - model = "RK3588 EDGE LP4x V1.0 BlueBerry Board"; + model = "Mekotronics R58X (RK3588 EDGE LP4x V1.0 BlueBerry Board)"; compatible = "rockchip,rk3588-hugsun-edge-v10-linux", "rockchip,rk3588"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts index d31efbcc57902..1e96232da7ff3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts @@ -10,7 +10,7 @@ #include "rk3588-linux.dtsi" / { - model = "RK3588 EDGE LP4x V1.2 BlueBerry Board"; + model = "Mekotronics R58X-4G (RK3588 EDGE LP4x V1.2 BlueBerry Board)"; compatible = "rockchip,rk3588-hugsun-edge-v12-linux", "rockchip,rk3588"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts index e10f05eefb57c..b10a23112ff50 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts @@ -10,7 +10,7 @@ #include "rk3588-linux.dtsi" / { - model = "RK3588 MINIPC LP4x V1.0 BlueBerry Board"; + model = "Mekotronics R58 MiniPC (RK3588 MINIPC LP4x V1.0 BlueBerry Board)"; compatible = "rockchip,rk3588-hugsun-minipc-linux", "rockchip,rk3588"; }; From 6be230269adfa679eac45d80a7ca77abb2794d90 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sat, 1 Apr 2023 15:56:01 +0200 Subject: [PATCH 016/249] mekotronics: dts: rk3588-blueberry: add to Makefile --- arch/arm64/boot/dts/rockchip/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index c68b6f4d70238..3e4d99a29828b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -202,6 +202,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v12-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-minipc-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-csi-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-dvp-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dtb From 727a069107ac7323f0e42570cda9769d213b13dc Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sun, 2 Apr 2023 16:03:14 +0200 Subject: [PATCH 017/249] mekotronics: dts: delete `chosen` node --- arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts index 79dcd3ec3ad1e..a00649f9f7111 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts @@ -12,6 +12,7 @@ / { model = "Mekotronics R58X (RK3588 EDGE LP4x V1.0 BlueBerry Board)"; compatible = "rockchip,rk3588-hugsun-edge-v10-linux", "rockchip,rk3588"; + /delete-node/ chosen; }; &pwm3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts index 1e96232da7ff3..afc5a868d9876 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts @@ -12,6 +12,7 @@ / { model = "Mekotronics R58X-4G (RK3588 EDGE LP4x V1.2 BlueBerry Board)"; compatible = "rockchip,rk3588-hugsun-edge-v12-linux", "rockchip,rk3588"; + /delete-node/ chosen; }; &pwm3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts index b10a23112ff50..1ed02353453aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts @@ -12,6 +12,7 @@ / { model = "Mekotronics R58 MiniPC (RK3588 MINIPC LP4x V1.0 BlueBerry Board)"; compatible = "rockchip,rk3588-hugsun-minipc-linux", "rockchip,rk3588"; + /delete-node/ chosen; }; &pwm3 { From e7dbe3674085edc9295dcad0d7ed8e714a034cca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Muhammed=20Efe=20=C3=87etin?= Date: Fri, 14 Apr 2023 16:17:34 +0300 Subject: [PATCH 018/249] arm64: dts: Add device trees for NanoPi R6S and R6C arm64: dts: Add device trees for NanoPi R6S and R6C arm64: dts: Add device trees for NanoPi R6S and R6C arm64: dts: Add device trees for NanoPi R6S and R6C --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../rockchip/rk3588s-nanopi-r6-common.dtsi | 688 ++++++++++++++++++ .../boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 28 + .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 189 +++++ 4 files changed, 907 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3e4d99a29828b..239915e765a3d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -343,5 +343,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb subdir-y := $(dts-dirs) overlay diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi new file mode 100644 index 0000000000000..e6d35bb716e02 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-android.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + aliases { + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &sdhci; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 coherent_pool=1m irqchip.gicv3_pseudo_nmi=0"; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi0"; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + test-power { + status = "okay"; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + upthreshold = <60>; + downdifferential = <30>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,no-vlhash; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy0 { + /* Single Vdiff Training Table for power reduction (optional) */ + training-table = /bits/ 8 < + /* voltage swing 0, pre-emphasis 0->3 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 1, pre-emphasis 0->2 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 2, pre-emphasis 0->1 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 3, pre-emphasis 0 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + >; + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c7 { + status = "disabled"; +}; + +&i2c8 { + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xc43b>; + /* /system/usr/keylayout/Generic.kl */ + rockchip,key_table = + <0xff KEY_POWER>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xf2 KEY_UP>, + <0xea KEY_DOWN>, + <0xee KEY_ENTER>, + <0xe9 KEY_MUTE>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf3 KEY_VOLUMEUP>, + <0xae KEY_MENU>, + <0xeb 172>, + <0xaf KEY_BACK>, + <0xf7 204>, + <0xe5 KEY_SYSRQ>, + <0xf5 580>; + }; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts new file mode 100644 index 0000000000000..eb4a3e0c5bb23 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3588s-nanopi-r6s.dts" + +/ { + model = "FriendlyElec NanoPi R6C"; + compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588"; + + aliases { + ethernet0 = &r8125_u25; + }; +}; + +&lan2_led { + label = "user_led"; +}; + +&pcie2x1l2 { + /delete-node/ pcie@40; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts new file mode 100644 index 0000000000000..9a8f66734fc68 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + + /dts-v1/; + +#include "rk3588s-nanopi-r6-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R6S"; + compatible = "friendlyelec,nanopi-r6s", "rockchip,rk3588"; + + aliases { + ethernet0 = &r8125_u25; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + vcc5v0_host_20: vcc5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&pcie2x1l1 { + pcie@30 { + reg = <0x00300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u25: pcie@30,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie2x1l2 { + pcie@40 { + reg = <0x00400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u40: pcie@40,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + /delete-property/ rockchip,plane-mask; + /delete-property/ rockchip,primary-plane; +}; \ No newline at end of file From 24bad6c316360144777607c802ffe48cd0ebf654 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Mon, 3 Apr 2023 21:05:15 +0200 Subject: [PATCH 019/249] use 'python3', not 'python' (reduced version) --- Documentation/sphinx/maintainers_include.py | 2 +- scripts/bmpconvert | 2 +- scripts/clang-wrapper.py | 2 +- scripts/gcc-wrapper.py | 2 +- scripts/mkmultidtb.py | 2 +- tools/perf/python/tracepoint.py | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/sphinx/maintainers_include.py b/Documentation/sphinx/maintainers_include.py index 328b3631a585c..b3c0e64238288 100755 --- a/Documentation/sphinx/maintainers_include.py +++ b/Documentation/sphinx/maintainers_include.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0 # -*- coding: utf-8; mode: python -*- # pylint: disable=R0903, C0330, R0914, R0912, E0401 diff --git a/scripts/bmpconvert b/scripts/bmpconvert index 9863444da093c..30acca17fcc01 100755 --- a/scripts/bmpconvert +++ b/scripts/bmpconvert @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0 */ # -*- coding: utf-8 -*- diff --git a/scripts/clang-wrapper.py b/scripts/clang-wrapper.py index a255e0996c40b..02525a079ee59 100755 --- a/scripts/clang-wrapper.py +++ b/scripts/clang-wrapper.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 # -*- coding: utf-8 -*- # Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. diff --git a/scripts/gcc-wrapper.py b/scripts/gcc-wrapper.py index ea74ea852242d..ad9d6a2153ff2 100755 --- a/scripts/gcc-wrapper.py +++ b/scripts/gcc-wrapper.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 # -*- coding: utf-8 -*- # Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. diff --git a/scripts/mkmultidtb.py b/scripts/mkmultidtb.py index 81b814acd3042..7fe1dc24cb75f 100755 --- a/scripts/mkmultidtb.py +++ b/scripts/mkmultidtb.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) # Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd # diff --git a/tools/perf/python/tracepoint.py b/tools/perf/python/tracepoint.py index bba68a6d45156..91cc1f8230a24 100755 --- a/tools/perf/python/tracepoint.py +++ b/tools/perf/python/tracepoint.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0 # -*- python -*- # -*- coding: utf-8 -*- From 7f6f60c5dca883814f8ce78f8910ec7101d61ffd Mon Sep 17 00:00:00 2001 From: amazingfate Date: Wed, 19 Apr 2023 15:51:30 +0800 Subject: [PATCH 020/249] arm64: dts: Add device tree for Hinlink H88K --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-hinlink-h88k.dts | 1103 +++++++++++++++++ 2 files changed, 1104 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-hinlink-h88k.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 239915e765a3d..050163964a496 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -308,6 +308,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v11-linux-ipc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-rk628-hdmi2csi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-hinlink-h88k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-ipc-4x-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-hinlink-h88k.dts b/arch/arm64/boot/dts/rockchip/rk3588-hinlink-h88k.dts new file mode 100644 index 0000000000000..865f3141b7423 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-hinlink-h88k.dts @@ -0,0 +1,1103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + model = "HINLINK H88K"; + compatible = "hinlink,h88k", "rockchip,rk3588"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + dp0_sound: dp0-sound { + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip,dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8388-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-es8316"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8388>; + }; + }; + }; + + hdmi0-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int_pin>; + pinctrl-names = "default"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_net_en>, <&led_sata_en>, + <&led_user_en>, <&led_work_en>; + + net { + label = "blue:net"; + gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + }; + + sata { + label = "amber:sata"; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + + user { + label = "green:user"; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + work { + label = "red:work"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + /* it's modem reset pin */ + modem_enable: modem-enable { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "modem-enable"; + vin-supply = <&vcc_3v3_s3>; + startup-delay-us = <500000>; + pinctrl-names = "default"; + pintctrl-0 = <&modem_reset_en>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "pcie20_avdd0v85"; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie20_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie30_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm14 0 50000 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_m2_sata: vcc3v3-m2-sata { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sata"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_modem: vcc3v3-modem { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_modem"; + pinctrl-names = "default"; + pintctrl-0 = <&modem_power_en>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb_host"; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_hub: vcc5v0-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_hub_en>; + regulator-name = "vcc5v0_usb_hub"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb_otg"; + vin-supply = <&vcc5v0_usb>; + }; + + wifi_regon: wifi-regon { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "wifi_regon"; + startup-delay-us = <5000>; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp1 { + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + phy-handle = <&rgmii_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + }; +}; + +&i2c6 { + status = "okay"; + + husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_usb_otg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: es8388@11 { + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + ir_int_pin: ir-int-pin { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_net_en: led_net_en { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_sata_en: led_sata_en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_user_en: led_user_en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_work_en: led_work_en { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + modem { + modem_power_en: modem-power-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + modem_reset_en: modem-reset-en { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm14 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&route_hdmi1 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + | RKPM_SLP_PMU_DBG + ) + >; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + max-frequency = <50000000>; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + rockchip,dp-lane-mux = < 0 1 2 3 >; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + svid = <0xff01>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; From 92a0fabcb8fa4764d7187154c6f4c6aea5d7f055 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=2E=20Efe=20=C3=87etin?= Date: Fri, 21 Apr 2023 18:17:23 +0300 Subject: [PATCH 021/249] arm64: dts: enable sdhci node in OPi5 device tree --- arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi index af25013fcbe8d..bef3ca70c06da 100755 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi @@ -466,7 +466,7 @@ max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; - status = "disabled"; + status = "okay"; }; &sdmmc { From bf4cca62b9c1aadeff87510767d1f306a99f523d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=2E=20Efe=20=C3=87etin?= Date: Fri, 21 Apr 2023 18:18:32 +0300 Subject: [PATCH 022/249] arm64: dts: remove OPi 5B device tree --- .../boot/dts/rockchip/rk3588s-orangepi-5b.dts | 412 ------------------ 1 file changed, 412 deletions(-) delete mode 100755 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts deleted file mode 100755 index 66305a01e4d44..0000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts +++ /dev/null @@ -1,412 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-orangepi-5.dtsi" -#include "rk3588-linux.dtsi" -#include "rk3588s-orangepi-5-lcd.dtsi" - -#include "rk3588s-orangepi-5-camera1.dtsi" -#include "rk3588s-orangepi-5-camera2.dtsi" -#include "rk3588s-orangepi-5-camera3.dtsi" - -/ { - model = "Orange Pi 5"; - compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; - - /delete-node/ chosen; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - enable-active-low; - vin-supply = <&vcc_3v3_s3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 =<&leds_gpio>; - status = "okay"; - - led@1 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - linux,default-trigger-delay-ms = <0>; - }; - }; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x42>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - cec-enable; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&route_hdmi0{ - status = "okay"; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s1_8ch { - status = "okay"; - rockchip,i2s-tx-route = <3 2 1 0>; - rockchip,i2s-rx-route = <1 3 2 0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclk - &i2s1m0_lrck - &i2s1m0_sdi1 - &i2s1m0_sdo3>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -/* - pin3: GPIO1_B7 - pin5: GPIO1_B6 -*/ -&i2c5 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; -}; - -&uart1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1m1_xfer>; -}; - -&pwm13 { - status = "disabled"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm13m2_pins>; -}; - -/* - pin7: GPIO1_C6 -*/ -&pwm15 { - status = "disabled"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm15m2_pins>; -}; - -/* - pin11: GPIO4_B2 - pin13: GPIO4_B3 -*/ -&pwm14 { - status = "disabled"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm14m1_pins>; -}; - -&can1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&can1m1_pins>; - assigned-clocks = <&cru CLK_CAN1>; - assigned-clock-rates = <200000000>; -}; - -/* - pin15: GPIO0_D4 - pin12: GPIO0_D5 -*/ -&can2 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&can2m1_pins>; - assigned-clocks = <&cru CLK_CAN2>; - assigned-clock-rates = <200000000>; -}; - -/* - pin19: GPIO1_C1 - pin21: GPIO1_C0 - pin23: GPIO1_C2 - pin24: GPIO1_C4 -*/ -&spi4 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; - assigned-clocks = <&cru CLK_SPI4>; - assigned-clock-rates = <200000000>; - num-cs = <2>; - - spi_dev@1 { - compatible = "rockchip,spidev"; - reg = <1>; - spi-max-frequency = <50000000>; - }; -}; - -&i2c3 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m0_xfer>; -}; - -&uart3 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3m0_xfer>; -}; - -&pwm3 { - status = "disabled"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm3m2_pins>; - //pinctrl-0 = <&pwm3m0_pins>; -}; - -/* - pin8: GPIO4_A3 - pin10: GPIO4_A4 -*/ -&uart0 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0m2_xfer>; -}; - -/* - pin16: GPIO1_D3 - pin18: GPIO1_D2 -*/ -&uart4 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4m0_xfer>; -}; - -&i2c1 { - status = "disabled"; - pinctrl-names = "default"; - //pinctrl-0 = <&i2c1m4_xfer>; - pinctrl-0 = <&i2c1m2_xfer>; -}; - -&pwm0 { - status = "disabled"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm0m1_pins>; -}; - -/* - pin26: GPIO1_A3 -*/ -&pwm1 { - status = "disabled"; - pinctrl-names = "active"; - //pinctrl-0 = <&pwm1m2_pins>; - pinctrl-0 = <&pwm1m1_pins>; -}; - -/* watchdog */ -&wdt { - status = "okay"; -}; - -&sfc { - status = "disabled"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&wireless_bluetooth { - BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&wireless_wlan { - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pinctrl -{ - wireless-bluetooth { - uart9_gpios: uart9-gpios { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_gpio: bt-gpio { - rockchip,pins = - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; From 6ebc6bc991ca959d558d54b4ffe8e061d9000122 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=2E=20Efe=20=C3=87etin?= Date: Fri, 21 Apr 2023 18:24:42 +0300 Subject: [PATCH 023/249] arm64: dts: remove OPi 5B device tree --- arch/arm64/boot/dts/rockchip/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 050163964a496..a6da598d8fc05 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -340,7 +340,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb8-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb From dcf63d6982a59b2064c0f7b05872b8c37d34d904 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=2E=20Efe=20=C3=87etin?= Date: Tue, 25 Apr 2023 11:27:54 +0300 Subject: [PATCH 024/249] arm64: dts: enable wireless nodes on OPi5 devicetree --- arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index 0aab227fe9823..62d7b03ccec9a 100755 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -71,7 +71,7 @@ pinctrl-1 = <&uart9_gpios>; BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "disabled"; + status = "okay"; }; wireless_wlan: wireless-wlan { @@ -81,7 +81,7 @@ pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; - status = "disabled"; + status = "okay"; }; vbus5v0_typec: vbus5v0-typec { From 36d2b16cd3adc431ad334042972b27465c2fee59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Muhammed=20Efe=20=C3=87etin?= Date: Tue, 25 Apr 2023 11:45:49 +0300 Subject: [PATCH 025/249] arm64: dts: Add missing nodes on OPi5 --- arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index 62d7b03ccec9a..8f8ebcb0db68c 100755 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -71,6 +71,7 @@ pinctrl-1 = <&uart9_gpios>; BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -312,7 +313,8 @@ bt_gpio: bt-gpio { rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; From 50388c8acbcb26fcd17565812cdc347c11f7521b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=2E=20Efe=20=C3=87etin?= Date: Tue, 25 Apr 2023 18:15:30 +0300 Subject: [PATCH 026/249] arm64: dts: Reduce DMC upthreshold --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index fee6171e01ab1..11a7ea7791b0a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1734,7 +1734,7 @@ clocks = <&scmi_clk 4>; clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; - upthreshold = <40>; + upthreshold = <25>; downdifferential = <20>; system-status-level = < /*system status freq level*/ From 937ba96685d8726713aceb7407131b0a50dd6702 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Muhammed=20Efe=20=C3=87etin?= Date: Tue, 25 Apr 2023 11:49:01 +0300 Subject: [PATCH 027/249] arm64: dts: Add missing screen resolutions on NanoPi R6S --- arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi index e6d35bb716e02..4e0646770ed19 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi @@ -15,8 +15,8 @@ #include #include #include "rk3588s.dtsi" -#include "rk3588-android.dtsi" #include "rk3588-rk806-single.dtsi" +#include "rk3588-s.dtsi" / { aliases { @@ -686,3 +686,8 @@ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; rockchip,primary-plane = ; }; + +&display_subsystem { + clocks = <&hdptxphy_hdmi_clk0>; + clock-names = "hdmi0_phy_pll"; +}; \ No newline at end of file From 3b415effa08ff154ae4e3b1446115cc46096b59e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Muhammed=20Efe=20=C3=87etin?= Date: Tue, 25 Apr 2023 16:20:03 +0300 Subject: [PATCH 028/249] arm64: dts: Add missing screen resolutions on NanoPi R6S --- arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi index 4e0646770ed19..640d9d731adbc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi @@ -16,7 +16,7 @@ #include #include "rk3588s.dtsi" #include "rk3588-rk806-single.dtsi" -#include "rk3588-s.dtsi" +#include "rk3588-linux.dtsi" / { aliases { From b07774a25ca73618cb05b72d0ddc19c317af8f76 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Thu, 4 May 2023 15:21:48 +0800 Subject: [PATCH 029/249] arm64:dts: Add pwm-fan node to rock5b --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index e3e694e793c84..27daaa82ec584 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -256,6 +256,13 @@ sound-dai = <&hdmiin_dc>; }; }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <72 94 117 139 162 184 207 229 255>; + pwms = <&pwm1 0 10000 0>; + }; }; &av1d { @@ -543,6 +550,95 @@ status = "okay"; }; +&soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <45000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip5: trip-point@5 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip6: trip-point@6 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@7 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&trip5>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + map6 { + trip = <&trip6>; + cooling-device = <&fan0 6 7>; + contribution = <1024>; + }; + map7 { + trip = <&pcritical>; + cooling-device = <&fan0 7 8>; + contribution = <1024>; + }; + }; +}; + &uart6 { pinctrl-names = "default"; pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; From d843b7d567a21aa16396b099d29f298796442ffc Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 30 Mar 2023 11:19:02 +0800 Subject: [PATCH 030/249] khadas: arm64: dts: khadas edge 2 [rpardini rework] - rework: - rk3588-rk806-single-khadas.dtsi instead of hacking common dtsi - arm64: dts: rk3588s-khadas-edge2: remove chosen node - drop useless nvr-demo / chosen-thingy dtsi - squashed, scripts/packaging/etc removed, grouped by directory - source - https://github.com/khadas/linux/commits/khadas-edges-5.10.y - https://github.com/khadas/linux/commit/85a8b25939a28b66f2147823b62f5861d23d69c1 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3588-rk806-single-khadas.dtsi | 396 ++++ .../rockchip/rk3588s-khadas-edge2-camera.dtsi | 492 +++++ .../dts/rockchip/rk3588s-khadas-edge2.dts | 943 +++++++++ .../dts/rockchip/rk3588s-khadas-edge2.dtsi | 1780 +++++++++++++++++ 5 files changed, 3612 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rk806-single-khadas.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2-camera.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a6da598d8fc05..d55da2a7abb2b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -345,5 +345,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb subdir-y := $(dts-dirs) overlay diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rk806-single-khadas.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single-khadas.dtsi new file mode 100644 index 0000000000000..e88fb8e4a66b3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single-khadas.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Wesion Technology Co., Ltd. + * + */ + +#include +#include + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + rk806single: rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + /* 2800mv-3500mv */ + low_voltage_threshold = <3000>; + /* 2700mv-3400mv */ + shutdown_voltage_threshold = <2700>; + /* 140 160 */ + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2-camera.dtsi new file mode 100644 index 0000000000000..5cb2350c3e42e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2-camera.dtsi @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Wesion Technology Co., Ltd. + * + */ + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_dcphy0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415b_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_dcphy1: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415f_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415c_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + dw9714b: dw9714b@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + pinctrl-names = "focusb_gpios"; + pinctrl-0 = <&focusb_gpio>; + focus-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <76>; + rockchip,vcm-step-mode = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx415b: imx415b@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default", "camb_gpios"; + pinctrl-0 = <&mipim1_camera1_clk>, <&camb_gpio>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&dw9714b>; + port { + imx415b_out0: endpoint { + remote-endpoint = <&mipi_in_dcphy0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9714f: dw9714f@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + pinctrl-names = "focusf_gpios"; + pinctrl-0 = <&focusf_gpio>; + focus-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <76>; + rockchip,vcm-step-mode = <0>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + }; + + imx415f: imx415f@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default", "camf_gpios"; + pinctrl-0 = <&mipim1_camera2_clk>, <&camf_gpio>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&dw9714f>; + port { + imx415f_out1: endpoint { + remote-endpoint = <&mipi_in_dcphy1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + dw9714c: dw9714c@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + pinctrl-names = "focusc_gpios"; + pinctrl-0 = <&focusc_gpio>; + focus-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <76>; + rockchip,vcm-step-mode = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default", "camc_gpios"; + pinctrl-0 = <&mipim1_camera3_clk>, <&camc_gpio>; + power-domains = <&power RK3588_PD_VI>; + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&dw9714c>; + port { + imx415c_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pinctrl { + cam { + camf_gpio: camf-gpio { + rockchip,pins = + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + camb_gpio: camb-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + camc_gpio: camc-gpio { + rockchip,pins = + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + focusb_gpio: focusb-gpio { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + focusf_gpio: focusf-gpio { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + focusc_gpio: focusc-gpio { + rockchip,pins = + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; + +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts new file mode 100644 index 0000000000000..06232ec3bbc18 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Wesion Technology Co., Ltd. + * + */ + +/dts-v1/; + +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588s-khadas-edge2.dtsi" +#include "rk3588-rk806-single-khadas.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588s-khadas-edge2-camera.dtsi" + +/ { + model = "Khadas Edge2"; + compatible = "khadas,edge2", "rockchip,rk3588"; + /delete-node/ chosen; + + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + sound_micarray: sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + es8316_sound: es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8316>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&red_led_gpio &green_led_gpio &blue_led_gpio>; + + red_led { + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + label = "red_led"; + linux,default-trigger = "none"; + default-state = "off"; + }; + + green_led { + gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + label = "green_led"; + linux,default-trigger = "default-on"; + default-state = "on"; + }; + + blue_led { + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + label = "blue_led"; + linux,default-trigger = "none"; + default-state = "off"; + }; + }; + + khadas_wdt { + compatible = "linux,wdt-khadas"; + status = "okay"; + hw_margin_ms = <500>; + hw-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_en>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&pt7c4363>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <1>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + // WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc3v3_lcd1_en: vcc3v3-lcd1-en { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc3v3_lcd2_en: vcc3v3-lcd2-en { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd2_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + +}; + +&backlight_mipi0 { + pwms = <&pwm12 0 25000 0>; + power-supply = <&vcc3v3_lcd1_en>; + status = "okay"; +}; + +&backlight_mipi1 { + pwms = <&pwm13 0 25000 0>; + power-supply = <&vcc3v3_lcd2_en>; + status = "disabled"; +}; + + +&combphy0_ps { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + reset-delay-ms = <20>; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; + +}; + +&dsi0_panel { + status = "okay"; + power-supply = <&vcc3v3_lcd1_en>; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&dsi1 { + reset-delay-ms = <20>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd2_rst_gpio1>; + status = "disabled"; +}; + +&dsi1_panel { + status = "disabled"; + power-supply = <&vcc3v3_lcd2_en>; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +//&hdptxphy0 { + /* Single Vdiff Training Table for power reduction (optional) */ +// training-table = /bits/ 8 < + /* voltage swing 0, pre-emphasis 0->3 */ +// 0x0d 0x00 0x00 0x00 0x00 0x00 +// 0x0d 0x00 0x00 0x00 0x00 0x00 +// 0x0d 0x00 0x00 0x00 0x00 0x00 +// 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 1, pre-emphasis 0->2 */ +// 0x0d 0x00 0x00 0x00 0x00 0x00 +// 0x0d 0x00 0x00 0x00 0x00 0x00 +// 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 2, pre-emphasis 0->1 */ +// 0x0d 0x00 0x00 0x00 0x00 0x00 +// 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 3, pre-emphasis 0 */ +// 0x0d 0x00 0x00 0x00 0x00 0x00 +// >; +// status = "okay"; +//}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; + }; + +&hdptxphy_hdmi0 { + status = "okay"; + }; + +&i2s2_2ch { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2c2 { + + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + int-n-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + pt7c4363: pt7c4363@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pt7c4363"; + wakeup-source; + }; + + mcu: khadas-mcu@18 { + compatible = "khadas-mcu"; + status = "okay"; + reg = <0x18>; + fan,trig_temp_level0 = <50>; + fan,trig_temp_level1 = <60>; + fan,trig_temp_level2 = <70>; + fan,trig_temp_level3 = <80>; + hwver = "EDGE2.V11"; + + }; +}; + +&reboot_mode { + mode-reboot_test = ; +}; + +&i2c3 { + status = "okay"; + + gs_kxtj3: gs_kxtj3@e { + compatible = "gs_kxtj3"; + reg = <0x0e>; + irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + status = "okay"; + }; + + es8316: es8316@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x10>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default","hp_det","spk_con"; + pinctrl-0 = <&i2s0_mclk>,<&hp_det>,<&spk_con>; + spk-con-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + }; + +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + status = "okay"; +}; + +&i2c5 { + status = "disabled"; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + ft5336@38 { + compatible = "edt,edt-ft5336", "ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = ; + reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_rst_gpio>; + status = "okay"; + }; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + max-x = <1920>; + max-y = <1200>; + tp-size = <89>; + }; + +}; + +&pcie2x1l1 { +// reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "disabled"; +}; + +&pcie2x1l2 { +// reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pdm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pdm0m0_clk + &pdm0m0_clk1 + &pdm0m0_sdi0 + &pdm0m0_sdi1 + &pdm0m0_sdi2>; + rockchip,path-map = <0 1 2 3>; + status = "okay"; +}; + +&pinctrl { + audio { + hp_det: hp-det { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + spk_con: spk-con { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + lcd2_rst_gpio1: lcd2-rst-gpio1 { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + red_led_gpio: red-led-gpio { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + green_led_gpio: green-led-gpio { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + blue_led_gpio: blue-led-gpio { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_en: vcc-sd-en { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ft5336 { + tp_rst_gpio: tp-rst-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + // wifi_poweren_gpio: wifi-poweren-gpio { + // rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + // }; + }; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m3_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xeb KEY_POWER>, + <0xec KEY_MENU>, + <0xfc KEY_UP>, + <0xfd KEY_DOWN>, + <0xf1 KEY_LEFT>, + <0xe5 KEY_RIGHT>, + <0xf8 KEY_ENTER>, + <0xa7 KEY_VOLUMEDOWN>, + <0xa3 388>, + <0xa4 388>, + <0xf4 KEY_VOLUMEUP>, + <0xfe KEY_BACK>, + <0xb7 KEY_HOMEPAGE>; + }; +}; + +&pwm7 { + pinctrl-0 = <&pwm7m0_pins>; + status = "disabled"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&pwm13 { + pinctrl-0 = <&pwm13m1_pins>; + status = "okay"; +}; + + +&rockchip_suspend { + + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + | RKPM_SLP_PMU_DBG + ) + >; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&sdmmc { + status = "okay"; + card-detect-delay = <1200>; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; +}; + +&spdif_tx1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m1_tx>; +}; + +&spdif_tx1_dc { + status = "disabled"; +}; + +&spdif_tx1_sound { + status = "disabled"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spi1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vcc_1v8_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dtsi new file mode 100644 index 0000000000000..da7c6884e88b7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dtsi @@ -0,0 +1,1780 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Wesion Technology Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + home-key { + label = "home"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + backlight_mipi0: backlight-mipi0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip,dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + backlight_mipi1: backlight-mipi1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi0"; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight_mipi0>; + // reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 FF 05 + 15 00 02 FB 01 + 15 64 02 C5 01 + 15 00 02 FF EE + 15 00 02 FB 01 + 15 00 02 1F 45 + 15 00 02 24 4F + 15 00 02 38 C8 + 15 00 02 39 27 + 15 00 02 1E 77 + 15 00 02 1D 0F + 15 00 02 7E 71 + 15 00 02 7C 03 + 15 00 02 FF 00 + 15 00 02 FB 01 + 15 00 02 35 01 + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 00 01 + 15 00 02 01 55 + 15 00 02 02 40 + 15 00 02 05 40 + 15 00 02 06 4A + 15 00 02 07 24 + 15 00 02 08 0C + 15 00 02 0B 7D + 15 00 02 0C 7D + 15 00 02 0E B0 + 15 00 02 0F AE + 15 00 02 11 10 + 15 00 02 12 10 + 15 00 02 13 03 + 15 00 02 14 4A + 15 00 02 15 12 + 15 00 02 16 12 + 15 00 02 18 00 + 15 00 02 19 77 + 15 00 02 1A 55 + 15 00 02 1B 13 + 15 00 02 1C 00 + 15 00 02 1D 00 + 15 00 02 1E 13 + 15 00 02 1F 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 00 + 15 00 02 35 00 + 15 00 02 66 00 + 15 00 02 58 82 + 15 00 02 59 02 + 15 00 02 5A 02 + 15 00 02 5B 02 + 15 00 02 5C 82 + 15 00 02 5D 82 + 15 00 02 5E 02 + 15 00 02 5F 02 + 15 00 02 72 31 + 15 00 02 FF 05 + 15 00 02 FB 01 + 15 00 02 00 01 + 15 00 02 01 0B + 15 00 02 02 0C + 15 00 02 03 09 + 15 00 02 04 0A + 15 00 02 05 00 + 15 00 02 06 0F + 15 00 02 07 10 + 15 00 02 08 00 + 15 00 02 09 00 + 15 00 02 0A 00 + 15 00 02 0B 00 + 15 00 02 0C 00 + 15 00 02 0D 13 + 15 00 02 0E 15 + 15 00 02 0F 17 + 15 00 02 10 01 + 15 00 02 11 0B + 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56 + 15 00 02 A9 03 + 15 00 02 AA 66 + 15 00 02 AB 03 + 15 00 02 AC 76 + 15 00 02 AD 03 + 15 00 02 AE 85 + 15 00 02 AF 03 + 15 00 02 B0 90 + 15 00 02 B1 03 + 15 00 02 B2 CB + 15 00 02 B3 00 + 15 00 02 B4 DF + 15 00 02 B5 00 + 15 00 02 B6 E4 + 15 00 02 B7 00 + 15 00 02 B8 ED + 15 00 02 B9 00 + 15 00 02 BA F6 + 15 00 02 BB 00 + 15 00 02 BC FF + 15 00 02 BD 01 + 15 00 02 BE 07 + 15 00 02 BF 01 + 15 00 02 C0 10 + 15 00 02 C1 01 + 15 00 02 C2 18 + 15 00 02 C3 01 + 15 00 02 C4 20 + 15 00 02 C5 01 + 15 00 02 C6 3D + 15 00 02 C7 01 + 15 00 02 C8 56 + 15 00 02 C9 01 + 15 00 02 CA 84 + 15 00 02 CB 01 + 15 00 02 CC AB + 15 00 02 CD 01 + 15 00 02 CE EC + 15 00 02 CF 02 + 15 00 02 D0 22 + 15 00 02 D1 02 + 15 00 02 D2 23 + 15 00 02 D3 02 + 15 00 02 D4 55 + 15 00 02 D5 02 + 15 00 02 D6 8B + 15 00 02 D7 02 + 15 00 02 D8 AF + 15 00 02 D9 02 + 15 00 02 DA DF + 15 00 02 DB 03 + 15 00 02 DC 01 + 15 00 02 DD 03 + 15 00 02 DE 2C + 15 00 02 DF 03 + 15 00 02 E0 39 + 15 00 02 E1 03 + 15 00 02 E2 47 + 15 00 02 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15 00 02 9C 21 + 15 00 02 9D 03 + 15 00 02 9E 2E + 15 00 02 9F 03 + 15 00 02 A0 3D + 15 00 02 A2 03 + 15 00 02 A3 4C + 15 00 02 A4 03 + 15 00 02 A5 5E + 15 00 02 A6 03 + 15 00 02 A7 71 + 15 00 02 A9 03 + 15 00 02 AA 86 + 15 00 02 AB 03 + 15 00 02 AC 94 + 15 00 02 AD 03 + 15 00 02 AE FA + 15 00 02 AF 00 + 15 00 02 B0 00 + 15 00 02 B1 00 + 15 00 02 B2 21 + 15 00 02 B3 00 + 15 00 02 B4 4C + 15 00 02 B5 00 + 15 00 02 B6 6B + 15 00 02 B7 00 + 15 00 02 B8 85 + 15 00 02 B9 00 + 15 00 02 BA 9A + 15 00 02 BB 00 + 15 00 02 BC AD + 15 00 02 BD 00 + 15 00 02 BE BE + 15 00 02 BF 00 + 15 00 02 C0 CD + 15 00 02 C1 01 + 15 00 02 C2 01 + 15 00 02 C3 01 + 15 00 02 C4 29 + 15 00 02 C5 01 + 15 00 02 C6 68 + 15 00 02 C7 01 + 15 00 02 C8 98 + 15 00 02 C9 01 + 15 00 02 CA E5 + 15 00 02 CB 02 + 15 00 02 CC 1E + 15 00 02 CD 02 + 15 00 02 CE 20 + 15 00 02 CF 02 + 15 00 02 D0 52 + 15 00 02 D1 02 + 15 00 02 D2 88 + 15 00 02 D3 02 + 15 00 02 D4 AA + 15 00 02 D5 02 + 15 00 02 D6 D7 + 15 00 02 D7 02 + 15 00 02 D8 F7 + 15 00 02 D9 03 + 15 00 02 DA 21 + 15 00 02 DB 03 + 15 00 02 DC 2E + 15 00 02 DD 03 + 15 00 02 DE 3D + 15 00 02 DF 03 + 15 00 02 E0 4C + 15 00 02 E1 03 + 15 00 02 E2 5E + 15 00 02 E3 03 + 15 00 02 E4 71 + 15 00 02 E5 03 + 15 00 02 E6 86 + 15 00 02 E7 03 + 15 00 02 E8 94 + 15 00 02 E9 03 + 15 00 02 EA FA + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 FF 02 + 15 00 02 FB 01 + 15 00 02 FF 04 + 15 00 02 FB 01 + 15 00 02 FF 00 + 15 00 02 D3 05 + 15 00 02 D4 04 + 05 78 01 11 + 15 00 02 FF 00 + 15 00 02 35 00 + 05 0A 01 29 + ]; + + panel-init-sequence2 = [ + 39 00 04 B9 FF 83 99 + 39 00 05 BA 63 23 68 CF + 15 00 02 D2 55 + 39 00 10 B1 02 04 70 90 01 32 33 11 11 4D 57 56 73 02 02 + 39 00 0c B2 00 80 80 AE 0A 0E 75 11 00 00 00 + 39 00 2f B4 00 FF 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 21 03 00 00 08 A6 88 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 00 00 08 A6 00 08 11 + 39 00 22 D3 00 00 00 00 00 00 18 18 32 10 09 00 09 32 10 00 00 00 00 00 00 00 00 11 00 02 02 03 00 00 00 0A 40 + 39 00 21 D5 18 18 18 18 21 20 18 18 19 19 19 19 18 18 18 18 03 02 01 00 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 21 D6 18 18 18 18 20 21 19 19 18 18 19 19 18 18 18 18 00 01 02 03 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 09 D8 0A BE FA A0 0A BE FA A0 + 15 00 02 BD 01 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 02 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 00 + 39 00 37 E0 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 C5 BD C5 B6 C2 C2 62 5D 66 73 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 B5 BD C5 B6 C2 C2 62 5D 66 73 + 39 00 03 B6 97 97 + 15 00 02 CC C8 + 39 00 05 BF 40 41 50 19 + 39 00 03 C6 FF F9 + 39 00 03 C0 25 5A + 05 78 01 11 + 05 14 01 29 + ]; + + panel-exit-sequence = [ + 05 05 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <152200000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <104>; + hsync-len = <4>; + hback-porch = <127>; + vfront-porch = <4>; + vsync-len = <2>; + vback-porch = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + disp_timings01: display-timings1 { + native-mode = <&dsi0_timing01>; + dsi0_timing01: timing01 { + clock-frequency = <152350000>; + hactive = <1920>; + vactive = <1200>; + hfront-porch = <110>; + hsync-len = <4>; + hback-porch = <32>; + vfront-porch = <11>; + vsync-len = <4>; + vback-porch = <14>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "disabled"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight_mipi1>; +// reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 FF 05 + 15 00 02 FB 01 + 15 64 02 C5 01 + 15 00 02 FF EE + 15 00 02 FB 01 + 15 00 02 1F 45 + 15 00 02 24 4F + 15 00 02 38 C8 + 15 00 02 39 27 + 15 00 02 1E 77 + 15 00 02 1D 0F + 15 00 02 7E 71 + 15 00 02 7C 03 + 15 00 02 FF 00 + 15 00 02 FB 01 + 15 00 02 35 01 + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 00 01 + 15 00 02 01 55 + 15 00 02 02 40 + 15 00 02 05 40 + 15 00 02 06 4A + 15 00 02 07 24 + 15 00 02 08 0C + 15 00 02 0B 7D + 15 00 02 0C 7D + 15 00 02 0E B0 + 15 00 02 0F AE + 15 00 02 11 10 + 15 00 02 12 10 + 15 00 02 13 03 + 15 00 02 14 4A + 15 00 02 15 12 + 15 00 02 16 12 + 15 00 02 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15 00 02 B7 00 + 15 00 02 B8 ED + 15 00 02 B9 00 + 15 00 02 BA F6 + 15 00 02 BB 00 + 15 00 02 BC FF + 15 00 02 BD 01 + 15 00 02 BE 07 + 15 00 02 BF 01 + 15 00 02 C0 10 + 15 00 02 C1 01 + 15 00 02 C2 18 + 15 00 02 C3 01 + 15 00 02 C4 20 + 15 00 02 C5 01 + 15 00 02 C6 3D + 15 00 02 C7 01 + 15 00 02 C8 56 + 15 00 02 C9 01 + 15 00 02 CA 84 + 15 00 02 CB 01 + 15 00 02 CC AB + 15 00 02 CD 01 + 15 00 02 CE EC + 15 00 02 CF 02 + 15 00 02 D0 22 + 15 00 02 D1 02 + 15 00 02 D2 23 + 15 00 02 D3 02 + 15 00 02 D4 55 + 15 00 02 D5 02 + 15 00 02 D6 8B + 15 00 02 D7 02 + 15 00 02 D8 AF + 15 00 02 D9 02 + 15 00 02 DA DF + 15 00 02 DB 03 + 15 00 02 DC 01 + 15 00 02 DD 03 + 15 00 02 DE 2C + 15 00 02 DF 03 + 15 00 02 E0 39 + 15 00 02 E1 03 + 15 00 02 E2 47 + 15 00 02 E3 03 + 15 00 02 E4 56 + 15 00 02 E5 03 + 15 00 02 E6 66 + 15 00 02 E7 03 + 15 00 02 E8 76 + 15 00 02 E9 03 + 15 00 02 EA 85 + 15 00 02 EB 03 + 15 00 02 EC 90 + 15 00 02 ED 03 + 15 00 02 EE CB + 15 00 02 EF 00 + 15 00 02 F0 BB + 15 00 02 F1 00 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CB + 15 00 02 32 00 + 15 00 02 33 BB + 15 00 02 34 00 + 15 00 02 35 C0 + 15 00 02 36 00 + 15 00 02 37 CC + 15 00 02 38 00 + 15 00 02 39 D6 + 15 00 02 3A 00 + 15 00 02 3B E1 + 15 00 02 3D 00 + 15 00 02 3F EA + 15 00 02 40 00 + 15 00 02 41 F4 + 15 00 02 42 00 + 15 00 02 43 FE + 15 00 02 44 01 + 15 00 02 45 07 + 15 00 02 46 01 + 15 00 02 47 28 + 15 00 02 48 01 + 15 00 02 49 44 + 15 00 02 4A 01 + 15 00 02 4B 76 + 15 00 02 4C 01 + 15 00 02 4D A0 + 15 00 02 4E 01 + 15 00 02 4F E7 + 15 00 02 50 02 + 15 00 02 51 1F + 15 00 02 52 02 + 15 00 02 53 22 + 15 00 02 54 02 + 15 00 02 55 54 + 15 00 02 56 02 + 15 00 02 58 8B + 15 00 02 59 02 + 15 00 02 5A AF + 15 00 02 5B 02 + 15 00 02 5C E0 + 15 00 02 5D 03 + 15 00 02 5E 01 + 15 00 02 5F 03 + 15 00 02 60 2D + 15 00 02 61 03 + 15 00 02 62 39 + 15 00 02 63 03 + 15 00 02 64 47 + 15 00 02 65 03 + 15 00 02 66 57 + 15 00 02 67 03 + 15 00 02 68 65 + 15 00 02 69 03 + 15 00 02 6A 77 + 15 00 02 6B 03 + 15 00 02 6C 85 + 15 00 02 6D 03 + 15 00 02 6E 8F + 15 00 02 6F 03 + 15 00 02 70 CB + 15 00 02 71 00 + 15 00 02 72 00 + 15 00 02 73 00 + 15 00 02 74 21 + 15 00 02 75 00 + 15 00 02 76 4C + 15 00 02 77 00 + 15 00 02 78 6B + 15 00 02 79 00 + 15 00 02 7A 85 + 15 00 02 7B 00 + 15 00 02 7C 9A + 15 00 02 7D 00 + 15 00 02 7E AD + 15 00 02 7F 00 + 15 00 02 80 BE + 15 00 02 81 00 + 15 00 02 82 CD + 15 00 02 83 01 + 15 00 02 84 01 + 15 00 02 85 01 + 15 00 02 86 29 + 15 00 02 87 01 + 15 00 02 88 68 + 15 00 02 89 01 + 15 00 02 8A 98 + 15 00 02 8B 01 + 15 00 02 8C E5 + 15 00 02 8D 02 + 15 00 02 8E 1E + 15 00 02 8F 02 + 15 00 02 90 30 + 15 00 02 91 02 + 15 00 02 92 52 + 15 00 02 93 02 + 15 00 02 94 88 + 15 00 02 95 02 + 15 00 02 96 AA + 15 00 02 97 02 + 15 00 02 98 D7 + 15 00 02 99 02 + 15 00 02 9A F7 + 15 00 02 9B 03 + 15 00 02 9C 21 + 15 00 02 9D 03 + 15 00 02 9E 2E + 15 00 02 9F 03 + 15 00 02 A0 3D + 15 00 02 A2 03 + 15 00 02 A3 4C + 15 00 02 A4 03 + 15 00 02 A5 5E + 15 00 02 A6 03 + 15 00 02 A7 71 + 15 00 02 A9 03 + 15 00 02 AA 86 + 15 00 02 AB 03 + 15 00 02 AC 94 + 15 00 02 AD 03 + 15 00 02 AE FA + 15 00 02 AF 00 + 15 00 02 B0 00 + 15 00 02 B1 00 + 15 00 02 B2 21 + 15 00 02 B3 00 + 15 00 02 B4 4C + 15 00 02 B5 00 + 15 00 02 B6 6B + 15 00 02 B7 00 + 15 00 02 B8 85 + 15 00 02 B9 00 + 15 00 02 BA 9A + 15 00 02 BB 00 + 15 00 02 BC AD + 15 00 02 BD 00 + 15 00 02 BE BE + 15 00 02 BF 00 + 15 00 02 C0 CD + 15 00 02 C1 01 + 15 00 02 C2 01 + 15 00 02 C3 01 + 15 00 02 C4 29 + 15 00 02 C5 01 + 15 00 02 C6 68 + 15 00 02 C7 01 + 15 00 02 C8 98 + 15 00 02 C9 01 + 15 00 02 CA E5 + 15 00 02 CB 02 + 15 00 02 CC 1E + 15 00 02 CD 02 + 15 00 02 CE 20 + 15 00 02 CF 02 + 15 00 02 D0 52 + 15 00 02 D1 02 + 15 00 02 D2 88 + 15 00 02 D3 02 + 15 00 02 D4 AA + 15 00 02 D5 02 + 15 00 02 D6 D7 + 15 00 02 D7 02 + 15 00 02 D8 F7 + 15 00 02 D9 03 + 15 00 02 DA 21 + 15 00 02 DB 03 + 15 00 02 DC 2E + 15 00 02 DD 03 + 15 00 02 DE 3D + 15 00 02 DF 03 + 15 00 02 E0 4C + 15 00 02 E1 03 + 15 00 02 E2 5E + 15 00 02 E3 03 + 15 00 02 E4 71 + 15 00 02 E5 03 + 15 00 02 E6 86 + 15 00 02 E7 03 + 15 00 02 E8 94 + 15 00 02 E9 03 + 15 00 02 EA FA + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 FF 02 + 15 00 02 FB 01 + 15 00 02 FF 04 + 15 00 02 FB 01 + 15 00 02 FF 00 + 15 00 02 D3 05 + 15 00 02 D4 04 + 05 78 01 11 + 15 00 02 FF 00 + 15 00 02 35 00 + 05 0A 01 29 + ]; + + panel-init-sequence2 = [ + 39 00 04 B9 FF 83 99 + 39 00 05 BA 63 23 68 CF + 15 00 02 D2 55 + 39 00 10 B1 02 04 70 90 01 32 33 11 11 4D 57 56 73 02 02 + 39 00 0c B2 00 80 80 AE 0A 0E 75 11 00 00 00 + 39 00 2f B4 00 FF 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 21 03 00 00 08 A6 88 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 00 00 08 A6 00 08 11 + 39 00 22 D3 00 00 00 00 00 00 18 18 32 10 09 00 09 32 10 00 00 00 00 00 00 00 00 11 00 02 02 03 00 00 00 0A 40 + 39 00 21 D5 18 18 18 18 21 20 18 18 19 19 19 19 18 18 18 18 03 02 01 00 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 21 D6 18 18 18 18 20 21 19 19 18 18 19 19 18 18 18 18 00 01 02 03 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 09 D8 0A BE FA A0 0A BE FA A0 + 15 00 02 BD 01 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 02 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 00 + 39 00 37 E0 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 C5 BD C5 B6 C2 C2 62 5D 66 73 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 B5 BD C5 B6 C2 C2 62 5D 66 73 + 39 00 03 B6 97 97 + 15 00 02 CC C8 + 39 00 05 BF 40 41 50 19 + 39 00 03 C6 FF F9 + 39 00 03 C0 25 5A + 05 78 01 11 + 05 14 01 29 + ]; + + panel-exit-sequence = [ + 05 05 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <152198100>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <104>; + hsync-len = <4>; + hback-porch = <127>; + vfront-porch = <4>; + vsync-len = <2>; + vback-porch = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; From eeb5eef293883b5d7b70eed5cd264afe0ab48ef5 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 30 Mar 2023 11:36:11 +0800 Subject: [PATCH 031/249] khadas: drivers/watchdog - squashed, scripts/packaging/etc removed, grouped by directory - source - https://github.com/khadas/linux/commits/khadas-edges-5.10.y - https://github.com/khadas/linux/commit/85a8b25939a28b66f2147823b62f5861d23d69c1 --- drivers/watchdog/Kconfig | 10 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/khadas_wdt.c | 157 ++++++++++++++++++++++++++++++++++ 3 files changed, 168 insertions(+) create mode 100644 drivers/watchdog/khadas_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b64bc49c7f30e..51c66b8236a85 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -832,6 +832,16 @@ config MEDIATEK_WATCHDOG To compile this driver as a module, choose M here: the module will be called mtk_wdt. +config KHADAS_WATCHDOG + tristate "KHADAS watchdog support" + default y + help + Say Y here to include watchdog support embedded into KHADAS. + If the watchdog timer expires, TPS3851 will shut down all its power + supplies. + To compile this driver as a module, choose M here: the + module will be called KHADAS_wdt. + config DIGICOLOR_WATCHDOG tristate "Conexant Digicolor SoCs watchdog support" depends on ARCH_DIGICOLOR || COMPILE_TEST diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index d41e5f830ae7f..5387c78e273a8 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC) += pretimeout_panic.o obj-$(CONFIG_PCWATCHDOG) += pcwd.o obj-$(CONFIG_MIXCOMWD) += mixcomwd.o obj-$(CONFIG_WDT) += wdt.o +obj-$(CONFIG_KHADAS_WATCHDOG) += khadas_wdt.o # PCI-based Watchdog Cards obj-$(CONFIG_PCIPCWATCHDOG) += pcwd_pci.o diff --git a/drivers/watchdog/khadas_wdt.c b/drivers/watchdog/khadas_wdt.c new file mode 100644 index 0000000000000..3b28a52fd6ae0 --- /dev/null +++ b/drivers/watchdog/khadas_wdt.c @@ -0,0 +1,157 @@ +//#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct timer_list mytimer; +static unsigned int hw_margin = 3; +static int khadas_input_pin; +static unsigned int khadas_enble = 1; + +static void time_pre(struct timer_list *timer) +{ + static unsigned int flag=0; + flag = !flag; + gpio_direction_output(khadas_input_pin, flag); + + //printk("%s\n", __func__); + mytimer.expires = jiffies + hw_margin * HZ/1000; // 500ms 运行一次 + if(khadas_enble) + mod_timer(&mytimer, mytimer.expires); +} + +/* +static void wdt_exit(void) +{ + if(timer_pending(&mytimer)) + { + del_timer(&mytimer); + } + printk("exit Success \n"); +}*/ + +static ssize_t show_enble(struct class *cls, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", khadas_enble); +} + +static ssize_t store_enble(struct class *cls, struct class_attribute *attr, + const char *buf, size_t count) +{ + int enable; + + if (kstrtoint(buf, 0, &enable)){ + printk("khadas_enble error\n"); + return -EINVAL; + } + printk("khadas_enble=%d\n",enable); + khadas_enble = enable; + if(khadas_enble){ + mytimer.expires = jiffies + hw_margin * HZ/1000; // 500ms 运行一次 + mod_timer(&mytimer, mytimer.expires); + } + return count; +} + +static ssize_t store_pin_out(struct class *cls, struct class_attribute *attr, + const char *buf, size_t count) +{ + int enable; + + if (kstrtoint(buf, 0, &enable)){ + printk("khadas_pin_out error\n"); + return -EINVAL; + } + printk("khadas_pin_out=%d\n",enable); + gpio_direction_output(khadas_input_pin, enable); + return count; +} + +static struct class_attribute khadas_attrs[] = { + __ATTR(enble, 0644, show_enble, store_enble), + __ATTR(pin_out, 0644, NULL, store_pin_out), +}; + +static void create_khadas_attrs(void) +{ + int i; + struct class *khadas_class; + printk("%s\n",__func__); + khadas_class = class_create(THIS_MODULE, "khadas"); + if (IS_ERR(khadas_class)) { + pr_err("create khadas_class debug class fail\n"); + return; + } + for (i = 0; i < ARRAY_SIZE(khadas_attrs); i++) { + if (class_create_file(khadas_class, &khadas_attrs[i])) + pr_err("create khadas attribute %s fail\n", khadas_attrs[i].attr.name); + } +} + +static int wdt_probe(struct platform_device *pdev) +{ + const char *value; + int ret; + printk("hw_wdt enter probe\n"); + + ret = of_property_read_u32(pdev->dev.of_node,"hw_margin_ms", &hw_margin); + if (ret) + return ret; + + ret = of_property_read_string(pdev->dev.of_node, + "hw-gpios", &value); + if (ret) { + printk("no hw-gpios"); + return -1; + } else { + khadas_input_pin = of_get_named_gpio_flags + (pdev->dev.of_node, + "hw-gpios", + 0, NULL); + printk("hlm hw-gpios: %d.\n", khadas_input_pin); + ret = gpio_request(khadas_input_pin, "khadas"); + } + + timer_setup(&mytimer, time_pre, 0); + mytimer.expires = jiffies + hw_margin * HZ/1000; //// 5ms 运行一次 + add_timer(&mytimer); + create_khadas_attrs(); + return 0; +} + +static const struct of_device_id hw_khadas_wdt_dt_ids[] = { + { .compatible = "linux,wdt-khadas", }, + { } +}; +MODULE_DEVICE_TABLE(of, hw_khadas_wdt_dt_ids); + +static struct platform_driver khadas_wdt_driver = { + .driver = { + .name = "hw_khadas_wdt", + .of_match_table = hw_khadas_wdt_dt_ids, + }, + .probe = wdt_probe, +}; + +static int __init wdt_drv_init(void) +{ + return platform_driver_register(&khadas_wdt_driver); +} +arch_initcall(wdt_drv_init); + +MODULE_LICENSE("GPL"); From 38662585fd914f5241267ff793aa90ab779e1ee8 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 30 Mar 2023 12:02:13 +0800 Subject: [PATCH 032/249] khadas: drivers/net - squashed, scripts/packaging/etc removed, grouped by directory - source - https://github.com/khadas/linux/commits/khadas-edges-5.10.y - https://github.com/khadas/linux/commit/85a8b25939a28b66f2147823b62f5861d23d69c1 --- drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_config.h | 1 + drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/wl_cfgscan.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_config.h b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_config.h index fd9e4a1007c27..623cad92545b0 100755 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_config.h +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_config.h @@ -21,6 +21,7 @@ #define FW_TYPE_AG 1 #define FW_PATH_AUTO_SELECT 1 +#define CONFIG_PATH_AUTO_SELECT #ifdef BCMDHD_MDRIVER #define CONFIG_PATH_AUTO_SELECT #else diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/wl_cfgscan.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/wl_cfgscan.c index 8d0e9094f5f61..be3fc3721113b 100755 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/wl_cfgscan.c +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/wl_cfgscan.c @@ -2314,7 +2314,7 @@ wl_run_escan(struct bcm_cfg80211 *cfg, struct net_device *ndev, } bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr); - WL_MSG(ndev->name, "LEGACY_SCAN sync ID: %d, bssidx: %d\n", sync_id, bssidx); + // WL_MSG(ndev->name, "LEGACY_SCAN sync ID: %d, bssidx: %d\n", sync_id, bssidx); err = wldev_iovar_setbuf(ndev, "escan", params, params_size, cfg->escan_ioctl_buf, WLC_IOCTL_MEDLEN, NULL); if (unlikely(err)) { From 587e9c8a40ddad2e1b6e02a37e34537b2076f1c9 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 9 Mar 2023 11:22:13 +0800 Subject: [PATCH 033/249] khadas: drivers/usb/core - squashed, scripts/packaging/etc removed, grouped by directory - source - https://github.com/khadas/linux/commits/khadas-edges-5.10.y - https://github.com/khadas/linux/commit/85a8b25939a28b66f2147823b62f5861d23d69c1 --- drivers/usb/core/quirks.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index 906c051c9740b..37fa019d5d1a8 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -475,6 +475,9 @@ static const struct usb_device_id usb_quirk_list[] = { /* Lenovo Powered USB-C Travel Hub (4X90S92381, RTL8153 GigE) */ { USB_DEVICE(0x17ef, 0x721e), .driver_info = USB_QUIRK_NO_LPM }, + /* SPCA2100 PC Camera */ + { USB_DEVICE(0x15aa, 0x1555), .driver_info = USB_QUIRK_AUTO_SUSPEND }, + /* Lenovo ThinkCenter A630Z TI024Gen3 usb-audio */ { USB_DEVICE(0x17ef, 0xa012), .driver_info = USB_QUIRK_DISCONNECT_SUSPEND }, From 8d04eb3203c3183783d822dc5ed3d4446678a6d3 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 30 Mar 2023 11:36:53 +0800 Subject: [PATCH 034/249] khadas: drivers/leds - squashed, scripts/packaging/etc removed, grouped by directory - source - https://github.com/khadas/linux/commits/khadas-edges-5.10.y - https://github.com/khadas/linux/commit/85a8b25939a28b66f2147823b62f5861d23d69c1 --- drivers/leds/leds-gpio.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c index 092eb59a7d325..a8682db8a4116 100644 --- a/drivers/leds/leds-gpio.c +++ b/drivers/leds/leds-gpio.c @@ -79,6 +79,25 @@ static int create_gpio_led(const struct gpio_led *template, struct led_init_data init_data = {}; int ret, state; + led_dat->gpiod = template->gpiod; + if (!led_dat->gpiod) { + unsigned long flags = GPIOF_OUT_INIT_LOW; + if (!gpio_is_valid(template->gpio)) { + dev_info(parent, "Skipping unavailable LED gpio %d (%s)\n", + template->gpio, template->name); + return 0; + } + if (template->active_low) + flags |= GPIOF_ACTIVE_LOW; + ret = devm_gpio_request_one(parent, template->gpio, flags, + template->name); + if (ret < 0) + return ret; + led_dat->gpiod = gpio_to_desc(template->gpio); + if (!led_dat->gpiod) + return -EINVAL; + } + led_dat->cdev.name = template->name; led_dat->cdev.default_trigger = template->default_trigger; led_dat->can_sleep = gpiod_cansleep(led_dat->gpiod); if (!led_dat->can_sleep) @@ -127,6 +146,12 @@ struct gpio_leds_priv { struct gpio_led_data leds[]; }; +static inline int sizeof_gpio_leds_priv(int num_leds) +{ + return sizeof(struct gpio_leds_priv) + + (sizeof(struct gpio_led_data) * num_leds); +} + static struct gpio_leds_priv *gpio_leds_create(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -146,19 +171,30 @@ static struct gpio_leds_priv *gpio_leds_create(struct platform_device *pdev) struct gpio_led_data *led_dat = &priv->leds[priv->num_leds]; struct gpio_led led = {}; + struct device_node *np = to_of_node(child); + ret = fwnode_property_read_string(child, "label", &led.name); + if (ret && IS_ENABLED(CONFIG_OF) && np) + led.name = np->name; + if (!led.name) { + fwnode_handle_put(child); + return ERR_PTR(-EINVAL); + } + /* * Acquire gpiod from DT with uninitialized label, which * will be updated after LED class device is registered, * Only then the final LED name is known. */ led.gpiod = devm_fwnode_get_gpiod_from_child(dev, NULL, child, - GPIOD_ASIS, - NULL); + GPIOD_ASIS,led.name); if (IS_ERR(led.gpiod)) { fwnode_handle_put(child); return ERR_CAST(led.gpiod); } + fwnode_property_read_string(child, "linux,default-trigger", + &led.default_trigger); + led_dat->gpiod = led.gpiod; led.default_state = led_init_default_state_get(child); From 261a6ef2d8c66f4392a1d5fdaa0f9ea9e78e0726 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Muhammed=20Efe=20=C3=87etin?= Date: Fri, 5 May 2023 15:37:00 +0300 Subject: [PATCH 035/249] drm/panel: Add Innolux AFJ101 BA2131 panel --- drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile | 1 + .../drm/panel/panel-innolux-afj101-ba2131.c | 492 ++++++++++++++++++ 3 files changed, 504 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-innolux-afj101-ba2131.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 0cd428ad5c675..1e26bcdc261ae 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -751,4 +751,15 @@ config DRM_PANEL_XINPENG_XPP055C272 Say Y here if you want to enable support for the Xinpeng XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI system interfaces. + +config DRM_PANEL_INNOLUX_AFJ101_BA2131 + tristate "Innolux AFJ101 BA2131 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Innolux BA2131 + TFT-LCD modules. The panel has a 800x1280 resolution and uses + 24 bit RGB per pixel. It provides a MIPI DSI interface to + the host and has a built-in LED backlight. endmenu diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 61d09b6420398..1dd773ebb5a12 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o +obj-$(CONFIG_DRM_PANEL_INNOLUX_AFJ101_BA2131) += panel-innolux-afj101-ba2131.o obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o obj-$(CONFIG_DRM_PANEL_JADARD_JD9365DA_H3) += panel-jadard-jd9365da-h3.o diff --git a/drivers/gpu/drm/panel/panel-innolux-afj101-ba2131.c b/drivers/gpu/drm/panel/panel-innolux-afj101-ba2131.c new file mode 100644 index 0000000000000..4464741b1e2ef --- /dev/null +++ b/drivers/gpu/drm/panel/panel-innolux-afj101-ba2131.c @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2020 Kali Prasad + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include