From 93dec8f233bff5d6bc77c637959b2e662d9fc297 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Fri, 28 Jun 2024 20:21:13 +0200 Subject: [PATCH 1/2] add FriendlyElec's 5.10-rkr6 NanoPi R5S/R5C/R5S-LTS - straight from https://github.com/friendlyarm/kernel-rockchip/tree/nanopi5-v5.10.y_opt - at sha1 83ad55ea02e284cb96b49df7eda89dc6797d9d9c --- arch/arm64/boot/dts/rockchip/Makefile | 6 + .../dts/rockchip/rk3568-nanopi5-common.dtsi | 960 ++++++++++++++++++ .../dts/rockchip/rk3568-nanopi5-rev01.dts | 315 ++++++ .../dts/rockchip/rk3568-nanopi5-rev02.dts | 216 ++++ .../dts/rockchip/rk3568-nanopi5-rev03.dts | 18 + .../dts/rockchip/rk3568-nanopi5-rev04.dts | 18 + .../dts/rockchip/rk3568-nanopi5-rev07.dts | 72 ++ 7 files changed, 1605 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev03.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev04.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a7d846a369c13..aa008a5d35e75 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -167,6 +167,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-hnas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev01.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev02.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev03.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev04.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev05.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev07.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi new file mode 100644 index 0000000000000..41cdf3bd6ce81 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi @@ -0,0 +1,960 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "FriendlyElec boards based on Rockchip RK3568"; + compatible = "friendlyelec,nanopi5", + "rockchip,rk3568"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 coherent_pool=1m"; + }; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdhci; + mmc3 = &sdmmc2; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + mach: board { + compatible = "friendlyelec,board"; + machine = "NANOPI5"; + hwrev = <255>; + model = "NanoPi 5 Series"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>; + nvmem-cell-names = "id", "cpu-version"; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec 0>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vdd_usbc: vdd-usbc { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc3v3_sysp: vcc3v3-sysp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sysp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_sysp: vcc5v0-sysp { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sysp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc3v3_sysp>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sysp>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sysp>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + test-power { + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +/* video_phy0/1 needs to be enabled when dsi0/1 is enabled */ +&dsi0 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc3v3_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "disabled"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm4 { + status = "disabled"; +}; + +&pwm5 { + status = "disabled"; +}; + +&pwm7 { + status = "disabled"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; +}; + +&reserved_memory { + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 0x10000000 0x0 0x00800000>; + linux,cma-default; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + rockchip,disable-auto-freq; + assigned-clock-rates = <396000000>, <396000000>, <396000000>, <600000000>; + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + support-multi-area; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <( + 1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 )>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_SMART0 | 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + status = "disabled"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts new file mode 100644 index 0000000000000..7bec22082dba5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include "rk3568-nanopi5-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R5S"; + compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; + + aliases { + ethernet1 = &r8125_1; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 18 102 170 255>; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sysp>; + pwms = <&pwm0 0 50000 0>; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc3v3_sysp>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + status = "disabled"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mach { + hwrev = <1>; + model = "NanoPi R5S"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_int>; + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie2x1 { + num-viewport = <4>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@00 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_1: pcie@01,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie3x1 { + num-viewport = <4>; + rockchip,bifurcation; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@10 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_2: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie3x2 { + max-link-speed = <2>; + num-lanes = <1>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + rockchip,bifurcation; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + gmac_int: gmac-int { + rockchip,pins = + <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata2 { + status = "disabled"; +}; + +&soc_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +/* GPIO Connector */ +&spi1 { + num-cs = <1>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + pinctrl-1 = <&spi1m1_cs0 &spi1m1_pins_hs>; + status = "disabled"; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; + status = "disabled"; +}; + +&uart7 { + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; +}; + +&uart9 { + pinctrl-0 = <&uart9m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts new file mode 100644 index 0000000000000..6781337edcf8c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include "rk3568-nanopi5-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; + + aliases { + ethernet0 = &r8125_1; + ethernet1 = &r8125_2; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + m2_wlan_radio: m2-wlan-radio { + compatible = "rfkill-gpio"; + type = "wlan"; + shutdown-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + status = "disabled"; +}; + +&mach { + hwrev = <2>; + model = "NanoPi R5C"; +}; + +&i2c5 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie2x1 { + num-viewport = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&m2_w_disable_pin>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie3x1 { + num-viewport = <4>; + rockchip,bifurcation; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@10 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_2: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie3x2 { + num-viewport = <4>; + rockchip,bifurcation; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@20 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_1: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + m2-pins { + m2_w_disable_pin: m2-w-disable-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "disabled"; +}; + +&sata2 { + status = "disabled"; +}; + +&sfc { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev03.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev03.dts new file mode 100644 index 0000000000000..128d07ab30d3e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev03.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev02.dts" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; +}; + +&mach { + hwrev = <3>; + model = "NanoPi R5C"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev04.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev04.dts new file mode 100644 index 0000000000000..cde69197b66d8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev04.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev02.dts" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; +}; + +&mach { + hwrev = <4>; + model = "NanoPi R5C"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts new file mode 100644 index 0000000000000..e59628356f045 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev01.dts" + +/ { + model = "FriendlyElec NanoPi R5S C1"; + compatible = "friendlyelec,nanopi-r5s-c1", "rockchip,rk3568"; + + m2-wlan-radio { + compatible = "rfkill-gpio"; + type = "wlan"; + shutdown-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&mach { + hwrev = <7>; + model = "NanoPi R5S C1"; +}; + +/delete-node/ &r8125_2; + +&pcie3x1 { + pinctrl-names = "default"; + pinctrl-0 = <&m2_w_disable_pin>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; +}; + +&pcie3x2 { + max-link-speed = <3>; +}; + +&pinctrl { + m2-pins { + m2_w_disable_pin: m2-w-disable-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&spi1 { + status = "okay"; + + spi_oled091: oled091@0 { + status = "okay"; + compatible = "solomon,ssd1306"; + reg = <0>; + spi-max-frequency = <10000000>; + dc-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + width = <128>; + height = <32>; + buswidth = <8>; + fps = <30>; + rotate = <0>; + }; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; + status = "disabled"; +}; + +&uart7 { + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; +}; From 8681a80cbfc9d65277e960d5c2080d669aba6b64 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Fri, 28 Jun 2024 20:23:29 +0200 Subject: [PATCH 2/2] add FriendlyElec's 5.10-rkr6 NanoPi R5S/R5C/R5S-LTS (update from 6.1-rkr1) - straight from https://github.com/friendlyarm/kernel-rockchip/tree/nanopi6-v6.1.y - at sha1 34cd890017997ea3be9524977b278ed4c21298b9 - just blatantly overwrite with 6.1-rkr1 stuff --- .../dts/rockchip/rk3568-nanopi5-common.dtsi | 35 +++++++++---- .../dts/rockchip/rk3568-nanopi5-rev01.dts | 6 +-- .../dts/rockchip/rk3568-nanopi5-rev02.dts | 9 +++- .../dts/rockchip/rk3568-nanopi5-rev05.dts | 52 +++++++++++++++++++ 4 files changed, 88 insertions(+), 14 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev05.dts diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi index 41cdf3bd6ce81..d92d197511dc1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi @@ -84,7 +84,7 @@ compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <128>; - simple-audio-card,name = "rockchip,hdmi"; + simple-audio-card,name = "rockchip,hdmi0"; status = "disabled"; simple-audio-card,cpu { @@ -123,7 +123,7 @@ }; rk809_sound: rk809-sound { - status = "okay"; + status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,name = "rockchip,rk809-codec"; @@ -133,7 +133,7 @@ sound-dai = <&i2s1_8ch>; }; simple-audio-card,codec { - sound-dai = <&rk809_codec 0>; + sound-dai = <&rk809_codec>; }; }; @@ -229,6 +229,19 @@ pinctrl-0 = <&vcc5v0_otg_en>; }; + simple_bat: battery { + compatible = "simple-battery"; + voltage-max-design-microvolt = <13000000>; + voltage-min-design-microvolt = <4500000>; + }; + + simple_vin: simple-vin { + compatible = "simple-adc-power-v1"; + io-channels = <&saradc 2>; + io-channel-names = "voltage"; + monitored-battery = <&simple_bat>; + }; + test-power { status = "okay"; }; @@ -562,7 +575,7 @@ }; rk809_codec: codec { - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; clocks = <&cru I2S1_MCLKOUT>; clock-names = "mclk"; @@ -573,7 +586,6 @@ pinctrl-0 = <&i2s1m0_mclk>; hp-volume = <20>; spk-volume = <3>; - mic-in-differential; status = "okay"; }; }; @@ -592,7 +604,7 @@ &i2s1_8ch { status = "disabled"; - rockchip,clk-trcm = <1>; + rockchip,trcm-sync-tx-only; pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx @@ -774,6 +786,10 @@ status = "okay"; }; +&crypto { + status = "okay"; +}; + &rockchip_suspend { status = "okay"; }; @@ -842,11 +858,11 @@ }; &u2phy0_otg { + phy-supply = <&vcc5v0_otg>; status = "okay"; }; &u2phy1_host { - phy-supply = <&vcc5v0_otg>; status = "okay"; }; @@ -929,8 +945,9 @@ &vop { status = "okay"; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + vop-supply = <&vdd_logic>; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; support-multi-area; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts index 7bec22082dba5..290ed0b158e95 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts @@ -178,12 +178,12 @@ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; status = "okay"; - pcie@00 { + pcie@0,0 { reg = <0x00000000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - r8125_1: pcie@01,0 { + r8125_1: pcie@1,0 { reg = <0x000000 0 0 0 0>; local-mac-address = [ 00 00 00 00 00 00 ]; }; @@ -197,7 +197,7 @@ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; status = "okay"; - pcie@10 { + pcie@0,0 { reg = <0x00100000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts index 6781337edcf8c..8d0bb45eaa4ad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts @@ -130,7 +130,7 @@ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; status = "okay"; - pcie@10 { + pcie@0,0 { reg = <0x00100000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -148,7 +148,7 @@ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; status = "okay"; - pcie@20 { + pcie@0,0 { reg = <0x00200000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -214,3 +214,8 @@ &sfc { status = "disabled"; }; + +&simple_bat { + voltage-max-design-microvolt = <5400000>; + voltage-min-design-microvolt = <4200000>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev05.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev05.dts new file mode 100644 index 0000000000000..7a6c5d6048126 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev05.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev01.dts" + +/ { + model = "FriendlyElec NanoPi R5S LTS"; + compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; +}; + +&mach { + hwrev = <5>; + model = "NanoPi R5S LTS"; +}; + +&pcie3x2 { + max-link-speed = <3>; +}; + +&pwm7 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + remote_pwm_id = <7>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xc43b>; + rockchip,key_table = + <0xff KEY_POWER>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xf2 KEY_UP>, + <0xea KEY_DOWN>, + <0xee KEY_ENTER>, + <0xe9 KEY_MUTE>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf3 KEY_VOLUMEUP>, + <0xae KEY_MENU>, + <0xeb KEY_LEFTMETA>, + <0xaf KEY_BACK>, + <0xf7 KEY_MODE>, + <0xe5 KEY_SYSRQ>, + <0xf5 KEY_ESC>; + }; +};