diff --git a/.github/workflows/compile.yaml b/.github/workflows/compile.yaml new file mode 100644 index 0000000000000..018b227049d46 --- /dev/null +++ b/.github/workflows/compile.yaml @@ -0,0 +1,54 @@ +name: Build kernel on PR + +on: + workflow_dispatch: + pull_request: + types: [opened, synchronize] + +jobs: + Build: + name: Compile and upload kernel + runs-on: rockchip + if: ${{ github.repository_owner == 'armbian' }} + env: + OCI_TARGET_BASE: "ghcr.io/${{ github.repository }}/" # This is picked up by the Docker launcher automatically + steps: + # Login to ghcr.io, for later uploading rootfs to ghcr.io + - name: Docker Login to GitHub Container Registry + uses: docker/login-action@v3 + with: + registry: ghcr.io + username: ${{ github.actor }} # GitHub username or org + password: ${{ secrets.GITHUB_TOKEN }} # GitHub actions builtin token. repo has to have pkg access. + + - name: Checkout build repo + uses: actions/checkout@v4 + with: + repository: armbian/build + ref: main + fetch-depth: 1 + clean: false + + - name: Build kernel at ${{ github.event.pull_request.head.sha }} + id: kernel + run: | + + rm -rf output/debs/* + mkdir -p userpatches/extensions/ + cat <<- EOF > userpatches/extensions/pull-request.sh + function post_family_config__force_commit_for_rk3588() { + KERNELBRANCH="commit:${{ github.event.pull_request.head.sha }}" + } + EOF + bash ./compile.sh kernel \ + SHARE_LOG=yes \ + BOARD=orangepi5 \ + BRANCH=vendor \ + ENABLE_EXTENSIONS="pull-request" + + - name: Upload artifact + uses: actions/upload-artifact@v4 + with: + name: linux-rockchip-vendor + path: output/debs/*.deb + retention-days: 5 diff --git a/.gitignore b/.gitignore index 6437e14db07b9..1cab9a5bee766 100644 --- a/.gitignore +++ b/.gitignore @@ -10,7 +10,6 @@ # # Normal rules (sorted alphabetically) # -.* *.a *.asn1.[ch] *.bin diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml new file mode 100644 index 0000000000000..f9e69e86b033a --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Mali Valhall GPU + +maintainers: + - Liviu Dudau + - Boris Brezillon + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + oneOf: + - items: + - enum: + - rockchip,rk3588-mali + - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable + + reg: + maxItems: 1 + + interrupts: + items: + - description: Job interrupt + - description: MMU interrupt + - description: GPU interrupt + + interrupt-names: + items: + - const: job + - const: mmu + - const: gpu + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + items: + - const: core + - const: coregroup + - const: stacks + + mali-supply: true + + operating-points-v2: true + opp-table: + type: object + + power-domains: + minItems: 1 + maxItems: 5 + + power-domain-names: + minItems: 1 + maxItems: 5 + + sram-supply: true + + "#cooling-cells": + const: 2 + + dynamic-power-coefficient: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the GPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - mali-supply + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-mali + then: + properties: + clocks: + minItems: 3 + power-domains: + maxItems: 1 + power-domain-names: false + +examples: + - | + #include + #include + #include + #include + + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0xfb000000 0x200000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clock-names = "core", "coregroup", "stacks"; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + power-domains = <&power RK3588_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + }; + }; + +... \ No newline at end of file diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml index 084960fd5a1fd..cf46b690010f2 100644 --- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml +++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml @@ -11,7 +11,7 @@ maintainers: description: | Khadas embeds a microcontroller on their VIM and Edge boards adding some - system feature as PWM Fan control (for VIM2 rev14 or VIM3), User memory + system feature as PWM Fan control (for VIM2 rev14, VIM3, Edge2), User memory storage, IR/Key resume control, system power LED control and more. properties: @@ -22,6 +22,11 @@ properties: "#cooling-cells": # Only needed for boards having FAN control feature const: 2 + cooling-levels: + description: Max speed of PWM fan. This property is necessary for Khadas Edge 2. + items: + maximum: 100 + reg: maxItems: 1 diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 36a76cbe90954..c010ad76f001a 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -158,6 +158,12 @@ DMA Fence Signalling Annotations .. kernel-doc:: drivers/dma-buf/dma-fence.c :doc: fence signalling annotation +DMA Fence Deadline Hints +~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence.c + :doc: deadline hints + DMA Fences Functions Reference ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst index 4411e6919a3df..7b6d9006306cf 100644 --- a/Documentation/gpu/driver-uapi.rst +++ b/Documentation/gpu/driver-uapi.rst @@ -6,3 +6,8 @@ drm/i915 uAPI ============= .. kernel-doc:: include/uapi/drm/i915_drm.h + +drm/panthor uAPI +================ + +.. kernel-doc:: i \ No newline at end of file diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index a79fd3549ff8c..709c4f149f6ec 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -466,6 +466,42 @@ DRM MM Range Allocator Function References .. kernel-doc:: drivers/gpu/drm/drm_mm.c :export: +DRM GPU VA Manager +================== + +Overview +-------- + +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c + :doc: Overview + +Split and Merge +--------------- + +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c + :doc: Split and Merge + +Locking +------- + +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c + :doc: Locking + +Examples +-------- + +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c + :doc: Examples + +DRM GPU VA Manager Function References +-------------------------------------- + +.. kernel-doc:: include/drm/drm_gpuva_mgr.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c + :export: + DRM Buddy Allocator =================== @@ -493,6 +529,18 @@ DRM Sync Objects .. kernel-doc:: drivers/gpu/drm/drm_syncobj.c :export: +DRM Execution context +===================== + +.. kernel-doc:: drivers/gpu/drm/drm_exec.c + :doc: Overview + +.. kernel-doc:: include/drm/drm_exec.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_exec.c + :export: + GPU Scheduler ============= @@ -502,6 +550,12 @@ Overview .. kernel-doc:: drivers/gpu/drm/scheduler/sched_main.c :doc: Overview +Flow Control +------------ + +.. kernel-doc:: drivers/gpu/drm/scheduler/sched_main.c + :doc: Flow Control + Scheduler Function References ----------------------------- diff --git a/Documentation/sphinx/maintainers_include.py b/Documentation/sphinx/maintainers_include.py index 328b3631a585c..b3c0e64238288 100755 --- a/Documentation/sphinx/maintainers_include.py +++ b/Documentation/sphinx/maintainers_include.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0 # -*- coding: utf-8; mode: python -*- # pylint: disable=R0903, C0330, R0914, R0912, E0401 diff --git a/MAINTAINERS b/MAINTAINERS index bbfedb0b20938..f3f1159e89a11 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1622,6 +1622,17 @@ T: git git://anongit.freedesktop.org/drm/drm-misc F: drivers/gpu/drm/panfrost/ F: include/uapi/drm/panfrost_drm.h +ARM MALI PANTHOR DRM DRIVER +M: Boris Brezillon +M: Steven Price +M: Liviu Dudau +L: dri-devel@lists.freedesktop.org +S: Supported +T: git git://anongit.freedesktop.org/drm/drm-misc +F: Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +F: drivers/gpu/drm/panthor/ +F: include/uapi/drm/panthor_drm.h + ARM MALI-DP DRM DRIVER M: Liviu Dudau M: Brian Starkey diff --git a/Makefile b/Makefile index 0e33150db2bfc..9fd4986a42657 100644 --- a/Makefile +++ b/Makefile @@ -865,7 +865,7 @@ stackp-flags-$(CONFIG_STACKPROTECTOR_STRONG) := -fstack-protector-strong KBUILD_CFLAGS += $(stackp-flags-y) -KBUILD_CFLAGS-$(CONFIG_WERROR) += -Werror +#KBUILD_CFLAGS-$(CONFIG_WERROR) += -Werror KBUILD_CFLAGS-$(CONFIG_CC_NO_ARRAY_BOUNDS) += -Wno-array-bounds KBUILD_RUSTFLAGS-$(CONFIG_WERROR) += -Dwarnings diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore index 8c759326baf44..7ced212024ca0 100644 --- a/arch/arm/boot/.gitignore +++ b/arch/arm/boot/.gitignore @@ -4,3 +4,5 @@ zImage xipImage bootpImage uImage +*.dtb* +*.scr \ No newline at end of file diff --git a/arch/arm64/boot/.gitignore b/arch/arm64/boot/.gitignore index af5dc61f8b438..1f74929d6f8ec 100644 --- a/arch/arm64/boot/.gitignore +++ b/arch/arm64/boot/.gitignore @@ -2,3 +2,5 @@ Image Image.gz vmlinuz* +*.dtb* +*.scr \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 03a83d59618f5..3d012fba5288e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -95,6 +95,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-edp-avb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo1-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10-linux.dtb @@ -106,6 +107,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb3-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-hinlink-h28k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-hinlink-ht2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-mangopi-m28k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-dictpen-test3-v20.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb @@ -149,6 +154,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-pdm-mic-array.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb5-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero3.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero3-ap6212.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-firefly-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w103.dtb @@ -156,11 +167,13 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-taishanpi-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-dual-channel-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-single-channel-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-armsom-sige3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb-rk628-hdmi2bt1120-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dtb @@ -192,18 +205,41 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-hnas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mixtile-edge2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev01.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev02.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev03.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev04.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev05.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi5-rev07.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ok3568c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-pcie-ep-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-yy3568.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-bananapi-m7.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blade3-v101-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v12-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v12-maizhuo-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v14-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-minipc-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-minipc-mizhuo-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-csi-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-dvp-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dtb @@ -236,6 +272,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.d dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-cm5-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-cm5-rpi-cm4-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-blueberry-edge-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-ebook-color-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-ebook-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-ebook-x3-v10.dtb @@ -313,6 +353,17 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v11-linux-ipc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-rk628-hdmi2csi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-aim7-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-cyber-aib.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-fxblox-rk1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-hinlink-h88k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-cm3588-nas.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-ipc-4x-linux.dtb @@ -323,6 +374,13 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo3-v10-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-pcie-ep-demo-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-pcie-ep-demo-v11-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-max.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-radxa-rock-5b+.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mixtile-core3588e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v10.dtb @@ -343,6 +401,28 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb8-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-youyeetoo-r1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-9tripod-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-lubancat-4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-m6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5-pro.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-rpi-cm4-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-e52c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-nx5-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-retro-lite-cm5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-retroled-cm5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-luckfox-core3566.dtb + +subdir-y := $(dts-dirs) overlay diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile new file mode 100644 index 0000000000000..153c781a84881 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: GPL-2.0 +dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + armsom-cm5-io-camera-imx219-cs0.dtbo \ + armsom-cm5-io-camera-ov13850-cs1.dtbo \ + armsom-cm5-io-display-10hd.dtbo \ + armsom-cm5-rpi-cm4-io-camera0.dtbo \ + armsom-cm5-rpi-cm4-io-camera1.dtbo \ + armsom-cm5-rpi-cm4-io-display.dtbo \ + armsom-sige5-camera-ov13850-cs0.dtbo \ + armsom-sige5-camera-ov13850-cs1.dtbo \ + armsom-sige5-display-10hd.dtbo \ + armsom-sige7-camera-imx415-4k.dtbo \ + armsom-sige7-camera-ov13850-csi0.dtbo \ + armsom-sige7-camera-ov13850-csi1.dtbo \ + armsom-sige7-display-10hd.dtbo \ + armsom-w3-camera-imx419-csi.dtbo \ + armsom-w3-camera-ov13850-csi.dtbo \ + armsom-w3-display-10hd.dtbo \ + orangepi-5-lcd1.dtbo \ + orangepi-5-lcd2.dtbo \ + orangepi-5-sata.dtbo \ + orangepi-5-ap6275p.dtbo \ + orangepi-5-disable-led.dtbo \ + orangepi-5-plus-disable-leds.dtbo \ + orangepi-5-plus-hdmi2-8k.dtbo \ + orangepi-5-plus-lcd.dtbo \ + orangepi-5-plus-ov13850.dtbo \ + orangepi-5-plus-ov13855.dtbo \ + orangepi-5-plus-sata2.dtbo \ + orangepi-5-pro-lcd.dtbo \ + orangepi-5-pro-sfc.dtbo \ + orangepi-5-pro-cam1.dtbo \ + orangepi-5-pro-cam2.dtbo \ + orangepi-5-pro-disable-leds.dtbo \ + rock-3a-sata.dtbo \ + rock-5a-hdmi-8k.dtbo \ + rock-5a-i2c5-rtc-hym8563.dtbo \ + rock-5a-radxa-camera-4k.dtbo \ + rock-5a-radxa-display-10hd.dtbo \ + rock-5a-radxa-display-10fhd.dtbo \ + rock-5a-radxa-display-8hd.dtbo \ + rock-5a-spi-nor-flash.dtbo \ + rock-5a-usb-otg.dtbo \ + rock-5a-rpi-camera-v2.dtbo \ + rock-5a-sata.dtbo \ + rock-5b-hdmi1-8k.dtbo \ + rock-5b-hdmi2-8k.dtbo \ + rock-5b-pd-max-voltage-12v.dtbo \ + rock-5b-radxa-display-10hd.dtbo \ + rock-5b-radxa-display-8hd.dtbo \ + rock-5b-radxa-display-10fhd.dtbo \ + rock-5b-rpi-camera-v2.dtbo \ + rock-5b-radxa-camera-4k.dtbo \ + rock-5b-sata.dtbo \ + rock-5-itx-radxa-camera-4k-on-cam0.dtbo \ + rock-5-itx-radxa-camera-4k-on-cam1.dtbo \ + rock-5-itx-radxa-display-8hd-on-lcd0.dtbo \ + rock-5-itx-radxa-display-8hd-on-lcd1.dtbo \ + rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dtbo \ + radxa-cm5-io-radxa-camera-4k.dtbo \ + radxa-cm5-io-raspi-7inch-touchscreen.dtbo \ + radxa-cm5-io-radxa-display-10hd.dtbo \ + radxa-cm5-io-radxa-display-8hd.dtbo \ + radxa-cm5-io-rpi-camera-v2.dtbo \ + radxa-cm5-io-sata.dtbo \ + radxa-nx5-io-rpi-camera-v2-cam0.dtbo \ + radxa-nx5-io-rpi-camera-v2-cam1.dtbo \ + rk3588s-roc-pc-sata0.dtbo \ + turing-rk1-sata2.dtbo \ + mixtile-blade3-sata2.dtbo \ + radxa-zero3-rpi-camera-v2.dtbo \ + radxa-zero3-rpi-camera-v1.3.dtbo \ + radxa-zero3-external-antenna.dtbo \ + radxa-zero3-disabled-ethernet.dtbo \ + radxa-zero3-disabled-wireless.dtbo \ + yy3568-camera.dtbo \ + yy3568-display-dsi0.dtbo \ + yy3568-display-dsi1.dtbo \ + yy3568-display-edp.dtbo \ + yy3568-sata2.dtbo \ + khadas-edge2-display-dsi0.dtbo \ + khadas-edge2-display-dsi1.dtbo \ + khadas-edge2-cam1.dtbo \ + khadas-edge2-cam2.dtbo \ + khadas-edge2-cam3.dtbo \ + nanopi-m6-display-dsi0-yx35.dtbo \ + nanopi-m6-display-dsi1-yx35.dtbo \ + rockchip-rk3588-opp-oc-24ghz.dtbo \ + rockchip-rk3588-panthor-gpu.dtbo \ + rk3566-roc-pc-sata2.dtbo \ + rk3576-can1-m1.dtbo \ + rk3576-i2c0-m1.dtbo \ + rk3576-i2c1-m0.dtbo \ + rk3576-i2c2-m0.dtbo \ + rk3576-i2c3-m0.dtbo \ + rk3576-i2c4-m3.dtbo \ + rk3576-i2c5-m3.dtbo \ + rk3576-i2c6-m0.dtbo \ + rk3576-i2c7-m1.dtbo \ + rk3576-i2c8-m2.dtbo \ + rk3576-pwm1-ch0-m3.dtbo \ + rk3576-pwm2-ch6-m2.dtbo \ + rk3576-pwm2-ch7-m2.dtbo \ + rk3576-spi4-m0-cs1-spidev.dtbo \ + rk3576-uart2-m2.dtbo \ + rk3576-uart6-m3.dtbo \ + rk3576-uart7-m0.dtbo \ + rk3576-uart10-m2.dtbo \ + rk3588-can0-m0.dtbo \ + rk3588-can1-m0.dtbo \ + rk3588-can1-m1.dtbo \ + rk3588-can2-m1.dtbo \ + rk3588-dwc3-host.dtbo \ + rk3588-dwc3-peripheral.dtbo \ + rk3588-i2c0-m1.dtbo \ + rk3588-i2c1-m0.dtbo \ + rk3588-i2c1-m2.dtbo \ + rk3588-i2c1-m4.dtbo \ + rk3588-i2c2-m0.dtbo \ + rk3588-i2c2-m4.dtbo \ + rk3588-i2c3-m0.dtbo \ + rk3588-i2c3-m1.dtbo \ + rk3588-i2c4-m3.dtbo \ + rk3588-i2c5-m3.dtbo \ + rk3588-i2c6-m0.dtbo \ + rk3588-i2c6-m3.dtbo \ + rk3588-i2c6-m4.dtbo \ + rk3588-i2c7-m3.dtbo \ + rk3588-i2c8-m2.dtbo \ + rk3588-i2c8-m4.dtbo \ + rk3588-ov13850-c1.dtbo \ + rk3588-ov13850-c2.dtbo \ + rk3588-ov13850-c3.dtbo \ + rk3588-ov13855-c1.dtbo \ + rk3588-ov13855-c2.dtbo \ + rk3588-ov13855-c3.dtbo \ + rk3588-pwm0-m0.dtbo \ + rk3588-pwm0-m1.dtbo \ + rk3588-pwm0-m2.dtbo \ + rk3588-pwm10-m0.dtbo \ + rk3588-pwm11-m0.dtbo \ + rk3588-pwm11-m1.dtbo \ + rk3588-pwm12-m0.dtbo \ + rk3588-pwm13-m0.dtbo \ + rk3588-pwm13-m2.dtbo \ + rk3588-pwm14-m0.dtbo \ + rk3588-pwm14-m1.dtbo \ + rk3588-pwm14-m2.dtbo \ + rk3588-pwm15-m0.dtbo \ + rk3588-pwm15-m1.dtbo \ + rk3588-pwm15-m2.dtbo \ + rk3588-pwm15-m3.dtbo \ + rk3588-pwm1-m0.dtbo \ + rk3588-pwm1-m1.dtbo \ + rk3588-pwm1-m2.dtbo \ + rk3588-pwm2-m1.dtbo \ + rk3588-pwm3-m0.dtbo \ + rk3588-pwm3-m1.dtbo \ + rk3588-pwm3-m2.dtbo \ + rk3588-pwm3-m3.dtbo \ + rk3588-pwm5-m2.dtbo \ + rk3588-pwm6-m0.dtbo \ + rk3588-pwm6-m2.dtbo \ + rk3588-pwm7-m0.dtbo \ + rk3588-pwm7-m3.dtbo \ + rk3588-pwm8-m0.dtbo \ + rk3588-spi0-m1-cs0-spidev.dtbo \ + rk3588-spi0-m1-cs1-spidev.dtbo \ + rk3588-spi0-m2-cs0-cs1-spidev.dtbo \ + rk3588-spi0-m2-cs0-spidev.dtbo \ + rk3588-spi0-m2-cs1-spidev.dtbo \ + rk3588-spi1-m1-cs0-spidev.dtbo \ + rk3588-spi1-m1-cs1-mcp2515-8mhz.dtbo \ + rk3588-spi1-m1-cs1-spidev.dtbo \ + rk3588-spi4-m0-cs1-spidev.dtbo \ + rk3588-spi4-m1-cs0-cs1-spidev.dtbo \ + rk3588-spi4-m1-cs0-spidev.dtbo \ + rk3588-spi4-m1-cs1-spidev.dtbo \ + rk3588-spi4-m2-cs0-spidev.dtbo \ + rk3588-uart0-m2.dtbo \ + rk3588-uart1-m1.dtbo \ + rk3588-uart2-m0.dtbo \ + rk3588-uart2-m2.dtbo \ + rk3588-uart3-m0.dtbo \ + rk3588-uart3-m1.dtbo \ + rk3588-uart4-m0.dtbo \ + rk3588-uart4-m2.dtbo \ + rk3588-uart6-m1.dtbo \ + rk3588-uart6-m1-full.dtbo \ + rk3588-uart7-m1.dtbo \ + rk3588-uart7-m1-full.dtbo \ + rk3588-uart7-m2.dtbo \ + rk3588-uart8-m0.dtbo \ + rk3588-uart8-m0-full.dtbo \ + rk3588-uart8-m1.dtbo \ + rk3588-w1-gpio3-b3.dtbo \ + rk3588-w1-gpio4-b1.dtbo \ + rk3588-hdmirx.dtbo + + +dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \ + README.rockchip-overlays + +targets += $(dtbo-y) $(dtbotxt-y) + +always-y := $(dtbo-y) $(dtbotxt-y) +clean-files := *.dtbo + diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays new file mode 100644 index 0000000000000..491c78cb7addf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays @@ -0,0 +1 @@ +## Introduction \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-imx219-cs0.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-imx219-cs0.dts new file mode 100644 index 0000000000000..75cae58d6c7ad --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-imx219-cs0.dts @@ -0,0 +1,223 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + imx219: imx219@10 { + status = "okay"; + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cam_clk1m1_clk1>; + VANA-supply = <&vcc_3v3_s0>; /* 2.8v */ + VDIG-supply = <&vcc_3v3_s0>; /* 1.8v */ + VDDL-supply = <&vcc_3v3_s0>; /* 1.2v */ + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + imx219_out: endpoint { + remote-endpoint = <&mipidphy3_in_ucam3>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&csi2_dphy4>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx219_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&mipi3_csi2>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds3>; + __overlay__ { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mipi_lvds3_sditf>; + __overlay__ { + status = "okay"; + + port { + mipi_lvds3_sditf: endpoint { + remote-endpoint = <&isp_vir0_in1>; + }; + }; + }; + }; + + fragment@9 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&rkisp_vir0>; + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds3_sditf>; + }; + }; + }; + }; + + fragment@13 { + target = <&pinctrl>; + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-ov13850-cs1.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-ov13850-cs1.dts new file mode 100644 index 0000000000000..0bc0b04d42e04 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-camera-ov13850-cs1.dts @@ -0,0 +1,220 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + camera1_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera1_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam1_pwdn_gpio>; + }; + }; + }; + + fragment@1 { + target = <&i2c5>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + ov13850: ov13850@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk1m0_clk1>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&csi2_dphy0>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&mipi1_csi2>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds1>; + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi_csi2_output>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mipi_lvds1_sditf>; + __overlay__ { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp_vir0_in0>; + }; + }; + }; + }; + + fragment@9 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&rkisp_vir1>; + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; + }; + }; + + fragment@13 { + target = <&pinctrl>; + __overlay__ { + camera { + cam1_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-display-10hd.dts new file mode 100644 index 0000000000000..aff568b9a89df --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-io-display-10hd.dts @@ -0,0 +1,318 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1_6ch_1 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&pwm1_6ch_1>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm1m0_ch1>; + }; + }; + + fragment@2 { + target = <&dsi>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc_lcd_mipi1>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + backlight = <&dsi1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 B0 01 + 15 00 02 C0 26 + 15 00 02 C1 10 + 15 00 02 C2 0E + 15 00 02 C3 00 + 15 00 02 C4 00 + 15 00 02 C5 23 + 15 00 02 C6 11 + 15 00 02 C7 22 + 15 00 02 C8 20 + 15 00 02 C9 1E + 15 00 02 CA 1C + 15 00 02 CB 0C + 15 00 02 CC 0A + 15 00 02 CD 08 + 15 00 02 CE 06 + 15 00 02 CF 18 + 15 00 02 D0 02 + 15 00 02 D1 00 + 15 00 02 D2 00 + 15 00 02 D3 00 + 15 00 02 D4 26 + 15 00 02 D5 0F + 15 00 02 D6 0D + 15 00 02 D7 00 + 15 00 02 D8 00 + 15 00 02 D9 23 + 15 00 02 DA 11 + 15 00 02 DB 21 + 15 00 02 DC 1F + 15 00 02 DD 1D + 15 00 02 DE 1B + 15 00 02 DF 0B + 15 00 02 E0 09 + 15 00 02 E1 07 + 15 00 02 E2 05 + 15 00 02 E3 17 + 15 00 02 E4 01 + 15 00 02 E5 00 + 15 00 02 E6 00 + 15 00 02 E7 00 + 15 00 02 B0 03 + 15 00 02 BE 04 + 15 00 02 B9 40 + 15 00 02 CC 88 + 15 00 02 C8 0C + 15 00 02 C9 07 + 15 00 02 CD 01 + 15 00 02 CA 40 + 15 00 02 CE 1A + 15 00 02 CF 60 + 15 00 02 D2 08 + 15 00 02 D3 08 + 15 00 02 DB 01 + 15 00 02 D9 06 + 15 00 02 D4 00 + 15 00 02 D5 01 + 15 00 02 D6 04 + 15 00 02 D7 03 + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 B0 06 + 15 00 02 C0 A5 + 15 00 02 D5 1C + 15 00 02 C0 00 + 15 00 02 B0 00 + 15 00 02 BD 30 + + 15 00 02 F9 5C + 15 00 02 C2 14 + 15 00 02 C4 14 + 15 00 02 BF 15 + 15 00 02 C0 0C + + + 15 00 02 B0 00 + 15 00 02 B1 79 + 15 00 02 BA 8F + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 32 01 28 + 05 78 01 10 + ]; + disp_timings0: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hfront-porch = <80>; + hsync-len = <1>; + hback-porch = <60>; + vfront-porch = <35>; + vsync-len = <1>; + vback-porch = <25>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipidcphy0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&dsi_in_vp1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&vp1>; + __overlay__ { + assigned-clocks = <&cru DCLK_VP1_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; + }; + }; + + fragment@7 { + target = <&i2c0>; + __overlay__ { + pinctrl-0 = <&i2c0m1_xfer>; + status = "okay"; + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <9271>; + tp-supply = <&vcc_lcd_mipi1>; + configfile-num = <1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-camera0.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-camera0.dts new file mode 100644 index 0000000000000..d055f096ee047 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-camera0.dts @@ -0,0 +1,261 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m_0: external-camera-clock-24m-0 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m_0"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c4m3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m_0>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy1_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + + + fragment@3 { + target = <&csi2_dphy4>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi3_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in3>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds3>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi_in3: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds3_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi3_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir2>; + }; + }; + }; + }; + + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_vir2>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_lvds_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&rkvpss>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@13 { + target = <&rkvpss_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@14 { + target = <&rkvpss_vir2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@15 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-camera1.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-camera1.dts new file mode 100644 index 0000000000000..dca24749d2fed --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-camera1.dts @@ -0,0 +1,261 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m_0: external-camera-clock-24m-0 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m_0"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c5m3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219_1: camera-imx219-1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m_0>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out1: endpoint { + remote-endpoint = <&mipidphy1_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + + + fragment@3 { + target = <&csi2_dphy1>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy1_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi1_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds1>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds1_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; + }; + }; + + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&rkvpss>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@13 { + target = <&rkvpss_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@14 { + target = <&rkvpss_vir0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@15 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-display.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-display.dts new file mode 100644 index 0000000000000..24fc5a1f93a7c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-cm5-rpi-cm4-io-display.dts @@ -0,0 +1,100 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&dsi>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + rockchip,lane-rate = <605>; + dsi_panel: dsi-panel@0 { + compatible = "raspits,tc358762"; + reg = <0x0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + + }; + }; + + fragment@1 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c5m3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + raspits_ft5426: raspits_ft5426@38 { + compatible = "raspits_ft5426"; + reg = <0x38>; + }; + + chipone_icn8952: chipone_icn8952@30 { + compatible = "chipone_icn8505"; + reg = <0x30>; + }; + + rockpi_mcu: rockpi-mcu@45 { + compatible = "rockpi_mcu"; + reg = <0x45>; + }; + + }; + }; + + fragment@2 { + target = <&mipidcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&route_dsi>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@4 { + target = <&dsi_in_vp1>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs0.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs0.dts new file mode 100644 index 0000000000000..397aeccef60f6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs0.dts @@ -0,0 +1,188 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c5>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + ov13850: ov13850@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk1m0_clk1>; + pwdn-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi1_csi2>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds1>; + __overlay__ { + status = "okay"; + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds1_sditf>; + __overlay__ { + status = "okay"; + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp_vir0_in0>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_vir1>; + __overlay__ { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs1.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs1.dts new file mode 100644 index 0000000000000..2d3720643791e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-camera-ov13850-cs1.dts @@ -0,0 +1,188 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c4>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + ov13850_1: ov13850_1@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2m0_clk2>; + pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out1: endpoint { + remote-endpoint = <&mipidphy3_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy1_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy3>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi3_csi2>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in3>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds3>; + __overlay__ { + status = "okay"; + port { + cif_mipi_in3: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds3_sditf>; + __overlay__ { + status = "okay"; + port { + mipi_lvds3_sditf: endpoint { + remote-endpoint = <&isp_vir0_in1>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp_vir0>; + __overlay__ { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds3_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-display-10hd.dts new file mode 100644 index 0000000000000..24be21e542a12 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige5-display-10hd.dts @@ -0,0 +1,333 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_bl_n: vcc3v3-bl-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bl_n"; + regulator-boot-on; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1_6ch_1 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&pwm1_6ch_1>; + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm1m0_ch1>; + }; + }; + + fragment@2 { + target = <&dsi>; + __overlay__ { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc_lcd_mipi1>; + reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + backlight = <&dsi1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 B0 01 + 15 00 02 C0 26 + 15 00 02 C1 10 + 15 00 02 C2 0E + 15 00 02 C3 00 + 15 00 02 C4 00 + 15 00 02 C5 23 + 15 00 02 C6 11 + 15 00 02 C7 22 + 15 00 02 C8 20 + 15 00 02 C9 1E + 15 00 02 CA 1C + 15 00 02 CB 0C + 15 00 02 CC 0A + 15 00 02 CD 08 + 15 00 02 CE 06 + 15 00 02 CF 18 + 15 00 02 D0 02 + 15 00 02 D1 00 + 15 00 02 D2 00 + 15 00 02 D3 00 + 15 00 02 D4 26 + 15 00 02 D5 0F + 15 00 02 D6 0D + 15 00 02 D7 00 + 15 00 02 D8 00 + 15 00 02 D9 23 + 15 00 02 DA 11 + 15 00 02 DB 21 + 15 00 02 DC 1F + 15 00 02 DD 1D + 15 00 02 DE 1B + 15 00 02 DF 0B + 15 00 02 E0 09 + 15 00 02 E1 07 + 15 00 02 E2 05 + 15 00 02 E3 17 + 15 00 02 E4 01 + 15 00 02 E5 00 + 15 00 02 E6 00 + 15 00 02 E7 00 + 15 00 02 B0 03 + 15 00 02 BE 04 + 15 00 02 B9 40 + 15 00 02 CC 88 + 15 00 02 C8 0C + 15 00 02 C9 07 + 15 00 02 CD 01 + 15 00 02 CA 40 + 15 00 02 CE 1A + 15 00 02 CF 60 + 15 00 02 D2 08 + 15 00 02 D3 08 + 15 00 02 DB 01 + 15 00 02 D9 06 + 15 00 02 D4 00 + 15 00 02 D5 01 + 15 00 02 D6 04 + 15 00 02 D7 03 + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 B0 06 + 15 00 02 C0 A5 + 15 00 02 D5 1C + 15 00 02 C0 00 + 15 00 02 B0 00 + 15 00 02 BD 30 + + 15 00 02 F9 5C + 15 00 02 C2 14 + 15 00 02 C4 14 + 15 00 02 BF 15 + 15 00 02 C0 0C + + + 15 00 02 B0 00 + 15 00 02 B1 79 + 15 00 02 BA 8F + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 32 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hfront-porch = <80>; + hsync-len = <1>; + hback-porch = <60>; + vfront-porch = <35>; + vsync-len = <1>; + vback-porch = <25>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipidcphy0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&dsi_in_vp1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&vp1>; + __overlay__ { + assigned-clocks = <&cru DCLK_VP1_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; + }; + }; + + fragment@7 { + target = <&i2c0>; + __overlay__ { + pinctrl-0 = <&i2c0m1_xfer>; + status = "okay"; + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD1 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <89>; + tp-supply = <&vcc_lcd_mipi1>; + + configfile-num = <1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = + <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-imx415-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-imx415-4k.dts new file mode 100755 index 0000000000000..a99cff09cc237 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-imx415-4k.dts @@ -0,0 +1,379 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415p0: imx415p0@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + imx415p1: imx415p1@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out3: endpoint { + remote-endpoint = <&mipidphy3_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy1_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + + fragment@4 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&csi2_dphy3>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out3>; + data-lanes = <1 2 3 4>; + }; + + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; + }; + }; + + fragment@6 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@7 { + target = <&mipi4_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@10 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@11 { + target = <&rkcif_mipi_lvds4>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; + }; + }; + + fragment@12 { + target = <&rkcif_mipi_lvds4_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; + + }; + }; + + fragment@13 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@14 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@15 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@16 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + + fragment@17 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@18 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@19 { + target = <&rkisp1_vir1>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; + }; + }; + +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi0.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi0.dts new file mode 100755 index 0000000000000..d9c08a4763917 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi0.dts @@ -0,0 +1,203 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov13850: ov13850@10{ + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2 3 4>; + }; + + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir2>; + }; + }; + }; + }; + + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir2>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi1.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi1.dts new file mode 100755 index 0000000000000..c0b8983138a8a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-camera-ov13850-csi1.dts @@ -0,0 +1,205 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + + fragment@0 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + ov13850_1: ov13850_1@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out1: endpoint { + remote-endpoint = <&mipidphy3_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy1_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy3>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out1>; + data-lanes = <1 2 3 4>; + }; + + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi4_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds4>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds4_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; + + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp1_vir1>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; + }; + }; + +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-display-10hd.dts new file mode 100755 index 0000000000000..c0cebd7c01fc0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-sige7-display-10hd.dts @@ -0,0 +1,350 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_lcd_n: vcc5v0-lcd0-n { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_lcd_n"; + gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc_lcd_mipi1>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>; + backlight = <&dsi1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 B0 01 + 15 00 02 C0 26 + 15 00 02 C1 10 + 15 00 02 C2 0E + 15 00 02 C3 00 + 15 00 02 C4 00 + 15 00 02 C5 23 + 15 00 02 C6 11 + 15 00 02 C7 22 + 15 00 02 C8 20 + 15 00 02 C9 1E + 15 00 02 CA 1C + 15 00 02 CB 0C + 15 00 02 CC 0A + 15 00 02 CD 08 + 15 00 02 CE 06 + 15 00 02 CF 18 + 15 00 02 D0 02 + 15 00 02 D1 00 + 15 00 02 D2 00 + 15 00 02 D3 00 + 15 00 02 D4 26 + 15 00 02 D5 0F + 15 00 02 D6 0D + 15 00 02 D7 00 + 15 00 02 D8 00 + 15 00 02 D9 23 + 15 00 02 DA 11 + 15 00 02 DB 21 + 15 00 02 DC 1F + 15 00 02 DD 1D + 15 00 02 DE 1B + 15 00 02 DF 0B + 15 00 02 E0 09 + 15 00 02 E1 07 + 15 00 02 E2 05 + 15 00 02 E3 17 + 15 00 02 E4 01 + 15 00 02 E5 00 + 15 00 02 E6 00 + 15 00 02 E7 00 + 15 00 02 B0 03 + 15 00 02 BE 04 + 15 00 02 B9 40 + 15 00 02 CC 88 + 15 00 02 C8 0C + 15 00 02 C9 07 + 15 00 02 CD 01 + 15 00 02 CA 40 + 15 00 02 CE 1A + 15 00 02 CF 60 + 15 00 02 D2 08 + 15 00 02 D3 08 + 15 00 02 DB 01 + 15 00 02 D9 06 + 15 00 02 D4 00 + 15 00 02 D5 01 + 15 00 02 D6 04 + 15 00 02 D7 03 + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 B0 06 + 15 00 02 C0 A5 + 15 00 02 D5 1C + 15 00 02 C0 00 + 15 00 02 B0 00 + 15 00 02 BD 30 + + 15 00 02 F9 5C + 15 00 02 C2 14 + 15 00 02 C4 14 + 15 00 02 BF 15 + 15 00 02 C0 0C + + + 15 00 02 B0 00 + 15 00 02 B1 79 + 15 00 02 BA 8F + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 32 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hfront-porch = <80>; + hsync-len = <1>; + hback-porch = <60>; + vfront-porch = <35>; + vsync-len = <1>; + vback-porch = <25>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + + }; + }; + + fragment@7 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <89>; + tp-supply = <&vcc_lcd_mipi1>; + + configfile-num = <1>; + }; + + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-camera-imx419-csi.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-camera-imx419-csi.dts new file mode 100644 index 0000000000000..4657e65d4ef35 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-camera-imx419-csi.dts @@ -0,0 +1,236 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3588"; + + fragment@0 { + target = <&camera_pwdn_gpio>; + __overlay__ { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + }; + + fragment@1 { + target = <&clk_cam_24m>; + __overlay__ { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; + }; + + fragment@2 { + target = <&i2c3>; + __overlay__ { + status = "okay"; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + camera_imx219: camera-imx219@10 { + status = "disabled"; + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&csi2_dphy0>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&mipi2_csi2>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds2>; + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp0_vir0>; + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&pinctrl>; + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-camera-ov13850-csi.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-camera-ov13850-csi.dts new file mode 100755 index 0000000000000..d9c08a4763917 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-camera-ov13850-csi.dts @@ -0,0 +1,203 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov13850: ov13850@10{ + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ZC-OV13850R2A-V1"; + rockchip,camera-module-lens-name = "Largan-50064B31"; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2 3 4>; + }; + + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir2>; + }; + }; + }; + }; + + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir2>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-display-10hd.dts new file mode 100644 index 0000000000000..c0cebd7c01fc0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/armsom-w3-display-10hd.dts @@ -0,0 +1,350 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_lcd_n: vcc5v0-lcd0-n { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_lcd_n"; + gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc_lcd_mipi1>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>; + backlight = <&dsi1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 B0 01 + 15 00 02 C0 26 + 15 00 02 C1 10 + 15 00 02 C2 0E + 15 00 02 C3 00 + 15 00 02 C4 00 + 15 00 02 C5 23 + 15 00 02 C6 11 + 15 00 02 C7 22 + 15 00 02 C8 20 + 15 00 02 C9 1E + 15 00 02 CA 1C + 15 00 02 CB 0C + 15 00 02 CC 0A + 15 00 02 CD 08 + 15 00 02 CE 06 + 15 00 02 CF 18 + 15 00 02 D0 02 + 15 00 02 D1 00 + 15 00 02 D2 00 + 15 00 02 D3 00 + 15 00 02 D4 26 + 15 00 02 D5 0F + 15 00 02 D6 0D + 15 00 02 D7 00 + 15 00 02 D8 00 + 15 00 02 D9 23 + 15 00 02 DA 11 + 15 00 02 DB 21 + 15 00 02 DC 1F + 15 00 02 DD 1D + 15 00 02 DE 1B + 15 00 02 DF 0B + 15 00 02 E0 09 + 15 00 02 E1 07 + 15 00 02 E2 05 + 15 00 02 E3 17 + 15 00 02 E4 01 + 15 00 02 E5 00 + 15 00 02 E6 00 + 15 00 02 E7 00 + 15 00 02 B0 03 + 15 00 02 BE 04 + 15 00 02 B9 40 + 15 00 02 CC 88 + 15 00 02 C8 0C + 15 00 02 C9 07 + 15 00 02 CD 01 + 15 00 02 CA 40 + 15 00 02 CE 1A + 15 00 02 CF 60 + 15 00 02 D2 08 + 15 00 02 D3 08 + 15 00 02 DB 01 + 15 00 02 D9 06 + 15 00 02 D4 00 + 15 00 02 D5 01 + 15 00 02 D6 04 + 15 00 02 D7 03 + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 B0 06 + 15 00 02 C0 A5 + 15 00 02 D5 1C + 15 00 02 C0 00 + 15 00 02 B0 00 + 15 00 02 BD 30 + + 15 00 02 F9 5C + 15 00 02 C2 14 + 15 00 02 C4 14 + 15 00 02 BF 15 + 15 00 02 C0 0C + + + 15 00 02 B0 00 + 15 00 02 B1 79 + 15 00 02 BA 8F + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 32 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hfront-porch = <80>; + hsync-len = <1>; + hback-porch = <60>; + vfront-porch = <35>; + vsync-len = <1>; + vback-porch = <25>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + + }; + }; + + fragment@7 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <89>; + tp-supply = <&vcc_lcd_mipi1>; + + configfile-num = <1>; + }; + + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam1.dts b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam1.dts new file mode 100644 index 0000000000000..9ccd832226f74 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam1.dts @@ -0,0 +1,233 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dcphy1>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_dcphy1: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415f_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi1_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds1>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds1_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; + }; + }; + + fragment@5 { + target = <&rkisp0_vir1>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; + }; + }; + + fragment@6 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9714f: dw9714f@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + pinctrl-names = "focusf_gpios"; + pinctrl-0 = <&focusf_gpio>; + focus-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <76>; + rockchip,vcm-step-mode = <0>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + }; + + imx415f: imx415f@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default", "camf_gpios"; + pinctrl-0 = <&mipim1_camera2_clk>, <&camf_gpio>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&dw9714f>; + port { + imx415f_out1: endpoint { + remote-endpoint = <&mipi_in_dcphy1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@7 { + target = <&pinctrl>; + + __overlay__ { + cam1 { + camf_gpio: camf-gpio { + rockchip,pins = + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + focusf_gpio: focusf-gpio { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam2.dts b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam2.dts new file mode 100644 index 0000000000000..d0f191d9898fe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam2.dts @@ -0,0 +1,234 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dcphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_dcphy0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415b_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi0_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@5 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; + }; + }; + + fragment@6 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + dw9714b: dw9714b@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + pinctrl-names = "focusb_gpios"; + pinctrl-0 = <&focusb_gpio>; + focus-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <76>; + rockchip,vcm-step-mode = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx415b: imx415b@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default", "camb_gpios"; + pinctrl-0 = <&mipim1_camera1_clk>, <&camb_gpio>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&dw9714b>; + port { + imx415b_out0: endpoint { + remote-endpoint = <&mipi_in_dcphy0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@7 { + target = <&pinctrl>; + + __overlay__ { + cam2 { + camb_gpio: camb-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + focusb_gpio: focusb-gpio { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam3.dts b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam3.dts new file mode 100644 index 0000000000000..e1c2c506be4fe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-cam3.dts @@ -0,0 +1,232 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415c_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; + }; + }; + + fragment@5 { + target = <&rkisp1_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + + fragment@6 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + dw9714c: dw9714c@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + pinctrl-names = "focusc_gpios"; + pinctrl-0 = <&focusc_gpio>; + focus-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <76>; + rockchip,vcm-step-mode = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default", "camc_gpios"; + pinctrl-0 = <&mipim1_camera3_clk>, <&camc_gpio>; + power-domains = <&power RK3588_PD_VI>; + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&dw9714c>; + port { + imx415c_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@7 { + target = <&pinctrl>; + + __overlay__ { + cam3 { + camc_gpio: camc-gpio { + rockchip,pins = + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + focusc_gpio: focusc-gpio { + rockchip,pins = + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-display-dsi0.dts b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-display-dsi0.dts new file mode 100644 index 0000000000000..6750023306d93 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-display-dsi0.dts @@ -0,0 +1,810 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_mipi0: backlight-mipi0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm12 0 25000 0>; + power-supply = <&vcc3v3_lcd1_en>; + status = "okay"; + }; + + vcc3v3_lcd1_en: vcc3v3-lcd1-en { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + status = "okay"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + fragment@1 { + target = <&pwm12>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm12m1_pins>; + }; + }; + + fragment@2 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@4 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&route_dsi0>; + + __overlay__ { + connect = <&vp3_out_dsi0>; + status = "okay"; + }; + }; + + fragment@6 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + reset-delay-ms = <20>; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight_mipi0>; + power-supply = <&vcc3v3_lcd1_en>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 FF 05 + 15 00 02 FB 01 + 15 64 02 C5 01 + 15 00 02 FF EE + 15 00 02 FB 01 + 15 00 02 1F 45 + 15 00 02 24 4F + 15 00 02 38 C8 + 15 00 02 39 27 + 15 00 02 1E 77 + 15 00 02 1D 0F + 15 00 02 7E 71 + 15 00 02 7C 03 + 15 00 02 FF 00 + 15 00 02 FB 01 + 15 00 02 35 01 + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 00 01 + 15 00 02 01 55 + 15 00 02 02 40 + 15 00 02 05 40 + 15 00 02 06 4A + 15 00 02 07 24 + 15 00 02 08 0C + 15 00 02 0B 7D + 15 00 02 0C 7D + 15 00 02 0E B0 + 15 00 02 0F AE + 15 00 02 11 10 + 15 00 02 12 10 + 15 00 02 13 03 + 15 00 02 14 4A + 15 00 02 15 12 + 15 00 02 16 12 + 15 00 02 18 00 + 15 00 02 19 77 + 15 00 02 1A 55 + 15 00 02 1B 13 + 15 00 02 1C 00 + 15 00 02 1D 00 + 15 00 02 1E 13 + 15 00 02 1F 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 00 + 15 00 02 35 00 + 15 00 02 66 00 + 15 00 02 58 82 + 15 00 02 59 02 + 15 00 02 5A 02 + 15 00 02 5B 02 + 15 00 02 5C 82 + 15 00 02 5D 82 + 15 00 02 5E 02 + 15 00 02 5F 02 + 15 00 02 72 31 + 15 00 02 FF 05 + 15 00 02 FB 01 + 15 00 02 00 01 + 15 00 02 01 0B + 15 00 02 02 0C + 15 00 02 03 09 + 15 00 02 04 0A + 15 00 02 05 00 + 15 00 02 06 0F + 15 00 02 07 10 + 15 00 02 08 00 + 15 00 02 09 00 + 15 00 02 0A 00 + 15 00 02 0B 00 + 15 00 02 0C 00 + 15 00 02 0D 13 + 15 00 02 0E 15 + 15 00 02 0F 17 + 15 00 02 10 01 + 15 00 02 11 0B + 15 00 02 12 0C + 15 00 02 13 09 + 15 00 02 14 0A + 15 00 02 15 00 + 15 00 02 16 0F + 15 00 02 17 10 + 15 00 02 18 00 + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B 00 + 15 00 02 1C 00 + 15 00 02 1D 13 + 15 00 02 1E 15 + 15 00 02 1F 17 + 15 00 02 20 00 + 15 00 02 21 03 + 15 00 02 22 01 + 15 00 02 23 40 + 15 00 02 24 40 + 15 00 02 25 ED + 15 00 02 29 58 + 15 00 02 2A 12 + 15 00 02 2B 01 + 15 00 02 4B 06 + 15 00 02 4C 11 + 15 00 02 4D 20 + 15 00 02 4E 02 + 15 00 02 4F 02 + 15 00 02 50 20 + 15 00 02 51 61 + 15 00 02 52 01 + 15 00 02 53 63 + 15 00 02 54 77 + 15 00 02 55 ED + 15 00 02 5B 00 + 15 00 02 5C 00 + 15 00 02 5D 00 + 15 00 02 5E 00 + 15 00 02 5F 15 + 15 00 02 60 75 + 15 00 02 61 00 + 15 00 02 62 00 + 15 00 02 63 00 + 15 00 02 64 00 + 15 00 02 65 00 + 15 00 02 66 00 + 15 00 02 67 00 + 15 00 02 68 04 + 15 00 02 69 00 + 15 00 02 6A 00 + 15 00 02 6C 40 + 15 00 02 75 01 + 15 00 02 76 01 + 15 00 02 7A 80 + 15 00 02 7B A3 + 15 00 02 7C D8 + 15 00 02 7D 60 + 15 00 02 7F 15 + 15 00 02 80 81 + 15 00 02 83 05 + 15 00 02 93 08 + 15 00 02 94 10 + 15 00 02 8A 00 + 15 00 02 9B 0F + 15 00 02 EA FF + 15 00 02 EC 00 + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 75 00 + 15 00 02 76 DF + 15 00 02 77 00 + 15 00 02 78 E4 + 15 00 02 79 00 + 15 00 02 7A ED + 15 00 02 7B 00 + 15 00 02 7C F6 + 15 00 02 7D 00 + 15 00 02 7E FF + 15 00 02 7F 01 + 15 00 02 80 07 + 15 00 02 81 01 + 15 00 02 82 10 + 15 00 02 83 01 + 15 00 02 84 18 + 15 00 02 85 01 + 15 00 02 86 20 + 15 00 02 87 01 + 15 00 02 88 3D + 15 00 02 89 01 + 15 00 02 8A 56 + 15 00 02 8B 01 + 15 00 02 8C 84 + 15 00 02 8D 01 + 15 00 02 8E AB + 15 00 02 8F 01 + 15 00 02 90 EC + 15 00 02 91 02 + 15 00 02 92 22 + 15 00 02 93 02 + 15 00 02 94 23 + 15 00 02 95 02 + 15 00 02 96 55 + 15 00 02 97 02 + 15 00 02 98 8B + 15 00 02 99 02 + 15 00 02 9A AF + 15 00 02 9B 02 + 15 00 02 9C DF + 15 00 02 9D 03 + 15 00 02 9E 01 + 15 00 02 9F 03 + 15 00 02 A0 2C + 15 00 02 A2 03 + 15 00 02 A3 39 + 15 00 02 A4 03 + 15 00 02 A5 47 + 15 00 02 A6 03 + 15 00 02 A7 56 + 15 00 02 A9 03 + 15 00 02 AA 66 + 15 00 02 AB 03 + 15 00 02 AC 76 + 15 00 02 AD 03 + 15 00 02 AE 85 + 15 00 02 AF 03 + 15 00 02 B0 90 + 15 00 02 B1 03 + 15 00 02 B2 CB + 15 00 02 B3 00 + 15 00 02 B4 DF + 15 00 02 B5 00 + 15 00 02 B6 E4 + 15 00 02 B7 00 + 15 00 02 B8 ED + 15 00 02 B9 00 + 15 00 02 BA F6 + 15 00 02 BB 00 + 15 00 02 BC FF + 15 00 02 BD 01 + 15 00 02 BE 07 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00 + 15 00 02 FA EA + 15 00 02 FF 02 + 15 00 02 FB 01 + 15 00 02 00 00 + 15 00 02 01 F4 + 15 00 02 02 00 + 15 00 02 03 EF + 15 00 02 04 01 + 15 00 02 05 07 + 15 00 02 06 01 + 15 00 02 07 28 + 15 00 02 08 01 + 15 00 02 09 44 + 15 00 02 0A 01 + 15 00 02 0B 76 + 15 00 02 0C 01 + 15 00 02 0D A0 + 15 00 02 0E 01 + 15 00 02 0F E7 + 15 00 02 10 02 + 15 00 02 11 1F + 15 00 02 12 02 + 15 00 02 13 22 + 15 00 02 14 02 + 15 00 02 15 54 + 15 00 02 16 02 + 15 00 02 17 8B + 15 00 02 18 02 + 15 00 02 19 AF + 15 00 02 1A 02 + 15 00 02 1B E0 + 15 00 02 1C 03 + 15 00 02 1D 01 + 15 00 02 1E 03 + 15 00 02 1F 2D + 15 00 02 20 03 + 15 00 02 21 39 + 15 00 02 22 03 + 15 00 02 23 47 + 15 00 02 24 03 + 15 00 02 25 57 + 15 00 02 26 03 + 15 00 02 27 65 + 15 00 02 28 03 + 15 00 02 29 77 + 15 00 02 2A 03 + 15 00 02 2B 85 + 15 00 02 2D 03 + 15 00 02 2F 8F + 15 00 02 30 03 + 15 00 02 31 CB + 15 00 02 32 00 + 15 00 02 33 BB + 15 00 02 34 00 + 15 00 02 35 C0 + 15 00 02 36 00 + 15 00 02 37 CC + 15 00 02 38 00 + 15 00 02 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15 00 02 FF 04 + 15 00 02 FB 01 + 15 00 02 FF 00 + 15 00 02 D3 05 + 15 00 02 D4 04 + 05 78 01 11 + 15 00 02 FF 00 + 15 00 02 35 00 + 05 0A 01 29 + ]; + + panel-init-sequence2 = [ + 39 00 04 B9 FF 83 99 + 39 00 05 BA 63 23 68 CF + 15 00 02 D2 55 + 39 00 10 B1 02 04 70 90 01 32 33 11 11 4D 57 56 73 02 02 + 39 00 0c B2 00 80 80 AE 0A 0E 75 11 00 00 00 + 39 00 2f B4 00 FF 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 21 03 00 00 08 A6 88 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 00 00 08 A6 00 08 11 + 39 00 22 D3 00 00 00 00 00 00 18 18 32 10 09 00 09 32 10 00 00 00 00 00 00 00 00 11 00 02 02 03 00 00 00 0A 40 + 39 00 21 D5 18 18 18 18 21 20 18 18 19 19 19 19 18 18 18 18 03 02 01 00 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 21 D6 18 18 18 18 20 21 19 19 18 18 19 19 18 18 18 18 00 01 02 03 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 09 D8 0A BE FA A0 0A BE FA A0 + 15 00 02 BD 01 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 02 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 00 + 39 00 37 E0 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 C5 BD C5 B6 C2 C2 62 5D 66 73 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 B5 BD C5 B6 C2 C2 62 5D 66 73 + 39 00 03 B6 97 97 + 15 00 02 CC C8 + 39 00 05 BF 40 41 50 19 + 39 00 03 C6 FF F9 + 39 00 03 C0 25 5A + 05 78 01 11 + 05 14 01 29 + ]; + + panel-exit-sequence = [ + 05 05 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <152200000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <104>; + hsync-len = <4>; + hback-porch = <127>; + vfront-porch = <4>; + vsync-len = <2>; + vback-porch = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + disp_timings01: display-timings1 { + native-mode = <&dsi0_timing01>; + dsi0_timing01: timing01 { + clock-frequency = <152350000>; + hactive = <1920>; + vactive = <1200>; + hfront-porch = <110>; + hsync-len = <4>; + hback-porch = <32>; + vfront-porch = <11>; + vsync-len = <4>; + vback-porch = <14>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@7 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + ft5336: ft5336@38 { + compatible = "edt,edt-ft5336", "ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = ; + reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_rst_gpio>; + status = "okay"; + }; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + max-x = <1920>; + max-y = <1200>; + tp-size = <89>; + status = "okay"; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + ft5336 { + tp_rst_gpio: tp-rst-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dsi0-lcd { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-display-dsi1.dts b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-display-dsi1.dts new file mode 100644 index 0000000000000..b633e7d11b39e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/khadas-edge2-display-dsi1.dts @@ -0,0 +1,753 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_mipi1: backlight-mipi1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm13 0 25000 0>; + power-supply = <&vcc3v3_lcd2_en>; + status = "okay"; + }; + + vcc3v3_lcd2_en: vcc3v3-lcd2-en { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd2_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + status = "okay"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + fragment@1 { + target = <&pwm13>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm13m1_pins>; + }; + }; + + fragment@2 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@4 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&route_dsi1>; + + __overlay__ { + connect = <&vp3_out_dsi1>; + status = "okay"; + }; + }; + + fragment@6 { + target = <&dsi1>; + + __overlay__ { + reset-delay-ms = <20>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd2_rst_gpio1>; + status = "okay"; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight_mipi1>; + power-supply = <&vcc3v3_lcd2_en>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 FF 05 + 15 00 02 FB 01 + 15 64 02 C5 01 + 15 00 02 FF EE + 15 00 02 FB 01 + 15 00 02 1F 45 + 15 00 02 24 4F + 15 00 02 38 C8 + 15 00 02 39 27 + 15 00 02 1E 77 + 15 00 02 1D 0F + 15 00 02 7E 71 + 15 00 02 7C 03 + 15 00 02 FF 00 + 15 00 02 FB 01 + 15 00 02 35 01 + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 00 01 + 15 00 02 01 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03 + 15 00 02 60 2D + 15 00 02 61 03 + 15 00 02 62 39 + 15 00 02 63 03 + 15 00 02 64 47 + 15 00 02 65 03 + 15 00 02 66 57 + 15 00 02 67 03 + 15 00 02 68 65 + 15 00 02 69 03 + 15 00 02 6A 77 + 15 00 02 6B 03 + 15 00 02 6C 85 + 15 00 02 6D 03 + 15 00 02 6E 8F + 15 00 02 6F 03 + 15 00 02 70 CB + 15 00 02 71 00 + 15 00 02 72 00 + 15 00 02 73 00 + 15 00 02 74 21 + 15 00 02 75 00 + 15 00 02 76 4C + 15 00 02 77 00 + 15 00 02 78 6B + 15 00 02 79 00 + 15 00 02 7A 85 + 15 00 02 7B 00 + 15 00 02 7C 9A + 15 00 02 7D 00 + 15 00 02 7E AD + 15 00 02 7F 00 + 15 00 02 80 BE + 15 00 02 81 00 + 15 00 02 82 CD + 15 00 02 83 01 + 15 00 02 84 01 + 15 00 02 85 01 + 15 00 02 86 29 + 15 00 02 87 01 + 15 00 02 88 68 + 15 00 02 89 01 + 15 00 02 8A 98 + 15 00 02 8B 01 + 15 00 02 8C E5 + 15 00 02 8D 02 + 15 00 02 8E 1E + 15 00 02 8F 02 + 15 00 02 90 30 + 15 00 02 91 02 + 15 00 02 92 52 + 15 00 02 93 02 + 15 00 02 94 88 + 15 00 02 95 02 + 15 00 02 96 AA + 15 00 02 97 02 + 15 00 02 98 D7 + 15 00 02 99 02 + 15 00 02 9A F7 + 15 00 02 9B 03 + 15 00 02 9C 21 + 15 00 02 9D 03 + 15 00 02 9E 2E + 15 00 02 9F 03 + 15 00 02 A0 3D + 15 00 02 A2 03 + 15 00 02 A3 4C + 15 00 02 A4 03 + 15 00 02 A5 5E + 15 00 02 A6 03 + 15 00 02 A7 71 + 15 00 02 A9 03 + 15 00 02 AA 86 + 15 00 02 AB 03 + 15 00 02 AC 94 + 15 00 02 AD 03 + 15 00 02 AE FA + 15 00 02 AF 00 + 15 00 02 B0 00 + 15 00 02 B1 00 + 15 00 02 B2 21 + 15 00 02 B3 00 + 15 00 02 B4 4C + 15 00 02 B5 00 + 15 00 02 B6 6B + 15 00 02 B7 00 + 15 00 02 B8 85 + 15 00 02 B9 00 + 15 00 02 BA 9A + 15 00 02 BB 00 + 15 00 02 BC AD + 15 00 02 BD 00 + 15 00 02 BE BE + 15 00 02 BF 00 + 15 00 02 C0 CD + 15 00 02 C1 01 + 15 00 02 C2 01 + 15 00 02 C3 01 + 15 00 02 C4 29 + 15 00 02 C5 01 + 15 00 02 C6 68 + 15 00 02 C7 01 + 15 00 02 C8 98 + 15 00 02 C9 01 + 15 00 02 CA E5 + 15 00 02 CB 02 + 15 00 02 CC 1E + 15 00 02 CD 02 + 15 00 02 CE 20 + 15 00 02 CF 02 + 15 00 02 D0 52 + 15 00 02 D1 02 + 15 00 02 D2 88 + 15 00 02 D3 02 + 15 00 02 D4 AA + 15 00 02 D5 02 + 15 00 02 D6 D7 + 15 00 02 D7 02 + 15 00 02 D8 F7 + 15 00 02 D9 03 + 15 00 02 DA 21 + 15 00 02 DB 03 + 15 00 02 DC 2E + 15 00 02 DD 03 + 15 00 02 DE 3D + 15 00 02 DF 03 + 15 00 02 E0 4C + 15 00 02 E1 03 + 15 00 02 E2 5E + 15 00 02 E3 03 + 15 00 02 E4 71 + 15 00 02 E5 03 + 15 00 02 E6 86 + 15 00 02 E7 03 + 15 00 02 E8 94 + 15 00 02 E9 03 + 15 00 02 EA FA + 15 00 02 FF 01 + 15 00 02 FB 01 + 15 00 02 FF 02 + 15 00 02 FB 01 + 15 00 02 FF 04 + 15 00 02 FB 01 + 15 00 02 FF 00 + 15 00 02 D3 05 + 15 00 02 D4 04 + 05 78 01 11 + 15 00 02 FF 00 + 15 00 02 35 00 + 05 0A 01 29 + ]; + + panel-init-sequence2 = [ + 39 00 04 B9 FF 83 99 + 39 00 05 BA 63 23 68 CF + 15 00 02 D2 55 + 39 00 10 B1 02 04 70 90 01 32 33 11 11 4D 57 56 73 02 02 + 39 00 0c B2 00 80 80 AE 0A 0E 75 11 00 00 00 + 39 00 2f B4 00 FF 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 21 03 00 00 08 A6 88 04 A4 02 A0 00 00 10 00 00 02 00 24 02 04 0A 00 00 08 A6 00 08 11 + 39 00 22 D3 00 00 00 00 00 00 18 18 32 10 09 00 09 32 10 00 00 00 00 00 00 00 00 11 00 02 02 03 00 00 00 0A 40 + 39 00 21 D5 18 18 18 18 21 20 18 18 19 19 19 19 18 18 18 18 03 02 01 00 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 21 D6 18 18 18 18 20 21 19 19 18 18 19 19 18 18 18 18 00 01 02 03 2F 2F 30 30 31 31 18 18 18 18 18 18 + 39 00 09 D8 0A BE FA A0 0A BE FA A0 + 15 00 02 BD 01 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 02 + 39 00 09 D8 0F FF FF E0 0F FF FF E0 + 15 00 02 BD 00 + 39 00 37 E0 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 C5 BD C5 B6 C2 C2 62 5D 66 73 01 35 41 3B 79 81 8C 85 8E 95 9B A0 A4 AB B1 B3 B7 B5 BD C5 B6 C2 C2 62 5D 66 73 + 39 00 03 B6 97 97 + 15 00 02 CC C8 + 39 00 05 BF 40 41 50 19 + 39 00 03 C6 FF F9 + 39 00 03 C0 25 5A + 05 78 01 11 + 05 14 01 29 + ]; + + panel-exit-sequence = [ + 05 05 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <152198100>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <104>; + hsync-len = <4>; + hback-porch = <127>; + vfront-porch = <4>; + vsync-len = <2>; + vback-porch = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@7 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + lcd2_rst_gpio1: lcd2-rst-gpio1 { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-sata2.dts b/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-sata2.dts new file mode 100644 index 0000000000000..c68e11dc16049 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-sata2.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pcie2x1l1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&sata2>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi0-yx35.dts b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi0-yx35.dts new file mode 100755 index 0000000000000..c3ec4c91e0a59 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi0-yx35.dts @@ -0,0 +1,249 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&pwm_backlight>; + + __overlay__ { + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm10 0 25000 0>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&pwm10>; + + __overlay__ { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c4>; + + __overlay__ { + clock-frequency = <200000>; + pinctrl-0 = <&i2c4m3_xfer>; + status = "okay"; + + dsi0_gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_dsi0_gpio>; + interrupt-parent = <&gpio3>; + interrupts = ; + goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_EDGE_FALLING>; + goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + keep-otp-config; + status = "okay"; + }; + + dsi0_e2prom: eeprom@50 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x50>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + status = "okay"; + }; + }; + }; + + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + connect = <&vp2_out_dsi0>; + status = "okay"; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + dsi0_panel: panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + + backlight = <&pwm_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst0_gpio>; + reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + panel-name = "yx35,210dpi"; + nvmems = <&dsi0_i2c 0x50 0xe0 0x10>; + nvmem-status = <1>; + + reset-delay-ms = <20>; + init-delay-ms = <120>; + enable-delay-ms = <5>; + prepare-delay-ms = <0>; + unprepare-delay-ms = <10>; + disable-delay-ms = <5>; + width-mm = <45>; + height-mm = <75>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <2>; + panel-init-sequence = [ + 15 0A 02 01 00 + 15 7D 02 11 00 + 39 00 06 FF 77 01 00 00 13 + 15 00 02 EF 08 + 39 00 06 FF 77 01 00 00 10 + 39 00 03 C0 63 00 + 39 00 03 C1 14 14 + 39 00 03 C2 37 02 + 15 00 02 CC 10 + 39 00 11 B0 C5 11 1B 0D 11 07 0A 09 08 24 05 12 10 A9 32 DF + 39 00 11 B1 C5 19 21 0B 0E 03 0C 07 07 26 04 12 11 AA 32 DF + 39 00 06 FF 77 01 00 00 11 + 15 00 02 B0 4D + 15 00 02 B1 59 + 15 00 02 B2 81 + 15 00 02 B3 80 + 15 00 02 B5 4E + 15 00 02 B7 85 + 15 00 02 B8 32 + 15 00 02 BB 03 + 15 00 02 C1 08 + 15 00 02 C2 08 + 15 00 02 D0 88 + 39 00 04 E0 00 00 02 + 39 00 0C E1 06 28 08 28 05 28 07 28 0E 33 33 + 39 00 0D E2 30 30 33 33 34 00 00 00 34 00 00 00 + 39 00 05 E3 00 00 33 33 + 39 00 03 E4 44 44 + 39 00 11 E5 09 2F 2C 8C 0B 31 2C 8C 0D 33 2C 8C 0F 35 2C 8C + 39 00 05 E6 00 00 33 33 + 39 00 03 E7 44 44 + 39 00 11 E8 08 2E 2C 8C 0A 30 2C 8C 0C 32 2C 8C 0E 34 2C 8C + 39 00 03 E9 36 00 + 39 00 08 EB 00 01 E4 E4 44 88 40 + 39 00 11 ED FF FC B2 45 67 FA 01 FF FF 10 AF 76 54 2B CF FF + 39 00 07 EF 08 08 08 45 3F 54 + 39 00 06 FF 77 01 00 00 13 + 39 00 03 E8 00 0E + 15 78 02 11 00 + 39 0A 03 E8 00 0C + 39 00 03 E8 00 00 + 39 00 06 FF 77 01 00 00 00 + 15 00 02 36 00 + 15 00 02 29 00 + ]; + + panel-exit-sequence = [ + 15 00 02 28 00 + 15 3C 02 10 00 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <29700000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <40>; + hsync-len = <32>; + hback-porch = <30>; + vfront-porch = <20>; + vsync-len = <10>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi1-yx35.dts b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi1-yx35.dts new file mode 100755 index 0000000000000..96670975e5b59 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/nanopi-m6-display-dsi1-yx35.dts @@ -0,0 +1,249 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target = <&pwm_backlight>; + + __overlay__ { + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm11 0 25000 0>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&pwm11>; + + __overlay__ { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c5>; + + __overlay__ { + clock-frequency = <200000>; + pinctrl-0 = <&i2c5m2_xfer>; + status = "okay"; + + dsi1_gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_dsi1_gpio>; + interrupt-parent = <&gpio4>; + interrupts = ; + goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>; + goodix,rst-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + keep-otp-config; + status = "okay"; + }; + + dsi1_e2prom: eeprom@50 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x50>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + status = "okay"; + }; + }; + }; + + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + connect = <&vp2_out_dsi1>; + status = "okay"; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + dsi1_panel: panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + + backlight = <&pwm_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst1_gpio>; + reset-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + panel-name = "yx35,210dpi"; + nvmems = <&i2c5 0x50 0xe0 0x10>; + nvmem-status = <1>; + + reset-delay-ms = <20>; + init-delay-ms = <120>; + enable-delay-ms = <5>; + prepare-delay-ms = <0>; + unprepare-delay-ms = <10>; + disable-delay-ms = <5>; + width-mm = <45>; + height-mm = <75>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <2>; + panel-init-sequence = [ + 15 0A 02 01 00 + 15 7D 02 11 00 + 39 00 06 FF 77 01 00 00 13 + 15 00 02 EF 08 + 39 00 06 FF 77 01 00 00 10 + 39 00 03 C0 63 00 + 39 00 03 C1 14 14 + 39 00 03 C2 37 02 + 15 00 02 CC 10 + 39 00 11 B0 C5 11 1B 0D 11 07 0A 09 08 24 05 12 10 A9 32 DF + 39 00 11 B1 C5 19 21 0B 0E 03 0C 07 07 26 04 12 11 AA 32 DF + 39 00 06 FF 77 01 00 00 11 + 15 00 02 B0 4D + 15 00 02 B1 59 + 15 00 02 B2 81 + 15 00 02 B3 80 + 15 00 02 B5 4E + 15 00 02 B7 85 + 15 00 02 B8 32 + 15 00 02 BB 03 + 15 00 02 C1 08 + 15 00 02 C2 08 + 15 00 02 D0 88 + 39 00 04 E0 00 00 02 + 39 00 0C E1 06 28 08 28 05 28 07 28 0E 33 33 + 39 00 0D E2 30 30 33 33 34 00 00 00 34 00 00 00 + 39 00 05 E3 00 00 33 33 + 39 00 03 E4 44 44 + 39 00 11 E5 09 2F 2C 8C 0B 31 2C 8C 0D 33 2C 8C 0F 35 2C 8C + 39 00 05 E6 00 00 33 33 + 39 00 03 E7 44 44 + 39 00 11 E8 08 2E 2C 8C 0A 30 2C 8C 0C 32 2C 8C 0E 34 2C 8C + 39 00 03 E9 36 00 + 39 00 08 EB 00 01 E4 E4 44 88 40 + 39 00 11 ED FF FC B2 45 67 FA 01 FF FF 10 AF 76 54 2B CF FF + 39 00 07 EF 08 08 08 45 3F 54 + 39 00 06 FF 77 01 00 00 13 + 39 00 03 E8 00 0E + 15 78 02 11 00 + 39 0A 03 E8 00 0C + 39 00 03 E8 00 00 + 39 00 06 FF 77 01 00 00 00 + 15 00 02 36 00 + 15 00 02 29 00 + ]; + + panel-exit-sequence = [ + 15 00 02 28 00 + 15 3C 02 10 00 + ]; + + display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <29700000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <40>; + hsync-len = <32>; + hback-porch = <30>; + vfront-porch = <20>; + vsync-len = <10>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-ap6275p.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-ap6275p.dts new file mode 100644 index 0000000000000..8e00f95992a84 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-ap6275p.dts @@ -0,0 +1,19 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&wireless_bluetooth>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&wireless_wlan>; + __overlay__ { + status = "okay"; + wifi_chip_type = "ap6275p"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-disable-led.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-disable-led.dts new file mode 100644 index 0000000000000..e1c31d41e768b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-disable-led.dts @@ -0,0 +1,17 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&leds>; + + __overlay__ { + status = "okay"; + + led@1 { + linux,default-trigger = "none"; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd1.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd1.dts new file mode 100644 index 0000000000000..e70752aa050c9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd1.dts @@ -0,0 +1,214 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_1: backlight_1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm6 0 25000 0>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&dsi1>; + __overlay__ { + status = "okay"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight_1>; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi_dcphy1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi1_in_vp3>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&hdmi0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&hdptxphy_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&route_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dp0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&dp0_in_vp1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&dp0_in_vp2>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&dp0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@12 { + target = <&spdif_tx2>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@13 { + target = <&i2c2>; + __overlay__ { + status = "okay"; + + gt9xx_0: touchscreen@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PA7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + //touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + status = "okay"; + }; + }; + }; + + fragment@14 { + target = <&route_dsi1>; + __overlay__ { + status = "disabled"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@15 { + target = <&pwm6>; + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd2.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd2.dts new file mode 100644 index 0000000000000..4330a00d1f80f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-lcd2.dts @@ -0,0 +1,216 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm2 0 25000 0>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&dsi0>; + __overlay__ { + status = "okay"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi_dcphy0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi0_in_vp2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&hdmi0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&hdptxphy_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&route_hdmi0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dp0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&dp0_in_vp1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&dp0_in_vp2>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&dp0_sound>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@12 { + target = <&spdif_tx2>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@13 { + target = <&i2c7>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + gt9xx_1: touchscreen@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + //touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + status = "okay"; + }; + }; + }; + + fragment@14 { + target = <&route_dsi0>; + __overlay__ { + status = "disabled"; + connect = <&vp2_out_dsi0>; + }; + }; + + fragment@15 { + target = <&pwm2>; + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-disable-leds.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-disable-leds.dts new file mode 100644 index 0000000000000..db7d9fa05cfb0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-disable-leds.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&leds>; + + __overlay__ { + status = "okay"; + + blue_led@1 { + linux,default-trigger = "none"; + }; + + green_led@2 { + linux,default-trigger = "none"; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-hdmi2-8k.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-hdmi2-8k.dts new file mode 100644 index 0000000000000..8d9992169fd58 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-hdmi2-8k.dts @@ -0,0 +1,37 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&hdmi0_in_vp0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&hdmi0_in_vp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&hdmi1_in_vp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&hdmi1_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-lcd.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-lcd.dts new file mode 100644 index 0000000000000..4cf55f15ed5ac --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-lcd.dts @@ -0,0 +1,153 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm2 0 25000 0>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&mipi_te1>; + status = "okay"; + //rockchip,lane-rate = <1000>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&route_dsi1>; + + __overlay__ { + status = "disabled"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@4 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + + gt9xx_0: touchscreen@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&gpio2>; + interrupts = ; + irq-gpios = <&gpio2 RK_PB2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + //touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + status = "okay"; + }; + }; + }; + + fragment@5 { + target = <&pwm2>; + + __overlay__ { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + status = "okay"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-ov13850.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-ov13850.dts new file mode 100644 index 0000000000000..366a904dc3fb3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-ov13850.dts @@ -0,0 +1,101 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp0_vir1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + + vm149c-p1@c { + status = "okay"; + }; + + ov13850-1@10 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-ov13855.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-ov13855.dts new file mode 100644 index 0000000000000..f3c29c825c8d0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-ov13855.dts @@ -0,0 +1,101 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp0_vir1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + + dw9714-p1@c { + status = "okay"; + }; + + ov13855-1@36 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-sata2.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-sata2.dts new file mode 100644 index 0000000000000..0491a4967d745 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-plus-sata2.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&sata2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&pcie2x1l1>; + + __overlay__ { + status = "disabled"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-cam1.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-cam1.dts new file mode 100644 index 0000000000000..b6e6a215b7145 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-cam1.dts @@ -0,0 +1,108 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp0_vir1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + + vm149c-p1@c { + status = "okay"; + }; + + ov13850-1@10 { + status = "okay"; + }; + + dw9714-p1@c { + status = "okay"; + }; + + ov13855-1@36 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-cam2.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-cam2.dts new file mode 100644 index 0000000000000..04bcabab79440 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-cam2.dts @@ -0,0 +1,102 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + fragment@0 { + target = <&csi2_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&mipi0_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&rkcif_mipi_lvds>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp1_vir0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + + vm149c-p2@c { + status = "okay"; + }; + + ov13850-2@10 { + status = "okay"; + }; + + dw9714-p2@c { + status = "okay"; + }; + + ov13855-2@36 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-disable-leds.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-disable-leds.dts new file mode 100644 index 0000000000000..c8501f3a2c2f8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-disable-leds.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&leds>; + + __overlay__ { + status = "okay"; + + blue_led@1 { + linux,default-trigger = "none"; + }; + + green_led@2 { + linux,default-trigger = "none"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-lcd.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-lcd.dts new file mode 100644 index 0000000000000..a2d70291c64b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-lcd.dts @@ -0,0 +1,129 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm6 0 25000 0>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&dsi1>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_te1>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c7>; + __overlay__ { + status = "okay"; + + gt9xx_0: touchscreen@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + //touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&dsi1_in_vp3>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-sfc.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-sfc.dts new file mode 100644 index 0000000000000..9cd2037505234 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-pro-sfc.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&sfc>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&sdhci>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-sata.dts b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-sata.dts new file mode 100644 index 0000000000000..2ec37defd3185 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/orangepi-5-sata.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&sata0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&pcie2x1l2>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-camera-4k.dts new file mode 100644 index 0000000000000..9ac4959d81f49 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-camera-4k.dts @@ -0,0 +1,209 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CSI1"; + compatible = "radxa,cm5-io"; + category = "camera"; + exclusive = "csi2_dcphy0"; + description = "Enable Radxa Camera 4K on CSI1."; + }; + + fragment@0 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c8m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidcphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dcphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidcphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + + fragment@3 { + target = <&mipi0_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi0_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi0_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-display-10hd.dts new file mode 100644 index 0000000000000..c26449b60dc34 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-display-10hd.dts @@ -0,0 +1,215 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 10HD on DSI1"; + compatible = "radxa,cm5-io"; + category = "display"; + exclusive = "dsi1"; + description = "Enable Radxa Display 10HD on DSI1."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + lcd_3v3: lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm15 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm15>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m1_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible ="radxa,display-10hd-ad001"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&lcd_3v3>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech: focaltech@38 { + status = "okay"; + compatible = "focaltech,fts"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&focaltech_gpio>; + focaltech,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_HIGH>; + focaltech,reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + focaltech,display-coords = <0 0 799 1279>; + }; + }; + }; + + fragment@10 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + focaltech { + focaltech_gpio: focaltech-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-display-8hd.dts new file mode 100644 index 0000000000000..2b18f0d8f817f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-radxa-display-8hd.dts @@ -0,0 +1,218 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD on DSI1"; + compatible = "radxa,cm5-io"; + category = "display"; + exclusive = "dsi1"; + description = "Enable Radxa Display 8HD on DSI1."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + lcd_3v3: lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm15 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm15>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m1_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible ="radxa,display-8hd"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&lcd_3v3>; + //vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&lcd_3v3>; + }; + }; + }; + + fragment@10 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-raspi-7inch-touchscreen.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-raspi-7inch-touchscreen.dts new file mode 100644 index 0000000000000..36e0fa7992ddd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-raspi-7inch-touchscreen.dts @@ -0,0 +1,104 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable Raspberry Pi 7-inch Touchscreen on DSI0"; + compatible = "radxa,cm5-io"; + category = "display"; + exclusive = "dsi0"; + description = "Enable Raspberry Pi 7-inch Touchscreen on DSI0."; + }; + + fragment@0 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + rockchip,lane-rate = <696>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c7m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + raspits_panel: raspits-panel@45 { + compatible = "raspberrypi,7inch-touchscreen-panel"; + reg = <0x45>; + + port { + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + + raspits_touch_ft5426: raspits-touch-ft5426@38 { + compatible = "raspits_ft5426"; + reg = <0x38>; + }; + + chipone_icn8952: chipone_icn8952@30 { + compatible = "chipone_icn8505"; + reg = <0x30>; + }; + }; + }; + + fragment@2 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@4 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-rpi-camera-v2.dts new file mode 100644 index 0000000000000..1535caa07bb61 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-rpi-camera-v2.dts @@ -0,0 +1,240 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2 on CSI0"; + compatible = "radxa,cm5-io"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Raspberry Pi Camera V2 on CSI1."; + }; + + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c7m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-sata.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-sata.dts new file mode 100644 index 0000000000000..f498132adf16c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-cm5-io-sata.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + + metadata { + title = "Enable SATA0"; + compatible = "radxa,cm5-io"; + category = "misc"; + exclusive = "combphy0_ps"; + description = "Enable SATA0.\nWhen SATA0 is enabled, PCIe cannot be enabled on the same port."; + }; + + fragment@0 { + target = <&pcie2x1l2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&sata0>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-nx5-io-rpi-camera-v2-cam0.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-nx5-io-rpi-camera-v2-cam0.dts new file mode 100644 index 0000000000000..a247215ed6ef0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-nx5-io-rpi-camera-v2-cam0.dts @@ -0,0 +1,238 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera v2 on CAM0"; + compatible = "radxa,nx5-io"; + category = "camera"; + exclusive = "csi2_dcphy0"; + description = "Enable Raspberry Pi Camera v2 on CAM0."; + }; + + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera0_pwdn_gpio: camera0-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera0_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_pwdn_gpio>; + }; + + clk_cam0_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam0_24m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c4m2_xfer>; + + camera0_imx219: camera0-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam0_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidcphy0_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dcphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidcphy0_in_ucam0: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi0_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi0_in0>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi0_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp1_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam0_pwdn_gpio: cam0-pwdn-gpio { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-nx5-io-rpi-camera-v2-cam1.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-nx5-io-rpi-camera-v2-cam1.dts new file mode 100644 index 0000000000000..5f50b2cce99ac --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-nx5-io-rpi-camera-v2-cam1.dts @@ -0,0 +1,237 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera v2 on CAM1"; + compatible = "radxa,nx5-io"; + category = "camera"; + exclusive = "csi2_dphy2"; + description = "Enable Raspberry Pi Camera v2 on CAM1."; + }; + + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera1_pwdn_gpio: camera1-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera1_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam1_pwdn_gpio>; + }; + + clk_cam1_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam1_24m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + + camera1_imx219: camera1-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam1_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out1: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi3_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi3_in0>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds3>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi3_in0: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds3_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds3_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds3_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam1_pwdn_gpio: cam1-pwdn-gpio { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-disabled-ethernet.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-disabled-ethernet.dts new file mode 100644 index 0000000000000..c8b84be08e2c4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-disabled-ethernet.dts @@ -0,0 +1,31 @@ +/dts-v1/; +/plugin/; + +#include +#include + + +/ { + metadata { + title = "Disabled Zero 3W Ethernet"; + compatible = "radxa,zero3"; + category = "misc"; + description = "Disabled Zero 3W Ethernet."; + }; + + fragment@0 { + target = <&mdio1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&gmac1>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-disabled-wireless.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-disabled-wireless.dts new file mode 100644 index 0000000000000..7b1fc065c0c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-disabled-wireless.dts @@ -0,0 +1,31 @@ +/dts-v1/; +/plugin/; + +#include +#include + + +/ { + metadata { + title = "Disabled Zero 3E Wireless"; + compatible = "radxa,zero3"; + category = "misc"; + description = "Disabled Zero 3E Wireless."; + }; + + fragment@0 { + target = <&uart1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&sdmmc1>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-external-antenna.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-external-antenna.dts new file mode 100644 index 0000000000000..196ab187c372a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-external-antenna.dts @@ -0,0 +1,46 @@ +/dts-v1/; +/plugin/; + +#include +#include + + +/ { + metadata { + title = "Enable external antenna"; + compatible = "radxa,zero3"; + category = "misc"; + exclusive = "GPIO3_D2"; + description = "Enable external antenna."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + board_antenna: board-antenna { + status = "okay"; + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + pinctrl-0 = <&ant_1>; + pinctrl-names = "default"; + regulator-name = "board_antenna"; + }; + }; + }; + + fragment@1 { + target = <&pinctrl>; + + __overlay__ { + antenna { + ant_1: ant-1 { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-rpi-camera-v1.3.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-rpi-camera-v1.3.dts new file mode 100644 index 0000000000000..7c96d28970ad5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-rpi-camera-v1.3.dts @@ -0,0 +1,156 @@ +/dts-v1/; +/plugin/; + +#include +#include + + +/ { + metadata { + title = "Enable Raspberry Pi Camera v1.3"; + compatible = "radxa,zero3"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Raspberry Pi Camera v1.3."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + camera_ov5647: camera-ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v1p3"; + rockchip,camera-module-lens-name = "default"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkisp_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy0_out>; + }; + }; + }; + }; + + fragment@5 { + target = <&rkisp>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkisp_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-rpi-camera-v2.dts new file mode 100644 index 0000000000000..6b1121af68c74 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/radxa-zero3-rpi-camera-v2.dts @@ -0,0 +1,165 @@ +/dts-v1/; +/plugin/; + +#include +#include + + +/ { + metadata { + title = "Enable Raspberry Pi Camera v2"; + compatible = "radxa,zero3"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Raspberry Pi Camera v2."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + clk_cam_24m: external-camera-clock-24m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; + + camera_pwdn_gpio: camera-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@1 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + status = "okay"; + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkisp_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy0_out>; + }; + }; + }; + }; + + fragment@5 { + target = <&rkisp>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkisp_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3566-roc-pc-sata2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3566-roc-pc-sata2.dts new file mode 100644 index 0000000000000..0de43e5a22d36 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3566-roc-pc-sata2.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&sata2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&pcie2x1>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-can1-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-can1-m1.dts new file mode 100644 index 0000000000000..b470f1e0fff36 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-can1-m1.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&can1>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c0-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c0-m1.dts new file mode 100755 index 0000000000000..0ad56e111a762 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c0-m1.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + + fragment@0 { + target = <&i2c0>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c0m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c1-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c1-m0.dts new file mode 100755 index 0000000000000..a02d1a66ea969 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c1-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + + fragment@0 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c1m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c2-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c2-m0.dts new file mode 100755 index 0000000000000..434f1d557e580 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c2-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c3-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c3-m0.dts new file mode 100755 index 0000000000000..c9fb6b4e5cfcb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c3-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c4-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c4-m3.dts new file mode 100755 index 0000000000000..48792fe644750 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c4-m3.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c5-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c5-m3.dts new file mode 100755 index 0000000000000..be0f852b74d44 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c5-m3.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c6-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c6-m0.dts new file mode 100755 index 0000000000000..f7eae2716d0ad --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c6-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + + fragment@0 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c6m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c7-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c7-m1.dts new file mode 100755 index 0000000000000..1d3e2047f1d3f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c7-m1.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +/ { + + + fragment@0 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c7m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c8-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c8-m2.dts new file mode 100755 index 0000000000000..24993c8809842 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-i2c8-m2.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm1-ch0-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm1-ch0-m3.dts new file mode 100755 index 0000000000000..aa71447364d7d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm1-ch0-m3.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm1_6ch_0>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm1m3_ch0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm2-ch6-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm2-ch6-m2.dts new file mode 100755 index 0000000000000..0031d363ed5ca --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm2-ch6-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm2_8ch_6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm2m2_ch6>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm2-ch7-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm2-ch7-m2.dts new file mode 100755 index 0000000000000..c5edfec17b2ab --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-pwm2-ch7-m2.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + + fragment@0 { + target = <&pwm2_8ch_7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm2m2_ch7>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-spi4-m0-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-spi4-m0-cs1-spidev.dts new file mode 100755 index 0000000000000..49c25ad0108e4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-spi4-m0-cs1-spidev.dts @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_csn0 &spi4m0_pins>; + + spidev@1 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart10-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart10-m2.dts new file mode 100755 index 0000000000000..ff0b90569bd27 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart10-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart10>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart10m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart2-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart2-m2.dts new file mode 100755 index 0000000000000..030a0f5a8ae6e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart2-m2.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + + fragment0 { + target = <&uart2>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart2m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart6-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart6-m3.dts new file mode 100755 index 0000000000000..c2b1d4afc3f49 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart6-m3.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart6m3_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart7-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart7-m0.dts new file mode 100755 index 0000000000000..65c2a18af15e9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3576-uart7-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + + fragment@0 { + target = <&uart7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart7m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-can0-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can0-m0.dts new file mode 100644 index 0000000000000..54562280c4bcf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can0-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&can0>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-can1-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can1-m0.dts new file mode 100644 index 0000000000000..10348b755b6fc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can1-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&can1>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-can1-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can1-m1.dts new file mode 100644 index 0000000000000..b470f1e0fff36 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can1-m1.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&can1>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-can2-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can2-m1.dts new file mode 100644 index 0000000000000..0756868744bf7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-can2-m1.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&can2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-dwc3-host.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-dwc3-host.dts new file mode 100644 index 0000000000000..2536a594059fe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-dwc3-host.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Set OTG port to Host mode"; + compatible = "rockchip,rk3588"; + category = "misc"; + exclusive = "usbdrd_dwc3-dr_mode"; + description = "Set OTG port to Host mode.\nUse this when you want to connect USB devices."; + }; + + fragment@0 { + target = <&usbdrd_dwc3_0>; + + __overlay__ { + status = "okay"; + dr_mode = "host"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-dwc3-peripheral.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-dwc3-peripheral.dts new file mode 100644 index 0000000000000..52543fcab9e2e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-dwc3-peripheral.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Set OTG port to Peripheral mode"; + compatible = "rockchip,rk3588"; + category = "misc"; + exclusive = "usbdrd_dwc3-dr_mode"; + description = "Set OTG port to Peripheral mode.\nUse this when you want to connect to another computer."; + }; + + fragment@0 { + target = <&usbdrd_dwc3_0>; + + __overlay__ { + status = "okay"; + dr_mode = "peripheral"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-hdmirx.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-hdmirx.dts new file mode 100644 index 0000000000000..91b3120d309ed --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-hdmirx.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&hdmirx_ctrler>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c0-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c0-m1.dts new file mode 100644 index 0000000000000..e906b00d41e55 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c0-m1.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable I2C0-M1"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO4_C6", "GPIO4_C5"; + description = "Enable I2C0-M1.\nOn Radxa ROCK 5B this is SDA pin 27 and this is SCL pin 28."; + }; + + fragment@0 { + target = <&i2c0>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c0m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m0.dts new file mode 100644 index 0000000000000..ea50a65a5ceb7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m0.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable I2C1-M0"; + compatible = "radxa,rock-5a", "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO0_B5", "GPIO0_B6"; + description = "Enable I2C1-M0.\nOn Radxa ROCK 5A this is SDA pin 10 and SCL pin 8.\nOn Radxa ROCK 5B this is SDA pin 10 and SCL pin 8."; + }; + + fragment@0 { + target = <&fiq_debugger>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c1m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m2.dts new file mode 100644 index 0000000000000..5d8e3104f4dd9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m2.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m4.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m4.dts new file mode 100644 index 0000000000000..e581359fe5a1b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c1-m4.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m4_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c2-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c2-m0.dts new file mode 100644 index 0000000000000..434f1d557e580 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c2-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c2-m4.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c2-m4.dts new file mode 100644 index 0000000000000..c766203eb4857 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c2-m4.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c3-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c3-m0.dts new file mode 100644 index 0000000000000..c9fb6b4e5cfcb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c3-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c3-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c3-m1.dts new file mode 100644 index 0000000000000..3f23eaf893ef0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c3-m1.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable I2C3-M1"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_B7", "GPIO3_C0"; + description = "Enable I2C3-M1.\nOn Radxa ROCK 5B this is SDA pin 15 and this is SCL pin 13."; + }; + + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c3m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c4-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c4-m3.dts new file mode 100644 index 0000000000000..48792fe644750 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c4-m3.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c5-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c5-m3.dts new file mode 100644 index 0000000000000..be0f852b74d44 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c5-m3.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m0.dts new file mode 100644 index 0000000000000..edc5595bdf271 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m0.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable I2C6-M0"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO0_C7", "GPIO0_D0"; + description = "Enable I2C6-M0.\nOn Radxa ROCK 5A this is SDA pin 27 and SCL pin 28."; + }; + + fragment@0 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c6m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m3.dts new file mode 100644 index 0000000000000..f5cda0dbd2d00 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m3.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable I2C6-M3"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO4_B0", "GPIO4_B1"; + description = "Enable I2C6-M3.\nOn Radxa ROCK 5A this is SDA pin 32 and SCL pin 40."; + }; + + fragment@0 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c6m3_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m4.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m4.dts new file mode 100644 index 0000000000000..cd5050fb4d070 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c6-m4.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m4_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c7-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c7-m3.dts new file mode 100644 index 0000000000000..0a69cd6673a69 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c7-m3.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable I2C7-M3"; + compatible = "unknown"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable I2C7-M3."; + }; + + fragment@0 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c7m3_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c8-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c8-m2.dts new file mode 100644 index 0000000000000..24993c8809842 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c8-m2.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c8-m4.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c8-m4.dts new file mode 100644 index 0000000000000..4144c9da79724 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-i2c8-m4.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable I2C8-M4"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_C3", "GPIO3_C2"; + description = "Enable I2C8-M4.\nOn Radxa ROCK 5B this is SDA pin 7 and SCL pin 32."; + }; + + fragment@0 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c8m4_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c1.dts new file mode 100644 index 0000000000000..1e692504723ec --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c1.dts @@ -0,0 +1,100 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp0_vir1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + + vm149c-p1@c { + status = "okay"; + }; + + ov13850-1@10 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c2.dts new file mode 100644 index 0000000000000..353a39a05a092 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c2.dts @@ -0,0 +1,94 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + fragment@0 { + target = <&csi2_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&mipi0_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&rkcif_mipi_lvds>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + + vm149c-p2@c { + status = "okay"; + }; + + ov13850-2@10 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c3.dts new file mode 100644 index 0000000000000..b1b7ee841fe55 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13850-c3.dts @@ -0,0 +1,94 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + fragment@0 { + target = <&csi2_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&mipi1_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&rkcif_mipi_lvds1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds1_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp1_vir0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + + vm149c@c { + status = "okay"; + }; + + ov13850@10 { + status = "okay"; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c1.dts new file mode 100644 index 0000000000000..1275ce0ed64c1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c1.dts @@ -0,0 +1,100 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp0_vir1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + + dw9714-p1@c { + status = "okay"; + }; + + ov13855-1@36 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c2.dts new file mode 100644 index 0000000000000..5822176874c94 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c2.dts @@ -0,0 +1,94 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + fragment@0 { + target = <&csi2_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&mipi0_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&rkcif_mipi_lvds>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + + dw9714-p2@c { + status = "okay"; + }; + + ov13855-2@36 { + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c3.dts new file mode 100644 index 0000000000000..20d4817724470 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-ov13855-c3.dts @@ -0,0 +1,94 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + fragment@0 { + target = <&csi2_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&mipi1_csi2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&rkcif_mipi_lvds1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif_mipi_lvds1_sditf>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp1_vir0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + + dw9714@c { + status = "okay"; + }; + + ov13855@36 { + status = "okay"; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m0.dts new file mode 100644 index 0000000000000..211ddc646f45d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm0>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m1.dts new file mode 100644 index 0000000000000..353162ec79ee1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m1.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm0>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm0m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m2.dts new file mode 100644 index 0000000000000..f7c03e93e3b84 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm0-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm0>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm0m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m0.dts new file mode 100644 index 0000000000000..bb19090ad249f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm1>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m1.dts new file mode 100644 index 0000000000000..e935135023ee6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m1.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm1>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m2.dts new file mode 100644 index 0000000000000..155d0bd4138b0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm1-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm1>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm1m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm10-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm10-m0.dts new file mode 100644 index 0000000000000..281071bbbc0f4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm10-m0.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm10>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm10m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm11-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm11-m0.dts new file mode 100644 index 0000000000000..1bebcd619d95b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm11-m0.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm11>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm11m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm11-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm11-m1.dts new file mode 100644 index 0000000000000..b85076feabadc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm11-m1.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM11-M1"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO4_B4"; + description = "Enable PWM11-M1.\nOn Radxa ROCK 5A this is pin 15."; + }; + + fragment@0 { + target = <&pwm11>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm11m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm12-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm12-m0.dts new file mode 100644 index 0000000000000..6dc0c7ed0b581 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm12-m0.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm12>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm12m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm13-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm13-m0.dts new file mode 100644 index 0000000000000..38ec499ce586f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm13-m0.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm13>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm13m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm13-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm13-m2.dts new file mode 100644 index 0000000000000..0d9b225fff0db --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm13-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm13>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm13m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m0.dts new file mode 100644 index 0000000000000..330406d939ad8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m0.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm14>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m1.dts new file mode 100644 index 0000000000000..82fec22ebbd12 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m1.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm14>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m2.dts new file mode 100644 index 0000000000000..7a26f2dc891a0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm14-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm14>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm14m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m0.dts new file mode 100644 index 0000000000000..076bef9f64d91 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m0.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM15-M0"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_C3"; + description = "Enable PWM15-M0.\nOn Radxa ROCK 5B this is pin 7."; + }; + + fragment@0 { + target = <&pwm15>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm15m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m1.dts new file mode 100644 index 0000000000000..7d3de70b05cfe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m1.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm15>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm15m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m2.dts new file mode 100644 index 0000000000000..c1b2aea10acbc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm15>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm15m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m3.dts new file mode 100644 index 0000000000000..79e421a4958fa --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm15-m3.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM15-M3"; + compatible = "radxa,rock-5a", "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO1_D7"; + description = "Enable PWM15-M3.\nOn Radxa ROCK 5A this is pin 3.\nOn Radxa ROCK 5B this is pin 29."; + }; + + fragment@0 { + target = <&pwm15>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm15m3_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm2-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm2-m1.dts new file mode 100644 index 0000000000000..653583fdb7e4f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm2-m1.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM2-M1"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_B1"; + description = "Enable PWM2-M1.\nOn Radxa ROCK 5B this is pin 36."; + }; + + fragment@0 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm2m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m0.dts new file mode 100644 index 0000000000000..a6a9181ab5963 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m0.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm3>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm3m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m1.dts new file mode 100644 index 0000000000000..23ff1ad689931 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m1.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM3-M1"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_B2"; + description = "Enable PWM3-M1.\nOn Radxa ROCK 5B this is pin 38."; + }; + + fragment@0 { + target = <&pwm3>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm3m1_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m2.dts new file mode 100644 index 0000000000000..b70d2097ea324 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm3>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm3m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m3.dts new file mode 100644 index 0000000000000..db544f2502fdf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm3-m3.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pwm3>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm3m3_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm5-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm5-m2.dts new file mode 100644 index 0000000000000..ce26d29f33cfe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm5-m2.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM5-M2"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO4_C4"; + description = "Enable PWM5-M2.\nOn Radxa ROCK 5B this is pin 18."; + }; + + fragment@0 { + target = <&pwm5>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm5m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm6-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm6-m0.dts new file mode 100644 index 0000000000000..e4d0ce3f58647 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm6-m0.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM6-M0"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO0_C7"; + description = "Enable PWM6-M0.\nOn Radxa ROCK 5A this is pin 27."; + }; + + fragment@0 { + target = <&pwm6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm6m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm6-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm6-m2.dts new file mode 100644 index 0000000000000..5e66d1d33ef42 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm6-m2.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM6-M2"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO4_C5"; + description = "Enable PWM6-M2.\nOn Radxa ROCK 5B this is pin 28."; + }; + + fragment@0 { + target = <&pwm6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm6m2_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm7-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm7-m0.dts new file mode 100644 index 0000000000000..6516762486dd4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm7-m0.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM7-M0"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO0_D0"; + description = "Enable PWM7-M0.\nOn Radxa ROCK 5A this is pin 28."; + }; + + fragment@0 { + target = <&pwm7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm7m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm7-m3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm7-m3.dts new file mode 100644 index 0000000000000..9a7d919f6cd6a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm7-m3.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM7-M3"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO4_C6"; + description = "Enable PWM7-M3.\nOn Radxa ROCK 5B this is pin 27."; + }; + + fragment@0 { + target = <&pwm7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm7m3_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm8-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm8-m0.dts new file mode 100644 index 0000000000000..e461cffb597af --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-pwm8-m0.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM8-M0"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_A7"; + description = "Enable PWM8-M0.\nOn Radxa ROCK 5B this is pin 33."; + }; + + fragment@0 { + target = <&pwm8>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&pwm8m0_pins>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m1-cs0-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m1-cs0-spidev.dts new file mode 100644 index 0000000000000..5566e5a84a90f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m1-cs0-spidev.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable spidev on SPI0-M1 over CS0"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO4_A2", "GPIO4_A1", "GPIO4_A0", "GPIO4_B2"; + description = "Enable spidev on SPI0-M1 over CS0."; + }; + + fragment@0 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>; + max-freq = <50000000>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m1-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m1-cs1-spidev.dts new file mode 100644 index 0000000000000..b90d880cae09b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m1-cs1-spidev.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable spidev on SPI0-M1 over CS1"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO4_A2", "GPIO4_A1", "GPIO4_A0", "GPIO4_B1"; + description = "Enable spidev on SPI0-M1 over CS1."; + }; + + fragment@0 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m1_cs1 &spi0m1_pins>; + max-freq = <50000000>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs0-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs0-cs1-spidev.dts new file mode 100644 index 0000000000000..b5b325e1b0fcf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs0-cs1-spidev.dts @@ -0,0 +1,31 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_cs0 &spi0m2_cs1 &spi0m2_pins>; + max-freq = <50000000>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + + spidev@1 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs0-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs0-spidev.dts new file mode 100644 index 0000000000000..d3843ab3407f6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs0-spidev.dts @@ -0,0 +1,24 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; + max-freq = <50000000>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs1-spidev.dts new file mode 100644 index 0000000000000..4335bd151efc9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi0-m2-cs1-spidev.dts @@ -0,0 +1,24 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_cs1 &spi0m2_pins>; + max-freq = <50000000>; + + spidev@1 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs0-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs0-spidev.dts new file mode 100644 index 0000000000000..d7a2cb889f56d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs0-spidev.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable spidev on SPI1-M1 over CS0"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_C2", "GPIO3_C1", "GPIO3_B7", "GPIO3_C0"; + description = "Enable spidev on SPI1-M1 over CS0."; + }; + + fragment@0 { + target = <&spi1>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + max-freq = <50000000>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs1-mcp2515-8mhz.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs1-mcp2515-8mhz.dts new file mode 100644 index 0000000000000..975a7f0ca1fb7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs1-mcp2515-8mhz.dts @@ -0,0 +1,60 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable MCP2515 with 8MHz external clock on SPI1-M1 over CS1"; + compatible = "unknown"; + category = "misc"; + description = "Provide support for Microchip MCP2515 SPI CAN controller.\nAssumes 8MHz external clock.\nUses Pin 19 (GPIOI1_B2) for INT."; + }; + + fragment@0 { + target = <&spi1>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_pins &spi1m1_cs0 &spi1m1_cs1>; + + can0: mcp2515@1 { + compatible = "microchip,mcp2515"; + reg = <1>; + spi-max-frequency = <10000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcp2515_int_pins>; + + interrupt-parent = <&gpio1>; + interrupts = ; + + clocks = <&can0_osc>; + }; + }; + }; + + fragment@1 { + target = <&pinctrl>; + __overlay__ { + mcp2515 { + mcp2515_int_pins: mcp2515-int-pins { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; + + fragment@2 { + target-path = "/"; + __overlay__ { + can0_osc: can0-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8000000>; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs1-spidev.dts new file mode 100644 index 0000000000000..13021103e9bc4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi1-m1-cs1-spidev.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable spidev on SPI1-M1 over CS1"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_C3", "GPIO3_C1", "GPIO3_B7", "GPIO3_C0"; + description = "Enable spidev on SPI1-M1 over CS1."; + }; + + fragment@0 { + target = <&spi1>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs1 &spi1m1_pins>; + max-freq = <50000000>; + + spidev@1 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m0-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m0-cs1-spidev.dts new file mode 100644 index 0000000000000..62447cff57e34 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m0-cs1-spidev.dts @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; + + spidev@1 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs0-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs0-cs1-spidev.dts new file mode 100644 index 0000000000000..2e40bc43ba48a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs0-cs1-spidev.dts @@ -0,0 +1,30 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m1_cs0 &spi4m1_cs1 &spi4m1_pins>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + + spidev@1 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs0-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs0-spidev.dts new file mode 100644 index 0000000000000..ed1f77cf1bbe5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs0-spidev.dts @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs1-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs1-spidev.dts new file mode 100644 index 0000000000000..40d10db5a7c6f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m1-cs1-spidev.dts @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m1_cs1 &spi4m1_pins>; + + spidev@1 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m2-cs0-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m2-cs0-spidev.dts new file mode 100644 index 0000000000000..a6b2d747ca86e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-spi4-m2-cs0-spidev.dts @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&spi4>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart0-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart0-m2.dts new file mode 100644 index 0000000000000..1d36d889dae2c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart0-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart0>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart0m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart1-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart1-m1.dts new file mode 100644 index 0000000000000..909f6058fd69e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart1-m1.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart1>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart1m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart2-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart2-m0.dts new file mode 100644 index 0000000000000..ce03b5c40b82e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart2-m0.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART2-M0"; + compatible = "radxa,rock-5a", "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO0_B5", "GPIO0_B6"; + description = "Enable UART2-M0.\nOn Radxa ROCK 5A this is TX pin 8 and RX pin 10.\nOn Radxa ROCK 5B this is TX pin 8 and this is RX pin 10."; + }; + + fragment@0 { + target = <&uart2>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart2m0_xfer>; + }; + }; + + fragment@1 { + target = <&fiq_debugger>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart2-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart2-m2.dts new file mode 100644 index 0000000000000..4fd0b40344f37 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart2-m2.dts @@ -0,0 +1,30 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART2-M2"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_B1", "GPIO3_B2"; + description = "Enable UART2-M2.\nOn Radxa ROCK 5B this is TX pin 36 and this is RX pin 38."; + }; + + fragment@0 { + target = <&fiq_debugger>; + + __overlay__ { + status = "okay"; + rockchip,serial-id = <0xffffffff>; + }; + }; + + fragment1 { + target = <&uart2>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart2m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart3-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart3-m0.dts new file mode 100644 index 0000000000000..c2e98cb61e750 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart3-m0.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart3>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart3m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart3-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart3-m1.dts new file mode 100644 index 0000000000000..cc5522c9cd3a7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart3-m1.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart3>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart3m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart4-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart4-m0.dts new file mode 100644 index 0000000000000..f470906641d61 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart4-m0.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart4>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart4m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart4-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart4-m2.dts new file mode 100644 index 0000000000000..a371018ef5853 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart4-m2.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart4>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart4m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart6-m1-full.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart6-m1-full.dts new file mode 100644 index 0000000000000..ebfa1c4596087 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart6-m1-full.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART6-M1 with Hardware Follow Control"; + compatible = "unknown"; + category = "misc"; + exclusive = "GPIO1_A1", "GPIO1_A0", "GPIO1_A2", "GPIO1_A3"; + description = "Enable UART6-M1 with hardware follow control.\nOn Radxa ROCK 5A this is CTSN pin 24, RTSN pin 23, TX pin 19, and RX pin 21."; + }; + + fragment@0 { + target = <&uart6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart6-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart6-m1.dts new file mode 100644 index 0000000000000..46cea59e9fee2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart6-m1.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart6>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart6m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m1-full.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m1-full.dts new file mode 100644 index 0000000000000..c6c708228d552 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m1-full.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART7-M1 with Hardware Flow Control"; + compatible = "unknown"; + category = "misc"; + exclusive = "GPIO3_C3", "GPIO3_C1", "GPIO3_C0", "GPIO3_C2"; + description = "Enable UART7-M1 with hardware flow control.\nOn Radxa ROCK 5B this is CTSN pin 7, RTSN pin 32, RX pin 11, and TX pin 15."; + }; + + fragment@0 { + target = <&uart7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn &uart7m1_rtsn>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m1.dts new file mode 100644 index 0000000000000..99774bdefc061 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m1.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART7-M1"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_C1", "GPIO3_C0"; + description = "Enable UART7-M1.\nOn Radxa ROCK 5B this is RX pin 11 and TX pin 15."; + }; + + fragment@0 { + target = <&uart7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart7m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m2.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m2.dts new file mode 100644 index 0000000000000..d2d8b65e7323f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart7-m2.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART7-M2"; + compatible = "radxa,rock-5a", "radxa,rock-5b"; + category = "misc"; + exclusive= "GPIO1_B5", "GPIO1_B4"; + description = "Enable UART7-M2.\nOn Radxa ROCK 5A this is TX pin 22 and RX pin 33.\nOn Radxa ROCK 5B this is TX pin 26 and this RX pin 24."; + }; + + fragment@0 { + target = <&uart7>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart7m2_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m0-full.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m0-full.dts new file mode 100644 index 0000000000000..affe168592dab --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m0-full.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART8-M0 with Hardware Follow Control"; + compatible = "unknown"; + category = "misc"; + exclusive = "GPIO4_B3", "GPIO4_B2", "GPIO4_B0", "GPIO4_B1"; + description = "Enable UART8-M0 with hardware follow control.\nOn Radxa ROCK 5A this is CTSN pin 11, RTSN pin 13, TX pin 32, and RX pin 40."; + }; + + fragment@0 { + target = <&uart8>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m0.dts new file mode 100644 index 0000000000000..9d7135aca21f6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m0.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART8-M0"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive= "GPIO4_B0", "GPIO4_B1"; + description = "Enable UART8-M0.\nOn Radxa ROCK 5A this is TX pin 32 and RX pin 40."; + }; + + fragment@0 { + target = <&uart8>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart8m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m1.dts new file mode 100644 index 0000000000000..e1b3b3a38b279 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-uart8-m1.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&uart8>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&uart8m1_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-w1-gpio3-b3.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-w1-gpio3-b3.dts new file mode 100644 index 0000000000000..70633677273cd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-w1-gpio3-b3.dts @@ -0,0 +1,27 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title = "Enable 1-Wire on GPIO3_B3"; + compatible = "radxa,rock-5b"; + category = "misc"; + exclusive = "GPIO3_B3"; + description = "Enable 1-Wire on GPIO3_B3.\nOn Radxa ROCK 5B this is pin 40."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + w1: onewire@0 { + compatible = "w1-gpio"; + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-w1-gpio4-b1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-w1-gpio4-b1.dts new file mode 100644 index 0000000000000..40f1fd04d1c16 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-w1-gpio4-b1.dts @@ -0,0 +1,27 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title = "Enable 1-Wire on GPIO4_B1"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "GPIO4_B1"; + description = "Enable 1-Wire on GPIO4_B1.\nOn Radxa ROCK 5A this is pin 40."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + w1: onewire@0 { + compatible = "w1-gpio"; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588s-roc-pc-sata0.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588s-roc-pc-sata0.dts new file mode 100644 index 0000000000000..e67d041af885d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588s-roc-pc-sata0.dts @@ -0,0 +1,36 @@ +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target = <&sata0>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sata_reset>; + }; + }; + + fragment@1 { + target = <&pcie2x1l2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&pinctrl>; + + __overlay__ { + sata { + sata_reset:sata-reset{ + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-3a-sata.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-3a-sata.dts new file mode 100644 index 0000000000000..dedb6065581f8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-3a-sata.dts @@ -0,0 +1,27 @@ +// ROCK 3A Pcie M.2 to sata +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable SATA2"; + compatible = "radxa,rock-3a"; + category = "misc"; + description = "Enable SATA2. +When SATA2 is enabled, PCIe cannot be enabled on the same port."; + }; + + fragment@0 { + target = <&pcie2x1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&sata2>; + __overlay__ { + status = "okay"; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts new file mode 100644 index 0000000000000..94744af220076 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-enable-sharp-lq133t1jw01-edp-lcd-disable-dp1.dts @@ -0,0 +1,222 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable Sharp LQ133T1JW01 Display on eDP"; + compatible = "radxa,rock-5-itx"; + category = "display"; + exclusive = "dp1", "edp0", "vp2"; + description = "Enable Sharp LQ133T1JW01 display on eDP.\nThis will disable DP1."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_edp0: backlight-edp0 { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm8 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_lcd_edp0: vcc3v3-lcd-edp0 { + status = "okay"; + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "vcc3v3_lcd_edp0"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + edp0_panel: edp0-panel { + status = "okay"; + compatible = "simple-panel"; + backlight = <&backlight_edp0>; + power-supply = <&vcc3v3_lcd_edp0>; + pinctrl-names = "default"; + prepare-delay-ms = <100>; + enable-delay-ms = <100>; + bpc = <8>; + width-mm = <305>; + height-mm = <107>; + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <241500000>; + hactive = <2560>; + vactive = <1440>; + hfront-porch = <80>; + hsync-len = <32>; + hback-porch = <48>; + vfront-porch = <31>; + vsync-len = <5>; + vback-porch = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&pwm8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + + }; + }; + + fragment@2 { + target = <&edp0>; + + __overlay__ { + force-hpd; + disable-audio; + status = "okay"; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&hdptxphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&edp0_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&edp0_in_vp0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&edp0_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&route_edp0>; + + __overlay__ { + status = "okay"; + connect = <&vp2_out_edp0>; + }; + }; + + fragment@8 { + target = <&dp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@9 { + target = <&dp1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@10 { + target = <&route_dp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&dp1_sound>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam0.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam0.dts new file mode 100644 index 0000000000000..60772887e009b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam0.dts @@ -0,0 +1,208 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM0"; + compatible = "radxa,rock-5-itx"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 4K on CAM0."; + }; + + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415_0: imx415-0@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam1.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam1.dts new file mode 100644 index 0000000000000..27bfcc581377d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-camera-4k-on-cam1.dts @@ -0,0 +1,209 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM1"; + compatible = "radxa,rock-5-itx"; + category = "camera"; + exclusive = "csi2_dphy3"; + description = "Enable Radxa Camera 4K on CAM1."; + }; + + fragment@0 { + target = <&i2c7>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415_1: imx415-1@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out1: endpoint { + remote-endpoint = <&mipidphy1_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy1_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + /* dphy1 full mode */ + target = <&csi2_dphy3>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy1_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input_1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi4_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output_1: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in1>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds4>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi4_in1: endpoint { + remote-endpoint = <&mipi4_csi2_output_1>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds4_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi4_lvds2_sditf_1: endpoint { + remote-endpoint = <&isp1_vir2>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp1_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp1_vir2>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds2_sditf_1>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd0.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd0.dts new file mode 100644 index 0000000000000..d94afb23e5cbd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd0.dts @@ -0,0 +1,219 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD on LCD0"; + compatible = "radxa,rock-5-itx"; + category = "display"; + exclusive = "dsi0", "vp3"; + description = "Enable Radxa Display 8HD on LCD0."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi0_backlight: dsi0-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + backlight = <&dsi0_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi0-lcd { + dsi0_lcd_rst_gpio: dsi0-lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi0_backlight_en: dsi0-backlight-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd1.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd1.dts new file mode 100644 index 0000000000000..555b9b909d030 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5-itx-radxa-display-8hd-on-lcd1.dts @@ -0,0 +1,219 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD on LCD1"; + compatible = "radxa,rock-5-itx"; + category = "display"; + exclusive = "dsi1", "vp3"; + description = "Enable Radxa Display 8HD on LCD1."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c8>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m4_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-hdmi-8k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-hdmi-8k.dts new file mode 100644 index 0000000000000..5337d42112b5e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-hdmi-8k.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; +#include + +/ { + metadata { + title ="Enable 8K output on ROCK 5A"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "display"; + description = "Enable 8K output on ROCK 5A"; + }; + + fragment@0 { + target = <&vop>; + + __overlay__ { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-i2c5-rtc-hym8563.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-i2c5-rtc-hym8563.dts new file mode 100644 index 0000000000000..e4fedcd48381b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-i2c5-rtc-hym8563.dts @@ -0,0 +1,51 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable RTC Hym8563 on I2C-5 bus on ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "misc"; + description = "Enable RTC Hym8563 on I2C-5 bus on ROCK 5A"; + }; + + fragment@0 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + }; + }; + }; + + fragment@1 { + target = <&pinctrl>; + + __overlay__ { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-camera-4k.dts new file mode 100644 index 0000000000000..3663dfd37b5be --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-camera-4k.dts @@ -0,0 +1,208 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K"; + compatible = "radxa,rock-5a"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 4K."; + }; + + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10fhd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10fhd.dts new file mode 100644 index 0000000000000..7b08042e9cb55 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10fhd.dts @@ -0,0 +1,85 @@ +// ROCK 5A Radxa Display 10FHD +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable Radxa Display 10FHD"; + compatible = "unknown"; + category = "display"; + exclusive = "dsi0"; + description = "Enable Radxa Display 10FHD."; + }; + + fragment@0 { + target = <&vcc_lcd_mipi0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&dsi0_backlight>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&pwm10>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi0_panel>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10hd.dts new file mode 100644 index 0000000000000..23add70801992 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-10hd.dts @@ -0,0 +1,228 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 10HD"; + compatible = "radxa,rock-5a"; + category = "display"; + exclusive = "dsi0"; + description = "Enable Radxa Display 10HD."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_tp: vcc-tp { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_tp"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + enable-active-low; + regulator-boot-on; + regulator-always-on; + }; + + vcc_lcd_mipi0: vcc-lcd-mipi0 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi0"; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi0_backlight: dsi0-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm10 0 25000 0>; + brightness-levels = < + 255 254 253 252 251 250 249 248 + 247 246 245 244 243 242 241 240 + 239 238 237 236 235 234 233 232 + 231 230 229 228 227 226 225 224 + 223 222 221 220 219 218 217 216 + 215 214 213 212 211 210 209 208 + 207 206 205 204 203 202 201 200 + 199 198 197 196 195 194 193 192 + 191 190 189 188 187 186 185 184 + 183 182 181 180 179 178 177 176 + 175 174 173 172 171 170 169 168 + 167 166 165 164 163 162 161 160 + 159 158 157 156 155 154 153 152 + 151 150 149 148 147 146 145 144 + 143 142 141 140 139 138 137 136 + 135 134 133 132 131 130 129 128 + 127 126 125 124 123 122 121 120 + 119 118 117 116 115 114 113 112 + 111 110 109 108 107 106 105 104 + 103 102 101 100 99 98 97 96 + 95 94 93 92 91 90 89 88 + 87 86 85 84 83 82 81 80 + 79 78 77 76 75 74 73 72 + 71 70 69 68 67 66 65 64 + 63 62 61 60 59 58 57 56 + 55 54 53 52 51 50 49 48 + 47 46 45 44 43 42 41 40 + 39 38 38 37 37 36 36 35 + 35 34 34 33 33 32 32 31 + 31 30 30 29 29 28 28 27 + 27 26 26 25 25 24 24 23 + 23 22 22 21 21 20 20 0 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm10>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-10hd-ad001"; + reg = <0>; + backlight = <&dsi0_backlight>; + + vdd-supply = <&vcc_lcd_mipi0>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech: focaltech@38 { + status = "okay"; + compatible = "focaltech,fts"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&focaltech_gpio>; + focaltech,irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + focaltech,display-coords = <0 0 799 1279>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi0-lcd { + dsi0_lcd_rst_gpio: dsi0-lcd-rst-gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi0_backlight_en: dsi0-backlight-en { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + focaltech { + focaltech_gpio: focaltech-gpio { + rockchip,pins = + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-8hd.dts new file mode 100644 index 0000000000000..76f86ef7a4931 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-radxa-display-8hd.dts @@ -0,0 +1,231 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD"; + compatible = "radxa,rock-5a"; + category = "display"; + exclusive = "dsi0"; + description = "Enable Radxa Display 8HD."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_tp: vcc-tp { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_tp"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + enable-active-low; + regulator-boot-on; + regulator-always-on; + }; + + vcc_lcd_mipi0: vcc-lcd-mipi0 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi0"; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi0_backlight: dsi0-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm10 0 25000 0>; + brightness-levels = < + 255 254 253 252 251 250 249 248 + 247 246 245 244 243 242 241 240 + 239 238 237 236 235 234 233 232 + 231 230 229 228 227 226 225 224 + 223 222 221 220 219 218 217 216 + 215 214 213 212 211 210 209 208 + 207 206 205 204 203 202 201 200 + 199 198 197 196 195 194 193 192 + 191 190 189 188 187 186 185 184 + 183 182 181 180 179 178 177 176 + 175 174 173 172 171 170 169 168 + 167 166 165 164 163 162 161 160 + 159 158 157 156 155 154 153 152 + 151 150 149 148 147 146 145 144 + 143 142 141 140 139 138 137 136 + 135 134 133 132 131 130 129 128 + 127 126 125 124 123 122 121 120 + 119 118 117 116 115 114 113 112 + 111 110 109 108 107 106 105 104 + 103 102 101 100 99 98 97 96 + 95 94 93 92 91 90 89 88 + 87 86 85 84 83 82 81 80 + 79 78 77 76 75 74 73 72 + 71 70 69 68 67 66 65 64 + 63 62 61 60 59 58 57 56 + 55 54 53 52 51 50 49 48 + 47 46 45 44 43 42 41 40 + 39 38 38 37 37 36 36 35 + 35 34 34 33 33 32 32 31 + 31 30 30 29 29 28 28 27 + 27 26 26 25 25 24 24 23 + 23 22 22 21 21 20 20 0 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm10>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible ="radxa,display-8hd"; + reg = <0>; + backlight = <&dsi0_backlight>; + + vdd-supply = <&vcc_lcd_mipi0>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_tp>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi0-lcd { + dsi0_lcd_rst_gpio: dsi0-lcd-rst-gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi0_backlight_en: dsi0-backlight-en { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-rpi-camera-v2.dts new file mode 100644 index 0000000000000..fc869c97f34d0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-rpi-camera-v2.dts @@ -0,0 +1,237 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2"; + compatible = "radxa,rock-5a"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Raspberry Pi Camera V2."; + }; + + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-sata.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-sata.dts new file mode 100644 index 0000000000000..6239c1f69b7d3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-sata.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + + metadata { + title = "Enable SATA0"; + compatible = "radxa,rock-5a"; + category = "misc"; + exclusive = "combphy0_ps"; + description = "Enable SATA0.\nWhen SATA0 is enabled, PCIe cannot be enabled on the same port."; + }; + + fragment@0 { + target = <&pcie2x1l2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&sata0>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-spi-nor-flash.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-spi-nor-flash.dts new file mode 100644 index 0000000000000..6d7723747a82a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-spi-nor-flash.dts @@ -0,0 +1,54 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Enable SPI Nor Flash on ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "misc"; + description = "Enable SPI Nor Flash on ROCK 5A"; + }; + + fragment@0 { + target = <&sfc>; + + __overlay__ { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&sdhci>; + + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5a-usb-otg.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-usb-otg.dts new file mode 100644 index 0000000000000..50ce0dd7e2142 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5a-usb-otg.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Set Type-A OTG port in OTG mode for ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + category = "misc"; + description = "Set Type-A OTG port in OTG mode for ROCK 5A"; + }; + + fragment@0 { + target = <&usbdrd_dwc3_0>; + + __overlay__ { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi1-8k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi1-8k.dts new file mode 100644 index 0000000000000..5d2efa8857e97 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi1-8k.dts @@ -0,0 +1,63 @@ +/dts-v1/; +/plugin/; +#include + +/ { + metadata { + title = "Enable 8K output on HDMI1"; + compatible = "radxa,rock-5b"; + category = "display"; + description = "Enable 8K output on HDMI1.\n8K cannot be enabled on HDMI1 and HDMI2 at the same time."; + }; + + fragment@0 { + target = <&route_hdmi1>; + + __overlay__ { + connect = <&vp2_out_hdmi1>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&hdmi1_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&hdmi1_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&route_hdmi0>; + + __overlay__ { + connect = <&vp0_out_hdmi0>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi0_in_vp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&vop>; + + __overlay__ { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi2-8k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi2-8k.dts new file mode 100644 index 0000000000000..f3f411a179586 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-hdmi2-8k.dts @@ -0,0 +1,79 @@ +/dts-v1/; +/plugin/; +#include + +/ { + metadata { + title = "Enable 8K output on HDMI2"; + compatible = "radxa,rock-5b"; + category = "display"; + description = "Enable 8K output on HDMI2.\n8K cannot be enabled on HDMI1 and HDMI2 at the same time."; + }; + + fragment@0 { + target = <&route_hdmi1>; + + __overlay__ { + connect = <&vp0_out_hdmi1>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&hdmi1_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&hdmi1_in_vp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&route_hdmi0>; + + __overlay__ { + connect = <&vp2_out_hdmi0>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi0_in_vp2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&hdmi0_in_vp1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&hdmi0_in_vp0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&vop>; + + __overlay__ { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-pd-max-voltage-12v.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-pd-max-voltage-12v.dts new file mode 100644 index 0000000000000..5ebf037028204 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-pd-max-voltage-12v.dts @@ -0,0 +1,24 @@ +/dts-v1/; +/plugin/; + +#include "dt-bindings/usb/pd.h" + +/ { + metadata { + title ="Power Supply PD 12V on ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + category = "misc"; + description = "Power Supply PD 12V on ROCK 5B."; + }; + + fragment@0 { + target = <&usb_con>; + + __overlay__ { + sink-pdos = + ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-4k.dts new file mode 100644 index 0000000000000..9a6cf7bce2c18 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-4k.dts @@ -0,0 +1,208 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K"; + compatible = "radxa,rock-5b"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 4K."; + }; + + fragment@0 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10fhd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10fhd.dts new file mode 100644 index 0000000000000..99873cf515540 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10fhd.dts @@ -0,0 +1,85 @@ +// ROCK 5B Radxa Display 10FHD +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable Radxa Display 10FHD"; + compatible = "unknown"; + category = "display"; + exclusive = "dsi1"; + description = "Enable Radxa Display 10FHD."; + }; + + fragment@0 { + target = <&vcc_lcd_mipi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&dsi1_backlight>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&dsi1_panel>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10hd.dts new file mode 100644 index 0000000000000..30eb5c9688afc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-10hd.dts @@ -0,0 +1,221 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 10HD"; + compatible = "radxa,rock-5b"; + category = "display"; + exclusive = "dsi1"; + description = "Enable Radxa Display 10HD."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 255 254 253 252 251 250 249 248 + 247 246 245 244 243 242 241 240 + 239 238 237 236 235 234 233 232 + 231 230 229 228 227 226 225 224 + 223 222 221 220 219 218 217 216 + 215 214 213 212 211 210 209 208 + 207 206 205 204 203 202 201 200 + 199 198 197 196 195 194 193 192 + 191 190 189 188 187 186 185 184 + 183 182 181 180 179 178 177 176 + 175 174 173 172 171 170 169 168 + 167 166 165 164 163 162 161 160 + 159 158 157 156 155 154 153 152 + 151 150 149 148 147 146 145 144 + 143 142 141 140 139 138 137 136 + 135 134 133 132 131 130 129 128 + 127 126 125 124 123 122 121 120 + 119 118 117 116 115 114 113 112 + 111 110 109 108 107 106 105 104 + 103 102 101 100 99 98 97 96 + 95 94 93 92 91 90 89 88 + 87 86 85 84 83 82 81 80 + 79 78 77 76 75 74 73 72 + 71 70 69 68 67 66 65 64 + 63 62 61 60 59 58 57 56 + 55 54 53 52 51 50 49 48 + 47 46 45 44 43 42 41 40 + 39 38 38 37 37 36 36 35 + 35 34 34 33 33 32 32 31 + 31 30 30 29 29 28 28 27 + 27 26 26 25 25 24 24 23 + 23 22 22 21 21 20 20 0 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "chongzhou,cz101b4001"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech: focaltech@38 { + status = "okay"; + compatible = "focaltech,fts"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&focaltech_gpio>; + focaltech,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + focaltech,display-coords = <0 0 799 1279>; + }; + }; + }; + + + + + fragment@5 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + focaltech { + focaltech_gpio: focaltech-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-8hd.dts new file mode 100644 index 0000000000000..da2226353355f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-display-8hd.dts @@ -0,0 +1,219 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD"; + compatible = "radxa,rock-5b"; + category = "display"; + exclusive = "dsi1"; + description = "Enable Radxa Display 8HD."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 255 254 253 252 251 250 249 248 + 247 246 245 244 243 242 241 240 + 239 238 237 236 235 234 233 232 + 231 230 229 228 227 226 225 224 + 223 222 221 220 219 218 217 216 + 215 214 213 212 211 210 209 208 + 207 206 205 204 203 202 201 200 + 199 198 197 196 195 194 193 192 + 191 190 189 188 187 186 185 184 + 183 182 181 180 179 178 177 176 + 175 174 173 172 171 170 169 168 + 167 166 165 164 163 162 161 160 + 159 158 157 156 155 154 153 152 + 151 150 149 148 147 146 145 144 + 143 142 141 140 139 138 137 136 + 135 134 133 132 131 130 129 128 + 127 126 125 124 123 122 121 120 + 119 118 117 116 115 114 113 112 + 111 110 109 108 107 106 105 104 + 103 102 101 100 99 98 97 96 + 95 94 93 92 91 90 89 88 + 87 86 85 84 83 82 81 80 + 79 78 77 76 75 74 73 72 + 71 70 69 68 67 66 65 64 + 63 62 61 60 59 58 57 56 + 55 54 53 52 51 50 49 48 + 47 46 45 44 43 42 41 40 + 39 38 38 37 37 36 36 35 + 35 34 34 33 33 32 32 31 + 31 30 30 29 29 28 28 27 + 27 26 26 25 25 24 24 23 + 23 22 22 21 21 20 20 0 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; + }; + }; + + fragment@1 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&mipi_dcphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi1>; + }; + }; + + fragment@5 { + target = <&dsi1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&dsi1_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c6>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v2.dts new file mode 100644 index 0000000000000..1a3eb8d6ee249 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v2.dts @@ -0,0 +1,237 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2"; + compatible = "radxa,rock-5b"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Raspberry Pi Camera V2."; + }; + + + fragment@0 { + target-path = "/"; + + __overlay__ { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@7 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@8 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; + + fragment@12 { + target = <&pinctrl>; + + __overlay__ { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-sata.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-sata.dts new file mode 100644 index 0000000000000..8020aa511b356 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-sata.dts @@ -0,0 +1,44 @@ +// ROCK 5B Pcie M.2 to sata +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable SATA1"; + compatible = "radxa,rock-5b"; + category = "misc"; + description = "Enable SATA1.\nWhen SATA1 is enabled, PCIe cannot be enabled on the same port."; + }; + + fragment@0 { + target = <&wifi_disable>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&bt_wake>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&pcie2x1l0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&sata1>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-opp-oc-24ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-opp-oc-24ghz.dts new file mode 100644 index 0000000000000..d329e22a3f612 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-opp-oc-24ghz.dts @@ -0,0 +1,355 @@ +// RK3588 CPU Overclock to 2.4 GHz + +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Overclock Big Cores to 2.4 GHz on RK3588/RK3588S boards"; + compatible = "rockchip,rk3588"; + category = "misc"; + description = "Overclock Big Cores to 2.4 GHz on RK3588/RK3588S boards"; + }; + + fragment@0 { + target = <&cluster1_opp_table>; + __overlay__ { + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L2 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L3 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L4 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L5 = <687500 687500 1050000>, + <687500 687500 1050000>; + opp-microvolt-L6 = <675000 675000 1050000>, + <675000 675000 1050000>; + opp-microvolt-L7 = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1050000>, + <762500 762500 1050000>; + opp-microvolt-L2 = <750000 750000 1050000>, + <750000 750000 1050000>; + opp-microvolt-L3 = <737500 737500 1050000>, + <737500 737500 1050000>; + opp-microvolt-L4 = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L5 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L6 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L7 = <700000 700000 1050000>, + <700000 700000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L1 = <837500 837500 1050000>, + <837500 837500 1050000>; + opp-microvolt-L2 = <825000 825000 1050000>, + <825000 825000 1050000>; + opp-microvolt-L3 = <812500 812500 1050000>, + <812500 812500 1050000>; + opp-microvolt-L4 = <800000 800000 1050000>, + <800000 800000 1050000>; + opp-microvolt-L5 = <787500 787500 1050000>, + <787500 787500 1050000>; + opp-microvolt-L6 = <775000 775000 1050000>, + <775000 775000 1050000>; + opp-microvolt-L7 = <762500 762500 1050000>, + <762500 762500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L1 = <912500 912500 1050000>, + <912500 912500 1050000>; + opp-microvolt-L2 = <900000 900000 1050000>, + <900000 900000 1050000>; + opp-microvolt-L3 = <887500 887500 1050000>, + <887500 887500 1050000>; + opp-microvolt-L4 = <875000 875000 1050000>, + <875000 875000 1050000>; + opp-microvolt-L5 = <862500 862500 1050000>, + <862500 862500 1050000>; + opp-microvolt-L6 = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L7 = <837500 837500 1050000>, + <837500 837500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1050000>, + <987500 987500 1050000>; + opp-microvolt-L1 = <975000 975000 1050000>, + <975000 975000 1050000>; + opp-microvolt-L2 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L3 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L4 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L5 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L6 = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L7 = <912500 912500 1050000>, + <912500 912500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1050000>, + <1000000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1030000 1000000 1050000>, + <1030000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1040000 1010000 1050000>, + <1040000 1010000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1050000 1020000 1050000>, + <1050000 1020000 1050000>; + clock-latency-ns = <40000>; + }; + }; + }; + + fragment@1 { + target = <&cluster2_opp_table>; + __overlay__ { + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L2 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L3 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L4 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L5 = <687500 687500 1050000>, + <687500 687500 1050000>; + opp-microvolt-L6 = <675000 675000 1050000>, + <675000 675000 1050000>; + opp-microvolt-L7 = <675000 675000 1050000>, + <675000 675000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1050000>, + <762500 762500 1050000>; + opp-microvolt-L2 = <750000 750000 1050000>, + <750000 750000 1050000>; + opp-microvolt-L3 = <737500 737500 1050000>, + <737500 737500 1050000>; + opp-microvolt-L4 = <725000 725000 1050000>, + <725000 725000 1050000>; + opp-microvolt-L5 = <712500 712500 1050000>, + <712500 712500 1050000>; + opp-microvolt-L6 = <700000 700000 1050000>, + <700000 700000 1050000>; + opp-microvolt-L7 = <700000 700000 1050000>, + <700000 700000 1050000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L1 = <837500 837500 1050000>, + <837500 837500 1050000>; + opp-microvolt-L2 = <825000 825000 1050000>, + <825000 825000 1050000>; + opp-microvolt-L3 = <812500 812500 1050000>, + <812500 812500 1050000>; + opp-microvolt-L4 = <800000 800000 1050000>, + <800000 800000 1050000>; + opp-microvolt-L5 = <787500 787500 1050000>, + <787500 787500 1050000>; + opp-microvolt-L6 = <775000 775000 1050000>, + <775000 775000 1050000>; + opp-microvolt-L7 = <762500 762500 1050000>, + <762500 762500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L1 = <912500 912500 1050000>, + <912500 912500 1050000>; + opp-microvolt-L2 = <900000 900000 1050000>, + <900000 900000 1050000>; + opp-microvolt-L3 = <887500 887500 1050000>, + <887500 887500 1050000>; + opp-microvolt-L4 = <875000 875000 1050000>, + <875000 875000 1050000>; + opp-microvolt-L5 = <862500 862500 1050000>, + <862500 862500 1050000>; + opp-microvolt-L6 = <850000 850000 1050000>, + <850000 850000 1050000>; + opp-microvolt-L7 = <837500 837500 1050000>, + <837500 837500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1050000>, + <987500 987500 1050000>; + opp-microvolt-L1 = <975000 975000 1050000>, + <975000 975000 1050000>; + opp-microvolt-L2 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L3 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L4 = <962500 962500 1050000>, + <962500 962500 1050000>; + opp-microvolt-L5 = <950000 950000 1050000>, + <950000 950000 1050000>; + opp-microvolt-L6 = <925000 925000 1050000>, + <925000 925000 1050000>; + opp-microvolt-L7 = <912500 912500 1050000>, + <912500 912500 1050000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1050000>, + <1000000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1030000 1000000 1050000>, + <1030000 1000000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1040000 1010000 1050000>, + <1040000 1010000 1050000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1050000 1020000 1050000>, + <1050000 1020000 1050000>; + clock-latency-ns = <40000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-panthor-gpu.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-panthor-gpu.dts new file mode 100644 index 0000000000000..2da62dbb4a931 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3588-panthor-gpu.dts @@ -0,0 +1,19 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&gpu>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&gpu_panthor>; + __overlay__ { + status = "okay"; + mali-supply = <&vdd_gpu_s0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/turing-rk1-sata2.dts b/arch/arm64/boot/dts/rockchip/overlay/turing-rk1-sata2.dts new file mode 100644 index 0000000000000..c68e11dc16049 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/turing-rk1-sata2.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&pcie2x1l1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&sata2>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/yy3568-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/yy3568-camera.dts new file mode 100644 index 0000000000000..2ed2cc00ba5e4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/yy3568-camera.dts @@ -0,0 +1,183 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable YY3568 Camera"; + compatible = "youyeetoo,yy3568"; + }; + + fragment@0 { + target = <&csi2_dphy_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c4>; + + __overlay__ { + status = "okay"; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,grf = <&grf>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + status = "okay"; + + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + os04a10: os04a10@36 { + compatible = "ovti,os04a10"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + status = "okay"; + + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&rkisp>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkisp_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-dsi0.dts b/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-dsi0.dts new file mode 100644 index 0000000000000..e7c99e1b339ba --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-dsi0.dts @@ -0,0 +1,229 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable YY3568 DSI0"; + compatible = "youyeetoo,yy3568"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + + enable-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@1 { + target = <&pwm4>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 80 ac + 15 00 02 81 b8 + 15 00 02 82 09 + 15 00 02 83 78 + 15 00 02 84 7f + 15 00 02 85 bb + 15 00 02 86 70 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi0>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&dsi0_in_vp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_RISING>; + reset-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + max-x = <1024>; + max-y = <600>; + tp-size = <911>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + tp-supply = <&vcc_3v3>; + status = "okay"; + }; + }; + }; + + fragment@5 { + target = <&video_phy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp1_out_dsi0>; + }; + }; + + fragment@7 { + target = <&dsi0_timing0>; + + __overlay__ { + clock-frequency = <51668640>; //DCLK + hactive = <1024>; //hactive + vactive = <600>; //vactive + hfront-porch = <160>; //hfp + hback-porch = <160>; //hbp + hsync-len = <10>; //hsa + vfront-porch = <12>; //vfp + vsync-len = <1>; //vsa + vback-porch = <23>; //vbp + hsync-active = <0>; //hync æžæ€§æŽ§åˆ¶ ç½® 1 å转æžæ€§ + vsync-active = <0>; //vsync æžæ€§æŽ§åˆ¶ ç½® 1 å转æžæ€§ + de-active = <1>; //DEN æžæ€§æŽ§åˆ¶ + pixelclk-active = <0>; //dclk æžæ€§æŽ§åˆ¶ + }; + }; + + fragment@8 { + target = <&disp_timings1>; + + __overlay__ { + native-mode = <&dsi0_timing0>; + }; + }; + + fragment@9 { + target = <&pinctrl>; + + __overlay__ { + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-dsi1.dts b/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-dsi1.dts new file mode 100644 index 0000000000000..8bab82cf8e451 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-dsi1.dts @@ -0,0 +1,229 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable YY3568 DSI1"; + compatible = "youyeetoo,yy3568"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_1: backlight-1 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + + enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@1 { + target = <&pwm5>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight_1>; + + enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 80 ac + 15 00 02 81 b8 + 15 00 02 82 09 + 15 00 02 83 78 + 15 00 02 84 7f + 15 00 02 85 bb + 15 00 02 86 70 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&dsi1_in_vp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + gt9xxdsi: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio0 RK_PC1 IRQ_TYPE_EDGE_RISING>; + reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + max-x = <1024>; + max-y = <600>; + tp-size = <911>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + tp-supply = <&vcc_3v3>; + status = "okay"; + }; + }; + }; + + fragment@5 { + target = <&video_phy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp1_out_dsi1>; + }; + }; + + fragment@7 { + target = <&dsi1_timing0>; + + __overlay__ { + clock-frequency = <65000000>; //DCLK + hactive = <1024>; //hactive + vactive = <600>; //vactive + hfront-porch = <160>; //hfp + hback-porch = <160>; //hbp + hsync-len = <10>; //hsa + vfront-porch = <12>; //vfp + vsync-len = <1>; //vsa + vback-porch = <23>; //vbp + hsync-active = <0>; //hync æžæ€§æŽ§åˆ¶ ç½® 1 å转æžæ€§ + vsync-active = <0>; //vsync æžæ€§æŽ§åˆ¶ ç½® 1 å转æžæ€§ + de-active = <1>; //DEN æžæ€§æŽ§åˆ¶ + pixelclk-active = <0>; //dclk æžæ€§æŽ§åˆ¶ + }; + }; + + fragment@8 { + target = <&disp_timings1>; + + __overlay__ { + native-mode = <&dsi1_timing0>; + }; + }; + + fragment@9 { + target = <&pinctrl>; + + __overlay__ { + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-edp.dts b/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-edp.dts new file mode 100644 index 0000000000000..1db0bf785431d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/yy3568-display-edp.dts @@ -0,0 +1,189 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title ="Enable YY3568 eDP"; + compatible = "youyeetoo,yy3568"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_2: backlight-2 { + compatible = "pwm-backlight"; + pwms = <&pwm14 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + + enable-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + edp-panel { + compatible = "simple-panel"; + backlight = <&backlight_2>; + //power-supply = <&vcc3v3_lcd0_n>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + + display-timings { + native-mode = <&edp_timing>; + + edp_timing: timing0 { + clock-frequency = <138500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <64>; + hsync-len = <32>; + hback-porch = <64>; + vfront-porch = <12>; + vsync-len = <7>; + vback-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&pwm14>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&edp>; + + __overlay__ { + force-hpd; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&edp_phy>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&edp_in_vp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&route_edp>; + + __overlay__ { + connect = <&vp1_out_edp>; + status = "okay"; + }; + }; + + fragment@6 { + target = <&i2c1>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + gt9xxedp: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio0 RK_PB7 IRQ_TYPE_EDGE_RISING>; + reset-gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + max-x = <1920>; + max-y = <1080>; + tp-size = <928>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + tp-supply = <&vcc_3v3>; + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&pinctrl>; + + __overlay__ { + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/yy3568-sata2.dts b/arch/arm64/boot/dts/rockchip/overlay/yy3568-sata2.dts new file mode 100644 index 0000000000000..db5f362067f87 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/yy3568-sata2.dts @@ -0,0 +1,25 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title ="Enable YY3568 SATA Port"; + compatible = "youyeetoo,yy3568"; + }; + + fragment@0 { + target = <&pcie2x1>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&sata2>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts new file mode 100755 index 0000000000000..3189fb509909d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -0,0 +1,742 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model = "ArmSom Sige1"; + compatible = "armsom,sige1", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc; + mmc1 = &sdhci; + mmc2 = &sdio0; + }; + + + acodec_sound: acodec-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rk3528-acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + /omit-if-no-ref/ + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + /omit-if-no-ref/ + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_0v9_s3: vdd-0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8_s3: vdd-1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s3: vcc-3v3-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr_s3: vcc-ddr-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi"; + rockchip,cpu = <&sai3>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; + + vcc5v0_usb_host1: vcc5v0-usb-host1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host1"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host1_pwren>; + }; + + vcc5v0_usb_host2: vcc5v0-usb-host2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host2_pwren>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "rtl8852bs"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + led_green: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + led_red: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm6 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; +}; + +&avsd { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + // status = "okay"; + // rockchip,sleep-debug-en = <1>; + // rockchip,virtual-poweroff = <1>; + // rockchip,sleep-mode-config = < + // (0 + // | RKPM_SLP_ARMPD + // ) + // >; + // rockchip,wakeup-config = < + // (0 + // | RKPM_CPU0_WKUP_EN + // | RKPM_GPIO_WKUP_EN + // ) + // >; + // rockchip,pwm-regulator-config = < + // (0 + // | RKPM_PWM0_M0_REGULATOR_EN + // | RKPM_PWM1_M0_REGULATOR_EN + // ) + // >; +}; + +&sai3 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_s3>; +}; + +&sdhci { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&tve { + status = "disabled"; +}; + +&tve_in_vp1 { + status = "disabled"; +}; + + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn &uart2m1_rtsn>; + uart-has-rtscts; + bluetooth { + compatible = "brcm,bcm43438-bt"; + device-wakeup-gpios = <&gpio3 RK_PC3 0>; + host-wakeup-gpios = <&gpio1 RK_PC2 0>; + shutdown-gpios = <&gpio1 RK_PC1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vdd_1v8_s3>; + }; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x30>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus + ð_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + }; +}; + + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake: bt-host-wake { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host1_pwren: usb-host1-pwren { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host2_pwren: usb-host2-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_rgb_r: led-red-en { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_g: led-green-en { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6m2_pins>; +}; + +&acodec { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_sys>; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&vcc5v0_sys>; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + // Only USB2.0 START + extcon = <&usb2phy>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + // Only USB2.0 END + snps,usb2-lpm-disable; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi>; + }; + route_tve: route-tve { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_tve>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts new file mode 100644 index 0000000000000..ec7a841662684 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: flippy (flippy@sina.com) + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model = "Hinlink H28K"; + compatible = "hlink,h28k", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + ethernet1 = &pcie_eth; + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + + chosen: chosen{ + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyS0,1500000"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; + }; + + firmware: firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cmd: cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x2000000>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; + + adc_keys: adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_3v3_s3: vcc-3v3-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8_s3: vdd-1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr_s3: vcc-ddr-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_0v9_s3: vdd-0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1148000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "led-green", "led-amber", "led-blue"; + pinctrl-0 = <&led_green_en>, <&led_amber_en>, <&led_blue_en>; + + led_green: led-green { + label = "led_green"; + gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led_amber: led-amber { + label = "led_amber"; + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + }; + + led_blue: led-blue { + label = "led_blue"; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&reserved_memory { +}; + +&avsd { + status = "okay"; +}; + +&combphy_pu { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus>; + + phy-supply = <&vcc_3v3_s3>; + phy-handle = <&rgmii_phy>; + + phy-mode = "rgmii"; + clock_in_out = "output"; + tx_delay = <0x36>; + rx_delay = <0x2b>; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&display_subsystem { + status = "disabled"; + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi>; + }; + + route_tve: route-tve { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_tve>; + }; + }; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; + +&hdmiphy { + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM0_M0_REGULATOR_EN + | RKPM_PWM1_M0_REGULATOR_EN + ) + >; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_s3>; +}; + +&sdhci { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs200-1_8v; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <100000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy_host { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy_otg { + phy-supply = <&vcc5v0_sys>; + vbus-supply = <&vcc_3v3_s3>; + status = "disabled"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "disabled"; + dr_mode = "otg"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&pcie2x1 { + status = "okay"; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_rtl8111_isolate>; + + pcie@0,0 { + reg = <0x000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + pcie_eth: pcie-eth@10,0 { + compatible = "pci10ec,8168"; + reg = <0x000000 0 0 0 0>; + realtek,led-data = <0x0870>; + }; + }; +}; + +&pinctrl { + leds { + led_green_en: led-green-en { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + led_amber_en: led-amber-en { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + led_blue_en: led-blue-en { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_rtl8111_isolate: pcie-rtl8111-isolate { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-hinlink-ht2.dts b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-ht2.dts new file mode 100644 index 0000000000000..c3701ce8124ed --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-ht2.dts @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: hoochi + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model = "Hinlink HT2"; + compatible = "hinlink,ht2", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyS0,1500000"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; + }; + + firmware: firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cmd: cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x2000000>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; + + adc_keys: adc-keys { + status = "disabled"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_0v9_s3: vdd-0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8_s3: vdd-1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s3: vcc-3v3-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1148000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + /omit-if-no-ref/ + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + /omit-if-no-ref/ + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ddr_s3: vcc-ddr-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi0"; + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_host_wake_irq>; + pinctrl-1 = <&uart2m1_gpios>; + BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_green_en>, <&led_blue_en>; + + work { + label = "led_green"; + gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + wlan { + label = "led_blue"; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + +}; + +&avsd { + status = "okay"; +}; + +&combphy_pu { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi>; + }; + route_tve: route-tve { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_tve>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM0_M0_REGULATOR_EN + | RKPM_PWM1_M0_REGULATOR_EN + ) + >; +}; + +&sai3 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_s3>; +}; + +&sdhci { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&tve { + status = "disabled"; +}; + +&tve_in_vp1 { + status = "disabled"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "host"; + extcon = <&usb2phy>; + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x30>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + /*rockchip,default-sample-phase = <90>;*/ + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + /delete-property/ rockchip,use-v2-tuning; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>; +}; + +&pinctrl { + leds { + led_green_en: led-green-en { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_blue_en: led-blue-en { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart2m1_gpios: uart2m1-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_host_wake_irq: bt-host-wake-irq { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-mangopi-m28k.dts b/arch/arm64/boot/dts/rockchip/rk3528-mangopi-m28k.dts new file mode 100644 index 0000000000000..5ba8fd86a330a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-mangopi-m28k.dts @@ -0,0 +1,859 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: hoochi + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model = "MangoPi M28K"; + compatible = "mangopi,m28k", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyS0,1500000"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; + }; + + firmware: firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cmd: cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x2000000>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; + + adc_keys: adc-keys { + status = "disabled"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_0v9_s3: vdd-0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8_s3: vdd-1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s3: vcc-3v3-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1148000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + /omit-if-no-ref/ + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + /omit-if-no-ref/ + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ddr_s3: vcc-ddr-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi0"; + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_host_wake_irq>; + pinctrl-1 = <&uart2m1_gpios>; + BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_green_en>, <&led_amber_en>, <&led_blue_en>; + + work { + label = "led_green"; + gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + lan { + label = "led_amber"; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + wan { + label = "led_blue"; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + }; + +}; + +&avsd { + status = "okay"; +}; + +&combphy_pu { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu0_opp_table { + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1100000 1100000 1100000>; + opp-microvolt-L1 = <1100000 1100000 1100000>; + opp-microvolt-L2 = <1100000 1100000 1100000>; + opp-microvolt-L3 = <1100000 1100000 1100000>; + opp-microvolt-L4 = <1100000 1100000 1100000>; + opp-microvolt-L5 = <1100000 1100000 1100000>; + opp-microvolt-L6 = <1100000 1100000 1100000>; + opp-microvolt-L7 = <1100000 1100000 1100000>; + opp-microvolt-L8 = <1100000 1100000 1100000>; + opp-microvolt-L9 = <1100000 1100000 1100000>; + opp-microvolt-L10 = <1100000 1100000 1100000>; + opp-microvolt-L11 = <1100000 1100000 1100000>; + clock-latency-ns = <40000>; + }; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi>; + }; + route_tve: route-tve { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_tve>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +// interrupt-names = "gp", +// "gpmmu", +// "pp", +// "pp0", +// "ppmmu0", +// "pp1", +// "ppmmu1"; +// clocks = <&cru ACLK_GPU_MALI>, <&cru ACLK_GPU_MALI>; +// clock-names = "bus", "core"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM0_M0_REGULATOR_EN + | RKPM_PWM1_M0_REGULATOR_EN + ) + >; +}; + +&sai3 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_s3>; +}; + +&sdhci { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&tve { + status = "disabled"; +}; + +&tve_in_vp1 { + status = "disabled"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "host"; + extcon = <&usb2phy>; + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x30>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + /*rockchip,default-sample-phase = <90>;*/ + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + /delete-property/ rockchip,use-v2-tuning; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_csn1 &spi0_pins>; + num-cs = <2>; + + spi_dev@1 { + compatible = "rockchip,spidev"; + reg = <1>; + spi-max-frequency = <50000000>; + }; + +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + +}; + +&pcie2x1 { + status = "okay"; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_rtl8111_isolate>; + + pcie@0,0 { + reg = <0x000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + pcie_eth: pcie-eth@10,0 { + compatible = "pci10ec,8168"; + reg = <0x000000 0 0 0 0>; + realtek,led-data = <0x0870>; + }; + }; +}; + +&pinctrl { + leds { + led_green_en: led-green-en { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + led_amber_en: led-amber-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + led_blue_en: led-blue-en { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart2m1_gpios: uart2m1-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_host_wake_irq: bt-host-wake-irq { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_rtl8111_isolate: pcie-rtl8111-isolate { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts new file mode 100644 index 0000000000000..f05b65549f551 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" +#include "rk3528-linux.dtsi" + +/ { + model = "Radxa E20C"; + compatible = "radxa,e20c", "radxa,rock-2", "rockchip,rk3528a"; + + /delete-node/ chosen; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + mmc2 = &sdio0; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_0v9_s3: vdd-0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s3: vcc-3v3-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8_s3: vdd-1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ddr_s3: vcc-ddr-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_gpu: vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_key>; + autorepeat; + + user-key { + label = "KEY F15"; + linux,code = ; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + sys-led { + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + wan-led { + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + lan-led { + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM0_M0_REGULATOR_EN + | RKPM_PWM1_M0_REGULATOR_EN + ) + >; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_s3>; +}; + +&avsd { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x30>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&u2phy_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + extcon = <&usb2phy>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@0,0 { + reg = <0x000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + pcie_eth:pcie-eth@10,0 { + compatible = "pci10ec,8168"; + reg = <0x000000 0 0 0 0>; + realtek,led-data = <0x007f>; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + + eeprom: bl24c16@50 { + status = "okay"; + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + user_key: user-key { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index a8ff558a524f0..05d3127d36259 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1019,16 +1019,15 @@ , , ; - interrupt-names = "Mali_GP_IRQ", - "Mali_GP_MMU_IRQ", - "IRQPP", - "Mali_PP0_IRQ", - "Mali_PP0_MMU_IRQ", - "Mali_PP1_IRQ", - "Mali_PP1_MMU_IRQ"; - clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>, - <&cru PCLK_GPU_ROOT>; - clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu"; + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU_MALI>, <&cru ACLK_GPU_MALI>; + clock-names = "bus", "core"; assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <300000000>; power-domains = <&power RK3528_PD_GPU>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts new file mode 100644 index 0000000000000..425083407685f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts @@ -0,0 +1,1597 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + + /dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Firefly RK3566-ROC-PC HDMI(Linux)"; + compatible = "rockchip,rk3566-firefly-roc-pc", "rockchip,rk3566"; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + //hp-det-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + // pinctrl-names = "default"; + // pinctrl-0 = <&hp_det>; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_vbus_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery-key { + label = "F12"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_vga: vcc3v3-vga { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_vga"; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6356s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 0>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn + &bt_host_wake_gpio + &bt_poweren + &bt_host_wake_irq>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + flash_led: flash-led { + compatible = "led,rgb13h"; + label = "pwm-flash-led"; + led-max-microamp = <20000>; + flash-max-microamp = <20000>; + flash-max-timeout-us = <1000000>; + pwms = <&pwm11 0 25000 0>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + status = "disabled"; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + //gpio = <&pca9555 0 GPIO_ACTIVE_HIGH>; + gpio = <&pca9555 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_cam>; + regulator-name = "vcc_camera"; + enable-active-high; + status = "disabled"; + }; + + sd_vcc3v3_power: sd-vcc3v3-power { + status = "disabled"; + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_vcc3v3_power_en>; + regulator-name = "sd_vcc3v3_power_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + firefly_leds: leds { + compatible = "gpio-leds"; + power_led: power { + label = "firefly:blue:power"; + linux,default-trigger = "ir-power-click"; + default-state = "on"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_power>; + }; + + user_led: user { + label = "firefly:yellow:user"; + linux,default-trigger = "ir-user-click"; + default-state = "off"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_user>; + }; + }; + + test-power { + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default","spk_gpio"; + pinctrl-0 = <&i2s1m0_mclk>; + pinctrl-1 = <&spk_ctl_gpio>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + + capture-volume = <0>; + io-channels = <&saradc 4>; + hp-det-adc-value = <1000>; + spk-ctl-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + //vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&pinctrl { + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + spk_ctl_gpio: spk_ctl_gpio { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + cam { + vcc_cam: vcc-cam { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host_vbus_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd { + sd_vcc3v3_power_en: sd-vcc3v3-power-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_rts_gpio: uart1-rts-gpio { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_irq: bt-host-wake-irq { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + bt_host_wake_gpio: bt-host-wake-gpio { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + bt_poweren: bt-poweren { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_reset_gpio: pcie-reset-gpio { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { + led_power: led-power { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_user: led-user { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + +&i2c4 { + status = "okay"; + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "disabled"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,grf = <&grf>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + os04a10: os04a10@36 { + status = "disabled"; + compatible = "ovti,os04a10"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + ov5695: ov5695@36 { + status = "disabled"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c1 { + status = "disabled"; + clock-frequency = <100000>; + + pca9555: gpio@21 { + status = "disabled"; + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-group-num = <200>; + }; + + gt1x: gt1x@14 { + status = "disabled"; + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c5 { + status = "disabled"; + + mc3230: mc3230sensor@4c { + compatible = "gs_mc3230"; + reg = <0x4c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <4>; + status = "disabled"; + }; + + mxc6655xa: mxc6655xa@15 { + status = "disabled"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&rk809_codec { + pinctrl-0 = <&i2s1m0_mclk>; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&sata2 { + status = "disabled"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + status = "disabled"; +}; + +&spdif_8ch { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm1_tx>; +}; + +&uart3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&can1 { + status = "disabled"; + compatible = "rockchip,rk3568-can-2.0"; + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +&can2 { + status = "disabled"; + compatible = "rockchip,rk3568-can-2.0"; + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; +}; + +&spi1 { + status = "disabled"; + max-freq = <48000000>; + dev-port = <0>; + pinctrl-0 = <&spi1m1_pins>; + pinctrl-1 = <&spi1m1_pins_hs>; + + spi_wk2xxx: spi_wk2xxx@0{ + status = "disabled"; + compatible = "firefly,spi-wk2xxx"; + reg = <0x00>; + spi-max-frequency = <10000000>; + power-gpio = <&pca9555 15 GPIO_ACTIVE_HIGH>; + reset-gpio = <&pca9555 9 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio0 RK_PA6 IRQ_TYPE_EDGE_FALLING>; + cs-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + /* rk3399 driver support SPI_CPOL | SPI_CPHA | SPI_CS_HIGH */ + //spi-cpha; /* SPI mode: CPHA=1 */ + //spi-cpol; /* SPI mode: CPOL=1 */ + //spi-cs-high; + }; +}; + +&pwm7 { + status = "disabled"; + + compatible = "rockchip,remotectl-pwm"; + interrupts = ; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + + ir_key_firefly{ + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xeb KEY_POWER>, + <0xec KEY_MENU>, + <0xfe KEY_BACK>, + <0xb7 KEY_HOME>, + <0xa3 KEY_WWW>, + <0xf4 KEY_VOLUMEUP>, + <0xa7 KEY_VOLUMEDOWN>, + <0xf8 KEY_REPLY>, + <0xfc KEY_UP>, + <0xfd KEY_DOWN>, + <0xf1 KEY_LEFT>, + <0xe5 KEY_RIGHT>; + }; +}; + +&sfc{ + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + assigned-clock-rates = <50000000>; + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; +}; + +&lpddr4_params { + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1056>; +}; + +&lpddr4x_params { + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1056>; +}; + +&power { + pd_pipe@RK3568_PD_PIPE { + reg = ; + clocks = <&cru PCLK_PIPE>; + pm_qos = <&qos_pcie2x1>, + <&qos_sata1>, + <&qos_sata2>, + <&qos_usb3_0>, + <&qos_usb3_1>; + }; +}; + +&rkisp { + rockchip,iq-feature = /bits/ 64 <0x1BFBF7FE67FF>; +}; + +&usbdrd_dwc3 { + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&vcc5v0_otg { + status = "disabled"; +}; + +/* WiFi config */ +&sdmmc1 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +// iomux with GPIO2_B2(WIFI,host_wake_irq) +&uart8 { + status = "disabled"; +}; + +/* BT config */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + status = "okay"; +}; + +&rk809_codec { + io-channels = <&saradc 3>; + hp-det-adc-value = <941>; + hp_adc_drift_scope = <20>; + board-spk-from-hp; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_gpio>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "okay"; +}; + +&pcie30_3v3 { + status = "okay"; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; +}; + +&its { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout>; + + tx_delay = <0x4e>; + rx_delay = <0x2c>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&rgmii_phy1 { + led_status_value = <0x2f60>; +}; + +&i2c2 { + status = "okay"; +}; + +&csi2_dphy0{ + status="disabled"; +}; + +&csi2_dphy2{ + status = "disabled"; +}; + +&csi2_dphy1 { + status = "disabled"; + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ +}; + +&rk809 { + rtc { + status = "disabled"; + }; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-luckfox-core3566.dts b/arch/arm64/boot/dts/rockchip/rk3566-luckfox-core3566.dts new file mode 100755 index 0000000000000..47d6889b0cdcf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-luckfox-core3566.dts @@ -0,0 +1,910 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 luckfox technology Limited. + */ + + /dts-v1/; + + // #include "core3566-base.dtsi" + // #include "core3566-hdmi-screen.dtsi" + // #include "core3566-mipi-camera-imx219-cam0.dtsi" + // #include "core3566-mipi-camera-imx219-cam1.dtsi" + + #include "rk3566.dtsi" + + / { + compatible = "luckfox,core3566", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work{ + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + default-state = "on"; + }; + }; + + mcp251x_clk:mcp251x-clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + sc16is752_clk:sc16is752-clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sc16is752_clk"; + clock-frequency = <14745600>; + // 16000000 + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=tty1 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + // rockchip,serial-id = <7>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + // pinctrl-0 = <&uart7m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x1000000>; /* 100000 1M 0x20000000 512M A00000 10m at least 16m */ + alignment = <0x0 0x1000>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + /*"IN1P", "Mic Jack",*/ + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + &cpu0 { + cpu-supply = <&vdd_cpu>; + }; + + &dfi { + status = "okay"; + }; + + &dmc { + center-supply = <&vdd_logic>; + //ddr频率设置 + //status = "disabled"; + status = "okay"; + }; + + &rkcif { + status = "okay"; + }; + + &rkcif_mmu { + status = "okay"; + }; + + &rkisp { + status = "okay"; + }; + + &rkisp_mmu { + status = "okay"; + }; + + &gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; + }; + + // &pmu_io_domains { + // status = "okay"; + // pmuio1-supply = <&vcc3v3_pmu>; + // pmuio2-supply = <&VCC_GPIO18_45_3V3>; + // vccio1-supply = <&vccio_acodec>; + // vccio2-supply = <&vcca1v8_pmu>; + // vccio3-supply = <&vccio_sd>; + // vccio4-supply = <&VCC_GPIO0_17>; + // vccio5-supply = <&VCC_GPIO18_45_3V3>; + // vccio6-supply = <&VCC_GPIO0_17>; + // vccio7-supply = <&vcc_3v3>; + // }; + + &pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + }; + + &i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + // vcc1-supply = <&vcc_sys>; + // vcc2-supply = <&vcc_sys>; + // vcc3-supply = <&vcc_sys>; + // vcc4-supply = <&vcc_sys>; + // vcc5-supply = <&vcc_sys>; + // vcc6-supply = <&vcc_sys>; + // vcc7-supply = <&vcc_sys>; + // vcc8-supply = <&vcc3v3_sys>; + // vcc9-supply = <&vcc_sys>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + VCC_GPIO0_17: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_GPIO0_17"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + + avrman-spk-con-gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + avrman-hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; + }; + + &i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + }; + + &iep { + status = "okay"; + }; + + &iep_mmu { + status = "okay"; + }; + + &jpegd { + status = "okay"; + }; + + &jpegd_mmu { + status = "okay"; + }; + + &mpp_srv { + status = "okay"; + }; + + &rk_rga { + status = "okay"; + }; + + &rkvdec { + status = "okay"; + }; + + &rkvdec_mmu { + status = "okay"; + }; + + &rkvenc { + status = "okay"; + }; + + &rkvenc_mmu { + status = "okay"; + }; + + &bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "disabled"; + }; + + &rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_gpu>; + status = "disabled"; + }; + + &rknpu_mmu { + status = "disabled"; + }; + + &saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; + }; + + &sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + rockchip,txclk-tapnum = <0x8>; + max-frequency = <200000000>; + status = "okay"; + }; + + &uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + }; + + + &sfc { + status = "okay"; + }; + + &tsadc { + status = "okay"; + }; + + /////////// + + &u2phy0_otg { + status = "okay"; + }; + + &usb2phy0 { + status = "okay"; + }; + + &usb2phy1 { + status = "okay"; + }; + + &usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; + }; + + &usbdrd30 { + status = "okay"; + }; + + &pcie2x1 { + status = "disabled"; + }; + + &vdpu { + status = "okay"; + }; + + &vdpu_mmu { + status = "okay"; + }; + + &vepu { + status = "okay"; + }; + + &vepu_mmu { + status = "okay"; + }; + + &vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + }; + + &vop_mmu { + status = "okay"; + }; + + &reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + }; + + &rng { + status = "okay"; + }; + + &rockchip_suspend { + status = "okay"; + }; + + &pinctrl { + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + + &i2s0_8ch { + status = "okay"; + }; + + &display_subsystem { + status = "okay"; + }; + + // ======================================================================================================= + + + + + &sdmmc0 { + max-frequency = <150000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + supports-sd; + card-detect-delay = <800>; + ignore-pm-notify; + disable-wp; + sd-uhs-sdr50; + sd-uhs-sdr25; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; + }; + + &usbhost_dwc3 { + status = "okay"; + }; + + &usbhost30 { + status = "okay"; + }; + + &combphy1_usq { + status = "okay"; + }; + + &combphy2_psq { + status = "okay"; + }; + + &u2phy0_host { + status = "disabled"; + }; + + &u2phy1_otg { + status = "disabled"; + }; + + &u2phy1_host { + status = "disabled"; + }; + + &usb_host0_ehci { + status = "disabled"; + }; + + &usb_host0_ohci { + status = "disabled"; + }; + + &usb_host1_ehci { + status = "disabled"; + }; + + &usb_host1_ohci { + status = "disabled"; + }; + + &gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x40>; + rx_delay = <0x24>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; + }; + + &mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + }; + + &sdmmc1 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; + }; + + //PCIe + &pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; + }; + + + &hdmi { + status = "okay"; + luckfox,hot-plug-detect-invert; + }; + + &hdmi_in_vp0 { + status = "okay"; + }; + + &hdmi_in_vp1 { + status = "disabled"; + }; + + &hdmi_sound { + status = "okay"; + }; + + &route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; + }; + \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts new file mode 100644 index 0000000000000..2692c2eddd365 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts @@ -0,0 +1,1225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Rockchip RK3566 OPi 3B"; + compatible = "rockchip,rk3566-orangepi-3b", "rockchip,rk3566"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0"; + }; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* labeled +3.3v For PCIe only in schematic */ + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led@1 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + test-power { + status = "okay"; + }; + + unisoc_uwe_bsp: uwe-bsp { + compatible = "unisoc,uwe_bsp"; + wl-reg-on = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + bt-reg-on = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + wl-wake-host-gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + bt-wake-host-gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + //sdio-ext-int-gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + unisoc,btwf-file-name = "/vendor/etc/firmware/wcnmodem.bin"; + //adma-tx; + //adma-rx; + data-irq; + blksz-512; + keep-power-on; + status = "okay"; + }; + + sprd-mtty { + compatible = "sprd,mtty"; + sprd,name = "ttyBT"; + status = "okay"; + }; + + vcc_camera_ov5647: vcc-camera-ov5647 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_camera_ov5647"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ext_cam_ov5647_clk: external-camera-ov5647-clock { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "ext_cam_ov5647_clk"; + #clock-cells = <0>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm7 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp-panel { + compatible = "simple-panel"; + backlight = <&backlight>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + + display-timings { + native-mode = <&edp_timing>; + + edp_timing: timing0 { + clock-frequency = <125000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <180>; + hfront-porch = <120>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + +&gpu { + clock-names = "gpu", "bus"; + interrupt-names = "gpu", "mmu", "job"; + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <1>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&pwm7 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + work-led { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl_en: bl-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "disabled"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vbus>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + //snps,reset-delays-us = <0 20000 100000>; + snps,reset-delays-us = <0 50000 200000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + + tx_delay = <0x30>; + rx_delay = <0x10>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | 1 << + ROCKCHIP_VOP2_SMART0 | 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | 1 << + ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&i2c1 { + status = "okay"; + + ov5647: ov5647@36 { + status = "disabled"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&ext_cam_ov5647_clk>; + clock-names = "ext_cam_ov5647_clk"; + pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "LMM248"; + rockchip,camera-module-lens-name = "YXC-M804A2"; + port { + ov5647_out: endpoint { + remote-endpoint = <&dphy1_in>; + data-lanes = <1 2>; + }; + }; + }; + + raspits_panel: raspits-panel@45 { + status = "disabled"; + compatible = "raspberrypi,7inch-touchscreen-panel"; + reg = <0x45>; + + port { + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + + raspits_touch_ft5426: raspits-touch-ft5426@38 { + status = "disabled"; + compatible = "raspits_ft5426"; + reg = <0x38>; + }; +}; + +&csi2_dphy_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; +}; + +&csi2_dphy1 { + status = "disabled"; + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5647_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&rkisp { + status = "disabled"; +}; + +&rkisp_mmu { + status = "disabled"; +}; + +&rkisp_vir0 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy1_out>; + }; + }; +}; + +&edp { + status = "disabled"; + force-hpd; + hpd-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd &bl_en>; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "disabled"; +}; + +&route_edp { + status = "disabled"; +}; + +&pwm2 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; + + ports { + port@1 { + reg = <1>; + + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts new file mode 100644 index 0000000000000..3a4ffca1eab78 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts @@ -0,0 +1,1215 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Rockchip RK3566 OPi 3B"; + compatible = "rockchip,rk3566-orangepi-3b", "rockchip,rk3566"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0"; + }; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* labeled +3.3v For PCIe only in schematic */ + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led@1 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + test-power { + status = "okay"; + }; + + vcc_camera_ov5647: vcc-camera-ov5647 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_camera_ov5647"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ext_cam_ov5647_clk: external-camera-ov5647-clock { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "ext_cam_ov5647_clk"; + #clock-cells = <0>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vccio_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vccio_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm7 0 20000000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp-panel { + compatible = "simple-panel"; + backlight = <&backlight>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + + display-timings { + native-mode = <&edp_timing>; + + edp_timing: timing0 { + clock-frequency = <125000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <180>; + hfront-porch = <120>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <1>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reset_h>; + }; +}; + +&pwm7 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + bt { + bt_reset_h: bt-reset-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + work-led { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl_en: bl-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vccio_phy>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "disabled"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vbus>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + //snps,reset-delays-us = <0 20000 100000>; + snps,reset-delays-us = <0 50000 200000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + + tx_delay = <0x30>; + rx_delay = <0x10>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | 1 << + ROCKCHIP_VOP2_SMART0 | 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | 1 << + ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&i2c1 { + status = "okay"; + + ov5647: ov5647@36 { + status = "disabled"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&ext_cam_ov5647_clk>; + clock-names = "ext_cam_ov5647_clk"; + pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "LMM248"; + rockchip,camera-module-lens-name = "YXC-M804A2"; + port { + ov5647_out: endpoint { + remote-endpoint = <&dphy1_in>; + data-lanes = <1 2>; + }; + }; + }; + + raspits_panel: raspits-panel@45 { + status = "disabled"; + compatible = "raspberrypi,7inch-touchscreen-panel"; + reg = <0x45>; + + port { + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + + raspits_touch_ft5426: raspits-touch-ft5426@38 { + status = "disabled"; + compatible = "raspits_ft5426"; + reg = <0x38>; + }; +}; + +&csi2_dphy_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; +}; + +&csi2_dphy1 { + status = "disabled"; + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5647_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&rkisp { + status = "disabled"; +}; + +&rkisp_mmu { + status = "disabled"; +}; + +&rkisp_vir0 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy1_out>; + }; + }; +}; + +&edp { + status = "disabled"; + force-hpd; + hpd-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd &bl_en>; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "disabled"; +}; + +&route_edp { + status = "disabled"; +}; + +&pwm2 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; + + ports { + port@1 { + reg = <1>; + + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dts new file mode 100644 index 0000000000000..f97e33bd8108a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3-ap6212.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3-ap6212.dts new file mode 100644 index 0000000000000..fd82de35cbf86 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3-ap6212.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Radxa Limited. + * + */ + +/dts-v1/; + +#include "rk3566-radxa-zero3.dtsi" + +/ { + model = "Radxa ZERO 3"; + compatible ="radxa,zero3", "rockchip,rk3566"; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6212"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + }; + + board_antenna: board-antenna { + status = "okay"; + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + pinctrl-0 = <&ant_1>; + pinctrl-names = "default"; + regulator-name = "board_antenna"; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk817 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&sdmmc1 { + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + rockchip,default-sample-phase = <180>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + no-sd; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&pinctrl { + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_12>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_12>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_12>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_12>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_12>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_12>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + antenna { + ant_1: ant-1 { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3.dts new file mode 100644 index 0000000000000..1713009b76423 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Radxa Limited. + * + */ + +/dts-v1/; + +#include "rk3566-radxa-zero3.dtsi" + +/ { + model = "Radxa ZERO 3"; + compatible ="radxa,zero3-aic8800ds2", "rockchip,rk3566"; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + WIFI,poweren_gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + }; + + board_antenna: board-antenna { + status = "okay"; + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + pinctrl-0 = <&ant_1>; + pinctrl-names = "default"; + regulator-name = "board_antenna"; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&sdmmc1 { + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + rockchip,default-sample-phase = <180>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + no-sd; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&pinctrl { + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_12>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_12>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_12>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_12>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_12>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_12>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + antenna { + ant_1: ant-1 { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3.dtsi new file mode 100644 index 0000000000000..67b7699edaa9e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero3.dtsi @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Radxa Limited. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Radxa ZERO 3"; + compatible = "radxa,zero3", "rockchip,rk3566"; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + board-led { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&board_led>; + linux,default-trigger = "heartbeat"; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi0"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: rk860x@40 { + status = "okay"; + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <1000000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + out-l2spk-r2hp; + //spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_gpu>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x47>; + rx_delay = <0x27>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + status = "okay"; + }; +}; + +&sfc { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + sel-gpios= <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + }; + }; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "", "", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "", + + /* GPIO0_D0-D3 */ + "PIN_10", "PIN_8", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "PIN_3", "PIN_5", "", "", + /* GPIO1_A4-A7 */ + "PIN_37", "", "", "", + + /* GPIO1_B0-B3 */ + "", "", "", "", + /* GPIO1_B4-B7 */ + "", "", "", "", + + /* GPIO1_C0-C3 */ + "", "", "", "", + /* GPIO1_C4-C7 */ + "", "", "", "", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "PIN_11", "PIN_13", "PIN_12", + /* GPIO3_A4-A7 */ + "PIN_35", "PIN_40", "PIN_38", "PIN_36", + + /* GPIO3_B0-B3 */ + "PIN_15", "PIN_16", "PIN_18", "PIN_29", + /* GPIO3_B4-B7 */ + "PIN_31", "", "", "", + + /* GPIO3_C0-C3 */ + "", "PIN_22", "PIN_32", "PIN_33", + /* GPIO3_C4-C7 */ + "PIN_7", "", "", "", + + /* GPIO3_D0-D3 */ + "", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "", "", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "PIN_27", "PIN_28", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "PIN_23", "PIN_19", + /* GPIO4_C4-C7 */ + "", "PIN_21", "PIN_24", "", + + /* GPIO4_D0-D3 */ + "", "PIN_26", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&hdmi { + status = "okay"; + preset_max_hdisplay = <1920>; + preset_max_vdisplay = <1080>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_CENTER_OFF + | RKPM_SLP_HW_PLLS_OFF + | RKPM_SLP_PMUALIVE_32K + | RKPM_SLP_32K_PVTM + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + board_led: board-led { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-taishanpi-v10.dts b/arch/arm64/boot/dts/rockchip/rk3566-taishanpi-v10.dts new file mode 100644 index 0000000000000..56b5b6d35998e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-taishanpi-v10.dts @@ -0,0 +1,1192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "TaishanPi V10 Board"; + compatible = "lckfb,tspi-v10", "rockchip,rk3566"; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + restart-key { + label = "restart"; + linux,code = ; + press-threshold-microvolt = <108>; + }; + }; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6212"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + leds: leds { + compatible = "gpio-leds"; + rgb_led_r: rgb-led-r { + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + linux,delay-reg = <0>; + linux,blink-delay-on = <500>; + linux,blink-delay-off = <500>; + }; + rgb_led_g: rgb-led-g { + gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + linux,delay-reg = <100>; + linux,blink-delay-on = <1000>; + linux,blink-delay-off = <1000>; + }; + rgb_led_b: rgb-led-b { + gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + linux,delay-reg = <100>; + linux,blink-delay-on = <1500>; + linux,blink-delay-off = <1500>; + }; + }; + + ex39-usb-vcc5v0-host-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ex39_usb_vcc5v0_host_en>; + regulator-name = "ex39_usb_vcc5v0_host_en"; + regulator-always-on; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + + +&rockchip_suspend { + status = "okay"; +}; + +&vop { + disable-win-move; +}; + +&vp0 { + cursor-win-id = ; +}; + +&vp1 { + cursor-win-id = ; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can0m1_pins>; + status = "disabled"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "disabled"; +}; + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + status = "disabled"; +}; + + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + + +&dfi { + status = "okay"; +}; + + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + xpt2046-touchscreen { + xpt2046_int_pin: xpt2046-int-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + spi3 { + spi3_cs0n: spi3-cs0n { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up_drv_level_2>; + }; + + spi3_cs1n: spi3-cs1n { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_drv_level_2>; + }; + }; + + ex39_usb { + ex39_usb_vcc5v0_host_en: ex39-usb-vcc5v0-host-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&leds { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; +}; + + +&spi3 { + status = "okay"; + max-freq = <48000000>; + dma-names = "tx","rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi3_cs0n &spi3_cs1n &spi3m1_pins>; + pinctrl-1 = <&spi3_cs0n &spi3_cs1n &spi3m1_pins_hs>; + cs-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>, <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + status = "okay"; + }; + + xpt2046@1 { + pinctrl-names = "default"; + pinctrl-0 = <&xpt2046_int_pin>; + reg = <1>; + compatible = "ti,ads7846"; + interrupt-parent = <&gpio3>; + interrupts = ; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio3 RK_PA6 0>; + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <0xfff>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <0xfff>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <512>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <30>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on = <1>; + /* + * Do not set to wakeup source, + * cause TL3568-EVM board will make xpt2046 + * int pin level change when suspend, this + * will auto resume TL3568-EVM board. + */ + /delete-property/ linux,wakeup; + /delete-property/ wakeup-source; + }; +}; + +&pwm8 { + status = "okay"; +}; + +&pwm9 { + status = "okay"; +}; + +&pwm14 { + status = "okay"; +}; + +&pwm15 { + status = "okay"; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m0_pins>; + + //how to：dmesg usercode=address&key_table=command + //echo 1 > sys/module/rockchip_pwm_remotectl/parameters/code_print + //find in include/dt-bindings/input/linux-event-codes.h + ir_key1 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf2 KEY_MENU>, + <0xe9 KEY_BACK>, + <0xe3 KEY_ENTER>, + <0xe7 KEY_UP>, + <0xad KEY_DOWN>, + <0xf7 KEY_LEFT>, + <0xa5 KEY_RIGHT>, + <0xba KEY_1>, + <0xb9 KEY_2>, + <0xb8 KEY_3>, + <0xbb KEY_4>, + <0xbf KEY_5>, + <0xbc KEY_6>, + <0xf8 KEY_7>, + <0xea KEY_8>, + <0xf6 KEY_9>, + <0xe6 KEY_0>; + }; +}; + +&usbhost_dwc3 { + phys = <&u2phy0_host>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; +&combphy1_usq { + rockchip,dis-u3otg1-port; + status = "okay"; +}; + +&sata1 { + rockchip,enable-ssc; + status = "okay"; +}; + +&rk_headset { + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x25>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>;//wucaicheng wifi VCCIO_WL 0¦¸=1V8 + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>;//wucaicheng PHY 0¦¸=1V8 + vccio7-supply = <&vcc_3v3>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&sfc { + status = "disabled"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-armsom-sige3.dts b/arch/arm64/boot/dts/rockchip/rk3568-armsom-sige3.dts new file mode 100644 index 0000000000000..ee335789b10e3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-armsom-sige3.dts @@ -0,0 +1,1092 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "ArmSom Sige3"; + compatible = "armsom,sige3", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm3 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + label = "red"; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + default-state = "off"; + }; + + active_led: active { + label = "green"; + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + default-state = "on"; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + rk809_sound: rk809-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &clk32k_out1>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc3v3_pcie0: vcc3v3-pcie0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_host2: vcc5v0-host2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host2_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x48>;//3c + rx_delay = <0x2a>;//2f + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + + usbc1: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc1_int>; + vbus-supply = <&vcc3v3_sys>; + status = "okay"; + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + }; + }; + + vdd_cpu: rk8600@40 { + compatible = "rockchip,rk8600"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; + + +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake: bt-host-wake { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host2_en: vcc5v0-host2-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + usbc1_int: usbc1-int { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + vcc3v3_pcie_en: vcc3v3-pcie-en { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm3 { + status = "okay"; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host2>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host2>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + bluetooth { + compatible = "brcm,bcm43438-bt"; + device-wakeup-gpios = <&gpio2 RK_PC1 0>; + host-wakeup-gpios = <&gpio2 RK_PC0 0>; + shutdown-gpios = <&gpio2 RK_PB7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + disable-win-move; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts new file mode 100644 index 0000000000000..eb64bb66d442b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-hinlink-h6xk.dtsi" + +/ { + model = "HINLINK H66K"; + compatible = "hinlink,h66k", "rockchip,rk3568"; + + aliases { + ethernet0 = &rtl8125_1; + ethernet1 = &rtl8125_2; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts new file mode 100644 index 0000000000000..94eb1b1410932 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-hinlink-h6xk.dtsi" + +/ { + model = "HINLINK H68K"; + compatible = "hinlink,h68k", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h6xk.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h6xk.dtsi new file mode 100644 index 0000000000000..893c2d7fac3f3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h6xk.dtsi @@ -0,0 +1,985 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>; + + led_net: net { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "blue:net"; + }; + + led_sata: sata { + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + label = "amber:sata"; + }; + + led_work: work { + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + label = "green:work"; + linux,default-trigger = "heartbeat"; + }; + }; + + rk809_sound: rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_sys_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie"; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + clock-names = "gpu", "bus"; + interrupt-names = "gpu", "mmu", "job"; + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <1>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x1 { + rockchip,bifurcation; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; + + pcie@0,0 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + rtl8125_1: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie3x2 { + rockchip,bifurcation; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; + + pcie@0,0 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + rtl8125_2: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_net_en: led-net-en { + rockchip,pins = + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + led_sata_en: led-sata-en { + rockchip,pins = + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + led_work_en: led-work-en { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc { + vcc3v3_sys_en: vcc3v3-sys-en { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm3 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; + + ir_key4 { + rockchip,usercode = <0xdd22>; + rockchip,key_table = + <0x23 KEY_POWER>, + <0x63 KEY_MUTE>, + <0x35 KEY_UP>, + <0x2d KEY_DOWN>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x31 KEY_ENTER>, + <0x6a KEY_ESC>, + <0x7d KEY_MENU>, + <0x7f KEY_VOLUMEUP>, + <0x7e KEY_VOLUMEDOWN>, + <0x77 KEY_HOME>; + }; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + }; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + sd-uhs-sdr104; + disable-wp; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + phys = <&u2phy0_otg>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + support-multi-area; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-hnas.dts b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-hnas.dts new file mode 100644 index 0000000000000..fdd04463fdbef --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-hnas.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-hinlink-h6xk.dtsi" + +/ { + model = "HINLINK HNAS"; + compatible = "hinlink,hnas", "rockchip,rk3568"; + + aliases { + ethernet0 = &rtl8125_1; + ethernet1 = &rtl8125_2; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <8 39 70 100 131 162 193 224 255>; + pwms = <&pwm0 0 10000 0>; + }; + + hdd_leds { + led_hdd1: led-hdd1 { + pinctrl-names = "default"; + pinctrl-0 = <&led_hdd1_pin>; + label = "led:hdd1"; + gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + }; + + led_hdd2: led-hdd2 { + pinctrl-names = "default"; + pinctrl-0 = <&led_hdd2_pin>; + label = "led:hdd2"; + gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + + led_hdd3: led-hdd3 { + pinctrl-names = "default"; + pinctrl-0 = <&led_hdd3_pin>; + label = "led:hdd3"; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + }; + + led_hdd4: led-hdd4 { + pinctrl-names = "default"; + pinctrl-0 = <&led_hdd4_pin>; + label = "led:hdd4"; + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + }; + + sata_pm_power: sata-pm-power { + compatible = "regulator-fixed"; + regulator-name = "sata_pm_power"; + regulator-enable-ramp-delay = <1000000>; + regulator-always-on; + regulator-boot-on; + + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sata_pm_power_en>; + vin-supply = <&vcc3v3_sys>; + }; + + sata_pm_reset: sata-pm-reset { + compatible = "regulator-fixed"; + regulator-name = "sata_pm_reset"; + regulator-enable-ramp-delay = <1000000>; + regulator-always-on; + regulator-boot-on; + + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sata_pm_reset_en>; + vin-supply = <&vcc3v3_sys>; + }; + + sata_hdd_power: sata-hdd-power { + compatible = "regulator-fixed"; + regulator-name = "sata_hdd_power"; + regulator-enable-ramp-delay = <1000000>; + regulator-always-on; + regulator-boot-on; + + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sata_hdd_power_en>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&pinctrl { + hdd-leds { + led_hdd1_pin: led-hdd1-pin { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_hdd2_pin: led-hdd2-pin { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_hdd3_pin: led-hdd3-pin { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_hdd4_pin: led-hdd4-pin { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata-pm { + sata_pm_power_en: sata-pm-power-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + sata_pm_reset_en: sata-pm-reset-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + sata_hdd_power_en: sata-hdd-power-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&soc_thermal { + trips { + trip0: trip-point@0 { + temperature = <45000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip5: trip-point@5 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip6: trip-point@6 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + trip7: trip-point@7 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&trip5>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + map6 { + trip = <&trip6>; + cooling-device = <&fan0 6 7>; + contribution = <1024>; + }; + map7 { + trip = <&trip7>; + cooling-device = <&fan0 7 8>; + contribution = <1024>; + }; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-mixtile-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3568-mixtile-edge2.dts new file mode 100644 index 0000000000000..57ff428f449d4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-mixtile-edge2.dts @@ -0,0 +1,1194 @@ +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" +#include "rk3568-linux.dtsi" + +/ { + + model = "Mixtile Edge 2"; + compatible = "focalcrest,mixtile-edge2", "rockchip,rk3568"; + /delete-node/ chosen; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + button@0 { + gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + label = "GPIO Loader"; + linux,code = ; + }; + }; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi-sound"; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&hdmi>; + }; + + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_m2: vcc3v3-m2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_m2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + + }; + + vcc1v8_m2: vcc1v8-m2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_m2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&vcc1v8_m2_pin>; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + + }; + + vcc3v3_minipcie: vcc3v3-minipcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_minipcie"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + clocks = <&rk809 1>; + clock-names = "clk_wifi"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; + +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + rockchip,bifurcation; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&pdm { + pinctrl-0 = <&pdmm0_clk + &pdmm0_clk1 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + status = "okay"; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "disabled"; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&pinctrl { + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + bt { + bt_enable: bt-enable { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake: bt-host-wake { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc1v8-m2-pin { + vcc1v8_m2_pin: vcc1v8-m2-pin { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi new file mode 100644 index 0000000000000..35da30fc1ba3c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi @@ -0,0 +1,977 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "FriendlyElec boards based on Rockchip RK3568"; + compatible = "friendlyelec,nanopi5", + "rockchip,rk3568"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 coherent_pool=1m"; + }; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdhci; + mmc3 = &sdmmc2; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi0"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + mach: board { + compatible = "friendlyelec,board"; + machine = "NANOPI5"; + hwrev = <255>; + model = "NanoPi 5 Series"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>; + nvmem-cell-names = "id", "cpu-version"; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vdd_usbc: vdd-usbc { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc3v3_sysp: vcc3v3-sysp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sysp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_sysp: vcc5v0-sysp { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sysp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc3v3_sysp>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sysp>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sysp>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + simple_bat: battery { + compatible = "simple-battery"; + voltage-max-design-microvolt = <13000000>; + voltage-min-design-microvolt = <4500000>; + }; + + nanopi_adc_vin: nanopi-adc-vin { + compatible = "nanopi-adc-power-v1"; + io-channels = <&saradc 2>; + io-channel-names = "voltage"; + monitored-battery = <&simple_bat>; + }; + + test-power { + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +/* video_phy0/1 needs to be enabled when dsi0/1 is enabled */ +&dsi0 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc3v3_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "disabled"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm4 { + status = "disabled"; +}; + +&pwm5 { + status = "disabled"; +}; + +&pwm7 { + status = "disabled"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; +}; + +&reserved_memory { + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 0x10000000 0x0 0x00800000>; + linux,cma-default; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + rockchip,disable-auto-freq; + assigned-clock-rates = <396000000>, <396000000>, <396000000>, <600000000>; + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&vop { + status = "okay"; + vop-supply = <&vdd_logic>; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; + support-multi-area; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <( + 1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 )>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_SMART0 | 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + status = "disabled"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts new file mode 100644 index 0000000000000..290ed0b158e95 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include "rk3568-nanopi5-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R5S"; + compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; + + aliases { + ethernet1 = &r8125_1; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 18 102 170 255>; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sysp>; + pwms = <&pwm0 0 50000 0>; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc3v3_sysp>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + status = "disabled"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mach { + hwrev = <1>; + model = "NanoPi R5S"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_int>; + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie2x1 { + num-viewport = <4>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_1: pcie@1,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie3x1 { + num-viewport = <4>; + rockchip,bifurcation; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@0,0 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_2: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie3x2 { + max-link-speed = <2>; + num-lanes = <1>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + rockchip,bifurcation; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + gmac_int: gmac-int { + rockchip,pins = + <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata2 { + status = "disabled"; +}; + +&soc_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +/* GPIO Connector */ +&spi1 { + num-cs = <1>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + pinctrl-1 = <&spi1m1_cs0 &spi1m1_pins_hs>; + status = "disabled"; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; + status = "disabled"; +}; + +&uart7 { + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; +}; + +&uart9 { + pinctrl-0 = <&uart9m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts new file mode 100644 index 0000000000000..8d0bb45eaa4ad --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev02.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include "rk3568-nanopi5-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; + + aliases { + ethernet0 = &r8125_1; + ethernet1 = &r8125_2; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + m2_wlan_radio: m2-wlan-radio { + compatible = "rfkill-gpio"; + type = "wlan"; + shutdown-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + status = "disabled"; +}; + +&mach { + hwrev = <2>; + model = "NanoPi R5C"; +}; + +&i2c5 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie2x1 { + num-viewport = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&m2_w_disable_pin>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie3x1 { + num-viewport = <4>; + rockchip,bifurcation; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@0,0 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_2: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie3x2 { + num-viewport = <4>; + rockchip,bifurcation; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@0,0 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_1: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + m2-pins { + m2_w_disable_pin: m2-w-disable-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "disabled"; +}; + +&sata2 { + status = "disabled"; +}; + +&sfc { + status = "disabled"; +}; + +&simple_bat { + voltage-max-design-microvolt = <5400000>; + voltage-min-design-microvolt = <4200000>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev03.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev03.dts new file mode 100644 index 0000000000000..128d07ab30d3e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev03.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev02.dts" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; +}; + +&mach { + hwrev = <3>; + model = "NanoPi R5C"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev04.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev04.dts new file mode 100644 index 0000000000000..cde69197b66d8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev04.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev02.dts" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; +}; + +&mach { + hwrev = <4>; + model = "NanoPi R5C"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev05.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev05.dts new file mode 100644 index 0000000000000..7a6c5d6048126 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev05.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev01.dts" + +/ { + model = "FriendlyElec NanoPi R5S LTS"; + compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; +}; + +&mach { + hwrev = <5>; + model = "NanoPi R5S LTS"; +}; + +&pcie3x2 { + max-link-speed = <3>; +}; + +&pwm7 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + remote_pwm_id = <7>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xc43b>; + rockchip,key_table = + <0xff KEY_POWER>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xf2 KEY_UP>, + <0xea KEY_DOWN>, + <0xee KEY_ENTER>, + <0xe9 KEY_MUTE>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf3 KEY_VOLUMEUP>, + <0xae KEY_MENU>, + <0xeb KEY_LEFTMETA>, + <0xaf KEY_BACK>, + <0xf7 KEY_MODE>, + <0xe5 KEY_SYSRQ>, + <0xf5 KEY_ESC>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts new file mode 100644 index 0000000000000..e59628356f045 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3568-nanopi5-rev01.dts" + +/ { + model = "FriendlyElec NanoPi R5S C1"; + compatible = "friendlyelec,nanopi-r5s-c1", "rockchip,rk3568"; + + m2-wlan-radio { + compatible = "rfkill-gpio"; + type = "wlan"; + shutdown-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&mach { + hwrev = <7>; + model = "NanoPi R5S C1"; +}; + +/delete-node/ &r8125_2; + +&pcie3x1 { + pinctrl-names = "default"; + pinctrl-0 = <&m2_w_disable_pin>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; +}; + +&pcie3x2 { + max-link-speed = <3>; +}; + +&pinctrl { + m2-pins { + m2_w_disable_pin: m2-w-disable-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&spi1 { + status = "okay"; + + spi_oled091: oled091@0 { + status = "okay"; + compatible = "solomon,ssd1306"; + reg = <0>; + spi-max-frequency = <10000000>; + dc-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + width = <128>; + height = <32>; + buswidth = <8>; + fps = <30>; + rotate = <0>; + }; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; + status = "disabled"; +}; + +&uart7 { + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts new file mode 100644 index 0000000000000..cc270e1c4914f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-odroid.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Hardkernel ODROID-M1"; + /delete-node/ chosen; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + i2c0 = &i2c3; + i2c3 = &i2c0; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + status = "disabled"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A */ + "", "", "", "", "", "", "", "", + /* GPIO0_B */ + "", "", "", + "PIN_28", /* GPIO0_B3 */ + "PIN_27", /* GPIO0_B4 */ + "PIN_33", /* GPIO0_B5 */ + "PIN_7", /* GPIO0_B6 */ + "", + /* GPIO0_C */ + "PIN_11", /* GPIO0_C0 */ + "PIN_13", /* GPIO0_C1 */ + "", "", "", "", "", "", + /* GPIO0_D */ + "", "", "", "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A */ + "", "", "", "", "", "", "", "", + /* GPIO1_B */ + "", "", "", "", "", "", "", "", + /* GPIO1_C */ + "", "", "", "", "", "", "", "", + /* GPIO1_D */ + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A */ + "", "", "", "", "", "", "", "", + /* GPIO2_B */ + "", "", "", "", "", "", "", "", + /* GPIO2_C */ + "", "", "", "", "", "", "", "", + /* GPIO2_D */ + "PIN_21", /* GPIO2_D0 */ + "PIN_19", /* GPIO2_D1 */ + "PIN_24", /* GPIO2_D2 */ + "PIN_23", /* GPIO2_D3 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A */ + "", "", "", "", "", "", "", "", + /* GPIO3_B */ + "", "", + "PIN_15", /* GPIO3_B2 */ + "", "", + "PIN_5", /* GPIO3_B5 */ + "PIN_3", /* GPIO3_B6 */ + "", + /* GPIO3_C */ + "", "", "", "", "", "", + "PIN_16", /* GPIO3_C6 */ + "PIN_18", /* GPIO3_C7 */ + /* GPIO3_D */ + "PIN_12", /* GPIO3_D0 */ + "PIN_22", /* GPIO3_D1 */ + "PIN_26", /* GPIO3_D2 */ + "PIN_32", /* GPIO3_D3 */ + "PIN_36", /* GPIO3_D4 */ + "PIN_35", /* GPIO3_D5 */ + "PIN_8", /* GPIO3_D6 */ + "PIN_10"; /* GPIO3_D7 */ +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A */ + "", "", "", "", "", "", "", "", + /* GPIO4_B */ + "", "", "", "", "", "", + "PIN_31", /* GPIO4_B6 */ + "", + /* GPIO4_C */ + "", + "PIN_29", /* GPIO4_C1 */ + "", "", "", + "", "", "", + /* GPIO4_D */ + "", "", "", "", "", "", "", ""; +}; + +&hdmi_sound { + simple-audio-card,name = "ODROID-M1-HDMI"; + /delete-property/ rockchip,jack-det; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pwm1 { + status = "disabled"; + pinctrl-0 = <&pwm1m1_pins>; +}; + +&pwm2 { + status = "disabled"; + pinctrl-0 = <&pwm2m1_pins>; +}; + +&reserved_memory { + pcie3x2@80900000{ + reg = <0x0 0x80900000 0x0 0x100000>; + }; +}; + +&rk809_sound { + simple-audio-card,name = "ODROID-M1-FRONT"; +}; + +&sata2 { + status = "okay"; +}; + +&sfc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; +}; + +&spi0 { + status = "disabled"; + + pinctrl-0 = <&spi0m1_pins>; + pinctrl-1 = <&spi0m1_pins_hs>; + num_chipselect = <1>; + + cs-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; +}; + +&uart1 { + status = "disabled"; + dma-names = "tx", "rx"; + /* uart1 uart1-with-ctsrts */ + pinctrl-0 = <&uart1m1_xfer>; + pinctrl-1 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi new file mode 100644 index 0000000000000..7adc1f43ca834 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + /delete-node/ adc-keys; + /delete-node/ nandc@fe330000; + /delete-node/ sdio-pwrseq; + /delete-node/ vcc3v3-lcd0-n; + /delete-node/ vcc3v3-lcd1-n; + /delete-node/ wireless-bluetooth; + /delete-node/ wireless-wlan; + + leds: leds { + power_led: power { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + work_led: work { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + rk3568-gpiomem { + compatible = "rockchip,rk3568-gpiomem"; + reg = <0x0 0xfd660000 0x0 0x1000>; + status = "okay"; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,widgets = "Headphones", "Headphones Jack"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; + + /delete-node/ gt1x@14; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; +}; + +&i2c5 { + status = "disabled"; + + /delete-node/ mxc6655xa@15; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet_irq>; + }; +}; + +&pinctrl { + can_pins { + mcp2515_int_pins: mcp2515_int_pins { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + ethernet { + ethernet_irq: ethernet-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pinctrl { + /delete-node/ mxc6655xa; + /delete-node/ touch; + /delete-node/ wifi-enable-h; + /delete-node/ wireless-bluetooth; + + fspi { + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + vccio4-supply = <&vcc_1v8>; +}; + +&pwm3 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins>; + + ir_key1 { + rockchip,usercode = <0x4db2>; + rockchip,key_table = + <0x23 KEY_POWER>, + <0x77 KEY_MUTE>, + <0x7d KEY_HOME>, + <0x31 KEY_ENTER>, + <0x35 KEY_UP>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x2d KEY_DOWN>, + <0x3a KEY_MENU>, + <0x65 KEY_BACK>, + <0x7e KEY_VOLUMEDOWN>, + <0x7f KEY_VOLUMEUP>; + }; +}; + +&pwm7 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7_pins>; + + status = "disabled"; + + /delete-property/ remote_pwm_id; + /delete-property/ handle_cpu_id; + /delete-property/ remote_support_psci; + /delete-node/ ir_key1; + /delete-node/ ir_key2; + /delete-node/ ir_key3; +}; + +&rknpu_mmu { + status = "disabled"; +}; + +&rng { + status = "okay"; +}; + +&sdhci { + pinctrl-0 = <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + pinctrl-names = "default"; + + mmc-hs200-1_8v; + cap-mmc-hw-reset; +}; + +&video_phy0 { + status = "okay"; +}; + +&hdmi_sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "okay"; + rockchip,jack-det; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; +}; + +&rk809_sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,widgets = "Headphones", "Headphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; +}; + +&rk809_codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk &hp_det>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; +}; + +&rk_headset { + status = "disabled"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&spdif_out { + status = "disabled"; +}; + +// Suggested by amazingfate: https://github.com/armbian/build/pull/4794#issuecomment-1423606844 +// "add these properties to node &gpu to support panfrost driver" +&gpu { + clock-names = "gpu", "bus"; + interrupt-names = "gpu", "mmu", "job"; +}; + +// Suggested by amazingfate: https://github.com/armbian/build/pull/4794#issuecomment-1423606844 +// "add &vp0 node to support video output" +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-ok3568c.dts b/arch/arm64/boot/dts/rockchip/rk3568-ok3568c.dts new file mode 100644 index 0000000000000..3dd149e7b48b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-ok3568c.dts @@ -0,0 +1,1479 @@ +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" +#include + +/ { + model = "Forlinx OK3568-C Board"; + compatible = "forlinx,ok3568", "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568"; + + panel-lvds0 { + compatible = "simple-panel"; + backlight = <&lvds_backlight>; + power-supply = <&vcc3v3_lcd2_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <71100000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <10>; + vfront-porch = <12>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + }; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + }; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi"; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + //simple-audio-card,hp-det-gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm14 0 20000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + is-forlinx; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + vcc12v: vcc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v>; + }; + + vcc3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3>; + }; + + vcc1v2: vcc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc3v3>; + }; + + vcc2v8: vcc-2v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc3v3>; + }; + + vcc3v3_lcd2_n: vcc3v3-lcd2-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd2_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + 5g-rst { + compatible = "regulator-fixed"; + regulator-name = "5g-rst"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + enable-active-low; + regulator-boot-on; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&net_5g_rst_gpio>; + status = "okay"; + }; + + 5g-pwr { + compatible = "regulator-fixed"; + regulator-name = "5g-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&net_5g_pwr_gpio>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + status = "okay"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&gpu { + clock-names = "gpu", "bus"; + interrupt-names = "gpu", "mmu", "job"; + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&lvds0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1 { + status = "disabled"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + + vm149c_0: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>, <&ov13850_default_pin>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "ov13850-csi"; + rockchip,camera-module-lens-name = "ov13850-2mp"; + lens-focus = <&vm149c_0>; + + port { + ov13850_out: endpoint { + remote-endpoint = <&mipi_in_ov13850>; + data-lanes = <1 2>; + }; + }; + }; + + gt9xx_lvds: gt9xx-lvds@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + touch-gpio = <&gpio1 RK_PA4 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + max-x = <1280>; + max-y = <800>; + tp-size = <970>; + status = "disabled"; + }; + + gt9xx_rgb: gt9xx-rgb@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&rgb_touch_gpio>; + interrupt-parent = <&gpio4>; + interrupts = ; + irq-gpio = <&gpio4 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + //uniq = "rgb"; + status = "disabled"; + }; + + gt9xx_dsi: gt9xx@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_gt911_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + uniq = "dsi"; + status = "disabled"; + }; + + polytouch: edt-ft5x06@38{ + compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "defaults"; + pinctrl-0 = <&ft5x06_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + + rx8010: rx8010@32 { + compatible = "epson,rx8010"; + reg = <0x32>; + }; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm14 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + extcon=<&usb2phy0>; + status="okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&xpcs { + status="disabled"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>, <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins>; + + tx_delay = <0x2f>; + rx_delay = <0x00>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>, <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + ð1m1_pins>; + + tx_delay = <0x35>; + rx_delay = <0x00>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + clocks = <&cru CLK_MAC0_OUT>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + clocks = <&cru CLK_MAC1_OUT>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ov13850: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&pinctrl { + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgb_touch_gpio: rgb-touch-gpio { + rockchip,pins = + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ft5x06_int: ft5x06-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi_gt911_int: dsi-gt911-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ov13850_default_pin: ov13850-default-pin { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + ov13850_sleep_pin: ov13850-sleep-pin { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + 5g { + net_5g_rst_gpio: net_5g_rst_gpio { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + net_5g_pwr_gpio: net_5g_pwr_gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&spi0 { + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>; + pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>; + status = "disabled"; + + spi@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&spi2 { + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>; + pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>; + status = "okay"; + + spi@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + + spi@1 { + compatible = "rockchip,spidev"; + reg = <1>; + spi-max-frequency = <50000000>; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts new file mode 100644 index 0000000000000..79629044c9f73 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2021 Radxa Limited. + * + */ + +/dts-v1/; + +#include "rk3568-radxa-rock-3-compute-module-plus.dtsi" + +/ { + model = "Radxa E25"; + compatible = "radxa,e25", "rockchip,rk3568"; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; + + pcie30_3v3: pcie30-3v3 { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_minipcie_en>; + regulator-name = "vcc3v3_minipcie"; + regulator-always-on; + regulator-boot-on; + }; + + //low:wifi,high:5G + vcc3v3_minipcie_to_5g_or_wifi: vcc3v3-minipcie-to-5g-or-wifi { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_minipcie_to_5g_or_wifi_en>; + regulator-name = "vcc3v3_minipcie_to_5g_or_wifi"; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_pcie_30x1: vcc3v3-pci-30x1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_30x1_en>; + regulator-name = "vcc3v3_pci_30x1"; + regulator-always-on; + regulator-boot-on; + }; + + em05_modem: em05-modem { + compatible = "lte-em05-modem-platdata"; + pinctrl-names = "default"; + pinctrl-0 = <&em05_power_en &em05_airplane_mode &em05_reset>; + em05,power-gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + em05,reset-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + em05,airplane-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + rgb0: rgb0 { + compatible = "pwm-leds"; + status = "okay"; + + rgb0-red { + pwms = <&pwm1 0 1000000 0>; + max-brightness = <255>; + }; + + rgb0-blue { + pwms = <&pwm12 0 1000000 0>; + max-brightness = <255>; + }; + + rgb0-green { + pwms = <&pwm2 0 1000000 0>; + max-brightness = <255>; + }; + }; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&sdio_pwrseq { + status = "disabled"; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +//sdcard +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + cd-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +/* USB OTG/USB Host_1 USB 2.0 Comb PHY_0 */ +&usb2phy0 { + status = "okay"; + u2phy0_host { + status = "okay"; + }; + u2phy0_otg { + status = "okay"; + }; +}; + +/* USB Host_2/USB Host_3 USB 2.0 Comb PHY_1 */ +&usb2phy1 { + status = "okay"; + u2phy1_host { + status = "okay"; + }; + u2phy1_otg { + status = "okay"; + }; +}; + +/* USB 2.0 Host_2 EHCI controller for high speed */ +&usb_host0_ehci { + status = "okay"; +}; + +/* USB 2.0 Host_2 OHCI controller for full/low speed */ +&usb_host0_ohci { + status = "okay"; +}; + +/* USB 2.0 Host_3 EHCI controller for high speed */ +&usb_host1_ehci { + status = "okay"; +}; + +/* USB 2.0 Host_3 OHCI controller for full/low speed */ +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + extcon=<&usb2phy0>; + status="okay"; +}; + +/* USB 3.0 OTG controller */ +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + phys = <&u2phy0_host>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; /* set dwc3 controller to high speed */ + status = "okay"; +}; + +/* USB 3.0 Host_1 controller */ +&usbhost30 { + status = "disabled"; +}; + +/* USB 3.0 OTG/SATA Combo PHY_0 */ +&combphy0_us { + status = "okay"; +}; + +/* USB 3.0 Host/SATA/QSGMII Combo PHY_1 */ +&combphy1_usq { + rockchip,dis-u3otg1-port; /* set dwc3 controller to high speed */ + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x1 { + rockchip,bifurcation; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + pinctrl-0 = <&pcie30x1m0_pins>; + status = "okay"; +}; + +&pcie3x2 { + rockchip,bifurcation; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + pinctrl-0 = <&pcie30x2m1_pins>; + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + pinctrl-0 = <&pcie20m2_pins>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; +}; + +&pwm12 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m1_pins>; +}; + +&user_leds { + linux,default-trigger = "none"; + default-state = "off"; +}; + +&pinctrl { + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pci-en { + vcc3v3_minipcie_en: vcc3v3-minipcie-en { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie_30x1_en: vcc3v3-pcie-30x1-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_minipcie_to_5g_or_wifi_en: vcc3v3-minipcie-to-5g-or-wifi-en { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lte-em05-modem { + em05_airplane_mode: em05-airplane-mode { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + em05_power_en: em05-power-en { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + em05_reset: em05-reset { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-rock-3-compute-module-plus.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-rock-3-compute-module-plus.dtsi new file mode 100644 index 0000000000000..29b978245f71a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-rock-3-compute-module-plus.dtsi @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2021 Radxa Limited. + * + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + compatible = "radxa,rock-3-compute-module-plus", "rockchip,rk3568"; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + }; + }; + + rk809_sound: rk809-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; //WIFI_REG_ON_H + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + clocks = <&rk809 1>; + clock-names = "clk_wifi"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //WIFI_WAKE_HOST_H + status = "okay"; + }; + + bt_uart8: wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //BT_REG_ON_H + BT,wake_gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; //HOST_WAKE_BT_H + BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; //BT_WAKE_HOST_H + status = "okay"; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + user_leds: user-led { + gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + default-state = "on"; + pinctrl-0 = <&user_led>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + clock-names = "gpu", "bus"; + interrupt-names = "gpu", "mmu", "job"; + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "disabled"; + }; + }; +}; + +&i2s1_8ch { + status = "disabled"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x44>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +&mdio1 { + status = "disabled"; + + rgmii_phy1: phy@0 { + status = "disabled"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +//wifi +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +//bt +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led: user-led { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a-display.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a-display.dtsi new file mode 100644 index 0000000000000..b98b78e53bba9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a-display.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited. + * + */ + +/ { + compatible = "radxa,rock-3a", "rockchip,rk3568"; + + vcc_mipi: vcc-mipi { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "vcc_mipi"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&video_phy1 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; + power-supply = <&vcc_mipi>; + + dsi1_panel: dsi-panel@0 { + compatible = "rockpi,tc358762"; + reg = <0x0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp1_out_dsi1>; +}; + +&i2c3 { + status = "disabled"; + pinctrl-0 = <&i2c3m1_xfer>; + + rockpi_mcu: rockpi-mcu@45 { + compatible = "rockpi_mcu"; + reg = <0x45>; + status = "disabled"; + }; + + rockpi_ft5406: rockpi-ft5406@38 { + compatible = "rockpi_ft5406"; + reg = <0x38>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index bab46db2b18cd..30b4c43a855e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -1,82 +1,149 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /dts-v1/; #include -#include +#include #include -#include +#include +#include +#include +#include #include "rk3568.dtsi" +#include "rk3568-rock-3a-display.dtsi" +#include "rk3568-rock-3ab-cameras.dtsi" / { model = "Radxa ROCK3 Model A"; compatible = "radxa,rock3a", "rockchip,rk3568"; - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; }; - chosen: chosen { - stdout-path = "serial2:1500000n8"; + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; }; - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + }; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; }; }; - leds { - compatible = "gpio-leds"; + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "okay"; - led_user: led-0 { - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; }; }; - rk809-sound { + rk809_sound: rk809-sound { + status = "okay"; compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; + simple-audio-card,name = "rockchip,rk809-codec"; simple-audio-card,mclk-fs = <256>; simple-audio-card,cpu { sound-dai = <&i2s1_8ch>; }; - simple-audio-card,codec { - sound-dai = <&rk809>; + sound-dai = <&rk809_codec>; }; }; - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; //HP_HOOK pin }; - vcc3v3_pcie: vcc3v3-pcie-regulator { + dc_12v: dc-12v { compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; }; vcc3v3_sys: vcc3v3-sys { @@ -86,7 +153,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; + vin-supply = <&dc_12v>; }; vcc5v0_sys: vcc5v0-sys { @@ -96,173 +163,215 @@ regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; + vin-supply = <&dc_12v>; }; - vcc5v0_usb: vcc5v0-usb { + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; }; - vcc5v0_usb_host: vcc5v0-usb-host { + vcc5v0_otg: vcc5v0-otg-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + regulator-boot-on; }; - vcc5v0_usb_hub: vcc5v0-usb-hub-regulator { + vcc5v0_usbhub: vcc5v0-usbhub-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_hub_en>; - regulator-name = "vcc5v0_usb_hub"; + pinctrl-0 = <&vcc5v0_hub_en>; + regulator-name = "vcc5v0_hub"; regulator-always-on; - vin-supply = <&vcc5v0_usb>; }; - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + pcie30_avdd0v9: pcie30-avdd0v9 { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; }; - vcc_cam: vcc-cam { + pcie30_avdd1v8: pcie30-avdd1v8 { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_cam_en>; - regulator-name = "vcc_cam"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <&vcc3v3_sys>; + }; - regulator-state-mem { - regulator-off-in-suspend; - }; + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; }; - vcc_mipi: vcc-mipi { + vcc3v3_bu: vcc3v3-bu { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_mipi_en>; - regulator-name = "vcc_mipi"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; + vin-supply = <&vcc5v0_sys>; + }; - regulator-state-mem { - regulator-off-in-suspend; - }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; //WIFI_REG_ON_H }; -}; -&combphy0 { - status = "okay"; -}; + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + clocks = <&rk809 1>; + clock-names = "clk_wifi"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //WIFI_WAKE_HOST_H + status = "okay"; + }; -&combphy1 { - status = "okay"; -}; + bt_uart1: wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //BT_REG_ON_H + BT,wake_gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; //HOST_WAKE_BT_H + BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; //BT_WAKE_HOST_H + status = "okay"; + }; -&combphy2 { - status = "okay"; + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + user-led { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + default-state = "on"; + pinctrl-0 = <&user_led>; + }; + + wifi-led { + gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "rfkill2"; + default-state = "on"; + pinctrl-0 = <&wifi_led>; + }; + }; }; &cpu0 { cpu-supply = <&vdd_cpu>; }; -&cpu1 { - cpu-supply = <&vdd_cpu>; +&crypto { + status = "okay"; }; -&cpu2 { - cpu-supply = <&vdd_cpu>; +&dfi { + status = "okay"; }; -&cpu3 { - cpu-supply = <&vdd_cpu>; +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; }; -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; +&video_phy0 { status = "okay"; }; +&display_subsystem { + status = "okay"; +}; + &gpu { + clock-names = "gpu", "bus"; + interrupt-names = "gpu", "mmu", "job"; mali-supply = <&vdd_gpu>; status = "okay"; }; &hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; status = "okay"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>; }; -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; +&hdmi_in_vp0 { + status = "okay"; }; -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; +&hdmi_in_vp1 { + status = "disabled"; }; &hdmi_sound { status = "okay"; }; +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + &i2c0 { status = "okay"; - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; regulator-state-mem { regulator-off-in-suspend; }; @@ -272,16 +381,25 @@ compatible = "rockchip,rk809"; reg = <0x20>; interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; - #sound-dai-cells = <0>; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + vcc1-supply = <&vcc3v3_sys>; vcc2-supply = <&vcc3v3_sys>; vcc3-supply = <&vcc3v3_sys>; @@ -291,103 +409,121 @@ vcc7-supply = <&vcc3v3_sys>; vcc8-supply = <&vcc3v3_sys>; vcc9-supply = <&vcc3v3_sys>; - wakeup-source; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "disabled"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; regulators { vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; - + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; + regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; - + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-initial-mode = <0x2>; - + regulator-name = "vcc_ddr"; regulator-state-mem { regulator-on-in-suspend; }; }; vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; regulator-state-mem { regulator-off-in-suspend; }; }; vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; + regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; - + regulator-name = "vdda0v9_image"; regulator-state-mem { regulator-off-in-suspend; }; }; vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; - + regulator-name = "vdda_0v9"; regulator-state-mem { regulator-off-in-suspend; }; }; vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; - + regulator-name = "vdda0v9_pmu"; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <900000>; @@ -395,33 +531,33 @@ }; vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; regulator-state-mem { regulator-off-in-suspend; }; }; vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - + regulator-name = "vccio_sd"; regulator-state-mem { regulator-off-in-suspend; }; }; vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - + regulator-name = "vcc3v3_pmu"; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3300000>; @@ -429,24 +565,22 @@ }; vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - + regulator-name = "vcca_1v8"; regulator-state-mem { regulator-off-in-suspend; }; }; vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - + regulator-name = "vcca1v8_pmu"; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; @@ -454,65 +588,75 @@ }; vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; regulator-always-on; regulator-boot-on; - + regulator-name = "vcc_3v3"; regulator-state-mem { regulator-off-in-suspend; }; }; vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; regulator-name = "vcc3v3_sd"; - regulator-state-mem { regulator-off-in-suspend; }; }; }; - codec { + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; mic-in-differential; + status = "okay"; }; }; }; -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m1_xfer>; - status = "disabled"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "disabled"; -}; - &i2c5 { - status = "okay"; + status = "okay"; + pinctrl-0 = <&i2c5m0_xfer>; - hym8563: rtc@51 { + hym8563: hym8563@51 { compatible = "haoyu,hym8563"; + status = "okay"; reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; #clock-cells = <0>; - clock-output-names = "rtcic_32kout"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; + clock-frequency = <32768>; + clock-output-names = "hym8563"; }; }; @@ -521,155 +665,195 @@ }; &i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; - rockchip,trcm-sync-tx-only; status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; }; -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - }; +&iep { + status = "okay"; }; -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; +&iep_mmu { status = "okay"; }; -&pinctrl { - cam { - vcc_cam_en: vcc_cam_en { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - display { - vcc_mipi_en: vcc_mipi_en { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - led_user_en: led_user_en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; +&jpegd { + status = "okay"; +}; - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; +&jpegd_mmu { + status = "okay"; +}; - usb { - vcc5v0_usb_host_en: vcc5v0_usb_host_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; +&mpp_srv { + status = "okay"; }; &pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; + status = "okay"; pmuio2-supply = <&vcc3v3_pmu>; vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; vccio3-supply = <&vccio_sd>; vccio4-supply = <&vcc_1v8>; vccio5-supply = <&vcc_3v3>; vccio6-supply = <&vcc_1v8>; vccio7-supply = <&vcc_3v3>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { status = "okay"; }; &saradc { - vref-supply = <&vcca_1v8>; status = "okay"; + vref-supply = <&vcca_1v8>; }; &sdhci { bus-width = <8>; - max-frequency = <200000000>; + supports-emmc; non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; + max-frequency = <200000000>; status = "okay"; }; &sdmmc0 { + max-frequency = <150000000>; + supports-sd; bus-width = <4>; + cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr50; + sd-uhs-sdr104; vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; status = "okay"; }; +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + &tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; status = "okay"; }; -&uart2 { +&u2phy0_host { + phy-supply = <&vcc5v0_host>; status = "okay"; }; -&usb_host0_ehci { +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; status = "okay"; }; -&usb_host0_ohci { +&u2phy1_host { + phy-supply = <&vcc5v0_host>; status = "okay"; }; -&usb_host0_xhci { - extcon = <&usb2phy0>; +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { status = "okay"; }; @@ -681,51 +865,232 @@ status = "okay"; }; -&usb_host1_xhci { +&usbdrd_dwc3 { + extcon=<&usb2phy0>; + status="okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { status = "okay"; }; -&usb2phy0 { +&usbhost30 { status = "okay"; }; -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; +&combphy0_us { status = "okay"; }; -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; +&combphy1_usq { status = "okay"; }; -&usb2phy1 { +&sata0 { + status = "disabled"; +}; + +&sata1 { + status = "disabled"; +}; + +&xpcs { + status="disabled"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { status = "okay"; }; -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_host>; +&vepu { status = "okay"; }; -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; +&vepu_mmu { status = "okay"; }; &vop { + status = "okay"; assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; }; &vop_mmu { status = "okay"; }; -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x42>; + rx_delay = <0x28>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + //num-lanes = <2>; + pinctrl-0 = <&pcie30x2m1_pins>; + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + pinctrl-0 = <&pcie20m1_pins>; + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_hub_en: vcc5v0-hub-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + user_led: user-led { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_led: wifi-led { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3ab-cameras.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-rock-3ab-cameras.dtsi new file mode 100644 index 0000000000000..5ceac78329ccb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3ab-cameras.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited. + * + */ + +/ { + ext_cam_clk: ext-cam-clk { + status = "disabled"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "ext_cam_clk"; + #clock-cells = <0>; + }; + + ext_cam_clk_imx219: ext-cam-clk-imx219 { + status = "disabled"; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "ext_cam_clk_imx219"; + #clock-cells = <0>; + }; + + vcc_camera: vcc-camera { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "vcc_camera"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + + ov5647: ov5647@36 { + status = "disabled"; + compatible = "ovti,ov5647"; + reg = <0x36>; + + clocks = <&ext_cam_clk>; + clock-names = "ext_cam_clk"; + pwdn-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + + port { + ov5647_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + imx219: imx219@10 { + status = "disabled"; + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&ext_cam_clk_imx219>; + clock-names = "ext_cam_clk_imx219"; + pwdn-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5647_out>; + data-lanes = <1 2>; + }; + + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&rkisp_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy0_out>; + }; + }; +}; + +&rkisp { + status = "disabled"; +}; + +&rkisp_mmu { + status = "disabled"; +}; + +&rkcif_mmu { + status = "disabled"; +}; + +&rkcif { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-yy3568.dts b/arch/arm64/boot/dts/rockchip/rk3568-yy3568.dts new file mode 100644 index 0000000000000..0e95a6e2d29bd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-yy3568.dts @@ -0,0 +1,1273 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Youyeetoo YY3568"; + compatible = "youyeetoo,yy3568", "rockchip,rk3568"; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + leds { + compatible = "gpio-leds"; + + work-led { + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + work-led-1 { + gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <1800>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + }; + }; + + audiopwmout_diff: audiopwmout-diff { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + bt_sound: bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <0>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + compatible = "rockchip,multicodecs-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + rockchip,card-name = "rockchip-rk809"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + WIFI,poweren_gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + enable-active-high; + regulator-boot-on; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + enable-active-high; + regulator-boot-on; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + clock-names = "gpu", "bus"; + interrupt-names = "gpu", "mmu", "job"; + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi { + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs452x@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "okay"; + + mxc6655xa: mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + status = "okay"; +}; + +&i2s3_2ch { + pinctrl-0 = <&i2s3m0_sclk &i2s3m0_lrck &i2s3m0_sdi &i2s3m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1 { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm7 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + supports-emmc; + max-frequency = <200000000>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&spdifm1_tx>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&uart3m1_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4m1_xfer>; + status = "okay"; +}; + +&uart8 { + pinctrl-0 = <&uart8m0_xfer>; + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index bada80a16e9c9..999178a6f4479 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -331,25 +331,25 @@ /* RK3568 && RK3568M gpu OPPs */ opp-200000000 { - opp-supported-hw = <0xfb 0xffff>; + //opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <200000000>; opp-microvolt = <850000 850000 1000000>; }; opp-300000000 { - opp-supported-hw = <0xfb 0xffff>; + //opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <850000 850000 1000000>; }; opp-400000000 { - opp-supported-hw = <0xfb 0xffff>; + //opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <850000 850000 1000000>; }; opp-600000000 { - opp-supported-hw = <0xfb 0xffff>; + //opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <900000 900000 1000000>; opp-microvolt-L0 = <900000 900000 1000000>; @@ -359,7 +359,7 @@ }; opp-700000000 { - opp-supported-hw = <0xfb 0xffff>; + //opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <950000 950000 1000000>; opp-microvolt-L0 = <950000 950000 1000000>; @@ -369,7 +369,7 @@ }; opp-800000000 { - opp-supported-hw = <0xf9 0xffff>; + //opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1000000 1000000 1000000>; opp-microvolt-L0 = <1000000 1000000 1000000>; @@ -1258,13 +1258,13 @@ interrupts = , , ; - interrupt-names = "GPU", "MMU", "JOB"; + interrupt-names = "gpu", "mmu", "job"; upthreshold = <40>; downdifferential = <10>; clocks = <&scmi_clk 1>, <&cru CLK_GPU>; - clock-names = "clk_mali", "clk_gpu"; + clock-names = "gpu", "bus"; power-domains = <&power RK3568_PD_GPU>; #cooling-cells = <2>; operating-points-v2 = <&gpu_opp_table>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts new file mode 100644 index 0000000000000..a0dabd8d8dd79 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts @@ -0,0 +1,501 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3576-armsom-cm5.dtsi" +#include "rk3576-linux.dtsi" + +/ { + model = "ArmSoM CM5 IO"; + compatible = "armsom,cm5-io", "rockchip,rk3576"; + + /delete-node/ chosen; + + dp0_sound: dp0-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <512>; + rockchip,card-name = "rockchip-dp0"; + rockchip,cpu = <&spdif_tx3>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8388_sound: es8388-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8388-codec"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&es8388>; + }; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm2_8ch_6 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi"; + rockchip,cpu = <&sai6>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_device: vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_2v0_pldo_s3: vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v8_s0: vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_rtc_s5: vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren>; + }; + + vcc3v3_pcie0: vcc3v3-pcie0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi>; + clock-names = "hdmi0_phy_pll"; +}; + +&dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + + tx_delay = <0x21>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + //enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,sda-falling-delay-ns = <360>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m1_xfer>; + + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_mclk>; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + port { + usbc0_role_sw: endpoint { + remote-endpoint = <&usb_drd0_role_switch>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy_dp_altmode_mux>; + }; + }; + }; + + }; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&pcie0 { + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie0>; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2_8ch_6 { + status = "okay"; + pinctrl-0 = <&pwm2m2_ch6>; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&sai1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; +}; + +&sai6 { + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spdif_tx3 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy_dp { + status = "okay"; +}; + +&usbdp_phy_u3 { + status = "okay"; +}; + +&usb_drd0_dwc3 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + usb_drd0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; + vop-supply = <&vdd_logic_s0>; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + status = "okay"; +}; + +&vp2 { + status = "okay"; + assigned-clocks = <&cru DCLK_VP2_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-rpi-cm4-io.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-rpi-cm4-io.dts new file mode 100644 index 0000000000000..967c572763c9f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-rpi-cm4-io.dts @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3576-armsom-cm5.dtsi" +#include "rk3576-linux.dtsi" + +/ { + model = "ArmSoM CM5 CM4 IO"; + compatible = "armsom,cm5-cm4-io", "rockchip,rk3576"; + + /delete-node/ chosen; + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi"; + rockchip,cpu = <&sai6>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + label = "red"; + gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + active_led: active { + label = "green"; + gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_heartbeat>; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_device: vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_2v0_pldo_s3: vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v8_s0: vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_rtc_s5: vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie0: vcc3v3-pcie0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi>; + clock-names = "hdmi0_phy_pll"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + + tx_delay = <0x21>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + //enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,sda-falling-delay-ns = <360>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + + emc2301: emc2301@2f { + compatible = "microchip,emc2301"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #cooling-cells = <2>; + microchip,pwm-separate; + microchip,cooling-levels = <10>; + channel@0 { + reg = <0>; + pwm-min = <0>; + }; + }; + + pcf85063: pcf85063@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&pcie0 { + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie0>; + status = "okay"; +}; + +&pinctrl { + led { + led_heartbeat: led-heartbeat { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&sai1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; +}; + +&sai6 { + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spdif_tx3 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,sel-pipe-phystatus; + rockchip,dis-u2-susphy; + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdp_phy { + maximum-speed = "high-speed"; + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy_dp { + status = "okay"; +}; + +&usbdp_phy_u3 { + status = "okay"; +}; + +&usb_drd0_dwc3 { + status = "okay"; + dr_mode = "host"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; + vop-supply = <&vdd_logic_s0>; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + status = "okay"; +}; + +&vp2 { + status = "okay"; + assigned-clocks = <&cru DCLK_VP2_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi new file mode 100644 index 0000000000000..278ad59cea151 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3576.dtsi" +#include "rk3576-rk806.dtsi" + +/ { + model = "ArmSoM CM5 IO"; + compatible = "armsom,cm5", "rockchip,rk3576"; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_poweren_gpio>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4m1_rtsn>; + pinctrl-1 = <&uart4m1_rts_gpio>; + BT,power_gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + //BT,reset_gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + //BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "rtl8852bs"; + clocks = <&hym8563>; //如果使用hym8563，åªèƒ½é…置一个 + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpege { + status = "okay"; +}; + +&jpeg_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + uart4m1_rts_gpio: uart4m1-rts-gpio { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rga2_core0 { + status = "okay"; +}; + +&rga2_core0_mmu { + status = "okay"; +}; + +&rga2_core1 { + status = "okay"; +}; + +&rga2_core1_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; + +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + + rockchip,sleep-io-ret-config = < + (0 + | RKPM_VCCIO3_RET_EN + ) + >; + + rockchip,regulator-on-before-mem = <&vdd_npu_s0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdio { + max-frequency = <200000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1m0_bus4 &sdmmc1m0_clk &sdmmc1m0_cmd>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>; +}; + +&vdpp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts new file mode 100644 index 0000000000000..c9093c5a9d1a1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -0,0 +1,1193 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "rk3576.dtsi" +#include "rk3576-rk806.dtsi" +#include "rk3576-linux.dtsi" + +/ { + model = "ArmSoM Sige5"; + compatible = "armsom,sige5", "rockchip,rk3576"; + + /delete-node/ chosen; + + dp0_sound: dp0-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <512>; + rockchip,card-name = "rockchip-dp0"; + rockchip,cpu = <&spdif_tx3>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8388-codec"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&es8388>; + }; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1_6ch_1 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm2_8ch_7 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi"; + rockchip,cpu = <&sai6>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_poweren_gpio>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_device: vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_2v0_pldo_s3: vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_rtc_s5: vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + vcc_1v8_s0: vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc1v8_ufs_vccq2_s0: vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc1v2_ufs_vccq_s0: vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + }; + + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_bl_n: vcc3v3-bl-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bl_n"; + regulator-boot-on; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "rtl8852bs"; + clocks = <&hym8563>; //如果使用hym8563，åªèƒ½é…置一个 + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi>; + clock-names = "hdmi0_phy_pll"; +}; + +&dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + + tx_delay = <0x21>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð1m0_miim + ð1m0_tx_bus2 + ð1m0_rx_bus2 + ð1m0_rgmii_clk + ð1m0_rgmii_bus + ðm0_clk1_25m_out>; + + tx_delay = <0x20>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,sda-falling-delay-ns = <360>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi { + status = "okay"; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc_lcd_mipi1>; + reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + backlight = <&dsi1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 B0 01 + 15 00 02 C0 26 + 15 00 02 C1 10 + 15 00 02 C2 0E + 15 00 02 C3 00 + 15 00 02 C4 00 + 15 00 02 C5 23 + 15 00 02 C6 11 + 15 00 02 C7 22 + 15 00 02 C8 20 + 15 00 02 C9 1E + 15 00 02 CA 1C + 15 00 02 CB 0C + 15 00 02 CC 0A + 15 00 02 CD 08 + 15 00 02 CE 06 + 15 00 02 CF 18 + 15 00 02 D0 02 + 15 00 02 D1 00 + 15 00 02 D2 00 + 15 00 02 D3 00 + 15 00 02 D4 26 + 15 00 02 D5 0F + 15 00 02 D6 0D + 15 00 02 D7 00 + 15 00 02 D8 00 + 15 00 02 D9 23 + 15 00 02 DA 11 + 15 00 02 DB 21 + 15 00 02 DC 1F + 15 00 02 DD 1D + 15 00 02 DE 1B + 15 00 02 DF 0B + 15 00 02 E0 09 + 15 00 02 E1 07 + 15 00 02 E2 05 + 15 00 02 E3 17 + 15 00 02 E4 01 + 15 00 02 E5 00 + 15 00 02 E6 00 + 15 00 02 E7 00 + 15 00 02 B0 03 + 15 00 02 BE 04 + 15 00 02 B9 40 + 15 00 02 CC 88 + 15 00 02 C8 0C + 15 00 02 C9 07 + 15 00 02 CD 01 + 15 00 02 CA 40 + 15 00 02 CE 1A + 15 00 02 CF 60 + 15 00 02 D2 08 + 15 00 02 D3 08 + 15 00 02 DB 01 + 15 00 02 D9 06 + 15 00 02 D4 00 + 15 00 02 D5 01 + 15 00 02 D6 04 + 15 00 02 D7 03 + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 C2 00 + 15 00 02 C3 0E + 15 00 02 C4 00 + 15 00 02 C5 0E + 15 00 02 DD 00 + 15 00 02 DE 0E + 15 00 02 E6 00 + 15 00 02 E7 0E + 15 00 02 B0 06 + 15 00 02 C0 A5 + 15 00 02 D5 1C + 15 00 02 C0 00 + 15 00 02 B0 00 + 15 00 02 BD 30 + + 15 00 02 F9 5C + 15 00 02 C2 14 + 15 00 02 C4 14 + 15 00 02 BF 15 + 15 00 02 C0 0C + + + 15 00 02 B0 00 + 15 00 02 B1 79 + 15 00 02 BA 8F + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 32 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hfront-porch = <80>; + hsync-len = <1>; + hback-porch = <60>; + vfront-porch = <35>; + vsync-len = <1>; + vback-porch = <25>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&mipidcphy0 { + status = "okay"; +}; + +&route_dsi { + status = "disabled"; +}; + +&dsi_in_vp1 { + status = "okay"; +}; + +&vp1 { + assigned-clocks = <&cru DCLK_VP1_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0m1_xfer>; + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD1 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <89>; + tp-supply = <&vcc_lcd_mipi1>; + + configfile-num = <1>; + }; + + usbc1: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc1_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + altmodes { + #address-cells = <1>; + #size-cells = <0>; + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + + port { + usbc0_role_sw: endpoint { + remote-endpoint = <&usb_drd0_role_switch>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_mclk>; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpege { + status = "okay"; +}; + +&jpeg_mmu { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC1_OUT>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie0 { + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake: bt-host-wake { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_rgb_r: led-red-en { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_g: led-green-en { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usbc1_int: usbc1-int { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = + <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1_6ch_1 { + status = "okay"; + pinctrl-0 = <&pwm1m0_ch1>; +}; + +&pwm2_8ch_7 { + status = "okay"; + pinctrl-0 = <&pwm2m3_ch7>; +}; + +&rga2_core0 { + status = "okay"; +}; + +&rga2_core0_mmu { + status = "okay"; +}; + +&rga2_core1 { + status = "okay"; +}; + +&rga2_core1_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; + +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + + rockchip,sleep-io-ret-config = < + (0 + | RKPM_VCCIO3_RET_EN + ) + >; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&sai1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; +}; + +&sai6 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1m0_bus4 &sdmmc1m0_clk &sdmmc1m0_cmd>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + non-removable; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spdif_tx3 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn &uart4m1_rtsn>; + uart-has-rtscts; + bluetooth { + compatible = "brcm,bcm43438-bt"; + device-wakeup-gpios = <&gpio1 RK_PD4 0>; + host-wakeup-gpios = <&gpio0 RK_PB1 0>; + shutdown-gpios = <&gpio1 RK_PC7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + +&ufs { + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbdp_phy { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy_dp { + status = "okay"; +}; + +&usbdp_phy_u3 { + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + usb_drd0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vop { + status = "okay"; + /* vop-supply = <&vdd_logic_s0>; */ +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + status = "okay"; +}; + +&vp2 { + assigned-clocks = <&cru DCLK_VP2_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge-rk628-hdmi2csi.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge-rk628-hdmi2csi.dtsi new file mode 100644 index 0000000000000..e3fbaf2469361 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge-rk628-hdmi2csi.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/ { + rk628f_dc: rk628f-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + rkvtunnel: rkvtunnel { + compatible = "rockchip,video-tunnel"; + status = "okay"; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&sai4>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&rk628f_dc>; + }; + }; + + //vcc_mipicsi1: vcc-mipicsi1-regulator { + // compatible = "regulator-fixed"; + // gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + // pinctrl-names = "default"; + // pinctrl-0 = <&mipicsi1_pwr>; + // regulator-name = "vcc_mipicsi1"; + // enable-active-high; + //}; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmiin_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + pinctrl-0 = <&i2c5m3_xfer>; + clock-frequency = <100000>; + //clock-frequency = <400000>; + + rk628_csi: rk628_csi@51 { + reg = <0x51>; + compatible = "rockchip,rk628-csi-v4l2"; + status = "okay"; + //clocks = <&cru REF_CLK0_OUT_PLL>; + //clock-names = "xvclk"; + pinctrl-names = "default"; + //pinctrl-0 = <&rk628_hdmiin_pin &ref_clk0_clk0>; + pinctrl-0 = <&rk628_hdmiin_pin>; + power-domains = <&power RK3576_PD_VI>; + interrupt-parent = <&gpio4>; + interrupts = ; + enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + plugin-det-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + continues-clk = <1>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HDMI-MIPI1"; + rockchip,camera-module-lens-name = "RK628-CSI"; + + multi-dev-info { + dev-idx-l = <1>; + dev-idx-r = <3>; + combine-idx = <1>; + pixel-offset = <0>; + dev-num = <2>; + }; + + port { + hdmiin_out: endpoint { + remote-endpoint = <&hdmi_mipi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&sai4 { + pinctrl-names = "default"; + pinctrl-0 = <&sai4m0_lrck + &sai4m0_sclk + &sai4m0_sdi>; + status = "okay"; +}; + +&pinctrl { + hdmiin { + //mipicsi1_pwr: mipicsi1-pwr { + // rockchip,pins = + // /* 628H camera power en */ + // <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + //}; + + rk628_hdmiin_pin: rk628-hdmiin-pin { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge-v10.dts new file mode 100644 index 0000000000000..f0319c3b418c1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge-v10.dts @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + + +#include +#include +#include +#include +#include +#include +#include +#include "rk3576.dtsi" +#include "rk3576-blueberry-edge.dtsi" +#include "rk3576-blueberry-edge-rk628-hdmi2csi.dtsi" +#include "rk3576-linux.dtsi" + +/ { + model = "Blueberry RK3576 EDGE V10 Board"; + compatible = "blueberry,rk3576-edge-v10", "rockchip,rk3576"; + /delete-node/ chosen; + + + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s0>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1_6ch_1 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + +&dsi { + //rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <60>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 00 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +/* + * mipidcphy0 needs to be enabled + * when dsi is enabled + */ +&dsi { + status = "disabled"; +}; + +&mipidcphy0 { + status = "okay"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; +}; + +&dsi_in_vp1 { + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&pwm1_6ch_1 { + status = "okay"; + pinctrl-0 = <&pwm1m0_ch1>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m1_xfer>; + status = "okay"; + + gt1x: gt1x@14 { + status = "disabled"; + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl { + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + +//Note. rk3576 gpio control +//GPio out +//GPIO4_B0_OUT1 +// echo 136 > /sys/class/gpio/export +// echo out > /sys/class/gpio/gpio136/direction +// echo 1 > /sys/class/gpio/gpio136/value +//GPIO4_B2_OUT2 +// echo 138 > /sys/class/gpio/export +// echo out > /sys/class/gpio/gpio138/direction +// echo 1 > /sys/class/gpio/gpio138/value + +//RS485_Ctrl GPIO3_A3 +// echo 99 > /sys/class/gpio/export +// echo out > /sys/class/gpio/gpio99/direction +// echo 1 > /sys/class/gpio/gpio99/value + +//Gpio input +//GPIO3_D0_IN1 +// echo 130 > /sys/class/gpio/export +// echo in > /sys/class/gpio/gpio130/direction +// can /sys/class/gpio/gpio130/value +//GPIO3_D4_IN2 +// echo 124 > /sys/class/gpio/export +// echo in > /sys/class/gpio/gpio124/direction +// cat /sys/class/gpio/gpio124/value diff --git a/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge.dtsi new file mode 100644 index 0000000000000..f5e68e459262e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-blueberry-edge.dtsi @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3576.dtsi" +#include "rk3576-blueberry.dtsi" +#include "rk3576-rk806.dtsi" + +/ { + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + spk-con-gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + //hp-con-gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai1>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm1>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_poweren_gpio>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + vcc_1v8_s0: vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc1v8_ufs_vccq2_s0: vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc1v2_ufs_vccq_s0: vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie0: vcc3v3-pcie0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren>; + }; + + //vcc_mipicsi0: vcc-mipicsi0-regulator { + // compatible = "regulator-fixed"; + // gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + // pinctrl-names = "default"; + // pinctrl-0 = <&mipicsi0_pwr>; + // regulator-name = "vcc_mipicsi0"; + // enable-active-high; + //}; + + //vcc_mipidcphy0: vcc-mipidcphy0-regulator { + // compatible = "regulator-fixed"; + // gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + // pinctrl-names = "default"; + // pinctrl-0 = <&mipidcphy0_pwr>; + // regulator-name = "vcc_mipidcphy0"; + // enable-active-high; + //}; + + modem { + compatible = "rockchip,modem"; + status = "okay"; + power-on_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + reset_gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; //GPIO_C4 + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4m1_rtsn>; + pinctrl-1 = <&uart4_gpios>; + BT,reset_gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,vbat_gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + //WIFI,poweren_gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + + tx_delay = <0x21>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð1m0_miim + ð1m0_tx_bus2 + ð1m0_rx_bus2 + ð1m0_rgmii_clk + ð1m0_rgmii_bus + ðm0_clk1_25m_out>; + + tx_delay = <0x20>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,sda-falling-delay-ns = <360>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + usbc0: husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + port { + usbc0_role_sw: endpoint { + remote-endpoint = <&usb_drd0_role_switch>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_mclk>; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC1_OUT>; + }; +}; + +&pcie0 { + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie0>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pdm1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm1m1_clk0 + &pdm1m1_clk1 + &pdm1m1_sdi0 + &pdm1m1_sdi1 + &pdm1m1_sdi2 + &pdm1m1_sdi3>; +}; + +&pinctrl { + cam { + //mipicsi0_pwr: mipicsi0-pwr { + // rockchip,pins = + // /* camera power en */ + // <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + //}; + + //mipidcphy0_pwr: mipidcphy0-pwr { + // rockchip,pins = + // /* camera power en */ + // <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + //}; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + uart4_gpios: uart4-gpios { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&sai1 { + status = "okay"; + rockchip,sai-tx-route = <1 2 0 3>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo2>; +}; + +&sdio { + max-frequency = <200000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1m0_bus4 &sdmmc1m0_clk &sdmmc1m0_cmd>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>; +}; + +&uart5 { + status = "okay"; + //RS485_Ctrl gpio3_a3 pin99 + pinctrl-names = "default"; + pinctrl-0 = <&uart5m2_xfer>; + linux,rs485-enabled-at-boot-time; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usb_drd0_dwc3 { + dr_mode = "otg"; + usb-role-switch; + port { + usb_drd0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vp0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-blueberry.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-blueberry.dtsi new file mode 100644 index 0000000000000..179345108283a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-blueberry.dtsi @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rk3576-evb-input-keymap.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <512>; + rockchip,card-name = "rockchip-dp0"; + rockchip,cpu = <&spdif_tx3>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <512>; + rockchip,card-name = "rockchip-dp1"; + rockchip,cpu = <&spdif_tx3>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + dp2_sound: dp2-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <512>; + rockchip,card-name = "rockchip-dp2"; + rockchip,cpu = <&spdif_tx3>; + rockchip,codec = <&dp2 1>; + rockchip,jack-det; + }; + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi"; + rockchip,cpu = <&sai6>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_device: vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_2v0_pldo_s3: vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_rtc_s5: vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi>; + clock-names = "hdmi0_phy_pll"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpege { + status = "okay"; +}; + +&jpeg_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rga2_core0 { + status = "okay"; +}; + +&rga2_core0_mmu { + status = "okay"; +}; + +&rga2_core1 { + status = "okay"; +}; + +&rga2_core1_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; + +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + + rockchip,sleep-io-ret-config = < + (0 + | RKPM_VCCIO3_RET_EN + ) + >; +}; + +&sai6 { + status = "okay"; +}; + +&spdif_tx3 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&ufs { + status = "okay"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; +}; + +&usbdp_phy { + status = "okay"; +}; + +&usbdp_phy_dp { + status = "okay"; +}; + +&usbdp_phy_u3 { + status = "okay"; +}; + +&usb_drd0_dwc3 { + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vop { + status = "okay"; + vop-supply = <&vdd_logic_s0>; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp2 { + assigned-clocks = <&cru DCLK_VP2_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index f865fcc9eab9d..d772b29b3644f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1984,7 +1984,9 @@ /* These power domains are grouped by VD_GPU */ power-domain@RK3576_PD_GPU { reg = ; + clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; /* These power domains are grouped by VD_LOGIC */ power-domain@RK3576_PD_NVM { @@ -2282,13 +2284,13 @@ interrupts = , , ; - interrupt-names = "GPU", "MMU", "JOB"; + interrupt-names = "gpu", "mmu", "job"; upthreshold = <40>; downdifferential = <10>; - clocks = <&scmi_clk CLK_GPU>, <&cru CLK_GPU>; - clock-names = "clk_mali", "clk_gpu"; + clocks = <&cru CLK_GPU>; + clock-names = "core"; assigned-clocks = <&cru CLK_GPU>; assigned-clock-rates = <198000000>; power-domains = <&power RK3576_PD_GPU>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-aim7-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-aim7-io.dts new file mode 100644 index 0000000000000..3adbd078382b4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-aim7-io.dts @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Jianfeng Liu + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588-armsom-aim7.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "ArmSoM AIM7 IO"; + compatible = "armsom,aim7-io", "rockchip,rk3588"; + + /delete-node/ chosen; + + dp0_sound: dp0-sound { + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + pinctrl-names = "default"; + pinctrl-0 = <&dp0m2_pins>; + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x43>; + + phy-handle = <&rgmii_phy>; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_clkreqn_m1>; + status = "okay"; +}; + +&pinctrl { + pcie3 { + pcie3_clkreqn_m1: pcie3-clkreqn-m1 { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vcc3v3_pcie30_en: pcie3-reg { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&usbhost3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-aim7.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-armsom-aim7.dtsi new file mode 100644 index 0000000000000..611e8d90f8a24 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-aim7.dtsi @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Jianfeng Liu + * + */ + +#include +#include +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + model = "ArmSoM AIM7 "; + compatible = "armsom,aim7", "rockchip,rk3588"; + +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts new file mode 100755 index 0000000000000..434f9f6107ec7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -0,0 +1,1010 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Rockchip rk3588-evb7-v11, Lhd. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "ArmSom RK3588 sige7 Board"; + compatible = "rockchip,rk3588-armsom-sige7", "rockchip,rk3588"; + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm1 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmi0_sound: hdmi0-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + label = "red"; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + default-state = "off"; + }; + + active_led: active { + label = "green"; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + default-state = "on"; + }; + }; + + es8316_sound: es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-es8316"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8316>; + }; + }; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys >; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>,<&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dp0 { + status = "okay"; +}; +&dp0_in_vp2 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + usbc1: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc1_int>; + //vbus-supply = <&vcc12v_dcin>; + vbus-supply = <&vcc5v0_usbdcin>; + status = "okay"; + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + //vbus-supply = <&vcc12v_dcin>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c7 { + status = "okay"; + i2c-scl-rising-time-ns = <265>; + i2c-scl-falling-time-ns = <26>; + clock-frequency = <400000>; + + es8316: es8316@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + status = "okay"; + +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usbc1_int: usbc1-int { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +}; + +&pwm1 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts new file mode 100644 index 0000000000000..1310bc220353e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts @@ -0,0 +1,1186 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 bananapi Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "armsom w3"; + compatible = "rockchip,rk3588-armsom-w3", "rockchip,rk3588"; + + /delete-node/ chosen; + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc_5v0_en: vcc-5v0-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_en"; + enable-active-high; + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_pwren>; + regulator-boot-on; + regulator-always-on; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + bt_uart6: wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-es8316"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8316>; + }; + }; + }; + + rk_headset: rk-headset { + status = "okay"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_b>; + + led_rgb_b { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + led_rgb_r { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + //mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&display_subsystem { + route { + route_hdmi0: route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi0>; + }; + + route_hdmi1: route-hdmi1 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_hdmi1>; + }; + }; +}; + +&hdmi0 { + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + cec-enable = "true"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + //vbus-supply = <&vcc12v_dcin>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c7 { + status = "okay"; + i2c-scl-rising-time-ns = <265>; + i2c-scl-falling-time-ns = <26>; + clock-frequency = <400000>; + + es8316: es8316@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + vcc-supply { + vcc_5v0_pwren: vcc-5v0-pwren { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + typec5v_pwren: typec5v-pwren { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-bananapi-m7.dts b/arch/arm64/boot/dts/rockchip/rk3588-bananapi-m7.dts new file mode 100644 index 0000000000000..8489240ab8bd7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-bananapi-m7.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588-armsom-sige7.dts" + +/ { + model = "Banana Pi M7"; + compatible = "bananapi,m7", "rockchip,rk3588"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts new file mode 100644 index 0000000000000..e90aad5665c03 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts @@ -0,0 +1,1048 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Mixtile Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Mixtile Blade 3 v1.0.1"; + compatible = "rockchip,rk3588-blade3-v101-linux", "rockchip,rk3588"; + /delete-node/ chosen; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + }; + + vbus5v0_typec0: vbus5v0-typec0 { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren0>; + }; + + vbus5v0_typec1: vbus5v0-typec1 { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren1>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + + interrupt-parent = <&gpio3>; + interrupts = ; + pulses-per-revolution = <2>; + + #cooling-cells = <2>; + pwms = <&pwm8 0 250000 0>; + cooling-levels = <0 35 70 100 125 150>; + rockchip,temp-trips = < + 30000 1 + 45000 2 + 50000 3 + 55000 4 + 60000 5 + >; + }; +}; + +/*&pwrkey { + status = "disabled"; +};*/ + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = <0x4000024>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + status = "okay"; + rockchip,typec-vbus-det; +}; + +&u2phy2_host { // 30PIN GPIO + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost3_0 { // miniPCIe combo + status = "disable"; +}; + +&usbhost_dwc3_0 { // miniPCIe combo + status = "disable"; +}; + +&usbdp_phy0 { + status = "okay"; + + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp0_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; + + orientation-switch; + svid = <0xff01>; // linux/usb/typec_dp.h:USB_TYPEC_DP_SID + sbu1-dc-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy1_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_orien_sw>; + }; + + usbdp_phy1_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp1_altmode_mux>; + }; + }; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_1_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_role_sw>; + }; + }; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&dp1 { + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + usbc1: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc1_int>; + vbus-supply = <&vbus5v0_typec1>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc1_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_1_role_switch>; + }; + }; + }; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + faster-pd-negotiation; + op-sink-microwatt = <15000000>; + sink-pdos = + // ; + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc1_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy1_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp1_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy1_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c4 { // U.2 port + status = "okay"; + pinctrl-0 = <&i2c4m0_xfer>; +}; + +&i2c6 { // USB Type-C 0 + status = "okay"; + pinctrl-0 = <&i2c6m0_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con0: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp0_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c5 { // 30PIN GPIO + status = "okay"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&pwm8 { // 30PIN GPIO + pinctrl-names = "active"; + status = "okay"; + pinctrl-0 = <&pwm8m2_pins>; +}; + +&pwm14 { // 30PIN GPIO + status = "okay"; + pinctrl-0 = <&pwm14m2_pins>; +}; + +&pwm15 { // 30PIN GPIO + status = "disabled"; + pinctrl-0 = <&pwm15m3_pins>; +}; + +&spi4 { // 30PIN GPIO + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>; + num-cs = <1>; +}; + +&i2s2_2ch { // 30PIN GPIO + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_mclk + &i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; +}; + +&can2 { // 30PIN GPIO + status = "okay"; +}; + +&pcie2x1l0 { // combphy1, to ASM1182e + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l1 { // combphy2, to miniPCIe socket + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { +rockchip,pcie30-phymode = ; /* P1:PCIe3x2 + P0:PCIe3x2 */ +status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usbc1_int: usbc1-int { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren0: typec5v-pwren0 { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + typec5v_pwren1: typec5v-pwren1 { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts new file mode 100644 index 0000000000000..db3028981f133 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10-linux.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-edge-v10.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Mekotronics R58X (RK3588 EDGE LP4x V1.0 BlueBerry Board)"; + compatible = "rockchip,rk3588-blueberry-edge-v10-linux", "rockchip,rk3588"; + /delete-node/ chosen; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xd8 KEY_BACK>, + <0xc7 KEY_UP>, + <0xbf KEY_DOWN>, + <0xc8 KEY_LEFT>, + <0xc6 KEY_RIGHT>, + <0x8c KEY_HOME>, + <0x78 KEY_VOLUMEUP>, + <0x76 KEY_VOLUMEDOWN>, + <0x7e KEY_POWER>, + <0xed KEY_POWER>, //20171123 + <0x7c KEY_MENU>, + <0xb7 388>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi new file mode 100644 index 0000000000000..ff28e52af7687 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-blueberry.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + i2s0_sound: i2s0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8311"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8311>; + }; + }; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + wifi_led: wifi-led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_led: eth-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + //gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + vk2c21_lcd { + compatible = "lcd_vk2c21"; + i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + + status = "disabled"; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 + startup-delay-us = <10000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&dp1 { + pinctrl-0 = <&dp1m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&dp1_sound{ + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + cec-enable = "true" ; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; //gpio1_d5 +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8311: es8311@18 { + status = "okay"; + compatible = "everest,es8311"; + reg = <0x18>; + #sound-dai-cells = <0>; + adc-pga-gain = <6>; /* 18dB */ + adc-volume = <0xbf>; /* 0dB */ + dac-volume = <0xbf>; /* 0dB */ + aec-mode = "adc left, adc right"; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +//hdmi01 sound +&i2s5_8ch { + status = "okay"; +}; + +//hdmi02 sound +&i2s6_8ch { + status = "okay"; +}; + +//hdmiin sound +&i2s7_8ch { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_dp1 { + status = "okay"; + connect = <&vp2_out_dp1>; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&sata0 { + status = "okay"; +}; + +//rs485 +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +//rs232 +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + + +&pinctrl { + + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + //rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; +}; + +//type-c0 +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +//usb2.0 host0 +&u2phy2 { + status = "okay"; +}; + +//usb2.0 host1 +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts new file mode 100644 index 0000000000000..01d0dd5cdf210 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-linux.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-edge-v12.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Mekotronics R58X-4G (RK3588 EDGE LP4x V1.2 BlueBerry Board)"; + compatible = "rockchip,rk3588-blueberry-edge-v12-linux", "rockchip,rk3588"; + /delete-node/ chosen; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xd8 KEY_BACK>, + <0xc7 KEY_UP>, + <0xbf KEY_DOWN>, + <0xc8 KEY_LEFT>, + <0xc6 KEY_RIGHT>, + <0x8c KEY_HOME>, + <0x78 KEY_VOLUMEUP>, + <0x76 KEY_VOLUMEDOWN>, + <0x7e KEY_POWER>, + <0xed KEY_POWER>, //20171123 + <0x7c KEY_MENU>, + <0xb7 388>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-maizhuo-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-maizhuo-linux.dts new file mode 100644 index 0000000000000..c50ad4456d346 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-maizhuo-linux.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-edge-v12.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "RK3588 EDGE LP4x V1.2 MeiZhuo BlueBerry Board"; + compatible = "rockchip,rk3588-blueberry-edge-v12-linux", "rockchip,rk3588"; + /delete-node/ chosen; + + vk2c21_lcd { + compatible = "lcd_vk2c21"; + i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + + status = "okay";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; + }; +}; + +&gpio_keys{ + vol_up { + debounce-interval = <0>; + autorepeat = <1>; + gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + label = "GPIO Key Vol+"; + linux,code = ; + wakeup-source; + }; + + vol_down { + debounce-interval = <0>; + autorepeat = <1>; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + label = "GPIO Key Vol-"; + linux,code = ; + wakeup-source; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi new file mode 100644 index 0000000000000..3da66e7dded0e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi @@ -0,0 +1,900 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-blueberry.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + //hp-det-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + wifi_led: wifi-led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_led: eth-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + //linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + //gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + vk2c21_lcd { + compatible = "lcd_vk2c21"; + i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + + status = "disabled";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 + startup-delay-us = <10000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + modem { + compatible = "rockchip,modem"; + status = "okay"; + power-on_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; //GPIO_C4 + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "disable"; +}; + +//&dp0_in_vp2 { +// status = "okay"; +//}; + +&dp1 { + pinctrl-0 = <&dp1m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&dp1_sound{ + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + cec-enable = "true" ; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; //gpio1_d5 + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +//hdmi01 sound +&i2s5_8ch { + status = "okay"; +}; + +//hdmi02 sound +&i2s6_8ch { + status = "okay"; +}; + +//hdmiin sound +&i2s7_8ch { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_dp1 { + status = "okay"; + connect = <&vp2_out_dp1>; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&sata0 { + status = "okay"; +}; + +//rs485 +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +//rs232 +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + + +&pinctrl { + + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + //rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; +}; + +//type-c0 +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +//usb2.0 host0 +&u2phy2 { + status = "okay"; +}; + +//usb2.0 host1 +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14-linux.dts new file mode 100644 index 0000000000000..2332aeb23d05f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14-linux.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-edge-v14.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "RK3588 EDGE LP4x V1.4 BlueBerry Board"; + compatible = "rockchip,rk3588-blueberry-edge-v14-linux", "rockchip,rk3588"; + /delete-node/ chosen; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xd8 KEY_BACK>, + <0xc7 KEY_UP>, + <0xbf KEY_DOWN>, + <0xc8 KEY_LEFT>, + <0xc6 KEY_RIGHT>, + <0x8c KEY_HOME>, + <0x78 KEY_VOLUMEUP>, + <0x76 KEY_VOLUMEDOWN>, + <0x7e KEY_POWER>, + <0xed KEY_POWER>, //20171123 + <0x7c KEY_MENU>, + <0xb7 388>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14.dtsi new file mode 100644 index 0000000000000..862376cd61f47 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14.dtsi @@ -0,0 +1,1063 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-blueberry.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + //hp-det-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + + leds: leds { + compatible = "gpio-leds"; + wifi_led: wifi-led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_led: eth-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + //linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + //gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + vk2c21_lcd { + compatible = "lcd_vk2c21"; + i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + + status = "disabled";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 + startup-delay-us = <10000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + modem { + compatible = "rockchip,modem"; + status = "okay"; + power-on_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; //GPIO_C4 + }; + + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "CLK_CAMERA_24MHZ"; + #clock-cells = <0>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "disable"; +}; + +//&dp0_in_vp2 { +// status = "okay"; +//}; + +&dp1 { + pinctrl-0 = <&dp1m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&dp1_sound{ + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + cec-enable = "true" ; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +/* lt6911 hdmi in */ +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_lt6911: endpoint@1 { + reg = <1>; + remote-endpoint = <<6911_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + status = "okay"; + + lt6911:lt6911@2b { + compatible = "lontium,lt6911uxc"; + status = "okay"; + reg = <0x2b>; + clocks = <&ext_cam_clk>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <<6911uxc_pin>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; + plugin-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "lt6911"; + rockchip,camera-module-lens-name = "default"; + port { + lt6911_out: endpoint { + remote-endpoint = <&mipi_in_lt6911>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +/* lt6911 hdmi in end */ + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "disabled"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; //gpio1_d5 + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +//hdmi01 sound +&i2s5_8ch { + status = "okay"; +}; + +//hdmi02 sound +&i2s6_8ch { + status = "okay"; +}; + +//hdmiin sound +&i2s7_8ch { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_dp1 { + status = "okay"; + connect = <&vp2_out_dp1>; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&sata0 { + status = "okay"; +}; + +//rs485 +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +//rs232 +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + + +&pinctrl { + + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + //rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmiin { + lt6911uxc_pin: lt6911uxc-pin { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; +}; + +//type-c0 +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +//usb2.0 host0 +&u2phy2 { + status = "okay"; +}; + +//usb2.0 host1 +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts new file mode 100644 index 0000000000000..d94829d0d5b9d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-linux.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-minipc.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Mekotronics R58 MiniPC (RK3588 MINIPC LP4x V1.0 BlueBerry Board)"; + compatible = "rockchip,rk3588-blueberry-minipc-linux", "rockchip,rk3588"; + /delete-node/ chosen; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xd8 KEY_BACK>, + <0xc7 KEY_UP>, + <0xbf KEY_DOWN>, + <0xc8 KEY_LEFT>, + <0xc6 KEY_RIGHT>, + <0x8c KEY_HOME>, + <0x78 KEY_VOLUMEUP>, + <0x76 KEY_VOLUMEDOWN>, + <0x7e KEY_POWER>, + <0xed KEY_POWER>, //20171123 + <0x7c KEY_MENU>, + <0xb7 388>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-mizhuo-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-mizhuo-linux.dts new file mode 100644 index 0000000000000..368e4ff2c94bf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc-mizhuo-linux.dts @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-blueberry-minipc.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "RK3588 MINIPC-MIZHUO LP4x V1.0 BlueBerry Board"; + compatible = "rockchip,rk3588-blueberry-minipc-linux", "rockchip,rk3588"; + /delete-node/ chosen; +}; + +&work_led { + linux,default-trigger = "default-on"; //"timer"; + default-state = "on"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { //hugsun blue remote ��mizhuo�� + rockchip,usercode = <0x7f80>; + rockchip,key_table = + <0xec KEY_F11>, + <0xd8 KEY_F2>, + <0xc7 KEY_F7>, + <0xbf KEY_F8>, + <0xc8 KEY_F9>, + <0xc6 KEY_F10>, + <0x8c KEY_F1>, + <0x78 KEY_F6>, + <0x76 KEY_F4>, + <0x7e KEY_F12>, + <0x7c KEY_F3>, + <0xb7 KEY_F5>; + }; + + ir_key2 { //hugsun + rockchip,usercode = <0xef10>; + rockchip,key_table = + <0xa2 KEY_POWER>, + <0xe8 KEY_VOLUMEUP>, + <0xec KEY_VOLUMEDOWN>, + <0xa6 141>,//KEY_SETUP>, + <0xa5 388>, + <0xff KEY_BACK>, + <0xba KEY_UP>, + <0xf8 KEY_LEFT>, + <0xbe KEY_REPLY>, + <0xfe KEY_RIGHT>, + <0xaa KEY_DOWN>, + <0xb9 KEY_HOME>, + <0xfa KEY_MENU>, + <0xe5 KEY_REWIND>, + <0xa7 KEY_PLAYPAUSE>, + <0xe2 KEY_FASTFORWARD>, + <0xa0 77>, //@ + <0xb0 KEY_0>, + <0xa1 14>, + <0xaf KEY_1>, + <0xad KEY_2>, + <0xef KEY_3>, + <0xb3 KEY_4>, + <0xb5 KEY_5>, + <0xee KEY_6>, + <0xf0 KEY_7>, + <0xb1 KEY_8>, + <0xf2 KEY_9>; + }; + + ir_key3 { + rockchip,usercode = <0xdf00>; + rockchip,key_table = + <0xe3 KEY_POWER>, + <0xb4 63>, //youtube + <0xfe 67>, //Media Center + <0xa2 KEY_VOLUMEUP>, + <0xb0 66>, //Netflix + <0xa0 68>, //SetupWizard + <0xa3 KEY_VOLUMEDOWN>, + + <0xbd KEY_HOME>, + <0xf5 KEY_BACK>, + + <0xe5 KEY_UP>, + <0xb8 KEY_LEFT>, + <0xf9 KEY_REPLY>, + <0xf8 KEY_RIGHT>, + <0xb7 KEY_DOWN>, + <0xfc 388>, + <0xe7 KEY_MENU>, + + <0xab KEY_1>, + <0xe9 KEY_2>, + <0xea KEY_3>, + <0xaf KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0xb3 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xbe 227>, //Fn + <0xf3 KEY_0>, + <0xef 14>; + + }; + + ir_key4{ + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0x4d KEY_POWER>; //power (for 2.4g) + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc.dtsi new file mode 100644 index 0000000000000..72de6d6ba54d5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-minipc.dtsi @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-blueberry.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + wifi_led: wifi-led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_led: eth-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,reset_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "disable"; +}; + +//&dp0_in_vp1 { +// status = "okay"; +//}; + +&dp1 { + pinctrl-0 = <&dp1m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp1 { + status = "okay"; +}; + +&dp1_sound{ + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + cec-enable = "true" ; + hdcp1x-enable; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + cec-enable = "true" ; + hdcp1x-enable; + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; //gpio1_d5 +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +//hdmi01 sound +&i2s5_8ch { + status = "okay"; +}; + +//hdmi02 sound +&i2s6_8ch { + status = "okay"; +}; + +//hdmiin sound +&i2s7_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&wdt { + status = "okay"; +}; + +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&route_hdmi1 { + status = "okay"; + connect = <&vp2_out_hdmi1>; +}; + +&sata0 { + status = "okay"; +}; + +//rs485 +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +//rs232 +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + + +&pinctrl { + + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +//type-c0 +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +//usb2.0 host0 +&u2phy2 { + status = "okay"; +}; + +//usb2.0 host1 +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry.dtsi new file mode 100644 index 0000000000000..75e9947e59144 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry.dtsi @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rk3588-cpu-swap.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + test-power { + status = "okay"; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&CPU_SLEEP { + status = "disabled"; +}; + +&cluster0_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cluster1_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cluster2_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&gpu_opp_table { + /delete-node/ opp-198000000; + /delete-node/ opp-297000000; + /delete-node/ opp-396000000; + /delete-node/ opp-500000000; + /delete-node/ opp-1000000000; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-cyber-aib.dts b/arch/arm64/boot/dts/rockchip/rk3588-cyber-aib.dts new file mode 100644 index 0000000000000..f7e9c1db92997 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-cyber-aib.dts @@ -0,0 +1,1283 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Cyber RD Group + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Cyber 3588 AIB"; + compatible = "cyber,cyber3588-aib", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + wwan_disable: wwan-disable-regulator { + compatible = "regulator-fixed"; + regulator-name = "wwan_disable"; + enable-active-high; + gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wwan_disable_h>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-always-on; + }; + + wwan_power_off: wwan-power-off-regulator { + compatible = "regulator-fixed"; + regulator-name = "wwan_power_off"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wwan_power_off_h>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-always-on; + }; + + switch_phy_pwr_en: switch-phy-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_pwr_en>; + vin-supply = <&vcc12v_dcin>; + }; + + pcie_wifi_enable: pcie-wifi-enable-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie_wifi_enable"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie_wifi_enable_h>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + vin-supply = <&vcc5v0_sys>; + }; + + usb5v0_typec0: usb5v0-typec0-regulator{ + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + //enable-active-high; + regulator-boot-on; + regulator-always-on; + //gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + //enable-active-high; + //gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sata: vcc5v0-sata { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sata"; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <1000000>; + //usb-pd-controller = <&usbc0>; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sata1_pwr_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + user-led2 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <72 94 117 139 162 184 207 229 255>; + pwms = <&pwm1 0 10000 1>; + }; + + rtl8367s { + compatible = "realtek,rtl8367s", "realtek,rtl8367b"; + cpu_port = <7>; + mii-bus = <&mdio1>; + realtek,extif2 = <1 0 1 1 1 1 1 1 2>; + phy-id = <29>; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <2000>; + + trips { + trip0: trip-point@0 { + temperature = <45000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip5: trip-point@5 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip6: trip-point@6 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@7 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&trip5>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + map6 { + trip = <&trip6>; + cooling-device = <&fan0 6 7>; + contribution = <1024>; + }; + map7 { + trip = <&pcritical>; + cooling-device = <&fan0 7 8>; + contribution = <1024>; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; + route { + route_hdmi0: route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi0>; + }; + }; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&sata1{ + ahci-supply = <&vcc5v0_sata>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + //int-n-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&usb5v0_typec0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "host"; + dr_mode = "host"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&combphy1_ps { + // pinctrl-names = "default"; + // pinctrl-0 = <&sata1_pm_reset>; + status = "okay"; +}; + +&combphy0_ps { + //rockchip,ext-refclk; + //assigned-clock-rates = <100000000>; + status = "okay"; +}; + +&pcie30phy { + //rockchip,ext-refclk; + assigned-clock-rates = <100000000>; + rockchip,pcie30-phymode = ; //4*pcie3.0x1 + 1* pcie2.0x1 + status = "okay"; +}; + +&pcie2x1l0 { + /* 2.pcie30phy port0 lane1 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + //reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //checked + //prsnt-gpios=<&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; + + pcie@20 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme1: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie2x1l1 { + /* 4.pcie30phy port1 lane1 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; //checked + + //prsnt-gpios=<&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@30 { + reg = <0x00300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + rtl8125_0: pcie@30,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie2x1l2 { + //reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + prsnt-gpios=<&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + status = "okay"; + + pcie@40 { + reg = <0x00400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + rtl8125_1: pcie@40,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie3x4 { + max-link-speed = <3>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + //prsnt-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie3x2 { + /* 3.pcie30phy port1 lane0 */ + max-link-speed = <3>; + num-lanes = <1>; + //reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //checked + //prsnt-gpios=<&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + bus-scan-delay-ms = <30000>; + delayed-auto; + link_retries_count = <400>; + + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&gmac0 { + status = "disabled"; +}; + +/* +&gmac1 { + clock_in_out = "output"; + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + snps,reset-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 15000 50000>; + + tx_delay = <0x42>; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +};*/ + +/*&mdio1 { + switch@29 { + compatible = "realtek,rtl8365mb"; + reg = <29>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "lan5"; + }; + + port@7 { + reg = <7>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +};*/ + +&pinctrl { + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + phy-pwr { + phy_pwr_en: phy-pwr-en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_pwr_en: led-pwr-en { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd_pwr { + sd_pwr_en_h: sd-pwr-en-h { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wwan_pwr { + wwan_rst_en: wwan-rst-en { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wwan_disable_h: wwan-disable-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wwan_power_off_h: wwan-power-off-h { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie_wifi_h { + pcie_wifi_enable_h: pcie_wifi_enable_h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + sata { + sata1_pwr_en: sata-pwr-en{ + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_output_high>; + }; + sata1_pm_reset: sata1-pm-reset { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts new file mode 100644 index 0000000000000..2323b96571d07 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts @@ -0,0 +1,1416 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* +* Copyright (c) 2021 Rockchip Electronics Co., Ltd. +* +*/ + +/dts-v1/; + +#include +#include "rk3588.dtsi" +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include "rk3588-linux.dtsi" + + +/ { + model = "Firefly ITX-3588J HDMI(Linux)"; + compatible = "rockchip,rk3588-firefly-itx-3588j", "rockchip,rk3588"; + + /delete-node/ chosen; + + adc_keys: adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery-key{ + label = "F12"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + bt_sco: bt-sco { + status = "okay"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <0>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "firefly,multicodecs-card"; + firefly,not-use-dapm; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + spk-con-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + linein-type = <0>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <384>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT2", "Main Mic", + "RINPUT2", "Main Mic", + "LINPUT1", "Headset Mic", + "RINPUT1", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <60 100 140 160 185 220 255>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm15 0 50000 1>; + }; + + firefly_leds: leds { + compatible = "gpio-leds"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + power_led: power { + label = ":power";//green led + linux,default-trigger = "ir-power-click"; + default-state = "on"; + gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + user_led: user { + label = ":user";//yellow led + linux,default-trigger = "ir-user-click"; + default-state = "off"; + gpios = <&pca9555 PCA_IO0_3 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc_hub3_reset: vcc-hub3-reset-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_hub3_reset"; + regulator-always-on; + enable-active-high; + status = "okay"; + gpio = <&pca9555 PCA_IO0_6 GPIO_ACTIVE_HIGH>;//PCA_IO 06 + }; + + vbus5v0_typec_pwr_en: vbus5v0-typec-pwr-en-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec_pwr_en"; + enable-active-high; + status = "okay"; + gpio = <&pca9555 PCA_IO1_4 GPIO_ACTIVE_HIGH>;//PCA_IO 14 + }; + + vcc_hub_reset: vcc-hub-reset-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_hub_reset"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + status = "okay"; + gpio = <&pca9555 PCA_IO0_4 GPIO_ACTIVE_HIGH>;//PCA_IO 04 + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host3: vcc5v0-host3 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pca9555 PCA_IO0_7 GPIO_ACTIVE_HIGH>;//PCA_IO 07 + vin-supply = <&vcc5v0_usb>; + status = "okay"; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pca9555 PCA_IO0_5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + status = "okay"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_sata_pwr_en: vcc-sata-pwr-en-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sata_pwr_en"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + status = "okay"; + gpio = <&pca9555 PCA_IO1_2 GPIO_ACTIVE_HIGH>;//PCA_IO 12 + }; + + vcc_fan_pwr_en: vcc-fan-pwr-en-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_fan_pwr_en"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + status = "okay"; + gpio = <&pca9555 PCA_IO1_3 GPIO_ACTIVE_HIGH>;//PCA_IO 13 + }; + + vcc_sdcard_pwr_en: vcc-sdcard-pwr-en-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sdcard_pwr_en"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pca9555 PCA_IO1_5 GPIO_ACTIVE_HIGH>;//PCA_IO 15 + status = "okay"; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + status = "okay"; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip,dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart6m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart6_gpios>; + BT,power_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_poweren_gpio>; + /delete-property/ WIFI,host_wake_irq; + WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin_sound: hdmiin-sound { + compatible = "rockchip,hdmi"; + status = "okay"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&can1 { + status = "okay"; + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +/* sata pm */ +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay";// USB3.1/SATA/PCIe Combo PHY +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +/* display port1 to vga */ +&dp1_in_vp2 { + status = "okay"; +}; + +&dp1 { + pinctrl-names = "default"; + pinctrl-0 = <&dp1_hpd>; + hpd-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&route_dp1{ + status = "disabled"; + connect = <&vp2_out_dp1>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x45>; + //rx_delay = <0x4a>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac0_tx_bus2{ + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB6 1 &pcfg_pull_up_drv_level_6>, + /* gmac0_txd1 */ + <2 RK_PB7 1 &pcfg_pull_up_drv_level_6>, + /* gmac0_txen */ + <2 RK_PC0 1 &pcfg_pull_none>; +}; + +&gmac0_rgmii_bus{ + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA6 1 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA7 1 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PB1 1 &pcfg_pull_up_drv_level_6>, + /* gmac0_txd3 */ + <2 RK_PB2 1 &pcfg_pull_up_drv_level_6>; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + //rx_delay = <0x4f>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gmac1_tx_bus2{ + rockchip,pins = + /* gmac1_txd0 */ + <3 RK_PB3 1 &pcfg_pull_up_drv_level_6>, + /* gmac1_txd1 */ + <3 RK_PB4 1 &pcfg_pull_up_drv_level_6>, + /* gmac1_txen */ + <3 RK_PB5 1 &pcfg_pull_none>; +}; + +&gmac1_rgmii_bus{ + rockchip,pins = + /* gmac1_rxd2 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* gmac1_rxd3 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* gmac1_txd2 */ + <3 RK_PA0 1 &pcfg_pull_up_drv_level_6>, + /* gmac1_txd3 */ + <3 RK_PA1 1 &pcfg_pull_up_drv_level_6>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0{ + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&route_hdmi1{ + status = "okay"; + connect = <&vp1_out_hdmi1>; +}; + +&hdmirx_ctrler { + status = "okay"; + #sound-dai-cells = <1>; + //memory-region = <&hdmirx>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c6 { + status = "okay"; + clock-frequency = <400000>;// For others Display Port Screen + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-group-num = <200>; + status = "okay"; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + status = "okay"; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec_pwr_en>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s1_8ch { + status = "okay"; + pinctrl-0 = <&i2s1m0_lrck &i2s1m0_sclk &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,bclk-fs = <32>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +/* pcie3.0 x 4 slot */ +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + leds_gpio: leds-gpio { + /* led_power */ + rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + uart6_gpios: uart6-gpios { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm15 { + pinctrl-0 = <&pwm15m2_pins>; + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + | RKPM_SLP_PMU_DBG + ) + >; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&soc_thermal { + sustainable-power = <15000>; /* milliwatts */ + polling-delay = <1000>; + polling-delay-passive = <2000>; + + trips { + trip0: trip-point@0 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@5 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&pcritical>; + cooling-device = <&fan 5 6>; + contribution = <1024>; + }; + }; +}; + +/* uart/232/485 */ +&uart0{ + pinctrl-0 = <&uart0m2_xfer>; + status = "okay"; +}; + +&uart1{ + pinctrl-0 = <&uart1m1_xfer>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + status = "okay"; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/*usb3.1 host2 controller for 5G module*/ +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdd_log_s0 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&avdd_0v75_s0 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&tsadc { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&spdif_tx2{ + status = "okay"; +}; + +&avcc_1v8_s0{ + regulator-state-mem { + regulator-on-in-suspend; + }; +}; + +&vcc_1v8_s0{ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts new file mode 100644 index 0000000000000..aff8d8d957b8a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -0,0 +1,832 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; + +#include "rk3588.dtsi" +#include "rk3588s-nanopi-r6-common.dtsi" + +/ { + model = "FriendlyElec CM3588"; + compatible = "friendlyelec,cm3588", "rockchip,rk3588"; + + aliases { + ethernet0 = &r8125_u10; + nvme0 = &nvme0; + nvme1 = &nvme1; + nvme2 = &nvme2; + nvme3 = &nvme3; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; + linux,cma-default; + }; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip,dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + }; + + rt5616_sound: rt5616-sound { + status = "okay"; + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphone Jack"; + + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + fan: pwm-fan { + status = "disabled"; + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + cooling-levels = <0 35 64 100 150 255>; + rockchip,hold-time-ms = <2000>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + usr_led: led-1 { + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + label = "usr_led"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pin>; + }; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + }; + + hdmiin_sound: hdmiin-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + vcc5v0_host_30: vcc5v0-host-30 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host30_en>; + regulator-name = "vcc5v0_host_30"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc3v3_host_32: vcc3v3-host-32 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_host32_en>; + regulator-name = "vcc3v3_host_32"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host_20: vcc5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound { + status = "okay"; +}; + +&gmac1 { + status = "disabled"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdmiin_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + edid-version = <3>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c5 { + pinctrl-0 = <&i2c5m0_xfer>; + /* connected with MIPI-DSI0 */ +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: rt5616@1b { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "rt5616"; + reg = <0x1b>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + /* connected with MIPI-CSI1 */ +}; + +&i2c8 { + status = "okay"; + pinctrl-0 = <&i2c8m2_xfer>; + /* connected with Header_2.54MM */ +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + rockchip,trcm-sync-tx-only; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio1 { + status = "disabled"; +}; + +&pcie2x1l0 { + /* 2. CON14: pcie30phy port0 lane1 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@20 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme1: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie2x1l1 { + /* 4. CON16: pcie30phy port1 lane1 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@30 { + reg = <0x00300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme3: pcie@30,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; + + pcie@40 { + reg = <0x00400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u10: pcie@40,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + /* 1. CON13: pcie30phy port0 lane0 */ + max-link-speed = <3>; + num-lanes = <1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@00 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme0: pcie@00,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie3x2 { + /* 3. CON15: pcie30phy port1 lane0 */ + max-link-speed = <3>; + num-lanes = <1>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@10 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme2: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usr_led_pin: usr-led-pin { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + /omit-if-no-ref/ + lcd_rst0_gpio: lcd-rst0-gpio { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcd_rst1_gpio: lcd-rst1-gpio { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi0_gpio: touch-dsi0-gpio { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi1_gpio: touch-dsi1-gpio { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_host30_en: vcc5v0-host30-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_host32_en: vcc3v3-host32-en { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + /* connected with MIPI-DSI0 */ +}; + +&pwm8 { + pinctrl-0 = <&pwm8m0_pins>; + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host_30>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc3v3_host_32>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + rockchip,dp-lane-mux = <0 1 2 3 >; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + snps,xhci-trb-ent-quirk; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vcc_3v3_sd_s0 { + /delete-property/ enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; +}; + +&vop { + disable-win-move; +}; + +/* GPIO Connector */ +&pwm5 { + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +&pwm9 { + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +&spi0 { + num-cs = <1>; + pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; + status = "disabled"; + + spidev0: spidev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <5000000>; + status = "disabled"; + }; +}; + +&spi4 { + num-cs = <1>; + pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>; + status = "disabled"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; +}; + +&uart3 { + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +&uart4 { + pinctrl-0 = <&uart4m2_xfer>; + status = "disabled"; +}; + +&uart6 { + pinctrl-0 = <&uart6m1_xfer>; + status = "okay"; +}; + +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +&uart8 { + pinctrl-0 = <&uart8m1_xfer>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts b/arch/arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts new file mode 100644 index 0000000000000..7b09635a08531 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts @@ -0,0 +1,1336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Fxblox RK1"; + compatible = "fxland,fxblox-rk1", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "disable"; + }; + + hdmi1_sound: hdmi1-sound { + status = "disable"; + + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "disable"; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + // pcie3x4 + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vbus5v0_typec1: vbus5v0-typec1 { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&typec1_5v_pwren>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + led_red { + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_green { + gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_blue { + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + user-led1 { + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + vin-supply = <&vcc12v_dcin>; + cooling-levels = <90 110 130 150 170 190 210 230 255>; + pwms = <&pwm1 0 10000 0>; + }; + + panel-edp0 { + compatible = "simple-panel"; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <4>; + vsync-len = <5>; + vback-porch = <36>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp0: endpoint { + data-lanes = <2>; + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <45000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip5: trip-point@5 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip6: trip-point@6 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@7 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&trip5>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + map6 { + trip = <&trip6>; + cooling-device = <&fan0 6 7>; + contribution = <1024>; + }; + map7 { + trip = <&pcritical>; + cooling-device = <&fan0 7 8>; + contribution = <1024>; + }; + }; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + host-wakeup-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_pcie2x1l0>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; + route { + route_dp0: route-dp0 { + status = "ok"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_dp0>; + }; + + route_dp1: route-dp1 { + status = "ok"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_dp1>; + }; + + route_edp0: route-edp0 { + status = "ok"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp2_out_edp0>; + }; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + + + +&u2phy3 { + status = "okay"; +}; +&u2phy3_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; +&combphy2_psu { + status = "okay"; +}; +&usbhost3_0 { + status = "okay"; +}; +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; + + usbc1: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc1_int>; + vbus-supply = <&vbus5v0_typec1>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc1_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_1_role_switch>; + }; + }; + }; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc1_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy1_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp1_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy1_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_1_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + rockchip,dp-lane-mux = <0 1 2 3 >; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + status = "okay"; + orientation-switch; + rockchip,dp-lane-mux = <0 1 2 3 >; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy1_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_orien_sw>; + }; + + usbdp_phy1_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp1_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp1 { + status = "okay"; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp1_in_vp1 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp0_out_dp0>; +}; + +&route_dp1 { + status = "okay"; + connect = <&vp1_out_dp1>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +// sata0 +&sata0 { + status = "okay"; +}; +&combphy0_ps { + status = "okay"; +}; +&pcie2x1l2 { + status = "disable"; +}; +// sata0 end + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +// pcie3x4 +&pcie3x4 { + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; +// pcie3x4 + + +&pwm1 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec1 { + usbc1_int: usbc1-int { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec1_5v_pwren: typec1_5v-pwren { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + + +&edp0_in_vp2 { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&spdif_tx3 { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-hinlink-h88k.dts b/arch/arm64/boot/dts/rockchip/rk3588-hinlink-h88k.dts new file mode 100644 index 0000000000000..6e69f2b772d13 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-hinlink-h88k.dts @@ -0,0 +1,1102 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + model = "HINLINK H88K"; + compatible = "hinlink,h88k", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + dp0_sound: dp0-sound { + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8388-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-es8316"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8388>; + }; + }; + }; + + hdmi0-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int_pin>; + pinctrl-names = "default"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_net_en>, <&led_sata_en>, + <&led_user_en>, <&led_work_en>; + + net { + label = "blue:net"; + gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + }; + + sata { + label = "amber:sata"; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + + user { + label = "green:user"; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + work { + label = "red:work"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + /* it's modem reset pin */ + modem_enable: modem-enable { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "modem-enable"; + vin-supply = <&vcc_3v3_s3>; + startup-delay-us = <500000>; + pinctrl-names = "default"; + pintctrl-0 = <&modem_reset_en>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "pcie20_avdd0v85"; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie20_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie30_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm14 0 50000 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_m2_sata: vcc3v3-m2-sata { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sata"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_modem: vcc3v3-modem { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_modem"; + pinctrl-names = "default"; + pintctrl-0 = <&modem_power_en>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb_host"; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_hub: vcc5v0-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_hub_en>; + regulator-name = "vcc5v0_usb_hub"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb_otg"; + vin-supply = <&vcc5v0_usb>; + }; + + wifi_regon: wifi-regon { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "wifi_regon"; + startup-delay-us = <5000>; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp1 { + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + phy-handle = <&rgmii_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + }; +}; + +&i2c6 { + status = "okay"; + + husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_usb_otg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: es8388@11 { + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + ir_int_pin: ir-int-pin { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_net_en: led_net_en { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_sata_en: led_sata_en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_user_en: led_user_en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_work_en: led_work_en { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + modem { + modem_power_en: modem-power-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + modem_reset_en: modem-reset-en { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm14 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&route_hdmi1 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + | RKPM_SLP_PMU_DBG + ) + >; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + max-frequency = <50000000>; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + rockchip,dp-lane-mux = < 0 1 2 3 >; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + svid = <0xff01>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts new file mode 100644 index 0000000000000..e5e2d21e70bc7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts @@ -0,0 +1,991 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Mixtile Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Mixtile Core 3588E"; + compatible = "mixtile,core3588e", "rockchip,rk3588"; + /delete-node/ chosen; + + aliases { + i2c0 = &i2c4; + i2c1 = &i2c5; + i2c2 = &i2c3; + i2c3 = &i2c0; + i2c4 = &i2c1; + i2c5 = &i2c2; + spi0 = &spi1; + spi1 = &spi0; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pwr-led { + gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + edp1_sound: edp1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-edp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&edp1>; + rockchip,jack-det; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm2 0 50000 0>; + interrupt-parent = <&gpio3>; + interrupts = ; + pulses-per-revolution = <2>; + cooling-levels = <50 100 150 200 255>; + rockchip,temp-trips = < + 40000 1 + 45000 2 + 50000 3 + 55000 4 + >; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = <0x4000024>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_data_strobe>; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + bus-width = <1>; + disable-wp; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + extcon = <&u2phy0>; + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + rx_delay = <0x00>; + tx_delay = <0x43>; + + phy-handle = <&rgmii_phy>; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&edp1 { + pinctrl-names = "default"; + pinctrl-0 = <&edp1_hpd>; + hpd-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + //force-hpd; + status = "okay"; +}; + +&edp1_in_vp2 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn &uart7m1_rtsn>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m3_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + status = "okay"; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m1_pins>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m3_cs1 &spi0m3_pins>; + num-cs = <1>; + + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m2_cs0 &spi1m2_pins>; + num-cs = <1>; + + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4m1_pins>; + supports-clkreq; + status = "okay"; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp1_hpd: edp1-hpd { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + emmc { + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_down>; + }; + }; +}; + +&route_hdmi0 { + connect = <&vp0_out_hdmi0>; + status = "okay"; +}; + +&route_edp1 { + status = "okay"; + connect = <&vp2_out_edp1>; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "PIN_29", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "", "", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "", + + /* GPIO0_D0-D3 */ + "", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "", "", "", + /* GPIO1_A4-A7 */ + "", "", "", "", + + /* GPIO1_B0-B3 */ + "", "", "", "", + /* GPIO1_B4-B7 */ + "", "", "", "", + + /* GPIO1_C0-C3 */ + "", "", "PIN_07", "", + /* GPIO1_C4-C7 */ + "", "", "", "", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "PIN_32", "", "", "PIN_15", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "PIN_33", "", "", "", + /* GPIO3_B4-B7 */ + "", "", "", "", + + /* GPIO3_C0-C3 */ + "", "", "", "", + /* GPIO3_C4-C7 */ + "", "", "PIN_31", "", + + /* GPIO3_D0-D3 */ + "", "", "", "", + /* GPIO3_D4-D7 */ + + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "", "", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "", "", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-cm3588-nas.dts new file mode 100644 index 0000000000000..54415970831d1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-cm3588-nas.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588-friendlyelec-cm3588-nas.dts" + +// DO NOT ADD ANYTHING TO THIS DTS! +// This file only exists for backwards compatibility for existing installations installed before 2024-08-22. diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts new file mode 100644 index 0000000000000..71b050b05a86a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; +#include "rk3588-nanopc-t6.dts" + +/ { + model = "FriendlyElec NanoPC-T6 LTS"; + compatible = "friendlyelec,nanopc-t6", "rockchip,rk3588"; + + vcc5v0_host_20: vcc5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host_20>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts new file mode 100644 index 0000000000000..ff20cd2c15890 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; + +#include "rk3588.dtsi" +#include "rk3588s-nanopi-r6-common.dtsi" + +/ { + model = "FriendlyElec NanoPC-T6"; + compatible = "friendlyelec,nanopc-t6", "rockchip,rk3588"; + + aliases { + ethernet0 = &r8125_u10; + ethernet1 = &r8125_u12; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + rt5616_sound: rt5616-sound { + status = "okay"; + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphone Jack"; + + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + fan: pwm-fan { + status = "okay"; + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + cooling-levels = <0 35 64 100 150 255>; + rockchip,hold-time-ms = <2000>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + usr_led: led-1 { + gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + label = "usr_led"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pin>; + }; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + }; + + hdmiin_sound: hdmiin-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + vcc5v0_host_30: vcc5v0-host-30 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host30_en>; + regulator-name = "vcc5v0_host_30"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_mpcie_3v3: vdd-mpcie-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_1_pwren>; + regulator-name = "vdd_mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_4glte_3v3: vdd-4glte-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_4glte_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <10000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1_ps { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound { + status = "okay"; +}; + +&gmac1 { + status = "disabled"; +}; + +&hdmi0 { + cec-enable = "true"; + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + cec-enable = "true"; + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdmiin_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + edid-version = <3>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3m0_xfer>; + /* connected with MIPI-CSI0 */ +}; + +&i2c4 { + pinctrl-0 = <&i2c4m3_xfer>; + /* connected with MIPI-DSI1 */ +}; + +&i2c5 { + pinctrl-0 = <&i2c5m0_xfer>; + /* connected with MIPI-DSI0 */ +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: rt5616@1b { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "rt5616"; + reg = <0x1b>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + /* connected with MIPI-CSI1 */ +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + /* connected with Header_2.54MM */ +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + rockchip,trcm-sync-tx-only; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; + + pcie@20 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u12: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <500>; + vpcie3v3-supply = <&vdd_mpcie_3v3>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; + + pcie@40 { + reg = <0x00400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u10: pcie@40,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim1_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usr_led_pin: usr-led-pin { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + /omit-if-no-ref/ + lcd_rst0_gpio: lcd-rst0-gpio { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcd_rst1_gpio: lcd-rst1-gpio { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi0_gpio: touch-dsi0-gpio { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi1_gpio: touch-dsi1-gpio { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_m2_0_pwren: pcie-m20-pwren { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_m2_1_pwren: pcie-m21-pwren { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_host30_en: vcc5v0-host30-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + /* connected with MIPI-DSI0 */ +}; + +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + /* connected with MIPI-DSI1 */ +}; + +&spdif_tx2 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host_30>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + rockchip,dp-lane-mux = <0 1 2 3 >; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + snps,xhci-trb-ent-quirk; + status = "okay"; +}; + +&vcc_3v3_sd_s0 { + /delete-property/ enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; +}; + + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera0.dtsi new file mode 100644 index 0000000000000..9746b7792f388 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera0.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy0 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out0>; + data-lanes = <1 2>; + }; + + mipidphy0_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + vm149c_p0: vm149c-p0@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_0: ov13850-0@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p0>; + port { + ov13850_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p0: dw9714-p0@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_0: ov13855-0@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p0>; + port { + ov13855_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "disabled"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir2>; + }; + }; +}; + +&rkisp0_vir2 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp0_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera1.dtsi new file mode 100644 index 0000000000000..61cafdf539288 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera1.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy3 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy1_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out1>; + data-lanes = <1 2>; + }; + + mipidphy1_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + vm149c_p1: vm149c-p1@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_1: ov13850-1@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera2_clk>; + reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p1>; + port { + ov13850_out1: endpoint { + remote-endpoint = <&mipidphy1_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p1: dw9714-p1@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855-1@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera2_clk>; + reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p1>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipidphy1_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "disabled"; + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "disabled"; + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkisp1_vir1 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera2.dtsi new file mode 100644 index 0000000000000..fe6c4434f2f55 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera2.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidcphy0_in_cam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out2>; + data-lanes = <1 2>; + }; + + mipidcphy0_in_cam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + vm149c_p2: vm149c-p2@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_2: ov13850-2@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera3_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p2>; + port { + ov13850_out2: endpoint { + remote-endpoint = <&mipidcphy0_in_cam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p2: dw9714-p2@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <2>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_2: ov13855-2@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera3_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p2>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipidcphy0_in_cam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "disabled"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "disabled"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkisp0_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts new file mode 100644 index 0000000000000..c857ce0086740 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts @@ -0,0 +1,1356 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" + +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588-orangepi-5-max-camera0.dtsi" +#include "rk3588-orangepi-5-max-camera1.dtsi" +#include "rk3588-orangepi-5-max-camera2.dtsi" + +/ { + model = "RK3588 OPi 5 Max"; + compatible = "rockchip,rk3588-orangepi-5-max", "rockchip,rk3588"; + + /delete-node/ chosen; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm15 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "disabled"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,es8388"; + hp-det-gpio = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + hp-con-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + //gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie_eth: vcc3v3-pcie-eth { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_eth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-low; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart7m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart7_gpios>; + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6611"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_rgb>; + status = "okay"; + + blue_led@1 { + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "blue_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + + green_led@2 { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + label = "green_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm9 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + + status = "okay"; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "disabled"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "disabled"; + compatible = "innolux,afj101-ba2131"; + reg = <0>; + backlight = <&backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; + disable-win-move; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&vp1 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&vp2 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&vp3 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&spdif_tx2{ + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_panel { + status = "disabled"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_te1>; +}; + +&dsi1_panel { + status = "disabled"; +}; + +&gmac0 { + status = "disabled"; +}; + +&hdmi0 { + status = "okay"; + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + cec-enable = "true"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c6 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + status = "okay"; + }; + +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +//phy1 +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +//phy2 +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +//phy0 +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart7_gpios: uart7-gpios { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds_gpio { + leds_rgb: leds-rgb { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy0>; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* Fan */ +&pwm9 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m2_pins>; +}; + +/* watchdog */ +&wdt { + status = "okay"; +}; + +&sfc { + status = "okay"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&pwm15 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m2_pins>; + status = "okay"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; +}; + +&spi0 { + assigned-clocks = <&cru CLK_SPI0>; + assigned-clock-rates = <200000000>; + num-cs = <2>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer &uart7m0_ctsn>; +}; + +&spi4 { + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "disabled"; + reset-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&i2c7 { + status = "okay"; + + gt9xx_0: touchscreen@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&gpio2>; + interrupts = ; + irq-gpios = <&gpio2 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + //touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + status = "okay"; + }; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi new file mode 100755 index 0000000000000..d212098ae7e0c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dphy0_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out2>; + data-lanes = <1 2>; + }; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + vm149c_p1: vm149c-p1@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_1: ov13850-1@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera3_clk>; + reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p1>; + port { + ov13850_out2: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p1: dw9714-p1@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855-1@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera3_clk>; + reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p1>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "disabled"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir1 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts new file mode 100644 index 0000000000000..146d5f873cc5c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -0,0 +1,1336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588-orangepi-5-plus-camera1.dtsi" + +/ { + model = "Orange Pi 5 Plus"; + compatible = "rockchip,rk3588-orangepi-5-plus", "rockchip,rk3588"; + + /delete-node/ chosen; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm3 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + + status = "okay"; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_rgb>; + status = "okay"; + + blue_led@1 { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "blue_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + + green_led@2 { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + label = "green_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + enable-active-low; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie_eth: vcc3v3-pcie-eth { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_eth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-low; + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&can0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; +}; + +&can1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m0_pins>; + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; +}; + +&can2 { + status = "disabled"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + cec-enable = "true"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "disabled"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; +}; + +&i2c4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&i2c6 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + status = "okay"; + }; + +}; + +&i2c7 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c8 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +//phy1 +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +//phy2 +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,default-link-up; + status = "okay"; +}; + +//phy0 +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + rockchip,default-link-up; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds_gpio { + leds_rgb: leds-rgb { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc_pwr { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm0 { + status = "disabled"; +}; + +&pwm1 { + status = "disabled"; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m1_pins>; +}; + +&pwm10 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; +}; + +&pwm11 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; +}; + +&pwm12 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; +}; + +&pwm13 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; +}; + +&pwm14 { + status = "disabled"; +}; + +&pwm15 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m1_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xfb04>; + rockchip,key_table = + <0xa3 KEY_ENTER>, + <0xe4 388>, + <0xf5 KEY_BACK>, + <0xbb KEY_UP>, + <0xe2 KEY_DOWN>, + <0xe3 KEY_LEFT>, + <0xb7 KEY_RIGHT>, + <0xe0 KEY_HOME>, + <0xba KEY_VOLUMEUP>, + <0xda KEY_VOLUMEUP>, + <0xe6 KEY_VOLUMEDOWN>, + <0xdb KEY_VOLUMEDOWN>, + <0xbc KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xe5 KEY_POWER>, + <0xde KEY_POWER>, + <0xdc KEY_MUTE>, + <0xa2 KEY_MENU>, + <0xec KEY_1>, + <0xef KEY_2>, + <0xee KEY_3>, + <0xf0 KEY_4>, + <0xf3 KEY_5>, + <0xf2 KEY_6>, + <0xf4 KEY_7>, + <0xf7 KEY_8>, + <0xf6 KEY_9>, + <0xb8 KEY_0>; + }; +}; + +&sata0 { + status = "disabled"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&spi0 { + status = "disabled"; + assigned-clocks = <&cru CLK_SPI0>; + assigned-clock-rates = <200000000>; + num-cs = <2>; +}; + + +&spi4 { + status = "disabled"; + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; +}; + +&sfc { + status = "okay"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim1_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&uart1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; +}; + +&uart3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; +}; + +&uart6 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; +}; + +&uart7 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; +}; + +&uart8 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; + disable-win-move; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&wdt { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-radxa-rock-5b+.dts b/arch/arm64/boot/dts/rockchip/rk3588-radxa-rock-5b+.dts new file mode 100644 index 0000000000000..4de7c160d2df0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-radxa-rock-5b+.dts @@ -0,0 +1,1283 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Radxa ROCK 5B+"; + compatible = "radxa,rock-5b-plus", "rockchip,rk3588"; + + /delete-node/ chosen; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + pwms = <&pwm1 0 10000 0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_l>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-hdmi2"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8316"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8316>; + poll-interval = <100>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + play-pause-key { + label = "playpause"; + linux,code = <164>; + press-threshold-microvolt = <2000>; + }; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + em05_modem: em05-modem { + compatible = "lte-em05-modem-platdata"; + pinctrl-names = "default"; + pinctrl-0 = <&em05_power_en &em05_airplane_mode &em05_reset>; + em05,power-gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + em05,reset-gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + em05,airplane-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + user-led2 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; + + route { + route_hdmi0: route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi0>; + }; + + route_hdmi1: route-hdmi1 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_hdmi1>; + }; + }; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + cec-enable = "true"; + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + cec-enable = "true"; + enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; + #sound-dai-cells = <1>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <2>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + cooling-maps { + map4 { + trip = <&target>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + map5 { + trip = <&threshold>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + status = "okay"; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_wake_l: bt-wake-l { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lte-em05-modem { + em05_airplane_mode: em05-airplane-mode { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + em05_power_en: em05-power-en { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + em05_reset: em05-reset { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "", + + /* GPIO0_D0-D3 */ + "", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "", "PIN_31", "PIN_29", + /* GPIO1_A4-A7 */ + "", "", "", "", + + /* GPIO1_B0-B3 */ + "", "PIN_21", "PIN_19", "PIN_23", + /* GPIO1_B4-B7 */ + "PIN_24", "PIN_26", "", "", + + /* GPIO1_C0-C3 */ + "", "", "", "", + /* GPIO1_C4-C7 */ + "", "", "", "", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "PIN_16", "", "", "PIN_33", + + /* GPIO3_B0-B3 */ + "", "PIN_36", "PIN_38", "PIN_40", + /* GPIO3_B4-B7 */ + "", "PIN_12", "PIN_35", "PIN_13", + + /* GPIO3_C0-C3 */ + "PIN_15", "PIN_11", "PIN_32", "PIN_7", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "", "", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "PIN_5", "PIN_3", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "PIN_18", "PIN_28", "PIN_27", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rk806-single-khadas.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single-khadas.dtsi new file mode 100644 index 0000000000000..e88fb8e4a66b3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single-khadas.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Wesion Technology Co., Ltd. + * + */ + +#include +#include + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + rk806single: rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + /* 2800mv-3500mv */ + low_voltage_threshold = <3000>; + /* 2700mv-3400mv */ + shutdown_voltage_threshold = <2700>; + /* 140 160 */ + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts new file mode 100644 index 0000000000000..1bf298e63938d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -0,0 +1,1240 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Radxa ROCK 5 ITX"; + compatible = "radxa,rock-5-itx", "rockchip,rk3588"; + + /delete-node/ chosen; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + status = "okay"; + + maskrom-key { + label = "macro"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + pwms = <&pwm14 0 10000 0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-hdmi2"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8316"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8316>; + poll-interval = <100>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + play-pause-key { + label = "playpause"; + linux,code = <164>; + press-threshold-microvolt = <2000>; + }; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + gpio = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + power-led1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + hdd-led2 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + host-wakeup-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_pcie2x1l0>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + cec-enable = "true"; + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; + #sound-dai-cells = <1>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m4_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c8m4_xfer { + rockchip,pins = + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_up_drv_level_6>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_up_drv_level_6>; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp1_hpd>; + hpd-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; + vbus-supply = <&vcc5v0_host>; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; + dr_mode = "host"; +}; + +&usbdp_phy1 { + status = "okay"; + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&spdif_tx1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m2_tx>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <2>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pwm14 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m1_pins>; + status = "okay"; +}; + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + cooling-maps { + map4 { + trip = <&target>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + map5 { + trip = <&threshold>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + status = "okay"; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&vdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-camera.dtsi new file mode 100644 index 0000000000000..aff5628db5ea3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-camera.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + camera_pwdn_gpio: camera-pwdn-gpio { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + status = "disabled"; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "disabled"; + + imx415: imx415@1a { + status = "disabled"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + camera_imx219: camera-imx219@10 { + status = "disabled"; + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "disabled"; +}; + +&rkcif_mipi_lvds2 { + status = "disabled"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "disabled"; +}; + +&rkisp0 { + status = "disabled"; +}; + +&isp0_mmu { + status = "disabled"; +}; + +&rkisp0_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-display.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-display.dtsi new file mode 100644 index 0000000000000..e91a778cae88b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-display.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited. + * + */ + +/ { + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "disabled"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; +}; + +&pwm2 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; +}; + +&dsi1 { + status = "disabled"; + rockchip,lane-rate = <480>; + + dsi1_panel: panel@0 { + status = "disabled"; + compatible ="chongzhou,cz101b4001"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + + gt9xx: gt9xx@14 { + status = "disabled"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; + + focaltech: focaltech@38 { + status = "disabled"; + compatible = "focaltech,fts"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&focaltech_gpio>; + focaltech,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + focaltech,display-coords = <0 0 799 1279>; + }; +}; + +&pinctrl { + + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = + <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + focaltech { + focaltech_gpio: focaltech-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts new file mode 100644 index 0000000000000..b776fd9666b29 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -0,0 +1,1340 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Radxa ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8316"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch >; + rockchip,codec = <&es8316>; + poll-interval = <100>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + play-pause-key { + label = "playpause"; + linux,code = <164>; + press-threshold-microvolt = <2000>; + }; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + user-led2 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <72 94 117 139 162 184 207 229 255>; + pwms = <&pwm1 0 10000 0>; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <45000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip5: trip-point@5 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip6: trip-point@6 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@7 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&trip5>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + map6 { + trip = <&trip6>; + cooling-device = <&fan0 6 7>; + contribution = <1024>; + }; + map7 { + trip = <&pcritical>; + cooling-device = <&fan0 7 8>; + contribution = <1024>; + }; + }; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + host-wakeup-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_pcie2x1l0>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; + + route { + route_hdmi0: route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi0>; + }; + + route_hdmi1: route-hdmi1 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_hdmi1>; + }; + }; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + cec-enable = "true"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdrd3_1{ + status = "okay"; +}; + +&usbdrd_dwc3_1{ + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc12v_dcin>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + faster-pd-negotiation; + power-role = "sink"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&sfc { + status = "okay"; + max-freq = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "", + + /* GPIO0_D0-D3 */ + "", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "", "", "", + /* GPIO1_A4-A7 */ + "", "", "", "", + + /* GPIO1_B0-B3 */ + "", "PIN_21", "PIN_19", "PIN_23", + /* GPIO1_B4-B7 */ + "PIN_24", "PIN_26", "", "PIN_31", + + /* GPIO1_C0-C3 */ + "", "", "", "", + /* GPIO1_C4-C7 */ + "", "", "", "", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "", "", "", "PIN_29"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "PIN_16", "", "", "PIN_33", + + /* GPIO3_B0-B3 */ + "", "PIN_36", "PIN_38", "PIN_40", + /* GPIO3_B4-B7 */ + "", "PIN_12", "PIN_35", "PIN_13", + + /* GPIO3_C0-C3 */ + "PIN_15", "PIN_11", "PIN_32", "PIN_7", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "", "", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "PIN_5", "PIN_3", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "PIN_18", "PIN_28", "PIN_27", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dts b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dts new file mode 100644 index 0000000000000..18662b44c1f18 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Joshua Riek + * + */ + +/dts-v1/; + +#include "rk3588-turing-rk1.dtsi" + +/ { + model = "Turing Machines RK1"; + compatible = "turing,rk1", "rockchip,rk3588"; + + chosen { + stdout-path = "serial9:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi new file mode 100644 index 0000000000000..63760508b8e2f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -0,0 +1,764 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Joshua Riek + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + compatible = "turing,rk1", "rockchip,rk3588"; + + /delete-node/ chosen; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + serial2 = &uart2; + serial9 = &uart9; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <100 160 190 200 215 235 255>; + fan-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0m2_pins &fan_int>; + pwms = <&pwm0 0 50000 0>; + #cooling-cells = <2>; + rockchip,temp-trips = < + 55000 1 + 60000 2 + 65000 3 + 70000 4 + 75000 5 + 80000 6 + >; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + rx_delay = <0x00>; + tx_delay = <0x43>; + + phy-handle = <&rgmii_phy1>; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&pcie2x1l1 { + linux,pci-domain = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_reset>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + linux,pci-domain = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>, <&pcie3_clkreqn_m1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fan { + fan_int: fan-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vga { + vga_hpdin_l: vga-hpdin-l { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_reset: pcie2-reset { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_clkreqn_m1: pcie3-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vcc3v3_pcie30_en: pcie3-reg { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_down>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_data_strobe>; + status = "okay"; +}; + +&dp0 { + pinctrl-names = "default"; + pinctrl-0 = <&vga_hpdin_l>; + hpd-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + ddc-i2c-rxfilter = <0x10>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&uart9 { + pinctrl-0 = <&uart9m0_xfer>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,sel-pipe-phystatus; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <3 2 1 0>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-9tripod-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588s-9tripod-linux.dts new file mode 100755 index 0000000000000..2b31a2f34a89e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-9tripod-linux.dts @@ -0,0 +1,1222 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Indiedroid Nova"; + compatible = "9tripod,rk3588s", "rockchip,rk3588"; + + /delete-node/ chosen; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + //spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + //hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT2", + "Headphone", "ROUT2", + "Speaker", "LOUT1", + "Speaker", "ROUT1", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + minipcie_power: minipcie-power { + compatible = "regulator-fixed"; + regulator-name = "minipcie_power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + //gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + //pinctrl-names = "default"; + //pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + //gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_2v8_cam_s0: vcc-2v8-cam-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v8_cam_s0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v2_cam_s0: vcc-1v2-cam-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_cam_s0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: vcc-1v8-cam-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_cam_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_s3>; + }; + +// ANDROID +// sdio_pwrseq: sdio-pwrseq { +// compatible = "mmc-pwrseq-simple"; +// clocks = <&hym8563>; +// clock-names = "ext_clock"; +// pinctrl-names = "default"; +// pinctrl-0 = <&wifi_enable_h>; +// /* +// * On the module itself this is one of these (depending +// * on the actual card populated): +// * - SDIO_RESET_L_WL_REG_ON +// * - PDN (power down when low) +// */ +// post-power-on-delay-ms = <200>; +// reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; +// }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "rtl8821cs"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,grf = <&sys_grf>; + status = "okay"; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&backlight { + pwms = <&pwm14 0 25000 0>; + enable-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + status = "disabled"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&dp0 { + //pinctrl-names = "default"; + //pinctrl-0 = <&dp0_hpd>; + //hpd-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <600>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + //power-supply = <&vcc3v3_lcd_n>; + //reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + reset-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hsync-len = <20>; + hback-porch = <150>; + vfront-porch = <8>; + vsync-len = <3>; + vback-porch = <24>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&dsi0_panel { + status = "disabled"; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + gslx680@40 { + compatible = "9tripod,gslx680"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_irq_gpio &tp_rst_gpio>; + touch-gpio = <&gpio0 RK_PD5 IRQ_TYPE_EDGE_RISING>; + reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + max-x = <1024>; + max-y = <600>; + status = "okay"; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + status = "okay"; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +// ES8388 Sound +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,i2s-tx-route = <3 2 1 0>; + rockchip,i2s-rx-route = <1 3 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_lrck + &i2s1m0_sdi1 + &i2s1m0_sdo3>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ + +&mipi_dcphy0 { + status = "disabled"; +}; + +&mpp_srv { + status = "okay"; +}; + +// PCIE +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + status = "okay"; +}; + +&pinctrl { + backlight { + bl_en: bl-en { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dp { + dp0_hpd: dp0-hpd { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +// ANDROID +// sdio-pwrseq { +// wifi_enable_h: wifi-enable-h { +// rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; +// }; +// }; + + tp_irq { + tp_irq_gpio: tp-irq-gpio { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + tp_rst_gpio: tp-rst-gpio { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + //vcc5v0_host_en: vcc5v0-host-en { + // rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + //}; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm14 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m1_pins>; +}; + +&rga2 { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp3_out_dsi0>; +}; + +&route_hdmi0{ + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +// EMMC +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +// WLAN +&sdio { + max-frequency = <100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + // mmc-pwrseq = <&sdio_pwrseq>; //ANDROID + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + // sd-uhs-sdr104; // commented out for sd card stability + status = "okay"; +}; + +// SD +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + //vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; +}; + +&tsadc { + status = "okay"; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; +}; + +&uart7 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; +}; + +// BT UART +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy2 { + status = "okay"; + rockchip,typec-vbus-det; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +// #USB3.1/DP PHY0 +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,dp-lane-mux = <2 3>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; + disable-win-move; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +/* pin 40 pwm fan control */ +&pwm15 { + pinctrl-0 = <&pwm15m1_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts new file mode 100644 index 0000000000000..949026d0a534f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -0,0 +1,1138 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Wesion Technology Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588-rk806-single-khadas.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Khadas Edge2"; + compatible = "khadas,edge2", "rockchip,rk3588"; + /delete-node/ chosen; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + home-key { + label = "home"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + sound_micarray: sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + es8316_sound: es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8316>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&red_led_gpio &green_led_gpio &blue_led_gpio>; + + red_led { + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + label = "red_led"; + linux,default-trigger = "none"; + default-state = "off"; + }; + + green_led { + gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + label = "green_led"; + linux,default-trigger = "default-on"; + default-state = "on"; + }; + + blue_led { + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + label = "blue_led"; + linux,default-trigger = "none"; + default-state = "off"; + }; + }; + + khadas_wdt { + compatible = "linux,wdt-khadas"; + status = "okay"; + hw_margin_ms = <500>; + hw-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_en>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi0"; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&pt7c4363>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <1>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + // WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s2_2ch { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + int-n-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + pt7c4363: pt7c4363@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pt7c4363"; + wakeup-source; + }; + + khadas_mcu: system-controller@18 { + compatible = "khadas,mcu"; + reg = <0x18>; + cooling-levels = <0 50 72 100>; + #cooling-cells = <2>; + }; +}; + +&reboot_mode { + mode-reboot_test = ; +}; + +&i2c3 { + status = "okay"; + + gs_kxtj3: gs_kxtj3@e { + compatible = "gs_kxtj3"; + reg = <0x0e>; + irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + status = "okay"; + }; + + es8316: es8316@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x10>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default","hp_det","spk_con"; + pinctrl-0 = <&i2s0_mclk>,<&hp_det>,<&spk_con>; + spk-con-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + }; + +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pdm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pdm0m0_clk + &pdm0m0_clk1 + &pdm0m0_sdi0 + &pdm0m0_sdi1 + &pdm0m0_sdi2>; + rockchip,path-map = <0 1 2 3>; + status = "okay"; +}; + +&pinctrl { + audio { + hp_det: hp-det { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + spk_con: spk-con { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + red_led_gpio: red-led-gpio { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + green_led_gpio: green-led-gpio { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + blue_led_gpio: blue-led-gpio { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_en: vcc-sd-en { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + // wifi_poweren_gpio: wifi-poweren-gpio { + // rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + // }; + }; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m3_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xeb KEY_POWER>, + <0xec KEY_MENU>, + <0xfc KEY_UP>, + <0xfd KEY_DOWN>, + <0xf1 KEY_LEFT>, + <0xe5 KEY_RIGHT>, + <0xf8 KEY_ENTER>, + <0xa7 KEY_VOLUMEDOWN>, + <0xa3 388>, + <0xa4 388>, + <0xf4 KEY_VOLUMEUP>, + <0xfe KEY_BACK>, + <0xb7 KEY_HOMEPAGE>; + }; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + | RKPM_SLP_PMU_DBG + ) + >; + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdmmc { + max-frequency = <150000000>; + card-detect-delay = <1200>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spdif_tx1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m1_tx>; +}; + +&spdif_tx1_dc { + status = "disabled"; +}; + +&spdif_tx1_sound { + status = "disabled"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&spi1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + +&soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <2000>; + + trips { + trip0: trip-point@0 { + temperature = <45000>; + hysteresis = <5000>; + type = "active"; + }; + + trip1: trip-point@1 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + + trip2: trip-point@2 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + + trip3: trip-point@3 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&khadas_mcu 0 1>; + contribution = <1024>; + }; + + map1 { + trip = <&trip1>; + cooling-device = <&khadas_mcu 1 2>; + contribution = <1024>; + }; + + map2 { + trip = <&trip2>; + cooling-device = <&khadas_mcu 2 3>; + contribution = <1024>; + }; + + map3 { + trip = <&trip3>; + cooling-device = <&khadas_mcu 3 THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vcc_1v8_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts new file mode 100644 index 0000000000000..18a4f00682fda --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts @@ -0,0 +1,1552 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 EmbedFire + * Copyright (c) 2023 erd-yunmu + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Embedfire LubanCat-4"; + compatible = "rockchip,rk3588s-lubancat-4", "rockchip,rk3588"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 coherent_pool=1m irqchip.gicv3_pseudo_nmi=0"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + power { + label = "power"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + leds: leds { + status = "okay"; + compatible = "gpio-leds"; + + sys_status_led: sys-status-led { + label = "sys_status_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sys_status_led_pin>; + }; + }; + + vcc5v0_dcin: vcc5v0-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_dcin>; + }; + + vcc_5v0: vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s3: vcc-3v3-sd-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec_vbus_en>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_pwr_en>; + }; + + vcc5v0_usb20_host: vcc5v0-usb20-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_pwr_en>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + mipi_dsi0_power: mipi-dsi0-power-regulator { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi0_power"; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + mipi_dsi1_power: mipi-dsi1-power-regulator { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi1_power"; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 4>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + + previous-song-key { + label = "previoussong"; + linux,code = ; + press-threshold-microvolt = <145000>; + }; + + next-song-key { + label = "nextsong"; + linux,code = ; + press-threshold-microvolt = <290000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm0 0 250000 0>; + cooling-levels = <0 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + >; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm6 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + test-power { + status = "okay"; + }; +}; + +&rockchip_suspend { + status = "disabled"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_CPU0_WKUP_EN + ) + >; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + upthreshold = <60>; + downdifferential = <30>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Typec Controller Fusb302 */ + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb302_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + /* 2800mv-3500mv */ + low_voltage_threshold = <3000>; + /* 2700mv-3400mv */ + shutdown_voltage_threshold = <2700>; + /* 140 160 */ + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + avcc_1v8_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avcc_3v3_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + avdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "avdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + nldo5_s0: NLDO_REG5 { + regulator-name = "nldo5_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&pwm6 { + pinctrl-0 = <&pwm6m0_pins>; + status = "okay"; +}; + +&pwm7 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key_lubancat{ + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xeb KEY_POWER>, + <0xec KEY_MENU>, + <0xfe KEY_BACK>, + <0xb7 KEY_HOME>, + <0xa3 KEY_WWW>, + <0xf4 KEY_VOLUMEUP>, + <0xa7 KEY_VOLUMEDOWN>, + <0xf8 KEY_REPLY>, + <0xfc KEY_UP>, + <0xfd KEY_DOWN>, + <0xf1 KEY_LEFT>, + <0xe5 KEY_RIGHT>; + }; + + ir_key2 { + rockchip,usercode = <0xf708>; + rockchip,key_table = + <0x28 KEY_POWER>, + <0xfe KEY_SETUP>, + <0xa4 KEY_MUTE>, + <0x6d KEY_UP>, + <0x68 KEY_LEFT>, + <0x64 KEY_ENTER>, + <0x60 KEY_RIGHT>, + <0x27 KEY_DOWN>, + <0x3c KEY_MENU>, + <0x7d KEY_HOME>, + <0x2b KEY_BACK>, + <0x7c KEY_VOLUMEDOWN>, + <0x79 KEY_VOLUMEUP>, + <0x57 KEY_AUDIO>, + <0x5d KEY_SUBTITLE>, + <0x99 KEY_PHONE>, + <0xfd KEY_WWW>, + <0xfc KEY_F1>, + <0x7e KEY_TV>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x30>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +/* SATA30/PCIe20x1_2 Combo PHY */ +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + disable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +/* USB3.1/DP Combo PHY0 */ +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +/* USB3.1 OTG0 Controller */ +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +/* USB2.0 PHY0 */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +/* USB3.1/SATA/PCIe20x1_1 Combo PHY */ +&combphy2_psu { + status = "okay"; +}; + +/* USB3.1 HOST2 Controller */ +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2.0 HOST0 PHY2 */ +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +/* USB2.0 HOST0 Controller */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB2.0 HOST1 PHY3 */ +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +/* USB2.0 HOST1 Controller */ +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* hdmi0 display */ +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + cec-enable = "true"; + status = "okay"; +}; + +&route_hdmi0{ + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +/* dp0 display */ +&dp0 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "dsiabled"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&vop { + status = "okay"; + disable-win-move; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + fusb302_int: fusb302-int { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec_vbus_en: typec-vbus-en { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb30_host_pwr_en: usb30-host-pwr-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb20_host_pwr_en: usb20-host-pwr-en { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + sys_status_led_pin: sys-status-led-pin { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts new file mode 100644 index 0000000000000..4ad1229ab338e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-m6.dts @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3588s-nanopi-r6-common.dtsi" + +/ { + model = "FriendlyElec NanoPi M6"; + compatible = "friendlyelec,nanopi-m6", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac1; + }; + + rt5616_sound: rt5616-sound { + status = "okay"; + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphone Jack"; + + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + fan: pwm-fan { + status = "okay"; + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm5 0 50000 0>; + cooling-levels = <0 35 64 100 150 255>; + rockchip,hold-time-ms = <2000>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + user_led: led-1 { + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "user_led"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_pin>; + }; + }; + + vcc3v3_pcie_m2: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_pwren>; + regulator-name = "vcc3v3_pcie_m2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host_20: vcc5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + pwm_backlight: pwm-backlight { + status = "disabled"; + compatible = "pwm-backlight"; + }; +}; + + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_prsnt>; + prsnt-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + vpcie3v3-supply = <&vcc3v3_pcie_m2>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&sata0 { + phys = <&combphy0_ps PHY_TYPE_SATA>; + target-supply = <&vcc3v3_pcie_m2>; + status = "disabled"; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + /omit-if-no-ref/ + lcd_rst0_gpio: lcd-rst0-gpio { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcd_rst1_gpio: lcd-rst1-gpio { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi0_gpio: touch-dsi0-gpio { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + touch_dsi1_gpio: touch-dsi1-gpio { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_m2_0_pwren: pcie-m20-pwren { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_m2_0_prsnt: pcie-m20-prsnt { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +// EEPROM is not mounted by default. +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: rt5616@1b { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "rt5616"; + reg = <0x1b>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + /* connected with MIPI-CSI1 */ +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + rockchip,trcm-sync-tx-only; +}; + +&pwm5 { + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/* GPIO Connector */ +&i2c1 { + pinctrl-0 = <&i2c1m2_xfer>; + status = "disabled"; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; + status = "disabled"; + + spidev0: spidev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "disabled"; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; +}; + +&uart4 { + pinctrl-0 = <&uart4m2_xfer>; + status = "disabled"; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; + status = "okay"; +}; + +&uart6 { + pinctrl-0 = <&uart6m1_xfer>; + status = "okay"; +}; + +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +&uart8 { + pinctrl-0 = <&uart8m0_xfer>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi new file mode 100644 index 0000000000000..093d52dbc69e8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 coherent_pool=1m irqchip.gicv3_pseudo_nmi=0"; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + simple_bat: battery { + compatible = "simple-battery"; + voltage-max-design-microvolt = <21000000>; + voltage-min-design-microvolt = <4500000>; + }; + + nanopi_adc_vin: nanopi-adc-vin { + compatible = "nanopi-adc-power-v2"; + io-channels = <&saradc 2>; + io-channel-names = "voltage"; + monitored-battery = <&simple_bat>; + }; + + test-power { + status = "okay"; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + upthreshold = <60>; + downdifferential = <30>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,no-vlhash; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&hdmi0 { + cec-enable; + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy0 { + /* Single Vdiff Training Table for power reduction (optional) */ + training-table = /bits/ 8 < + /* voltage swing 0, pre-emphasis 0->3 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 1, pre-emphasis 0->2 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 2, pre-emphasis 0->1 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 3, pre-emphasis 0 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + >; + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c7 { + status = "disabled"; +}; + +&i2c8 { + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xc43b>; + /* /system/usr/keylayout/Generic.kl */ + rockchip,key_table = + <0xff KEY_POWER>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xf2 KEY_UP>, + <0xea KEY_DOWN>, + <0xee KEY_ENTER>, + <0xe9 KEY_MUTE>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf3 KEY_VOLUMEUP>, + <0xae KEY_MENU>, + <0xeb KEY_LEFTMETA>, + <0xaf KEY_BACK>, + <0xf7 KEY_MODE>, + <0xe5 KEY_SYSRQ>, + <0xf5 KEY_ESC>; + }; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&rng { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + vop-supply = <&vdd_log_s0>; + support-multi-area; + status = "okay"; + disable-win-move; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&wdt { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts new file mode 100644 index 0000000000000..269d33d359470 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3588s-nanopi-r6s.dts" + +/ { + model = "FriendlyElec NanoPi R6C"; + compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588"; + + aliases { + ethernet0 = &r8125_u25; + }; +}; + +&lan2_led { + label = "user_led"; +}; + +&pcie2x1l2 { + rockchip,skip-hw-retry; + /delete-node/ pcie@40; +}; + +/* GPIO Connector */ +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m2_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts new file mode 100644 index 0000000000000..86291d51be3dc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + + /dts-v1/; + +#include "rk3588s-nanopi-r6-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R6S"; + compatible = "friendlyelec,nanopi-r6s", "rockchip,rk3588"; + + aliases { + ethernet0 = &r8125_u25; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + vcc5v0_host_20: vcc5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&pcie2x1l1 { + pcie@30 { + reg = <0x00300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u25: pcie@30,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie2x1l2 { + pcie@40 { + reg = <0x00400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u40: pcie@40,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + + +&uart4 { + pinctrl-0 = <&uart4m2_xfer>; + status = "disabled"; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi new file mode 100755 index 0000000000000..f87e5567d378f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy0_hw { + status = "disabled"; +}; + +&csi2_dphy0 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out2>; + data-lanes = <1 2>; + }; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + vm149c_p1: vm149c-p1@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_1: ov13850-1@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p1>; + port { + ov13850_out2: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p1: dw9714-p1@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855-1@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p1>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "disabled"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0_vir1 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi new file mode 100755 index 0000000000000..2ae9ac623b938 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_cam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out>; + data-lanes = <1 2>; + }; + + mipi_in_cam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + vm149c_p2: vm149c-p2@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_2: ov13850-2@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p2>; + port { + ov13850_out: endpoint { + remote-endpoint = <&mipi_in_cam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p2: dw9714-p2@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_2: ov13855-2@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p2>; + port { + ov13855_out: endpoint { + remote-endpoint = <&mipi_in_cam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "disabled"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "disabled"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + +&rkisp0_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi new file mode 100755 index 0000000000000..c1d6f49dc6e96 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy1 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_dcphy0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out1>; + data-lanes = <1 2>; + }; + + mipi_in_dcphy1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vm149cp1: vm149c@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + }; + + ov13850_3: ov13850@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149cp1>; + port { + ov13850_out1: endpoint { + remote-endpoint = <&mipi_in_dcphy0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_3: ov13855@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipi_in_dcphy1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "disabled"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "disabled"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in0>; + }; + }; +}; + +&rkisp1_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera1.dtsi new file mode 100644 index 0000000000000..6f4231e157a2d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera1.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy0 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out2>; + data-lanes = <1 2>; + }; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + vm149c_p1: vm149c-p1@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_1: ov13850-1@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera3_clk>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p1>; + port { + ov13850_out2: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p1: dw9714-p1@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855-1@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera3_clk>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p1>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "disabled"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0_vir1 { + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera2.dtsi new file mode 100644 index 0000000000000..09d796c2ff9eb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera2.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_cam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13850_out>; + data-lanes = <1 2>; + }; + + mipi_in_cam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + vm149c_p2: vm149c-p2@c { + compatible = "silicon touch,vm149c"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13850_2: ov13850-2@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&vm149c_p2>; + port { + ov13850_out: endpoint { + remote-endpoint = <&mipi_in_cam0>; + data-lanes = <1 2>; + }; + }; + }; + + dw9714_p2: dw9714-p2@c { + compatible = "dongwoon,dw9714"; + status = "disabled"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_2: ov13855-2@36 { + compatible = "ovti,ov13855"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9714_p2>; + port { + ov13855_out: endpoint { + remote-endpoint = <&mipi_in_cam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "disabled"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "disabled"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + +&rkisp1_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts new file mode 100644 index 0000000000000..9c14c4a6db3e0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts @@ -0,0 +1,956 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" + +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588s-orangepi-5-pro-camera1.dtsi" +#include "rk3588s-orangepi-5-pro-camera2.dtsi" + +/ { + model = "Orange Pi 5 Pro"; + compatible = "rockchip,rk3588s-orangepi-5-pro", "rockchip,rk3588"; + /delete-node/ chosen; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + test-power { + status = "disabled"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + hp-con-gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s2_2ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + dp_en: dp-en { + compatible = "regulator-fixed"; + regulator-name = "dp_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_otg: vcc5v0-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc3v3_pcie_eth: vcc3v3-pcie-eth { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_eth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + vin-supply = <&vcc_3v3_s3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_LOW>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6256"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_rgb>; + status = "okay"; + + blue_led@1 { + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + label = "blue_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + + green_led@2 { + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "green_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm2 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + + status = "okay"; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; + disable-win-move; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&vp1 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&vp2 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&vp3 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + rockchip,primary-plane = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&spdif_tx2{ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s2>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s2>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_mclk>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + status = "okay"; + }; + +}; + +&i2s2_2ch { + status = "okay"; + + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +//phy2 +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +//phy0 +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dp0 { + dp0_hpd: dp0-hpd { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart7-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds_gpio { + leds_rgb: leds-rgb { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m1_pins>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; + extcon = <&u2phy0>; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&usbdp_phy0 { + status = "okay"; + rockchip,dp-lane-mux = <0 1>; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&dp0 { + pinctrl-names = "default"; + pinctrl-0 = <&dp0_hpd>; + hpd-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +/* watchdog */ +&wdt { + status = "okay"; +}; + +&sfc { + status = "disabled"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&pwm6 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + status = "okay"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; +}; + +&spi0 { + assigned-clocks = <&cru CLK_SPI0>; + assigned-clock-rates = <200000000>; + num-cs = <2>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&spi4 { + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file mode 100755 index 0000000000000..fe6e843f4cea1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -0,0 +1,1165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588-rk806-single.dtsi" +#include +#include +#include +#include +#include +#include +#include + +#include "rk3588s-orangepi-5-camera1.dtsi" +#include "rk3588s-orangepi-5-camera2.dtsi" +#include "rk3588s-orangepi-5-camera3.dtsi" + +/ { + model = "Orange Pi 5"; + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; + + /delete-node/ chosen; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + enable-active-low; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + status = "okay"; + + led@1 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&can1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; +}; + +/* + pin15: GPIO0_D4 + pin12: GPIO0_D5 +*/ +&can2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <200000000>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +/* Fix tty terminal out of screen, and most dclk of resolutions was not supported in hdmiphy clock from parent clock by default */ +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + cec-enable; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + //pinctrl-0 = <&i2c1m4_xfer>; + pinctrl-0 = <&i2c1m2_xfer>; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +/* + pin3: GPIO1_B7 + pin5: GPIO1_B6 +*/ +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + es8388: es8388@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_i2s1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s1>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,i2s-tx-route = <3 2 1 0>; + rockchip,i2s-rx-route = <1 3 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_lrck + &i2s1m0_sdi1 + &i2s1m0_sdo3>; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pinctrl { + sata { + sata_reset:sata-reset{ + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-func { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +/* + pin26: GPIO1_A3 +*/ +&pwm1 { + status = "disabled"; + pinctrl-names = "active"; + //pinctrl-0 = <&pwm1m2_pins>; + pinctrl-0 = <&pwm1m1_pins>; +}; + +&pwm3 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m2_pins>; + //pinctrl-0 = <&pwm3m0_pins>; +}; + +&pwm13 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; +}; + +/* + pin11: GPIO4_B2 + pin13: GPIO4_B3 +*/ +&pwm14 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m1_pins>; +}; + +/* + pin7: GPIO1_C6 +*/ +&pwm15 { + status = "disabled"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m2_pins>; +}; + +&sata0 { + pinctrl-names = "default"; + pinctrl-0 = <&sata_reset>; + status = "disabled"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + status = "okay"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&spdif_tx2 { + status = "okay"; +}; + +/* + pin19: GPIO1_C1 + pin21: GPIO1_C0 + pin23: GPIO1_C2 + pin24: GPIO1_C4 +*/ +&spi4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + spi_dev@1 { + compatible = "rockchip,spidev"; + reg = <1>; + spi-max-frequency = <50000000>; + }; +}; + +/* + pin8: GPIO4_A3 + pin10: GPIO4_A4 +*/ +&uart0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +&uart1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; +}; + +&uart3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +/* + pin16: GPIO1_D3 + pin18: GPIO1_D2 +*/ +&uart4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +/* watchdog */ +&wdt { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbhost3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&vop { + status = "okay"; + disable-win-move; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts new file mode 100644 index 0000000000000..183f2aca99574 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-orangepi-5.dts" + +/ { + model = "Orange Pi 5B"; + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; +}; + +&sdhci { + status = "okay"; +}; + +&sfc { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "okay"; +}; + +&wireless_wlan { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts new file mode 100644 index 0000000000000..b085bff0f4ab3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Radxa Limited + * + */ + +/dts-v1/; + +#include "rk3588s-radxa-cm5.dtsi" + +/ { + model = "Radxa CM5 IO"; + compatible = "radxa,cm5-io", "radxa,cm5", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-hdmi1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8316"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8316>; + poll-interval = <100>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + hp-det-gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; + play-pause-key { + label = "playpause"; + linux,code = <164>; + press-threshold-microvolt = <2000>; + }; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <100 160 190 200 215 235 255>; + pwms = <&pwm11 0 10000 0>; + rockchip,temp-trips = < + 55000 1 + 60000 2 + 65000 3 + 70000 4 + 75000 5 + 80000 6 + >; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + pinctrl-0 = <&i2c8m2_xfer>; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + status = "okay"; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&pwm4 { + status = "okay"; + pinctrl-0 = <&pwm4m0_pins>; +}; + +&pwm11 { + status = "okay"; + pinctrl-0 = <&pwm11m3_pins>; +}; + +&sdhci { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&pinctrl { + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302 { + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "PIN_12", "", + /* GPIO0_C4-C7 */ + "", "", "", "PIN_31", + + /* GPIO0_D0-D3 */ + "PIN_29", "", "", "PIN_40", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "", "", "", + /* GPIO1_A4-A7 */ + "", "", "", "", + + /* GPIO1_B0-B3 */ + "", "PIN_22", "", "", + /* GPIO1_B4-B7 */ + "", "", "", "PIN_32", + + /* GPIO1_C0-C3 */ + "", "PIN_33", "", "", + /* GPIO1_C4-C7 */ + "PIN_16", "", "PIN_36", "", + + /* GPIO1_D0-D3 */ + "", "", "PIN_38", "", + /* GPIO1_D4-D7 */ + "", "PIN_18", "PIN_28", "PIN_27"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "", "", "", "", + /* GPIO3_B4-B7 */ + "", "", "", "PIN_26", + + /* GPIO3_C0-C3 */ + "PIN_35", "", "", "", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "", "", "PIN_5", "PIN_3", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "PIN_21", "PIN_19", "PIN_23", "", + /* GPIO4_A4-A7 */ + "PIN_15", "PIN_13", "PIN_11", "PIN_7", + + /* GPIO4_B0-B3 */ + "", "", "PIN_24", "", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-rpi-cm4-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-rpi-cm4-io.dts new file mode 100644 index 0000000000000..ef36f2b01d8ec --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-rpi-cm4-io.dts @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Radxa Limited + * + */ + +/dts-v1/; + +#include "rk3588s-radxa-cm5.dtsi" + +/ { + model = "Radxa CM5 RPI CM4 IO"; + compatible = "radxa,cm5-rpi-cm4-io", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + usb20_reset: usb-up-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_reset_pin>; + regulator-name = "usb20_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gpio_leds { + activity-led-green { + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + pwr-led-red { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; +}; + +&sdhci { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + + emc2301: emc2301@2f { + status = "okay"; + compatible = "microchip,emc2301"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #cooling-cells = <2>; + microchip,pwm-separate; + microchip,cooling-levels = <10>; + channel@0 { + reg = <0>; + pwm-min = <0>; + }; + }; + + pcf85063: pcf85063@51 { + compatible = "nxp,pcf85063"; + status = "okay"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; +}; + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + cooling-maps { + sustainable-power = <5000>; /* milliwatts */ + map3 { + trip = <&target>; + cooling-device = + <&emc2301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + map4 { + trip = <&threshold>; + cooling-device = + <&emc2301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + }; +}; + +&pinctrl { + + usb { + usb20_reset_pin: usb20-reset { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd>; + status = "okay"; +}; + +/* Fix the issue of board howling */ +&vdd_cpu_big0_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_cpu_big1_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_npu_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_gpu_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_cpu_lit_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_log_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_vdenc_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_ddr_s0 { + regulator-initial-mode = <1>; +}; + +&vdd2_ddr_s3 { + regulator-initial-mode = <1>; +}; + +&vcc_2v0_pldo_s3 { + regulator-initial-mode = <1>; +}; + +&vcc_3v3_s3 { + regulator-initial-mode = <1>; +}; + +&vddq_ddr_s0 { + regulator-initial-mode = <1>; +}; + +&vcc_1v8_s3 { + regulator-initial-mode = <1>; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "PIN_5", + + /* GPIO0_D0-D3 */ + "PIN_3", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "PIN_38", "PIN_40", "PIN_12", + /* GPIO1_A4-A7 */ + "PIN_36", "", "PIN_18", "PIN_16", + + /* GPIO1_B0-B3 */ + "PIN_22", "PIN_21", "PIN_19", "PIN_23", + /* GPIO1_B4-B7 */ + "PIN_24", "PIN_26", "", "", + + /* GPIO1_C0-C3 */ + "", "", "PIN_11", "PIN_15", + /* GPIO1_C4-C7 */ + "", "PIN_13", "", "PIN_29", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "PIN_7", "", "PIN_28", "PIN_27"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "", "", "", "", + /* GPIO3_B4-B7 */ + "", "", "", "", + + /* GPIO3_C0-C3 */ + "", "", "", "", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "PIN_37", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "PIN_33", "PIN_31", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "PIN_32", "", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi new file mode 100644 index 0000000000000..fdb2d754c76e1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + compatible = "radxa,cm5", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + status-led-blue { + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + eeprom: at24c16@50 { + status = "okay"; + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + cec-enable = "true"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + // Reset time is 20ms, 100ms for rtl8211f + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x41>; + rx_delay = <0x3a>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&vdd_0v75_s0 { + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e52c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e52c.dts new file mode 100644 index 0000000000000..332dc5a85f94f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e52c.dts @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Radxa E52C"; + compatible = "radxa,e52c", "rockchip,rk3588"; + + /delete-node/ chosen; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + pwms = <&pwm3 0 10000 0>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_5v0: vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + vin-supply = <&vcc5v0_sys>; + }; + + gpio-leds { + compatible = "gpio-leds"; + + sys-led { + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + wan-led { + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + + lan-led { + gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +/* CPU */ + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +/* GPU */ + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +/* NPU */ + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +/* Storage */ +/* eMMC */ + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +/* SD */ + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +/* ADC */ + +&tsadc { + status = "okay"; +}; + +/* HDMI */ + +&hdmi0 { + status = "okay"; + cec-enable = "true"; + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim1_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +/* Video Ports */ + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +/* USB */ + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + vbus-supply = <&vcc5v0_otg>; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + extcon = <&u2phy0>; + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +/* PCIe */ + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + status = "okay"; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; +}; + +&combphy2_psu { + status = "okay"; +}; + +&pcie2x1l1 { + status = "okay"; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3m1_pins>; +}; + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + cooling-maps { + map4 { + trip = <&target>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + map5 { + trip = <&threshold>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-0 = <&i2c5m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pinctrl { + power { + vcc_5v0_en: vcc-5v0-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-nx5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-nx5-io.dts new file mode 100644 index 0000000000000..4d1df55f8fc10 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-nx5-io.dts @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Radxa Limited + * + */ + +/dts-v1/; + +#include "rk3588s-radxa-nx5-module.dtsi" + +/ { + model = "Radxa NX5 IO"; + compatible = "radxa,nx5-io", "rockchip,rk3588"; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <512>; + rockchip,card-name= "rockchip-hdmi1"; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + pwms = <&pwm12 0 10000 0>; + }; + + bluetooth_en: bluetooth-en { + compatible = "regulator-fixed"; + regulator-name = "bluetooth_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-low; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ble_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led0_en &led1_en>; + pinctrl-names = "default"; + state_led { + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + cooling-maps { + map4 { + trip = <&target>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + map5 { + trip = <&threshold>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + }; +}; + +&threshold { + temperature = <60000>; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + vpcie3v3-supply = <&vcc3v3_pcie>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; + dr_mode = "host"; + /* Fix usb suspend failure */ + snps,dis_u3_susphy_quirk; +}; + +&usbdp_phy0 { + status = "okay"; + rockchip,dp-lane-mux = < 0 1 2 3>; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&dp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_hpd>; + hpd-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&sdhci { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&sdmmc { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +/* Fix the issue of board howling */ +&vdd_cpu_big0_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_cpu_big1_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_npu_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_gpu_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_cpu_lit_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_log_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_vdenc_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_ddr_s0 { + regulator-initial-mode = <1>; +}; + +&vdd2_ddr_s3 { + regulator-initial-mode = <1>; +}; + +&vcc_2v0_pldo_s3 { + regulator-initial-mode = <1>; +}; + +&vcc_3v3_s3 { + regulator-initial-mode = <1>; +}; + +&vddq_ddr_s0 { + regulator-initial-mode = <1>; +}; + +&vcc_1v8_s3 { + regulator-initial-mode = <1>; +}; + +&pinctrl { + dp { + dp0_hpd: dp0-hpd { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bluetooth { + ble_en: ble-en { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + led { + led1_en: led1-en { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "PIN_31", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "PIN_15", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "", + + /* GPIO0_D0-D3 */ + "", "", "", "", + /* GPIO0_D4-D7 */ + "PIN_3", "PIN_5", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "PIN_33", "", "", + /* GPIO1_A4-A7 */ + "", "", "", "", + + /* GPIO1_B0-B3 */ + "", "PIN_21", "PIN_19", "PIN_23", + /* GPIO1_B4-B7 */ + "PIN_24", "PIN_26", "", "", + + /* GPIO1_C0-C3 */ + "PIN_7", "", "", "PIN_12", + /* GPIO1_C4-C7 */ + "", "PIN_35", "", "PIN_40", + + /* GPIO1_D0-D3 */ + "PIN_22", "PIN_37", "PIN_13", "PIN_18", + /* GPIO1_D4-D7 */ + "PIN_38", "PIN_16", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "", "", "", "", + /* GPIO3_B4-B7 */ + "", "", "", "", + + /* GPIO3_C0-C3 */ + "", "", "", "", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "", "", "PIN_11", "PIN_36", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "", "", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "", "PIN_32", + /* GPIO4_B4-B7 */ + "", "", "PIN_29", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-nx5-module.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-nx5-module.dtsi new file mode 100644 index 0000000000000..66f894a5e0a16 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-nx5-module.dtsi @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Radxa NX5 Module"; + compatible = "radxa,nx5-module", "rockchip,rk3588"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + mmc2 = &sdio; + }; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led0_en>; + pinctrl-names = "default"; + user_led { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&sdhci { + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vcc_1v8_s3>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gmac1 { + status = "okay"; + // Use rgmii-rxid mode to disable rx delay inside Soc + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + // Reset time is 20ms, 100ms for rtl8211f + snps,reset-delays-us = <0 200000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x43>; + //rx_delay = <0x3e>; + + phy-handle = <&rgmii_phy1>; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m3_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + led { + led0_en: led0-en { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-retro-lite-cm5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-retro-lite-cm5.dts new file mode 100644 index 0000000000000..7aca7a9e93702 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-retro-lite-cm5.dts @@ -0,0 +1,1008 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 StonedEdge and GinKage + * + */ + +/dts-v1/; + +#include "rk3588s-radxa-cm5.dtsi" +#include +#include +#include + +/ { + model = "Retro Lite CM5"; + compatible = "retro-lite,cm5", "radxa,cm5", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-hdmi1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <15 35 55 75 100 140 160>; + pwms = <&pwm11 0 40000 0>; + }; + + wm8960_mclk: wm8960-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + wm8960_sound: wm8960-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "wm8960-soundcard"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphone Jack"; + sac_cpu: simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + sac_codec: simple-audio-card,codec { + sound-dai = <&wm8960>; + clocks = <&wm8960_mclk>; + clock-names = "mclk"; + }; + }; + + lcd_3v3: lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 PWM_POLARITY_INVERTED>; + brightness-levels = < + 0 6 6 6 6 6 6 6 + 6 6 6 6 6 6 6 6 + 6 6 6 6 6 6 6 6 + 6 6 6 6 6 6 6 6 + 6 7 7 7 7 7 7 7 + 7 7 7 7 7 7 7 7 + 7 7 7 8 8 8 8 8 + 8 8 8 8 8 8 8 8 + 8 9 9 9 9 9 9 9 + 9 9 9 10 10 10 10 10 + 10 10 10 11 11 11 11 11 + 11 11 12 12 12 12 12 12 + 12 13 13 13 13 13 14 14 + 14 14 14 15 15 15 15 16 + 16 16 16 17 17 17 17 18 + 18 18 19 19 19 19 20 20 + 20 21 21 22 22 22 23 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 33 33 34 34 35 36 + 36 37 38 39 39 40 41 42 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 61 62 63 64 66 67 + 68 70 71 73 74 76 77 79 + 80 82 84 86 87 89 91 93 + 95 97 99 101 103 105 107 110 + 112 114 117 119 122 124 127 130 + 132 135 138 141 144 147 150 153 + 156 160 163 167 170 174 177 181 + 185 189 193 197 201 206 210 215 + 219 224 229 234 239 244 249 255 + >; + default-brightness-level = <200>; + }; + + bq24292i_charger: charger { + compatible = "gpio-charger"; + charger-type = "usb-sdp"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + charge-status-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bq24292i_gpio>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&volume_keys>; + + key-vol-down { + label = "volume down"; + linux,code = ; + gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + key-vol-up { + label = "volume up"; + linux,code = ; + gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + key-power { + label = "lid"; + linux,code = ; + linux,input-type = ; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_poweroff: gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&poweroff_gpio>; + gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&usbdp_phy0 { + status = "okay"; + rockchip,dp-lane-mux = <0 1 3 2>; +}; + +&dp0 { + // force-hpd; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_hpd>; + hpd-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + AVDD-supply = <&vcc5v0_sys>; + DVDD-supply = <&vcc_3v3_s3>; + }; + + battery: battery@36 { + compatible = "maxim,max17055"; + reg = <0x36>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fuel_gauge>; + power-supplies = <&bq24292i_charger>; + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <800>; + maxim,dead-volt = <3100>; + maxim,over-volt = <4300>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt911"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + //AVDD28-supply = <&lcd_3v3>; + //VDDIO-supply = <&vcc_1v8_s0>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + rockchip,i2s-tx-route = <1 0 2 3>; + rockchip,i2s-rx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_lrck + &i2s1m0_sdi0 + &i2s1m0_sdo1>; +}; + +&pwm11 { + status = "okay"; + pinctrl-0 = <&pwm11m3_pins>; +}; + +&threshold { + temperature = <50000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@5 { + temperature = <80000>; + hysteresis = <5000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&pcritical>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; + vop-supply = <&vdd_log_s0>; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <550>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&lcd_3v3>; + power-supply = <&lcd_3v3>; + //vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rotation = <270>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + //te-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + + reset-delay-ms = <120>; + enable-delay-ms = <120>; + init-delay-ms = <120>; + stbyb-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + width-mm = <68>; + height-mm = <121>; + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 72 + 15 00 02 04 00 + 15 00 02 05 00 + 15 00 02 06 09 + 15 00 02 07 00 + 15 00 02 08 00 + 15 00 02 09 01 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 01 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 00 + 15 00 02 16 00 + 15 00 02 17 00 + 15 00 02 18 00 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e 40 + 15 00 02 1f 80 + 15 00 02 20 05 + 15 00 02 21 02 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 33 + 15 00 02 29 02 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 00 + 15 00 02 36 00 + 15 00 02 37 00 + 15 00 02 38 3C + 15 00 02 39 00 + 15 00 02 3a 40 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + 15 00 02 40 00 + 15 00 02 41 00 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 00 + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 11 + 15 00 02 5f 01 + 15 00 02 60 00 + 15 00 02 61 15 + 15 00 02 62 14 + 15 00 02 63 0E + 15 00 02 64 0F + 15 00 02 65 0C + 15 00 02 66 0D + 15 00 02 67 06 + 15 00 02 68 02 + 15 00 02 69 02 + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 07 + 15 00 02 6f 02 + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 02 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 01 + 15 00 02 76 00 + 15 00 02 77 14 + 15 00 02 78 15 + 15 00 02 79 0E + 15 00 02 7a 0F + 15 00 02 7b 0C + 15 00 02 7c 0D + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 07 + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 07 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 02 + 15 00 02 89 02 + 15 00 02 8A 02 + 39 00 04 FF 98 81 04 + 15 00 02 6C 15 + 15 00 02 6E 2A + 15 00 02 6F 33 + 15 00 02 3A 94 + 15 00 02 8D 1A + 15 00 02 87 BA + 15 00 02 26 76 + 15 00 02 B2 D1 + 15 00 02 B5 06 + 39 00 04 FF 98 81 01 + 15 00 02 22 0A + 15 00 02 31 00 + 15 00 02 53 98 + 15 00 02 55 98 + 15 00 02 50 AE + 15 00 02 51 AE + 15 00 02 60 28 + 15 00 02 A0 0F + 15 00 02 A1 1B + 15 00 02 A2 28 + 15 00 02 A3 12 + 15 00 02 A4 15 + 15 00 02 A5 28 + 15 00 02 A6 1B + 15 00 02 A7 1E + 15 00 02 A8 79 + 15 00 02 A9 1B + 15 00 02 AA 27 + 15 00 02 AB 69 + 15 00 02 AC 19 + 15 00 02 AD 18 + 15 00 02 AE 4C + 15 00 02 AF 21 + 15 00 02 B0 28 + 15 00 02 B1 52 + 15 00 02 B2 65 + 15 00 02 B3 3F + 15 00 02 C0 04 + 15 00 02 C1 1B + 15 00 02 C2 27 + 15 00 02 C3 13 + 15 00 02 C4 15 + 15 00 02 C5 28 + 15 00 02 C6 1C + 15 00 02 C7 1E + 15 00 02 C8 79 + 15 00 02 C9 1A + 15 00 02 CA 27 + 15 00 02 CB 69 + 15 00 02 CC 1A + 15 00 02 CD 18 + 15 00 02 CE 4C + 15 00 02 CF 21 + 15 00 02 D0 27 + 15 00 02 D1 52 + 15 00 02 D2 65 + 15 00 02 D3 3F + 39 00 04 FF 98 81 00 + 15 00 02 35 00 + 15 00 02 3A 70 + 05 78 01 11 + 05 14 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <59603000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <20>; + hsync-len = <6>; + hback-porch = <10>; + vfront-porch = <20>; + vsync-len = <4>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + //<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bq24292i { + bq24292i_gpio: bq24292i-gpio { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dp { + dp0_hpd: dp0-hpd { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + volume_keys: volume-keys { + rockchip,pins = + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + poweroff { + poweroff_gpio: poweroff-gpio { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gauge { + fuel_gauge: fuel-gauge { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + // rockchip,typec-vbus-det; + /delete-property/ rockchip,usbctrl-grf; + status = "okay"; + phy-supply = <&vcc5v0_sys>; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_sys>; +}; + +&u2phy3_host { + status = "okay"; + phy-supply = <&vcc5v0_sys>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + status = "okay"; + extcon = <&u2phy2>; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&rknpu { + status = "disabled"; +}; + +&rknpu_mmu { + status = "disabled"; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-retroled-cm5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-retroled-cm5.dts new file mode 100644 index 0000000000000..9172292af2796 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-retroled-cm5.dts @@ -0,0 +1,753 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 StonedEdge and GinKage + * + */ + +/dts-v1/; + +#include "rk3588s-radxa-cm5.dtsi" +#include +#include +#include + +/ { + model = "RetrOLED CM5"; + compatible = "retroled,cm5", "radxa,cm5", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-hdmi1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + bt_wake: bt-wake-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "bt_wake"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <15 55 95 135 175 215 255>; + pwms = <&pwm11 0 40000 0>; + }; + + wm8960_mclk: wm8960-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + wm8960_sound: wm8960-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "wm8960-soundcard"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphone Jack"; + sac_cpu: simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + sac_codec: simple-audio-card,codec { + sound-dai = <&wm8960>; + clocks = <&wm8960_mclk>; + clock-names = "mclk"; + }; + }; + + lcd_3v3: lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + bq24292i_charger: charger { + compatible = "gpio-charger"; + charger-type = "usb-sdp"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + charge-status-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bq24292i_gpio>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&volume_keys>; + + key-vol-down { + label = "volume down"; + linux,code = ; + gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + key-vol-up { + label = "volume up"; + linux,code = ; + gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + key-power { + label = "lid"; + linux,code = ; + linux,input-type = ; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_poweroff: gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&poweroff_gpio>; + gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&usbdp_phy0 { + status = "okay"; + rockchip,dp-lane-mux = <0 1 3 2>; +}; + +&dp0 { + // force-hpd; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_hpd>; + hpd-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + AVDD-supply = <&vcc5v0_sys>; + DVDD-supply = <&vcc_3v3_s3>; + }; + + battery: battery@36 { + compatible = "maxim,max17055"; + reg = <0x36>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fuel_gauge>; + power-supplies = <&bq24292i_charger>; + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <800>; + maxim,dead-volt = <3100>; + maxim,over-volt = <4300>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9886: gt9886@5d { + status = "okay"; + compatible = "goodix,gt9886"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <>x8_gpio>; + interrupt-parent = <&gpio1>; + interrupts = ; + goodix,irq-gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + goodix,reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-flags = <2>; /* 1:trigger rising, 2:trigger falling;*/ + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <1920>; + goodix,panel-max-w = <255>; + }; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + rockchip,i2s-tx-route = <1 0 2 3>; + rockchip,i2s-rx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_lrck + &i2s1m0_sdi0 + &i2s1m0_sdo1>; +}; + +&pwm11 { + status = "okay"; + pinctrl-0 = <&pwm11m3_pins>; +}; + +&threshold { + temperature = <50000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@5 { + temperature = <80000>; + hysteresis = <5000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&pcritical>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; + vop-supply = <&vdd_log_s0>; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <550>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "raydium,rm67199"; + reg = <0>; + + vdd-supply = <&lcd_3v3>; + power-supply = <&lcd_3v3>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rotation = <270>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + width-mm = <68>; + height-mm = <121>; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <133710720>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <26>; + hsync-len = <2>; + hback-porch = <36>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <16>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = + //<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gtx8 { + gtx8_gpio: gtx8-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bq24292i { + bq24292i_gpio: bq24292i-gpio { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dp { + dp0_hpd: dp0-hpd { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + volume_keys: volume-keys { + rockchip,pins = + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + poweroff { + poweroff_gpio: poweroff-gpio { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gauge { + fuel_gauge: fuel-gauge { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + // rockchip,typec-vbus-det; + /delete-property/ rockchip,usbctrl-grf; + status = "okay"; + phy-supply = <&vcc5v0_sys>; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_sys>; +}; + +&u2phy3_host { + status = "okay"; + phy-supply = <&vcc5v0_sys>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + status = "okay"; + extcon = <&u2phy2>; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&rknpu { + status = "disabled"; +}; + +&rknpu_mmu { + status = "disabled"; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts new file mode 100644 index 0000000000000..8c542a209623d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -0,0 +1,1094 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "ROC-RK3588S-PC V12(Linux)"; + compatible = "firefly,roc-rk3588s-pc", "firefly,station-m3", "rockchip,rk3588"; + + adc_keys: adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery-key{ + label = "F12"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + hp-con-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + hw-ver =<0x1>; + io-channels = <&saradc 5>; + io-channel-names = "hw-ver"; + linein-type = <1>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <384>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT2", + "Headphone", "ROUT2", + "Speaker", "LOUT1", + "Speaker", "ROUT1", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "LINPUT1", "Main Mic", + "RINPUT1", "Main Mic", + "LINPUT2", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc12v_dcin>; + cooling-levels = <60 100 140 160 185 220 255>; + pwms = <&pwm11 0 50000 1>; + }; + + firefly_leds: leds { + status = "okay"; + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + power_led: power { + label = ":power"; //green led + linux,default-trigger = "ir-power-click"; + default-state = "on"; + gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;//blue led + }; + + user_led: user { + label = ":user"; //yellow led + linux,default-trigger = "ir-user-click"; + default-state = "off"; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;//red led + }; + + user1_led: user1 { + label = ":user1"; + default-state = "off"; + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;//green led + }; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + lcd_rst: lcd_rst { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "lcd_rst"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + vin-supply = <&vcc12v_dcin>; + }; + + lcd_en: lcd_en { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "lcd_en"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + enable-active-high; + gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + reset-delay-us = <200000>; + startup-delay-us = <1200000>; + enable-active-high; + gpio = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec_pwr_en: vbus5v0-typec-pwr-en-regulator { + status = "okay"; + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vbus5v0_typec_pwr_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_LOW>; + enable-active-low; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_hub_reset: vcc-hub-reset-regulator { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_hub_reset"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + +}; + +&chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 coherent_pool=1m irqchip.gicv3_pseudo_nmi=0"; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +/* default use sata3.0 , pcie2.0 optional*/ +&combphy0_ps { + status = "okay"; +}; + +/* usb3.0 */ +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x43>; + //rx_delay = <0x4f>; + + phy-handle = <&rgmii_phy1>; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; +}; + +/* hdmi0 */ +&hdmi0 { + status = "okay"; + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; // For others Display Port Screen + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + + hym8563: hym8563@51 { + status = "okay"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + + usbc0: fusb302@22 { + status = "okay"; + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec_pwr_en>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +&i2c5 { + status = "disabled"; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@5 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&pcritical>; + cooling-device = <&fan 5 6>; + contribution = <1024>; + }; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm11 { + status = "okay"; + pinctrl-0 = <&pwm11m3_pins>; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + status = "okay"; + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; + +}; + +&route_hdmi0{ + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + status = "okay"; + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&sdmmc { + status = "okay"; + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; +}; + +&spdif_tx2{ + status = "okay"; +}; + +/* spi1 */ +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m2_cs0 &spi1m2_pins>; + num-cs = <1>; +}; + +/* PMIC spi2 */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; +}; + +&tsadc { + status = "okay"; +}; + +//usb +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + rockchip,typec-vbus-det; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +/* uart7 */ +&uart7{ + status = "okay"; + pinctrl-0 = <&uart7m2_xfer>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&pcie2x1l2 { + status = "okay"; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; +}; + +&pinctrl { + leds { + leds_gpio: leds-gpio { + rockchip,pins = + /* led_user */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + /* led_power */ + <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + /* led_user1 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +// for fan when deep sleep +&vdd_log_s0{ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&avcc_1v8_s0{ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0{ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +// for usb wakeup when deep sleep +&avdd_0v75_s0{ + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vcc_3v3_s0{ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts new file mode 100644 index 0000000000000..2d5c6327701a0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -0,0 +1,1020 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Radxa ROCK 5A"; + compatible = "radxa,rock-5a", "rockchip,rk3588"; + + /delete-node/ chosen; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <100 160 190 200 215 235 255>; + pwms = <&pwm3 0 10000 0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <512>; + rockchip,card-name= "rockchip-hdmi1"; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8316"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch >; + rockchip,codec = <&es8316>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + play-pause-key { + label = "playpause"; + linux,code = <164>; + press-threshold-microvolt = <2000>; + }; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + user-led1 { + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +/* CPU */ + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +/* GPU */ + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +/* NPU */ + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +/* Storage */ +/* eMMC */ + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_rstnout &emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe>; + status = "okay"; +}; + +/* SD */ + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +/* ADC */ + +&tsadc { + status = "okay"; +}; + +/* HDMI */ + +&hdmi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim1_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +/* DP */ + +&dp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_hpd>; + hpd-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +/* Video Ports */ + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +/* USB */ + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + vbus-supply = <&vcc5v0_otg>; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; + rockchip,dp-lane-mux = < 2 3 >; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +/* PCIe */ + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + status = "okay"; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; +}; + +/* Ethernet */ + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + // Reset time is 20ms, 100ms for rtl8211f + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x3a>; + rx_delay = <0x3e>; + + phy-handle = <&rgmii_phy1>; +}; + +/* I2C */ + +&i2c7 { + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3m1_pins>; +}; + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@5 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&pcritical>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + + power { + vcc_5v0_en: vcc-5v0-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifibt { + wl_reset: wl-reset { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wl_dis: wl-dis { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wl_wake_host: wl-wake-host { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_dis: bt-dis { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dp { + dp0_hpd: dp0-hpd { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_down>; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "PIN_27", + + /* GPIO0_D0-D3 */ + "PIN_28", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "PIN_21", "PIN_19", "PIN_23", "PIN_24", + /* GPIO1_A4-A7 */ + "PIN_26", "PIN_16", "", "", + + /* GPIO1_B0-B3 */ + "PIN_18", "PIN_31", "PIN_29", "PIN_7", + /* GPIO1_B4-B7 */ + "PIN_33", "PIN_22", "", "", + + /* GPIO1_C0-C3 */ + "", "", "", "", + /* GPIO1_C4-C7 */ + "", "", "", "", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "", "", "PIN_5", "PIN_3"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "", "", "", "", + /* GPIO3_B4-B7 */ + "", "", "", "", + + /* GPIO3_C0-C3 */ + "", "", "", "", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "PIN_35", "PIN_12", "PIN_36", "", + /* GPIO4_A4-A7 */ + "", "PIN_38", "", "", + + /* GPIO4_B0-B3 */ + "PIN_32", "PIN_40", "PIN_13", "PIN_11", + /* GPIO4_B4-B7 */ + "PIN_15", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts new file mode 100644 index 0000000000000..9f72ecd2d464a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -0,0 +1,905 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Radxa Limited + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Radxa ROCK 5C"; + compatible = "radxa,rock-5c", "rockchip,rk3588"; + + /delete-node/ chosen; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + pwms = <&pwm3 0 10000 0>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_5v0: vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + wifibt-power { + compatible = "regulator-fixed"; + regulator-name = "wifibt_power"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&wifibt_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + es8316_sound: es8316-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8316"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch >; + rockchip,codec = <&es8316>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + play-pause-key { + label = "playpause"; + linux,code = <164>; + press-threshold-microvolt = <2000>; + }; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + user-led1 { + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +/* CPU */ + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +/* GPU */ + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +/* NPU */ + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +/* Storage */ +/* eMMC */ + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +/* SD */ + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +/* ADC */ + +&tsadc { + status = "okay"; +}; + +/* HDMI */ + +&hdmi0 { + status = "okay"; + cec-enable = "true"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim1_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +/* Video Ports */ + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +/* USB */ + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + vbus-supply = <&vcc5v0_otg>; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +/* PCIe */ + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + status = "okay"; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; +}; + +/* Ethernet */ + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + // Reset time is 20ms, 100ms for rtl8211f + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x3a>; + rx_delay = <0x3e>; + + phy-handle = <&rgmii_phy1>; +}; + +/* I2C */ + +&i2c7 { + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + status = "okay"; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3m1_pins>; +}; + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + cooling-maps { + map3 { + trip = <&target>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + map4 { + trip = <&threshold>; + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + }; +}; + +&rockchip_suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&avdd_0v75_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; +}; + +&pinctrl { + + power { + vcc_5v0_en: vcc-5v0-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifibt { + wifibt_en: wifibit-en { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + host_wake_wl: host-wake-wl { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wl_wake_host: wl-wake-host { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "PIN_27", + + /* GPIO0_D0-D3 */ + "PIN_28", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "PIN_21", "PIN_19", "PIN_23", "PIN_24", + /* GPIO1_A4-A7 */ + "PIN_26", "PIN_16", "", "", + + /* GPIO1_B0-B3 */ + "PIN_18", "PIN_31", "PIN_29", "PIN_7", + /* GPIO1_B4-B7 */ + "PIN_33", "PIN_22", "", "", + + /* GPIO1_C0-C3 */ + "", "", "", "", + /* GPIO1_C4-C7 */ + "", "", "", "", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "", "", "PIN_5", "PIN_3"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "", "", "", "", + /* GPIO3_B4-B7 */ + "", "", "", "", + + /* GPIO3_C0-C3 */ + "", "", "", "", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "PIN_35", "PIN_12", "PIN_36", "", + /* GPIO4_A4-A7 */ + "", "PIN_38", "", "", + + /* GPIO4_B0-B3 */ + "PIN_32", "PIN_40", "PIN_13", "PIN_11", + /* GPIO4_B4-B7 */ + "PIN_15", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts b/arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts new file mode 100644 index 0000000000000..a80e8ce0dc5c1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-youyeetoo-r1.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-yyt-common.dtsi" +#include "rk3588s-yyt-lcd.dtsi" + +/ { + model = "Youyeetoo R1"; + compatible = "youyeetoo,r1", "rockchip,rk3588"; + + /* AUDIO */ + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT1", + "Speaker", "ROUT1", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "LINPUT1", "Headset Mic", + "RINPUT1", "Headset Mic", + "LINPUT2", "Main Mic", + "RINPUT2", "Main Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + /* BLUETOOTH */ + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + status = "okay"; + }; + + /* WIFI */ + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "rtl8852be"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + /* FAN */ + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <100 160 190 200 215 235 255>; + pwms = <&pwm6 0 40000 0>; + fan-supply = <&vcc12v_dcin>; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; +}; + +/* AUDIO */ +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +/* PWM */ +&pwm6{ + pinctrl-0 = <&pwm6m0_pins>; + pinctrl-names = "active"; + status = "okay"; +}; + +&pwm7{ + pinctrl-0 = <&pwm7m0_pins>; + pinctrl-names = "active"; + status = "okay"; +}; + +&pwm11 { + pinctrl-0 = <&pwm11m1_pins>; + pinctrl-names = "active"; + status = "okay"; +}; + +&pwm12 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m1_pins>; +}; + +/* LCD BACKLIGHT */ + +&backlight { + pwms = <&pwm12 0 25000 0>; + status = "okay"; + power-supply = <&vcc5v0_sys>; +}; + +&backlight1 { + pwms = <&pwm11 0 25000 0>; + status = "disabled"; + power-supply = <&vcc5v0_sys>; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-yyt-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-yyt-common.dtsi new file mode 100644 index 0000000000000..18f36391f30c0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-yyt-common.dtsi @@ -0,0 +1,953 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + + +/ { + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 coherent_pool=1m irqchip.gicv3_pseudo_nmi=0"; + }; + + /* HDMI SOUND */ + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi0"; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + }; + + /* POWER REGULATOR 12V DC-IN */ + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* POWER REGULATOR 5V SYS */ + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* POWER REGULATOR CPU */ + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* POWER REGULATOR 3V (SD) */ + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + /* POWER REGULATOR 3.3V (PCIE)*/ + + vcc_3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + /* POWER REGULATOR 5V (USB2 & USB3) */ + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host_20: vcc5v0-host-20 { // U13 (USB 2.0) + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_host_30: vcc5v0-host-30 { // U12 (USB 3.0) + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host30_en>; + regulator-name = "vcc5v0_host_30"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + /* POWER REGULATOR LCD DSI0/DSI1 */ + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s0>; + }; + + /* LED GREEN SYS */ + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_gpio>; + status = "okay"; + + led@1 { + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; +}; + +/* I2C */ + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +&i2c5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + /* RTC */ + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + status = "okay"; + }; +}; + + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c8 { + status = "disabled"; +}; + +/* CPU */ + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +/* GPU */ + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +/* NPU */ + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +/* HDMI */ + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + cec-enable = "true"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +/* VARIOUS */ +/* FAN CONTROL */ + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + sustainable-power = <5000>; /* milliwatts */ + polling-delay = <1000>; + polling-delay-passive = <2000>; + trips { + trip0: trip-point@0 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + trip1: trip-point@1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + trip2: trip-point@2 { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + trip3: trip-point@3 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + trip4: trip-point@4 { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; + pcritical: trip-point@5 { + temperature = <80000>; + hysteresis = <1000>; + type = "active"; + }; + }; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&fan0 0 1>; + contribution = <1024>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan0 1 2>; + contribution = <1024>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + contribution = <1024>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + contribution = <1024>; + }; + map4 { + trip = <&trip4>; + cooling-device = <&fan0 4 5>; + contribution = <1024>; + }; + map5 { + trip = <&pcritical>; + cooling-device = <&fan0 5 6>; + contribution = <1024>; + }; + }; +}; + +/* CAN */ +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0xc43b>; + /* /system/usr/keylayout/Generic.kl */ + rockchip,key_table = + <0xff KEY_POWER>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xf2 KEY_UP>, + <0xea KEY_DOWN>, + <0xee KEY_ENTER>, + <0xe9 KEY_MUTE>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf3 KEY_VOLUMEUP>, + <0xae KEY_MENU>, + <0xeb KEY_LEFTMETA>, + <0xaf KEY_BACK>, + <0xf7 KEY_MODE>, + <0xe5 KEY_SYSRQ>, + <0xf5 KEY_ESC>; + }; +}; + +&avcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +/* Storage */ +/* eMMC */ + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +/* SD */ + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +/* USB 2.0 / USB 3.0 */ + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_host_30>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; + extcon = <&u2phy0>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +/* PCIe */ + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +/* ADC */ + +&tsadc { + status = "okay"; +}; + +/* Ethernet */ + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + rx_delay = <0x00>; + tx_delay = <0x43>; + + phy-handle = <&rgmii_phy1>; + phy-supply = <&vcc_3v3_s3>; +}; + + +/* Video Ports */ + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + status = "okay"; + disable-win-move; +}; + +&vop_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + cursor-win-id=; + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&wdt { + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + +/* SPI */ + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m3_cs0 &spi0m3_cs1 &spi0m3_pins>; + num-cs = <2>; + spi_test@0 { + compatible = "rockchip,spi_test_bus0_cs1"; + reg = <0>; + spi-max-frequency = <5000000>; + }; +}; + + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; +}; + +/* UART */ + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&pinctrl { + /* HEADPHONE */ + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + /* RTC */ + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + /* SD */ + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + /* USB */ + usb { + vcc5v0_host20_en: vcc5v0-host20-en { // USB 2.0 + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vcc5v0_host30_en: vcc5v0-host30-en { // USB 3.0 + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + /* LCD */ + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + /* TOUCHSCREEN */ + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + /* WIRELESS */ + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + /* GPIO */ + gpio { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-yyt-lcd.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-yyt-lcd.dtsi new file mode 100644 index 0000000000000..0c4b5083ad0ae --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-yyt-lcd.dtsi @@ -0,0 +1,269 @@ +/* +* Youyeetoo R1 V3 - RK3588S +* LCD DSI0 & LCD DSI1 +* For some reason, pin cannot be reuse, so you've to compile it with DSI1_LCD/DSI0_LCD defined +* Currently Enabled: DSI0_LCD +*/ + +#define DSI0_LCD 1 +#define DSI1_LCD 0 + +#if DSI0_LCD +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "disabled"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 02 80 ac + 15 00 02 81 b8 + 15 00 02 82 09 + 15 00 02 83 78 + 15 00 02 84 7f + 15 00 02 85 bb + 15 00 02 86 70 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0:display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <51668640>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hback-porch = <160>; + hsync-len = <10>; + vfront-porch = <12>; + vsync-len = <10>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m2_xfer>; + + gt9xx: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + max-x = <1024>; + max-y = <600>; + tp-size = <911>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + + status = "okay"; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +#endif + +#if DSI1_LCD + +&dsi1 { + status = "okay"; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight1>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 02 80 ac + 15 00 02 81 b8 + 15 00 02 82 09 + 15 00 02 83 78 + 15 00 02 84 7f + 15 00 02 85 bb + 15 00 02 86 70 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1:display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <51668640>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hback-porch = <160>; + hsync-len = <10>; + vfront-porch = <12>; + vsync-len = <10>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&dsi1 { + pinctrl-names = "default"; + status = "okay"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&i2c5 { + status = "okay"; + pinctrl-0 = <&i2c5m3_xfer>; + + gt9xx: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + max-x = <1024>; + max-y = <600>; + tp-size = <911>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + + status = "okay"; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +#endif \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 1792f86da9082..8189cfa7df9d6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1734,7 +1734,7 @@ clocks = <&scmi_clk 4>; clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; - upthreshold = <40>; + upthreshold = <25>; downdifferential = <20>; system-status-level = < /*system status freq level*/ @@ -2387,6 +2387,62 @@ status = "disabled"; }; + gpu_panthor: gpu-panthor@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table_panthor>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table_panthor: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + gpu_opp_table: gpu-opp-table { compatible = "operating-points-v2"; diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig index e307074054553..ec9f6401e835b 100644 --- a/drivers/bluetooth/Kconfig +++ b/drivers/bluetooth/Kconfig @@ -442,4 +442,15 @@ config BT_VIRTIO Say Y here to compile support for HCI over Virtio into the kernel or say M to compile as a module. +config BT_HCIBTUSB_RTLBTUSB + tristate "Realtek HCI USB driver support" + depends on USB + help + Realtek Bluetooth HCI USB driver. + This driver is required if you want to use Realtek Bluetooth + device with USB interface. + + Say Y here to compile support for Bluetooth USB devices into the + kernel or say M to compile it as module (rtk_btusb). + endmenu diff --git a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile index 3321a8aea4a06..1552090be54cd 100644 --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@ -49,3 +49,6 @@ hci_uart-$(CONFIG_BT_HCIUART_QCA) += hci_qca.o hci_uart-$(CONFIG_BT_HCIUART_AG6XX) += hci_ag6xx.o hci_uart-$(CONFIG_BT_HCIUART_MRVL) += hci_mrvl.o hci_uart-objs := $(hci_uart-y) + +obj-$(CONFIG_BT_HCIBTUSB_RTLBTUSB) += rtk_btusb.o +rtk_btusb-objs := rtk_bt.o rtk_misc.o rtk_coex.o diff --git a/drivers/bluetooth/rtk_bt.c b/drivers/bluetooth/rtk_bt.c new file mode 100644 index 0000000000000..60ec72a4ae24e --- /dev/null +++ b/drivers/bluetooth/rtk_bt.c @@ -0,0 +1,1899 @@ +/* + * + * Realtek Bluetooth USB driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtk_bt.h" +#include "rtk_misc.h" + +#define VERSION "3.1.6d45ddf.20220519-142432" + +#ifdef BTCOEX +#include "rtk_coex.h" +#endif + +#ifdef RTKBT_SWITCH_PATCH +#include +#include +DEFINE_SEMAPHORE(switch_sem); +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 7, 1) +static bool reset = 0; +#endif + +static struct usb_driver btusb_driver; +static struct usb_device_id btusb_table[] = { + { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0bda, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x13d3, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0489, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x1358, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x04ca, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x2ff8, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0b05, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0930, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x10ec, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x04c5, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0cb5, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | + USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x0cb8, + .bInterfaceClass = 0xe0, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01 + }, { } +}; + +static void rtk_free(struct btusb_data *data) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 1) + kfree(data); +#endif + return; +} + +static struct btusb_data *rtk_alloc(struct usb_interface *intf) +{ + struct btusb_data *data; +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 1) + data = kzalloc(sizeof(*data), GFP_KERNEL); +#else + data = devm_kzalloc(&intf->dev, sizeof(*data), GFP_KERNEL); +#endif + return data; +} + +MODULE_DEVICE_TABLE(usb, btusb_table); + +static int inc_tx(struct btusb_data *data) +{ + unsigned long flags; + int rv; + + spin_lock_irqsave(&data->txlock, flags); + rv = test_bit(BTUSB_SUSPENDING, &data->flags); + if (!rv) + data->tx_in_flight++; + spin_unlock_irqrestore(&data->txlock, flags); + + return rv; +} + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) +static inline void btusb_free_frags(struct btusb_data *data) +{ + unsigned long flags; + + spin_lock_irqsave(&data->rxlock, flags); + + kfree_skb(data->evt_skb); + data->evt_skb = NULL; + + kfree_skb(data->acl_skb); + data->acl_skb = NULL; + + kfree_skb(data->sco_skb); + data->sco_skb = NULL; + + spin_unlock_irqrestore(&data->rxlock, flags); +} + +static int btusb_recv_intr(struct btusb_data *data, void *buffer, int count) +{ + struct sk_buff *skb; + int err = 0; + + spin_lock(&data->rxlock); + skb = data->evt_skb; + + while (count) { + int len; + + if (!skb) { + skb = bt_skb_alloc(HCI_MAX_EVENT_SIZE, GFP_ATOMIC); + if (!skb) { + err = -ENOMEM; + break; + } + + bt_cb(skb)->pkt_type = HCI_EVENT_PKT; + bt_cb(skb)->expect = HCI_EVENT_HDR_SIZE; + } + + len = min_t(uint, bt_cb(skb)->expect, count); + memcpy(skb_put(skb, len), buffer, len); + + count -= len; + buffer += len; + bt_cb(skb)->expect -= len; + + if (skb->len == HCI_EVENT_HDR_SIZE) { + /* Complete event header */ + bt_cb(skb)->expect = hci_event_hdr(skb)->plen; + + if (skb_tailroom(skb) < bt_cb(skb)->expect) { + kfree_skb(skb); + skb = NULL; + + err = -EILSEQ; + break; + } + } + + if (bt_cb(skb)->expect == 0) { + /* Complete frame */ + hci_recv_frame(data->hdev, skb); + skb = NULL; + } + } + + data->evt_skb = skb; + spin_unlock(&data->rxlock); + + return err; +} + +static int btusb_recv_bulk(struct btusb_data *data, void *buffer, int count) +{ + struct sk_buff *skb; + int err = 0; + + spin_lock(&data->rxlock); + skb = data->acl_skb; + + while (count) { + int len; + + if (!skb) { + skb = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC); + if (!skb) { + err = -ENOMEM; + break; + } + + bt_cb(skb)->pkt_type = HCI_ACLDATA_PKT; + bt_cb(skb)->expect = HCI_ACL_HDR_SIZE; + } + + len = min_t(uint, bt_cb(skb)->expect, count); + memcpy(skb_put(skb, len), buffer, len); + + count -= len; + buffer += len; + bt_cb(skb)->expect -= len; + + if (skb->len == HCI_ACL_HDR_SIZE) { + __le16 dlen = hci_acl_hdr(skb)->dlen; + + /* Complete ACL header */ + bt_cb(skb)->expect = __le16_to_cpu(dlen); + + if (skb_tailroom(skb) < bt_cb(skb)->expect) { + kfree_skb(skb); + skb = NULL; + + err = -EILSEQ; + break; + } + } + + if (bt_cb(skb)->expect == 0) { + /* Complete frame */ + hci_recv_frame(data->hdev, skb); + skb = NULL; + } + } + + data->acl_skb = skb; + spin_unlock(&data->rxlock); + + return err; +} + +static int btusb_recv_isoc(struct btusb_data *data, void *buffer, int count) +{ + struct sk_buff *skb; + int err = 0; + + spin_lock(&data->rxlock); + skb = data->sco_skb; + + while (count) { + int len; + + if (!skb) { + skb = bt_skb_alloc(HCI_MAX_SCO_SIZE, GFP_ATOMIC); + if (!skb) { + err = -ENOMEM; + break; + } + + bt_cb(skb)->pkt_type = HCI_SCODATA_PKT; + bt_cb(skb)->expect = HCI_SCO_HDR_SIZE; + } + + len = min_t(uint, bt_cb(skb)->expect, count); + memcpy(skb_put(skb, len), buffer, len); + + count -= len; + buffer += len; + bt_cb(skb)->expect -= len; + + if (skb->len == HCI_SCO_HDR_SIZE) { + /* Complete SCO header */ + bt_cb(skb)->expect = hci_sco_hdr(skb)->dlen; + + if (skb_tailroom(skb) < bt_cb(skb)->expect) { + kfree_skb(skb); + skb = NULL; + + err = -EILSEQ; + break; + } + } + + if (bt_cb(skb)->expect == 0) { + /* Complete frame */ + hci_recv_frame(data->hdev, skb); + skb = NULL; + } + } + + data->sco_skb = skb; + spin_unlock(&data->rxlock); + + return err; +} +#endif + +static void btusb_intr_complete(struct urb *urb) +{ + struct hci_dev *hdev = urb->context; + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + + //RTKBT_DBG("%s: urb %p status %d count %d ", __func__, + //urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + return; + + if (urb->status == 0) { + hdev->stat.byte_rx += urb->actual_length; + +#ifdef BTCOEX + rtk_btcoex_parse_event(urb->transfer_buffer, + urb->actual_length); +#endif +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 18, 0) + if (hci_recv_fragment(hdev, HCI_EVENT_PKT, + urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s: Corrupted event packet", __func__); + hdev->stat.err_rx++; + } +#else + if (btusb_recv_intr(data, urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s corrupted event packet", hdev->name); + hdev->stat.err_rx++; + } +#endif + } + /* Avoid suspend failed when usb_kill_urb */ + else if (urb->status == -ENOENT) { + return; + } + + if (!test_bit(BTUSB_INTR_RUNNING, &data->flags)) + return; + + usb_mark_last_busy(data->udev); + usb_anchor_urb(urb, &data->intr_anchor); + + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + /* -EPERM: urb is being killed; + * -ENODEV: device got disconnected */ + if (err != -EPERM && err != -ENODEV) + RTKBT_ERR("%s: Failed to re-submit urb %p, err %d", + __func__, urb, err); + usb_unanchor_urb(urb); + } +} + +static int btusb_submit_intr_urb(struct hci_dev *hdev, gfp_t mem_flags) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct urb *urb; + unsigned char *buf; + unsigned int pipe; + int err, size; + + //RTKBT_DBG("%s", hdev->name); + + if (!data->intr_ep) + return -ENODEV; + + urb = usb_alloc_urb(0, mem_flags); + if (!urb) + return -ENOMEM; + + size = le16_to_cpu(data->intr_ep->wMaxPacketSize); + + buf = kmalloc(size, mem_flags); + if (!buf) { + usb_free_urb(urb); + return -ENOMEM; + } + + pipe = usb_rcvintpipe(data->udev, data->intr_ep->bEndpointAddress); + + usb_fill_int_urb(urb, data->udev, pipe, buf, size, + btusb_intr_complete, hdev, data->intr_ep->bInterval); + + urb->transfer_flags |= URB_FREE_BUFFER; + + usb_anchor_urb(urb, &data->intr_anchor); + + err = usb_submit_urb(urb, mem_flags); + if (err < 0) { + RTKBT_ERR + ("btusb_submit_intr_urb %s urb %p submission failed (%d)", + hdev->name, urb, -err); + usb_unanchor_urb(urb); + } + + usb_free_urb(urb); + + return err; +} + +static void btusb_bulk_complete(struct urb *urb) +{ + struct hci_dev *hdev = urb->context; + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + + //RTKBT_DBG("%s: urb %p status %d count %d", + //__func__, urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + return; + +#ifdef BTCOEX + if (urb->status == 0) + rtk_btcoex_parse_l2cap_data_rx(urb->transfer_buffer, + urb->actual_length); +#endif + + if (urb->status == 0) { + hdev->stat.byte_rx += urb->actual_length; + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 18, 0) + if (hci_recv_fragment(hdev, HCI_ACLDATA_PKT, + urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s: Corrupted ACL packet", __func__); + hdev->stat.err_rx++; + } +#else + if (data->recv_bulk(data, urb->transfer_buffer, + urb->actual_length) < 0) { + RTKBT_ERR("%s corrupted ACL packet", hdev->name); + hdev->stat.err_rx++; + } +#endif + } + /* Avoid suspend failed when usb_kill_urb */ + else if (urb->status == -ENOENT) { + return; + } + + if (!test_bit(BTUSB_BULK_RUNNING, &data->flags)) + return; + + usb_anchor_urb(urb, &data->bulk_anchor); + usb_mark_last_busy(data->udev); + + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + /* -EPERM: urb is being killed; + * -ENODEV: device got disconnected */ + if (err != -EPERM && err != -ENODEV) + RTKBT_ERR + ("btusb_bulk_complete %s urb %p failed to resubmit (%d)", + hdev->name, urb, -err); + usb_unanchor_urb(urb); + } +} + +static int btusb_submit_bulk_urb(struct hci_dev *hdev, gfp_t mem_flags) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct urb *urb; + unsigned char *buf; + unsigned int pipe; + int err, size = HCI_MAX_FRAME_SIZE; + + //RTKBT_DBG("%s: hdev name %s", __func__, hdev->name); + + if (!data->bulk_rx_ep) + return -ENODEV; + + urb = usb_alloc_urb(0, mem_flags); + if (!urb) + return -ENOMEM; + + buf = kmalloc(size, mem_flags); + if (!buf) { + usb_free_urb(urb); + return -ENOMEM; + } + + pipe = usb_rcvbulkpipe(data->udev, data->bulk_rx_ep->bEndpointAddress); + + usb_fill_bulk_urb(urb, data->udev, pipe, + buf, size, btusb_bulk_complete, hdev); + + urb->transfer_flags |= URB_FREE_BUFFER; + + usb_mark_last_busy(data->udev); + usb_anchor_urb(urb, &data->bulk_anchor); + + err = usb_submit_urb(urb, mem_flags); + if (err < 0) { + RTKBT_ERR("%s: Failed to submit urb %p, err %d", __func__, urb, + err); + usb_unanchor_urb(urb); + } + + usb_free_urb(urb); + + return err; +} + +static void btusb_isoc_complete(struct urb *urb) +{ + struct hci_dev *hdev = urb->context; + struct btusb_data *data = GET_DRV_DATA(hdev); + int i, err; + + /* + RTKBT_DBG("%s urb %p status %d count %d", hdev->name, + urb, urb->status, urb->actual_length); + */ + if (!test_bit(HCI_RUNNING, &hdev->flags)) + return; + + if (urb->status == 0) { + for (i = 0; i < urb->number_of_packets; i++) { + unsigned int offset = urb->iso_frame_desc[i].offset; + unsigned int length = + urb->iso_frame_desc[i].actual_length; + + if (urb->iso_frame_desc[i].status) + continue; + + hdev->stat.byte_rx += length; + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 18, 0) + if (hci_recv_fragment(hdev, HCI_SCODATA_PKT, + urb->transfer_buffer + offset, + length) < 0) { + RTKBT_ERR("%s: Corrupted SCO packet", __func__); + hdev->stat.err_rx++; + } +#else + if (btusb_recv_isoc(data, urb->transfer_buffer + offset, + length) < 0) { + RTKBT_ERR("%s corrupted SCO packet", + hdev->name); + hdev->stat.err_rx++; + } +#endif + } + } + /* Avoid suspend failed when usb_kill_urb */ + else if (urb->status == -ENOENT) { + return; + } + + if (!test_bit(BTUSB_ISOC_RUNNING, &data->flags)) + return; + + usb_anchor_urb(urb, &data->isoc_anchor); + i = 0; +retry: + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + /* -EPERM: urb is being killed; + * -ENODEV: device got disconnected */ + if (err != -EPERM && err != -ENODEV) + RTKBT_ERR + ("%s: Failed to re-sumbit urb %p, retry %d, err %d", + __func__, urb, i, err); + if (i < 10) { + i++; + mdelay(1); + goto retry; + } + + usb_unanchor_urb(urb); + } +} + +static inline void __fill_isoc_descriptor(struct urb *urb, int len, int mtu) +{ + int i, offset = 0; + + //RTKBT_DBG("len %d mtu %d", len, mtu); + + for (i = 0; i < BTUSB_MAX_ISOC_FRAMES && len >= mtu; + i++, offset += mtu, len -= mtu) { + urb->iso_frame_desc[i].offset = offset; + urb->iso_frame_desc[i].length = mtu; + } + + if (len && i < BTUSB_MAX_ISOC_FRAMES) { + urb->iso_frame_desc[i].offset = offset; + urb->iso_frame_desc[i].length = len; + i++; + } + + urb->number_of_packets = i; +} + +static int btusb_submit_isoc_urb(struct hci_dev *hdev, gfp_t mem_flags) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct urb *urb; + unsigned char *buf; + unsigned int pipe; + int err, size; + + //RTKBT_DBG("%s", hdev->name); + + if (!data->isoc_rx_ep) + return -ENODEV; + + urb = usb_alloc_urb(BTUSB_MAX_ISOC_FRAMES, mem_flags); + if (!urb) + return -ENOMEM; + + size = le16_to_cpu(data->isoc_rx_ep->wMaxPacketSize) * + BTUSB_MAX_ISOC_FRAMES; + + buf = kmalloc(size, mem_flags); + if (!buf) { + usb_free_urb(urb); + return -ENOMEM; + } + + pipe = usb_rcvisocpipe(data->udev, data->isoc_rx_ep->bEndpointAddress); + + urb->dev = data->udev; + urb->pipe = pipe; + urb->context = hdev; + urb->complete = btusb_isoc_complete; + urb->interval = data->isoc_rx_ep->bInterval; + + urb->transfer_flags = URB_FREE_BUFFER | URB_ISO_ASAP; + urb->transfer_buffer = buf; + urb->transfer_buffer_length = size; + + __fill_isoc_descriptor(urb, size, + le16_to_cpu(data->isoc_rx_ep->wMaxPacketSize)); + + usb_anchor_urb(urb, &data->isoc_anchor); + + err = usb_submit_urb(urb, mem_flags); + if (err < 0) { + RTKBT_ERR("%s %s urb %p submission failed (%d)", + __func__, hdev->name, urb, err); + usb_unanchor_urb(urb); + } + + usb_free_urb(urb); + + return err; +} + +static void btusb_tx_complete(struct urb *urb) +{ + struct sk_buff *skb = urb->context; + struct hci_dev *hdev = (struct hci_dev *)skb->dev; + struct btusb_data *data = GET_DRV_DATA(hdev); + +// RTKBT_DBG("btusb_tx_complete %s urb %p status %d count %d", hdev->name, +// urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + goto done; + + if (!urb->status) + hdev->stat.byte_tx += urb->transfer_buffer_length; + else + hdev->stat.err_tx++; + +done: + spin_lock(&data->txlock); + data->tx_in_flight--; + spin_unlock(&data->txlock); + + kfree(urb->setup_packet); + + kfree_skb(skb); +} + +static void btusb_isoc_tx_complete(struct urb *urb) +{ + struct sk_buff *skb = urb->context; + struct hci_dev *hdev = (struct hci_dev *)skb->dev; + + RTKBT_DBG("%s: urb %p status %d count %d",__func__, + urb, urb->status, urb->actual_length); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) + goto done; + + if (!urb->status) + hdev->stat.byte_tx += urb->transfer_buffer_length; + else + hdev->stat.err_tx++; + +done: + kfree(urb->setup_packet); + + kfree_skb(skb); +} + +static int btusb_open(struct hci_dev *hdev) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + + err = usb_autopm_get_interface(data->intf); + if (err < 0) + return err; + + data->intf->needs_remote_wakeup = 1; + RTKBT_DBG("%s start", __func__); + + /*******************************/ + if (0 == atomic_read(&hdev->promisc)) { + RTKBT_ERR("btusb_open hdev->promisc ==0"); + //err = -1; + //goto failed; + } + + err = download_patch(data->intf); + if (err < 0) + goto failed; + /*******************************/ + + RTKBT_INFO("%s set HCI_RUNNING", __func__); + if (test_and_set_bit(HCI_RUNNING, &hdev->flags)) + goto done; + + if (test_and_set_bit(BTUSB_INTR_RUNNING, &data->flags)) + goto done; + + err = btusb_submit_intr_urb(hdev, GFP_KERNEL); + if (err < 0) + goto failed; + + err = btusb_submit_bulk_urb(hdev, GFP_KERNEL); + if (err < 0) { + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->intr_anchor); + goto failed; + } + + set_bit(BTUSB_BULK_RUNNING, &data->flags); + btusb_submit_bulk_urb(hdev, GFP_KERNEL); + +done: + usb_autopm_put_interface(data->intf); + +#ifdef BTCOEX + rtk_btcoex_open(hdev); +#endif + RTKBT_DBG("%s end", __FUNCTION__); + + return 0; + +failed: + clear_bit(BTUSB_INTR_RUNNING, &data->flags); + clear_bit(HCI_RUNNING, &hdev->flags); + usb_autopm_put_interface(data->intf); + RTKBT_ERR("%s failed", __FUNCTION__); + return err; +} + +static void btusb_stop_traffic(struct btusb_data *data) +{ + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->intr_anchor); + usb_kill_anchored_urbs(&data->bulk_anchor); + usb_kill_anchored_urbs(&data->isoc_anchor); +} + +static int btusb_close(struct hci_dev *hdev) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + int err; + +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 1, 0) + int i; +#endif + + /* When in kernel 4.4.0 and greater, the HCI_RUNNING bit is + * cleared in hci_dev_do_close(). */ +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 4, 0) + if (!test_and_clear_bit(HCI_RUNNING, &hdev->flags)) + return 0; +#else + if (test_bit(HCI_RUNNING, &hdev->flags)) { + RTKBT_ERR("HCI_RUNNING is not cleared before."); + return -1; + } +#endif + + RTKBT_DBG("btusb_close"); +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 1, 0) + /*******************************/ + for (i = 0; i < NUM_REASSEMBLY; i++) { + if (hdev->reassembly[i]) { + kfree_skb(hdev->reassembly[i]); + hdev->reassembly[i] = NULL; + RTKBT_DBG("%s free ressembly i=%d", __FUNCTION__, i); + } + } + /*******************************/ +#endif + cancel_work_sync(&data->work); + cancel_work_sync(&data->waker); + + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + clear_bit(BTUSB_BULK_RUNNING, &data->flags); + clear_bit(BTUSB_INTR_RUNNING, &data->flags); + + btusb_stop_traffic(data); +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + btusb_free_frags(data); +#endif + + err = usb_autopm_get_interface(data->intf); + if (err < 0) + goto failed; + + data->intf->needs_remote_wakeup = 0; + usb_autopm_put_interface(data->intf); + +#ifdef BTCOEX + rtk_btcoex_close(); +#endif + +failed: + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_scuttle_anchored_urbs(&data->deferred); + +#ifdef RTKBT_SWITCH_PATCH + down(&switch_sem); + if (data->context) { + struct api_context *ctx = data->context; + + if (ctx->flags & RTLBT_CLOSE) { + ctx->flags &= ~RTLBT_CLOSE; + ctx->status = 0; + complete(&ctx->done); + } + } + up(&switch_sem); +#endif + + return 0; +} + +static int btusb_flush(struct hci_dev *hdev) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + + RTKBT_DBG("%s add delay ", __FUNCTION__); + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->tx_anchor); +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + btusb_free_frags(data); +#endif + + return 0; +} + +const char pkt_ind[][8] = { + [HCI_COMMAND_PKT] = "cmd", + [HCI_ACLDATA_PKT] = "acl", + [HCI_SCODATA_PKT] = "sco", +}; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) +int btusb_send_frame(struct hci_dev *hdev, struct sk_buff *skb) +{ +#else +int btusb_send_frame(struct sk_buff *skb) +{ + struct hci_dev *hdev = (struct hci_dev *)skb->dev; +#endif + + struct btusb_data *data = GET_DRV_DATA(hdev); + struct usb_ctrlrequest *dr; + struct urb *urb; + unsigned int pipe; + int err; + + //RTKBT_DBG("%s", hdev->name); + + if (!test_bit(HCI_RUNNING, &hdev->flags)) { + /* If the parameter is wrong, the hdev isn't the correct + * one. Then no HCI commands can be sent. + * This issue is related to the wrong HCI_VERSION_CODE set */ + RTKBT_ERR("HCI is not running"); + return -EBUSY; + } + + /* Before kernel/hci version 3.13.0, the skb->dev is set before + * entering btusb_send_frame(). So there is no need to set it here. + * + * The skb->dev will be used in the callbacks when urb transfer + * completes. See btusb_tx_complete() and btusb_isoc_tx_complete() */ +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) + skb->dev = (void *)hdev; +#endif + + switch (bt_cb(skb)->pkt_type) { + case HCI_COMMAND_PKT: + print_command(skb); + +#ifdef BTCOEX + rtk_btcoex_parse_cmd(skb->data, skb->len); +#endif + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) + return -ENOMEM; + + dr = kmalloc(sizeof(*dr), GFP_ATOMIC); + if (!dr) { + usb_free_urb(urb); + return -ENOMEM; + } + + dr->bRequestType = data->cmdreq_type; + dr->bRequest = 0; + dr->wIndex = 0; + dr->wValue = 0; + dr->wLength = __cpu_to_le16(skb->len); + + pipe = usb_sndctrlpipe(data->udev, 0x00); + + usb_fill_control_urb(urb, data->udev, pipe, (void *)dr, + skb->data, skb->len, btusb_tx_complete, + skb); + + hdev->stat.cmd_tx++; + break; + + case HCI_ACLDATA_PKT: + print_acl(skb, 1); +#ifdef BTCOEX + rtk_btcoex_parse_l2cap_data_tx(skb->data, skb->len); +#endif + if (!data->bulk_tx_ep) + return -ENODEV; + + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) + return -ENOMEM; + + pipe = usb_sndbulkpipe(data->udev, + data->bulk_tx_ep->bEndpointAddress); + + usb_fill_bulk_urb(urb, data->udev, pipe, + skb->data, skb->len, btusb_tx_complete, skb); + + hdev->stat.acl_tx++; + break; + + case HCI_SCODATA_PKT: + if (!data->isoc_tx_ep || SCO_NUM < 1) + return -ENODEV; + + urb = usb_alloc_urb(BTUSB_MAX_ISOC_FRAMES, GFP_ATOMIC); + if (!urb) + return -ENOMEM; + + pipe = usb_sndisocpipe(data->udev, + data->isoc_tx_ep->bEndpointAddress); + + usb_fill_int_urb(urb, data->udev, pipe, + skb->data, skb->len, btusb_isoc_tx_complete, + skb, data->isoc_tx_ep->bInterval); + + urb->transfer_flags = URB_ISO_ASAP; + + __fill_isoc_descriptor(urb, skb->len, + le16_to_cpu(data->isoc_tx_ep-> + wMaxPacketSize)); + + hdev->stat.sco_tx++; + goto skip_waking; + + default: + return -EILSEQ; + } + + err = inc_tx(data); + if (err) { + usb_anchor_urb(urb, &data->deferred); + schedule_work(&data->waker); + err = 0; + goto done; + } + +skip_waking: + usb_anchor_urb(urb, &data->tx_anchor); + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + RTKBT_ERR("%s %s urb %p submission for %s failed, err %d", + __func__, hdev->name, urb, + pkt_ind[bt_cb(skb)->pkt_type], err); + kfree(urb->setup_packet); + usb_unanchor_urb(urb); + } else { + usb_mark_last_busy(data->udev); + } + usb_free_urb(urb); + +done: + return err; +} + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 4, 0) +static void btusb_destruct(struct hci_dev *hdev) +{ + RTKBT_DBG("btusb_destruct %s", hdev->name); + hci_free_dev(hdev); +} +#endif + +static void btusb_notify(struct hci_dev *hdev, unsigned int evt) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + + RTKBT_DBG("%s: %s evt %d", __func__, hdev->name, evt); + + if (SCO_NUM != data->sco_num) { + data->sco_num = SCO_NUM; + RTKBT_DBG("%s: Update sco num %d", __func__, data->sco_num); +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) + data->air_mode = evt; +#endif + schedule_work(&data->work); + } +} + +static inline int __set_isoc_interface(struct hci_dev *hdev, int altsetting) +{ + struct btusb_data *data = GET_DRV_DATA(hdev); + struct usb_interface *intf = data->isoc; + struct usb_endpoint_descriptor *ep_desc; + int i, err; + + if (!data->isoc) + return -ENODEV; + + RTKBT_INFO("set isoc interface: alt %d", altsetting); + + err = usb_set_interface(data->udev, 1, altsetting); + if (err < 0) { + RTKBT_ERR("%s setting interface failed (%d)", hdev->name, -err); + return err; + } + + data->isoc_altsetting = altsetting; + + data->isoc_tx_ep = NULL; + data->isoc_rx_ep = NULL; + + for (i = 0; i < intf->cur_altsetting->desc.bNumEndpoints; i++) { + ep_desc = &intf->cur_altsetting->endpoint[i].desc; + + if (!data->isoc_tx_ep && usb_endpoint_is_isoc_out(ep_desc)) { + data->isoc_tx_ep = ep_desc; + continue; + } + + if (!data->isoc_rx_ep && usb_endpoint_is_isoc_in(ep_desc)) { + data->isoc_rx_ep = ep_desc; + continue; + } + } + + if (!data->isoc_tx_ep || !data->isoc_rx_ep) { + RTKBT_ERR("%s invalid SCO descriptors", hdev->name); + return -ENODEV; + } + + return 0; +} + +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) +static int btusb_switch_alt_setting(struct hci_dev *hdev, int new_alts) +{ + struct btusb_data *data = hci_get_drvdata(hdev); + int err; + + if (data->isoc_altsetting != new_alts) { + unsigned long flags; + + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + usb_kill_anchored_urbs(&data->isoc_anchor); + + /* When isochronous alternate setting needs to be + * changed, because SCO connection has been added + * or removed, a packet fragment may be left in the + * reassembling state. This could lead to wrongly + * assembled fragments. + * + * Clear outstanding fragment when selecting a new + * alternate setting. + */ + spin_lock_irqsave(&data->rxlock, flags); + kfree_skb(data->sco_skb); + data->sco_skb = NULL; + spin_unlock_irqrestore(&data->rxlock, flags); + + err = __set_isoc_interface(hdev, new_alts); + if (err < 0) + return err; + } + + if (!test_and_set_bit(BTUSB_ISOC_RUNNING, &data->flags)) { + if (btusb_submit_isoc_urb(hdev, GFP_KERNEL) < 0) + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + else + btusb_submit_isoc_urb(hdev, GFP_KERNEL); + } + + return 0; +} + +static struct usb_host_interface *btusb_find_altsetting(struct btusb_data *data, + int alt) +{ + struct usb_interface *intf = data->isoc; + int i; + + BT_DBG("Looking for Alt no :%d", alt); + + for (i = 0; i < intf->num_altsetting; i++) { + if (intf->altsetting[i].desc.bAlternateSetting == alt) + return &intf->altsetting[i]; + } + + return NULL; +} +#endif + +static void btusb_work(struct work_struct *work) +{ + struct btusb_data *data = container_of(work, struct btusb_data, work); + struct hci_dev *hdev = data->hdev; + int err; + int new_alts = 0; + + RTKBT_DBG("%s: sco num %d", __func__, data->sco_num); + if (data->sco_num > 0) { + if (!test_bit(BTUSB_DID_ISO_RESUME, &data->flags)) { + err = + usb_autopm_get_interface(data->isoc ? data-> + isoc : data->intf); + if (err < 0) { + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + mdelay(URB_CANCELING_DELAY_MS); + usb_kill_anchored_urbs(&data->isoc_anchor); + return; + } + + set_bit(BTUSB_DID_ISO_RESUME, &data->flags); + } +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) + if (data->air_mode == HCI_NOTIFY_ENABLE_SCO_CVSD) { + if (hdev->voice_setting & 0x0020) { + static const int alts[3] = { 2, 4, 5 }; + new_alts = alts[data->sco_num - 1]; + } else { + new_alts = data->sco_num; + } + } else if (data->air_mode == HCI_NOTIFY_ENABLE_SCO_TRANSP) { + new_alts = btusb_find_altsetting(data, 6) ? 6 : 1; + } + + if (btusb_switch_alt_setting(hdev, new_alts) < 0) + RTKBT_ERR("set USB alt:(%d) failed!", new_alts); +#else +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 5, 0) + if (hdev->voice_setting & 0x0020) { + static const int alts[3] = { 2, 4, 5 }; + new_alts = alts[data->sco_num - 1]; + } else { + new_alts = data->sco_num; + } + if (data->isoc_altsetting != new_alts) { +#else + if (data->isoc_altsetting != 2) { + new_alts = 2; +#endif + + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + mdelay(URB_CANCELING_DELAY_MS); + usb_kill_anchored_urbs(&data->isoc_anchor); + + if (__set_isoc_interface(hdev, new_alts) < 0) + return; + } + + if (!test_and_set_bit(BTUSB_ISOC_RUNNING, &data->flags)) { + RTKBT_INFO("submit SCO RX urb."); + if (btusb_submit_isoc_urb(hdev, GFP_KERNEL) < 0) + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + else + btusb_submit_isoc_urb(hdev, GFP_KERNEL); + } +#endif + } else { + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + mdelay(URB_CANCELING_DELAY_MS); + usb_kill_anchored_urbs(&data->isoc_anchor); + + __set_isoc_interface(hdev, 0); + if (test_and_clear_bit(BTUSB_DID_ISO_RESUME, &data->flags)) + usb_autopm_put_interface(data->isoc ? data-> + isoc : data->intf); + } +} + +static void btusb_waker(struct work_struct *work) +{ + struct btusb_data *data = container_of(work, struct btusb_data, waker); + int err; + + err = usb_autopm_get_interface(data->intf); + RTKBT_DBG("%s start", __FUNCTION__); + if (err < 0) + return; + + usb_autopm_put_interface(data->intf); + RTKBT_DBG("%s end", __FUNCTION__); +} + +#ifdef RTKBT_TV_POWERON_WHITELIST +static int rtkbt_lookup_le_device_poweron_whitelist(struct hci_dev *hdev, + struct usb_device *udev) +{ + struct hci_conn_params *p; + u8 *cmd; + int result = 0; + + hci_dev_lock(hdev); + list_for_each_entry(p, &hdev->le_conn_params, list) { +#if 0 // for debug message + RTKBT_DBG("%s(): auto_connect = %d", __FUNCTION__, p->auto_connect); + RTKBT_DBG("%s(): addr_type = 0x%02x", __FUNCTION__, p->addr_type); + RTKBT_DBG("%s(): addr=%02x:%02x:%02x:%02x:%02x:%02x", __FUNCTION__, + p->addr.b[5], p->addr.b[4], p->addr.b[3], + p->addr.b[2], p->addr.b[1], p->addr.b[0]); +#endif + if ( p->auto_connect == HCI_AUTO_CONN_ALWAYS && + p->addr_type == ADDR_LE_DEV_PUBLIC ) { + + RTKBT_DBG("%s(): Set RTKBT LE Power-on Whitelist for " + "%02x:%02x:%02x:%02x:%02x:%02x", __FUNCTION__, + p->addr.b[5], p->addr.b[4], p->addr.b[3], + p->addr.b[2], p->addr.b[1], p->addr.b[0]); + + cmd = kzalloc(16, GFP_ATOMIC); + if (!cmd) { + RTKBT_ERR("Can't allocate memory for cmd"); + return -ENOMEM; + } + cmd[0] = 0x7b; + cmd[1] = 0xfc; + cmd[2] = 0x07; + cmd[3] = 0x00; + cmd[4] = p->addr.b[0]; + cmd[5] = p->addr.b[1]; + cmd[6] = p->addr.b[2]; + cmd[7] = p->addr.b[3]; + cmd[8] = p->addr.b[4]; + cmd[9] = p->addr.b[5]; + + result = __rtk_send_hci_cmd(udev, cmd, 10); + kfree(cmd); + } + } + hci_dev_unlock(hdev); + + return result; +} +#endif + +int rtkbt_pm_notify(struct notifier_block *notifier, + ulong pm_event, void *unused) +{ + struct btusb_data *data; + struct usb_device *udev; + struct usb_interface *intf; + struct hci_dev *hdev; + /* int err; */ +#if defined RTKBT_SWITCH_PATCH || defined RTKBT_TV_POWERON_WHITELIST + int result = 0; +#endif +#ifdef RTKBT_SWITCH_PATCH + u8 *cmd; + static u8 hci_state = 0; + struct api_context ctx; +#endif + + data = container_of(notifier, struct btusb_data, pm_notifier); + udev = data->udev; + intf = data->intf; + hdev = data->hdev; + + RTKBT_DBG("%s: pm_event %ld", __func__, pm_event); + switch (pm_event) { + case PM_SUSPEND_PREPARE: + case PM_HIBERNATION_PREPARE: + /* No need to load firmware because the download firmware + * process is deprecated in resume. + * We use rebind after resume instead */ + /* err = usb_autopm_get_interface(data->intf); + * if (err < 0) + * return err; + * patch_entry->fw_len = + * load_firmware(dev_entry, &patch_entry->fw_cache); + * usb_autopm_put_interface(data->intf); + * if (patch_entry->fw_len <= 0) { + * RTKBT_DBG("rtkbt_pm_notify return NOTIFY_BAD"); + * return NOTIFY_BAD; + * } */ + + RTKBT_DBG("%s: suspend prepare", __func__); + + if (!device_may_wakeup(&udev->dev)) { +#ifdef CONFIG_NEEDS_BINDING + intf->needs_binding = 1; + RTKBT_DBG("Remote wakeup not support, set " + "intf->needs_binding = 1"); +#else + RTKBT_DBG("Remote wakeup not support, no needs binding"); +#endif + } + +#ifdef RTKBT_SWITCH_PATCH + if (test_bit(HCI_UP, &hdev->flags)) { + unsigned long expire; + + init_completion(&ctx.done); + hci_state = 1; + + down(&switch_sem); + data->context = &ctx; + ctx.flags = RTLBT_CLOSE; + queue_work(hdev->req_workqueue, &hdev->power_off.work); + up(&switch_sem); + + expire = msecs_to_jiffies(1000); + if (!wait_for_completion_timeout(&ctx.done, expire)) + RTKBT_ERR("hdev close timeout"); + + down(&switch_sem); + data->context = NULL; + up(&switch_sem); + } + + cmd = kzalloc(16, GFP_ATOMIC); + if (!cmd) { + RTKBT_ERR("Can't allocate memory for cmd"); + return -ENOMEM; + } + + /* Clear patch */ + cmd[0] = 0x66; + cmd[1] = 0xfc; + cmd[2] = 0x00; + + result = __rtk_send_hci_cmd(udev, cmd, 3); + kfree(cmd); + msleep(100); /* From FW colleague's recommendation */ + result = download_lps_patch(intf); + + /* Tell the controller to wake up host if received special + * advertising packet + */ + set_scan(intf); + + /* Send special vendor commands */ +#endif + +#ifdef RTKBT_TV_POWERON_WHITELIST + result = rtkbt_lookup_le_device_poweron_whitelist(hdev, udev); + if (result < 0) { + RTKBT_ERR("rtkbt_lookup_le_device_poweron_whitelist error: %d", result); + } +#endif + break; + + case PM_POST_SUSPEND: + case PM_POST_HIBERNATION: + case PM_POST_RESTORE: + /* if (patch_entry->fw_len > 0) { + * kfree(patch_entry->fw_cache); + * patch_entry->fw_cache = NULL; + * patch_entry->fw_len = 0; + * } */ + +#ifdef RTKBT_SWITCH_PATCH + cmd = kzalloc(16, GFP_ATOMIC); + if (!cmd) { + RTKBT_ERR("Can't allocate memory for cmd"); + return -ENOMEM; + } + + /* Clear patch */ + cmd[0] = 0x66; + cmd[1] = 0xfc; + cmd[2] = 0x00; + + result = __rtk_send_hci_cmd(udev, cmd, 3); + kfree(cmd); + msleep(100); /* From FW colleague's recommendation */ + result = download_patch(intf); + if (hci_state) { + hci_state = 0; + queue_work(hdev->req_workqueue, &hdev->power_on); + } +#endif + +#ifdef BTUSB_RPM + RTKBT_DBG("%s: Re-enable autosuspend", __func__); + /* pm_runtime_use_autosuspend(&udev->dev); + * pm_runtime_set_autosuspend_delay(&udev->dev, 2000); + * pm_runtime_set_active(&udev->dev); + * pm_runtime_allow(&udev->dev); + * pm_runtime_mark_last_busy(&udev->dev); + * pm_runtime_autosuspend(&udev->dev); + * pm_runtime_put_autosuspend(&udev->dev); + * usb_disable_autosuspend(udev); */ + /* FIXME: usb_enable_autosuspend(udev) is useless here. + * Because it is always enabled after enabled in btusb_probe() + */ + usb_enable_autosuspend(udev); + pm_runtime_mark_last_busy(&udev->dev); +#endif + break; + + default: + break; + } + + return NOTIFY_DONE; +} + + +static int btusb_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + struct usb_endpoint_descriptor *ep_desc; + struct btusb_data *data; + struct hci_dev *hdev; + int i, err, flag1, flag2; + struct usb_device *udev; + udev = interface_to_usbdev(intf); + + RTKBT_DBG("btusb_probe intf->cur_altsetting->desc.bInterfaceNumber %d", + intf->cur_altsetting->desc.bInterfaceNumber); + + /* interface numbers are hardcoded in the spec */ + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return -ENODEV; + + /*******************************/ + flag1 = device_can_wakeup(&udev->dev); + flag2 = device_may_wakeup(&udev->dev); + RTKBT_DBG("btusb_probe can_wakeup %x, may wakeup %x", flag1, flag2); +#ifdef BTUSB_WAKEUP_HOST + device_wakeup_enable(&udev->dev); +#endif + //device_wakeup_enable(&udev->dev); + /*device_wakeup_disable(&udev->dev); + flag1=device_can_wakeup(&udev->dev); + flag2=device_may_wakeup(&udev->dev); + RTKBT_DBG("btusb_probe can_wakeup=%x flag2=%x",flag1,flag2); + */ + err = patch_add(intf); + if (err < 0) + return -1; + /*******************************/ + + data = rtk_alloc(intf); + if (!data) + return -ENOMEM; + + for (i = 0; i < intf->cur_altsetting->desc.bNumEndpoints; i++) { + ep_desc = &intf->cur_altsetting->endpoint[i].desc; + + if (!data->intr_ep && usb_endpoint_is_int_in(ep_desc)) { + data->intr_ep = ep_desc; + continue; + } + + if (!data->bulk_tx_ep && usb_endpoint_is_bulk_out(ep_desc)) { + data->bulk_tx_ep = ep_desc; + continue; + } + + if (!data->bulk_rx_ep && usb_endpoint_is_bulk_in(ep_desc)) { + data->bulk_rx_ep = ep_desc; + continue; + } + } + + if (!data->intr_ep || !data->bulk_tx_ep || !data->bulk_rx_ep) { + rtk_free(data); + return -ENODEV; + } + + data->cmdreq_type = USB_TYPE_CLASS; + + data->udev = interface_to_usbdev(intf); + data->intf = intf; + + spin_lock_init(&data->lock); + + INIT_WORK(&data->work, btusb_work); + INIT_WORK(&data->waker, btusb_waker); + spin_lock_init(&data->txlock); + + init_usb_anchor(&data->tx_anchor); + init_usb_anchor(&data->intr_anchor); + init_usb_anchor(&data->bulk_anchor); + init_usb_anchor(&data->isoc_anchor); + init_usb_anchor(&data->deferred); + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + spin_lock_init(&data->rxlock); + data->recv_bulk = btusb_recv_bulk; +#endif + + hdev = hci_alloc_dev(); + if (!hdev) { + rtk_free(data); + return -ENOMEM; + } + + HDEV_BUS = HCI_USB; + + data->hdev = hdev; + + SET_HCIDEV_DEV(hdev, &intf->dev); + + hdev->open = btusb_open; + hdev->close = btusb_close; + hdev->flush = btusb_flush; + hdev->send = btusb_send_frame; + hdev->notify = btusb_notify; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 4, 0) + hci_set_drvdata(hdev, data); +#else + hdev->driver_data = data; + hdev->destruct = btusb_destruct; + hdev->owner = THIS_MODULE; +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 7, 1) + if (!reset) + set_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks); + RTKBT_DBG("set_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks);"); +#endif + + /* Interface numbers are hardcoded in the specification */ + data->isoc = usb_ifnum_to_if(data->udev, 1); + + if (data->isoc) { + err = usb_driver_claim_interface(&btusb_driver, + data->isoc, data); + if (err < 0) { + hci_free_dev(hdev); + rtk_free(data); + return err; + } + } + +#if HCI_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) + set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks); +#endif + + err = hci_register_dev(hdev); + if (err < 0) { + hci_free_dev(hdev); + rtk_free(data); + return err; + } + + usb_set_intfdata(intf, data); + + /* Register PM notifier */ + data->pm_notifier.notifier_call = rtkbt_pm_notify; + register_pm_notifier(&data->pm_notifier); + +#ifdef BTCOEX + rtk_btcoex_probe(hdev); +#endif + + RTKBT_DBG("%s: done", __func__); + + return 0; +} + +static void btusb_disconnect(struct usb_interface *intf) +{ + struct btusb_data *data = usb_get_intfdata(intf); + struct hci_dev *hdev; + struct usb_device *udev; + udev = interface_to_usbdev(intf); + + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return; + + if (!data) + return; + + RTKBT_DBG("btusb_disconnect"); + + /* Un-register PM notifier */ + unregister_pm_notifier(&data->pm_notifier); + + /*******************************/ + patch_remove(intf); + /*******************************/ + + hdev = data->hdev; + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 4, 0) + __hci_dev_hold(hdev); +#endif + + usb_set_intfdata(data->intf, NULL); + + if (data->isoc) + usb_set_intfdata(data->isoc, NULL); + + hci_unregister_dev(hdev); + + if (intf == data->isoc) + usb_driver_release_interface(&btusb_driver, data->intf); + else if (data->isoc) + usb_driver_release_interface(&btusb_driver, data->isoc); + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 4, 0) + __hci_dev_put(hdev); +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + btusb_free_frags(data); +#endif + + hci_free_dev(hdev); + rtk_free(data); +} + +#ifdef CONFIG_PM +static int btusb_suspend(struct usb_interface *intf, pm_message_t message) +{ + struct btusb_data *data = usb_get_intfdata(intf); + + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return 0; + + /*******************************/ + RTKBT_DBG("btusb_suspend message.event 0x%x, data->suspend_count %d", + message.event, data->suspend_count); + if (!test_bit(HCI_RUNNING, &data->hdev->flags)) { + RTKBT_INFO("%s: hdev is not HCI_RUNNING", __func__); + /* set_scan(data->intf); */ + } + /*******************************/ + + if (data->suspend_count++) + return 0; + + spin_lock_irq(&data->txlock); + if (!((message.event & PM_EVENT_AUTO) && data->tx_in_flight)) { + set_bit(BTUSB_SUSPENDING, &data->flags); + spin_unlock_irq(&data->txlock); + RTKBT_INFO("%s: suspending...", __func__); + } else { + spin_unlock_irq(&data->txlock); + data->suspend_count--; + return -EBUSY; + } + + cancel_work_sync(&data->work); + + btusb_stop_traffic(data); + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_kill_anchored_urbs(&data->tx_anchor); + + return 0; +} + +static void play_deferred(struct btusb_data *data) +{ + struct urb *urb; + int err; + + while ((urb = usb_get_from_anchor(&data->deferred))) { + /************************************/ + usb_anchor_urb(urb, &data->tx_anchor); + err = usb_submit_urb(urb, GFP_ATOMIC); + if (err < 0) { + RTKBT_ERR("play_deferred urb %p submission failed", + urb); + kfree(urb->setup_packet); + usb_unanchor_urb(urb); + } else { + usb_mark_last_busy(data->udev); + } + usb_free_urb(urb); + /************************************/ + data->tx_in_flight++; + } + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_scuttle_anchored_urbs(&data->deferred); +} + +static int btusb_resume(struct usb_interface *intf) +{ + struct btusb_data *data = usb_get_intfdata(intf); + struct hci_dev *hdev = data->hdev; + int err = 0; + + if (intf->cur_altsetting->desc.bInterfaceNumber != 0) + return 0; + + /*******************************/ + RTKBT_DBG("%s: data->suspend_count %d", __func__, data->suspend_count); + + /* if intf->needs_binding is set, driver will be rebind. + * The probe will be called instead of resume */ + /* if (!test_bit(HCI_RUNNING, &hdev->flags)) { + * RTKBT_DBG("btusb_resume-----bt is off,download patch"); + * download_patch(intf); + * } else + * RTKBT_DBG("btusb_resume,----bt is on"); + */ + /*******************************/ + if (--data->suspend_count) + return 0; + + if (test_bit(BTUSB_INTR_RUNNING, &data->flags)) { + err = btusb_submit_intr_urb(hdev, GFP_NOIO); + if (err < 0) { + clear_bit(BTUSB_INTR_RUNNING, &data->flags); + goto failed; + } + } + + if (test_bit(BTUSB_BULK_RUNNING, &data->flags)) { + err = btusb_submit_bulk_urb(hdev, GFP_NOIO); + if (err < 0) { + clear_bit(BTUSB_BULK_RUNNING, &data->flags); + goto failed; + } + + btusb_submit_bulk_urb(hdev, GFP_NOIO); + } + + if (test_bit(BTUSB_ISOC_RUNNING, &data->flags)) { + if (btusb_submit_isoc_urb(hdev, GFP_NOIO) < 0) + clear_bit(BTUSB_ISOC_RUNNING, &data->flags); + else + btusb_submit_isoc_urb(hdev, GFP_NOIO); + } + + spin_lock_irq(&data->txlock); + play_deferred(data); + clear_bit(BTUSB_SUSPENDING, &data->flags); + spin_unlock_irq(&data->txlock); + schedule_work(&data->work); + + RTKBT_DBG("%s: data->suspend_count %d, done", __func__, + data->suspend_count); + + return 0; + +failed: + mdelay(URB_CANCELING_DELAY_MS); // Added by Realtek + usb_scuttle_anchored_urbs(&data->deferred); +//done: + spin_lock_irq(&data->txlock); + clear_bit(BTUSB_SUSPENDING, &data->flags); + spin_unlock_irq(&data->txlock); + RTKBT_DBG("%s: data->suspend_count %d, fail", __func__, + data->suspend_count); + + return err; +} +#endif + +static struct usb_driver btusb_driver = { + .name = "rtk_btusb", + .probe = btusb_probe, + .disconnect = btusb_disconnect, +#ifdef CONFIG_PM + .suspend = btusb_suspend, + .resume = btusb_resume, +#ifdef RTKBT_SWITCH_PATCH + .reset_resume = btusb_resume, +#endif +#endif + .id_table = btusb_table, + .supports_autosuspend = 1, +#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 7, 1) + .disable_hub_initiated_lpm = 1, +#endif +}; + +static int __init btusb_init(void) +{ + RTKBT_DBG("Realtek Bluetooth USB driver ver %s", VERSION); +#ifdef BTCOEX + rtk_btcoex_init(); +#endif + return usb_register(&btusb_driver); +} + +static void __exit btusb_exit(void) +{ + RTKBT_DBG("rtk_btusb: btusb_exit"); + usb_deregister(&btusb_driver); + +#ifdef BTCOEX + rtk_btcoex_exit(); +#endif +} + +module_init(btusb_init); +module_exit(btusb_exit); + +MODULE_AUTHOR(""); +MODULE_DESCRIPTION("Realtek Bluetooth USB driver ver " VERSION); +MODULE_VERSION(VERSION); +MODULE_LICENSE("GPL"); diff --git a/drivers/bluetooth/rtk_bt.h b/drivers/bluetooth/rtk_bt.h new file mode 100644 index 0000000000000..9d23b7fa2c312 --- /dev/null +++ b/drivers/bluetooth/rtk_bt.h @@ -0,0 +1,148 @@ +/* + * + * Realtek Bluetooth USB driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* #define HCI_VERSION_CODE KERNEL_VERSION(3, 14, 41) */ +#define HCI_VERSION_CODE LINUX_VERSION_CODE + +#ifdef CONFIG_BTCOEX +#define BTCOEX +#endif + +/*********************************** +** Realtek - For rtk_btusb driver ** +***********************************/ +#ifdef CONFIG_BTUSB_WAKEUP_HOST +#define BTUSB_WAKEUP_HOST +#endif + +#define URB_CANCELING_DELAY_MS 10 // Added by Realtek +#if HCI_VERSION_CODE > KERNEL_VERSION(2, 6, 33) +#define HDEV_BUS hdev->bus +#else +#define HDEV_BUS hdev->type +#endif + +#if HCI_VERSION_CODE < KERNEL_VERSION(2, 6, 36) +#define NUM_REASSEMBLY 3 +#endif + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 4, 0) +#define GET_DRV_DATA(x) hci_get_drvdata(x) +#else +#define GET_DRV_DATA(x) x->driver_data +#endif + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 13, 0) +#define SCO_NUM hdev->conn_hash.sco_num +#else +#define SCO_NUM hci_conn_num(hdev, SCO_LINK) +#endif + +int patch_add(struct usb_interface *intf); +void patch_remove(struct usb_interface *intf); +int download_patch(struct usb_interface *intf); +int set_btoff(struct usb_interface *intf); +void print_event(struct sk_buff *skb); +void print_command(struct sk_buff *skb); +void print_acl(struct sk_buff *skb, int dataOut); + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) +int btusb_send_frame(struct hci_dev *hdev, struct sk_buff *skb); +#else +int btusb_send_frame(struct sk_buff *skb); +#endif + +#define BTUSB_MAX_ISOC_FRAMES 10 +#define BTUSB_INTR_RUNNING 0 +#define BTUSB_BULK_RUNNING 1 +#define BTUSB_ISOC_RUNNING 2 +#define BTUSB_SUSPENDING 3 +#define BTUSB_DID_ISO_RESUME 4 + +struct btusb_data { + struct hci_dev *hdev; + struct usb_device *udev; + struct usb_interface *intf; + struct usb_interface *isoc; + + spinlock_t lock; + + unsigned long flags; + + struct work_struct work; + struct work_struct waker; + + struct usb_anchor tx_anchor; + struct usb_anchor intr_anchor; + struct usb_anchor bulk_anchor; + struct usb_anchor isoc_anchor; + struct usb_anchor deferred; + int tx_in_flight; + spinlock_t txlock; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + spinlock_t rxlock; + struct sk_buff *evt_skb; + struct sk_buff *acl_skb; + struct sk_buff *sco_skb; +#endif + + struct usb_endpoint_descriptor *intr_ep; + struct usb_endpoint_descriptor *bulk_tx_ep; + struct usb_endpoint_descriptor *bulk_rx_ep; + struct usb_endpoint_descriptor *isoc_tx_ep; + struct usb_endpoint_descriptor *isoc_rx_ep; + + __u8 cmdreq_type; + + unsigned int sco_num; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) + unsigned int air_mode; +#endif + int isoc_altsetting; + int suspend_count; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) + int (*recv_bulk) (struct btusb_data * data, void *buffer, int count); +#endif + struct notifier_block pm_notifier; + void *context; +}; diff --git a/drivers/bluetooth/rtk_coex.c b/drivers/bluetooth/rtk_coex.c new file mode 100644 index 0000000000000..6f05723b39887 --- /dev/null +++ b/drivers/bluetooth/rtk_coex.c @@ -0,0 +1,3069 @@ +/* +* +* Realtek Bluetooth USB driver +* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +* +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtk_coex.h" + +/* Software coex message can be sent to and receive from WiFi driver by + * UDP socket or exported symbol */ +/* #define RTK_COEX_OVER_SYMBOL */ + +#if BTRTL_HCI_IF == BTRTL_HCIUSB +#include +#include "rtk_bt.h" +#undef RTKBT_DBG +#undef RTKBT_INFO +#undef RTKBT_WARN +#undef RTKBT_ERR + +#elif BTRTL_HCI_IF == BTRTL_HCIUART +/* #define HCI_VERSION_CODE KERNEL_VERSION(3, 14, 41) */ +#define HCI_VERSION_CODE LINUX_VERSION_CODE + +#else +#error "Please set type of HCI interface" +#endif + +#define RTK_VERSION "1.2" + +#define RTKBT_DBG(fmt, arg...) printk(KERN_INFO "rtk_btcoex: " fmt "\n" , ## arg) +#define RTKBT_INFO(fmt, arg...) printk(KERN_INFO "rtk_btcoex: " fmt "\n" , ## arg) +#define RTKBT_WARN(fmt, arg...) printk(KERN_WARNING "rtk_btcoex: " fmt "\n", ## arg) +#define RTKBT_ERR(fmt, arg...) printk(KERN_WARNING "rtk_btcoex: " fmt "\n", ## arg) + +static struct rtl_coex_struct btrtl_coex; + +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL +static struct sk_buff_head rtw_q; +static struct workqueue_struct *rtw_wq; +static struct work_struct rtw_work; +static u8 rtw_coex_on; +#endif +#endif + +#define is_profile_connected(profile) ((btrtl_coex.profile_bitmap & BIT(profile)) > 0) +#define is_profile_busy(profile) ((btrtl_coex.profile_status & BIT(profile)) > 0) + +#ifdef RTB_SOFTWARE_MAILBOX +static void rtk_handle_event_from_wifi(uint8_t * msg); +#endif + +static int rtl_alloc_buff(struct rtl_coex_struct *coex) +{ + struct rtl_hci_ev *ev; + struct rtl_l2_buff *l2; + int i; + int order; + unsigned long addr; + unsigned long addr2; + int ev_size; + int l2_size; + int n; + + spin_lock_init(&coex->buff_lock); + + INIT_LIST_HEAD(&coex->ev_used_list); + INIT_LIST_HEAD(&coex->ev_free_list); + + INIT_LIST_HEAD(&coex->l2_used_list); + INIT_LIST_HEAD(&coex->l2_free_list); + + n = NUM_RTL_HCI_EV * sizeof(struct rtl_hci_ev); + ev_size = ALIGN(n, sizeof(unsigned long)); + + n = L2_MAX_PKTS * sizeof(struct rtl_l2_buff); + l2_size = ALIGN(n, sizeof(unsigned long)); + + RTKBT_DBG("alloc buffers %d, %d for ev and l2", ev_size, l2_size); + + order = get_order(ev_size + l2_size); + addr = __get_free_pages(GFP_KERNEL, order); + if (!addr) { + RTKBT_ERR("failed to alloc buffers for ev and l2."); + return -ENOMEM; + } + memset((void *)addr, 0, ev_size + l2_size); + + coex->pages_addr = addr; + coex->buff_size = ev_size + l2_size; + + ev = (struct rtl_hci_ev *)addr; + for (i = 0; i < NUM_RTL_HCI_EV; i++) { + list_add_tail(&ev->list, &coex->ev_free_list); + ev++; + } + + addr2 = addr + ev_size; + l2 = (struct rtl_l2_buff *)addr2; + for (i = 0; i < L2_MAX_PKTS; i++) { + list_add_tail(&l2->list, &coex->l2_free_list); + l2++; + } + + return 0; +} + +static void rtl_free_buff(struct rtl_coex_struct *coex) +{ + struct rtl_hci_ev *ev; + struct rtl_l2_buff *l2; + unsigned long flags; + + spin_lock_irqsave(&coex->buff_lock, flags); + + while (!list_empty(&coex->ev_used_list)) { + ev = list_entry(coex->ev_used_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + } + + while (!list_empty(&coex->ev_free_list)) { + ev = list_entry(coex->ev_free_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + } + + while (!list_empty(&coex->l2_used_list)) { + l2 = list_entry(coex->l2_used_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + } + + while (!list_empty(&coex->l2_free_list)) { + l2 = list_entry(coex->l2_free_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + } + + spin_unlock_irqrestore(&coex->buff_lock, flags); + + if (coex->buff_size > 0) { + free_pages(coex->pages_addr, get_order(coex->buff_size)); + coex->pages_addr = 0; + coex->buff_size = 0; + } +} + +static struct rtl_hci_ev *rtl_ev_node_get(struct rtl_coex_struct *coex) +{ + struct rtl_hci_ev *ev; + unsigned long flags; + + if (!coex->buff_size) + return NULL; + + spin_lock_irqsave(&coex->buff_lock, flags); + if (!list_empty(&coex->ev_free_list)) { + ev = list_entry(coex->ev_free_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + } else + ev = NULL; + spin_unlock_irqrestore(&coex->buff_lock, flags); + return ev; +} + +static int rtl_ev_node_to_used(struct rtl_coex_struct *coex, + struct rtl_hci_ev *ev) +{ + unsigned long flags; + + spin_lock_irqsave(&coex->buff_lock, flags); + list_add_tail(&ev->list, &coex->ev_used_list); + spin_unlock_irqrestore(&coex->buff_lock, flags); + + return 0; +} + +static struct rtl_l2_buff *rtl_l2_node_get(struct rtl_coex_struct *coex) +{ + struct rtl_l2_buff *l2; + unsigned long flags; + + if (!coex->buff_size) + return NULL; + + spin_lock_irqsave(&coex->buff_lock, flags); + + if(!list_empty(&coex->l2_free_list)) { + l2 = list_entry(coex->l2_free_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + } else + l2 = NULL; + + spin_unlock_irqrestore(&coex->buff_lock, flags); + return l2; +} + +static int rtl_l2_node_to_used(struct rtl_coex_struct *coex, + struct rtl_l2_buff *l2) +{ + unsigned long flags; + + spin_lock_irqsave(&coex->buff_lock, flags); + list_add_tail(&l2->list, &coex->l2_used_list); + spin_unlock_irqrestore(&coex->buff_lock, flags); + + return 0; +} + +static int8_t psm_to_profile_index(uint16_t psm) +{ + switch (psm) { + case PSM_AVCTP: + case PSM_SDP: + return -1; //ignore + + case PSM_HID: + case PSM_HID_INT: + return profile_hid; + + case PSM_AVDTP: + return profile_a2dp; + + case PSM_PAN: + case PSM_OPP: + case PSM_FTP: + case PSM_BIP: + case PSM_RFCOMM: + return profile_pan; + + default: + return profile_pan; + } +} + +static rtk_prof_info *find_by_psm(u16 psm) +{ + struct list_head *head = &btrtl_coex.profile_list; + struct list_head *iter = NULL; + struct list_head *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (desc->psm == psm) + return desc; + } + + return NULL; +} + +static void rtk_check_setup_timer(int8_t profile_index) +{ + if (profile_index == profile_a2dp) { + btrtl_coex.a2dp_packet_count = 0; + btrtl_coex.a2dp_count_timer.expires = + jiffies + msecs_to_jiffies(1000); + mod_timer(&btrtl_coex.a2dp_count_timer, + btrtl_coex.a2dp_count_timer.expires); + } + + if (profile_index == profile_pan) { + btrtl_coex.pan_packet_count = 0; + btrtl_coex.pan_count_timer.expires = + jiffies + msecs_to_jiffies(1000); + mod_timer(&btrtl_coex.pan_count_timer, + btrtl_coex.pan_count_timer.expires); + } + + /* hogp & voice share one timer now */ + if ((profile_index == profile_hogp) || (profile_index == profile_voice)) { + if ((0 == btrtl_coex.profile_refcount[profile_hogp]) + && (0 == btrtl_coex.profile_refcount[profile_voice])) { + btrtl_coex.hogp_packet_count = 0; + btrtl_coex.voice_packet_count = 0; + btrtl_coex.hogp_count_timer.expires = + jiffies + msecs_to_jiffies(1000); + mod_timer(&btrtl_coex.hogp_count_timer, + btrtl_coex.hogp_count_timer.expires); + } + } +} + +static void rtk_check_del_timer(int8_t profile_index) +{ + if (profile_a2dp == profile_index) { + btrtl_coex.a2dp_packet_count = 0; + del_timer_sync(&btrtl_coex.a2dp_count_timer); + } + if (profile_pan == profile_index) { + btrtl_coex.pan_packet_count = 0; + del_timer_sync(&btrtl_coex.pan_count_timer); + } + if (profile_hogp == profile_index) { + btrtl_coex.hogp_packet_count = 0; + if (btrtl_coex.profile_refcount[profile_voice] == 0) { + del_timer_sync(&btrtl_coex.hogp_count_timer); + } + } + if (profile_voice == profile_index) { + btrtl_coex.voice_packet_count = 0; + if (btrtl_coex.profile_refcount[profile_hogp] == 0) { + del_timer_sync(&btrtl_coex.hogp_count_timer); + } + } +} + + + +static rtk_conn_prof *find_connection_by_handle(struct rtl_coex_struct * coex, + uint16_t handle) +{ + struct list_head *head = &coex->conn_hash; + struct list_head *iter = NULL, *temp = NULL; + rtk_conn_prof *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_conn_prof, list); + if ((handle & 0xEFF) == desc->handle) { + return desc; + } + } + return NULL; +} + +static rtk_conn_prof *allocate_connection_by_handle(uint16_t handle) +{ + rtk_conn_prof *phci_conn = NULL; + phci_conn = kmalloc(sizeof(rtk_conn_prof), GFP_ATOMIC); + if (phci_conn) + phci_conn->handle = handle; + + return phci_conn; +} + +static void init_connection_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->conn_hash; + INIT_LIST_HEAD(head); +} + +static void add_connection_to_hash(struct rtl_coex_struct * coex, + rtk_conn_prof * desc) +{ + struct list_head *head = &coex->conn_hash; + list_add_tail(&desc->list, head); +} + +static void delete_connection_from_hash(rtk_conn_prof * desc) +{ + if (desc) { + list_del(&desc->list); + kfree(desc); + } +} + +static void flush_connection_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->conn_hash; + struct list_head *iter = NULL, *temp = NULL; + rtk_conn_prof *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_conn_prof, list); + if (desc) { + list_del(&desc->list); + kfree(desc); + } + } + //INIT_LIST_HEAD(head); +} + +static void init_profile_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->profile_list; + INIT_LIST_HEAD(head); +} + +static uint8_t list_allocate_add(uint16_t handle, uint16_t psm, + int8_t profile_index, uint16_t dcid, + uint16_t scid) +{ + rtk_prof_info *pprof_info = NULL; + + if (profile_index < 0) { + RTKBT_ERR("PSM 0x%x do not need parse", psm); + return FALSE; + } + + pprof_info = kmalloc(sizeof(rtk_prof_info), GFP_ATOMIC); + + if (NULL == pprof_info) { + RTKBT_ERR("list_allocate_add: allocate error"); + return FALSE; + } + + /* Check if it is the second l2cap connection for a2dp + * a2dp signal channel will be created first than media channel. + */ + if (psm == PSM_AVDTP) { + rtk_prof_info *pinfo = find_by_psm(psm); + if (!pinfo) { + pprof_info->flags = A2DP_SIGNAL; + RTKBT_INFO("%s: Add a2dp signal channel", __func__); + } else { + pprof_info->flags = A2DP_MEDIA; + RTKBT_INFO("%s: Add a2dp media channel", __func__); + } + } + + pprof_info->handle = handle; + pprof_info->psm = psm; + pprof_info->scid = scid; + pprof_info->dcid = dcid; + pprof_info->profile_index = profile_index; + list_add_tail(&(pprof_info->list), &(btrtl_coex.profile_list)); + + return TRUE; +} + +static void delete_profile_from_hash(rtk_prof_info * desc) +{ + if (desc) { + RTKBT_DBG("Delete profile: hndl 0x%04x, psm 0x%04x, dcid 0x%04x, " + "scid 0x%04x", desc->handle, desc->psm, desc->dcid, + desc->scid); + + list_del(&desc->list); + kfree(desc); + desc = NULL; + } +} + +static void flush_profile_hash(struct rtl_coex_struct * coex) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + spin_lock(&btrtl_coex.spin_lock_profile); + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + delete_profile_from_hash(desc); + } + //INIT_LIST_HEAD(head); + spin_unlock(&btrtl_coex.spin_lock_profile); +} + +static rtk_prof_info *find_profile_by_handle_scid(struct rtl_coex_struct * + coex, uint16_t handle, + uint16_t scid) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (((handle & 0xFFF) == desc->handle) && (scid == desc->scid)) { + return desc; + } + } + return NULL; +} + +static rtk_prof_info *find_profile_by_handle_dcid(struct rtl_coex_struct * + coex, uint16_t handle, + uint16_t dcid) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (((handle & 0xFFF) == desc->handle) && (dcid == desc->dcid)) { + return desc; + } + } + return NULL; +} + +static rtk_prof_info *find_profile_by_handle_dcid_scid(struct rtl_coex_struct + * coex, uint16_t handle, + uint16_t dcid, + uint16_t scid) +{ + struct list_head *head = &coex->profile_list; + struct list_head *iter = NULL, *temp = NULL; + rtk_prof_info *desc = NULL; + + list_for_each_safe(iter, temp, head) { + desc = list_entry(iter, rtk_prof_info, list); + if (((handle & 0xFFF) == desc->handle) && (dcid == desc->dcid) + && (scid == desc->scid)) { + return desc; + } + } + return NULL; +} + +static void rtk_vendor_cmd_to_fw(uint16_t opcode, uint8_t parameter_len, + uint8_t * parameter) +{ + int len = HCI_CMD_PREAMBLE_SIZE + parameter_len; + uint8_t *p; + struct sk_buff *skb; + struct hci_dev *hdev = btrtl_coex.hdev; + + if (!hdev) { + RTKBT_ERR("No HCI device"); + return; + } else if (!test_bit(HCI_UP, &hdev->flags)) { + RTKBT_WARN("HCI device is down"); + return; + } + + skb = bt_skb_alloc(len, GFP_ATOMIC); + if (!skb) { + RTKBT_DBG("there is no room for cmd 0x%x", opcode); + return; + } + + p = (uint8_t *) skb_put(skb, HCI_CMD_PREAMBLE_SIZE); + UINT16_TO_STREAM(p, opcode); + *p++ = parameter_len; + + if (parameter_len) + memcpy(skb_put(skb, parameter_len), parameter, parameter_len); + + bt_cb(skb)->pkt_type = HCI_COMMAND_PKT; + +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 4, 0) + bt_cb(skb)->opcode = opcode; +#else + bt_cb(skb)->hci.opcode = opcode; +#endif +#endif + + /* Stand-alone HCI commands must be flagged as + * single-command requests. + */ +#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 10, 0) +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 4, 0) + bt_cb(skb)->req.start = true; +#else + +#if HCI_VERSION_CODE < KERNEL_VERSION(4, 5, 0) + bt_cb(skb)->hci.req_start = true; +#else + + bt_cb(skb)->hci.req_flags |= HCI_REQ_START; +#endif + +#endif /* 4.4.0 */ +#endif /* 3.10.0 */ + RTKBT_DBG("%s: opcode 0x%x", __func__, opcode); + + /* It is harmless if set skb->dev twice. The dev will be used in + * btusb_send_frame() after or equal to kernel/hci 3.13.0, + * the hdev will not come from skb->dev. */ +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 13, 0) + skb->dev = (void *)btrtl_coex.hdev; +#endif + /* Put the skb to the global hdev->cmd_q */ + skb_queue_tail(&hdev->cmd_q, skb); + +#if HCI_VERSION_CODE < KERNEL_VERSION(3, 3, 0) + tasklet_schedule(&hdev->cmd_task); +#else + queue_work(hdev->workqueue, &hdev->cmd_work); +#endif + + return; +} + +static void rtk_notify_profileinfo_to_fw(void) +{ + struct list_head *head = NULL; + struct list_head *iter = NULL; + struct list_head *temp = NULL; + rtk_conn_prof *hci_conn = NULL; + uint8_t handle_number = 0; + uint32_t buffer_size = 0; + uint8_t *p_buf = NULL; + uint8_t *p = NULL; + + head = &btrtl_coex.conn_hash; + list_for_each_safe(iter, temp, head) { + hci_conn = list_entry(iter, rtk_conn_prof, list); + if (hci_conn && hci_conn->profile_bitmap) + handle_number++; + } + + buffer_size = 1 + handle_number * 3 + 1; + + p_buf = kmalloc(buffer_size, GFP_ATOMIC); + + if (NULL == p_buf) { + RTKBT_ERR("%s: alloc error", __func__); + return; + } + p = p_buf; + + RTKBT_DBG("%s: BufferSize %u", __func__, buffer_size); + *p++ = handle_number; + RTKBT_DBG("%s: NumberOfHandles %u", __func__, handle_number); + head = &btrtl_coex.conn_hash; + list_for_each(iter, head) { + hci_conn = list_entry(iter, rtk_conn_prof, list); + if (hci_conn && hci_conn->profile_bitmap) { + UINT16_TO_STREAM(p, hci_conn->handle); + RTKBT_DBG("%s: handle 0x%04x", __func__, + hci_conn->handle); + *p++ = hci_conn->profile_bitmap; + RTKBT_DBG("%s: profile_bitmap 0x%02x", __func__, + hci_conn->profile_bitmap); + handle_number--; + } + if (0 == handle_number) + break; + } + + *p++ = btrtl_coex.profile_status; + RTKBT_DBG("%s: profile_status 0x%02x", __func__, + btrtl_coex.profile_status); + + rtk_vendor_cmd_to_fw(HCI_VENDOR_SET_PROFILE_REPORT_COMMAND, buffer_size, + p_buf); + + kfree(p_buf); + return; +} + +static void update_profile_state(uint8_t profile_index, uint8_t is_busy) +{ + uint8_t need_update = FALSE; + + if ((btrtl_coex.profile_bitmap & BIT(profile_index)) == 0) { + RTKBT_ERR("%s: : ERROR!!! profile(Index: %x) does not exist", + __func__, profile_index); + return; + } + + if (is_busy) { + if ((btrtl_coex.profile_status & BIT(profile_index)) == 0) { + need_update = TRUE; + btrtl_coex.profile_status |= BIT(profile_index); + } + } else { + if ((btrtl_coex.profile_status & BIT(profile_index)) > 0) { + need_update = TRUE; + btrtl_coex.profile_status &= ~(BIT(profile_index)); + } + } + + if (need_update) { + RTKBT_DBG("%s: btrtl_coex.profie_bitmap = %x", + __func__, btrtl_coex.profile_bitmap); + RTKBT_DBG("%s: btrtl_coex.profile_status = %x", + __func__, btrtl_coex.profile_status); + rtk_notify_profileinfo_to_fw(); + } +} + +static void update_profile_connection(rtk_conn_prof * phci_conn, + int8_t profile_index, uint8_t is_add) +{ + uint8_t need_update = FALSE; + uint8_t kk; + + RTKBT_DBG("%s: is_add %d, profile_index %x", __func__, + is_add, profile_index); + if (profile_index < 0) + return; + + if (is_add) { + if (btrtl_coex.profile_refcount[profile_index] == 0) { + need_update = TRUE; + btrtl_coex.profile_bitmap |= BIT(profile_index); + + /* SCO is always busy */ + if (profile_index == profile_sco) + btrtl_coex.profile_status |= + BIT(profile_index); + + rtk_check_setup_timer(profile_index); + } + btrtl_coex.profile_refcount[profile_index]++; + + if (0 == phci_conn->profile_refcount[profile_index]) { + need_update = TRUE; + phci_conn->profile_bitmap |= BIT(profile_index); + } + phci_conn->profile_refcount[profile_index]++; + } else { + if (!btrtl_coex.profile_refcount[profile_index]) { + RTKBT_WARN("profile %u refcount is already zero", + profile_index); + return; + } + btrtl_coex.profile_refcount[profile_index]--; + RTKBT_DBG("%s: btrtl_coex.profile_refcount[%x] = %x", + __func__, profile_index, + btrtl_coex.profile_refcount[profile_index]); + if (btrtl_coex.profile_refcount[profile_index] == 0) { + need_update = TRUE; + btrtl_coex.profile_bitmap &= ~(BIT(profile_index)); + + /* if profile does not exist, status is meaningless */ + btrtl_coex.profile_status &= ~(BIT(profile_index)); + rtk_check_del_timer(profile_index); + } + + phci_conn->profile_refcount[profile_index]--; + if (0 == phci_conn->profile_refcount[profile_index]) { + need_update = TRUE; + phci_conn->profile_bitmap &= ~(BIT(profile_index)); + + /* clear profile_hid_interval if need */ + if ((profile_hid == profile_index) + && (phci_conn-> + profile_bitmap & (BIT(profile_hid_interval)))) { + phci_conn->profile_bitmap &= + ~(BIT(profile_hid_interval)); + btrtl_coex. + profile_refcount[profile_hid_interval]--; + } + } + } + + RTKBT_DBG("%s: btrtl_coex.profile_bitmap 0x%02x", __func__, + btrtl_coex.profile_bitmap); + for (kk = 0; kk < 8; kk++) + RTKBT_DBG("%s: btrtl_coex.profile_refcount[%d] = %d", + __func__, kk, + btrtl_coex.profile_refcount[kk]); + + if (need_update) + rtk_notify_profileinfo_to_fw(); +} + +static void update_hid_active_state(uint16_t handle, uint16_t interval) +{ + uint8_t need_update = 0; + rtk_conn_prof *phci_conn = + find_connection_by_handle(&btrtl_coex, handle); + + if (phci_conn == NULL) + return; + + RTKBT_DBG("%s: handle 0x%04x, interval %u", __func__, handle, interval); + if (((phci_conn->profile_bitmap) & (BIT(profile_hid))) == 0) { + RTKBT_DBG("HID not connected, nothing to be down"); + return; + } + + if (interval < 60) { + if ((phci_conn->profile_bitmap & (BIT(profile_hid_interval))) == + 0) { + need_update = 1; + phci_conn->profile_bitmap |= BIT(profile_hid_interval); + + btrtl_coex.profile_refcount[profile_hid_interval]++; + if (btrtl_coex. + profile_refcount[profile_hid_interval] == 1) + btrtl_coex.profile_status |= + BIT(profile_hid); + } + } else { + if ((phci_conn->profile_bitmap & (BIT(profile_hid_interval)))) { + need_update = 1; + phci_conn->profile_bitmap &= + ~(BIT(profile_hid_interval)); + + btrtl_coex.profile_refcount[profile_hid_interval]--; + if (btrtl_coex. + profile_refcount[profile_hid_interval] == 0) + btrtl_coex.profile_status &= + ~(BIT(profile_hid)); + } + } + + if (need_update) + rtk_notify_profileinfo_to_fw(); +} + +static uint8_t handle_l2cap_con_req(uint16_t handle, uint16_t psm, + uint16_t scid, uint8_t direction) +{ + uint8_t status = FALSE; + rtk_prof_info *prof_info = NULL; + int8_t profile_index = psm_to_profile_index(psm); + + if (profile_index < 0) { + RTKBT_DBG("PSM(0x%04x) do not need parse", psm); + return status; + } + + spin_lock(&btrtl_coex.spin_lock_profile); + if (direction) //1: out + prof_info = + find_profile_by_handle_scid(&btrtl_coex, handle, scid); + else // 0:in + prof_info = + find_profile_by_handle_dcid(&btrtl_coex, handle, scid); + + if (prof_info) { + RTKBT_DBG("%s: this profile is already exist!", __func__); + spin_unlock(&btrtl_coex.spin_lock_profile); + return status; + } + + if (direction) //1: out + status = list_allocate_add(handle, psm, profile_index, 0, scid); + else // 0:in + status = list_allocate_add(handle, psm, profile_index, scid, 0); + + spin_unlock(&btrtl_coex.spin_lock_profile); + + if (!status) + RTKBT_ERR("%s: list_allocate_add failed!", __func__); + + return status; +} + +static uint8_t handle_l2cap_con_rsp(uint16_t handle, uint16_t dcid, + uint16_t scid, uint8_t direction, + uint8_t result) +{ + rtk_prof_info *prof_info = NULL; + rtk_conn_prof *phci_conn = NULL; + + spin_lock(&btrtl_coex.spin_lock_profile); + if (!direction) //0, in + prof_info = + find_profile_by_handle_scid(&btrtl_coex, handle, scid); + else //1, out + prof_info = + find_profile_by_handle_dcid(&btrtl_coex, handle, scid); + + if (!prof_info) { + //RTKBT_DBG("handle_l2cap_con_rsp: prof_info Not Find!!"); + spin_unlock(&btrtl_coex.spin_lock_profile); + return FALSE; + } + + if (!result) { //success + RTKBT_DBG("l2cap connection success, update connection"); + if (!direction) //0, in + prof_info->dcid = dcid; + else //1, out + prof_info->scid = dcid; + + phci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (phci_conn) + update_profile_connection(phci_conn, + prof_info->profile_index, + TRUE); + } + + spin_unlock(&btrtl_coex.spin_lock_profile); + return TRUE; +} + +static uint8_t handle_l2cap_discon_req(uint16_t handle, uint16_t dcid, + uint16_t scid, uint8_t direction) +{ + rtk_prof_info *prof_info = NULL; + rtk_conn_prof *phci_conn = NULL; + RTKBT_DBG("%s: handle 0x%04x, dcid 0x%04x, scid 0x%04x, dir %u", + __func__, handle, dcid, scid, direction); + + spin_lock(&btrtl_coex.spin_lock_profile); + if (!direction) //0: in + prof_info = + find_profile_by_handle_dcid_scid(&btrtl_coex, handle, + scid, dcid); + else //1: out + prof_info = + find_profile_by_handle_dcid_scid(&btrtl_coex, handle, + dcid, scid); + + if (!prof_info) { + //LogMsg("handle_l2cap_discon_req: prof_info Not Find!"); + spin_unlock(&btrtl_coex.spin_lock_profile); + return 0; + } + + phci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (!phci_conn) { + spin_unlock(&btrtl_coex.spin_lock_profile); + return 0; + } + + update_profile_connection(phci_conn, prof_info->profile_index, FALSE); + if (prof_info->profile_index == profile_a2dp && + (phci_conn->profile_bitmap & BIT(profile_sink))) + update_profile_connection(phci_conn, profile_sink, FALSE); + + delete_profile_from_hash(prof_info); + spin_unlock(&btrtl_coex.spin_lock_profile); + + return 1; +} + +static const char sample_freqs[4][8] = { + "16", "32", "44.1", "48" +}; + +static const uint8_t sbc_blocks[4] = { 4, 8, 12, 16 }; + +static const char chan_modes[4][16] = { + "MONO", "DUAL_CHANNEL", "STEREO", "JOINT_STEREO" +}; + +static const char alloc_methods[2][12] = { + "LOUDNESS", "SNR" +}; + +static const uint8_t subbands[2] = { 4, 8 }; + +void print_sbc_header(struct sbc_frame_hdr *hdr) +{ + RTKBT_DBG("syncword: %02x", hdr->syncword); + RTKBT_DBG("freq %skHz", sample_freqs[hdr->sampling_frequency]); + RTKBT_DBG("blocks %u", sbc_blocks[hdr->blocks]); + RTKBT_DBG("channel mode %s", chan_modes[hdr->channel_mode]); + RTKBT_DBG("allocation method %s", + alloc_methods[hdr->allocation_method]); + RTKBT_DBG("subbands %u", subbands[hdr->subbands]); +} + +static void packets_count(uint16_t handle, uint16_t scid, uint16_t length, + uint8_t direction, u8 *user_data) +{ + rtk_prof_info *prof_info = NULL; + + rtk_conn_prof *hci_conn = + find_connection_by_handle(&btrtl_coex, handle); + if (NULL == hci_conn) + return; + + if (0 == hci_conn->type) { + if (!direction) //0: in + prof_info = + find_profile_by_handle_scid(&btrtl_coex, handle, + scid); + else //1: out + prof_info = + find_profile_by_handle_dcid(&btrtl_coex, handle, + scid); + + if (!prof_info) { + //RTKBT_DBG("packets_count: prof_info Not Find!"); + return; + } + + /* avdtp media data */ + if (prof_info->profile_index == profile_a2dp && + prof_info->flags == A2DP_MEDIA) { + if (!is_profile_busy(profile_a2dp)) { + struct sbc_frame_hdr *sbc_header; + struct rtp_header *rtph; + u8 bitpool; + + update_profile_state(profile_a2dp, TRUE); + if (!direction) { + if (!(hci_conn->profile_bitmap & BIT(profile_sink))) { + btrtl_coex.profile_bitmap |= BIT(profile_sink); + hci_conn->profile_bitmap |= BIT(profile_sink); + update_profile_connection(hci_conn, profile_sink, 1); + } + update_profile_state(profile_sink, TRUE); + } + + /* We assume it is SBC if the packet length + * is bigger than 100 bytes + */ + if (length > 100) { + RTKBT_INFO("Length %u", length); + rtph = (struct rtp_header *)user_data; + + RTKBT_DBG("rtp: v %u, cc %u, pt %u", + rtph->v, rtph->cc, rtph->pt); + /* move forward */ + user_data += sizeof(struct rtp_header) + + rtph->cc * 4 + 1; + + /* point to the sbc frame header */ + sbc_header = (struct sbc_frame_hdr *)user_data; + bitpool = sbc_header->bitpool; + + print_sbc_header(sbc_header); + + RTKBT_DBG("bitpool %u", bitpool); + + rtk_vendor_cmd_to_fw(HCI_VENDOR_SET_BITPOOL, + 1, &bitpool); + } + } + btrtl_coex.a2dp_packet_count++; + } + + if (prof_info->profile_index == profile_pan) + btrtl_coex.pan_packet_count++; + } +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void count_a2dp_packet_timeout(struct timer_list *unused) +#else +static void count_a2dp_packet_timeout(unsigned long data) +#endif +{ + if (btrtl_coex.a2dp_packet_count) + RTKBT_DBG("%s: a2dp_packet_count %d", __func__, + btrtl_coex.a2dp_packet_count); + if (btrtl_coex.a2dp_packet_count == 0) { + if (is_profile_busy(profile_a2dp)) { + RTKBT_DBG("%s: a2dp busy->idle!", __func__); + update_profile_state(profile_a2dp, FALSE); + if (btrtl_coex.profile_bitmap & BIT(profile_sink)) + update_profile_state(profile_sink, FALSE); + } + } + btrtl_coex.a2dp_packet_count = 0; + mod_timer(&btrtl_coex.a2dp_count_timer, + jiffies + msecs_to_jiffies(1000)); +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void count_pan_packet_timeout(struct timer_list *unused) +#else +static void count_pan_packet_timeout(unsigned long data) +#endif +{ + if (btrtl_coex.pan_packet_count) + RTKBT_DBG("%s: pan_packet_count %d", __func__, + btrtl_coex.pan_packet_count); + if (btrtl_coex.pan_packet_count < PAN_PACKET_COUNT) { + if (is_profile_busy(profile_pan)) { + RTKBT_DBG("%s: pan busy->idle!", __func__); + update_profile_state(profile_pan, FALSE); + } + } else { + if (!is_profile_busy(profile_pan)) { + RTKBT_DBG("timeout_handler: pan idle->busy!"); + update_profile_state(profile_pan, TRUE); + } + } + btrtl_coex.pan_packet_count = 0; + mod_timer(&btrtl_coex.pan_count_timer, + jiffies + msecs_to_jiffies(1000)); +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void count_hogp_packet_timeout(struct timer_list *unused) +#else +static void count_hogp_packet_timeout(unsigned long data) +#endif +{ + if (btrtl_coex.hogp_packet_count) + RTKBT_DBG("%s: hogp_packet_count %d", __func__, + btrtl_coex.hogp_packet_count); + if (btrtl_coex.hogp_packet_count == 0) { + if (is_profile_busy(profile_hogp)) { + RTKBT_DBG("%s: hogp busy->idle!", __func__); + update_profile_state(profile_hogp, FALSE); + } + } + btrtl_coex.hogp_packet_count = 0; + + if (btrtl_coex.voice_packet_count) + RTKBT_DBG("%s: voice_packet_count %d", __func__, + btrtl_coex.voice_packet_count); + if (btrtl_coex.voice_packet_count == 0) { + if (is_profile_busy(profile_voice)) { + RTKBT_DBG("%s: voice busy->idle!", __func__); + update_profile_state(profile_voice, FALSE); + } + } + btrtl_coex.voice_packet_count = 0; + mod_timer(&btrtl_coex.hogp_count_timer, + jiffies + msecs_to_jiffies(1000)); +} + +#ifdef RTB_SOFTWARE_MAILBOX + +#ifndef RTK_COEX_OVER_SYMBOL +static int udpsocket_send(char *tx_msg, int msg_size) +{ + u8 error = 0; + struct msghdr udpmsg; + mm_segment_t oldfs; + struct iovec iov; + + RTKBT_DBG("send msg %s with len:%d", tx_msg, msg_size); + + if (btrtl_coex.sock_open) { + iov.iov_base = (void *)tx_msg; + iov.iov_len = msg_size; + udpmsg.msg_name = &btrtl_coex.wifi_addr; + udpmsg.msg_namelen = sizeof(struct sockaddr_in); +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0) + udpmsg.msg_iov = &iov; + udpmsg.msg_iovlen = 1; +#else + iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size); +#endif + udpmsg.msg_control = NULL; + udpmsg.msg_controllen = 0; + udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL; + oldfs = get_fs(); + set_fs(KERNEL_DS); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0) + error = sock_sendmsg(btrtl_coex.udpsock, &udpmsg, msg_size); +#else + error = sock_sendmsg(btrtl_coex.udpsock, &udpmsg); +#endif + set_fs(oldfs); + + if (error < 0) + RTKBT_DBG("Error when sendimg msg, error:%d", error); + } + + return error; +} +#endif + +#ifdef RTK_COEX_OVER_SYMBOL +/* Receive message from WiFi */ +u8 rtw_btcoex_wifi_to_bt(u8 *msg, u8 msg_size) +{ + struct sk_buff *nskb; + + if (!rtw_coex_on) { + RTKBT_WARN("Bluetooth is closed"); + return 0; + } + + nskb = alloc_skb(msg_size, GFP_ATOMIC); + if (!nskb) { + RTKBT_ERR("Couldnt alloc skb for WiFi coex message"); + return 0; + } + + memcpy(skb_put(nskb, msg_size), msg, msg_size); + skb_queue_tail(&rtw_q, nskb); + + queue_work(rtw_wq, &rtw_work); + + return 1; +} +EXPORT_SYMBOL(rtw_btcoex_wifi_to_bt); + +static int rtk_send_coexmsg2wifi(u8 *msg, u8 size) +{ + u8 result; + u8 (*btmsg_to_wifi)(u8 *, u8); + + btmsg_to_wifi = __symbol_get(VMLINUX_SYMBOL_STR(rtw_btcoex_bt_to_wifi)); + + if (!btmsg_to_wifi) { + /* RTKBT_ERR("Couldnt get symbol"); */ + return -1; + } + + result = btmsg_to_wifi(msg, size); + __symbol_put(VMLINUX_SYMBOL_STR(rtw_btcoex_bt_to_wifi)); + if (!result) { + RTKBT_ERR("Couldnt send coex msg to WiFi"); + return -1; + } else if (result == 1){ + /* successful to send message */ + return 0; + } else { + RTKBT_ERR("Unknown result %d", result); + return -1; + } +} + +static int rtkbt_process_coexskb(struct sk_buff *skb) +{ + rtk_handle_event_from_wifi(skb->data); + return 0; +} + +static void rtw_work_func(struct work_struct *work) +{ + struct sk_buff *skb; + + while ((skb = skb_dequeue(&rtw_q))) { + rtkbt_process_coexskb(skb); + kfree_skb(skb); + } +} + +#endif + +static int rtkbt_coexmsg_send(char *tx_msg, int msg_size) +{ +#ifdef RTK_COEX_OVER_SYMBOL + return rtk_send_coexmsg2wifi((uint8_t *)tx_msg, (u8)msg_size); +#else + return udpsocket_send(tx_msg, msg_size); +#endif +} + +#ifndef RTK_COEX_OVER_SYMBOL +static void udpsocket_recv_data(void) +{ + u8 recv_data[512]; + u32 len = 0; + u16 recv_length; + struct sk_buff *skb; + + RTKBT_DBG("-"); + + spin_lock(&btrtl_coex.spin_lock_sock); + len = skb_queue_len(&btrtl_coex.sk->sk_receive_queue); + + while (len > 0) { + skb = skb_dequeue(&btrtl_coex.sk->sk_receive_queue); + + /*important: cut the udp header from skb->data! header length is 8 byte */ + recv_length = skb->len - 8; + memset(recv_data, 0, sizeof(recv_data)); + memcpy(recv_data, skb->data + 8, recv_length); + //RTKBT_DBG("received data: %s :with len %u", recv_data, recv_length); + + rtk_handle_event_from_wifi(recv_data); + + len--; + kfree_skb(skb); + } + + spin_unlock(&btrtl_coex.spin_lock_sock); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0) +static void udpsocket_recv(struct sock *sk, int bytes) +#else +static void udpsocket_recv(struct sock *sk) +#endif +{ + spin_lock(&btrtl_coex.spin_lock_sock); + btrtl_coex.sk = sk; + spin_unlock(&btrtl_coex.spin_lock_sock); + queue_delayed_work(btrtl_coex.sock_wq, &btrtl_coex.sock_work, 0); +} + +static void create_udpsocket(void) +{ + int err; + RTKBT_DBG("%s: connect_port: %d", __func__, CONNECT_PORT); + btrtl_coex.sock_open = 0; + + err = sock_create(AF_INET, SOCK_DGRAM, IPPROTO_UDP, + &btrtl_coex.udpsock); + if (err < 0) { + RTKBT_ERR("%s: sock create error, err = %d", __func__, err); + return; + } + + memset(&btrtl_coex.addr, 0, sizeof(struct sockaddr_in)); + btrtl_coex.addr.sin_family = AF_INET; + btrtl_coex.addr.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + btrtl_coex.addr.sin_port = htons(CONNECT_PORT); + + memset(&btrtl_coex.wifi_addr, 0, sizeof(struct sockaddr_in)); + btrtl_coex.wifi_addr.sin_family = AF_INET; + btrtl_coex.wifi_addr.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + btrtl_coex.wifi_addr.sin_port = htons(CONNECT_PORT_WIFI); + + err = + btrtl_coex.udpsock->ops->bind(btrtl_coex.udpsock, + (struct sockaddr *)&btrtl_coex. + addr, sizeof(struct sockaddr)); + if (err < 0) { + sock_release(btrtl_coex.udpsock); + RTKBT_ERR("%s: sock bind error, err = %d",__func__, err); + return; + } + + btrtl_coex.sock_open = 1; + btrtl_coex.udpsock->sk->sk_data_ready = udpsocket_recv; +} +#endif /* !RTK_COEX_OVER_SYMBOL */ + +static void rtk_notify_extension_version_to_wifi(void) +{ + uint8_t para_length = 2; + char p_buf[2 + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_EXTENSION_VERSION_NOTIFY); + *p++ = para_length; + UINT16_TO_STREAM(p, HCI_EXTENSION_VERSION); + RTKBT_DBG("extension version is 0x%x", HCI_EXTENSION_VERSION); + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_btpatch_version_to_wifi(void) +{ + uint8_t para_length = 4; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_PATCH_VER_NOTIFY); + *p++ = para_length; + UINT16_TO_STREAM(p, btrtl_coex.hci_reversion); + UINT16_TO_STREAM(p, btrtl_coex.lmp_subversion); + RTKBT_DBG("btpatch ver: len %u, hci_rev 0x%04x, lmp_subver 0x%04x", + para_length, btrtl_coex.hci_reversion, + btrtl_coex.lmp_subversion); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_afhmap_to_wifi(void) +{ + uint8_t para_length = 13; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + uint8_t kk = 0; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_AFH_MAP_NOTIFY); + *p++ = para_length; + *p++ = btrtl_coex.piconet_id; + *p++ = btrtl_coex.mode; + *p++ = 10; + memcpy(p, btrtl_coex.afh_map, 10); + + RTKBT_DBG("afhmap, piconet_id is 0x%x, map type is 0x%x", + btrtl_coex.piconet_id, btrtl_coex.mode); + for (kk = 0; kk < 10; kk++) + RTKBT_DBG("afhmap data[%d] is 0x%x", kk, + btrtl_coex.afh_map[kk]); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_btcoex_to_wifi(uint8_t opcode, uint8_t status) +{ + uint8_t para_length = 2; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_COEX_NOTIFY); + *p++ = para_length; + *p++ = opcode; + if (!status) + *p++ = 0; + else + *p++ = 1; + + RTKBT_DBG("btcoex, opcode is 0x%x, status is 0x%x", opcode, status); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_btoperation_to_wifi(uint8_t operation, + uint8_t append_data_length, + uint8_t * append_data) +{ + uint8_t para_length = 3 + append_data_length; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + uint8_t kk = 0; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_BT_OPERATION_NOTIFY); + *p++ = para_length; + *p++ = operation; + *p++ = append_data_length; + if (append_data_length) + memcpy(p, append_data, append_data_length); + + RTKBT_DBG("btoperation: op 0x%02x, append_data_length %u", + operation, append_data_length); + if (append_data_length) { + for (kk = 0; kk < append_data_length; kk++) + RTKBT_DBG("append data is 0x%x", *(append_data + kk)); + } + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_info_to_wifi(uint8_t reason, uint8_t length, + uint8_t *report_info) +{ + uint8_t para_length = 4 + length; + char buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = buf; + struct rtl_btinfo *report = (struct rtl_btinfo *)report_info; + + if (length) { + RTKBT_DBG("bt info: cmd %2.2X", report->cmd); + RTKBT_DBG("bt info: len %2.2X", report->len); + RTKBT_DBG("bt info: data %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X", + report->data[0], report->data[1], report->data[2], + report->data[3], report->data[4], report->data[5]); + } + RTKBT_DBG("bt info: reason 0x%2x, length 0x%2x", reason, length); + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_INFO_NOTIFY); + *p++ = para_length; + *p++ = btrtl_coex.polling_enable; + *p++ = btrtl_coex.polling_interval; + *p++ = reason; + *p++ = length; + + if (length) + memcpy(p, report_info, length); + + RTKBT_DBG("para length %2x, polling_enable %u, poiiling_interval %u", + para_length, btrtl_coex.polling_enable, + btrtl_coex.polling_interval); + /* send BT INFO to Wi-Fi driver */ + if (rtkbt_coexmsg_send(buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +static void rtk_notify_regester_to_wifi(uint8_t * reg_value) +{ + uint8_t para_length = 9; + char p_buf[para_length + HCI_CMD_PREAMBLE_SIZE]; + char *p = p_buf; + hci_mailbox_register *reg = (hci_mailbox_register *) reg_value; + + if (!btrtl_coex.wifi_on) + return; + + UINT16_TO_STREAM(p, HCI_OP_HCI_BT_REGISTER_VALUE_NOTIFY); + *p++ = para_length; + memcpy(p, reg_value, para_length); + + RTKBT_DBG("bt register, register type is %x", reg->type); + RTKBT_DBG("bt register, register offset is %x", reg->offset); + RTKBT_DBG("bt register, register value is %x", reg->value); + + if (rtkbt_coexmsg_send(p_buf, para_length + HCI_CMD_PREAMBLE_SIZE) < 0) + RTKBT_ERR("%s: sock send error", __func__); +} + +#endif + +void rtk_btcoex_parse_cmd(uint8_t *buffer, int count) +{ + u16 opcode = (buffer[0]) + (buffer[1] << 8); + + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_INFO("%s: Coex is closed, ignore", __func__); + return; + } + + switch (opcode) { + case HCI_OP_INQUIRY: + case HCI_OP_PERIODIC_INQ: + if (!btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci (periodic)inq, notify wifi " + "inquiry start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_START, + 0, NULL); +#else + RTKBT_INFO("hci (periodic)inq start"); +#endif + } + break; + case HCI_OP_INQUIRY_CANCEL: + case HCI_OP_EXIT_PERIODIC_INQ: + if (btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci (periodic)inq cancel/exit, notify wifi " + "inquiry stop"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, + NULL); +#else + RTKBT_INFO("hci (periodic)inq cancel/exit"); +#endif + } + break; + case HCI_OP_ACCEPT_CONN_REQ: + if (!btrtl_coex.ispaging) { + btrtl_coex.ispaging = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci accept connreq, notify wifi page start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_START, 0, + NULL); +#else + RTKBT_INFO("hci accept conn req"); +#endif + } + break; + case HCI_OP_DISCONNECT: + RTKBT_INFO("HCI Disconnect, handle %04x, reason 0x%02x", + ((u16)buffer[4] << 8 | buffer[3]), buffer[5]); + break; + default: + break; + } +} + +static void rtk_handle_inquiry_complete(void) +{ + if (btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("inq complete, notify wifi inquiry end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, NULL); +#else + RTKBT_INFO("inquiry complete"); +#endif + } +} + +static void rtk_handle_pin_code_req(void) +{ + if (!btrtl_coex.ispairing) { + btrtl_coex.ispairing = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("pin code req, notify wifi pair start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_START, 0, NULL); +#else + RTKBT_INFO("pin code request"); +#endif + } +} + +static void rtk_handle_io_capa_req(void) +{ + if (!btrtl_coex.ispairing) { + btrtl_coex.ispairing = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("io cap req, notify wifi pair start"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_START, 0, NULL); +#else + RTKBT_INFO("io capability request"); +#endif + } +} + +static void rtk_handle_auth_request(void) +{ + if (btrtl_coex.ispairing) { + btrtl_coex.ispairing = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("auth req, notify wifi pair end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_END, 0, NULL); +#else + RTKBT_INFO("authentication request"); +#endif + } +} + +static void rtk_handle_link_key_notify(void) +{ + if (btrtl_coex.ispairing) { + btrtl_coex.ispairing = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("link key notify, notify wifi pair end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_END, 0, NULL); +#else + RTKBT_INFO("link key notify"); +#endif + } +} + +static void rtk_handle_mode_change_evt(u8 * p) +{ + u16 mode_change_handle, mode_interval; + + p++; + STREAM_TO_UINT16(mode_change_handle, p); + p++; + STREAM_TO_UINT16(mode_interval, p); + update_hid_active_state(mode_change_handle, mode_interval); +} + +#ifdef RTB_SOFTWARE_MAILBOX +static void rtk_parse_vendor_mailbox_cmd_evt(u8 * p, u8 total_len) +{ + u8 status, subcmd; + u8 temp_cmd[10]; + + status = *p++; + if (total_len <= 4) { + RTKBT_DBG("receive mailbox cmd from fw, total length <= 4"); + return; + } + subcmd = *p++; + RTKBT_DBG("receive mailbox cmd from fw, subcmd is 0x%x, status is 0x%x", + subcmd, status); + + switch (subcmd) { + case HCI_VENDOR_SUB_CMD_BT_REPORT_CONN_SCO_INQ_INFO: + if (status == 0) //success + rtk_notify_info_to_wifi(POLLING_RESPONSE, + RTL_BTINFO_LEN, (uint8_t *)p); + break; + + case HCI_VENDOR_SUB_CMD_WIFI_CHANNEL_AND_BANDWIDTH_CMD: + rtk_notify_btcoex_to_wifi(WIFI_BW_CHNL_NOTIFY, status); + break; + + case HCI_VENDOR_SUB_CMD_WIFI_FORCE_TX_POWER_CMD: + rtk_notify_btcoex_to_wifi(BT_POWER_DECREASE_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_BT_ENABLE_IGNORE_WLAN_ACT_CMD: + rtk_notify_btcoex_to_wifi(IGNORE_WLAN_ACTIVE_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_SET_BT_PSD_MODE: + rtk_notify_btcoex_to_wifi(BT_PSD_MODE_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_SET_BT_LNA_CONSTRAINT: + rtk_notify_btcoex_to_wifi(LNA_CONSTRAIN_CONTROL, status); + break; + + case HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_ENABLE: + break; + + case HCI_VENDOR_SUB_CMD_BT_SET_TXRETRY_REPORT_PARAM: + break; + + case HCI_VENDOR_SUB_CMD_BT_SET_PTATABLE: + break; + + case HCI_VENDOR_SUB_CMD_GET_AFH_MAP_L: + if (status == 0) { + memcpy(btrtl_coex.afh_map, p + 4, 4); /* cmd_idx, length, piconet_id, mode */ + temp_cmd[0] = HCI_VENDOR_SUB_CMD_GET_AFH_MAP_M; + temp_cmd[1] = 2; + temp_cmd[2] = btrtl_coex.piconet_id; + temp_cmd[3] = btrtl_coex.mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 4, + temp_cmd); + } else { + memset(btrtl_coex.afh_map, 0, 10); + rtk_notify_afhmap_to_wifi(); + } + break; + + case HCI_VENDOR_SUB_CMD_GET_AFH_MAP_M: + if (status == 0) { + memcpy(btrtl_coex.afh_map + 4, p + 4, 4); + temp_cmd[0] = HCI_VENDOR_SUB_CMD_GET_AFH_MAP_H; + temp_cmd[1] = 2; + temp_cmd[2] = btrtl_coex.piconet_id; + temp_cmd[3] = btrtl_coex.mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 4, + temp_cmd); + } else { + memset(btrtl_coex.afh_map, 0, 10); + rtk_notify_afhmap_to_wifi(); + } + break; + + case HCI_VENDOR_SUB_CMD_GET_AFH_MAP_H: + if (status == 0) + memcpy(btrtl_coex.afh_map + 8, p + 4, 2); + else + memset(btrtl_coex.afh_map, 0, 10); + + rtk_notify_afhmap_to_wifi(); + break; + + case HCI_VENDOR_SUB_CMD_RD_REG_REQ: + if (status == 0) + rtk_notify_regester_to_wifi(p + 3); /* cmd_idx,length,regist type */ + break; + + case HCI_VENDOR_SUB_CMD_WR_REG_REQ: + rtk_notify_btcoex_to_wifi(BT_REGISTER_ACCESS, status); + break; + + default: + break; + } +} +#endif /* RTB_SOFTWARE_MAILBOX */ + +static void rtk_handle_cmd_complete_evt(u8 total_len, u8 * p) +{ + u16 opcode; + + p++; + STREAM_TO_UINT16(opcode, p); + //RTKBT_DBG("cmd_complete, opcode is 0x%x", opcode); + + if (opcode == HCI_OP_PERIODIC_INQ) { + if (*p++ && btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci period inq, start error, notify wifi " + "inquiry stop"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, + NULL); +#else + RTKBT_INFO("hci period inquiry start error"); +#endif + } + } + + if (opcode == HCI_OP_READ_LOCAL_VERSION) { + if (!(*p++)) { + p++; + STREAM_TO_UINT16(btrtl_coex.hci_reversion, p); + p += 3; + STREAM_TO_UINT16(btrtl_coex.lmp_subversion, p); + RTKBT_DBG("BTCOEX hci_rev 0x%04x", + btrtl_coex.hci_reversion); + RTKBT_DBG("BTCOEX lmp_subver 0x%04x", + btrtl_coex.lmp_subversion); + } + } + +#ifdef RTB_SOFTWARE_MAILBOX + if (opcode == HCI_VENDOR_MAILBOX_CMD) { + rtk_parse_vendor_mailbox_cmd_evt(p, total_len); + } +#endif +} + +static void rtk_handle_cmd_status_evt(u8 * p) +{ + u16 opcode; + u8 status; + + status = *p++; + p++; + STREAM_TO_UINT16(opcode, p); + //RTKBT_DBG("cmd_status, opcode is 0x%x", opcode); + if ((opcode == HCI_OP_INQUIRY) && (status)) { + if (btrtl_coex.isinquirying) { + btrtl_coex.isinquirying = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci inq, start error, notify wifi inq stop"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_INQUIRY_END, 0, + NULL); +#else + RTKBT_INFO("hci inquiry start error"); +#endif + } + } + + if (opcode == HCI_OP_CREATE_CONN) { + if (!status && !btrtl_coex.ispaging) { + btrtl_coex.ispaging = 1; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci create conn, notify wifi start page"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_START, 0, + NULL); +#else + RTKBT_INFO("hci create connection, start paging"); +#endif + } + } +} + +static void rtk_handle_connection_complete_evt(u8 * p) +{ + u16 handle; + u8 status, link_type; + rtk_conn_prof *hci_conn = NULL; + + status = *p++; + STREAM_TO_UINT16(handle, p); + p += 6; + link_type = *p++; + + RTKBT_INFO("connected, handle %04x, status 0x%02x", handle, status); + + if (status == 0) { + if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page success end"); + rtk_notify_btoperation_to_wifi + (BT_OPCODE_PAGE_SUCCESS_END, 0, NULL); +#else + RTKBT_INFO("Page success"); +#endif + } + + hci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (hci_conn == NULL) { + hci_conn = allocate_connection_by_handle(handle); + if (hci_conn) { + add_connection_to_hash(&btrtl_coex, + hci_conn); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + if ((0 == link_type) || (2 == link_type)) { //sco or esco + hci_conn->type = 1; + update_profile_connection(hci_conn, + profile_sco, + TRUE); + } else + hci_conn->type = 0; + } else { + RTKBT_ERR("hci connection allocate fail"); + } + } else { + RTKBT_DBG("hci conn handle 0x%04x already existed!", + handle); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + if ((0 == link_type) || (2 == link_type)) { //sco or esco + hci_conn->type = 1; + update_profile_connection(hci_conn, profile_sco, + TRUE); + } else + hci_conn->type = 0; + } + } else if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page unsuccess end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_UNSUCCESS_END, 0, + NULL); +#else + RTKBT_INFO("Page failed"); +#endif + } +} + +static void rtk_handle_le_connection_complete_evt(u8 enhanced, u8 * p) +{ + u16 handle, interval; + u8 status; + rtk_conn_prof *hci_conn = NULL; + + status = *p++; + STREAM_TO_UINT16(handle, p); + if (!enhanced) + p += 8; /* role, address type, address */ + else + p += (8 + 12); /* plus two bluetooth addresses */ + STREAM_TO_UINT16(interval, p); + + RTKBT_INFO("LE connected, handle %04x, status 0x%02x, interval %u", + handle, status, interval); + + if (status == 0) { + if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page success end"); + rtk_notify_btoperation_to_wifi + (BT_OPCODE_PAGE_SUCCESS_END, 0, NULL); +#else + RTKBT_INFO("Page success end"); +#endif + } + + hci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (hci_conn == NULL) { + hci_conn = allocate_connection_by_handle(handle); + if (hci_conn) { + add_connection_to_hash(&btrtl_coex, + hci_conn); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + hci_conn->type = 2; + update_profile_connection(hci_conn, profile_hid, TRUE); //for coex, le is the same as hid + update_hid_active_state(handle, interval); + } else { + RTKBT_ERR("hci connection allocate fail"); + } + } else { + RTKBT_DBG("hci conn handle 0x%04x already existed!", + handle); + hci_conn->profile_bitmap = 0; + memset(hci_conn->profile_refcount, 0, 8); + hci_conn->type = 2; + update_profile_connection(hci_conn, profile_hid, TRUE); + update_hid_active_state(handle, interval); + } + } else if (btrtl_coex.ispaging) { + btrtl_coex.ispaging = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi page unsuccess end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAGE_UNSUCCESS_END, 0, + NULL); +#else + RTKBT_INFO("Page failed"); +#endif + } +} + +static void rtk_handle_le_connection_update_complete_evt(u8 * p) +{ + u16 handle, interval; + /* u8 status; */ + + /* status = *p++; */ + p++; + + STREAM_TO_UINT16(handle, p); + STREAM_TO_UINT16(interval, p); + update_hid_active_state(handle, interval); +} + +static void rtk_handle_le_meta_evt(u8 * p) +{ + u8 sub_event = *p++; + switch (sub_event) { + case HCI_EV_LE_CONN_COMPLETE: + rtk_handle_le_connection_complete_evt(0, p); + break; + case HCI_EV_LE_ENHANCED_CONN_COMPLETE: + rtk_handle_le_connection_complete_evt(1, p); + break; + + case HCI_EV_LE_CONN_UPDATE_COMPLETE: + rtk_handle_le_connection_update_complete_evt(p); + break; + + default: + break; + } +} + +static u8 disconn_profile(struct rtl_hci_conn *conn, u8 pfe_index) +{ + u8 need_update = 0; + + if (!btrtl_coex.profile_refcount[pfe_index]) { + RTKBT_WARN("profile %u ref is 0", pfe_index); + return 0; + } + + btrtl_coex.profile_refcount[pfe_index]--; + RTKBT_INFO("%s: profile_ref[%u] %u", __func__, pfe_index, + btrtl_coex.profile_refcount[pfe_index]); + + if (!btrtl_coex.profile_refcount[pfe_index]) { + need_update = 1; + btrtl_coex.profile_bitmap &= ~(BIT(pfe_index)); + + /* if profile does not exist, status is meaningless */ + btrtl_coex.profile_status &= ~(BIT(pfe_index)); + rtk_check_del_timer(pfe_index); + } + + if (conn->profile_refcount[pfe_index]) + conn->profile_refcount[pfe_index]--; + else + RTKBT_INFO("%s: conn pfe ref[%u] is 0", __func__, + conn->profile_refcount[pfe_index]); + if (!conn->profile_refcount[pfe_index]) { + need_update = 1; + conn->profile_bitmap &= ~(BIT(pfe_index)); + + /* clear profile_hid_interval if need */ + if ((profile_hid == pfe_index) && + (conn->profile_bitmap & (BIT(profile_hid_interval)))) { + conn->profile_bitmap &= ~(BIT(profile_hid_interval)); + if (btrtl_coex.profile_refcount[profile_hid_interval]) + btrtl_coex.profile_refcount[profile_hid_interval]--; + } + } + + return need_update; +} + +static void disconn_acl(u16 handle, struct rtl_hci_conn *conn) +{ + struct rtl_coex_struct *coex = &btrtl_coex; + rtk_prof_info *prof_info = NULL; + struct list_head *iter = NULL, *temp = NULL; + u8 need_update = 0; + + spin_lock(&coex->spin_lock_profile); + + list_for_each_safe(iter, temp, &coex->profile_list) { + prof_info = list_entry(iter, rtk_prof_info, list); + if (handle == prof_info->handle) { + RTKBT_DBG("hci disconn, hndl %x, psm %x, dcid %x, " + "scid %x, profile %u", prof_info->handle, + prof_info->psm, prof_info->dcid, + prof_info->scid, prof_info->profile_index); + //If both scid and dcid > 0, L2cap connection is exist. + need_update |= disconn_profile(conn, + prof_info->profile_index); + if ((prof_info->flags & A2DP_MEDIA) && + (conn->profile_bitmap & BIT(profile_sink))) + need_update |= disconn_profile(conn, + profile_sink); + delete_profile_from_hash(prof_info); + } + } + if (need_update) + rtk_notify_profileinfo_to_fw(); + spin_unlock(&coex->spin_lock_profile); +} + +static void rtk_handle_disconnect_complete_evt(u8 * p) +{ + u16 handle; + u8 status; + u8 reason; + rtk_conn_prof *hci_conn = NULL; + + if (btrtl_coex.ispairing) { //for slave: connection will be disconnected if authentication fail + btrtl_coex.ispairing = 0; +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("hci disc complete, notify wifi pair end"); + rtk_notify_btoperation_to_wifi(BT_OPCODE_PAIR_END, 0, NULL); +#else + RTKBT_INFO("hci disconnection complete"); +#endif + } + + status = *p++; + STREAM_TO_UINT16(handle, p); + reason = *p; + + RTKBT_INFO("disconn cmpl evt: status 0x%02x, handle %04x, reason 0x%02x", + status, handle, reason); + + if (status == 0) { + RTKBT_DBG("process disconn complete event."); + hci_conn = find_connection_by_handle(&btrtl_coex, handle); + if (hci_conn) { + switch (hci_conn->type) { + case 0: + /* FIXME: If this is interrupted by l2cap rx, + * there may be deadlock on spin_lock_profile */ + disconn_acl(handle, hci_conn); + break; + + case 1: + update_profile_connection(hci_conn, profile_sco, + FALSE); + break; + + case 2: + update_profile_connection(hci_conn, profile_hid, + FALSE); + break; + + default: + break; + } + delete_connection_from_hash(hci_conn); + } else + RTKBT_ERR("hci conn handle 0x%04x not found", handle); + } +} + +static void rtk_handle_specific_evt(u8 * p) +{ + u16 subcode; + + STREAM_TO_UINT16(subcode, p); + if (subcode == HCI_VENDOR_PTA_AUTO_REPORT_EVENT) { +#ifdef RTB_SOFTWARE_MAILBOX + RTKBT_DBG("notify wifi driver with autoreport data"); + rtk_notify_info_to_wifi(AUTO_REPORT, RTL_BTINFO_LEN, + (uint8_t *)p); +#else + RTKBT_INFO("auto report data"); +#endif + } +} + +static void rtk_parse_event_data(struct rtl_coex_struct *coex, + u8 *data, u16 len) +{ + u8 *p = data; + u8 event_code = *p++; + u8 total_len = *p++; + + (void)coex; + (void)&len; + + switch (event_code) { + case HCI_EV_INQUIRY_COMPLETE: + rtk_handle_inquiry_complete(); + break; + + case HCI_EV_PIN_CODE_REQ: + rtk_handle_pin_code_req(); + break; + + case HCI_EV_IO_CAPA_REQUEST: + rtk_handle_io_capa_req(); + break; + + case HCI_EV_AUTH_COMPLETE: + rtk_handle_auth_request(); + break; + + case HCI_EV_LINK_KEY_NOTIFY: + rtk_handle_link_key_notify(); + break; + + case HCI_EV_MODE_CHANGE: + rtk_handle_mode_change_evt(p); + break; + + case HCI_EV_CMD_COMPLETE: + rtk_handle_cmd_complete_evt(total_len, p); + break; + + case HCI_EV_CMD_STATUS: + rtk_handle_cmd_status_evt(p); + break; + + case HCI_EV_CONN_COMPLETE: + case HCI_EV_SYNC_CONN_COMPLETE: + rtk_handle_connection_complete_evt(p); + break; + + case HCI_EV_DISCONN_COMPLETE: + rtk_handle_disconnect_complete_evt(p); + break; + + case HCI_EV_LE_META: + rtk_handle_le_meta_evt(p); + break; + + case HCI_EV_VENDOR_SPECIFIC: + rtk_handle_specific_evt(p); + break; + + default: + break; + } +} + +const char l2_dir_str[][4] = { + "RX", "TX", +}; + +void rtl_process_l2_sig(struct rtl_l2_buff *l2) +{ + /* u8 flag; */ + u8 code; + /* u8 identifier; */ + u16 handle; + /* u16 total_len; */ + /* u16 pdu_len, channel_id; */ + /* u16 command_len; */ + u16 psm, scid, dcid, result; + /* u16 status; */ + u8 *pp = l2->data; + + STREAM_TO_UINT16(handle, pp); + /* flag = handle >> 12; */ + handle = handle & 0x0FFF; + /* STREAM_TO_UINT16(total_len, pp); */ + pp += 2; /* data total length */ + + /* STREAM_TO_UINT16(pdu_len, pp); + * STREAM_TO_UINT16(channel_id, pp); */ + pp += 4; /* l2 len and channel id */ + + code = *pp++; + switch (code) { + case L2CAP_CONN_REQ: + /* identifier = *pp++; */ + pp++; + /* STREAM_TO_UINT16(command_len, pp); */ + pp += 2; + STREAM_TO_UINT16(psm, pp); + STREAM_TO_UINT16(scid, pp); + RTKBT_DBG("%s l2cap conn req, hndl 0x%04x, PSM 0x%04x, " + "scid 0x%04x", l2_dir_str[l2->out], handle, psm, + scid); + handle_l2cap_con_req(handle, psm, scid, l2->out); + break; + + case L2CAP_CONN_RSP: + /* identifier = *pp++; */ + pp++; + /* STREAM_TO_UINT16(command_len, pp); */ + pp += 2; + STREAM_TO_UINT16(dcid, pp); + STREAM_TO_UINT16(scid, pp); + STREAM_TO_UINT16(result, pp); + /* STREAM_TO_UINT16(status, pp); */ + pp += 2; + RTKBT_DBG("%s l2cap conn rsp, hndl 0x%04x, dcid 0x%04x, " + "scid 0x%04x, result 0x%04x", l2_dir_str[l2->out], + handle, dcid, scid, result); + handle_l2cap_con_rsp(handle, dcid, scid, l2->out, result); + break; + + case L2CAP_DISCONN_REQ: + /* identifier = *pp++; */ + pp++; + /* STREAM_TO_UINT16(command_len, pp); */ + pp += 2; + STREAM_TO_UINT16(dcid, pp); + STREAM_TO_UINT16(scid, pp); + RTKBT_DBG("%s l2cap disconn req, hndl 0x%04x, dcid 0x%04x, " + "scid 0x%04x", l2_dir_str[l2->out], handle, dcid, scid); + handle_l2cap_discon_req(handle, dcid, scid, l2->out); + break; + default: + RTKBT_DBG("undesired l2 command %u", code); + break; + } +} + +static void rtl_l2_data_process(u8 *pp, u16 len, int dir) +{ + u8 code; + u8 flag; + u16 handle, pdu_len, channel_id; + /* u16 total_len; */ + struct rtl_l2_buff *l2 = NULL; + u8 *hd = pp; + + /* RTKBT_DBG("l2 sig data %p, len %u, dir %d", pp, len, dir); */ + + STREAM_TO_UINT16(handle, pp); + flag = handle >> 12; + handle = handle & 0x0FFF; + /* STREAM_TO_UINT16(total_len, pp); */ + pp += 2; /* data total length */ + + STREAM_TO_UINT16(pdu_len, pp); + STREAM_TO_UINT16(channel_id, pp); + + if (channel_id == 0x0001) { + code = *pp++; + switch (code) { + case L2CAP_CONN_REQ: + case L2CAP_CONN_RSP: + case L2CAP_DISCONN_REQ: + RTKBT_DBG("l2cap op %u, len %u, out %d", code, len, + dir); + l2 = rtl_l2_node_get(&btrtl_coex); + if (l2) { + u16 n; + n = min_t(uint, len, L2_MAX_SUBSEC_LEN); + memcpy(l2->data, hd, n); + l2->out = dir; + rtl_l2_node_to_used(&btrtl_coex, l2); + queue_delayed_work(btrtl_coex.fw_wq, + &btrtl_coex.l2_work, 0); + } else + RTKBT_ERR("%s: failed to get l2 node", + __func__); + break; + case L2CAP_DISCONN_RSP: + break; + default: + break; + } + } else { + if ((flag != 0x01) && (is_profile_connected(profile_a2dp) || + is_profile_connected(profile_pan))) + /* Do not count the continuous packets */ + packets_count(handle, channel_id, pdu_len, dir, pp); + } + return; +} + + +static void rtl_l2_work(struct work_struct *work) +{ + struct rtl_coex_struct *coex; + struct rtl_l2_buff *l2; + unsigned long flags; + + coex = container_of(work, struct rtl_coex_struct, l2_work.work); + + spin_lock_irqsave(&coex->buff_lock, flags); + while (!list_empty(&coex->l2_used_list)) { + l2 = list_entry(coex->l2_used_list.next, struct rtl_l2_buff, + list); + list_del(&l2->list); + + spin_unlock_irqrestore(&coex->buff_lock, flags); + + rtl_process_l2_sig(l2); + + spin_lock_irqsave(&coex->buff_lock, flags); + + list_add_tail(&l2->list, &coex->l2_free_list); + } + spin_unlock_irqrestore(&coex->buff_lock, flags); + + return; +} + +static void rtl_ev_work(struct work_struct *work) +{ + struct rtl_coex_struct *coex; + struct rtl_hci_ev *ev; + unsigned long flags; + + coex = container_of(work, struct rtl_coex_struct, fw_work.work); + + spin_lock_irqsave(&coex->buff_lock, flags); + while (!list_empty(&coex->ev_used_list)) { + ev = list_entry(coex->ev_used_list.next, struct rtl_hci_ev, + list); + list_del(&ev->list); + spin_unlock_irqrestore(&coex->buff_lock, flags); + + rtk_parse_event_data(coex, ev->data, ev->len); + + spin_lock_irqsave(&coex->buff_lock, flags); + list_add_tail(&ev->list, &coex->ev_free_list); + } + spin_unlock_irqrestore(&coex->buff_lock, flags); +} + +static inline int cmd_cmplt_filter_out(u8 *buf) +{ + u16 opcode; + + opcode = buf[3] | (buf[4] << 8); + switch (opcode) { + case HCI_OP_PERIODIC_INQ: + case HCI_OP_READ_LOCAL_VERSION: +#ifdef RTB_SOFTWARE_MAILBOX + case HCI_VENDOR_MAILBOX_CMD: +#endif + return 0; + default: + return 1; + } +} + +static inline int cmd_status_filter_out(u8 *buf) +{ + u16 opcode; + + opcode = buf[4] | (buf[5] << 8); + switch (opcode) { + case HCI_OP_INQUIRY: + case HCI_OP_CREATE_CONN: + return 0; + default: + return 1; + } +} + +int ev_filter_out(u8 *buf) +{ + switch (buf[0]) { + case HCI_EV_INQUIRY_COMPLETE: + case HCI_EV_PIN_CODE_REQ: + case HCI_EV_IO_CAPA_REQUEST: + case HCI_EV_AUTH_COMPLETE: + case HCI_EV_LINK_KEY_NOTIFY: + case HCI_EV_MODE_CHANGE: + case HCI_EV_CONN_COMPLETE: + case HCI_EV_SYNC_CONN_COMPLETE: + case HCI_EV_DISCONN_COMPLETE: + case HCI_EV_VENDOR_SPECIFIC: + return 0; + case HCI_EV_LE_META: + /* Ignore frequent but not useful events that result in + * costing too much space. + */ + switch (buf[2]) { + case HCI_EV_LE_CONN_COMPLETE: + case HCI_EV_LE_ENHANCED_CONN_COMPLETE: + case HCI_EV_LE_CONN_UPDATE_COMPLETE: + return 0; + } + return 1; + case HCI_EV_CMD_COMPLETE: + return cmd_cmplt_filter_out(buf); + case HCI_EV_CMD_STATUS: + return cmd_status_filter_out(buf); + default: + return 1; + } +} + +static void rtk_btcoex_evt_enqueue(__u8 *s, __u16 count) +{ + struct rtl_hci_ev *ev; + + if (ev_filter_out(s)) + return; + + ev = rtl_ev_node_get(&btrtl_coex); + if (!ev) { + RTKBT_ERR("%s: no free ev node.", __func__); + return; + } + + if (count > MAX_LEN_OF_HCI_EV) { + memcpy(ev->data, s, MAX_LEN_OF_HCI_EV); + ev->len = MAX_LEN_OF_HCI_EV; + } else { + memcpy(ev->data, s, count); + ev->len = count; + } + + rtl_ev_node_to_used(&btrtl_coex, ev); + + queue_delayed_work(btrtl_coex.fw_wq, &btrtl_coex.fw_work, 0); +} + +/* Context: in_interrupt() */ +void rtk_btcoex_parse_event(uint8_t *buffer, int count) +{ + struct rtl_coex_struct *coex = &btrtl_coex; + __u8 *tbuff; + __u16 elen = 0; + + /* RTKBT_DBG("%s: parse ev.", __func__); */ + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + /* RTKBT_INFO("%s: Coex is closed, ignore", __func__); */ + RTKBT_INFO("%s: Coex is closed, ignore %x, %x", + __func__, buffer[0], buffer[1]); + return; + } + + spin_lock(&coex->rxlock); + + /* coex->tbuff will be set to NULL when initializing or + * there is a complete frame or there is start of a frame */ + tbuff = coex->tbuff; + + while (count) { + int len; + + /* Start of a frame */ + if (!tbuff) { + tbuff = coex->back_buff; + coex->tbuff = NULL; + coex->elen = 0; + + coex->pkt_type = HCI_EVENT_PKT; + coex->expect = HCI_EVENT_HDR_SIZE; + } + + len = min_t(uint, coex->expect, count); + memcpy(tbuff, buffer, len); + tbuff += len; + coex->elen += len; + + count -= len; + buffer += len; + coex->expect -= len; + + if (coex->elen == HCI_EVENT_HDR_SIZE) { + /* Complete event header */ + coex->expect = + ((struct hci_event_hdr *)coex->back_buff)->plen; + if (coex->expect > HCI_MAX_EVENT_SIZE - coex->elen) { + tbuff = NULL; + coex->elen = 0; + RTKBT_ERR("tbuff room is not enough"); + break; + } + } + + if (coex->expect == 0) { + /* Complete frame */ + elen = coex->elen; + spin_unlock(&coex->rxlock); + rtk_btcoex_evt_enqueue(coex->back_buff, elen); + spin_lock(&coex->rxlock); + + tbuff = NULL; + coex->elen = 0; + } + } + + /* coex->tbuff would be non-NULL if there isn't a complete frame + * And it will be updated next time */ + coex->tbuff = tbuff; + spin_unlock(&coex->rxlock); +} + + +void rtk_btcoex_parse_l2cap_data_tx(uint8_t *buffer, int count) +{ + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_INFO("%s: Coex is closed, ignore", __func__); + return; + } + + rtl_l2_data_process(buffer, count, 1); + //u16 handle, total_len, pdu_len, channel_ID, command_len, psm, scid, + // dcid, result, status; + //u8 flag, code, identifier; + //u8 *pp = (u8 *) (skb->data); + //STREAM_TO_UINT16(handle, pp); + //flag = handle >> 12; + //handle = handle & 0x0FFF; + //STREAM_TO_UINT16(total_len, pp); + //STREAM_TO_UINT16(pdu_len, pp); + //STREAM_TO_UINT16(channel_ID, pp); + + //if (channel_ID == 0x0001) { + // code = *pp++; + // switch (code) { + // case L2CAP_CONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(psm, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("TX l2cap conn req, hndl %x, PSM %x, scid=%x", + // handle, psm, scid); + // handle_l2cap_con_req(handle, psm, scid, 1); + // break; + + // case L2CAP_CONN_RSP: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // STREAM_TO_UINT16(result, pp); + // STREAM_TO_UINT16(status, pp); + // RTKBT_DBG("TX l2cap conn rsp, hndl %x, dcid %x, " + // "scid %x, result %x", + // handle, dcid, scid, result); + // handle_l2cap_con_rsp(handle, dcid, scid, 1, result); + // break; + + // case L2CAP_DISCONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("TX l2cap disconn req, hndl %x, dcid %x, " + // "scid %x", handle, dcid, scid); + // handle_l2cap_discon_req(handle, dcid, scid, 1); + // break; + + // case L2CAP_DISCONN_RSP: + // break; + + // default: + // break; + // } + //} else { + // if ((flag != 0x01) && (is_profile_connected(profile_a2dp) || is_profile_connected(profile_pan))) //Do not count the continuous packets + // packets_count(handle, channel_ID, pdu_len, 1, pp); + //} +} + +void rtk_btcoex_parse_l2cap_data_rx(uint8_t *buffer, int count) +{ + if (!test_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_INFO("%s: Coex is closed, ignore", __func__); + return; + } + + rtl_l2_data_process(buffer, count, 0); + //u16 handle, total_len, pdu_len, channel_ID, command_len, psm, scid, + // dcid, result, status; + //u8 flag, code, identifier; + //u8 *pp = urb->transfer_buffer; + //STREAM_TO_UINT16(handle, pp); + //flag = handle >> 12; + //handle = handle & 0x0FFF; + //STREAM_TO_UINT16(total_len, pp); + //STREAM_TO_UINT16(pdu_len, pp); + //STREAM_TO_UINT16(channel_ID, pp); + + //if (channel_ID == 0x0001) { + // code = *pp++; + // switch (code) { + // case L2CAP_CONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(psm, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("RX l2cap conn req, hndl %x, PSM %x, scid %x", + // handle, psm, scid); + // handle_l2cap_con_req(handle, psm, scid, 0); + // break; + + // case L2CAP_CONN_RSP: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // STREAM_TO_UINT16(result, pp); + // STREAM_TO_UINT16(status, pp); + // RTKBT_DBG("RX l2cap conn rsp, hndl %x, dcid %x, " + // "scid %x, result %x", + // handle, dcid, scid, result); + // handle_l2cap_con_rsp(handle, dcid, scid, 0, result); + // break; + + // case L2CAP_DISCONN_REQ: + // identifier = *pp++; + // STREAM_TO_UINT16(command_len, pp); + // STREAM_TO_UINT16(dcid, pp); + // STREAM_TO_UINT16(scid, pp); + // RTKBT_DBG("RX l2cap disconn req, hndl %x, dcid %x, " + // "scid %x", handle, dcid, scid); + // handle_l2cap_discon_req(handle, dcid, scid, 0); + // break; + + // case L2CAP_DISCONN_RSP: + // break; + + // default: + // break; + // } + //} else { + // if ((flag != 0x01) && (is_profile_connected(profile_a2dp) || is_profile_connected(profile_pan))) //Do not count the continuous packets + // packets_count(handle, channel_ID, pdu_len, 0, pp); + //} +} + +#ifdef RTB_SOFTWARE_MAILBOX + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +static void polling_bt_info(struct timer_list *unused) +#else +static void polling_bt_info(unsigned long data) +#endif +{ + uint8_t temp_cmd[1]; + RTKBT_DBG("polling timer"); + if (btrtl_coex.polling_enable) { + //temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_REPORT_CONN_SCO_INQ_INFO; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_STATUS_INFO; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 1, temp_cmd); + } + mod_timer(&btrtl_coex.polling_timer, + jiffies + msecs_to_jiffies(1000 * btrtl_coex.polling_interval)); +} + +static void rtk_handle_bt_info_control(uint8_t *p) +{ + uint8_t temp_cmd[20]; + struct rtl_btinfo_ctl *ctl = (struct rtl_btinfo_ctl*)p; + RTKBT_DBG("Received polling_enable %u, polling_time %u, " + "autoreport_enable %u", ctl->polling_enable, + ctl->polling_time, ctl->autoreport_enable); + RTKBT_DBG("coex: original polling_enable %u", + btrtl_coex.polling_enable); + + if (ctl->polling_enable && !btrtl_coex.polling_enable) { + /* setup polling timer for getting bt info from firmware */ + btrtl_coex.polling_timer.expires = + jiffies + msecs_to_jiffies(ctl->polling_time * 1000); + mod_timer(&btrtl_coex.polling_timer, + btrtl_coex.polling_timer.expires); + } + + /* Close bt info polling timer */ + if (!ctl->polling_enable && btrtl_coex.polling_enable) + del_timer(&btrtl_coex.polling_timer); + + if (btrtl_coex.autoreport != ctl->autoreport_enable) { + temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_ENABLE; + temp_cmd[1] = 1; + temp_cmd[2] = ctl->autoreport_enable; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + } + + btrtl_coex.polling_enable = ctl->polling_enable; + btrtl_coex.polling_interval = ctl->polling_time; + btrtl_coex.autoreport = ctl->autoreport_enable; + + rtk_notify_info_to_wifi(HOST_RESPONSE, 0, NULL); +} + +static void rtk_handle_bt_coex_control(uint8_t * p) +{ + uint8_t temp_cmd[20]; + uint8_t opcode, opcode_len, value, power_decrease, psd_mode, + access_type; + + opcode = *p++; + RTKBT_DBG("receive bt coex control event from wifi, op 0x%02x", opcode); + + switch (opcode) { + case BT_PATCH_VERSION_QUERY: + rtk_notify_btpatch_version_to_wifi(); + break; + + case IGNORE_WLAN_ACTIVE_CONTROL: + opcode_len = *p++; + value = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_BT_ENABLE_IGNORE_WLAN_ACT_CMD; + temp_cmd[1] = 1; + temp_cmd[2] = value; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case LNA_CONSTRAIN_CONTROL: + opcode_len = *p++; + value = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_SET_BT_LNA_CONSTRAINT; + temp_cmd[1] = 1; + temp_cmd[2] = value; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case BT_POWER_DECREASE_CONTROL: + opcode_len = *p++; + power_decrease = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_WIFI_FORCE_TX_POWER_CMD; + temp_cmd[1] = 1; + temp_cmd[2] = power_decrease; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case BT_PSD_MODE_CONTROL: + opcode_len = *p++; + psd_mode = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_SET_BT_PSD_MODE; + temp_cmd[1] = 1; + temp_cmd[2] = psd_mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 3, temp_cmd); + break; + + case WIFI_BW_CHNL_NOTIFY: + opcode_len = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_WIFI_CHANNEL_AND_BANDWIDTH_CMD; + temp_cmd[1] = 3; + memcpy(temp_cmd + 2, p, 3); //wifi_state, wifi_centralchannel, chnnels_btnotuse + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 5, temp_cmd); + break; + + case QUERY_BT_AFH_MAP: + opcode_len = *p++; + btrtl_coex.piconet_id = *p++; + btrtl_coex.mode = *p++; + temp_cmd[0] = HCI_VENDOR_SUB_CMD_GET_AFH_MAP_L; + temp_cmd[1] = 2; + temp_cmd[2] = btrtl_coex.piconet_id; + temp_cmd[3] = btrtl_coex.mode; + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 4, temp_cmd); + break; + + case BT_REGISTER_ACCESS: + opcode_len = *p++; + access_type = *p++; + if (access_type == 0) { //read + temp_cmd[0] = HCI_VENDOR_SUB_CMD_RD_REG_REQ; + temp_cmd[1] = 5; + temp_cmd[2] = *p++; + memcpy(temp_cmd + 3, p, 4); + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 7, + temp_cmd); + } else { //write + temp_cmd[0] = HCI_VENDOR_SUB_CMD_RD_REG_REQ; + temp_cmd[1] = 5; + temp_cmd[2] = *p++; + memcpy(temp_cmd + 3, p, 8); + rtk_vendor_cmd_to_fw(HCI_VENDOR_MAILBOX_CMD, 11, + temp_cmd); + } + break; + + default: + break; + } +} + +static void rtk_handle_event_from_wifi(uint8_t * msg) +{ + uint8_t *p = msg; + uint8_t event_code = *p++; + uint8_t total_length; + uint8_t extension_event; + uint8_t operation; + uint16_t wifi_opcode; + uint8_t op_status; + + if (memcmp(msg, invite_rsp, sizeof(invite_rsp)) == 0) { + RTKBT_DBG("receive invite rsp from wifi, wifi is already on"); + btrtl_coex.wifi_on = 1; + rtk_notify_extension_version_to_wifi(); + } + + if (memcmp(msg, attend_req, sizeof(attend_req)) == 0) { + RTKBT_DBG("receive attend req from wifi, wifi turn on"); + btrtl_coex.wifi_on = 1; + rtkbt_coexmsg_send(attend_ack, sizeof(attend_ack)); + rtk_notify_extension_version_to_wifi(); + } + + if (memcmp(msg, wifi_leave, sizeof(wifi_leave)) == 0) { + RTKBT_DBG("receive wifi leave from wifi, wifi turn off"); + btrtl_coex.wifi_on = 0; + rtkbt_coexmsg_send(leave_ack, sizeof(leave_ack)); + if (btrtl_coex.polling_enable) { + btrtl_coex.polling_enable = 0; + del_timer(&btrtl_coex.polling_timer); + } + } + + if (memcmp(msg, leave_ack, sizeof(leave_ack)) == 0) { + RTKBT_DBG("receive leave ack from wifi"); + } + + if (event_code == 0xFE) { + total_length = *p++; + extension_event = *p++; + switch (extension_event) { + case RTK_HS_EXTENSION_EVENT_WIFI_SCAN: + operation = *p; + RTKBT_DBG("Recv WiFi scan notify event from WiFi, " + "op 0x%02x", operation); + break; + + case RTK_HS_EXTENSION_EVENT_HCI_BT_INFO_CONTROL: + rtk_handle_bt_info_control(p); + break; + + case RTK_HS_EXTENSION_EVENT_HCI_BT_COEX_CONTROL: + rtk_handle_bt_coex_control(p); + break; + + default: + break; + } + } + + if (event_code == 0x0E) { + p += 2; //length, number of complete packets + STREAM_TO_UINT16(wifi_opcode, p); + op_status = *p; + RTKBT_DBG("Recv cmd complete event from WiFi, op 0x%02x, " + "status 0x%02x", wifi_opcode, op_status); + } +} +#endif /* RTB_SOFTWARE_MAILBOX */ + +static inline void rtl_free_frags(struct rtl_coex_struct *coex) +{ + unsigned long flags; + + spin_lock_irqsave(&coex->rxlock, flags); + + coex->elen = 0; + coex->tbuff = NULL; + + spin_unlock_irqrestore(&coex->rxlock, flags); +} + +void rtk_btcoex_open(struct hci_dev *hdev) +{ + if (test_and_set_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_WARN("RTL COEX is already running."); + return; + } + + RTKBT_INFO("Open BTCOEX"); + + /* Just for test */ + //struct rtl_btinfo_ctl ctl; + + INIT_DELAYED_WORK(&btrtl_coex.fw_work, (void *)rtl_ev_work); +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL + INIT_WORK(&rtw_work, rtw_work_func); + skb_queue_head_init(&rtw_q); + rtw_coex_on = 1; +#else + INIT_DELAYED_WORK(&btrtl_coex.sock_work, + (void *)udpsocket_recv_data); +#endif +#endif /* RTB_SOFTWARE_MAILBOX */ + INIT_DELAYED_WORK(&btrtl_coex.l2_work, (void *)rtl_l2_work); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 14, 0) +#ifdef RTB_SOFTWARE_MAILBOX + timer_setup(&btrtl_coex.polling_timer, polling_bt_info, 0); +#endif + timer_setup(&btrtl_coex.a2dp_count_timer, count_a2dp_packet_timeout, 0); + timer_setup(&btrtl_coex.pan_count_timer, count_pan_packet_timeout, 0); + timer_setup(&btrtl_coex.hogp_count_timer, count_hogp_packet_timeout, 0); +#else +#ifdef RTB_SOFTWARE_MAILBOX + setup_timer(&btrtl_coex.polling_timer, polling_bt_info, 0); +#endif + setup_timer(&btrtl_coex.a2dp_count_timer, count_a2dp_packet_timeout, 0); + setup_timer(&btrtl_coex.pan_count_timer, count_pan_packet_timeout, 0); + setup_timer(&btrtl_coex.hogp_count_timer, count_hogp_packet_timeout, 0); +#endif + + btrtl_coex.hdev = hdev; +#ifdef RTB_SOFTWARE_MAILBOX + btrtl_coex.wifi_on = 0; +#endif + + init_profile_hash(&btrtl_coex); + init_connection_hash(&btrtl_coex); + + btrtl_coex.pkt_type = 0; + btrtl_coex.expect = 0; + btrtl_coex.elen = 0; + btrtl_coex.tbuff = NULL; + +#ifdef RTB_SOFTWARE_MAILBOX +#ifndef RTK_COEX_OVER_SYMBOL + create_udpsocket(); +#endif + rtkbt_coexmsg_send(invite_req, sizeof(invite_req)); +#endif + + /* Just for test */ + //ctl.polling_enable = 1; + //ctl.polling_time = 1; + //ctl.autoreport_enable = 1; + //rtk_handle_bt_info_control((u8 *)&ctl); +} + +void rtk_btcoex_close(void) +{ + int kk = 0; + + if (!test_and_clear_bit(RTL_COEX_RUNNING, &btrtl_coex.flags)) { + RTKBT_WARN("RTL COEX is already closed."); + return; + } + + RTKBT_INFO("Close BTCOEX"); + +#ifdef RTB_SOFTWARE_MAILBOX + /* Close coex socket */ + if (btrtl_coex.wifi_on) + rtkbt_coexmsg_send(bt_leave, sizeof(bt_leave)); +#ifdef RTK_COEX_OVER_SYMBOL + rtw_coex_on = 0; + skb_queue_purge(&rtw_q); + cancel_work_sync(&rtw_work); +#else + cancel_delayed_work_sync(&btrtl_coex.sock_work); + if (btrtl_coex.sock_open) { + btrtl_coex.sock_open = 0; + RTKBT_DBG("release udp socket"); + sock_release(btrtl_coex.udpsock); + } +#endif + + /* Delete all timers */ + if (btrtl_coex.polling_enable) { + btrtl_coex.polling_enable = 0; + del_timer_sync(&(btrtl_coex.polling_timer)); + } +#endif /* RTB_SOFTWARE_MAILBOX */ + + del_timer_sync(&btrtl_coex.a2dp_count_timer); + del_timer_sync(&btrtl_coex.pan_count_timer); + del_timer_sync(&btrtl_coex.hogp_count_timer); + + cancel_delayed_work_sync(&btrtl_coex.fw_work); + cancel_delayed_work_sync(&btrtl_coex.l2_work); + + flush_connection_hash(&btrtl_coex); + flush_profile_hash(&btrtl_coex); + btrtl_coex.profile_bitmap = 0; + btrtl_coex.profile_status = 0; + for (kk = 0; kk < 8; kk++) + btrtl_coex.profile_refcount[kk] = 0; + + rtl_free_frags(&btrtl_coex); + RTKBT_DBG("-x"); +} + +void rtk_btcoex_probe(struct hci_dev *hdev) +{ + btrtl_coex.hdev = hdev; + spin_lock_init(&btrtl_coex.spin_lock_sock); + spin_lock_init(&btrtl_coex.spin_lock_profile); +} + +void rtk_btcoex_init(void) +{ + RTKBT_DBG("%s: version: %s", __func__, RTK_VERSION); + RTKBT_DBG("create workqueue"); +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL + RTKBT_INFO("Coex over Symbol"); + rtw_wq = create_workqueue("btcoexwork"); + skb_queue_head_init(&rtw_q); +#else + RTKBT_INFO("Coex over UDP"); + btrtl_coex.sock_wq = create_workqueue("btudpwork"); +#endif +#endif /* RTB_SOFTWARE_MAILBOX */ + btrtl_coex.fw_wq = create_workqueue("btfwwork"); + rtl_alloc_buff(&btrtl_coex); + spin_lock_init(&btrtl_coex.rxlock); +} + +void rtk_btcoex_exit(void) +{ + RTKBT_DBG("%s: destroy workqueue", __func__); +#ifdef RTB_SOFTWARE_MAILBOX +#ifdef RTK_COEX_OVER_SYMBOL + flush_workqueue(rtw_wq); + destroy_workqueue(rtw_wq); +#else + flush_workqueue(btrtl_coex.sock_wq); + destroy_workqueue(btrtl_coex.sock_wq); +#endif +#endif + flush_workqueue(btrtl_coex.fw_wq); + destroy_workqueue(btrtl_coex.fw_wq); + rtl_free_buff(&btrtl_coex); +} diff --git a/drivers/bluetooth/rtk_coex.h b/drivers/bluetooth/rtk_coex.h new file mode 100644 index 0000000000000..5b0ec85f0c60e --- /dev/null +++ b/drivers/bluetooth/rtk_coex.h @@ -0,0 +1,373 @@ +/* +* +* Realtek Bluetooth USB driver +* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +* +*/ +#include +#include + +/*********************************** +** Realtek - For coexistence ** +***********************************/ +#define BTRTL_HCIUSB 0 +#define BTRTL_HCIUART 1 + +#define BTRTL_HCI_IF BTRTL_HCIUSB + +#define TRUE 1 +#define FALSE 0 + +#define CONNECT_PORT 30001 +#define CONNECT_PORT_WIFI 30000 + +#define invite_req "INVITE_REQ" +#define invite_rsp "INVITE_RSP" +#define attend_req "ATTEND_REQ" +#define attend_ack "ATTEND_ACK" +#define wifi_leave "WIFI_LEAVE" +#define leave_ack "LEAVE_ACK" +#define bt_leave "BT_LEAVE" + +#define HCI_OP_PERIODIC_INQ 0x0403 +#define HCI_EV_LE_META 0x3e +#define HCI_EV_LE_CONN_COMPLETE 0x01 +#define HCI_EV_LE_CONN_UPDATE_COMPLETE 0x03 +#define HCI_EV_LE_ENHANCED_CONN_COMPLETE 0x0a + +//vendor cmd to fw +#define HCI_VENDOR_ENABLE_PROFILE_REPORT_COMMAND 0xfc18 +#define HCI_VENDOR_SET_PROFILE_REPORT_COMMAND 0xfc19 +#define HCI_VENDOR_MAILBOX_CMD 0xfc8f +#define HCI_VENDOR_SET_BITPOOL 0xfc51 + +//subcmd to fw +#define HCI_VENDOR_SUB_CMD_WIFI_CHANNEL_AND_BANDWIDTH_CMD 0x11 +#define HCI_VENDOR_SUB_CMD_WIFI_FORCE_TX_POWER_CMD 0x17 +#define HCI_VENDOR_SUB_CMD_BT_ENABLE_IGNORE_WLAN_ACT_CMD 0x1B +#define HCI_VENDOR_SUB_CMD_BT_REPORT_CONN_SCO_INQ_INFO 0x23 +#define HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_STATUS_INFO 0x27 +#define HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_ENABLE 0x28 +#define HCI_VENDOR_SUB_CMD_BT_SET_TXRETRY_REPORT_PARAM 0x29 +#define HCI_VENDOR_SUB_CMD_BT_SET_PTATABLE 0x2A +#define HCI_VENDOR_SUB_CMD_SET_BT_PSD_MODE 0x31 +#define HCI_VENDOR_SUB_CMD_SET_BT_LNA_CONSTRAINT 0x32 +#define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_L 0x40 +#define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_M 0x41 +#define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_H 0x42 +#define HCI_VENDOR_SUB_CMD_RD_REG_REQ 0x43 +#define HCI_VENDOR_SUB_CMD_WR_REG_REQ 0x44 + +#define HCI_EV_VENDOR_SPECIFIC 0xff + +//sub event from fw start +#define HCI_VENDOR_PTA_REPORT_EVENT 0x24 +#define HCI_VENDOR_PTA_AUTO_REPORT_EVENT 0x25 + +//vendor cmd to wifi driver +#define HCI_GRP_VENDOR_SPECIFIC (0x3f << 10) +#define HCI_OP_HCI_EXTENSION_VERSION_NOTIFY (0x0100 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_BT_OPERATION_NOTIFY (0x0102 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_INFO_NOTIFY (0x0106 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_COEX_NOTIFY (0x0107 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_PATCH_VER_NOTIFY (0x0108 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_AFH_MAP_NOTIFY (0x0109 | HCI_GRP_VENDOR_SPECIFIC) +#define HCI_OP_HCI_BT_REGISTER_VALUE_NOTIFY (0x010a | HCI_GRP_VENDOR_SPECIFIC) + +//bt info reason to wifi +#define HOST_RESPONSE 0 //Host response when receive the BT Info Control Event +#define POLLING_RESPONSE 1 //The BT Info response for polling by BT firmware. +#define AUTO_REPORT 2 //BT auto report by BT firmware. +#define STACK_REPORT_WHILE_DEVICE_D2 3 //Stack report when BT firmware is under power save state(ex:D2) + +// vendor event from wifi +#define RTK_HS_EXTENSION_EVENT_WIFI_SCAN 0x01 +#define RTK_HS_EXTENSION_EVENT_RADIO_STATUS_NOTIFY 0x02 +#define RTK_HS_EXTENSION_EVENT_HCI_BT_INFO_CONTROL 0x03 +#define RTK_HS_EXTENSION_EVENT_HCI_BT_COEX_CONTROL 0x04 + +//op code from wifi +#define BT_PATCH_VERSION_QUERY 0x00 +#define IGNORE_WLAN_ACTIVE_CONTROL 0x01 +#define LNA_CONSTRAIN_CONTROL 0x02 +#define BT_POWER_DECREASE_CONTROL 0x03 +#define BT_PSD_MODE_CONTROL 0x04 +#define WIFI_BW_CHNL_NOTIFY 0x05 +#define QUERY_BT_AFH_MAP 0x06 +#define BT_REGISTER_ACCESS 0x07 + +//bt operation to notify +#define BT_OPCODE_NONE 0 +#define BT_OPCODE_INQUIRY_START 1 +#define BT_OPCODE_INQUIRY_END 2 +#define BT_OPCODE_PAGE_START 3 +#define BT_OPCODE_PAGE_SUCCESS_END 4 +#define BT_OPCODE_PAGE_UNSUCCESS_END 5 +#define BT_OPCODE_PAIR_START 6 +#define BT_OPCODE_PAIR_END 7 +#define BT_OPCODE_ENABLE_BT 8 +#define BT_OPCODE_DISABLE_BT 9 + +#define HCI_EXTENSION_VERSION 0x0004 +#define HCI_CMD_PREAMBLE_SIZE 3 +#define PAN_PACKET_COUNT 5 + +#define STREAM_TO_UINT16(u16, p) {u16 = ((uint16_t)(*(p)) + (((uint16_t)(*((p) + 1))) << 8)); (p) += 2;} +#define UINT16_TO_STREAM(p, u16) {*(p)++ = (uint8_t)(u16); *(p)++ = (uint8_t)((u16) >> 8);} + +#define PSM_SDP 0x0001 +#define PSM_RFCOMM 0x0003 +#define PSM_PAN 0x000F +#define PSM_HID 0x0011 +#define PSM_HID_INT 0x0013 +#define PSM_AVCTP 0x0017 +#define PSM_AVDTP 0x0019 +#define PSM_FTP 0x1001 +#define PSM_BIP 0x1003 +#define PSM_OPP 0x1015 +//--add more if needed--// + +enum { + profile_sco = 0, + profile_hid = 1, + profile_a2dp = 2, + profile_pan = 3, + profile_hid_interval = 4, + profile_hogp = 5, + profile_voice = 6, + profile_sink = 7, + profile_max = 8 +}; + +#define A2DP_SIGNAL 0x01 +#define A2DP_MEDIA 0x02 +//profile info data +typedef struct { + struct list_head list; + uint16_t handle; + uint16_t psm; + uint16_t dcid; + uint16_t scid; + uint8_t profile_index; + uint8_t flags; +} rtk_prof_info, *prtk_prof_info; + +//profile info for each connection +typedef struct rtl_hci_conn { + struct list_head list; + uint16_t handle; + uint8_t type; // 0:l2cap, 1:sco/esco, 2:le + uint8_t profile_bitmap; + int8_t profile_refcount[8]; +} rtk_conn_prof, *prtk_conn_prof; + +#ifdef RTB_SOFTWARE_MAILBOX + +struct rtl_btinfo { + u8 cmd; + u8 len; + u8 data[6]; +}; +#define RTL_BTINFO_LEN (sizeof(struct rtl_btinfo)) +/* typedef struct { + * uint8_t cmd_index; + * uint8_t cmd_length; + * uint8_t link_status; + * uint8_t retry_cnt; + * uint8_t rssi; + * uint8_t mailbox_info; + * uint16_t acl_throughput; + * } hci_linkstatus_report; */ + +typedef struct { + uint8_t type; + uint32_t offset; + uint32_t value; +} hci_mailbox_register; + +struct rtl_btinfo_ctl { + uint8_t polling_enable; + uint8_t polling_time; + uint8_t autoreport_enable; +}; +#endif /* RTB_SOFTWARE_MAILBOX */ + +#define MAX_LEN_OF_HCI_EV 32 +#define NUM_RTL_HCI_EV 32 +struct rtl_hci_ev { + __u8 data[MAX_LEN_OF_HCI_EV]; + __u16 len; + struct list_head list; +}; + +#define L2_MAX_SUBSEC_LEN 128 +#define L2_MAX_PKTS 16 +struct rtl_l2_buff { + __u8 data[L2_MAX_SUBSEC_LEN]; + __u16 len; + __u16 out; + struct list_head list; +}; + +struct rtl_coex_struct { + struct list_head conn_hash; //hash for connections + struct list_head profile_list; //hash for profile info + struct hci_dev *hdev; +#ifdef RTB_SOFTWARE_MAILBOX + struct socket *udpsock; + struct sockaddr_in addr; + struct sockaddr_in wifi_addr; + struct timer_list polling_timer; +#endif + struct timer_list a2dp_count_timer; + struct timer_list pan_count_timer; + struct timer_list hogp_count_timer; +#ifdef RTB_SOFTWARE_MAILBOX + struct workqueue_struct *sock_wq; + struct delayed_work sock_work; +#endif + struct workqueue_struct *fw_wq; + struct delayed_work fw_work; + struct delayed_work l2_work; +#ifdef RTB_SOFTWARE_MAILBOX + struct sock *sk; +#endif + struct urb *urb; + spinlock_t spin_lock_sock; + spinlock_t spin_lock_profile; + uint32_t a2dp_packet_count; + uint32_t pan_packet_count; + uint32_t hogp_packet_count; + uint32_t voice_packet_count; + uint8_t profile_bitmap; + uint8_t profile_status; + int8_t profile_refcount[8]; + uint8_t ispairing; + uint8_t isinquirying; + uint8_t ispaging; +#ifdef RTB_SOFTWARE_MAILBOX + uint8_t wifi_state; + uint8_t autoreport; + uint8_t polling_enable; + uint8_t polling_interval; + uint8_t piconet_id; + uint8_t mode; + uint8_t afh_map[10]; +#endif + uint16_t hci_reversion; + uint16_t lmp_subversion; +#ifdef RTB_SOFTWARE_MAILBOX + uint8_t wifi_on; + uint8_t sock_open; +#endif + unsigned long cmd_last_tx; + + /* hci ev buff */ + struct list_head ev_used_list; + struct list_head ev_free_list; + + spinlock_t rxlock; + __u8 pkt_type; + __u16 expect; + __u8 *tbuff; + __u16 elen; + __u8 back_buff[HCI_MAX_EVENT_SIZE]; + + /* l2cap rx buff */ + struct list_head l2_used_list; + struct list_head l2_free_list; + + /* buff addr and size */ + spinlock_t buff_lock; + unsigned long pages_addr; + unsigned long buff_size; + +#define RTL_COEX_RUNNING (1 << 0) + unsigned long flags; + +}; + +#ifdef __LITTLE_ENDIAN +struct sbc_frame_hdr { + uint8_t syncword:8; /* Sync word */ + uint8_t subbands:1; /* Subbands */ + uint8_t allocation_method:1; /* Allocation method */ + uint8_t channel_mode:2; /* Channel mode */ + uint8_t blocks:2; /* Blocks */ + uint8_t sampling_frequency:2; /* Sampling frequency */ + uint8_t bitpool:8; /* Bitpool */ + uint8_t crc_check:8; /* CRC check */ +} __attribute__ ((packed)); + +/* NOTE: The code is copied from pa. + * only the bit field in 8-bit is affected by endian, not the 16-bit or 32-bit. + * why? + */ +struct rtp_header { + unsigned cc:4; + unsigned x:1; + unsigned p:1; + unsigned v:2; + + unsigned pt:7; + unsigned m:1; + + uint16_t sequence_number; + uint32_t timestamp; + uint32_t ssrc; + uint32_t csrc[0]; +} __attribute__ ((packed)); + +#else +/* big endian */ +struct sbc_frame_hdr { + uint8_t syncword:8; /* Sync word */ + uint8_t sampling_frequency:2; /* Sampling frequency */ + uint8_t blocks:2; /* Blocks */ + uint8_t channel_mode:2; /* Channel mode */ + uint8_t allocation_method:1; /* Allocation method */ + uint8_t subbands:1; /* Subbands */ + uint8_t bitpool:8; /* Bitpool */ + uint8_t crc_check:8; /* CRC check */ +} __attribute__ ((packed)); + +struct rtp_header { + unsigned v:2; + unsigned p:1; + unsigned x:1; + unsigned cc:4; + + unsigned m:1; + unsigned pt:7; + + uint16_t sequence_number; + uint32_t timestamp; + uint32_t ssrc; + uint32_t csrc[0]; +} __attribute__ ((packed)); +#endif /* __LITTLE_ENDIAN */ + +void rtk_btcoex_parse_event(uint8_t *buffer, int count); +void rtk_btcoex_parse_cmd(uint8_t *buffer, int count); +void rtk_btcoex_parse_l2cap_data_tx(uint8_t *buffer, int count); +void rtk_btcoex_parse_l2cap_data_rx(uint8_t *buffer, int count); + +void rtk_btcoex_open(struct hci_dev *hdev); +void rtk_btcoex_close(void); +void rtk_btcoex_probe(struct hci_dev *hdev); +void rtk_btcoex_init(void); +void rtk_btcoex_exit(void); diff --git a/drivers/bluetooth/rtk_misc.c b/drivers/bluetooth/rtk_misc.c new file mode 100644 index 0000000000000..54684de24212e --- /dev/null +++ b/drivers/bluetooth/rtk_misc.c @@ -0,0 +1,2108 @@ +/* + * + * Realtek Bluetooth USB download firmware driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32) +#include +#endif + +#include +#include +#include +#include +#include + +#include "rtk_misc.h" + +#include +#include +#define BDADDR_STRING_LEN 17 +#define BDADDR_FILE "/opt/bdaddr" + +struct cfg_list_item { + struct list_head list; + u16 offset; + u8 len; + u8 data[0]; +}; + +static struct list_head list_configs; + +#define EXTRA_CONFIG_FILE "/opt/rtk_btconfig.txt" +static struct list_head list_extracfgs; + +#define CMD_CMP_EVT 0x0e +#define PKT_LEN 300 +#define MSG_TO 1000 //us +#define PATCH_SEG_MAX 252 +#define DATA_END 0x80 +#define DOWNLOAD_OPCODE 0xfc20 +/* This command is used only for TV patch + * if host is going to suspend state, it should send this command to + * Controller. Controller will scan the special advertising packet + * which indicates Controller to wake up host */ +#define STARTSCAN_OPCODE 0xfc28 +#define TRUE 1 +#define FALSE 0 +#define CMD_HDR_LEN sizeof(struct hci_command_hdr) +#define EVT_HDR_LEN sizeof(struct hci_event_hdr) +#define CMD_CMP_LEN sizeof(struct hci_ev_cmd_complete) + +#define HCI_CMD_READ_BD_ADDR 0x1009 +#define HCI_VENDOR_CHANGE_BDRATE 0xfc17 +#define HCI_VENDOR_READ_RTK_ROM_VERISION 0xfc6d +#define HCI_VENDOR_READ_LMP_VERISION 0x1001 + +#define ROM_LMP_NONE 0x0000 +#define ROM_LMP_8723a 0x1200 +#define ROM_LMP_8723b 0x8723 +#define ROM_LMP_8821a 0X8821 +#define ROM_LMP_8761a 0X8761 +#define ROM_LMP_8822b 0X8822 +#define ROM_LMP_8852a 0x8852 + +struct rtk_eversion_evt { + uint8_t status; + uint8_t version; +} __attribute__ ((packed)); + +struct rtk_epatch_entry { + uint16_t chipID; + uint16_t patch_length; + uint32_t start_offset; +} __attribute__ ((packed)); + +struct rtk_epatch { + uint8_t signature[8]; + uint32_t fw_version; + uint16_t number_of_total_patch; + struct rtk_epatch_entry entry[0]; +} __attribute__ ((packed)); + +struct rtk_extension_entry { + uint8_t opcode; + uint8_t length; + uint8_t *data; +} __attribute__ ((packed)); + +//signature: Realtech +const uint8_t RTK_EPATCH_SIGNATURE[8] = + { 0x52, 0x65, 0x61, 0x6C, 0x74, 0x65, 0x63, 0x68 }; +//Extension Section IGNATURE:0x77FD0451 +const uint8_t Extension_Section_SIGNATURE[4] = { 0x51, 0x04, 0xFD, 0x77 }; + +uint16_t project_id[] = { + ROM_LMP_8723a, + ROM_LMP_8723b, + ROM_LMP_8821a, + ROM_LMP_8761a, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8822b, + ROM_LMP_8723b, /* RTL8723DU */ + ROM_LMP_8821a, /* RTL8821CU */ + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8822b, /* RTL8822CU */ + ROM_LMP_8761a, /* index 14 for 8761BU */ + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8852a, /* index 18 for 8852AU */ + ROM_LMP_8723b, /* index 19 for 8723FU */ + ROM_LMP_8852a, /* index 20 for 8852BU */ + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_NONE, + ROM_LMP_8852a, /* index 25 for 8852CU */ +}; + +enum rtk_endpoit { + CTRL_EP = 0, + INTR_EP = 1, + BULK_EP = 2, + ISOC_EP = 3 +}; + +/* software id */ +#define RTLPREVIOUS 0x00 +#define RTL8822BU 0x70 +#define RTL8723DU 0x71 +#define RTL8821CU 0x72 +#define RTL8822CU 0x73 +#define RTL8761BU 0x74 +#define RTL8852AU 0x75 +#define RTL8723FU 0x76 +#define RTL8852BU 0x77 +#define RTL8852CU 0x78 + +typedef struct { + uint16_t prod_id; + uint16_t lmp_sub; + char * mp_patch_name; + char * patch_name; + char * config_name; + u8 chip_type; +} patch_info; + +typedef struct { + struct list_head list_node; + struct usb_interface *intf; + struct usb_device *udev; + patch_info *patch_entry; +} dev_data; + +typedef struct { + dev_data *dev_entry; + int pipe_in, pipe_out; + uint8_t *send_pkt; + uint8_t *rcv_pkt; + struct hci_command_hdr *cmd_hdr; + struct hci_event_hdr *evt_hdr; + struct hci_ev_cmd_complete *cmd_cmp; + uint8_t *req_para, *rsp_para; + uint8_t *fw_data; + int pkt_len, fw_len; +} xchange_data; + +typedef struct { + uint8_t index; + uint8_t data[PATCH_SEG_MAX]; +} __attribute__ ((packed)) download_cp; + +typedef struct { + uint8_t status; + uint8_t index; +} __attribute__ ((packed)) download_rp; + +#define RTK_VENDOR_CONFIG_MAGIC 0x8723ab55 +const u8 cfg_magic[4] = { 0x55, 0xab, 0x23, 0x87 }; +struct rtk_bt_vendor_config_entry { + uint16_t offset; + uint8_t entry_len; + uint8_t entry_data[0]; +} __attribute__ ((packed)); + +struct rtk_bt_vendor_config { + uint32_t signature; + uint16_t data_len; + struct rtk_bt_vendor_config_entry entry[0]; +} __attribute__ ((packed)); +#define BT_CONFIG_HDRLEN sizeof(struct rtk_bt_vendor_config) + +static uint8_t gEVersion = 0xFF; + +static dev_data *dev_data_find(struct usb_interface *intf); +static patch_info *get_patch_entry(struct usb_device *udev); +static int load_firmware(dev_data * dev_entry, uint8_t ** buff); +static void init_xdata(xchange_data * xdata, dev_data * dev_entry); +static int check_fw_version(xchange_data * xdata); +static int download_data(xchange_data * xdata); +static int send_hci_cmd(xchange_data * xdata); +static int rcv_hci_evt(xchange_data * xdata); +static uint8_t rtk_get_eversion(dev_data * dev_entry); + +static patch_info fw_patch_table[] = { +/* { pid, lmp_sub, mp_fw_name, fw_name, config_name, chip_type } */ + {0x1724, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* RTL8723A */ + {0x8723, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE */ + {0xA723, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE for LI */ + {0x0723, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE */ + {0x3394, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AE for Azurewave */ + + {0x0724, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + {0x8725, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + {0x872A, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + {0x872B, 0x1200, "mp_rtl8723a_fw", "rtl8723a_fw", "rtl8723a_config", RTLPREVIOUS}, /* 8723AU */ + + {0xb720, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BU */ + {0xb72A, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BU */ + {0xb728, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for LC */ + {0xb723, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb72B, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb001, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for HP */ + {0xb002, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb003, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb004, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + {0xb005, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE */ + + {0x3410, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Azurewave */ + {0x3416, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Azurewave */ + {0x3459, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Azurewave */ + {0xE085, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Foxconn */ + {0xE08B, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Foxconn */ + {0xE09E, 0x8723, "mp_rtl8723b_fw", "rtl8723b_fw", "rtl8723b_config", RTLPREVIOUS}, /* RTL8723BE for Foxconn */ + + {0xA761, 0x8761, "mp_rtl8761a_fw", "rtl8761au_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU only */ + {0x818B, 0x8761, "mp_rtl8761a_fw", "rtl8761aw_fw", "rtl8761aw_config", RTLPREVIOUS}, /* RTL8761AW + 8192EU */ + {0x818C, 0x8761, "mp_rtl8761a_fw", "rtl8761aw_fw", "rtl8761aw_config", RTLPREVIOUS}, /* RTL8761AW + 8192EU */ + {0x8760, 0x8761, "mp_rtl8761a_fw", "rtl8761au8192ee_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8192EE */ + {0xB761, 0x8761, "mp_rtl8761a_fw", "rtl8761au_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AUV only */ + {0x8761, 0x8761, "mp_rtl8761a_fw", "rtl8761au8192ee_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8192EE for LI */ + {0x8A60, 0x8761, "mp_rtl8761a_fw", "rtl8761au8812ae_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8812AE */ + {0x3527, 0x8761, "mp_rtl8761a_fw", "rtl8761au8192ee_fw", "rtl8761a_config", RTLPREVIOUS}, /* RTL8761AU + 8814AE */ + + {0x8821, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x0821, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x0823, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AU */ + {0x3414, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x3458, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x3461, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + {0x3462, 0x8821, "mp_rtl8821a_fw", "rtl8821a_fw", "rtl8821a_config", RTLPREVIOUS}, /* RTL8821AE */ + + {0xb82c, 0x8822, "mp_rtl8822bu_fw", "rtl8822bu_fw", "rtl8822bu_config", RTL8822BU}, /* RTL8822BU */ + + {0xd720, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0xd723, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0xd739, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0xb009, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU */ + {0x0231, 0x8723, "mp_rtl8723du_fw", "rtl8723du_fw", "rtl8723du_config", RTL8723DU}, /* RTL8723DU for LiteOn */ + + {0xb820, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CU */ + {0xc820, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CU */ + {0xc821, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc823, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc824, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc825, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc827, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc025, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc024, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc030, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xb00a, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xb00e, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0xc032, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0x4000, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for LiteOn */ + {0x4001, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for LiteOn */ + {0x3529, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3530, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3532, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3533, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3538, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3539, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3558, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3559, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3581, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for Azurewave */ + {0x3540, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE */ + {0x3541, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for GSD */ + {0x3543, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CE for GSD */ + {0xc80c, 0x8821, "mp_rtl8821cu_fw", "rtl8821cu_fw", "rtl8821cu_config", RTL8821CU}, /* RTL8821CUH */ + + {0xc82c, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CU */ + {0xc82e, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CU */ + {0xc81d, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CU */ + {0xd820, 0x8822, "mp_rtl8821du_fw", "rtl8821du_fw", "rtl8821du_config", RTL8822CU}, /* RTL8821DU */ + + {0xc822, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc82b, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xb00c, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xb00d, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc123, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc126, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc127, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc128, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc129, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc131, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc136, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3549, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for Azurewave */ + {0x3548, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for Azurewave */ + {0xc125, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x4005, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for LiteOn */ + {0x3051, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE for LiteOn */ + {0x18ef, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x161f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3053, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc547, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3553, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0x3555, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE */ + {0xc82f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE-VS */ + {0xc02f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE-VS */ + {0xc03f, 0x8822, "mp_rtl8822cu_fw", "rtl8822cu_fw", "rtl8822cu_config", RTL8822CU}, /* RTL8822CE-VS */ + + {0x8771, 0x8761, "mp_rtl8761b_fw", "rtl8761bu_fw", "rtl8761bu_config", RTL8761BU}, /* RTL8761BU only */ + {0xa725, 0x8761, "mp_rtl8761b_fw", "rtl8725au_fw", "rtl8725au_config", RTL8761BU}, /* RTL8725AU */ + {0xa72A, 0x8761, "mp_rtl8761b_fw", "rtl8725au_fw", "rtl8725au_config", RTL8761BU}, /* RTL8725AU BT only */ + + {0x885a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AU */ + {0x8852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xa852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x2852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x385a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x1852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x4852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x4006, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3561, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3562, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x588a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x589a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x590a, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc125, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xe852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + //{0xb852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc852, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc549, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0xc127, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + {0x3565, 0x8852, "mp_rtl8852au_fw", "rtl8852au_fw", "rtl8852au_config", RTL8852AU}, /* RTL8852AE */ + + {0xb733, 0x8723, "mp_rtl8723fu_fw", "rtl8723fu_fw", "rtl8723fu_config", RTL8723FU}, /* RTL8723FU */ + {0xb73a, 0x8723, "mp_rtl8723fu_fw", "rtl8723fu_fw", "rtl8723fu_config", RTL8723FU}, /* RTL8723FU */ + {0xf72b, 0x8723, "mp_rtl8723fu_fw", "rtl8723fu_fw", "rtl8723fu_config", RTL8723FU}, /* RTL8723FU */ + + {0x8851, 0x8852, "mp_rtl8851au_fw", "rtl8851au_fw", "rtl8851au_config", RTL8852BU}, /* RTL8851AU */ + {0xa85b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BU */ + {0xb852, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BU */ + {0xb85b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb85c, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x3571, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x3570, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x3572, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x4b06, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x885b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x886b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x887b, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xc559, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb052, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb152, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0xb252, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x4853, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + {0x1670, 0x8852, "mp_rtl8852bu_fw", "rtl8852bu_fw", "rtl8852bu_config", RTL8852BU}, /* RTL8852BE */ + + {0xc85a, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CU */ + {0x0852, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x5852, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0xc85c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x885c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x886c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x887c, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + {0x4007, 0x8852, "mp_rtl8852cu_fw", "rtl8852cu_fw", "rtl8852cu_config", RTL8852CU}, /* RTL8852CE */ + +/* NOTE: must append patch entries above the null entry */ + {0, 0, NULL, NULL, NULL, 0} +}; + +static LIST_HEAD(dev_data_list); + +void util_hexdump(const u8 *buf, size_t len) +{ + static const char hexdigits[] = "0123456789abcdef"; + char str[16 * 3]; + size_t i; + + if (!buf || !len) + return; + + for (i = 0; i < len; i++) { + str[((i % 16) * 3)] = hexdigits[buf[i] >> 4]; + str[((i % 16) * 3) + 1] = hexdigits[buf[i] & 0xf]; + str[((i % 16) * 3) + 2] = ' '; + if ((i + 1) % 16 == 0) { + str[16 * 3 - 1] = '\0'; + RTKBT_DBG("%s", str); + } + } + + if (i % 16 > 0) { + str[(i % 16) * 3 - 1] = '\0'; + RTKBT_DBG("%s", str); + } +} + +#if defined RTKBT_SWITCH_PATCH || defined RTKBT_TV_POWERON_WHITELIST +int __rtk_send_hci_cmd(struct usb_device *udev, u8 *buf, u16 size) +{ + int result; + unsigned int pipe = usb_sndctrlpipe(udev, 0); + + result = usb_control_msg(udev, pipe, 0, USB_TYPE_CLASS, 0, 0, + buf, size, 1000); /* 1000 msecs */ + + if (result < 0) + RTKBT_ERR("%s: Couldn't send hci cmd, err %d", + __func__, result); + + return result; +} + +int __rtk_recv_hci_evt(struct usb_device *udev, u8 *buf, u8 len, u16 opcode) +{ + int recv_length = 0; + int result = 0; + int i; + unsigned int pipe = usb_rcvintpipe(udev, 1); + struct hci_event_hdr *hdr; + struct hci_ev_cmd_complete *cmd_cmpl; + + if (len < sizeof(*hdr) + sizeof(*cmd_cmpl)) { + RTKBT_ERR("%s: Invalid buf length %u", __func__, len); + return -1; + } + + while (1) { + for (i = 0; i < 5; i++) { + result = usb_interrupt_msg(udev, pipe, + (void *)buf, PKT_LEN, + &recv_length, MSG_TO); + if (result >= 0) + break; + } + + if (result < 0) { + RTKBT_ERR("%s; Couldn't receive HCI event, err %d", + __func__, result); + return result; + } + + /* Ignore the event which is not command complete event */ + if (recv_length < sizeof(*hdr) + sizeof(*cmd_cmpl)) + continue; + + hdr = (struct hci_event_hdr *)buf; + cmd_cmpl = (struct hci_ev_cmd_complete *)(buf + sizeof(*hdr)); + if (hdr->evt == 0x0e) { + if (opcode == cmd_cmpl->opcode) + return recv_length; + } + } +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0) +static inline struct inode *file_inode(const struct file *f) +{ + return f->f_path.dentry->d_inode; +} +#endif + +static int config_lists_init(void) +{ + INIT_LIST_HEAD(&list_configs); + INIT_LIST_HEAD(&list_extracfgs); + + return 0; +} + +static void config_lists_free(void) +{ + struct list_head *iter; + struct list_head *tmp; + struct list_head *head; + struct cfg_list_item *n; + + if (!list_empty(&list_extracfgs)) + list_splice_tail(&list_extracfgs, &list_configs); + head = &list_configs; + list_for_each_safe(iter, tmp, head) { + n = list_entry(iter, struct cfg_list_item, list); + if (n) { + list_del(&n->list); + kfree(n); + } + } + + INIT_LIST_HEAD(&list_configs); + INIT_LIST_HEAD(&list_extracfgs); +} + +static void line_process(char *buf, int len) +{ + char *argv[32]; + int argc = 0; + unsigned long offset; + u8 l; + u8 i = 0; + char *ptr = buf; + char *head = buf; + struct cfg_list_item *item; + + while ((ptr = strsep(&head, ", \t")) != NULL) { + if (!ptr[0]) + continue; + argv[argc++] = ptr; + if (argc >= 32) { + RTKBT_WARN("%s: Config item is too long", __func__); + break; + } + } + + if (argc < 4) { + RTKBT_WARN("%s: Invalid Config item, ignore", __func__); + return; + } + + offset = simple_strtoul(argv[0], NULL, 16); + offset = offset | (simple_strtoul(argv[1], NULL, 16) << 8); + l = (u8)simple_strtoul(argv[2], NULL, 16); + if (l != (u8)(argc - 3)) { + RTKBT_ERR("invalid len %u", l); + return; + } + + item = kzalloc(sizeof(*item) + l, GFP_KERNEL); + if (!item) { + RTKBT_WARN("%s: Cannot alloc mem for item, %04lx, %u", __func__, + offset, l); + return; + } + + item->offset = (u16)offset; + item->len = l; + for (i = 0; i < l; i++) + item->data[i] = (u8)simple_strtoul(argv[3 + i], NULL, 16); + list_add_tail(&item->list, &list_extracfgs); +} + +static void config_process(u8 *buff, int len) +{ + char *head = (void *)buff; + char *ptr = (void *)buff; + + while ((ptr = strsep(&head, "\n\r")) != NULL) { + if (!ptr[0]) + continue; + line_process(ptr, strlen(ptr) + 1); + } +} + +static void config_file_proc(const char *path) +{ + int size; + int rc; + struct file *file; + u8 tbuf[256]; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + loff_t pos = 0; +#endif + + file = filp_open(path, O_RDONLY, 0); + if (IS_ERR(file)) + return; + + if (!S_ISREG(file_inode(file)->i_mode)) + return; + size = i_size_read(file_inode(file)); + if (size <= 0) + return; + + memset(tbuf, 0, sizeof(tbuf)); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + rc = kernel_read(file, tbuf, size, &pos); +#else + rc = kernel_read(file, 0, tbuf, size); +#endif + fput(file); + if (rc != size) { + if (rc >= 0) + rc = -EIO; + return; + } + + tbuf[rc++] = '\n'; + tbuf[rc++] = '\0'; + config_process(tbuf, rc); +} + +int patch_add(struct usb_interface *intf) +{ + dev_data *dev_entry; + struct usb_device *udev; + + RTKBT_DBG("patch_add"); + dev_entry = dev_data_find(intf); + if (NULL != dev_entry) { + return -1; + } + + udev = interface_to_usbdev(intf); +#ifdef BTUSB_RPM + RTKBT_DBG("auto suspend is enabled"); + usb_enable_autosuspend(udev); + pm_runtime_set_autosuspend_delay(&(udev->dev), 2000); +#else + RTKBT_DBG("auto suspend is disabled"); + usb_disable_autosuspend(udev); +#endif + + dev_entry = kzalloc(sizeof(dev_data), GFP_KERNEL); + dev_entry->intf = intf; + dev_entry->udev = udev; + dev_entry->patch_entry = get_patch_entry(udev); + if (NULL == dev_entry->patch_entry) { + kfree(dev_entry); + return -1; + } + list_add(&dev_entry->list_node, &dev_data_list); + + /* Should reset the gEVersion to 0xff, otherwise the stored gEVersion + * would cause rtk_get_eversion() returning previous gEVersion if + * change to different ECO chip. + * This would cause downloading wrong patch, and the controller can't + * work. */ + RTKBT_DBG("%s: Reset gEVersion to 0xff", __func__); + gEVersion = 0xff; + + return 0; +} + +void patch_remove(struct usb_interface *intf) +{ + dev_data *dev_entry; + struct usb_device *udev; + + udev = interface_to_usbdev(intf); +#ifdef BTUSB_RPM + usb_disable_autosuspend(udev); +#endif + + dev_entry = dev_data_find(intf); + if (NULL == dev_entry) { + return; + } + + RTKBT_DBG("patch_remove"); + list_del(&dev_entry->list_node); + kfree(dev_entry); +} + +static int send_reset_command(xchange_data *xdata) +{ + int ret_val; + + RTKBT_DBG("HCI reset."); + + xdata->cmd_hdr->opcode = cpu_to_le16(HCI_OP_RESET); + xdata->cmd_hdr->plen = 0; + xdata->pkt_len = CMD_HDR_LEN; + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + RTKBT_ERR("failed to send hci cmd."); + return ret_val; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + RTKBT_ERR("failed to recv hci event."); + return ret_val; + } + + return 0; +} + +static inline int get_max_patch_size(u8 chip_type) +{ + int max_patch_size = 0; + + switch (chip_type) { + case RTLPREVIOUS: + max_patch_size = 24 * 1024; + break; + case RTL8822BU: + max_patch_size = 25 * 1024; + break; + case RTL8723DU: + case RTL8822CU: + case RTL8761BU: + case RTL8821CU: + max_patch_size = 40 * 1024; + break; + case RTL8852AU: + max_patch_size = 0x114D0 + 529; /* 69.2KB */ + break; + case RTL8723FU: + max_patch_size = 0xC4Cf + 529; /* 49.2KB */ + break; + case RTL8852BU: + max_patch_size = 0x104D0 + 529; /* 65KB */ + break; + case RTL8852CU: + max_patch_size = 0x130D0 + 529; /* 76.2KB */ + break; + default: + max_patch_size = 40 * 1024; + break; + } + + return max_patch_size; +} + +int download_patch(struct usb_interface *intf) +{ + dev_data *dev_entry; + patch_info *pinfo; + xchange_data *xdata = NULL; + uint8_t *fw_buf; + int ret_val; + int max_patch_size = 0; + + RTKBT_DBG("download_patch start"); + dev_entry = dev_data_find(intf); + if (NULL == dev_entry) { + ret_val = -1; + RTKBT_ERR("NULL == dev_entry"); + goto patch_end; + } + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (NULL == xdata) { + ret_val = -1; + RTKBT_DBG("NULL == xdata"); + goto patch_end; + } + + init_xdata(xdata, dev_entry); + + ret_val = check_fw_version(xdata); + if (ret_val < 0) { + RTKBT_ERR("Failed to get Local Version Information"); + goto patch_end; + + } else if (ret_val > 0) { + RTKBT_DBG("Firmware already exists"); + /* Patch alread exists, just return */ + if (gEVersion == 0xff) { + RTKBT_DBG("global_version is not set, get it!"); + gEVersion = rtk_get_eversion(dev_entry); + } + goto patch_end; + } + + xdata->fw_len = load_firmware(dev_entry, &xdata->fw_data); + if (xdata->fw_len <= 0) { + RTKBT_ERR("load firmware failed!"); + ret_val = -1; + goto patch_end; + } + + fw_buf = xdata->fw_data; + + pinfo = dev_entry->patch_entry; + if (!pinfo) { + RTKBT_ERR("%s: No patch entry", __func__); + ret_val = -1; + goto patch_fail; + } + max_patch_size = get_max_patch_size(pinfo->chip_type); + if (xdata->fw_len > max_patch_size) { + RTKBT_ERR("FW/CONFIG total length larger than allowed %d", + max_patch_size); + ret_val = -1; + goto patch_fail; + } + + ret_val = download_data(xdata); + if (ret_val < 0) { + RTKBT_ERR("download_data failed, err %d", ret_val); + goto patch_fail; + } + + ret_val = check_fw_version(xdata); + if (ret_val <= 0) { + RTKBT_ERR("%s: Read Local Version Info failure after download", + __func__); + ret_val = -1; + goto patch_fail; + } + + ret_val = 0; +patch_fail: + kfree(fw_buf); +patch_end: + if (xdata != NULL) { + if (xdata->send_pkt) + kfree(xdata->send_pkt); + if (xdata->rcv_pkt) + kfree(xdata->rcv_pkt); + kfree(xdata); + } + RTKBT_DBG("Rtk patch end %d", ret_val); + return ret_val; +} + +#ifdef RTKBT_SWITCH_PATCH +/* @return: + * -1: error + * 0: download patch successfully + * >0: patch already exists */ +int download_lps_patch(struct usb_interface *intf) +{ + dev_data *dev_entry; + xchange_data *xdata = NULL; + uint8_t *fw_buf; + int result; + char name1[64]; + char *origin_name1; + char name2[64]; + char *origin_name2; + + RTKBT_DBG("Download LPS Patch start"); + dev_entry = dev_data_find(intf); + if (!dev_entry) { + RTKBT_ERR("No Patch found"); + return -1; + } + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (!xdata) { + RTKBT_ERR("Couldn't alloc xdata"); + return -1; + } + + init_xdata(xdata, dev_entry); + + result = check_fw_version(xdata); + if (result < 0) { + RTKBT_ERR("Failed to get Local Version Information"); + goto patch_end; + + } else if (result > 0) { + RTKBT_DBG("Firmware already exists"); + /* Patch alread exists, just return */ + if (gEVersion == 0xff) { + RTKBT_DBG("global_version is not set, get it!"); + gEVersion = rtk_get_eversion(dev_entry); + } + goto patch_end; + } + + origin_name1 = dev_entry->patch_entry->patch_name; + origin_name2 = dev_entry->patch_entry->config_name; + snprintf(name1, sizeof(name1), "lps_%s", origin_name1); + snprintf(name2, sizeof(name2), "lps_%s", origin_name2); + dev_entry->patch_entry->patch_name = name1; + dev_entry->patch_entry->config_name = name2; + RTKBT_INFO("Loading %s and %s", name1, name2); + xdata->fw_len = load_firmware(dev_entry, &xdata->fw_data); + dev_entry->patch_entry->patch_name = origin_name1; + dev_entry->patch_entry->config_name = origin_name2; + if (xdata->fw_len <= 0) { + result = -1; + RTKBT_ERR("load firmware failed!"); + goto patch_end; + } + + fw_buf = xdata->fw_data; + + pinfo = dev_entry->patch_entry; + if (!pinfo) { + RTKBT_ERR("%s: No patch entry", __func__); + result = -1; + goto patch_fail; + } + max_patch_size = get_max_patch_size(pinfo->chip_type); + if (xdata->fw_len > max_patch_size) { + result = -1; + RTKBT_ERR("FW/CONFIG total length larger than allowed %d", + max_patch_size); + goto patch_fail; + } + + result = download_data(xdata); + if (result < 0) { + RTKBT_ERR("download_data failed, err %d", result); + goto patch_fail; + } + + result = check_fw_version(xdata); + if (result <= 0) { + RTKBT_ERR("%s: Read Local Version Info failure after download", + __func__); + result = -1; + goto patch_fail; + } + + result = 0; + +patch_fail: + kfree(fw_buf); +patch_end: + if (xdata->send_pkt) + kfree(xdata->send_pkt); + if (xdata->rcv_pkt) + kfree(xdata->rcv_pkt); + kfree(xdata); + RTKBT_DBG("Download LPS Patch end %d", result); + + return result; +} +#endif + +int set_scan(struct usb_interface *intf) +{ + dev_data *dev_entry; + xchange_data *xdata = NULL; + int result; + + RTKBT_DBG("%s", __func__); + dev_entry = dev_data_find(intf); + if (!dev_entry) + return -1; + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (!xdata) { + RTKBT_ERR("Could not alloc xdata"); + return -1; + } + + init_xdata(xdata, dev_entry); + + if ( !xdata->send_pkt || !xdata->rcv_pkt ){ + result = -1; + goto end; + } + + xdata->cmd_hdr->opcode = cpu_to_le16(STARTSCAN_OPCODE); + xdata->cmd_hdr->plen = 1; + xdata->pkt_len = CMD_HDR_LEN + 1; + xdata->send_pkt[CMD_HDR_LEN] = 1; + + result = send_hci_cmd(xdata); + if (result < 0) + goto end; + + result = rcv_hci_evt(xdata); +end: + kfree(xdata->send_pkt); + kfree(xdata->rcv_pkt); + kfree(xdata); + + RTKBT_DBG("%s done", __func__); + + return result; +} + +dev_data *dev_data_find(struct usb_interface * intf) +{ + dev_data *dev_entry; + + list_for_each_entry(dev_entry, &dev_data_list, list_node) { + if (dev_entry->intf == intf) { + patch_info *patch = dev_entry->patch_entry; + if (!patch) + return NULL; + + RTKBT_INFO("chip type value: 0x%02x", patch->chip_type); + return dev_entry; + } + } + + return NULL; +} + +patch_info *get_patch_entry(struct usb_device * udev) +{ + patch_info *patch_entry; + uint16_t pid; + + patch_entry = fw_patch_table; + pid = le16_to_cpu(udev->descriptor.idProduct); + RTKBT_DBG("pid = 0x%x", pid); + while (pid != patch_entry->prod_id) { + if (0 == patch_entry->prod_id) { + RTKBT_DBG + ("get_patch_entry =NULL, can not find device pid in patch_table"); + return NULL; //break; + } + patch_entry++; + } + + return patch_entry; +} + +static int is_mac(u8 chip_type, u16 offset) +{ + int result = 0; + + switch (chip_type) { + case RTL8822BU: + case RTL8723DU: + case RTL8821CU: + if (offset == 0x0044) + return 1; + break; + case RTL8822CU: + case RTL8761BU: + case RTL8852AU: + case RTL8723FU: + case RTL8852BU: + case RTL8852CU: + if (offset == 0x0030) + return 1; + break; + case RTLPREVIOUS: + if (offset == 0x003c) + return 1; + break; + } + + return result; +} + +static uint16_t get_mac_offset(u8 chip_type) +{ + switch (chip_type) { + case RTL8822BU: + case RTL8723DU: + case RTL8821CU: + return 0x0044; + case RTL8822CU: + case RTL8761BU: + case RTL8852AU: + case RTL8723FU: + case RTL8852BU: + case RTL8852CU: + return 0x0030; + case RTLPREVIOUS: + return 0x003c; + default: + return 0x003c; + } +} + +static void merge_configs(struct list_head *head, struct list_head *head2) +{ + struct list_head *epos, *enext; + struct list_head *pos, *next; + struct cfg_list_item *n; + struct cfg_list_item *extra; + + if (!head || !head2) + return; + + if (list_empty(head2)) + return; + + if (list_empty(head)) { + list_splice_tail(head2, head); + INIT_LIST_HEAD(head2); + return; + } + + /* Add or update & replace */ + list_for_each_safe(epos, enext, head2) { + extra = list_entry(epos, struct cfg_list_item, list); + + list_for_each_safe(pos, next, head) { + n = list_entry(pos, struct cfg_list_item, list); + if (extra->offset == n->offset) { + if (extra->len < n->len) { + /* Update the cfg data */ + RTKBT_INFO("Update cfg: ofs %04x len %u", + n->offset, n->len); + memcpy(n->data, extra->data, + extra->len); + list_del(epos); + kfree(extra); + break; + } else { + /* Replace the item */ + list_del(epos); + list_replace_init(pos, epos); + /* free the old item */ + kfree(n); + } + } + + } + + } + + if (list_empty(head2)) + return; + list_for_each_safe(epos, enext, head2) { + extra = list_entry(epos, struct cfg_list_item, list); + RTKBT_INFO("Add new cfg: ofs %04x, len %u", extra->offset, + extra->len); + /* Add the item to list */ + list_del(epos); + list_add_tail(epos, head); + } +} + +int rtk_parse_config_file(u8 *config_buf, int filelen) +{ + struct rtk_bt_vendor_config *config = (void *)config_buf; + u16 config_len = 0, temp = 0; + struct rtk_bt_vendor_config_entry *entry = NULL; + u32 i = 0; + struct cfg_list_item *item; + + if (!config_buf) + return -EINVAL; + + config_len = le16_to_cpu(config->data_len); + entry = config->entry; + + if (le32_to_cpu(config->signature) != RTK_VENDOR_CONFIG_MAGIC) { + RTKBT_ERR("sig magic num %08x, not rtk vendor magic %08x", + config->signature, RTK_VENDOR_CONFIG_MAGIC); + return -1; + } + + if (config_len != filelen - BT_CONFIG_HDRLEN) { + RTKBT_ERR("config length %u is not right %u", config_len, + (u16)(filelen - BT_CONFIG_HDRLEN)); + return -1; + } + + for (i = 0; i < config_len;) { + /* Add config item to list */ + item = kzalloc(sizeof(*item) + entry->entry_len, GFP_KERNEL); + if (item) { + item->offset = le16_to_cpu(entry->offset); + item->len = entry->entry_len; + memcpy(item->data, entry->entry_data, item->len); + list_add_tail(&item->list, &list_configs); + } else { + RTKBT_ERR("Cannot alloc mem for entry %04x, %u", + entry->offset, entry->entry_len); + break; + } + + temp = entry->entry_len + + sizeof(struct rtk_bt_vendor_config_entry); + i += temp; + entry = + (struct rtk_bt_vendor_config_entry *)((uint8_t *) entry + + temp); + } + + return 0;; +} + +uint8_t rtk_get_fw_project_id(uint8_t * p_buf) +{ + uint8_t opcode; + uint8_t len; + uint8_t data = 0; + + do { + opcode = *p_buf; + len = *(p_buf - 1); + if (opcode == 0x00) { + if (len == 1) { + data = *(p_buf - 2); + RTKBT_DBG + ("rtk_get_fw_project_id: opcode %d, len %d, data %d", + opcode, len, data); + break; + } else { + RTKBT_ERR + ("rtk_get_fw_project_id: invalid len %d", + len); + } + } + p_buf -= len + 2; + } while (*p_buf != 0xFF); + + return data; +} + +static void rtk_get_patch_entry(uint8_t * epatch_buf, + struct rtk_epatch_entry *entry) +{ + uint32_t svn_ver; + uint32_t coex_ver; + uint32_t tmp; + uint16_t i; + struct rtk_epatch *epatch_info = (struct rtk_epatch *)epatch_buf; + + epatch_info->number_of_total_patch = + le16_to_cpu(epatch_info->number_of_total_patch); + RTKBT_DBG("fw_version = 0x%x", le32_to_cpu(epatch_info->fw_version)); + RTKBT_DBG("number_of_total_patch = %d", + epatch_info->number_of_total_patch); + + /* get right epatch entry */ + for (i = 0; i < epatch_info->number_of_total_patch; i++) { + if (get_unaligned_le16(epatch_buf + 14 + 2 * i) == + gEVersion + 1) { + entry->chipID = gEVersion + 1; + entry->patch_length = get_unaligned_le16(epatch_buf + + 14 + + 2 * epatch_info->number_of_total_patch + + 2 * i); + entry->start_offset = get_unaligned_le32(epatch_buf + + 14 + + 4 * epatch_info-> number_of_total_patch + + 4 * i); + break; + } + } + + if (i >= epatch_info->number_of_total_patch) { + entry->patch_length = 0; + entry->start_offset = 0; + RTKBT_ERR("No corresponding patch found\n"); + return; + } + + svn_ver = get_unaligned_le32(epatch_buf + + entry->start_offset + + entry->patch_length - 8); + coex_ver = get_unaligned_le32(epatch_buf + + entry->start_offset + + entry->patch_length - 12); + + RTKBT_DBG("chipID %d", entry->chipID); + RTKBT_DBG("patch_length 0x%04x", entry->patch_length); + RTKBT_DBG("start_offset 0x%08x", entry->start_offset); + + RTKBT_DBG("Svn version: %8d", svn_ver); + tmp = ((coex_ver >> 16) & 0x7ff) + (coex_ver >> 27) * 10000; + RTKBT_DBG("Coexistence: BTCOEX_20%06d-%04x", + tmp, (coex_ver & 0xffff)); +} + +int bachk(const char *str) +{ + if (!str) + return -1; + + if (strlen(str) != 17) + return -1; + + while (*str) { + if (!isxdigit(*str++)) + return -1; + + if (!isxdigit(*str++)) + return -1; + + if (*str == 0) + break; + + if (*str++ != ':') + return -1; + } + + return 0; +} + +static int request_bdaddr(u8 *buf) +{ + int size; + int rc; + struct file *file; + u8 tbuf[BDADDR_STRING_LEN + 1]; + char *str; + int i; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + loff_t pos = 0; +#endif + + if (!buf) + return -EINVAL; + + file = filp_open(BDADDR_FILE, O_RDONLY, 0); + if (IS_ERR(file)) + return -ENOENT; + + if (!S_ISREG(file_inode(file)->i_mode)) + return -EINVAL; + size = i_size_read(file_inode(file)); + if (size <= 0) + return -EINVAL; + + if (size > BDADDR_STRING_LEN) + size = BDADDR_STRING_LEN; + + memset(tbuf, 0, sizeof(tbuf)); + RTKBT_INFO("size = %d", size); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + rc = kernel_read(file, tbuf, size, &pos); +#else + rc = kernel_read(file, 0, tbuf, size); +#endif + fput(file); + if (rc != size) { + if (rc >= 0) + rc = -EIO; + goto fail; + } + + if (bachk(tbuf) < 0) { + rc = -EINVAL; + goto fail; + } + + str = tbuf; + for (i = 5; i >= 0; i--) { + buf[i] = simple_strtol(str, NULL, 16); + str += 3; + } + + return size; +fail: + return rc; +} + +static u8 *load_config(dev_data *dev_entry, int *length) +{ + patch_info *patch_entry; + const char *config_name; + const struct firmware *fw; + struct usb_device *udev; + int result; + u8 *buf; + u8 *p; + u16 config_len; + u16 dlen; + u8 tmp_buf[32]; + int file_sz; + struct cfg_list_item *n; + struct list_head *pos, *next; + u8 chip_type; + + config_lists_init(); + patch_entry = dev_entry->patch_entry; + config_name = patch_entry->config_name; + udev = dev_entry->udev; + chip_type = patch_entry->chip_type; + + RTKBT_INFO("config filename %s", config_name); + result = request_firmware(&fw, config_name, &udev->dev); + if (result < 0) + return 0; + + file_sz = fw->size; + buf = (u8 *)fw->data; + + /* Load extra configs */ + config_file_proc(EXTRA_CONFIG_FILE); + list_for_each_safe(pos, next, &list_extracfgs) { + n = list_entry(pos, struct cfg_list_item, list); + RTKBT_INFO("extra cfg: ofs %04x, len %u", n->offset, n->len); + } + + /* Load extra bdaddr config */ + memset(tmp_buf, 0, sizeof(tmp_buf)); + result = request_bdaddr(tmp_buf); + if (result > 0) { + n = kzalloc(sizeof(*n) + 6, GFP_KERNEL); + if (n) { + n->offset = get_mac_offset(patch_entry->chip_type); + n->len = 6; + memcpy(n->data, tmp_buf, 6); + list_add_tail(&n->list, &list_extracfgs); + } else { + RTKBT_WARN("Couldn't alloc mem for bdaddr"); + } + } else { + if (result == -ENOENT) + RTKBT_WARN("no bdaddr file %s", BDADDR_FILE); + else + RTKBT_WARN("invalid customer bdaddr %d", result); + } + + RTKBT_INFO("Origin cfg len %u", (u16)file_sz); + util_hexdump((const u8 *)buf, file_sz); + + result = rtk_parse_config_file(buf, file_sz); + if (result < 0) { + RTKBT_ERR("Parse config file error"); + buf = NULL; + goto done; + } + + merge_configs(&list_configs, &list_extracfgs); + + /* Calculate the config_len */ + config_len = 4; /* magic word length */ + config_len += 2; /* data length field */ + dlen = 0; + list_for_each_safe(pos, next, &list_configs) { + n = list_entry(pos, struct cfg_list_item, list); + switch (n->offset) { + case 0x003c: + case 0x0030: + case 0x0044: + if (is_mac(chip_type, n->offset) && n->len == 6) { + char s[18]; + sprintf(s, "%2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X", + n->data[5], n->data[4], + n->data[3], n->data[2], + n->data[1], n->data[0]); + RTKBT_INFO("bdaddr ofs %04x, %s", n->offset, s); + } + break; + default: + break; + } + + config_len += (3 + n->len); + dlen += (3 + n->len); + } + + + buf = kzalloc(config_len, GFP_KERNEL); + if (!buf) { + RTKBT_ERR("Couldn't alloc buf for configs"); + goto done; + } + + /* Save configs to a buffer */ + memcpy(buf, cfg_magic, 4); + buf[4] = dlen & 0xff; + buf[5] = (dlen >> 8) & 0xff; + p = buf + 6; + list_for_each_safe(pos, next, &list_configs) { + n = list_entry(pos, struct cfg_list_item, list); + p[0] = n->offset & 0xff; + p[1] = (n->offset >> 8) & 0xff; + p[2] = n->len; + memcpy(p + 3, n->data, n->len); + p += (3 + n->len); + } + + RTKBT_INFO("New cfg len %u", config_len); + util_hexdump((const u8 *)buf, config_len); + + *length = config_len; + +done: + config_lists_free(); + release_firmware(fw); + + return buf; +} + +int load_firmware(dev_data * dev_entry, uint8_t ** buff) +{ + const struct firmware *fw; + struct usb_device *udev; + patch_info *patch_entry; + char *fw_name; + int fw_len = 0, ret_val = 0, config_len = 0, buf_len = -1; + uint8_t *buf = NULL, *config_file_buf = NULL, *epatch_buf = NULL; + uint8_t proj_id = 0; + uint8_t need_download_fw = 1; + uint16_t lmp_version; + struct rtk_epatch_entry current_entry = { 0 }; + + RTKBT_DBG("load_firmware start"); + udev = dev_entry->udev; + patch_entry = dev_entry->patch_entry; + lmp_version = patch_entry->lmp_sub; + RTKBT_DBG("lmp_version = 0x%04x", lmp_version); + + config_file_buf = load_config(dev_entry, &config_len); + + fw_name = patch_entry->patch_name; + RTKBT_ERR("fw name is %s", fw_name); + ret_val = request_firmware(&fw, fw_name, &udev->dev); + if (ret_val < 0) { + fw_len = 0; + kfree(config_file_buf); + config_file_buf = NULL; + goto fw_fail; + } + + epatch_buf = kzalloc(fw->size, GFP_KERNEL); + if (NULL == epatch_buf) + goto alloc_fail; + + memcpy(epatch_buf, fw->data, fw->size); + buf_len = fw->size + config_len; + + if (lmp_version == ROM_LMP_8723a) { + RTKBT_DBG("This is 8723a, use old patch style!"); + + if (memcmp(epatch_buf, RTK_EPATCH_SIGNATURE, 8) == 0) { + RTKBT_ERR("8723a Check signature error!"); + need_download_fw = 0; + } else { + if (!(buf = kzalloc(buf_len, GFP_KERNEL))) { + RTKBT_ERR("Can't alloc memory for fw&config"); + buf_len = -1; + } else { + RTKBT_DBG("8723a, fw copy direct"); + memcpy(buf, epatch_buf, fw->size); + if (config_len) { + memcpy(&buf[buf_len - config_len], + config_file_buf, config_len); + } + } + } + } else { + RTKBT_ERR("This is not 8723a, use new patch style!"); + + /* Get version from ROM */ + gEVersion = rtk_get_eversion(dev_entry); + RTKBT_DBG("%s: New gEVersion %d", __func__, gEVersion); + if (gEVersion == 0xFE) { + RTKBT_ERR("%s: Read ROM version failure", __func__); + need_download_fw = 0; + fw_len = 0; + goto alloc_fail; + } + + /* check Signature and Extension Section Field */ + if ((memcmp(epatch_buf, RTK_EPATCH_SIGNATURE, 8) != 0) || + memcmp(epatch_buf + buf_len - config_len - 4, + Extension_Section_SIGNATURE, 4) != 0) { + RTKBT_ERR("Check SIGNATURE error! do not download fw"); + need_download_fw = 0; + } else { + proj_id = + rtk_get_fw_project_id(epatch_buf + buf_len - + config_len - 5); + + if (lmp_version != project_id[proj_id]) { + RTKBT_ERR + ("lmp_version is %x, project_id is %x, does not match!!!", + lmp_version, project_id[proj_id]); + need_download_fw = 0; + } else { + RTKBT_DBG + ("lmp_version is %x, project_id is %x, match!", + lmp_version, project_id[proj_id]); + rtk_get_patch_entry(epatch_buf, ¤t_entry); + + if (current_entry.patch_length == 0) + goto alloc_fail; + + buf_len = + current_entry.patch_length + config_len; + RTKBT_DBG("buf_len = 0x%x", buf_len); + + if (!(buf = kzalloc(buf_len, GFP_KERNEL))) { + RTKBT_ERR + ("Can't alloc memory for multi fw&config"); + buf_len = -1; + } else { + memcpy(buf, + epatch_buf + + current_entry.start_offset, + current_entry.patch_length); + memcpy(buf + current_entry.patch_length - 4, epatch_buf + 8, 4); /*fw version */ + if (config_len) { + memcpy(&buf + [buf_len - config_len], + config_file_buf, + config_len); + } + } + } + } + } + + RTKBT_DBG("fw:%s exists, config file:%s exists", + (buf_len > 0) ? "" : "not", (config_len > 0) ? "" : "not"); + if (buf && (buf_len > 0) && (need_download_fw)) { + fw_len = buf_len; + *buff = buf; + } + + RTKBT_DBG("load_firmware done"); + +alloc_fail: + release_firmware(fw); + + if (epatch_buf) + kfree(epatch_buf); + + if (config_file_buf) + kfree(config_file_buf); +fw_fail: + if (fw_len == 0) + kfree(buf); + + return fw_len; +} + +void init_xdata(xchange_data * xdata, dev_data * dev_entry) +{ + memset(xdata, 0, sizeof(xchange_data)); + xdata->dev_entry = dev_entry; + xdata->pipe_in = usb_rcvintpipe(dev_entry->udev, INTR_EP); + xdata->pipe_out = usb_sndctrlpipe(dev_entry->udev, CTRL_EP); + xdata->send_pkt = kzalloc(PKT_LEN, GFP_KERNEL); + xdata->rcv_pkt = kzalloc(PKT_LEN, GFP_KERNEL); + xdata->cmd_hdr = (struct hci_command_hdr *)(xdata->send_pkt); + xdata->evt_hdr = (struct hci_event_hdr *)(xdata->rcv_pkt); + xdata->cmd_cmp = + (struct hci_ev_cmd_complete *)(xdata->rcv_pkt + EVT_HDR_LEN); + xdata->req_para = xdata->send_pkt + CMD_HDR_LEN; + xdata->rsp_para = xdata->rcv_pkt + EVT_HDR_LEN + CMD_CMP_LEN; +} + +int check_fw_version(xchange_data * xdata) +{ + struct hci_rp_read_local_version *read_ver_rsp; + patch_info *patch_entry; + int ret_val; + int retry = 0; + + /* Ensure that the first cmd is hci reset after system suspend + * or system reboot */ + send_reset_command(xdata); + +get_ver: + xdata->cmd_hdr->opcode = cpu_to_le16(HCI_OP_READ_LOCAL_VERSION); + xdata->cmd_hdr->plen = 0; + xdata->pkt_len = CMD_HDR_LEN; + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + RTKBT_ERR("%s: Failed to send HCI command.", __func__); + goto version_end; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + RTKBT_ERR("%s: Failed to receive HCI event.", __func__); + goto version_end; + } + + patch_entry = xdata->dev_entry->patch_entry; + read_ver_rsp = (struct hci_rp_read_local_version *)(xdata->rsp_para); + read_ver_rsp->lmp_subver = le16_to_cpu(read_ver_rsp->lmp_subver); + read_ver_rsp->hci_rev = le16_to_cpu(read_ver_rsp->hci_rev); + read_ver_rsp->manufacturer = le16_to_cpu(read_ver_rsp->manufacturer); + + RTKBT_DBG("read_ver_rsp->lmp_subver = 0x%x", read_ver_rsp->lmp_subver); + RTKBT_DBG("read_ver_rsp->hci_rev = 0x%x", read_ver_rsp->hci_rev); + RTKBT_DBG("patch_entry->lmp_sub = 0x%x", patch_entry->lmp_sub); + if (patch_entry->lmp_sub != read_ver_rsp->lmp_subver) { + return 1; + } + + ret_val = 0; +version_end: + if (ret_val) { + send_reset_command(xdata); + retry++; + if (retry < 2) + goto get_ver; + } + + return ret_val; +} + +uint8_t rtk_get_eversion(dev_data * dev_entry) +{ + struct rtk_eversion_evt *eversion; + patch_info *patch_entry; + int ret_val = 0; + xchange_data *xdata = NULL; + + RTKBT_DBG("%s: gEVersion %d", __func__, gEVersion); + if (gEVersion != 0xFF && gEVersion != 0xFE) { + RTKBT_DBG("gEVersion != 0xFF, return it directly!"); + return gEVersion; + } + + xdata = kzalloc(sizeof(xchange_data), GFP_KERNEL); + if (NULL == xdata) { + ret_val = 0xFE; + RTKBT_DBG("NULL == xdata"); + return ret_val; + } + + init_xdata(xdata, dev_entry); + + xdata->cmd_hdr->opcode = cpu_to_le16(HCI_VENDOR_READ_RTK_ROM_VERISION); + xdata->cmd_hdr->plen = 0; + xdata->pkt_len = CMD_HDR_LEN; + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + RTKBT_ERR("Failed to send read RTK rom version cmd."); + ret_val = 0xFE; + goto version_end; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + RTKBT_ERR("Failed to receive HCI event for rom version."); + ret_val = 0xFE; + goto version_end; + } + + patch_entry = xdata->dev_entry->patch_entry; + eversion = (struct rtk_eversion_evt *)(xdata->rsp_para); + RTKBT_DBG("eversion->status = 0x%x, eversion->version = 0x%x", + eversion->status, eversion->version); + if (eversion->status) { + ret_val = 0; + //global_eversion = 0; + } else { + ret_val = eversion->version; + //global_eversion = eversion->version; + } + +version_end: + if (xdata != NULL) { + if (xdata->send_pkt) + kfree(xdata->send_pkt); + if (xdata->rcv_pkt) + kfree(xdata->rcv_pkt); + kfree(xdata); + } + return ret_val; +} + +int download_data(xchange_data * xdata) +{ + download_cp *cmd_para; + download_rp *evt_para; + uint8_t *pcur; + int pkt_len, frag_num, frag_len; + int i, ret_val; + int j; + + RTKBT_DBG("download_data start"); + + cmd_para = (download_cp *) xdata->req_para; + evt_para = (download_rp *) xdata->rsp_para; + pcur = xdata->fw_data; + pkt_len = CMD_HDR_LEN + sizeof(download_cp); + frag_num = xdata->fw_len / PATCH_SEG_MAX + 1; + frag_len = PATCH_SEG_MAX; + + for (i = 0; i < frag_num; i++) { + if (i > 0x7f) + j = (i & 0x7f) + 1; + else + j = i; + + cmd_para->index = j; + if (i == (frag_num - 1)) { + cmd_para->index |= DATA_END; + frag_len = xdata->fw_len % PATCH_SEG_MAX; + pkt_len -= (PATCH_SEG_MAX - frag_len); + } + xdata->cmd_hdr->opcode = cpu_to_le16(DOWNLOAD_OPCODE); + xdata->cmd_hdr->plen = sizeof(uint8_t) + frag_len; + xdata->pkt_len = pkt_len; + memcpy(cmd_para->data, pcur, frag_len); + + ret_val = send_hci_cmd(xdata); + if (ret_val < 0) { + return ret_val; + } + + ret_val = rcv_hci_evt(xdata); + if (ret_val < 0) { + return ret_val; + } + + if (0 != evt_para->status) { + return -1; + } + + pcur += PATCH_SEG_MAX; + } + + RTKBT_DBG("download_data done"); + return xdata->fw_len; +} + +int send_hci_cmd(xchange_data * xdata) +{ + int ret_val; + + ret_val = usb_control_msg(xdata->dev_entry->udev, xdata->pipe_out, + 0, USB_TYPE_CLASS, 0, 0, + (void *)(xdata->send_pkt), + xdata->pkt_len, MSG_TO); + + if (ret_val < 0) + RTKBT_ERR("%s; failed to send ctl msg for hci cmd, err %d", + __func__, ret_val); + + return ret_val; +} + +int rcv_hci_evt(xchange_data * xdata) +{ + int ret_len = 0, ret_val = 0; + int i; // Added by Realtek + + while (1) { + // **************************** Modifed by Realtek (begin) + for (i = 0; i < 5; i++) // Try to send USB interrupt message 5 times. + { + ret_val = + usb_interrupt_msg(xdata->dev_entry->udev, + xdata->pipe_in, + (void *)(xdata->rcv_pkt), PKT_LEN, + &ret_len, MSG_TO); + if (ret_val >= 0) + break; + } + // **************************** Modifed by Realtek (end) + + if (ret_val < 0) { + RTKBT_ERR("%s; no usb intr msg for hci event, err %d", + __func__, ret_val); + return ret_val; + } + + if (CMD_CMP_EVT == xdata->evt_hdr->evt) { + if (xdata->cmd_hdr->opcode == xdata->cmd_cmp->opcode) + return ret_len; + } + } +} + +void print_acl(struct sk_buff *skb, int dataOut) +{ +#if PRINT_ACL_DATA + uint wlength = skb->len; + uint icount = 0; + u16 *handle = (u16 *) (skb->data); + u16 dataLen = *(handle + 1); + u8 *acl_data = (u8 *) (skb->data); +//if (0==dataOut) + printk("%d handle:%04x,len:%d,", dataOut, *handle, dataLen); +//else +// printk("In handle:%04x,len:%d,",*handle,dataLen); +/* for(icount=4;(icountlen; + uint icount = 0; + u16 *opcode = (u16 *) (skb->data); + u8 *cmd_data = (u8 *) (skb->data); + u8 paramLen = *(cmd_data + 2); + + switch (*opcode) { + case HCI_OP_INQUIRY: + printk("HCI_OP_INQUIRY"); + break; + case HCI_OP_INQUIRY_CANCEL: + printk("HCI_OP_INQUIRY_CANCEL"); + break; + case HCI_OP_EXIT_PERIODIC_INQ: + printk("HCI_OP_EXIT_PERIODIC_INQ"); + break; + case HCI_OP_CREATE_CONN: + printk("HCI_OP_CREATE_CONN"); + break; + case HCI_OP_DISCONNECT: + printk("HCI_OP_DISCONNECT"); + break; + case HCI_OP_CREATE_CONN_CANCEL: + printk("HCI_OP_CREATE_CONN_CANCEL"); + break; + case HCI_OP_ACCEPT_CONN_REQ: + printk("HCI_OP_ACCEPT_CONN_REQ"); + break; + case HCI_OP_REJECT_CONN_REQ: + printk("HCI_OP_REJECT_CONN_REQ"); + break; + case HCI_OP_AUTH_REQUESTED: + printk("HCI_OP_AUTH_REQUESTED"); + break; + case HCI_OP_SET_CONN_ENCRYPT: + printk("HCI_OP_SET_CONN_ENCRYPT"); + break; + case HCI_OP_REMOTE_NAME_REQ: + printk("HCI_OP_REMOTE_NAME_REQ"); + break; + case HCI_OP_READ_REMOTE_FEATURES: + printk("HCI_OP_READ_REMOTE_FEATURES"); + break; + case HCI_OP_SNIFF_MODE: + printk("HCI_OP_SNIFF_MODE"); + break; + case HCI_OP_EXIT_SNIFF_MODE: + printk("HCI_OP_EXIT_SNIFF_MODE"); + break; + case HCI_OP_SWITCH_ROLE: + printk("HCI_OP_SWITCH_ROLE"); + break; + case HCI_OP_SNIFF_SUBRATE: + printk("HCI_OP_SNIFF_SUBRATE"); + break; + case HCI_OP_RESET: + printk("HCI_OP_RESET"); + break; + default: + printk("CMD"); + break; + } + printk(":%04x,len:%d,", *opcode, paramLen); + for (icount = 3; (icount < wlength) && (icount < 24); icount++) { + printk("%02x ", *(cmd_data + icount)); + } + printk("\n"); + +#endif +} + +void print_event(struct sk_buff *skb) +{ +#if PRINT_CMD_EVENT + uint wlength = skb->len; + uint icount = 0; + u8 *opcode = (u8 *) (skb->data); + u8 paramLen = *(opcode + 1); + + switch (*opcode) { + case HCI_EV_INQUIRY_COMPLETE: + printk("HCI_EV_INQUIRY_COMPLETE"); + break; + case HCI_EV_INQUIRY_RESULT: + printk("HCI_EV_INQUIRY_RESULT"); + break; + case HCI_EV_CONN_COMPLETE: + printk("HCI_EV_CONN_COMPLETE"); + break; + case HCI_EV_CONN_REQUEST: + printk("HCI_EV_CONN_REQUEST"); + break; + case HCI_EV_DISCONN_COMPLETE: + printk("HCI_EV_DISCONN_COMPLETE"); + break; + case HCI_EV_AUTH_COMPLETE: + printk("HCI_EV_AUTH_COMPLETE"); + break; + case HCI_EV_REMOTE_NAME: + printk("HCI_EV_REMOTE_NAME"); + break; + case HCI_EV_ENCRYPT_CHANGE: + printk("HCI_EV_ENCRYPT_CHANGE"); + break; + case HCI_EV_CHANGE_LINK_KEY_COMPLETE: + printk("HCI_EV_CHANGE_LINK_KEY_COMPLETE"); + break; + case HCI_EV_REMOTE_FEATURES: + printk("HCI_EV_REMOTE_FEATURES"); + break; + case HCI_EV_REMOTE_VERSION: + printk("HCI_EV_REMOTE_VERSION"); + break; + case HCI_EV_QOS_SETUP_COMPLETE: + printk("HCI_EV_QOS_SETUP_COMPLETE"); + break; + case HCI_EV_CMD_COMPLETE: + printk("HCI_EV_CMD_COMPLETE"); + break; + case HCI_EV_CMD_STATUS: + printk("HCI_EV_CMD_STATUS"); + break; + case HCI_EV_ROLE_CHANGE: + printk("HCI_EV_ROLE_CHANGE"); + break; + case HCI_EV_NUM_COMP_PKTS: + printk("HCI_EV_NUM_COMP_PKTS"); + break; + case HCI_EV_MODE_CHANGE: + printk("HCI_EV_MODE_CHANGE"); + break; + case HCI_EV_PIN_CODE_REQ: + printk("HCI_EV_PIN_CODE_REQ"); + break; + case HCI_EV_LINK_KEY_REQ: + printk("HCI_EV_LINK_KEY_REQ"); + break; + case HCI_EV_LINK_KEY_NOTIFY: + printk("HCI_EV_LINK_KEY_NOTIFY"); + break; + case HCI_EV_CLOCK_OFFSET: + printk("HCI_EV_CLOCK_OFFSET"); + break; + case HCI_EV_PKT_TYPE_CHANGE: + printk("HCI_EV_PKT_TYPE_CHANGE"); + break; + case HCI_EV_PSCAN_REP_MODE: + printk("HCI_EV_PSCAN_REP_MODE"); + break; + case HCI_EV_INQUIRY_RESULT_WITH_RSSI: + printk("HCI_EV_INQUIRY_RESULT_WITH_RSSI"); + break; + case HCI_EV_REMOTE_EXT_FEATURES: + printk("HCI_EV_REMOTE_EXT_FEATURES"); + break; + case HCI_EV_SYNC_CONN_COMPLETE: + printk("HCI_EV_SYNC_CONN_COMPLETE"); + break; + case HCI_EV_SYNC_CONN_CHANGED: + printk("HCI_EV_SYNC_CONN_CHANGED"); + break; + case HCI_EV_SNIFF_SUBRATE: + printk("HCI_EV_SNIFF_SUBRATE"); + break; + case HCI_EV_EXTENDED_INQUIRY_RESULT: + printk("HCI_EV_EXTENDED_INQUIRY_RESULT"); + break; + case HCI_EV_IO_CAPA_REQUEST: + printk("HCI_EV_IO_CAPA_REQUEST"); + break; + case HCI_EV_SIMPLE_PAIR_COMPLETE: + printk("HCI_EV_SIMPLE_PAIR_COMPLETE"); + break; + case HCI_EV_REMOTE_HOST_FEATURES: + printk("HCI_EV_REMOTE_HOST_FEATURES"); + break; + default: + printk("event"); + break; + } + printk(":%02x,len:%d,", *opcode, paramLen); + for (icount = 2; (icount < wlength) && (icount < 24); icount++) { + printk("%02x ", *(opcode + icount)); + } + printk("\n"); + +#endif +} diff --git a/drivers/bluetooth/rtk_misc.h b/drivers/bluetooth/rtk_misc.h new file mode 100644 index 0000000000000..048d34eb7b114 --- /dev/null +++ b/drivers/bluetooth/rtk_misc.h @@ -0,0 +1,95 @@ +/* + * + * Realtek Bluetooth USB download firmware driver + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +/* Download LPS patch when host suspends or power off + * LPS patch name: lps_rtl8xxx_fw + * LPS config name: lps_rtl8xxx_config + * Download normal patch when host resume or power on */ +/* #define RTKBT_SWITCH_PATCH */ + +/* RTKBT Power-on Whitelist for sideband wake-up by LE Advertising from Remote. + * Note that it's necessary to apply TV FW Patch. */ +/* #define RTKBT_TV_POWERON_WHITELIST */ + +#if 1 +#define RTKBT_DBG(fmt, arg...) printk(KERN_INFO "rtk_btusb: " fmt "\n" , ## arg) +#define RTKBT_INFO(fmt, arg...) printk(KERN_INFO "rtk_btusb: " fmt "\n" , ## arg) +#define RTKBT_WARN(fmt, arg...) printk(KERN_WARNING "rtk_btusb: " fmt "\n", ## arg) +#else +#define RTKBT_DBG(fmt, arg...) +#endif + +#if 1 +#define RTKBT_ERR(fmt, arg...) printk(KERN_ERR "rtk_btusb: " fmt "\n" , ## arg) +#else +#define RTKBT_ERR(fmt, arg...) +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 33) +#define USB_RPM +#endif + +#define CONFIG_NEEDS_BINDING + +/* If module is still powered when kernel suspended, there is no re-binding. */ +#ifdef RTKBT_SWITCH_PATCH +#undef CONFIG_NEEDS_BINDING +#endif + +/* USB SS */ +#if (defined CONFIG_BTUSB_AUTOSUSPEND) && (defined USB_RPM) +#define BTUSB_RPM +#endif + +#define PRINT_CMD_EVENT 0 +#define PRINT_ACL_DATA 0 + +extern int patch_add(struct usb_interface *intf); +extern void patch_remove(struct usb_interface *intf); +extern int download_patch(struct usb_interface *intf); +extern void print_event(struct sk_buff *skb); +extern void print_command(struct sk_buff *skb); +extern void print_acl(struct sk_buff *skb, int dataOut); + +#if defined RTKBT_SWITCH_PATCH || defined RTKBT_TV_POWERON_WHITELIST +int __rtk_send_hci_cmd(struct usb_device *udev, u8 *buf, u16 size); +int __rtk_recv_hci_evt(struct usb_device *udev, u8 *buf, u8 len, u16 opcode); +#endif + +#ifdef RTKBT_SWITCH_PATCH +#define RTLBT_CLOSE (1 << 0) +struct api_context { + u32 flags; + struct completion done; + int status; +}; + +int download_lps_patch(struct usb_interface *intf); +int set_scan(struct usb_interface *intf); + +#endif diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 1b35d1724565e..10b862fecd597 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -45,3 +45,5 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o +#fox.luo@add vk2c21 lcd driver +obj-y += lcd_vk2c21.o diff --git a/drivers/char/lcd_vk2c21.c b/drivers/char/lcd_vk2c21.c new file mode 100644 index 0000000000000..0afde806a38d2 --- /dev/null +++ b/drivers/char/lcd_vk2c21.c @@ -0,0 +1,707 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LCD_EXT_DEBUG_INFO +#ifdef LCD_EXT_DEBUG_INFO +#define DBG_PRINT(...) printk(__VA_ARGS__) +#else +#define DBG_PRINT(...) +#endif +#define DEVICE_NAME "lcd_vk2c21" +/* ioctrl magic set */ +#define CH455_IOC_MAGIC 'h' +#define IOCTL_CHAR_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x10, unsigned char) +#define IOCTL_DOT_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x11, unsigned char) +#define IOCTL_COLON_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x12, unsigned char) +#define IOCTL_PWR_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x13, unsigned char) +#define IOCTL_LAN_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x14, unsigned char) +#define IOCTL_LAN_OFF _IOWR(CH455_IOC_MAGIC, 0x15, unsigned char) +#define IOCTL_WIFI_LOW_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x16, unsigned char) +#define IOCTL_WIFI_FINE_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x17, unsigned char) +#define IOCTL_WIFI_OFF _IOWR(CH455_IOC_MAGIC, 0x18, unsigned char) +#define IOCTL_LED_ON _IOWR(CH455_IOC_MAGIC, 0x19, unsigned char) +#define IOCTL_LED_OFF _IOWR(CH455_IOC_MAGIC, 0x1a, unsigned char) + +//以下管脚输出定义根æ®å®¢æˆ·å•ç‰‡æœºåšç›¸åº”的修改 +#define Vk2c21_SCL_H() gpio_set_value(gpio_i2c_scl,1) +#define Vk2c21_SCL_L() gpio_set_value(gpio_i2c_scl,0) + +#define Vk2c21_SDA_H() gpio_set_value(gpio_i2c_sda,1) +#define Vk2c21_SDA_L() gpio_set_value(gpio_i2c_sda,0) + +#define Vk2c21_GET_SDA() gpio_get_value(gpio_i2c_sda) +#define Vk2c21_SET_SDA_IN() gpio_direction_input(gpio_i2c_sda) +#define Vk2c21_SET_SDA_OUT() gpio_direction_output(gpio_i2c_sda, 1) + +static int gpio_i2c_scl,gpio_i2c_sda; +/** +****************************************************************************** +* @file vk2c21.c +* @author kevin_guo +* @version V1.2 +* @date 05-17-2020 +* @brief This file contains all the vk2c21 functions. +* 此文件适用于 VK2c21 +****************************************************************************** +* @attention +****************************************************************************** +*/ +#include "lcd_vk2c21.h" + +#define VK2c21_CLK 100 //SCLä¿¡å·çº¿é¢‘率,ç”±delay_nus实现 50->10kHz 10->50kHz 5->100kHz +//驱动segæ•° +//4com +//VK2C21A/B/C/D +#define Vk2c21_SEGNUM 13 +#define Vk2c21A_MAXSEGNUM 20 +#define Vk2c21B_MAXSEGNUM 16 +#define Vk2c21C_MAXSEGNUM 12 +#define Vk2c21D_MAXSEGNUM 8 + +//segtab[]数组对应实际的芯片到LCD连线，连线è§-VK2c21å‚考电路 +//4com +//Vk2c21A +unsigned char vk2c21_segtab[Vk2c21_SEGNUM]={ + 18,17,16,15,14,13,12,11,10, + 9,8,7,6 +}; + +//4com +unsigned char vk2c21_dispram[Vk2c21_SEGNUM/2];//4COMæ—¶æ¯ä¸ªå­—节数æ®å¯¹åº”2个SEG +//8com +//unsigned char vk2c21_dispram[Vk2c21_SEGNUM];//8COMæ—¶æ¯ä¸ªå­—节数æ®å¯¹åº”1个SEG + +unsigned char shuzi_zimo[15]= //数字和字符字模 +{ + //0 1 2 3 4 5 6 7 8 9 - L o H i + 0xf5,0x05,0xb6,0x97,0x47,0xd3,0xf3,0x85,0xf7,0xd7,0x02,0x70,0x33,0x67,0x50 +}; +unsigned char vk2c21_segi,vk2c21_comi; +unsigned char vk2c21_maxcom;//驱动的comæ•°VK2C23Aå¯ä»¥æ˜¯4com或者8com +unsigned char vk2c21_maxseg;//Vk2c21A=20 Vk2c21B=16 Vk2c21C=12 Vk2c21D=8 +/* Private function prototypes -----------------------------------------------*/ +unsigned char Vk2c21_InitSequence(void); +/* Private function ----------------------------------------------------------*/ + + +/******************************************************************************* +* Function Name : delay_nus +* Description : 延时1uSç¨‹åº +* Input : n->延时时间nuS +* Output : None +* Return : None +*******************************************************************************/ +static void delay_nus(unsigned int n) +{ + ndelay(n); +} +/******************************************************************************* +* Function Name : I2CStart I2CStop I2CSlaveAck +* I2CStart Description : 时钟线高时，数æ®çº¿ç”±é«˜åˆ°ä½Žçš„è·³å˜ï¼Œè¡¨ç¤ºI2Cå¼€å§‹ä¿¡å· +* I2CStop Description : 时钟线高时，数æ®çº¿ç”±ä½Žåˆ°é«˜çš„è·³å˜ï¼Œè¡¨ç¤ºI2Cåœæ­¢ä¿¡å· +* I2CSlaveAck Description : I2C从机设备应答查询 +*******************************************************************************/ +static void Vk2c21_I2CStart( void ) +{ + Vk2c21_SCL_H(); + Vk2c21_SDA_H(); + delay_nus(VK2c21_CLK); + Vk2c21_SDA_L(); + delay_nus(VK2c21_CLK); +} + +static void Vk2c21_I2CStop( void ) +{ + Vk2c21_SCL_H(); + Vk2c21_SDA_L(); + delay_nus(VK2c21_CLK); + Vk2c21_SDA_H(); + delay_nus(VK2c21_CLK); +} + +static unsigned char Vk2c21_I2CSlaveAck( void ) +{ + unsigned int TimeOut; + unsigned char RetValue; + + Vk2c21_SCL_L(); + //å•ç‰‡æœºSDA脚为å•å‘IOè¦è®¾ä¸ºè¾“入脚 + Vk2c21_SET_SDA_IN(); + delay_nus(VK2c21_CLK); + Vk2c21_SCL_H();//第9个sclk上å‡æ²¿ + + TimeOut = 10000; + while( TimeOut-- > 0 ) + { + if( Vk2c21_GET_SDA()!=0 )//读å–ack + { + RetValue = 1; + } + else + { + RetValue = 0; + break; + } + } + Vk2c21_SCL_L(); + //å•ç‰‡æœºSDA脚为å•å‘IOè¦è®¾ä¸ºè¾“出脚 + Vk2c21_SET_SDA_OUT(); + //printk("---%s----ret=%d------\n",__func__,RetValue); + return RetValue; +} +/******************************************************************************* +* Function Name : I2CWriteByte +* Description : I2C写一字节命令,命令先é€é«˜ä½ +* Input : byte-è¦å†™å…¥çš„æ•°æ® +* Output : None +* Return : None +*******************************************************************************/ +static void Vk2c21_I2CWriteByte( unsigned char byte ) +{ + unsigned char i=8; + while (i--) + { + Vk2c21_SCL_L(); + if(byte&0x80) + Vk2c21_SDA_H(); + else + Vk2c21_SDA_L(); + byte<<=1; + delay_nus(VK2c21_CLK); + Vk2c21_SCL_H(); + delay_nus(VK2c21_CLK); + } +} + +/************************************************************* +*函数å称: WriteCmdVk2c21 +*函数功能: å‘Vk2C23写1个命令 +*输入å‚æ•°: addr Dmodåœ°å€ + data å†™å…¥çš„æ•°æ® +*输出å‚数：SET: 写入正常；RESET:写入错误 +*备 注： +**************************************************************/ +static unsigned char WriteCmdVk2c21(unsigned char cmd, unsigned char data ) +{ + Vk2c21_I2CStart(); + + Vk2c21_I2CWriteByte( Vk2c21_ADDR|0x00 ); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 0; + } + Vk2c21_I2CWriteByte( cmd ); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 0; + } + Vk2c21_I2CWriteByte( data ); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 0; + } + Vk2c21_I2CStop(); + + return 0; //返回æ“作æˆè´¥æ ‡å¿— +} +/******************************************************************************* +* Function Name : Write1Data +* Description : 写1字节数æ®åˆ°æ˜¾ç¤ºRAM +* Input : Addr-写入ramçš„åœ°å€ +* : Dat->写入ramçš„æ•°æ® +* Output : None +* Return : 0-ok 1-fail +*******************************************************************************/ +static unsigned char Write1DataVk2c21(unsigned char Addr,unsigned char Dat) +{ + //START ä¿¡å· + Vk2c21_I2CStart(); + //SLAVEåœ°å€ + Vk2c21_I2CWriteByte(Vk2c21_ADDR); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 1; + } + //写显示RAM命令 + Vk2c21_I2CWriteByte(Vk2c21_RWRAM); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 0; + } + //显示RAMåœ°å€ + Vk2c21_I2CWriteByte(Addr); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 1; + } + //显示数æ®ï¼Œ1字节数æ®åŒ…å«2个SEG + Vk2c21_I2CWriteByte(Dat); + if( Vk2c21_I2CSlaveAck()==1 ) + { + Vk2c21_I2CStop(); + return 1; + } + //STOPä¿¡å· + Vk2c21_I2CStop(); + return 0; +} +/******************************************************************************* +* Function Name : WritenData +* Description : 写多个数æ®åˆ°æ˜¾ç¤ºRAM +* Input : Addr-写入ramçš„èµ·å§‹åœ°å€ +* : Databuf->写入ramçš„æ•°æ®buffer指针 +* : Cnt->写入ramçš„æ•°æ®ä¸ªæ•° +* Output : None +* Return : 0-ok 1-fail +*******************************************************************************/ +static unsigned char WritenDataVk2c21(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt) +{ + unsigned char n; + + //STARTä¿¡å· + Vk2c21_I2CStart(); + //SLAVEåœ°å€ + Vk2c21_I2CWriteByte(Vk2c21_ADDR); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 0; + } + //写显示RAM命令 + Vk2c21_I2CWriteByte(Vk2c21_RWRAM); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 0; + } + //显示RAMèµ·å§‹åœ°å€ + Vk2c21_I2CWriteByte(Addr); + if( 1 == Vk2c21_I2CSlaveAck() ) + { + Vk2c21_I2CStop(); + return 0; + } + //å‘é€Cnt个数æ®åˆ°æ˜¾ç¤ºRAM + for(n=0;n写入ramçš„æ•°æ®(1个字节数æ®å¯¹åº”2个SEG) +* Output : None +* Return : None +*******************************************************************************/ +static void Vk2c21_DisAll(unsigned char dat) +{ + unsigned char segi; + unsigned char dispram[16]; + + if(vk2c21_maxcom==4) + { + for(segi=0;segi<10;segi++) + { + dispram[segi]=dat; + } + WritenDataVk2c21(0,dispram,10);//这里é€8bitæ•°æ®å¯¹åº”2个SEG，æ¯8bitæ•°æ®åœ°å€åŠ 1，æ¯8ä½æ•°æ®1个ACK + } + else + { + for(segi=0;segi<16;segi++) + { + dispram[segi]=dat; + } + WritenDataVk2c21(0,dispram,16);//这里é€8bitæ•°æ®å¯¹åº”1个SEG，æ¯8bitæ•°æ®åœ°å€åŠ 1，æ¯8ä½æ•°æ®1个ACK + } +} +/******************************************************************************* +* Function Name : DisSegComOn +* Description : 点亮1个点(1个segå’Œ1个com交å‰å¯¹åº”的显示点) +* Input ：seg->点对应的segè„š +* ：com->点对应comè„š +* Output : None +* Return : None +*******************************************************************************/ +static void Vk2c21_DisSegComOn(unsigned char seg,unsigned char com) +{ + if(vk2c21_maxcom==4) + { + if(seg%2==0) + Write1DataVk2c21(seg/2,(1<<(com)));//这里é€8ä½æ•°æ®ä½Ž4bit有效，æ¯8bitæ•°æ®åœ°å€åŠ 1，æ¯8ä½æ•°æ®1个ACK) + else + Write1DataVk2c21(seg/2,(1<<(4+com)));//这里é€8ä½æ•°æ®é«˜4bit有效，æ¯8bitæ•°æ®åœ°å€åŠ 1，æ¯8ä½æ•°æ®1个ACK + } + else + { + Write1DataVk2c21(seg,(1<<(com)));//这里é€8ä½æ•°æ®ä½Ž4bit有效，æ¯8bitæ•°æ®åœ°å€åŠ 1，æ¯8ä½æ•°æ®1个ACK + } +} +/******************************************************************************* +* Function Name : DisSegComOff +* Description : 关闭1个点(1个segå’Œ1个com交å‰å¯¹åº”的显示点) +* Input ：seg->点对应的segè„š +* ：com->点对应comè„š +* Output : None +* Return : None +*******************************************************************************/ +static void Vk2c21_DisSegComOff(unsigned char seg,unsigned char com) +{ + if(vk2c21_maxcom==4) + { + if(seg%2==0) + Write1DataVk2c21(seg/2,~(1<0å置电压=VLCD + WriteCmdVk2c21(Vk2c21_IVASET,VLCDSEL_IVAOFF_R1); + //SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.652VDD 1/4bias=0.714VDD + //WriteCmdVk2c21(Vk2c21_IVASET,SEGSEL_IVA02H); + + //test + Vk2c21_DisAll(0x00); + disp_3num(456); + //Vk2c21_DisAll(0xff); //LCD全显 + //disp_3num(1234); + return ret; +} + +static int Vk2c21_open(struct inode *inode, struct file *file) +{ + int ret; + ret = nonseekable_open(inode, file); + if(ret < 0) + return ret; + return 0; +} + +static int Vk2c21_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static long Vk2c21_ioctl(struct file *file, unsigned int cmd, unsigned long args) +{ + int ret = 0 , i=0,pos_temp=0; + void __user *argp = (void __user *)args; + unsigned char display_arg[6]={0}; + switch (cmd){ + case IOCTL_CHAR_DISPLAY: + if (args) { + ret = copy_from_user(display_arg, argp,sizeof(display_arg)/sizeof(display_arg[0])); + } + for(i=0;i<6;i++) + { + if(display_arg[i] <= '9' && display_arg[i] >= '0') + { + pos_temp = display_arg[i] - '0'; + vk2c21_dispram[i]&=0xf0; + vk2c21_dispram[i]|=shuzi_zimo[pos_temp]&0x0f; + vk2c21_dispram[i]&=0x8f; + vk2c21_dispram[i]|=shuzi_zimo[pos_temp]&0xf0; + Write1DataVk2c21(vk2c21_segtab[2*i+2]/2,vk2c21_dispram[i]); + }else if(display_arg[i] <= 'z' && display_arg[i] >= 'a'){ + }else if(display_arg[i] <= 'Z' && display_arg[i] >= 'A'){ + } + } + break; + case IOCTL_DOT_DISPLAY: + break; + case IOCTL_COLON_DISPLAY: + break; + case IOCTL_PWR_DISPLAY: + break; + case IOCTL_LAN_DISPLAY: + Vk2c21_DisSegComOn(vk2c21_segtab[6],0x1); + break; + case IOCTL_LAN_OFF: + Vk2c21_DisSegComOff(vk2c21_segtab[6],0x1); + break; + case IOCTL_WIFI_LOW_DISPLAY: + break; + case IOCTL_WIFI_FINE_DISPLAY: + break; + case IOCTL_WIFI_OFF: + break; + case IOCTL_LED_ON: + Vk2c21_DisAll(0xff); //LCD全显 + break; + case IOCTL_LED_OFF: + Vk2c21_DisAll(0x00); //LCD全关 + break; + default: + printk("ERROR: IOCTL CMD NOT FOUND!!!\n"); + break; + } + return 0; +} +static struct file_operations Vk2c21_fops ={ + .owner =THIS_MODULE, + .open =Vk2c21_open, + .release =Vk2c21_release, + .unlocked_ioctl =Vk2c21_ioctl, +}; + + + +static int Vk2c21_probe(struct platform_device *pdev) +{ + static struct class * scull_class; + struct device_node *node = pdev->dev.of_node; + enum of_gpio_flags flags; + int ret; + + ret =register_chrdev(0,DEVICE_NAME,&Vk2c21_fops); + if(ret<0){ + printk("can't register device lcd_vk2c21.\n"); + return ret; + } + printk("register device lcd_vk2c21 success.\n"); + + scull_class = class_create(THIS_MODULE,DEVICE_NAME); + if(IS_ERR(scull_class)) + { + printk(KERN_ALERT "Err:faile in scull_class!\n"); + return -1; + } + device_create(scull_class, NULL, MKDEV(ret,0), NULL, DEVICE_NAME); + + + //--------------------------- + gpio_i2c_scl = of_get_named_gpio_flags(node, "i2c_scl", 0, &flags); + if (gpio_is_valid(gpio_i2c_scl)){ + if (gpio_request(gpio_i2c_scl, "i2c_scl_gpio")<0) { + printk("%s: failed to get gpio_i2c_scl.\n", __func__); + return -1; + } + gpio_direction_output(gpio_i2c_scl, 1); + printk("%s: get property: gpio,i2c_scl = %d\n", __func__, gpio_i2c_scl); + }else{ + printk("get property gpio,i2c vk2c21 failed \n"); + return -1; + } + + gpio_i2c_sda = of_get_named_gpio_flags(node, "i2c_sda", 0, &flags); + + if (gpio_is_valid(gpio_i2c_sda)){ + if (gpio_request(gpio_i2c_sda, "i2c_sda_gpio")<0) { + printk("%s: failed to get gpio_i2c_sda.\n", __func__); + return -1; + } + gpio_direction_output(gpio_i2c_sda, 1); + printk("%s: get property: gpio,i2c_sda = %d\n", __func__, gpio_i2c_sda); + }else{ + printk("get property gpio,i2c vk2c21 failed \n"); + return -1; + } + + printk("==========%s probe ok========\n", DEVICE_NAME); + + ret = Vk2c21_Init(); + if(ret < 0) + return -1; + + + return 0; +} + +static int Vk2c21_remove(struct platform_device *pdev) +{ + unregister_chrdev(0,DEVICE_NAME); + return 0; +} + + +static void Vk2c21_shutdown (struct platform_device *pdev) +{ + WriteCmdVk2c21(Vk2c21_SYSSET,SYSOFF_LCDOFF); +} + +#ifdef CONFIG_OF +static const struct of_device_id Vk2c21_dt_match[]={ + { .compatible = "lcd_vk2c21",}, + {} +}; +MODULE_DEVICE_TABLE(of, Vk2c21_dt_match); +#endif + +static struct platform_driver Vk2c21_driver = { + .probe = Vk2c21_probe, + .remove = Vk2c21_remove, + .shutdown = Vk2c21_shutdown, + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_OF + .of_match_table = of_match_ptr(Vk2c21_dt_match), +#endif + }, +}; + + +static int __init led_vk2c21_init(void) +{ + int ret; + DBG_PRINT("%s\n=============================================\n", __FUNCTION__); + ret = platform_driver_register(&Vk2c21_driver); + if (ret) { + printk("[error] %s failed to register vk2c21 driver module\n", __FUNCTION__); + return -ENODEV; + } + return ret; +} + +static void __exit led_vk2c21_exit(void) +{ + platform_driver_unregister(&Vk2c21_driver); +} + +module_init(led_vk2c21_init); +module_exit(led_vk2c21_exit); + +MODULE_AUTHOR("Hugsun"); +MODULE_DESCRIPTION("LCD Extern driver for lcd_vk2c21"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/lcd_vk2c21.h b/drivers/char/lcd_vk2c21.h new file mode 100644 index 0000000000000..ac6dd04442474 --- /dev/null +++ b/drivers/char/lcd_vk2c21.h @@ -0,0 +1,63 @@ +#ifndef __LCD_VK2C21_H__ +#define __LCD_VK2C21_H__ + +#define Vk2c21_ADDR 0x70 // IICåœ°å€ +//基本设置 +#define Vk2c21_RWRAM 0x80 // 读写显示RAM +#define Vk2c21_MODESET 0x82 // BIAS,COM设置 +#define CCOM_1_3__4 0x00 // 1/3bias 4com +#define CCOM_1_4__4 0x01 // 1/4bias 4com +#define CCOM_1_3__8 0x02 // 1/3bias 8com +#define CCOM_1_4__8 0x03 // 1/4bias 8com +#define Vk2c21_SYSSET 0x84 // IRC,LCD开关设置 +#define SYSOFF_LCDOFF 0x00 // IRC off,LCD off +#define SYSON_LCDOFF 0x02 // IRC on,LCD off +#define SYSON_LCDON 0x03 // IRC on,LCD on +#define Vk2c21_FRAMESET 0x86 // 帧频设置 +#define FRAME_80HZ 0x00 // 帧频80HZ +#define FRAME_160HZ 0x01 // 帧频160HZ +#define Vk2c21_BLINKSET 0x88 // é—ªçƒé¢‘率设置 +#define BLINK_OFF 0x00 // é—ªçƒå…³é—­ +#define BLINK_2HZ 0x01 // é—ªçƒ2HZ +#define BLINK_1HZ 0x02 // é—ªçƒ1HZ +#define BLINK_0D5HZ 0x03 // é—ªçƒ0.5HZ +#define Vk2c21_IVASET 0x8A // SEG/VLCD共用脚设置和内部电压调整设置 +#define VLCDSEL_IVAOFF_R0 0x00 // SEG/VLCD共用脚设为VLCD，内部电压调整功能关闭,VLCDå’ŒVDD短接VR=0å置电压=VDD +#define VLCDSEL_IVAOFF_R1 0x0F // SEG/VLCD共用脚设为VLCD，内部电压调整功能关闭,VLCDå’ŒVDD串接电阻VR>0å置电压=VLCD + +#define VLCDSEL_IVA00H 0x10 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=VDD 1/4bias=VDD +#define VLCDSEL_IVA01H 0x11 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.944VDD 1/4bias=0.957VDD +#define VLCDSEL_IVA02H 0x12 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.894VDD 1/4bias=0.918VDD +#define VLCDSEL_IVA03H 0x13 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.849VDD 1/4bias=0.882VDD +#define VLCDSEL_IVA04H 0x14 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.808VDD 1/4bias=0.849VDD +#define VLCDSEL_IVA05H 0x15 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.771VDD 1/4bias=0.818VDD +#define VLCDSEL_IVA06H 0x16 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.738VDD 1/4bias=0.789VDD +#define VLCDSEL_IVA07H 0x17 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.707VDD 1/4bias=0.763VDD +#define VLCDSEL_IVA08H 0x18 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.678VDD 1/4bias=0.738VDD +#define VLCDSEL_IVA09H 0x19 // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.652VDD 1/4bias=0.714VDD +#define VLCDSEL_IVA0AH 0x1A // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.628VDD 1/4bias=0.692VDD +#define VLCDSEL_IVA0BH 0x1B // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.605VDD 1/4bias=0.672VDD +#define VLCDSEL_IVA0CH 0x1C // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.584VDD 1/4bias=0.652VDD +#define VLCDSEL_IVA0DH 0x1D // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.565VDD 1/4bias=0.634VDD +#define VLCDSEL_IVA0EH 0x1E // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.547VDD 1/4bias=0.616VDD +#define VLCDSEL_IVA0FH 0x1F // SEG/VLCD共用脚设为VLCD输出，内部å置电压调整：1/3bias=0.529VDD 1/4bias=0.600VDD + +#define SEGSEL_IVAOFF 0x20 // SEG/VLCD共用脚设为SEG，内部电压调整功能关闭,VDDæä¾›å置电压 +#define SEGSEL_IVA00H 0x30 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=VDD 1/4bias=VDD +#define SEGSEL_IVA01H 0x31 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.944VDD 1/4bias=0.957VDD +#define SEGSEL_IVA02H 0x32 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.894VDD 1/4bias=0.918VDD +#define SEGSEL_IVA03H 0x33 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.849VDD 1/4bias=0.882VDD +#define SEGSEL_IVA04H 0x34 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.808VDD 1/4bias=0.849VDD +#define SEGSEL_IVA05H 0x35 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.771VDD 1/4bias=0.818VDD +#define SEGSEL_IVA06H 0x36 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.738VDD 1/4bias=0.789VDD +#define SEGSEL_IVA07H 0x37 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.707VDD 1/4bias=0.763VDD +#define SEGSEL_IVA08H 0x38 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.678VDD 1/4bias=0.738VDD +#define SEGSEL_IVA09H 0x39 // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.652VDD 1/4bias=0.714VDD +#define SEGSEL_IVA0AH 0x3A // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.628VDD 1/4bias=0.692VDD +#define SEGSEL_IVA0BH 0x3B // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.605VDD 1/4bias=0.672VDD +#define SEGSEL_IVA0CH 0x3C // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.584VDD 1/4bias=0.652VDD +#define SEGSEL_IVA0DH 0x3D // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.565VDD 1/4bias=0.634VDD +#define SEGSEL_IVA0EH 0x3E // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.547VDD 1/4bias=0.616VDD +#define SEGSEL_IVA0FH 0x3F // SEG/VLCD共用脚设为SEG，内部å置电压调整：1/3bias=0.529VDD 1/4bias=0.600VDD + +#endif diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 3bd5f7d240629..60a18db80427f 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3567,7 +3567,7 @@ static int __init clk_debug_init(void) { struct clk_core *core; -#ifdef CLOCK_ALLOW_WRITE_DEBUGFS +#if 0 pr_warn("\n"); pr_warn("********************************************************************\n"); pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index f804618f9bb73..1c0deb1e08242 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -1628,6 +1628,8 @@ int dma_buf_vmap(struct dma_buf *dmabuf, struct iosys_map *map) if (WARN_ON(!dmabuf)) return -EINVAL; + dma_resv_assert_held(dmabuf->resv); + if (!dmabuf->ops->vmap) return -EINVAL; @@ -1656,6 +1658,33 @@ int dma_buf_vmap(struct dma_buf *dmabuf, struct iosys_map *map) } EXPORT_SYMBOL_NS_GPL(dma_buf_vmap, DMA_BUF); +/** + * dma_buf_vmap_unlocked - Create virtual mapping for the buffer object into kernel + * address space. Same restrictions as for vmap and friends apply. + * @dmabuf: [in] buffer to vmap + * @map: [out] returns the vmap pointer + * + * Unlocked version of dma_buf_vmap() + * + * Returns 0 on success, or a negative errno code otherwise. + */ +int dma_buf_vmap_unlocked(struct dma_buf *dmabuf, struct iosys_map *map) +{ + int ret; + + iosys_map_clear(map); + + if (WARN_ON(!dmabuf)) + return -EINVAL; + + dma_resv_lock(dmabuf->resv, NULL); + ret = dma_buf_vmap(dmabuf, map); + dma_resv_unlock(dmabuf->resv); + + return ret; +} +EXPORT_SYMBOL_NS_GPL(dma_buf_vmap_unlocked, DMA_BUF); + /** * dma_buf_vunmap - Unmap a vmap obtained by dma_buf_vmap. * @dmabuf: [in] buffer to vunmap @@ -1666,6 +1695,8 @@ void dma_buf_vunmap(struct dma_buf *dmabuf, struct iosys_map *map) if (WARN_ON(!dmabuf)) return; + dma_resv_assert_held(dmabuf->resv); + BUG_ON(iosys_map_is_null(&dmabuf->vmap_ptr)); BUG_ON(dmabuf->vmapping_counter == 0); BUG_ON(!iosys_map_is_equal(&dmabuf->vmap_ptr, map)); @@ -1680,6 +1711,22 @@ void dma_buf_vunmap(struct dma_buf *dmabuf, struct iosys_map *map) } EXPORT_SYMBOL_NS_GPL(dma_buf_vunmap, DMA_BUF); +/** + * dma_buf_vunmap_unlocked - Unmap a vmap obtained by dma_buf_vmap. + * @dmabuf: [in] buffer to vunmap + * @map: [in] vmap pointer to vunmap + */ +void dma_buf_vunmap_unlocked(struct dma_buf *dmabuf, struct iosys_map *map) +{ + if (WARN_ON(!dmabuf)) + return; + + dma_resv_lock(dmabuf->resv, NULL); + dma_buf_vunmap(dmabuf, map); + dma_resv_unlock(dmabuf->resv); +} +EXPORT_SYMBOL_NS_GPL(dma_buf_vunmap_unlocked, DMA_BUF); + #ifdef CONFIG_DEBUG_FS static int dma_buf_debug_show(struct seq_file *s, void *unused) { diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index eef4786aaf862..8aa8f8cb7071e 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -913,6 +913,65 @@ dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, } EXPORT_SYMBOL(dma_fence_wait_any_timeout); +/** + * DOC: deadline hints + * + * In an ideal world, it would be possible to pipeline a workload sufficiently + * that a utilization based device frequency governor could arrive at a minimum + * frequency that meets the requirements of the use-case, in order to minimize + * power consumption. But in the real world there are many workloads which + * defy this ideal. For example, but not limited to: + * + * * Workloads that ping-pong between device and CPU, with alternating periods + * of CPU waiting for device, and device waiting on CPU. This can result in + * devfreq and cpufreq seeing idle time in their respective domains and in + * result reduce frequency. + * + * * Workloads that interact with a periodic time based deadline, such as double + * buffered GPU rendering vs vblank sync'd page flipping. In this scenario, + * missing a vblank deadline results in an *increase* in idle time on the GPU + * (since it has to wait an additional vblank period), sending a signal to + * the GPU's devfreq to reduce frequency, when in fact the opposite is what is + * needed. + * + * To this end, deadline hint(s) can be set on a &dma_fence via &dma_fence_set_deadline. + * The deadline hint provides a way for the waiting driver, or userspace, to + * convey an appropriate sense of urgency to the signaling driver. + * + * A deadline hint is given in absolute ktime (CLOCK_MONOTONIC for userspace + * facing APIs). The time could either be some point in the future (such as + * the vblank based deadline for page-flipping, or the start of a compositor's + * composition cycle), or the current time to indicate an immediate deadline + * hint (Ie. forward progress cannot be made until this fence is signaled). + * + * Multiple deadlines may be set on a given fence, even in parallel. See the + * documentation for &dma_fence_ops.set_deadline. + * + * The deadline hint is just that, a hint. The driver that created the fence + * may react by increasing frequency, making different scheduling choices, etc. + * Or doing nothing at all. + */ + +/** + * dma_fence_set_deadline - set desired fence-wait deadline hint + * @fence: the fence that is to be waited on + * @deadline: the time by which the waiter hopes for the fence to be + * signaled + * + * Give the fence signaler a hint about an upcoming deadline, such as + * vblank, by which point the waiter would prefer the fence to be + * signaled by. This is intended to give feedback to the fence signaler + * to aid in power management decisions, such as boosting GPU frequency + * if a periodic vblank deadline is approaching but the fence is not + * yet signaled.. + */ +void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline) +{ + if (fence->ops->set_deadline && !dma_fence_is_signaled(fence)) + fence->ops->set_deadline(fence, deadline); +} +EXPORT_SYMBOL(dma_fence_set_deadline); + /** * dma_fence_describe - Dump fence describtion into seq_file * @fence: the 6fence to describe diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index 4dd52a6a5b48d..f6941353b58e7 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -190,4 +190,14 @@ config EXTCON_USBC_TUSB320 Say Y here to enable support for USB Type C cable detection extcon support using a TUSB320. +config EXTCON_USBC_VIRTUAL_PD + tristate "Virtual Type-C PD EXTCON support" + depends on GPIOLIB || COMPILE_TEST + help + Say Y here to enable Virtual Type-C PD extcon driver support, if + hardware platform designed Type-C modes separately. + + Example, of designing Display Port separately from Type-C Altmode + instead of accessing Altmode Display Port in Type-C connector. + endif diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile index 1b390d934ca92..306019ae9c37b 100644 --- a/drivers/extcon/Makefile +++ b/drivers/extcon/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_EXTCON_SM5502) += extcon-sm5502.o obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o +obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-pd-virtual.o \ No newline at end of file diff --git a/drivers/extcon/extcon-pd-virtual.c b/drivers/extcon/extcon-pd-virtual.c new file mode 100644 index 0000000000000..b186ea5eb2850 --- /dev/null +++ b/drivers/extcon/extcon-pd-virtual.c @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct virtual_pd { + struct extcon_dev *extcon; + struct gpio_desc *gpio_irq; + struct regulator *dp_pwr; + struct device *dev; + bool flip; + bool usb_ss; + bool enable; + u8 mode; + int irq; + int enable_irq; + u8 plug_state; + struct workqueue_struct *virtual_pd_wq; + spinlock_t irq_lock; + struct delayed_work irq_work; + int shake_lev; +}; + +static const unsigned int vpd_cable[] = { + EXTCON_USB, + EXTCON_USB_HOST, + EXTCON_USB_VBUS_EN, + EXTCON_CHG_USB_SDP, + EXTCON_CHG_USB_CDP, + EXTCON_CHG_USB_DCP, +/* + FIXME: There's no real pd phy, control the charging is very + dangerous, just rely on the BC detection. We don't use slow + and fast. +*/ + EXTCON_CHG_USB_SLOW, + EXTCON_CHG_USB_FAST, + EXTCON_DISP_DP, + EXTCON_NONE, +}; + +enum vpd_mode { + VPD_DFP = 0, + VPD_UFP, + VPD_DP, + VPD_DP_UFP, +}; + +static void vpd_set_vbus_enable(struct virtual_pd *vpd, bool enable) +{ + extcon_set_state(vpd->extcon, EXTCON_USB_VBUS_EN, enable); + extcon_sync(vpd->extcon, EXTCON_USB_VBUS_EN); +} + +static void vpd_extcon_notify(struct virtual_pd *vpd, bool flip, bool usb_ss, + bool dfp, bool ufp, bool dp) +{ + union extcon_property_value property; + + property.intval = flip; + extcon_set_property(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_TYPEC_POLARITY, property); + extcon_set_property(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_TYPEC_POLARITY, property); + extcon_set_property(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_TYPEC_POLARITY, property); + + property.intval = usb_ss; + extcon_set_property(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_SS, property); + extcon_set_property(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_SS, property); + extcon_set_property(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_SS, property); + extcon_set_state(vpd->extcon, EXTCON_USB, ufp); + extcon_set_state(vpd->extcon, EXTCON_USB_HOST, dfp); + extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp); + extcon_sync(vpd->extcon, EXTCON_USB); + extcon_sync(vpd->extcon, EXTCON_USB_HOST); + extcon_sync(vpd->extcon, EXTCON_DISP_DP); +} + +static void vpd_extcon_notify_set(struct virtual_pd *vpd) +{ + bool flip = vpd->flip, usb_ss = vpd->usb_ss; + bool dfp = 0, ufp = 0, dp = 0; + + switch (vpd->mode) { + case VPD_DFP: + dfp = 1; + break; + case VPD_DP: + dp = 1; + dfp = 1; + break; + case VPD_DP_UFP: + dp = 1; + ufp = 1; + break; + case VPD_UFP: + /* fall through */ + default: + ufp = 1; + break; + } + + vpd_set_vbus_enable(vpd, !ufp); + vpd_extcon_notify(vpd, flip, usb_ss, dfp, ufp, dp); +} + +static void vpd_extcon_notify_clr(struct virtual_pd *vpd) +{ + vpd_set_vbus_enable(vpd, 0); + vpd_extcon_notify(vpd, vpd->flip, vpd->usb_ss, 0, 0, 0); +} + +void vpd_irq_disable(struct virtual_pd *vpd) +{ + unsigned long irqflags = 0; + + spin_lock_irqsave(&vpd->irq_lock, irqflags); + if (!vpd->enable_irq) { + disable_irq_nosync(vpd->irq); + vpd->enable_irq = 1; + } else { + dev_warn(vpd->dev, "irq have already disabled\n"); + } + spin_unlock_irqrestore(&vpd->irq_lock, irqflags); +} + +void vpd_irq_enable(struct virtual_pd *vpd) +{ + unsigned long irqflags = 0; + + spin_lock_irqsave(&vpd->irq_lock, irqflags); + if (vpd->enable_irq) { + enable_irq(vpd->irq); + vpd->enable_irq = 0; + } + spin_unlock_irqrestore(&vpd->irq_lock, irqflags); +} + +static void extcon_pd_delay_irq_work(struct work_struct *work) +{ + struct virtual_pd *vpd = + container_of(work, struct virtual_pd, irq_work.work); + int lev; + + lev = gpiod_get_raw_value(vpd->gpio_irq); + + if (vpd->shake_lev != lev) { + vpd_irq_enable(vpd); + return; + } + + switch (vpd->plug_state) { + case 1: + if (lev == 0) { + vpd->enable = false; + vpd_extcon_notify_clr(vpd); + vpd->plug_state=0; + } + break; + case 0: + if (lev == 1) { + vpd->enable = true; + vpd_extcon_notify_set(vpd); + vpd->plug_state=1; + } + break; + default: + break; + } + vpd_irq_enable(vpd); +} + +static irqreturn_t dp_det_irq_handler(int irq, void *dev_id) +{ + struct virtual_pd *vpd = dev_id; + int lev; + lev = gpiod_get_raw_value(vpd->gpio_irq); + vpd->shake_lev = lev; + schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10)); + vpd_irq_disable(vpd); + return IRQ_HANDLED; +} + +static void vpd_extcon_init(struct virtual_pd *vpd) +{ + struct device *dev = vpd->dev; + u32 tmp = 0; + int ret = 0; + + ret = device_property_read_u32(dev, "vpd,init-flip", &tmp); + if (ret < 0) + vpd->flip = 0; + else + vpd->flip = tmp; + dev_dbg(dev, "init-flip = %d\n", vpd->flip); + + ret = device_property_read_u32(dev, "vpd,init-ss", &tmp); + if (ret < 0) + vpd->usb_ss = 0; + else + vpd->usb_ss = tmp; + dev_dbg(dev, "init-ss = %d\n", vpd->usb_ss); + + ret = device_property_read_u32(dev, "vpd,init-mode", &tmp); + if (ret < 0) + vpd->mode = 0; + else + vpd->mode = tmp; + dev_dbg(dev, "init-mode = %d\n", vpd->mode); + + if(gpiod_get_raw_value(vpd->gpio_irq)) { + vpd_extcon_notify_set(vpd); + vpd->plug_state=1; + } +} + +static int vpd_extcon_probe(struct platform_device *pdev) +{ + struct virtual_pd *vpd; + struct device *dev = &pdev->dev; + int ret = 0; + + dev_info(dev, "probe start\n"); + + vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL); + if (!vpd) + return -ENOMEM; + + vpd->dev = dev; + dev_set_drvdata(dev, vpd); + vpd->enable = 1; + + vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable); + if (IS_ERR(vpd->extcon)) { + dev_err(dev, "allocat extcon failed\n"); + return PTR_ERR(vpd->extcon); + } + + ret = devm_extcon_dev_register(dev, vpd->extcon); + if (ret) { + dev_err(dev, "register extcon failed: %d\n", ret); + return ret; + } + + vpd->gpio_irq = devm_gpiod_get_optional(dev,"hpd", GPIOD_IN); + if (IS_ERR(vpd->gpio_irq)) { + dev_warn(dev, "maybe miss named GPIO for hpd\n"); + vpd->gpio_irq = NULL; + } + + vpd->dp_pwr = devm_regulator_get_optional(dev, "dp-pwr"); + if (IS_ERR(vpd->dp_pwr)) { + dev_warn(dev, "failed to get dp-pwr\n"); + vpd->dp_pwr = NULL; + } + + ret = regulator_enable(vpd->dp_pwr); + if (ret) + dev_warn(dev, "failed to enable dp-pwr\n"); + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set USB property capability failed: %d\n", ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set USB_HOST property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set DISP_DP property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB, + EXTCON_PROP_USB_SS); + if (ret) { + dev_err(dev, + "set USB USB_SS property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, + EXTCON_PROP_USB_SS); + if (ret) { + dev_err(dev, + "set USB_HOST USB_SS property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, + EXTCON_PROP_USB_SS); + if (ret) { + dev_err(dev, + "set DISP_DP USB_SS property capability failed: %d\n", + ret); + return ret; + } + + ret = extcon_set_property_capability(vpd->extcon, EXTCON_CHG_USB_FAST, + EXTCON_PROP_USB_TYPEC_POLARITY); + if (ret) { + dev_err(dev, + "set USB_PD property capability failed: %d\n", ret); + return ret; + } + + vpd_extcon_init(vpd); + INIT_DELAYED_WORK(&vpd->irq_work, extcon_pd_delay_irq_work); + + vpd->irq=gpiod_to_irq(vpd->gpio_irq); + if (vpd->irq){ + ret = devm_request_threaded_irq(dev, + vpd->irq, + NULL, + dp_det_irq_handler, + IRQF_TRIGGER_FALLING |IRQF_TRIGGER_RISING | IRQF_ONESHOT , + NULL, + vpd); + } + else + dev_err(dev,"gpio can not be irq !\n"); + + vpd->virtual_pd_wq = create_workqueue("virtual_pd_wq"); + + dev_info(dev, "probe success\n"); + + return 0; +} + +static int vpd_extcon_remove(struct platform_device *pdev) +{ + struct virtual_pd *vpd = platform_get_drvdata(pdev); + + regulator_disable(vpd->dp_pwr); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int vpd_extcon_suspend(struct device *dev) +{ + struct virtual_pd *vpd = dev_get_drvdata(dev); + + int lev=0; + lev = gpiod_get_raw_value(vpd->gpio_irq); + cancel_delayed_work_sync(&vpd->irq_work); + vpd_irq_disable(vpd); + return 0; +} + +static int vpd_extcon_resume(struct device *dev) +{ + struct virtual_pd *vpd = dev_get_drvdata(dev); + vpd_irq_enable(vpd); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops, + vpd_extcon_suspend, vpd_extcon_resume); + +static const struct of_device_id vpd_extcon_dt_match[] = { + { .compatible = "linux,extcon-pd-virtual", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vpd_extcon_dt_match); + +static struct platform_driver vpd_extcon_driver = { + .probe = vpd_extcon_probe, + .remove = vpd_extcon_remove, + .driver = { + .name = "extcon-pd-virtual", + .pm = &vpd_extcon_pm_ops, + .of_match_table = vpd_extcon_dt_match, + }, +}; + +static int __init __vpd_extcon_init(void) +{ + return platform_driver_register(&vpd_extcon_driver); +} + +static void __exit __vpd_extcon_exit(void) +{ + platform_driver_unregister(&vpd_extcon_driver); +} + +module_init(__vpd_extcon_init); +module_exit(__vpd_extcon_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("rockchip"); +MODULE_DESCRIPTION("Virtual Typec-pd extcon driver"); \ No newline at end of file diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index cd641b1bce7b7..ad3d8284419ad 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -207,6 +207,19 @@ config DRM_TTM GPU memory types. Will be enabled automatically if a device driver uses it. +config DRM_EXEC + tristate + depends on DRM + help + Execution context for command submissions + +config DRM_GPUVM + tristate + depends on DRM + help + GPU-VM representation providing helpers to manage a GPUs virtual + address space + config DRM_BUDDY tristate depends on DRM @@ -415,6 +428,8 @@ source "drivers/gpu/drm/lima/Kconfig" source "drivers/gpu/drm/panfrost/Kconfig" +source "drivers/gpu/drm/panthor/Kconfig" + source "drivers/gpu/drm/aspeed/Kconfig" source "drivers/gpu/drm/mcde/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index c611154667c20..dbb6173fc10b3 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -40,6 +40,9 @@ obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += drm_panel_orientation_quirks.o # # Memory-management helpers # +# +obj-$(CONFIG_DRM_EXEC) += drm_exec.o +obj-$(CONFIG_DRM_GPUVM) += drm_gpuvm.o obj-$(CONFIG_DRM_BUDDY) += drm_buddy.o @@ -141,6 +144,7 @@ obj-$(CONFIG_DRM_XEN) += xen/ obj-$(CONFIG_DRM_VBOXVIDEO) += vboxvideo/ obj-$(CONFIG_DRM_LIMA) += lima/ obj-$(CONFIG_DRM_PANFROST) += panfrost/ +obj-$(CONFIG_DRM_PANTHOR) += panthor/ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ obj-$(CONFIG_DRM_MCDE) += mcde/ obj-$(CONFIG_DRM_TIDSS) += tidss/ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 1ed2142a6e7bf..76ff7b17b6c1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -68,10 +68,10 @@ amdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio) return DRM_SCHED_PRIORITY_NORMAL; case AMDGPU_CTX_PRIORITY_VERY_LOW: - return DRM_SCHED_PRIORITY_MIN; + return DRM_SCHED_PRIORITY_LOW; case AMDGPU_CTX_PRIORITY_LOW: - return DRM_SCHED_PRIORITY_MIN; + return DRM_SCHED_PRIORITY_LOW; case AMDGPU_CTX_PRIORITY_NORMAL: return DRM_SCHED_PRIORITY_NORMAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 06ab6066da61a..d68f6f2277223 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1501,9 +1501,9 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) for (i = 0; i < AMDGPU_MAX_RINGS; i++) { struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; - kthread_park(ring->sched.thread); + drm_sched_wqueue_stop(&ring->sched); } seq_printf(m, "run ib test:\n"); @@ -1517,9 +1517,9 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) for (i = 0; i < AMDGPU_MAX_RINGS; i++) { struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; - kthread_unpark(ring->sched.thread); + drm_sched_wqueue_start(&ring->sched); } up_write(&adev->reset_domain->sem); @@ -1739,7 +1739,8 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) ring = adev->rings[val]; - if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread) + if (!ring || !ring->funcs->preempt_ib || + !drm_sched_wqueue_ready(&ring->sched)) return -EINVAL; /* the last preemption failed */ @@ -1757,7 +1758,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) goto pro_end; /* stop the scheduler */ - kthread_park(ring->sched.thread); + drm_sched_wqueue_stop(&ring->sched); resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); @@ -1793,7 +1794,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) failure: /* restart the scheduler */ - kthread_unpark(ring->sched.thread); + drm_sched_wqueue_start(&ring->sched); up_read(&adev->reset_domain->sem); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6a4749c0c5a58..ed99a14efa5c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2354,7 +2354,8 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) break; } - r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, + r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL, + DRM_SCHED_PRIORITY_COUNT, ring->num_hw_submission, amdgpu_job_hang_limit, timeout, adev->reset_domain->wq, ring->sched_score, ring->name, @@ -4650,7 +4651,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev) for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; spin_lock(&ring->sched.job_list_lock); @@ -4777,7 +4778,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; /*clear job fence from fence drv to avoid force_completion @@ -5176,94 +5177,6 @@ static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) return 0; } -static void amdgpu_device_recheck_guilty_jobs( - struct amdgpu_device *adev, struct list_head *device_list_handle, - struct amdgpu_reset_context *reset_context) -{ - int i, r = 0; - - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - struct amdgpu_ring *ring = adev->rings[i]; - int ret = 0; - struct drm_sched_job *s_job; - - if (!ring || !ring->sched.thread) - continue; - - s_job = list_first_entry_or_null(&ring->sched.pending_list, - struct drm_sched_job, list); - if (s_job == NULL) - continue; - - /* clear job's guilty and depend the folowing step to decide the real one */ - drm_sched_reset_karma(s_job); - drm_sched_resubmit_jobs_ext(&ring->sched, 1); - - if (!s_job->s_fence->parent) { - DRM_WARN("Failed to get a HW fence for job!"); - continue; - } - - ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout); - if (ret == 0) { /* timeout */ - DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n", - ring->sched.name, s_job->id); - - - amdgpu_fence_driver_isr_toggle(adev, true); - - /* Clear this failed job from fence array */ - amdgpu_fence_driver_clear_job_fences(ring); - - amdgpu_fence_driver_isr_toggle(adev, false); - - /* Since the job won't signal and we go for - * another resubmit drop this parent pointer - */ - dma_fence_put(s_job->s_fence->parent); - s_job->s_fence->parent = NULL; - - /* set guilty */ - drm_sched_increase_karma(s_job); - amdgpu_reset_prepare_hwcontext(adev, reset_context); -retry: - /* do hw reset */ - if (amdgpu_sriov_vf(adev)) { - amdgpu_virt_fini_data_exchange(adev); - r = amdgpu_device_reset_sriov(adev, false); - if (r) - adev->asic_reset_res = r; - } else { - clear_bit(AMDGPU_SKIP_HW_RESET, - &reset_context->flags); - r = amdgpu_do_asic_reset(device_list_handle, - reset_context); - if (r && r == -EAGAIN) - goto retry; - } - - /* - * add reset counter so that the following - * resubmitted job could flush vmid - */ - atomic_inc(&adev->gpu_reset_counter); - continue; - } - - /* got the hw fence, signal finished fence */ - atomic_dec(ring->sched.score); - dma_fence_get(&s_job->s_fence->finished); - dma_fence_signal(&s_job->s_fence->finished); - dma_fence_put(&s_job->s_fence->finished); - - /* remove node from list and free the job */ - spin_lock(&ring->sched.job_list_lock); - list_del_init(&s_job->list); - spin_unlock(&ring->sched.job_list_lock); - ring->sched.ops->free_job(s_job); - } -} - static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); @@ -5284,7 +5197,6 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) } - /** * amdgpu_device_gpu_recover - reset the asic and recover scheduler * @@ -5307,7 +5219,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, int i, r = 0; bool need_emergency_restart = false; bool audio_suspended = false; - int tmp_vram_lost_counter; bool gpu_reset_for_dev_remove = false; gpu_reset_for_dev_remove = @@ -5407,7 +5318,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = tmp_adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; drm_sched_stop(&ring->sched, job ? &job->base : NULL); @@ -5454,7 +5365,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, amdgpu_device_stop_pending_resets(tmp_adev); } - tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); /* Actual ASIC resets if needed.*/ /* Host driver will handle XGMI hive reset for SRIOV */ if (amdgpu_sriov_vf(adev)) { @@ -5479,29 +5389,17 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, /* Post ASIC reset for all devs .*/ list_for_each_entry(tmp_adev, device_list_handle, reset_list) { - /* - * Sometimes a later bad compute job can block a good gfx job as gfx - * and compute ring share internal GC HW mutually. We add an additional - * guilty jobs recheck step to find the real guilty job, it synchronously - * submits and pends for the first job being signaled. If it gets timeout, - * we identify it as a real guilty job. - */ - if (amdgpu_gpu_recovery == 2 && - !(tmp_vram_lost_counter < atomic_read(&adev->vram_lost_counter))) - amdgpu_device_recheck_guilty_jobs( - tmp_adev, device_list_handle, reset_context); - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = tmp_adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; /* No point to resubmit jobs if we didn't HW reset*/ if (!tmp_adev->asic_reset_res && !job_signaled) drm_sched_resubmit_jobs(&ring->sched); - drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); + drm_sched_start(&ring->sched); } if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)) @@ -5823,7 +5721,7 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; drm_sched_stop(&ring->sched, NULL); @@ -5951,12 +5849,12 @@ void amdgpu_pci_resume(struct pci_dev *pdev) for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->sched.thread) + if (!ring || !drm_sched_wqueue_ready(&ring->sched)) continue; drm_sched_resubmit_jobs(&ring->sched); - drm_sched_start(&ring->sched, true); + drm_sched_start(&ring->sched); } amdgpu_device_unset_mp1_state(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f24c3a20e901d..15da11f0c594e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -534,7 +534,7 @@ module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); * DOC: gpu_recovery (int) * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). */ -MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); +MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); /** @@ -2810,8 +2810,6 @@ static const struct drm_driver amdgpu_kms_driver = { .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = amdgpu_gem_prime_import, .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 3bf0e893c07df..8043d9b92fac8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -111,6 +111,8 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; return 0; + + return drm_sched_job_init(&(*job)->base, entity, 1, owner); } int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, @@ -248,7 +250,8 @@ int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, return 0; } -static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, +static struct dma_fence * +amdgpu_job_prepare_job(struct drm_sched_job *sched_job, struct drm_sched_entity *s_entity) { struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); @@ -326,8 +329,8 @@ void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) int i; /* Signal all jobs not yet scheduled */ - for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) { - struct drm_sched_rq *rq = &sched->sched_rq[i]; + for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { + struct drm_sched_rq *rq = sched->sched_rq[i]; spin_lock(&rq->lock); list_for_each_entry(s_entity, &rq->entities, list) { while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { @@ -351,7 +354,7 @@ void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) } const struct drm_sched_backend_ops amdgpu_sched_ops = { - .dependency = amdgpu_job_dependency, + .prepare_job = amdgpu_job_prepare_job, .run_job = amdgpu_job_run, .timedout_job = amdgpu_job_timedout, .free_job = amdgpu_job_free_cb diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c index 688ba358f5319..147bf1723bffd 100644 --- a/drivers/gpu/drm/armada/armada_drv.c +++ b/drivers/gpu/drm/armada/armada_drv.c @@ -38,8 +38,6 @@ DEFINE_DRM_GEM_FOPS(armada_drm_fops); static const struct drm_driver armada_drm_driver = { .lastclose = drm_fb_helper_lastclose, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = armada_gem_prime_import, .dumb_create = armada_gem_dumb_create, .major = 1, diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index c791e2826916a..563c8fa367835 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -1007,6 +1007,8 @@ static const struct hdmi_quirk *get_hdmi_quirk(u8 *vendor_id) static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) { + u32 ddc_i2c_rxfilter; + u64 scl_high_cnt, scl_low_cnt, val; scl_high_cnt = hdmi->i2c->scl_high_ns; @@ -1023,6 +1025,10 @@ static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) /* Software reset */ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); + /* Configure I2CM hold time and rxfilter */ + if (device_property_read_u32(hdmi->dev, "ddc-i2c-rxfilter", &ddc_i2c_rxfilter) == 0) + hdmi_writel(hdmi, ddc_i2c_rxfilter, I2CM_CONFIG0); + hdmi_writel(hdmi, val, I2CM_SM_SCL_CONFIG0); hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); @@ -3739,6 +3745,15 @@ void dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp *hdmi, bool plug_in, bool change) if (!plug_in) cec_notifier_set_phys_addr(hdmi->cec_notifier, CEC_PHYS_ADDR_INVALID); + else if (hdmi->ddc) { + struct edid *edid = drm_get_edid(&hdmi->connector, hdmi->ddc); + if (edid) { + if (hdmi->cec_notifier) + cec_notifier_set_phys_addr_from_edid( + hdmi->cec_notifier, edid); + kfree(edid); + } + } if (hdmi->bridge.dev) { #if IS_REACHABLE(CONFIG_DRM_DW_HDMI_CEC) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 619f08947a44a..042064842b61d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -363,6 +363,15 @@ static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) { if (hdmi->plugged_cb && hdmi->codec_dev) hdmi->plugged_cb(hdmi->codec_dev, plugged); + if (plugged && hdmi->ddc) { + struct edid *edid = drm_get_edid(&hdmi->connector, hdmi->ddc); + if (edid) { + if (hdmi->cec_notifier) + cec_notifier_set_phys_addr_from_edid( + hdmi->cec_notifier, edid); + kfree(edid); + } + } } int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c index dcbeeb68ca641..11de319ac6d90 100644 --- a/drivers/gpu/drm/drm_client.c +++ b/drivers/gpu/drm/drm_client.c @@ -344,7 +344,7 @@ drm_client_buffer_vmap(struct drm_client_buffer *buffer, * fd_install step out of the driver backend hooks, to make that * final step optional for internal users. */ - ret = drm_gem_vmap(buffer->gem, map); + ret = drm_gem_vmap_unlocked(buffer->gem, map); if (ret) return ret; @@ -366,7 +366,7 @@ void drm_client_buffer_vunmap(struct drm_client_buffer *buffer) { struct iosys_map *map = &buffer->map; - drm_gem_vunmap(buffer->gem, map); + drm_gem_vunmap_unlocked(buffer->gem, map); } EXPORT_SYMBOL(drm_client_buffer_vunmap); diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c new file mode 100644 index 0000000000000..48ee851b61d90 --- /dev/null +++ b/drivers/gpu/drm/drm_exec.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include +#include +#include + +/** + * DOC: Overview + * + * This component mainly abstracts the retry loop necessary for locking + * multiple GEM objects while preparing hardware operations (e.g. command + * submissions, page table updates etc..). + * + * If a contention is detected while locking a GEM object the cleanup procedure + * unlocks all previously locked GEM objects and locks the contended one first + * before locking any further objects. + * + * After an object is locked fences slots can optionally be reserved on the + * dma_resv object inside the GEM object. + * + * A typical usage pattern should look like this:: + * + * struct drm_gem_object *obj; + * struct drm_exec exec; + * unsigned long index; + * int ret; + * + * drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT); + * drm_exec_until_all_locked(&exec) { + * ret = drm_exec_prepare_obj(&exec, boA, 1); + * drm_exec_retry_on_contention(&exec); + * if (ret) + * goto error; + * + * ret = drm_exec_prepare_obj(&exec, boB, 1); + * drm_exec_retry_on_contention(&exec); + * if (ret) + * goto error; + * } + * + * drm_exec_for_each_locked_object(&exec, index, obj) { + * dma_resv_add_fence(obj->resv, fence, DMA_RESV_USAGE_READ); + * ... + * } + * drm_exec_fini(&exec); + * + * See struct dma_exec for more details. + */ + +/* Dummy value used to initially enter the retry loop */ +#define DRM_EXEC_DUMMY ((void *)~0) + +/* Unlock all objects and drop references */ +static void drm_exec_unlock_all(struct drm_exec *exec) +{ + struct drm_gem_object *obj; + unsigned long index; + + drm_exec_for_each_locked_object_reverse(exec, index, obj) { + dma_resv_unlock(obj->resv); + drm_gem_object_put(obj); + } + + drm_gem_object_put(exec->prelocked); + exec->prelocked = NULL; +} + +/** + * drm_exec_init - initialize a drm_exec object + * @exec: the drm_exec object to initialize + * @flags: controls locking behavior, see DRM_EXEC_* defines + * @nr: the initial # of objects + * + * Initialize the object and make sure that we can track locked objects. + * + * If nr is non-zero then it is used as the initial objects table size. + * In either case, the table will grow (be re-allocated) on demand. + */ +void drm_exec_init(struct drm_exec *exec, uint32_t flags, unsigned nr) +{ + if (!nr) + nr = PAGE_SIZE / sizeof(void *); + + exec->flags = flags; + exec->objects = kvmalloc_array(nr, sizeof(void *), GFP_KERNEL); + + /* If allocation here fails, just delay that till the first use */ + exec->max_objects = exec->objects ? nr : 0; + exec->num_objects = 0; + exec->contended = DRM_EXEC_DUMMY; + exec->prelocked = NULL; +} +EXPORT_SYMBOL(drm_exec_init); + +/** + * drm_exec_fini - finalize a drm_exec object + * @exec: the drm_exec object to finalize + * + * Unlock all locked objects, drop the references to objects and free all memory + * used for tracking the state. + */ +void drm_exec_fini(struct drm_exec *exec) +{ + drm_exec_unlock_all(exec); + kvfree(exec->objects); + if (exec->contended != DRM_EXEC_DUMMY) { + drm_gem_object_put(exec->contended); + ww_acquire_fini(&exec->ticket); + } +} +EXPORT_SYMBOL(drm_exec_fini); + +/** + * drm_exec_cleanup - cleanup when contention is detected + * @exec: the drm_exec object to cleanup + * + * Cleanup the current state and return true if we should stay inside the retry + * loop, false if there wasn't any contention detected and we can keep the + * objects locked. + */ +bool drm_exec_cleanup(struct drm_exec *exec) +{ + if (likely(!exec->contended)) { + ww_acquire_done(&exec->ticket); + return false; + } + + if (likely(exec->contended == DRM_EXEC_DUMMY)) { + exec->contended = NULL; + ww_acquire_init(&exec->ticket, &reservation_ww_class); + return true; + } + + drm_exec_unlock_all(exec); + exec->num_objects = 0; + return true; +} +EXPORT_SYMBOL(drm_exec_cleanup); + +/* Track the locked object in the array */ +static int drm_exec_obj_locked(struct drm_exec *exec, + struct drm_gem_object *obj) +{ + if (unlikely(exec->num_objects == exec->max_objects)) { + size_t size = exec->max_objects * sizeof(void *); + void *tmp; + + tmp = kvrealloc(exec->objects, size, size + PAGE_SIZE, + GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + exec->objects = tmp; + exec->max_objects += PAGE_SIZE / sizeof(void *); + } + drm_gem_object_get(obj); + exec->objects[exec->num_objects++] = obj; + + return 0; +} + +/* Make sure the contended object is locked first */ +static int drm_exec_lock_contended(struct drm_exec *exec) +{ + struct drm_gem_object *obj = exec->contended; + int ret; + + if (likely(!obj)) + return 0; + + /* Always cleanup the contention so that error handling can kick in */ + exec->contended = NULL; + if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { + ret = dma_resv_lock_slow_interruptible(obj->resv, + &exec->ticket); + if (unlikely(ret)) + goto error_dropref; + } else { + dma_resv_lock_slow(obj->resv, &exec->ticket); + } + + ret = drm_exec_obj_locked(exec, obj); + if (unlikely(ret)) + goto error_unlock; + + exec->prelocked = obj; + return 0; + +error_unlock: + dma_resv_unlock(obj->resv); + +error_dropref: + drm_gem_object_put(obj); + return ret; +} + +/** + * drm_exec_lock_obj - lock a GEM object for use + * @exec: the drm_exec object with the state + * @obj: the GEM object to lock + * + * Lock a GEM object for use and grab a reference to it. + * + * Returns: -EDEADLK if a contention is detected, -EALREADY when object is + * already locked (can be suppressed by setting the DRM_EXEC_IGNORE_DUPLICATES + * flag), -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) +{ + int ret; + + ret = drm_exec_lock_contended(exec); + if (unlikely(ret)) + return ret; + + if (exec->prelocked == obj) { + drm_gem_object_put(exec->prelocked); + exec->prelocked = NULL; + return 0; + } + + if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) + ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + else + ret = dma_resv_lock(obj->resv, &exec->ticket); + + if (unlikely(ret == -EDEADLK)) { + drm_gem_object_get(obj); + exec->contended = obj; + return -EDEADLK; + } + + if (unlikely(ret == -EALREADY) && + exec->flags & DRM_EXEC_IGNORE_DUPLICATES) + return 0; + + if (unlikely(ret)) + return ret; + + ret = drm_exec_obj_locked(exec, obj); + if (ret) + goto error_unlock; + + return 0; + +error_unlock: + dma_resv_unlock(obj->resv); + return ret; +} +EXPORT_SYMBOL(drm_exec_lock_obj); + +/** + * drm_exec_unlock_obj - unlock a GEM object in this exec context + * @exec: the drm_exec object with the state + * @obj: the GEM object to unlock + * + * Unlock the GEM object and remove it from the collection of locked objects. + * Should only be used to unlock the most recently locked objects. It's not time + * efficient to unlock objects locked long ago. + */ +void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) +{ + unsigned int i; + + for (i = exec->num_objects; i--;) { + if (exec->objects[i] == obj) { + dma_resv_unlock(obj->resv); + for (++i; i < exec->num_objects; ++i) + exec->objects[i - 1] = exec->objects[i]; + --exec->num_objects; + drm_gem_object_put(obj); + return; + } + + } +} +EXPORT_SYMBOL(drm_exec_unlock_obj); + +/** + * drm_exec_prepare_obj - prepare a GEM object for use + * @exec: the drm_exec object with the state + * @obj: the GEM object to prepare + * @num_fences: how many fences to reserve + * + * Prepare a GEM object for use by locking it and reserving fence slots. + * + * Returns: -EDEADLK if a contention is detected, -EALREADY when object is + * already locked, -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, + unsigned int num_fences) +{ + int ret; + + ret = drm_exec_lock_obj(exec, obj); + if (ret) + return ret; + + ret = dma_resv_reserve_fences(obj->resv, num_fences); + if (ret) { + drm_exec_unlock_obj(exec, obj); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_exec_prepare_obj); + +/** + * drm_exec_prepare_array - helper to prepare an array of objects + * @exec: the drm_exec object with the state + * @objects: array of GEM object to prepare + * @num_objects: number of GEM objects in the array + * @num_fences: number of fences to reserve on each GEM object + * + * Prepares all GEM objects in an array, aborts on first error. + * Reserves @num_fences on each GEM object after locking it. + * + * Returns: -EDEADLOCK on contention, -EALREADY when object is already locked, + * -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_prepare_array(struct drm_exec *exec, + struct drm_gem_object **objects, + unsigned int num_objects, + unsigned int num_fences) +{ + int ret; + + for (unsigned int i = 0; i < num_objects; ++i) { + ret = drm_exec_prepare_obj(exec, objects[i], num_fences); + if (unlikely(ret)) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_exec_prepare_array); + +MODULE_DESCRIPTION("DRM execution context"); +MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index b87ed4238fc83..482a7964b851c 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -164,11 +164,28 @@ void drm_gem_private_object_init(struct drm_device *dev, if (!obj->resv) obj->resv = &obj->_resv; + if (drm_core_check_feature(dev, DRIVER_GEM_GPUVA)) + drm_gem_gpuva_init(obj); + drm_vma_node_reset(&obj->vma_node); INIT_LIST_HEAD(&obj->lru_node); } EXPORT_SYMBOL(drm_gem_private_object_init); +/** + * drm_gem_private_object_fini - Finalize a failed drm_gem_object + * @obj: drm_gem_object + * + * Uninitialize an already allocated GEM object when it initialized failed + */ +void drm_gem_private_object_fini(struct drm_gem_object *obj) +{ + WARN_ON(obj->dma_buf); + + dma_resv_fini(&obj->_resv); +} +EXPORT_SYMBOL(drm_gem_private_object_fini); + /** * drm_gem_object_handle_free - release resources bound to userspace handles * @obj: GEM object to clean up. @@ -930,12 +947,11 @@ drm_gem_release(struct drm_device *dev, struct drm_file *file_private) void drm_gem_object_release(struct drm_gem_object *obj) { - WARN_ON(obj->dma_buf); - if (obj->filp) fput(obj->filp); - dma_resv_fini(&obj->_resv); + drm_gem_private_object_fini(obj); + drm_gem_free_mmap_offset(obj); drm_gem_lru_remove(obj); } @@ -1158,6 +1174,8 @@ int drm_gem_vmap(struct drm_gem_object *obj, struct iosys_map *map) { int ret; + dma_resv_assert_held(obj->resv); + if (!obj->funcs->vmap) return -EOPNOTSUPP; @@ -1173,6 +1191,8 @@ EXPORT_SYMBOL(drm_gem_vmap); void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map) { + dma_resv_assert_held(obj->resv); + if (iosys_map_is_null(map)) return; @@ -1184,6 +1204,26 @@ void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map) } EXPORT_SYMBOL(drm_gem_vunmap); +int drm_gem_vmap_unlocked(struct drm_gem_object *obj, struct iosys_map *map) +{ + int ret; + + dma_resv_lock(obj->resv, NULL); + ret = drm_gem_vmap(obj, map); + dma_resv_unlock(obj->resv); + + return ret; +} +EXPORT_SYMBOL(drm_gem_vmap_unlocked); + +void drm_gem_vunmap_unlocked(struct drm_gem_object *obj, struct iosys_map *map) +{ + dma_resv_lock(obj->resv, NULL); + drm_gem_vunmap(obj, map); + dma_resv_unlock(obj->resv); +} +EXPORT_SYMBOL(drm_gem_vunmap_unlocked); + /** * drm_gem_lock_reservations - Sets up the ww context and acquires * the lock on an array of GEM objects. diff --git a/drivers/gpu/drm/drm_gem_dma_helper.c b/drivers/gpu/drm/drm_gem_dma_helper.c index f6901ff97bbb5..df89fbd2d35cd 100644 --- a/drivers/gpu/drm/drm_gem_dma_helper.c +++ b/drivers/gpu/drm/drm_gem_dma_helper.c @@ -230,7 +230,7 @@ void drm_gem_dma_free(struct drm_gem_dma_object *dma_obj) if (gem_obj->import_attach) { if (dma_obj->vaddr) - dma_buf_vunmap(gem_obj->import_attach->dmabuf, &map); + dma_buf_vunmap_unlocked(gem_obj->import_attach->dmabuf, &map); drm_prime_gem_destroy(gem_obj, dma_obj->sgt); } else if (dma_obj->vaddr) { if (dma_obj->map_noncoherent) @@ -477,8 +477,8 @@ drm_gem_dma_prime_import_sg_table(struct drm_device *dev, dma_obj->dma_addr = sg_dma_address(sgt->sgl); dma_obj->sgt = sgt; - DRM_DEBUG_PRIME("dma_addr = %pad, size = %zu\n", &dma_obj->dma_addr, - attach->dmabuf->size); + drm_dbg_prime(dev, "dma_addr = %pad, size = %zu\n", &dma_obj->dma_addr, + attach->dmabuf->size); return &dma_obj->base; } @@ -581,7 +581,7 @@ drm_gem_dma_prime_import_sg_table_vmap(struct drm_device *dev, struct iosys_map map; int ret; - ret = dma_buf_vmap(attach->dmabuf, &map); + ret = dma_buf_vmap_unlocked(attach->dmabuf, &map); if (ret) { DRM_ERROR("Failed to vmap PRIME buffer\n"); return ERR_PTR(ret); @@ -589,7 +589,7 @@ drm_gem_dma_prime_import_sg_table_vmap(struct drm_device *dev, obj = drm_gem_dma_prime_import_sg_table(dev, attach, sgt); if (IS_ERR(obj)) { - dma_buf_vunmap(attach->dmabuf, &map); + dma_buf_vunmap_unlocked(attach->dmabuf, &map); return obj; } diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index 880a4975507fc..e35e224e6303a 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -354,7 +354,7 @@ int drm_gem_fb_vmap(struct drm_framebuffer *fb, struct iosys_map *map, ret = -EINVAL; goto err_drm_gem_vunmap; } - ret = drm_gem_vmap(obj, &map[i]); + ret = drm_gem_vmap_unlocked(obj, &map[i]); if (ret) goto err_drm_gem_vunmap; } @@ -376,7 +376,7 @@ int drm_gem_fb_vmap(struct drm_framebuffer *fb, struct iosys_map *map, obj = drm_gem_fb_get_obj(fb, i); if (!obj) continue; - drm_gem_vunmap(obj, &map[i]); + drm_gem_vunmap_unlocked(obj, &map[i]); } return ret; } @@ -403,7 +403,7 @@ void drm_gem_fb_vunmap(struct drm_framebuffer *fb, struct iosys_map *map) continue; if (iosys_map_is_null(&map[i])) continue; - drm_gem_vunmap(obj, &map[i]); + drm_gem_vunmap_unlocked(obj, &map[i]); } } EXPORT_SYMBOL(drm_gem_fb_vunmap); diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index e33f06bb66eb4..926e893f65276 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -79,15 +79,15 @@ __drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private) } else { ret = drm_gem_object_init(dev, obj, size); } - if (ret) + if (ret) { + drm_gem_private_object_fini(obj); goto err_free; + } ret = drm_gem_create_mmap_offset(obj); if (ret) goto err_release; - mutex_init(&shmem->pages_lock); - mutex_init(&shmem->vmap_lock); INIT_LIST_HEAD(&shmem->madv_list); if (!private) { @@ -139,11 +139,13 @@ void drm_gem_shmem_free(struct drm_gem_shmem_object *shmem) { struct drm_gem_object *obj = &shmem->base; - WARN_ON(shmem->vmap_use_count); - if (obj->import_attach) { drm_prime_gem_destroy(obj, shmem->sgt); } else { + dma_resv_lock(shmem->base.resv, NULL); + + drm_WARN_ON(obj->dev, shmem->vmap_use_count); + if (shmem->sgt) { dma_unmap_sgtable(obj->dev->dev, shmem->sgt, DMA_BIDIRECTIONAL, 0); @@ -152,28 +154,31 @@ void drm_gem_shmem_free(struct drm_gem_shmem_object *shmem) } if (shmem->pages) drm_gem_shmem_put_pages(shmem); - } - WARN_ON(shmem->pages_use_count); + drm_WARN_ON(obj->dev, shmem->pages_use_count); + + dma_resv_unlock(shmem->base.resv); + } drm_gem_object_release(obj); - mutex_destroy(&shmem->pages_lock); - mutex_destroy(&shmem->vmap_lock); kfree(shmem); } EXPORT_SYMBOL_GPL(drm_gem_shmem_free); -static int drm_gem_shmem_get_pages_locked(struct drm_gem_shmem_object *shmem) +static int drm_gem_shmem_get_pages(struct drm_gem_shmem_object *shmem) { struct drm_gem_object *obj = &shmem->base; struct page **pages; + dma_resv_assert_held(shmem->base.resv); + if (shmem->pages_use_count++ > 0) return 0; pages = drm_gem_get_pages(obj); if (IS_ERR(pages)) { - DRM_DEBUG_KMS("Failed to get pages (%ld)\n", PTR_ERR(pages)); + drm_dbg_kms(obj->dev, "Failed to get pages (%ld)\n", + PTR_ERR(pages)); shmem->pages_use_count = 0; return PTR_ERR(pages); } @@ -194,36 +199,18 @@ static int drm_gem_shmem_get_pages_locked(struct drm_gem_shmem_object *shmem) } /* - * drm_gem_shmem_get_pages - Allocate backing pages for a shmem GEM object + * drm_gem_shmem_put_pages - Decrease use count on the backing pages for a shmem GEM object * @shmem: shmem GEM object * - * This function makes sure that backing pages exists for the shmem GEM object - * and increases the use count. - * - * Returns: - * 0 on success or a negative error code on failure. + * This function decreases the use count and puts the backing pages when use drops to zero. */ -int drm_gem_shmem_get_pages(struct drm_gem_shmem_object *shmem) -{ - int ret; - - WARN_ON(shmem->base.import_attach); - - ret = mutex_lock_interruptible(&shmem->pages_lock); - if (ret) - return ret; - ret = drm_gem_shmem_get_pages_locked(shmem); - mutex_unlock(&shmem->pages_lock); - - return ret; -} -EXPORT_SYMBOL(drm_gem_shmem_get_pages); - -static void drm_gem_shmem_put_pages_locked(struct drm_gem_shmem_object *shmem) +void drm_gem_shmem_put_pages(struct drm_gem_shmem_object *shmem) { struct drm_gem_object *obj = &shmem->base; - if (WARN_ON_ONCE(!shmem->pages_use_count)) + dma_resv_assert_held(shmem->base.resv); + + if (drm_WARN_ON_ONCE(obj->dev, !shmem->pages_use_count)) return; if (--shmem->pages_use_count > 0) @@ -239,20 +226,25 @@ static void drm_gem_shmem_put_pages_locked(struct drm_gem_shmem_object *shmem) shmem->pages_mark_accessed_on_put); shmem->pages = NULL; } +EXPORT_SYMBOL(drm_gem_shmem_put_pages); -/* - * drm_gem_shmem_put_pages - Decrease use count on the backing pages for a shmem GEM object - * @shmem: shmem GEM object - * - * This function decreases the use count and puts the backing pages when use drops to zero. - */ -void drm_gem_shmem_put_pages(struct drm_gem_shmem_object *shmem) +static int drm_gem_shmem_pin_locked(struct drm_gem_shmem_object *shmem) { - mutex_lock(&shmem->pages_lock); - drm_gem_shmem_put_pages_locked(shmem); - mutex_unlock(&shmem->pages_lock); + int ret; + + dma_resv_assert_held(shmem->base.resv); + + ret = drm_gem_shmem_get_pages(shmem); + + return ret; +} + +static void drm_gem_shmem_unpin_locked(struct drm_gem_shmem_object *shmem) +{ + dma_resv_assert_held(shmem->base.resv); + + drm_gem_shmem_put_pages(shmem); } -EXPORT_SYMBOL(drm_gem_shmem_put_pages); /** * drm_gem_shmem_pin - Pin backing pages for a shmem GEM object @@ -266,9 +258,18 @@ EXPORT_SYMBOL(drm_gem_shmem_put_pages); */ int drm_gem_shmem_pin(struct drm_gem_shmem_object *shmem) { - WARN_ON(shmem->base.import_attach); + struct drm_gem_object *obj = &shmem->base; + int ret; + + drm_WARN_ON(obj->dev, obj->import_attach); - return drm_gem_shmem_get_pages(shmem); + ret = dma_resv_lock_interruptible(shmem->base.resv, NULL); + if (ret) + return ret; + ret = drm_gem_shmem_pin_locked(shmem); + dma_resv_unlock(shmem->base.resv); + + return ret; } EXPORT_SYMBOL(drm_gem_shmem_pin); @@ -281,36 +282,55 @@ EXPORT_SYMBOL(drm_gem_shmem_pin); */ void drm_gem_shmem_unpin(struct drm_gem_shmem_object *shmem) { - WARN_ON(shmem->base.import_attach); + struct drm_gem_object *obj = &shmem->base; - drm_gem_shmem_put_pages(shmem); + drm_WARN_ON(obj->dev, obj->import_attach); + + dma_resv_lock(shmem->base.resv, NULL); + drm_gem_shmem_unpin_locked(shmem); + dma_resv_unlock(shmem->base.resv); } EXPORT_SYMBOL(drm_gem_shmem_unpin); -static int drm_gem_shmem_vmap_locked(struct drm_gem_shmem_object *shmem, - struct iosys_map *map) +/* + * drm_gem_shmem_vmap - Create a virtual mapping for a shmem GEM object + * @shmem: shmem GEM object + * @map: Returns the kernel virtual address of the SHMEM GEM object's backing + * store. + * + * This function makes sure that a contiguous kernel virtual address mapping + * exists for the buffer backing the shmem GEM object. It hides the differences + * between dma-buf imported and natively allocated objects. + * + * Acquired mappings should be cleaned up by calling drm_gem_shmem_vunmap(). + * + * Returns: + * 0 on success or a negative error code on failure. + */ +int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem, + struct iosys_map *map) { struct drm_gem_object *obj = &shmem->base; int ret = 0; - if (shmem->vmap_use_count++ > 0) { - iosys_map_set_vaddr(map, shmem->vaddr); - return 0; - } - if (obj->import_attach) { ret = dma_buf_vmap(obj->import_attach->dmabuf, map); if (!ret) { - if (WARN_ON(map->is_iomem)) { + if (drm_WARN_ON(obj->dev, map->is_iomem)) { dma_buf_vunmap(obj->import_attach->dmabuf, map); - ret = -EIO; - goto err_put_pages; + return -EIO; } - shmem->vaddr = map->vaddr; } } else { pgprot_t prot = PAGE_KERNEL; + dma_resv_assert_held(shmem->base.resv); + + if (shmem->vmap_use_count++ > 0) { + iosys_map_set_vaddr(map, shmem->vaddr); + return 0; + } + ret = drm_gem_shmem_get_pages(shmem); if (ret) goto err_zero_use; @@ -326,7 +346,7 @@ static int drm_gem_shmem_vmap_locked(struct drm_gem_shmem_object *shmem, } if (ret) { - DRM_DEBUG_KMS("Failed to vmap pages, error %d\n", ret); + drm_dbg_kms(obj->dev, "Failed to vmap pages, error %d\n", ret); goto err_put_pages; } @@ -340,58 +360,8 @@ static int drm_gem_shmem_vmap_locked(struct drm_gem_shmem_object *shmem, return ret; } - -/* - * drm_gem_shmem_vmap - Create a virtual mapping for a shmem GEM object - * @shmem: shmem GEM object - * @map: Returns the kernel virtual address of the SHMEM GEM object's backing - * store. - * - * This function makes sure that a contiguous kernel virtual address mapping - * exists for the buffer backing the shmem GEM object. It hides the differences - * between dma-buf imported and natively allocated objects. - * - * Acquired mappings should be cleaned up by calling drm_gem_shmem_vunmap(). - * - * Returns: - * 0 on success or a negative error code on failure. - */ -int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem, - struct iosys_map *map) -{ - int ret; - - ret = mutex_lock_interruptible(&shmem->vmap_lock); - if (ret) - return ret; - ret = drm_gem_shmem_vmap_locked(shmem, map); - mutex_unlock(&shmem->vmap_lock); - - return ret; -} EXPORT_SYMBOL(drm_gem_shmem_vmap); -static void drm_gem_shmem_vunmap_locked(struct drm_gem_shmem_object *shmem, - struct iosys_map *map) -{ - struct drm_gem_object *obj = &shmem->base; - - if (WARN_ON_ONCE(!shmem->vmap_use_count)) - return; - - if (--shmem->vmap_use_count > 0) - return; - - if (obj->import_attach) { - dma_buf_vunmap(obj->import_attach->dmabuf, map); - } else { - vunmap(shmem->vaddr); - drm_gem_shmem_put_pages(shmem); - } - - shmem->vaddr = NULL; -} - /* * drm_gem_shmem_vunmap - Unmap a virtual mapping for a shmem GEM object * @shmem: shmem GEM object @@ -407,13 +377,28 @@ static void drm_gem_shmem_vunmap_locked(struct drm_gem_shmem_object *shmem, void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem, struct iosys_map *map) { - mutex_lock(&shmem->vmap_lock); - drm_gem_shmem_vunmap_locked(shmem, map); - mutex_unlock(&shmem->vmap_lock); + struct drm_gem_object *obj = &shmem->base; + + if (obj->import_attach) { + dma_buf_vunmap(obj->import_attach->dmabuf, map); + } else { + dma_resv_assert_held(shmem->base.resv); + + if (drm_WARN_ON_ONCE(obj->dev, !shmem->vmap_use_count)) + return; + + if (--shmem->vmap_use_count > 0) + return; + + vunmap(shmem->vaddr); + drm_gem_shmem_put_pages(shmem); + } + + shmem->vaddr = NULL; } EXPORT_SYMBOL(drm_gem_shmem_vunmap); -static struct drm_gem_shmem_object * +static int drm_gem_shmem_create_with_handle(struct drm_file *file_priv, struct drm_device *dev, size_t size, uint32_t *handle) @@ -423,7 +408,7 @@ drm_gem_shmem_create_with_handle(struct drm_file *file_priv, shmem = drm_gem_shmem_create(dev, size); if (IS_ERR(shmem)) - return shmem; + return PTR_ERR(shmem); /* * Allocate an id of idr table where the obj is registered @@ -432,10 +417,8 @@ drm_gem_shmem_create_with_handle(struct drm_file *file_priv, ret = drm_gem_handle_create(file_priv, &shmem->base, handle); /* drop reference from allocate - handle holds it now. */ drm_gem_object_put(&shmem->base); - if (ret) - return ERR_PTR(ret); - return shmem; + return ret; } /* Update madvise status, returns true if not purged, else @@ -443,32 +426,32 @@ drm_gem_shmem_create_with_handle(struct drm_file *file_priv, */ int drm_gem_shmem_madvise(struct drm_gem_shmem_object *shmem, int madv) { - mutex_lock(&shmem->pages_lock); + dma_resv_assert_held(shmem->base.resv); if (shmem->madv >= 0) shmem->madv = madv; madv = shmem->madv; - mutex_unlock(&shmem->pages_lock); - return (madv >= 0); } EXPORT_SYMBOL(drm_gem_shmem_madvise); -void drm_gem_shmem_purge_locked(struct drm_gem_shmem_object *shmem) +void drm_gem_shmem_purge(struct drm_gem_shmem_object *shmem) { struct drm_gem_object *obj = &shmem->base; struct drm_device *dev = obj->dev; - WARN_ON(!drm_gem_shmem_is_purgeable(shmem)); + dma_resv_assert_held(shmem->base.resv); + + drm_WARN_ON(obj->dev, !drm_gem_shmem_is_purgeable(shmem)); dma_unmap_sgtable(dev->dev, shmem->sgt, DMA_BIDIRECTIONAL, 0); sg_free_table(shmem->sgt); kfree(shmem->sgt); shmem->sgt = NULL; - drm_gem_shmem_put_pages_locked(shmem); + drm_gem_shmem_put_pages(shmem); shmem->madv = -1; @@ -484,17 +467,6 @@ void drm_gem_shmem_purge_locked(struct drm_gem_shmem_object *shmem) invalidate_mapping_pages(file_inode(obj->filp)->i_mapping, 0, (loff_t)-1); } -EXPORT_SYMBOL(drm_gem_shmem_purge_locked); - -bool drm_gem_shmem_purge(struct drm_gem_shmem_object *shmem) -{ - if (!mutex_trylock(&shmem->pages_lock)) - return false; - drm_gem_shmem_purge_locked(shmem); - mutex_unlock(&shmem->pages_lock); - - return true; -} EXPORT_SYMBOL(drm_gem_shmem_purge); /** @@ -518,7 +490,6 @@ int drm_gem_shmem_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args) { u32 min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); - struct drm_gem_shmem_object *shmem; if (!args->pitch || !args->size) { args->pitch = min_pitch; @@ -531,9 +502,7 @@ int drm_gem_shmem_dumb_create(struct drm_file *file, struct drm_device *dev, args->size = PAGE_ALIGN(args->pitch * args->height); } - shmem = drm_gem_shmem_create_with_handle(file, dev, args->size, &args->handle); - - return PTR_ERR_OR_ZERO(shmem); + return drm_gem_shmem_create_with_handle(file, dev, args->size, &args->handle); } EXPORT_SYMBOL_GPL(drm_gem_shmem_dumb_create); @@ -550,10 +519,10 @@ static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf) /* We don't use vmf->pgoff since that has the fake offset */ page_offset = (vmf->address - vma->vm_start) >> PAGE_SHIFT; - mutex_lock(&shmem->pages_lock); + dma_resv_lock(shmem->base.resv, NULL); if (page_offset >= num_pages || - WARN_ON_ONCE(!shmem->pages) || + drm_WARN_ON_ONCE(obj->dev, !shmem->pages) || shmem->madv < 0) { ret = VM_FAULT_SIGBUS; } else { @@ -562,7 +531,7 @@ static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf) ret = vmf_insert_pfn(vma, vmf->address, page_to_pfn(page)); } - mutex_unlock(&shmem->pages_lock); + dma_resv_unlock(shmem->base.resv); return ret; } @@ -572,19 +541,19 @@ static void drm_gem_shmem_vm_open(struct vm_area_struct *vma) struct drm_gem_object *obj = vma->vm_private_data; struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); - WARN_ON(shmem->base.import_attach); + drm_WARN_ON(obj->dev, obj->import_attach); - mutex_lock(&shmem->pages_lock); + dma_resv_lock(shmem->base.resv, NULL); /* * We should have already pinned the pages when the buffer was first * mmap'd, vm_open() just grabs an additional reference for the new * mm the vma is getting copied into (ie. on fork()). */ - if (!WARN_ON_ONCE(!shmem->pages_use_count)) + if (!drm_WARN_ON_ONCE(obj->dev, !shmem->pages_use_count)) shmem->pages_use_count++; - mutex_unlock(&shmem->pages_lock); + dma_resv_unlock(shmem->base.resv); drm_gem_vm_open(vma); } @@ -594,7 +563,10 @@ static void drm_gem_shmem_vm_close(struct vm_area_struct *vma) struct drm_gem_object *obj = vma->vm_private_data; struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); + dma_resv_lock(shmem->base.resv, NULL); drm_gem_shmem_put_pages(shmem); + dma_resv_unlock(shmem->base.resv); + drm_gem_vm_close(vma); } @@ -638,7 +610,10 @@ int drm_gem_shmem_mmap(struct drm_gem_shmem_object *shmem, struct vm_area_struct return ret; } + dma_resv_lock(shmem->base.resv, NULL); ret = drm_gem_shmem_get_pages(shmem); + dma_resv_unlock(shmem->base.resv); + if (ret) return ret; @@ -660,6 +635,9 @@ EXPORT_SYMBOL_GPL(drm_gem_shmem_mmap); void drm_gem_shmem_print_info(const struct drm_gem_shmem_object *shmem, struct drm_printer *p, unsigned int indent) { + if (shmem->base.import_attach) + return; + drm_printf_indent(p, indent, "pages_use_count=%u\n", shmem->pages_use_count); drm_printf_indent(p, indent, "vmap_use_count=%u\n", shmem->vmap_use_count); drm_printf_indent(p, indent, "vaddr=%p\n", shmem->vaddr); @@ -684,7 +662,7 @@ struct sg_table *drm_gem_shmem_get_sg_table(struct drm_gem_shmem_object *shmem) { struct drm_gem_object *obj = &shmem->base; - WARN_ON(shmem->base.import_attach); + drm_WARN_ON(obj->dev, obj->import_attach); return drm_prime_pages_to_sg(obj->dev, shmem->pages, obj->size >> PAGE_SHIFT); } @@ -699,9 +677,9 @@ static struct sg_table *drm_gem_shmem_get_pages_sgt_locked(struct drm_gem_shmem_ if (shmem->sgt) return shmem->sgt; - WARN_ON(obj->import_attach); + drm_WARN_ON(obj->dev, obj->import_attach); - ret = drm_gem_shmem_get_pages_locked(shmem); + ret = drm_gem_shmem_get_pages(shmem); if (ret) return ERR_PTR(ret); @@ -723,7 +701,7 @@ static struct sg_table *drm_gem_shmem_get_pages_sgt_locked(struct drm_gem_shmem_ sg_free_table(sgt); kfree(sgt); err_put_pages: - drm_gem_shmem_put_pages_locked(shmem); + drm_gem_shmem_put_pages(shmem); return ERR_PTR(ret); } @@ -748,11 +726,11 @@ struct sg_table *drm_gem_shmem_get_pages_sgt(struct drm_gem_shmem_object *shmem) int ret; struct sg_table *sgt; - ret = mutex_lock_interruptible(&shmem->pages_lock); + ret = dma_resv_lock_interruptible(shmem->base.resv, NULL); if (ret) return ERR_PTR(ret); sgt = drm_gem_shmem_get_pages_sgt_locked(shmem); - mutex_unlock(&shmem->pages_lock); + dma_resv_unlock(shmem->base.resv); return sgt; } @@ -787,7 +765,7 @@ drm_gem_shmem_prime_import_sg_table(struct drm_device *dev, shmem->sgt = sgt; - DRM_DEBUG_PRIME("size = %zu\n", size); + drm_dbg_prime(dev, "size = %zu\n", size); return &shmem->base; } diff --git a/drivers/gpu/drm/drm_gem_ttm_helper.c b/drivers/gpu/drm/drm_gem_ttm_helper.c index e5fc875990c4f..d5962a34c01d5 100644 --- a/drivers/gpu/drm/drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/drm_gem_ttm_helper.c @@ -64,13 +64,8 @@ int drm_gem_ttm_vmap(struct drm_gem_object *gem, struct iosys_map *map) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - int ret; - - dma_resv_lock(gem->resv, NULL); - ret = ttm_bo_vmap(bo, map); - dma_resv_unlock(gem->resv); - return ret; + return ttm_bo_vmap(bo, map); } EXPORT_SYMBOL(drm_gem_ttm_vmap); @@ -87,9 +82,7 @@ void drm_gem_ttm_vunmap(struct drm_gem_object *gem, { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - dma_resv_lock(gem->resv, NULL); ttm_bo_vunmap(bo, map); - dma_resv_unlock(gem->resv); } EXPORT_SYMBOL(drm_gem_ttm_vunmap); diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drivers/gpu/drm/drm_gpuvm.c new file mode 100644 index 0000000000000..9387823c2dde4 --- /dev/null +++ b/drivers/gpu/drm/drm_gpuvm.c @@ -0,0 +1,2752 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Red Hat. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Danilo Krummrich + * + */ + +#include + +#include +#include + +/** + * DOC: Overview + * + * The DRM GPU VA Manager, represented by struct drm_gpuvm keeps track of a + * GPU's virtual address (VA) space and manages the corresponding virtual + * mappings represented by &drm_gpuva objects. It also keeps track of the + * mapping's backing &drm_gem_object buffers. + * + * &drm_gem_object buffers maintain a list of &drm_gpuva objects representing + * all existent GPU VA mappings using this &drm_gem_object as backing buffer. + * + * GPU VAs can be flagged as sparse, such that drivers may use GPU VAs to also + * keep track of sparse PTEs in order to support Vulkan 'Sparse Resources'. + * + * The GPU VA manager internally uses a rb-tree to manage the + * &drm_gpuva mappings within a GPU's virtual address space. + * + * The &drm_gpuvm structure contains a special &drm_gpuva representing the + * portion of VA space reserved by the kernel. This node is initialized together + * with the GPU VA manager instance and removed when the GPU VA manager is + * destroyed. + * + * In a typical application drivers would embed struct drm_gpuvm and + * struct drm_gpuva within their own driver specific structures, there won't be + * any memory allocations of its own nor memory allocations of &drm_gpuva + * entries. + * + * The data structures needed to store &drm_gpuvas within the &drm_gpuvm are + * contained within struct drm_gpuva already. Hence, for inserting &drm_gpuva + * entries from within dma-fence signalling critical sections it is enough to + * pre-allocate the &drm_gpuva structures. + * + * &drm_gem_objects which are private to a single VM can share a common + * &dma_resv in order to improve locking efficiency (e.g. with &drm_exec). + * For this purpose drivers must pass a &drm_gem_object to drm_gpuvm_init(), in + * the following called 'resv object', which serves as the container of the + * GPUVM's shared &dma_resv. This resv object can be a driver specific + * &drm_gem_object, such as the &drm_gem_object containing the root page table, + * but it can also be a 'dummy' object, which can be allocated with + * drm_gpuvm_resv_object_alloc(). + * + * In order to connect a struct drm_gpuva its backing &drm_gem_object each + * &drm_gem_object maintains a list of &drm_gpuvm_bo structures, and each + * &drm_gpuvm_bo contains a list of &drm_gpuva structures. + * + * A &drm_gpuvm_bo is an abstraction that represents a combination of a + * &drm_gpuvm and a &drm_gem_object. Every such combination should be unique. + * This is ensured by the API through drm_gpuvm_bo_obtain() and + * drm_gpuvm_bo_obtain_prealloc() which first look into the corresponding + * &drm_gem_object list of &drm_gpuvm_bos for an existing instance of this + * particular combination. If not existent a new instance is created and linked + * to the &drm_gem_object. + * + * &drm_gpuvm_bo structures, since unique for a given &drm_gpuvm, are also used + * as entry for the &drm_gpuvm's lists of external and evicted objects. Those + * lists are maintained in order to accelerate locking of dma-resv locks and + * validation of evicted objects bound in a &drm_gpuvm. For instance, all + * &drm_gem_object's &dma_resv of a given &drm_gpuvm can be locked by calling + * drm_gpuvm_exec_lock(). Once locked drivers can call drm_gpuvm_validate() in + * order to validate all evicted &drm_gem_objects. It is also possible to lock + * additional &drm_gem_objects by providing the corresponding parameters to + * drm_gpuvm_exec_lock() as well as open code the &drm_exec loop while making + * use of helper functions such as drm_gpuvm_prepare_range() or + * drm_gpuvm_prepare_objects(). + * + * Every bound &drm_gem_object is treated as external object when its &dma_resv + * structure is different than the &drm_gpuvm's common &dma_resv structure. + */ + +/** + * DOC: Split and Merge + * + * Besides its capability to manage and represent a GPU VA space, the + * GPU VA manager also provides functions to let the &drm_gpuvm calculate a + * sequence of operations to satisfy a given map or unmap request. + * + * Therefore the DRM GPU VA manager provides an algorithm implementing splitting + * and merging of existent GPU VA mappings with the ones that are requested to + * be mapped or unmapped. This feature is required by the Vulkan API to + * implement Vulkan 'Sparse Memory Bindings' - drivers UAPIs often refer to this + * as VM BIND. + * + * Drivers can call drm_gpuvm_sm_map() to receive a sequence of callbacks + * containing map, unmap and remap operations for a given newly requested + * mapping. The sequence of callbacks represents the set of operations to + * execute in order to integrate the new mapping cleanly into the current state + * of the GPU VA space. + * + * Depending on how the new GPU VA mapping intersects with the existent mappings + * of the GPU VA space the &drm_gpuvm_ops callbacks contain an arbitrary amount + * of unmap operations, a maximum of two remap operations and a single map + * operation. The caller might receive no callback at all if no operation is + * required, e.g. if the requested mapping already exists in the exact same way. + * + * The single map operation represents the original map operation requested by + * the caller. + * + * &drm_gpuva_op_unmap contains a 'keep' field, which indicates whether the + * &drm_gpuva to unmap is physically contiguous with the original mapping + * request. Optionally, if 'keep' is set, drivers may keep the actual page table + * entries for this &drm_gpuva, adding the missing page table entries only and + * update the &drm_gpuvm's view of things accordingly. + * + * Drivers may do the same optimization, namely delta page table updates, also + * for remap operations. This is possible since &drm_gpuva_op_remap consists of + * one unmap operation and one or two map operations, such that drivers can + * derive the page table update delta accordingly. + * + * Note that there can't be more than two existent mappings to split up, one at + * the beginning and one at the end of the new mapping, hence there is a + * maximum of two remap operations. + * + * Analogous to drm_gpuvm_sm_map() drm_gpuvm_sm_unmap() uses &drm_gpuvm_ops to + * call back into the driver in order to unmap a range of GPU VA space. The + * logic behind this function is way simpler though: For all existent mappings + * enclosed by the given range unmap operations are created. For mappings which + * are only partically located within the given range, remap operations are + * created such that those mappings are split up and re-mapped partically. + * + * As an alternative to drm_gpuvm_sm_map() and drm_gpuvm_sm_unmap(), + * drm_gpuvm_sm_map_ops_create() and drm_gpuvm_sm_unmap_ops_create() can be used + * to directly obtain an instance of struct drm_gpuva_ops containing a list of + * &drm_gpuva_op, which can be iterated with drm_gpuva_for_each_op(). This list + * contains the &drm_gpuva_ops analogous to the callbacks one would receive when + * calling drm_gpuvm_sm_map() or drm_gpuvm_sm_unmap(). While this way requires + * more memory (to allocate the &drm_gpuva_ops), it provides drivers a way to + * iterate the &drm_gpuva_op multiple times, e.g. once in a context where memory + * allocations are possible (e.g. to allocate GPU page tables) and once in the + * dma-fence signalling critical path. + * + * To update the &drm_gpuvm's view of the GPU VA space drm_gpuva_insert() and + * drm_gpuva_remove() may be used. These functions can safely be used from + * &drm_gpuvm_ops callbacks originating from drm_gpuvm_sm_map() or + * drm_gpuvm_sm_unmap(). However, it might be more convenient to use the + * provided helper functions drm_gpuva_map(), drm_gpuva_remap() and + * drm_gpuva_unmap() instead. + * + * The following diagram depicts the basic relationships of existent GPU VA + * mappings, a newly requested mapping and the resulting mappings as implemented + * by drm_gpuvm_sm_map() - it doesn't cover any arbitrary combinations of these. + * + * 1) Requested mapping is identical. Replace it, but indicate the backing PTEs + * could be kept. + * + * :: + * + * 0 a 1 + * old: |-----------| (bo_offset=n) + * + * 0 a 1 + * req: |-----------| (bo_offset=n) + * + * 0 a 1 + * new: |-----------| (bo_offset=n) + * + * + * 2) Requested mapping is identical, except for the BO offset, hence replace + * the mapping. + * + * :: + * + * 0 a 1 + * old: |-----------| (bo_offset=n) + * + * 0 a 1 + * req: |-----------| (bo_offset=m) + * + * 0 a 1 + * new: |-----------| (bo_offset=m) + * + * + * 3) Requested mapping is identical, except for the backing BO, hence replace + * the mapping. + * + * :: + * + * 0 a 1 + * old: |-----------| (bo_offset=n) + * + * 0 b 1 + * req: |-----------| (bo_offset=n) + * + * 0 b 1 + * new: |-----------| (bo_offset=n) + * + * + * 4) Existent mapping is a left aligned subset of the requested one, hence + * replace the existent one. + * + * :: + * + * 0 a 1 + * old: |-----| (bo_offset=n) + * + * 0 a 2 + * req: |-----------| (bo_offset=n) + * + * 0 a 2 + * new: |-----------| (bo_offset=n) + * + * .. note:: + * We expect to see the same result for a request with a different BO + * and/or non-contiguous BO offset. + * + * + * 5) Requested mapping's range is a left aligned subset of the existent one, + * but backed by a different BO. Hence, map the requested mapping and split + * the existent one adjusting its BO offset. + * + * :: + * + * 0 a 2 + * old: |-----------| (bo_offset=n) + * + * 0 b 1 + * req: |-----| (bo_offset=n) + * + * 0 b 1 a' 2 + * new: |-----|-----| (b.bo_offset=n, a.bo_offset=n+1) + * + * .. note:: + * We expect to see the same result for a request with a different BO + * and/or non-contiguous BO offset. + * + * + * 6) Existent mapping is a superset of the requested mapping. Split it up, but + * indicate that the backing PTEs could be kept. + * + * :: + * + * 0 a 2 + * old: |-----------| (bo_offset=n) + * + * 0 a 1 + * req: |-----| (bo_offset=n) + * + * 0 a 1 a' 2 + * new: |-----|-----| (a.bo_offset=n, a'.bo_offset=n+1) + * + * + * 7) Requested mapping's range is a right aligned subset of the existent one, + * but backed by a different BO. Hence, map the requested mapping and split + * the existent one, without adjusting the BO offset. + * + * :: + * + * 0 a 2 + * old: |-----------| (bo_offset=n) + * + * 1 b 2 + * req: |-----| (bo_offset=m) + * + * 0 a 1 b 2 + * new: |-----|-----| (a.bo_offset=n,b.bo_offset=m) + * + * + * 8) Existent mapping is a superset of the requested mapping. Split it up, but + * indicate that the backing PTEs could be kept. + * + * :: + * + * 0 a 2 + * old: |-----------| (bo_offset=n) + * + * 1 a 2 + * req: |-----| (bo_offset=n+1) + * + * 0 a' 1 a 2 + * new: |-----|-----| (a'.bo_offset=n, a.bo_offset=n+1) + * + * + * 9) Existent mapping is overlapped at the end by the requested mapping backed + * by a different BO. Hence, map the requested mapping and split up the + * existent one, without adjusting the BO offset. + * + * :: + * + * 0 a 2 + * old: |-----------| (bo_offset=n) + * + * 1 b 3 + * req: |-----------| (bo_offset=m) + * + * 0 a 1 b 3 + * new: |-----|-----------| (a.bo_offset=n,b.bo_offset=m) + * + * + * 10) Existent mapping is overlapped by the requested mapping, both having the + * same backing BO with a contiguous offset. Indicate the backing PTEs of + * the old mapping could be kept. + * + * :: + * + * 0 a 2 + * old: |-----------| (bo_offset=n) + * + * 1 a 3 + * req: |-----------| (bo_offset=n+1) + * + * 0 a' 1 a 3 + * new: |-----|-----------| (a'.bo_offset=n, a.bo_offset=n+1) + * + * + * 11) Requested mapping's range is a centered subset of the existent one + * having a different backing BO. Hence, map the requested mapping and split + * up the existent one in two mappings, adjusting the BO offset of the right + * one accordingly. + * + * :: + * + * 0 a 3 + * old: |-----------------| (bo_offset=n) + * + * 1 b 2 + * req: |-----| (bo_offset=m) + * + * 0 a 1 b 2 a' 3 + * new: |-----|-----|-----| (a.bo_offset=n,b.bo_offset=m,a'.bo_offset=n+2) + * + * + * 12) Requested mapping is a contiguous subset of the existent one. Split it + * up, but indicate that the backing PTEs could be kept. + * + * :: + * + * 0 a 3 + * old: |-----------------| (bo_offset=n) + * + * 1 a 2 + * req: |-----| (bo_offset=n+1) + * + * 0 a' 1 a 2 a'' 3 + * old: |-----|-----|-----| (a'.bo_offset=n, a.bo_offset=n+1, a''.bo_offset=n+2) + * + * + * 13) Existent mapping is a right aligned subset of the requested one, hence + * replace the existent one. + * + * :: + * + * 1 a 2 + * old: |-----| (bo_offset=n+1) + * + * 0 a 2 + * req: |-----------| (bo_offset=n) + * + * 0 a 2 + * new: |-----------| (bo_offset=n) + * + * .. note:: + * We expect to see the same result for a request with a different bo + * and/or non-contiguous bo_offset. + * + * + * 14) Existent mapping is a centered subset of the requested one, hence + * replace the existent one. + * + * :: + * + * 1 a 2 + * old: |-----| (bo_offset=n+1) + * + * 0 a 3 + * req: |----------------| (bo_offset=n) + * + * 0 a 3 + * new: |----------------| (bo_offset=n) + * + * .. note:: + * We expect to see the same result for a request with a different bo + * and/or non-contiguous bo_offset. + * + * + * 15) Existent mappings is overlapped at the beginning by the requested mapping + * backed by a different BO. Hence, map the requested mapping and split up + * the existent one, adjusting its BO offset accordingly. + * + * :: + * + * 1 a 3 + * old: |-----------| (bo_offset=n) + * + * 0 b 2 + * req: |-----------| (bo_offset=m) + * + * 0 b 2 a' 3 + * new: |-----------|-----| (b.bo_offset=m,a.bo_offset=n+2) + */ + +/** + * DOC: Locking + * + * In terms of managing &drm_gpuva entries DRM GPUVM does not take care of + * locking itself, it is the drivers responsibility to take care about locking. + * Drivers might want to protect the following operations: inserting, removing + * and iterating &drm_gpuva objects as well as generating all kinds of + * operations, such as split / merge or prefetch. + * + * DRM GPUVM also does not take care of the locking of the backing + * &drm_gem_object buffers GPU VA lists and &drm_gpuvm_bo abstractions by + * itself; drivers are responsible to enforce mutual exclusion using either the + * GEMs dma_resv lock or alternatively a driver specific external lock. For the + * latter see also drm_gem_gpuva_set_lock(). + * + * However, DRM GPUVM contains lockdep checks to ensure callers of its API hold + * the corresponding lock whenever the &drm_gem_objects GPU VA list is accessed + * by functions such as drm_gpuva_link() or drm_gpuva_unlink(), but also + * drm_gpuvm_bo_obtain() and drm_gpuvm_bo_put(). + * + * The latter is required since on creation and destruction of a &drm_gpuvm_bo + * the &drm_gpuvm_bo is attached / removed from the &drm_gem_objects gpuva list. + * Subsequent calls to drm_gpuvm_bo_obtain() for the same &drm_gpuvm and + * &drm_gem_object must be able to observe previous creations and destructions + * of &drm_gpuvm_bos in order to keep instances unique. + * + * The &drm_gpuvm's lists for keeping track of external and evicted objects are + * protected against concurrent insertion / removal and iteration internally. + * + * However, drivers still need ensure to protect concurrent calls to functions + * iterating those lists, namely drm_gpuvm_prepare_objects() and + * drm_gpuvm_validate(). + * + * Alternatively, drivers can set the &DRM_GPUVM_RESV_PROTECTED flag to indicate + * that the corresponding &dma_resv locks are held in order to protect the + * lists. If &DRM_GPUVM_RESV_PROTECTED is set, internal locking is disabled and + * the corresponding lockdep checks are enabled. This is an optimization for + * drivers which are capable of taking the corresponding &dma_resv locks and + * hence do not require internal locking. + */ + +/** + * DOC: Examples + * + * This section gives two examples on how to let the DRM GPUVA Manager generate + * &drm_gpuva_op in order to satisfy a given map or unmap request and how to + * make use of them. + * + * The below code is strictly limited to illustrate the generic usage pattern. + * To maintain simplicitly, it doesn't make use of any abstractions for common + * code, different (asyncronous) stages with fence signalling critical paths, + * any other helpers or error handling in terms of freeing memory and dropping + * previously taken locks. + * + * 1) Obtain a list of &drm_gpuva_op to create a new mapping:: + * + * // Allocates a new &drm_gpuva. + * struct drm_gpuva * driver_gpuva_alloc(void); + * + * // Typically drivers would embedd the &drm_gpuvm and &drm_gpuva + * // structure in individual driver structures and lock the dma-resv with + * // drm_exec or similar helpers. + * int driver_mapping_create(struct drm_gpuvm *gpuvm, + * u64 addr, u64 range, + * struct drm_gem_object *obj, u64 offset) + * { + * struct drm_gpuva_ops *ops; + * struct drm_gpuva_op *op + * struct drm_gpuvm_bo *vm_bo; + * + * driver_lock_va_space(); + * ops = drm_gpuvm_sm_map_ops_create(gpuvm, addr, range, + * obj, offset); + * if (IS_ERR(ops)) + * return PTR_ERR(ops); + * + * vm_bo = drm_gpuvm_bo_obtain(gpuvm, obj); + * if (IS_ERR(vm_bo)) + * return PTR_ERR(vm_bo); + * + * drm_gpuva_for_each_op(op, ops) { + * struct drm_gpuva *va; + * + * switch (op->op) { + * case DRM_GPUVA_OP_MAP: + * va = driver_gpuva_alloc(); + * if (!va) + * ; // unwind previous VA space updates, + * // free memory and unlock + * + * driver_vm_map(); + * drm_gpuva_map(gpuvm, va, &op->map); + * drm_gpuva_link(va, vm_bo); + * + * break; + * case DRM_GPUVA_OP_REMAP: { + * struct drm_gpuva *prev = NULL, *next = NULL; + * + * va = op->remap.unmap->va; + * + * if (op->remap.prev) { + * prev = driver_gpuva_alloc(); + * if (!prev) + * ; // unwind previous VA space + * // updates, free memory and + * // unlock + * } + * + * if (op->remap.next) { + * next = driver_gpuva_alloc(); + * if (!next) + * ; // unwind previous VA space + * // updates, free memory and + * // unlock + * } + * + * driver_vm_remap(); + * drm_gpuva_remap(prev, next, &op->remap); + * + * if (prev) + * drm_gpuva_link(prev, va->vm_bo); + * if (next) + * drm_gpuva_link(next, va->vm_bo); + * drm_gpuva_unlink(va); + * + * break; + * } + * case DRM_GPUVA_OP_UNMAP: + * va = op->unmap->va; + * + * driver_vm_unmap(); + * drm_gpuva_unlink(va); + * drm_gpuva_unmap(&op->unmap); + * + * break; + * default: + * break; + * } + * } + * drm_gpuvm_bo_put(vm_bo); + * driver_unlock_va_space(); + * + * return 0; + * } + * + * 2) Receive a callback for each &drm_gpuva_op to create a new mapping:: + * + * struct driver_context { + * struct drm_gpuvm *gpuvm; + * struct drm_gpuvm_bo *vm_bo; + * struct drm_gpuva *new_va; + * struct drm_gpuva *prev_va; + * struct drm_gpuva *next_va; + * }; + * + * // ops to pass to drm_gpuvm_init() + * static const struct drm_gpuvm_ops driver_gpuvm_ops = { + * .sm_step_map = driver_gpuva_map, + * .sm_step_remap = driver_gpuva_remap, + * .sm_step_unmap = driver_gpuva_unmap, + * }; + * + * // Typically drivers would embedd the &drm_gpuvm and &drm_gpuva + * // structure in individual driver structures and lock the dma-resv with + * // drm_exec or similar helpers. + * int driver_mapping_create(struct drm_gpuvm *gpuvm, + * u64 addr, u64 range, + * struct drm_gem_object *obj, u64 offset) + * { + * struct driver_context ctx; + * struct drm_gpuvm_bo *vm_bo; + * struct drm_gpuva_ops *ops; + * struct drm_gpuva_op *op; + * int ret = 0; + * + * ctx.gpuvm = gpuvm; + * + * ctx.new_va = kzalloc(sizeof(*ctx.new_va), GFP_KERNEL); + * ctx.prev_va = kzalloc(sizeof(*ctx.prev_va), GFP_KERNEL); + * ctx.next_va = kzalloc(sizeof(*ctx.next_va), GFP_KERNEL); + * ctx.vm_bo = drm_gpuvm_bo_create(gpuvm, obj); + * if (!ctx.new_va || !ctx.prev_va || !ctx.next_va || !vm_bo) { + * ret = -ENOMEM; + * goto out; + * } + * + * // Typically protected with a driver specific GEM gpuva lock + * // used in the fence signaling path for drm_gpuva_link() and + * // drm_gpuva_unlink(), hence pre-allocate. + * ctx.vm_bo = drm_gpuvm_bo_obtain_prealloc(ctx.vm_bo); + * + * driver_lock_va_space(); + * ret = drm_gpuvm_sm_map(gpuvm, &ctx, addr, range, obj, offset); + * driver_unlock_va_space(); + * + * out: + * drm_gpuvm_bo_put(ctx.vm_bo); + * kfree(ctx.new_va); + * kfree(ctx.prev_va); + * kfree(ctx.next_va); + * return ret; + * } + * + * int driver_gpuva_map(struct drm_gpuva_op *op, void *__ctx) + * { + * struct driver_context *ctx = __ctx; + * + * drm_gpuva_map(ctx->vm, ctx->new_va, &op->map); + * + * drm_gpuva_link(ctx->new_va, ctx->vm_bo); + * + * // prevent the new GPUVA from being freed in + * // driver_mapping_create() + * ctx->new_va = NULL; + * + * return 0; + * } + * + * int driver_gpuva_remap(struct drm_gpuva_op *op, void *__ctx) + * { + * struct driver_context *ctx = __ctx; + * struct drm_gpuva *va = op->remap.unmap->va; + * + * drm_gpuva_remap(ctx->prev_va, ctx->next_va, &op->remap); + * + * if (op->remap.prev) { + * drm_gpuva_link(ctx->prev_va, va->vm_bo); + * ctx->prev_va = NULL; + * } + * + * if (op->remap.next) { + * drm_gpuva_link(ctx->next_va, va->vm_bo); + * ctx->next_va = NULL; + * } + * + * drm_gpuva_unlink(va); + * kfree(va); + * + * return 0; + * } + * + * int driver_gpuva_unmap(struct drm_gpuva_op *op, void *__ctx) + * { + * drm_gpuva_unlink(op->unmap.va); + * drm_gpuva_unmap(&op->unmap); + * kfree(op->unmap.va); + * + * return 0; + * } + */ + +/** + * get_next_vm_bo_from_list() - get the next vm_bo element + * @__gpuvm: the &drm_gpuvm + * @__list_name: the name of the list we're iterating on + * @__local_list: a pointer to the local list used to store already iterated items + * @__prev_vm_bo: the previous element we got from get_next_vm_bo_from_list() + * + * This helper is here to provide lockless list iteration. Lockless as in, the + * iterator releases the lock immediately after picking the first element from + * the list, so list insertion deletion can happen concurrently. + * + * Elements popped from the original list are kept in a local list, so removal + * and is_empty checks can still happen while we're iterating the list. + */ +#define get_next_vm_bo_from_list(__gpuvm, __list_name, __local_list, __prev_vm_bo) \ + ({ \ + struct drm_gpuvm_bo *__vm_bo = NULL; \ + \ + drm_gpuvm_bo_put(__prev_vm_bo); \ + \ + spin_lock(&(__gpuvm)->__list_name.lock); \ + if (!(__gpuvm)->__list_name.local_list) \ + (__gpuvm)->__list_name.local_list = __local_list; \ + else \ + drm_WARN_ON((__gpuvm)->drm, \ + (__gpuvm)->__list_name.local_list != __local_list); \ + \ + while (!list_empty(&(__gpuvm)->__list_name.list)) { \ + __vm_bo = list_first_entry(&(__gpuvm)->__list_name.list, \ + struct drm_gpuvm_bo, \ + list.entry.__list_name); \ + if (kref_get_unless_zero(&__vm_bo->kref)) { \ + list_move_tail(&(__vm_bo)->list.entry.__list_name, \ + __local_list); \ + break; \ + } else { \ + list_del_init(&(__vm_bo)->list.entry.__list_name); \ + __vm_bo = NULL; \ + } \ + } \ + spin_unlock(&(__gpuvm)->__list_name.lock); \ + \ + __vm_bo; \ + }) + +/** + * for_each_vm_bo_in_list() - internal vm_bo list iterator + * @__gpuvm: the &drm_gpuvm + * @__list_name: the name of the list we're iterating on + * @__local_list: a pointer to the local list used to store already iterated items + * @__vm_bo: the struct drm_gpuvm_bo to assign in each iteration step + * + * This helper is here to provide lockless list iteration. Lockless as in, the + * iterator releases the lock immediately after picking the first element from the + * list, hence list insertion and deletion can happen concurrently. + * + * It is not allowed to re-assign the vm_bo pointer from inside this loop. + * + * Typical use: + * + * struct drm_gpuvm_bo *vm_bo; + * LIST_HEAD(my_local_list); + * + * ret = 0; + * for_each_vm_bo_in_list(gpuvm, , &my_local_list, vm_bo) { + * ret = do_something_with_vm_bo(..., vm_bo); + * if (ret) + * break; + * } + * // Drop ref in case we break out of the loop. + * drm_gpuvm_bo_put(vm_bo); + * restore_vm_bo_list(gpuvm, , &my_local_list); + * + * + * Only used for internal list iterations, not meant to be exposed to the outside + * world. + */ +#define for_each_vm_bo_in_list(__gpuvm, __list_name, __local_list, __vm_bo) \ + for (__vm_bo = get_next_vm_bo_from_list(__gpuvm, __list_name, \ + __local_list, NULL); \ + __vm_bo; \ + __vm_bo = get_next_vm_bo_from_list(__gpuvm, __list_name, \ + __local_list, __vm_bo)) + +static void +__restore_vm_bo_list(struct drm_gpuvm *gpuvm, spinlock_t *lock, + struct list_head *list, struct list_head **local_list) +{ + /* Merge back the two lists, moving local list elements to the + * head to preserve previous ordering, in case it matters. + */ + spin_lock(lock); + if (*local_list) { + list_splice(*local_list, list); + *local_list = NULL; + } + spin_unlock(lock); +} + +/** + * restore_vm_bo_list() - move vm_bo elements back to their original list + * @__gpuvm: the &drm_gpuvm + * @__list_name: the name of the list we're iterating on + * + * When we're done iterating a vm_bo list, we should call restore_vm_bo_list() + * to restore the original state and let new iterations take place. + */ +#define restore_vm_bo_list(__gpuvm, __list_name) \ + __restore_vm_bo_list((__gpuvm), &(__gpuvm)->__list_name.lock, \ + &(__gpuvm)->__list_name.list, \ + &(__gpuvm)->__list_name.local_list) + +static void +cond_spin_lock(spinlock_t *lock, bool cond) +{ + if (cond) + spin_lock(lock); +} + +static void +cond_spin_unlock(spinlock_t *lock, bool cond) +{ + if (cond) + spin_unlock(lock); +} + +static void +__drm_gpuvm_bo_list_add(struct drm_gpuvm *gpuvm, spinlock_t *lock, + struct list_head *entry, struct list_head *list) +{ + cond_spin_lock(lock, !!lock); + if (list_empty(entry)) + list_add_tail(entry, list); + cond_spin_unlock(lock, !!lock); +} + +/** + * drm_gpuvm_bo_list_add() - insert a vm_bo into the given list + * @__vm_bo: the &drm_gpuvm_bo + * @__list_name: the name of the list to insert into + * @__lock: whether to lock with the internal spinlock + * + * Inserts the given @__vm_bo into the list specified by @__list_name. + */ +#define drm_gpuvm_bo_list_add(__vm_bo, __list_name, __lock) \ + __drm_gpuvm_bo_list_add((__vm_bo)->vm, \ + __lock ? &(__vm_bo)->vm->__list_name.lock : \ + NULL, \ + &(__vm_bo)->list.entry.__list_name, \ + &(__vm_bo)->vm->__list_name.list) + +static void +__drm_gpuvm_bo_list_del(struct drm_gpuvm *gpuvm, spinlock_t *lock, + struct list_head *entry, bool init) +{ + cond_spin_lock(lock, !!lock); + if (init) { + if (!list_empty(entry)) + list_del_init(entry); + } else { + list_del(entry); + } + cond_spin_unlock(lock, !!lock); +} + +/** + * drm_gpuvm_bo_list_del_init() - remove a vm_bo from the given list + * @__vm_bo: the &drm_gpuvm_bo + * @__list_name: the name of the list to insert into + * @__lock: whether to lock with the internal spinlock + * + * Removes the given @__vm_bo from the list specified by @__list_name. + */ +#define drm_gpuvm_bo_list_del_init(__vm_bo, __list_name, __lock) \ + __drm_gpuvm_bo_list_del((__vm_bo)->vm, \ + __lock ? &(__vm_bo)->vm->__list_name.lock : \ + NULL, \ + &(__vm_bo)->list.entry.__list_name, \ + true) + +/** + * drm_gpuvm_bo_list_del() - remove a vm_bo from the given list + * @__vm_bo: the &drm_gpuvm_bo + * @__list_name: the name of the list to insert into + * @__lock: whether to lock with the internal spinlock + * + * Removes the given @__vm_bo from the list specified by @__list_name. + */ +#define drm_gpuvm_bo_list_del(__vm_bo, __list_name, __lock) \ + __drm_gpuvm_bo_list_del((__vm_bo)->vm, \ + __lock ? &(__vm_bo)->vm->__list_name.lock : \ + NULL, \ + &(__vm_bo)->list.entry.__list_name, \ + false) + +#define to_drm_gpuva(__node) container_of((__node), struct drm_gpuva, rb.node) + +#define GPUVA_START(node) ((node)->va.addr) +#define GPUVA_LAST(node) ((node)->va.addr + (node)->va.range - 1) + +/* We do not actually use drm_gpuva_it_next(), tell the compiler to not complain + * about this. + */ +INTERVAL_TREE_DEFINE(struct drm_gpuva, rb.node, u64, rb.__subtree_last, + GPUVA_START, GPUVA_LAST, static __maybe_unused, + drm_gpuva_it) + +static int __drm_gpuva_insert(struct drm_gpuvm *gpuvm, + struct drm_gpuva *va); +static void __drm_gpuva_remove(struct drm_gpuva *va); + +static bool +drm_gpuvm_check_overflow(u64 addr, u64 range) +{ + u64 end; + + return check_add_overflow(addr, range, &end); +} + +static bool +drm_gpuvm_warn_check_overflow(struct drm_gpuvm *gpuvm, u64 addr, u64 range) +{ + return drm_WARN(gpuvm->drm, drm_gpuvm_check_overflow(addr, range), + "GPUVA address limited to %zu bytes.\n", sizeof(addr)); +} + +static bool +drm_gpuvm_in_mm_range(struct drm_gpuvm *gpuvm, u64 addr, u64 range) +{ + u64 end = addr + range; + u64 mm_start = gpuvm->mm_start; + u64 mm_end = mm_start + gpuvm->mm_range; + + return addr >= mm_start && end <= mm_end; +} + +static bool +drm_gpuvm_in_kernel_node(struct drm_gpuvm *gpuvm, u64 addr, u64 range) +{ + u64 end = addr + range; + u64 kstart = gpuvm->kernel_alloc_node.va.addr; + u64 krange = gpuvm->kernel_alloc_node.va.range; + u64 kend = kstart + krange; + + return krange && addr < kend && kstart < end; +} + +/** + * drm_gpuvm_range_valid() - checks whether the given range is valid for the + * given &drm_gpuvm + * @gpuvm: the GPUVM to check the range for + * @addr: the base address + * @range: the range starting from the base address + * + * Checks whether the range is within the GPUVM's managed boundaries. + * + * Returns: true for a valid range, false otherwise + */ +bool +drm_gpuvm_range_valid(struct drm_gpuvm *gpuvm, + u64 addr, u64 range) +{ + return !drm_gpuvm_check_overflow(addr, range) && + drm_gpuvm_in_mm_range(gpuvm, addr, range) && + !drm_gpuvm_in_kernel_node(gpuvm, addr, range); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_range_valid); + +static void +drm_gpuvm_gem_object_free(struct drm_gem_object *obj) +{ + drm_gem_object_release(obj); + kfree(obj); +} + +static const struct drm_gem_object_funcs drm_gpuvm_object_funcs = { + .free = drm_gpuvm_gem_object_free, +}; + +/** + * drm_gpuvm_resv_object_alloc() - allocate a dummy &drm_gem_object + * @drm: the drivers &drm_device + * + * Allocates a dummy &drm_gem_object which can be passed to drm_gpuvm_init() in + * order to serve as root GEM object providing the &drm_resv shared across + * &drm_gem_objects local to a single GPUVM. + * + * Returns: the &drm_gem_object on success, NULL on failure + */ +struct drm_gem_object * +drm_gpuvm_resv_object_alloc(struct drm_device *drm) +{ + struct drm_gem_object *obj; + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return NULL; + + obj->funcs = &drm_gpuvm_object_funcs; + drm_gem_private_object_init(drm, obj, 0); + + return obj; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_resv_object_alloc); + +/** + * drm_gpuvm_init() - initialize a &drm_gpuvm + * @gpuvm: pointer to the &drm_gpuvm to initialize + * @name: the name of the GPU VA space + * @flags: the &drm_gpuvm_flags for this GPUVM + * @drm: the &drm_device this VM resides in + * @r_obj: the resv &drm_gem_object providing the GPUVM's common &dma_resv + * @start_offset: the start offset of the GPU VA space + * @range: the size of the GPU VA space + * @reserve_offset: the start of the kernel reserved GPU VA area + * @reserve_range: the size of the kernel reserved GPU VA area + * @ops: &drm_gpuvm_ops called on &drm_gpuvm_sm_map / &drm_gpuvm_sm_unmap + * + * The &drm_gpuvm must be initialized with this function before use. + * + * Note that @gpuvm must be cleared to 0 before calling this function. The given + * &name is expected to be managed by the surrounding driver structures. + */ +void +drm_gpuvm_init(struct drm_gpuvm *gpuvm, const char *name, + enum drm_gpuvm_flags flags, + struct drm_device *drm, + struct drm_gem_object *r_obj, + u64 start_offset, u64 range, + u64 reserve_offset, u64 reserve_range, + const struct drm_gpuvm_ops *ops) +{ + gpuvm->rb.tree = RB_ROOT_CACHED; + INIT_LIST_HEAD(&gpuvm->rb.list); + + INIT_LIST_HEAD(&gpuvm->extobj.list); + spin_lock_init(&gpuvm->extobj.lock); + + INIT_LIST_HEAD(&gpuvm->evict.list); + spin_lock_init(&gpuvm->evict.lock); + + kref_init(&gpuvm->kref); + + gpuvm->name = name ? name : "unknown"; + gpuvm->flags = flags; + gpuvm->ops = ops; + gpuvm->drm = drm; + gpuvm->r_obj = r_obj; + + drm_gem_object_get(r_obj); + + drm_gpuvm_warn_check_overflow(gpuvm, start_offset, range); + gpuvm->mm_start = start_offset; + gpuvm->mm_range = range; + + memset(&gpuvm->kernel_alloc_node, 0, sizeof(struct drm_gpuva)); + if (reserve_range) { + gpuvm->kernel_alloc_node.va.addr = reserve_offset; + gpuvm->kernel_alloc_node.va.range = reserve_range; + + if (likely(!drm_gpuvm_warn_check_overflow(gpuvm, reserve_offset, + reserve_range))) + __drm_gpuva_insert(gpuvm, &gpuvm->kernel_alloc_node); + } +} +EXPORT_SYMBOL_GPL(drm_gpuvm_init); + +static void +drm_gpuvm_fini(struct drm_gpuvm *gpuvm) +{ + gpuvm->name = NULL; + + if (gpuvm->kernel_alloc_node.va.range) + __drm_gpuva_remove(&gpuvm->kernel_alloc_node); + + drm_WARN(gpuvm->drm, !RB_EMPTY_ROOT(&gpuvm->rb.tree.rb_root), + "GPUVA tree is not empty, potentially leaking memory.\n"); + + drm_WARN(gpuvm->drm, !list_empty(&gpuvm->extobj.list), + "Extobj list should be empty.\n"); + drm_WARN(gpuvm->drm, !list_empty(&gpuvm->evict.list), + "Evict list should be empty.\n"); + + drm_gem_object_put(gpuvm->r_obj); +} + +static void +drm_gpuvm_free(struct kref *kref) +{ + struct drm_gpuvm *gpuvm = container_of(kref, struct drm_gpuvm, kref); + + drm_gpuvm_fini(gpuvm); + + if (drm_WARN_ON(gpuvm->drm, !gpuvm->ops->vm_free)) + return; + + gpuvm->ops->vm_free(gpuvm); +} + +/** + * drm_gpuvm_put() - drop a struct drm_gpuvm reference + * @gpuvm: the &drm_gpuvm to release the reference of + * + * This releases a reference to @gpuvm. + * + * This function may be called from atomic context. + */ +void +drm_gpuvm_put(struct drm_gpuvm *gpuvm) +{ + if (gpuvm) + kref_put(&gpuvm->kref, drm_gpuvm_free); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_put); + +static int +exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, + unsigned int num_fences) +{ + return num_fences ? drm_exec_prepare_obj(exec, obj, num_fences) : + drm_exec_lock_obj(exec, obj); +} + +/** + * drm_gpuvm_prepare_vm() - prepare the GPUVMs common dma-resv + * @gpuvm: the &drm_gpuvm + * @exec: the &drm_exec context + * @num_fences: the amount of &dma_fences to reserve + * + * Calls drm_exec_prepare_obj() for the GPUVMs dummy &drm_gem_object; if + * @num_fences is zero drm_exec_lock_obj() is called instead. + * + * Using this function directly, it is the drivers responsibility to call + * drm_exec_init() and drm_exec_fini() accordingly. + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuvm_prepare_vm(struct drm_gpuvm *gpuvm, + struct drm_exec *exec, + unsigned int num_fences) +{ + return exec_prepare_obj(exec, gpuvm->r_obj, num_fences); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_prepare_vm); + +static int +__drm_gpuvm_prepare_objects(struct drm_gpuvm *gpuvm, + struct drm_exec *exec, + unsigned int num_fences) +{ + struct drm_gpuvm_bo *vm_bo; + LIST_HEAD(extobjs); + int ret = 0; + + for_each_vm_bo_in_list(gpuvm, extobj, &extobjs, vm_bo) { + ret = exec_prepare_obj(exec, vm_bo->obj, num_fences); + if (ret) + break; + } + /* Drop ref in case we break out of the loop. */ + drm_gpuvm_bo_put(vm_bo); + restore_vm_bo_list(gpuvm, extobj); + + return ret; +} + +static int +drm_gpuvm_prepare_objects_locked(struct drm_gpuvm *gpuvm, + struct drm_exec *exec, + unsigned int num_fences) +{ + struct drm_gpuvm_bo *vm_bo; + int ret = 0; + + drm_gpuvm_resv_assert_held(gpuvm); + list_for_each_entry(vm_bo, &gpuvm->extobj.list, list.entry.extobj) { + ret = exec_prepare_obj(exec, vm_bo->obj, num_fences); + if (ret) + break; + + if (vm_bo->evicted) + drm_gpuvm_bo_list_add(vm_bo, evict, false); + } + + return ret; +} + +/** + * drm_gpuvm_prepare_objects() - prepare all assoiciated BOs + * @gpuvm: the &drm_gpuvm + * @exec: the &drm_exec locking context + * @num_fences: the amount of &dma_fences to reserve + * + * Calls drm_exec_prepare_obj() for all &drm_gem_objects the given + * &drm_gpuvm contains mappings of; if @num_fences is zero drm_exec_lock_obj() + * is called instead. + * + * Using this function directly, it is the drivers responsibility to call + * drm_exec_init() and drm_exec_fini() accordingly. + * + * Note: This function is safe against concurrent insertion and removal of + * external objects, however it is not safe against concurrent usage itself. + * + * Drivers need to make sure to protect this case with either an outer VM lock + * or by calling drm_gpuvm_prepare_vm() before this function within the + * drm_exec_until_all_locked() loop, such that the GPUVM's dma-resv lock ensures + * mutual exclusion. + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuvm_prepare_objects(struct drm_gpuvm *gpuvm, + struct drm_exec *exec, + unsigned int num_fences) +{ + if (drm_gpuvm_resv_protected(gpuvm)) + return drm_gpuvm_prepare_objects_locked(gpuvm, exec, + num_fences); + else + return __drm_gpuvm_prepare_objects(gpuvm, exec, num_fences); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_prepare_objects); + +/** + * drm_gpuvm_prepare_range() - prepare all BOs mapped within a given range + * @gpuvm: the &drm_gpuvm + * @exec: the &drm_exec locking context + * @addr: the start address within the VA space + * @range: the range to iterate within the VA space + * @num_fences: the amount of &dma_fences to reserve + * + * Calls drm_exec_prepare_obj() for all &drm_gem_objects mapped between @addr + * and @addr + @range; if @num_fences is zero drm_exec_lock_obj() is called + * instead. + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuvm_prepare_range(struct drm_gpuvm *gpuvm, struct drm_exec *exec, + u64 addr, u64 range, unsigned int num_fences) +{ + struct drm_gpuva *va; + u64 end = addr + range; + int ret; + + drm_gpuvm_for_each_va_range(va, gpuvm, addr, end) { + struct drm_gem_object *obj = va->gem.obj; + + ret = exec_prepare_obj(exec, obj, num_fences); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_prepare_range); + +/** + * drm_gpuvm_exec_lock() - lock all dma-resv of all assoiciated BOs + * @vm_exec: the &drm_gpuvm_exec wrapper + * + * Acquires all dma-resv locks of all &drm_gem_objects the given + * &drm_gpuvm contains mappings of. + * + * Addionally, when calling this function with struct drm_gpuvm_exec::extra + * being set the driver receives the given @fn callback to lock additional + * dma-resv in the context of the &drm_gpuvm_exec instance. Typically, drivers + * would call drm_exec_prepare_obj() from within this callback. + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuvm_exec_lock(struct drm_gpuvm_exec *vm_exec) +{ + struct drm_gpuvm *gpuvm = vm_exec->vm; + struct drm_exec *exec = &vm_exec->exec; + unsigned int num_fences = vm_exec->num_fences; + int ret; + + drm_exec_init(exec, vm_exec->flags, 0); + + drm_exec_until_all_locked(exec) { + ret = drm_gpuvm_prepare_vm(gpuvm, exec, num_fences); + drm_exec_retry_on_contention(exec); + if (ret) + goto err; + + ret = drm_gpuvm_prepare_objects(gpuvm, exec, num_fences); + drm_exec_retry_on_contention(exec); + if (ret) + goto err; + + if (vm_exec->extra.fn) { + ret = vm_exec->extra.fn(vm_exec); + drm_exec_retry_on_contention(exec); + if (ret) + goto err; + } + } + + return 0; + +err: + drm_exec_fini(exec); + return ret; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_exec_lock); + +static int +fn_lock_array(struct drm_gpuvm_exec *vm_exec) +{ + struct { + struct drm_gem_object **objs; + unsigned int num_objs; + } *args = vm_exec->extra.priv; + + return drm_exec_prepare_array(&vm_exec->exec, args->objs, + args->num_objs, vm_exec->num_fences); +} + +/** + * drm_gpuvm_exec_lock_array() - lock all dma-resv of all assoiciated BOs + * @vm_exec: the &drm_gpuvm_exec wrapper + * @objs: additional &drm_gem_objects to lock + * @num_objs: the number of additional &drm_gem_objects to lock + * + * Acquires all dma-resv locks of all &drm_gem_objects the given &drm_gpuvm + * contains mappings of, plus the ones given through @objs. + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuvm_exec_lock_array(struct drm_gpuvm_exec *vm_exec, + struct drm_gem_object **objs, + unsigned int num_objs) +{ + struct { + struct drm_gem_object **objs; + unsigned int num_objs; + } args; + + args.objs = objs; + args.num_objs = num_objs; + + vm_exec->extra.fn = fn_lock_array; + vm_exec->extra.priv = &args; + + return drm_gpuvm_exec_lock(vm_exec); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_exec_lock_array); + +/** + * drm_gpuvm_exec_lock_range() - prepare all BOs mapped within a given range + * @vm_exec: the &drm_gpuvm_exec wrapper + * @addr: the start address within the VA space + * @range: the range to iterate within the VA space + * + * Acquires all dma-resv locks of all &drm_gem_objects mapped between @addr and + * @addr + @range. + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuvm_exec_lock_range(struct drm_gpuvm_exec *vm_exec, + u64 addr, u64 range) +{ + struct drm_gpuvm *gpuvm = vm_exec->vm; + struct drm_exec *exec = &vm_exec->exec; + int ret; + + drm_exec_init(exec, vm_exec->flags, 0); + + drm_exec_until_all_locked(exec) { + ret = drm_gpuvm_prepare_range(gpuvm, exec, addr, range, + vm_exec->num_fences); + drm_exec_retry_on_contention(exec); + if (ret) + goto err; + } + + return ret; + +err: + drm_exec_fini(exec); + return ret; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_exec_lock_range); + +static int +__drm_gpuvm_validate(struct drm_gpuvm *gpuvm, struct drm_exec *exec) +{ + const struct drm_gpuvm_ops *ops = gpuvm->ops; + struct drm_gpuvm_bo *vm_bo; + LIST_HEAD(evict); + int ret = 0; + + for_each_vm_bo_in_list(gpuvm, evict, &evict, vm_bo) { + ret = ops->vm_bo_validate(vm_bo, exec); + if (ret) + break; + } + /* Drop ref in case we break out of the loop. */ + drm_gpuvm_bo_put(vm_bo); + restore_vm_bo_list(gpuvm, evict); + + return ret; +} + +static int +drm_gpuvm_validate_locked(struct drm_gpuvm *gpuvm, struct drm_exec *exec) +{ + const struct drm_gpuvm_ops *ops = gpuvm->ops; + struct drm_gpuvm_bo *vm_bo, *next; + int ret = 0; + + drm_gpuvm_resv_assert_held(gpuvm); + + list_for_each_entry_safe(vm_bo, next, &gpuvm->evict.list, + list.entry.evict) { + ret = ops->vm_bo_validate(vm_bo, exec); + if (ret) + break; + + dma_resv_assert_held(vm_bo->obj->resv); + if (!vm_bo->evicted) + drm_gpuvm_bo_list_del_init(vm_bo, evict, false); + } + + return ret; +} + +/** + * drm_gpuvm_validate() - validate all BOs marked as evicted + * @gpuvm: the &drm_gpuvm to validate evicted BOs + * @exec: the &drm_exec instance used for locking the GPUVM + * + * Calls the &drm_gpuvm_ops::vm_bo_validate callback for all evicted buffer + * objects being mapped in the given &drm_gpuvm. + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuvm_validate(struct drm_gpuvm *gpuvm, struct drm_exec *exec) +{ + const struct drm_gpuvm_ops *ops = gpuvm->ops; + + if (unlikely(!ops || !ops->vm_bo_validate)) + return -EOPNOTSUPP; + + if (drm_gpuvm_resv_protected(gpuvm)) + return drm_gpuvm_validate_locked(gpuvm, exec); + else + return __drm_gpuvm_validate(gpuvm, exec); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_validate); + +/** + * drm_gpuvm_resv_add_fence - add fence to private and all extobj + * dma-resv + * @gpuvm: the &drm_gpuvm to add a fence to + * @exec: the &drm_exec locking context + * @fence: fence to add + * @private_usage: private dma-resv usage + * @extobj_usage: extobj dma-resv usage + */ +void +drm_gpuvm_resv_add_fence(struct drm_gpuvm *gpuvm, + struct drm_exec *exec, + struct dma_fence *fence, + enum dma_resv_usage private_usage, + enum dma_resv_usage extobj_usage) +{ + struct drm_gem_object *obj; + unsigned long index; + + drm_exec_for_each_locked_object(exec, index, obj) { + dma_resv_assert_held(obj->resv); + dma_resv_add_fence(obj->resv, fence, + drm_gpuvm_is_extobj(gpuvm, obj) ? + extobj_usage : private_usage); + } +} +EXPORT_SYMBOL_GPL(drm_gpuvm_resv_add_fence); + +/** + * drm_gpuvm_bo_create() - create a new instance of struct drm_gpuvm_bo + * @gpuvm: The &drm_gpuvm the @obj is mapped in. + * @obj: The &drm_gem_object being mapped in the @gpuvm. + * + * If provided by the driver, this function uses the &drm_gpuvm_ops + * vm_bo_alloc() callback to allocate. + * + * Returns: a pointer to the &drm_gpuvm_bo on success, NULL on failure + */ +struct drm_gpuvm_bo * +drm_gpuvm_bo_create(struct drm_gpuvm *gpuvm, + struct drm_gem_object *obj) +{ + const struct drm_gpuvm_ops *ops = gpuvm->ops; + struct drm_gpuvm_bo *vm_bo; + + if (ops && ops->vm_bo_alloc) + vm_bo = ops->vm_bo_alloc(); + else + vm_bo = kzalloc(sizeof(*vm_bo), GFP_KERNEL); + + if (unlikely(!vm_bo)) + return NULL; + + vm_bo->vm = drm_gpuvm_get(gpuvm); + vm_bo->obj = obj; + drm_gem_object_get(obj); + + kref_init(&vm_bo->kref); + INIT_LIST_HEAD(&vm_bo->list.gpuva); + INIT_LIST_HEAD(&vm_bo->list.entry.gem); + + INIT_LIST_HEAD(&vm_bo->list.entry.extobj); + INIT_LIST_HEAD(&vm_bo->list.entry.evict); + + return vm_bo; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_create); + +static void +drm_gpuvm_bo_destroy(struct kref *kref) +{ + struct drm_gpuvm_bo *vm_bo = container_of(kref, struct drm_gpuvm_bo, + kref); + struct drm_gpuvm *gpuvm = vm_bo->vm; + const struct drm_gpuvm_ops *ops = gpuvm->ops; + struct drm_gem_object *obj = vm_bo->obj; + bool lock = !drm_gpuvm_resv_protected(gpuvm); + + if (!lock) + drm_gpuvm_resv_assert_held(gpuvm); + + drm_gpuvm_bo_list_del(vm_bo, extobj, lock); + drm_gpuvm_bo_list_del(vm_bo, evict, lock); + + drm_gem_gpuva_assert_lock_held(obj); + list_del(&vm_bo->list.entry.gem); + + if (ops && ops->vm_bo_free) + ops->vm_bo_free(vm_bo); + else + kfree(vm_bo); + + drm_gpuvm_put(gpuvm); + drm_gem_object_put(obj); +} + +/** + * drm_gpuvm_bo_put() - drop a struct drm_gpuvm_bo reference + * @vm_bo: the &drm_gpuvm_bo to release the reference of + * + * This releases a reference to @vm_bo. + * + * If the reference count drops to zero, the &gpuvm_bo is destroyed, which + * includes removing it from the GEMs gpuva list. Hence, if a call to this + * function can potentially let the reference count drop to zero the caller must + * hold the dma-resv or driver specific GEM gpuva lock. + * + * This function may only be called from non-atomic context. + * + * Returns: true if vm_bo was destroyed, false otherwise. + */ +bool +drm_gpuvm_bo_put(struct drm_gpuvm_bo *vm_bo) +{ + might_sleep(); + + if (vm_bo) + return !!kref_put(&vm_bo->kref, drm_gpuvm_bo_destroy); + + return false; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_put); + +static struct drm_gpuvm_bo * +__drm_gpuvm_bo_find(struct drm_gpuvm *gpuvm, + struct drm_gem_object *obj) +{ + struct drm_gpuvm_bo *vm_bo; + + drm_gem_gpuva_assert_lock_held(obj); + drm_gem_for_each_gpuvm_bo(vm_bo, obj) + if (vm_bo->vm == gpuvm) + return vm_bo; + + return NULL; +} + +/** + * drm_gpuvm_bo_find() - find the &drm_gpuvm_bo for the given + * &drm_gpuvm and &drm_gem_object + * @gpuvm: The &drm_gpuvm the @obj is mapped in. + * @obj: The &drm_gem_object being mapped in the @gpuvm. + * + * Find the &drm_gpuvm_bo representing the combination of the given + * &drm_gpuvm and &drm_gem_object. If found, increases the reference + * count of the &drm_gpuvm_bo accordingly. + * + * Returns: a pointer to the &drm_gpuvm_bo on success, NULL on failure + */ +struct drm_gpuvm_bo * +drm_gpuvm_bo_find(struct drm_gpuvm *gpuvm, + struct drm_gem_object *obj) +{ + struct drm_gpuvm_bo *vm_bo = __drm_gpuvm_bo_find(gpuvm, obj); + + return vm_bo ? drm_gpuvm_bo_get(vm_bo) : NULL; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_find); + +/** + * drm_gpuvm_bo_obtain() - obtains and instance of the &drm_gpuvm_bo for the + * given &drm_gpuvm and &drm_gem_object + * @gpuvm: The &drm_gpuvm the @obj is mapped in. + * @obj: The &drm_gem_object being mapped in the @gpuvm. + * + * Find the &drm_gpuvm_bo representing the combination of the given + * &drm_gpuvm and &drm_gem_object. If found, increases the reference + * count of the &drm_gpuvm_bo accordingly. If not found, allocates a new + * &drm_gpuvm_bo. + * + * A new &drm_gpuvm_bo is added to the GEMs gpuva list. + * + * Returns: a pointer to the &drm_gpuvm_bo on success, an ERR_PTR on failure + */ +struct drm_gpuvm_bo * +drm_gpuvm_bo_obtain(struct drm_gpuvm *gpuvm, + struct drm_gem_object *obj) +{ + struct drm_gpuvm_bo *vm_bo; + + vm_bo = drm_gpuvm_bo_find(gpuvm, obj); + if (vm_bo) + return vm_bo; + + vm_bo = drm_gpuvm_bo_create(gpuvm, obj); + if (!vm_bo) + return ERR_PTR(-ENOMEM); + + drm_gem_gpuva_assert_lock_held(obj); + list_add_tail(&vm_bo->list.entry.gem, &obj->gpuva.list); + + return vm_bo; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_obtain); + +/** + * drm_gpuvm_bo_obtain_prealloc() - obtains and instance of the &drm_gpuvm_bo + * for the given &drm_gpuvm and &drm_gem_object + * @__vm_bo: A pre-allocated struct drm_gpuvm_bo. + * + * Find the &drm_gpuvm_bo representing the combination of the given + * &drm_gpuvm and &drm_gem_object. If found, increases the reference + * count of the found &drm_gpuvm_bo accordingly, while the @__vm_bo reference + * count is decreased. If not found @__vm_bo is returned without further + * increase of the reference count. + * + * A new &drm_gpuvm_bo is added to the GEMs gpuva list. + * + * Returns: a pointer to the found &drm_gpuvm_bo or @__vm_bo if no existing + * &drm_gpuvm_bo was found + */ +struct drm_gpuvm_bo * +drm_gpuvm_bo_obtain_prealloc(struct drm_gpuvm_bo *__vm_bo) +{ + struct drm_gpuvm *gpuvm = __vm_bo->vm; + struct drm_gem_object *obj = __vm_bo->obj; + struct drm_gpuvm_bo *vm_bo; + + vm_bo = drm_gpuvm_bo_find(gpuvm, obj); + if (vm_bo) { + drm_gpuvm_bo_put(__vm_bo); + return vm_bo; + } + + drm_gem_gpuva_assert_lock_held(obj); + list_add_tail(&__vm_bo->list.entry.gem, &obj->gpuva.list); + + return __vm_bo; +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_obtain_prealloc); + +/** + * drm_gpuvm_bo_extobj_add() - adds the &drm_gpuvm_bo to its &drm_gpuvm's + * extobj list + * @vm_bo: The &drm_gpuvm_bo to add to its &drm_gpuvm's the extobj list. + * + * Adds the given @vm_bo to its &drm_gpuvm's extobj list if not on the list + * already and if the corresponding &drm_gem_object is an external object, + * actually. + */ +void +drm_gpuvm_bo_extobj_add(struct drm_gpuvm_bo *vm_bo) +{ + struct drm_gpuvm *gpuvm = vm_bo->vm; + bool lock = !drm_gpuvm_resv_protected(gpuvm); + + if (!lock) + drm_gpuvm_resv_assert_held(gpuvm); + + if (drm_gpuvm_is_extobj(gpuvm, vm_bo->obj)) + drm_gpuvm_bo_list_add(vm_bo, extobj, lock); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_extobj_add); + +/** + * drm_gpuvm_bo_evict() - add / remove a &drm_gpuvm_bo to / from the &drm_gpuvms + * evicted list + * @vm_bo: the &drm_gpuvm_bo to add or remove + * @evict: indicates whether the object is evicted + * + * Adds a &drm_gpuvm_bo to or removes it from the &drm_gpuvms evicted list. + */ +void +drm_gpuvm_bo_evict(struct drm_gpuvm_bo *vm_bo, bool evict) +{ + struct drm_gpuvm *gpuvm = vm_bo->vm; + struct drm_gem_object *obj = vm_bo->obj; + bool lock = !drm_gpuvm_resv_protected(gpuvm); + + dma_resv_assert_held(obj->resv); + vm_bo->evicted = evict; + + /* Can't add external objects to the evicted list directly if not using + * internal spinlocks, since in this case the evicted list is protected + * with the VM's common dma-resv lock. + */ + if (drm_gpuvm_is_extobj(gpuvm, obj) && !lock) + return; + + if (evict) + drm_gpuvm_bo_list_add(vm_bo, evict, lock); + else + drm_gpuvm_bo_list_del_init(vm_bo, evict, lock); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_evict); + +static int +__drm_gpuva_insert(struct drm_gpuvm *gpuvm, + struct drm_gpuva *va) +{ + struct rb_node *node; + struct list_head *head; + + if (drm_gpuva_it_iter_first(&gpuvm->rb.tree, + GPUVA_START(va), + GPUVA_LAST(va))) + return -EEXIST; + + va->vm = gpuvm; + + drm_gpuva_it_insert(va, &gpuvm->rb.tree); + + node = rb_prev(&va->rb.node); + if (node) + head = &(to_drm_gpuva(node))->rb.entry; + else + head = &gpuvm->rb.list; + + list_add(&va->rb.entry, head); + + return 0; +} + +/** + * drm_gpuva_insert() - insert a &drm_gpuva + * @gpuvm: the &drm_gpuvm to insert the &drm_gpuva in + * @va: the &drm_gpuva to insert + * + * Insert a &drm_gpuva with a given address and range into a + * &drm_gpuvm. + * + * It is safe to use this function using the safe versions of iterating the GPU + * VA space, such as drm_gpuvm_for_each_va_safe() and + * drm_gpuvm_for_each_va_range_safe(). + * + * Returns: 0 on success, negative error code on failure. + */ +int +drm_gpuva_insert(struct drm_gpuvm *gpuvm, + struct drm_gpuva *va) +{ + u64 addr = va->va.addr; + u64 range = va->va.range; + int ret; + + if (unlikely(!drm_gpuvm_range_valid(gpuvm, addr, range))) + return -EINVAL; + + ret = __drm_gpuva_insert(gpuvm, va); + if (likely(!ret)) + /* Take a reference of the GPUVM for the successfully inserted + * drm_gpuva. We can't take the reference in + * __drm_gpuva_insert() itself, since we don't want to increse + * the reference count for the GPUVM's kernel_alloc_node. + */ + drm_gpuvm_get(gpuvm); + + return ret; +} +EXPORT_SYMBOL_GPL(drm_gpuva_insert); + +static void +__drm_gpuva_remove(struct drm_gpuva *va) +{ + drm_gpuva_it_remove(va, &va->vm->rb.tree); + list_del_init(&va->rb.entry); +} + +/** + * drm_gpuva_remove() - remove a &drm_gpuva + * @va: the &drm_gpuva to remove + * + * This removes the given &va from the underlaying tree. + * + * It is safe to use this function using the safe versions of iterating the GPU + * VA space, such as drm_gpuvm_for_each_va_safe() and + * drm_gpuvm_for_each_va_range_safe(). + */ +void +drm_gpuva_remove(struct drm_gpuva *va) +{ + struct drm_gpuvm *gpuvm = va->vm; + + if (unlikely(va == &gpuvm->kernel_alloc_node)) { + drm_WARN(gpuvm->drm, 1, + "Can't destroy kernel reserved node.\n"); + return; + } + + __drm_gpuva_remove(va); + drm_gpuvm_put(va->vm); +} +EXPORT_SYMBOL_GPL(drm_gpuva_remove); + +/** + * drm_gpuva_link() - link a &drm_gpuva + * @va: the &drm_gpuva to link + * @vm_bo: the &drm_gpuvm_bo to add the &drm_gpuva to + * + * This adds the given &va to the GPU VA list of the &drm_gpuvm_bo and the + * &drm_gpuvm_bo to the &drm_gem_object it is associated with. + * + * For every &drm_gpuva entry added to the &drm_gpuvm_bo an additional + * reference of the latter is taken. + * + * This function expects the caller to protect the GEM's GPUVA list against + * concurrent access using either the GEMs dma_resv lock or a driver specific + * lock set through drm_gem_gpuva_set_lock(). + */ +void +drm_gpuva_link(struct drm_gpuva *va, struct drm_gpuvm_bo *vm_bo) +{ + struct drm_gem_object *obj = va->gem.obj; + struct drm_gpuvm *gpuvm = va->vm; + + if (unlikely(!obj)) + return; + + drm_WARN_ON(gpuvm->drm, obj != vm_bo->obj); + + va->vm_bo = drm_gpuvm_bo_get(vm_bo); + + drm_gem_gpuva_assert_lock_held(obj); + list_add_tail(&va->gem.entry, &vm_bo->list.gpuva); +} +EXPORT_SYMBOL_GPL(drm_gpuva_link); + +/** + * drm_gpuva_unlink() - unlink a &drm_gpuva + * @va: the &drm_gpuva to unlink + * + * This removes the given &va from the GPU VA list of the &drm_gem_object it is + * associated with. + * + * This removes the given &va from the GPU VA list of the &drm_gpuvm_bo and + * the &drm_gpuvm_bo from the &drm_gem_object it is associated with in case + * this call unlinks the last &drm_gpuva from the &drm_gpuvm_bo. + * + * For every &drm_gpuva entry removed from the &drm_gpuvm_bo a reference of + * the latter is dropped. + * + * This function expects the caller to protect the GEM's GPUVA list against + * concurrent access using either the GEMs dma_resv lock or a driver specific + * lock set through drm_gem_gpuva_set_lock(). + */ +void +drm_gpuva_unlink(struct drm_gpuva *va) +{ + struct drm_gem_object *obj = va->gem.obj; + struct drm_gpuvm_bo *vm_bo = va->vm_bo; + + if (unlikely(!obj)) + return; + + drm_gem_gpuva_assert_lock_held(obj); + list_del_init(&va->gem.entry); + + va->vm_bo = NULL; + drm_gpuvm_bo_put(vm_bo); +} +EXPORT_SYMBOL_GPL(drm_gpuva_unlink); + +/** + * drm_gpuva_find_first() - find the first &drm_gpuva in the given range + * @gpuvm: the &drm_gpuvm to search in + * @addr: the &drm_gpuvas address + * @range: the &drm_gpuvas range + * + * Returns: the first &drm_gpuva within the given range + */ +struct drm_gpuva * +drm_gpuva_find_first(struct drm_gpuvm *gpuvm, + u64 addr, u64 range) +{ + u64 last = addr + range - 1; + + return drm_gpuva_it_iter_first(&gpuvm->rb.tree, addr, last); +} +EXPORT_SYMBOL_GPL(drm_gpuva_find_first); + +/** + * drm_gpuva_find() - find a &drm_gpuva + * @gpuvm: the &drm_gpuvm to search in + * @addr: the &drm_gpuvas address + * @range: the &drm_gpuvas range + * + * Returns: the &drm_gpuva at a given &addr and with a given &range + */ +struct drm_gpuva * +drm_gpuva_find(struct drm_gpuvm *gpuvm, + u64 addr, u64 range) +{ + struct drm_gpuva *va; + + va = drm_gpuva_find_first(gpuvm, addr, range); + if (!va) + goto out; + + if (va->va.addr != addr || + va->va.range != range) + goto out; + + return va; + +out: + return NULL; +} +EXPORT_SYMBOL_GPL(drm_gpuva_find); + +/** + * drm_gpuva_find_prev() - find the &drm_gpuva before the given address + * @gpuvm: the &drm_gpuvm to search in + * @start: the given GPU VA's start address + * + * Find the adjacent &drm_gpuva before the GPU VA with given &start address. + * + * Note that if there is any free space between the GPU VA mappings no mapping + * is returned. + * + * Returns: a pointer to the found &drm_gpuva or NULL if none was found + */ +struct drm_gpuva * +drm_gpuva_find_prev(struct drm_gpuvm *gpuvm, u64 start) +{ + if (!drm_gpuvm_range_valid(gpuvm, start - 1, 1)) + return NULL; + + return drm_gpuva_it_iter_first(&gpuvm->rb.tree, start - 1, start); +} +EXPORT_SYMBOL_GPL(drm_gpuva_find_prev); + +/** + * drm_gpuva_find_next() - find the &drm_gpuva after the given address + * @gpuvm: the &drm_gpuvm to search in + * @end: the given GPU VA's end address + * + * Find the adjacent &drm_gpuva after the GPU VA with given &end address. + * + * Note that if there is any free space between the GPU VA mappings no mapping + * is returned. + * + * Returns: a pointer to the found &drm_gpuva or NULL if none was found + */ +struct drm_gpuva * +drm_gpuva_find_next(struct drm_gpuvm *gpuvm, u64 end) +{ + if (!drm_gpuvm_range_valid(gpuvm, end, 1)) + return NULL; + + return drm_gpuva_it_iter_first(&gpuvm->rb.tree, end, end + 1); +} +EXPORT_SYMBOL_GPL(drm_gpuva_find_next); + +/** + * drm_gpuvm_interval_empty() - indicate whether a given interval of the VA space + * is empty + * @gpuvm: the &drm_gpuvm to check the range for + * @addr: the start address of the range + * @range: the range of the interval + * + * Returns: true if the interval is empty, false otherwise + */ +bool +drm_gpuvm_interval_empty(struct drm_gpuvm *gpuvm, u64 addr, u64 range) +{ + return !drm_gpuva_find_first(gpuvm, addr, range); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_interval_empty); + +/** + * drm_gpuva_map() - helper to insert a &drm_gpuva according to a + * &drm_gpuva_op_map + * @gpuvm: the &drm_gpuvm + * @va: the &drm_gpuva to insert + * @op: the &drm_gpuva_op_map to initialize @va with + * + * Initializes the @va from the @op and inserts it into the given @gpuvm. + */ +void +drm_gpuva_map(struct drm_gpuvm *gpuvm, + struct drm_gpuva *va, + struct drm_gpuva_op_map *op) +{ + drm_gpuva_init_from_op(va, op); + drm_gpuva_insert(gpuvm, va); +} +EXPORT_SYMBOL_GPL(drm_gpuva_map); + +/** + * drm_gpuva_remap() - helper to remap a &drm_gpuva according to a + * &drm_gpuva_op_remap + * @prev: the &drm_gpuva to remap when keeping the start of a mapping + * @next: the &drm_gpuva to remap when keeping the end of a mapping + * @op: the &drm_gpuva_op_remap to initialize @prev and @next with + * + * Removes the currently mapped &drm_gpuva and remaps it using @prev and/or + * @next. + */ +void +drm_gpuva_remap(struct drm_gpuva *prev, + struct drm_gpuva *next, + struct drm_gpuva_op_remap *op) +{ + struct drm_gpuva *va = op->unmap->va; + struct drm_gpuvm *gpuvm = va->vm; + + drm_gpuva_remove(va); + + if (op->prev) { + drm_gpuva_init_from_op(prev, op->prev); + drm_gpuva_insert(gpuvm, prev); + } + + if (op->next) { + drm_gpuva_init_from_op(next, op->next); + drm_gpuva_insert(gpuvm, next); + } +} +EXPORT_SYMBOL_GPL(drm_gpuva_remap); + +/** + * drm_gpuva_unmap() - helper to remove a &drm_gpuva according to a + * &drm_gpuva_op_unmap + * @op: the &drm_gpuva_op_unmap specifying the &drm_gpuva to remove + * + * Removes the &drm_gpuva associated with the &drm_gpuva_op_unmap. + */ +void +drm_gpuva_unmap(struct drm_gpuva_op_unmap *op) +{ + drm_gpuva_remove(op->va); +} +EXPORT_SYMBOL_GPL(drm_gpuva_unmap); + +static int +op_map_cb(const struct drm_gpuvm_ops *fn, void *priv, + u64 addr, u64 range, + struct drm_gem_object *obj, u64 offset) +{ + struct drm_gpuva_op op = {}; + + op.op = DRM_GPUVA_OP_MAP; + op.map.va.addr = addr; + op.map.va.range = range; + op.map.gem.obj = obj; + op.map.gem.offset = offset; + + return fn->sm_step_map(&op, priv); +} + +static int +op_remap_cb(const struct drm_gpuvm_ops *fn, void *priv, + struct drm_gpuva_op_map *prev, + struct drm_gpuva_op_map *next, + struct drm_gpuva_op_unmap *unmap) +{ + struct drm_gpuva_op op = {}; + struct drm_gpuva_op_remap *r; + + op.op = DRM_GPUVA_OP_REMAP; + r = &op.remap; + r->prev = prev; + r->next = next; + r->unmap = unmap; + + return fn->sm_step_remap(&op, priv); +} + +static int +op_unmap_cb(const struct drm_gpuvm_ops *fn, void *priv, + struct drm_gpuva *va, bool merge) +{ + struct drm_gpuva_op op = {}; + + op.op = DRM_GPUVA_OP_UNMAP; + op.unmap.va = va; + op.unmap.keep = merge; + + return fn->sm_step_unmap(&op, priv); +} + +static int +__drm_gpuvm_sm_map(struct drm_gpuvm *gpuvm, + const struct drm_gpuvm_ops *ops, void *priv, + u64 req_addr, u64 req_range, + struct drm_gem_object *req_obj, u64 req_offset) +{ + struct drm_gpuva *va, *next; + u64 req_end = req_addr + req_range; + int ret; + + if (unlikely(!drm_gpuvm_range_valid(gpuvm, req_addr, req_range))) + return -EINVAL; + + drm_gpuvm_for_each_va_range_safe(va, next, gpuvm, req_addr, req_end) { + struct drm_gem_object *obj = va->gem.obj; + u64 offset = va->gem.offset; + u64 addr = va->va.addr; + u64 range = va->va.range; + u64 end = addr + range; + bool merge = !!va->gem.obj; + + if (addr == req_addr) { + merge &= obj == req_obj && + offset == req_offset; + + if (end == req_end) { + ret = op_unmap_cb(ops, priv, va, merge); + if (ret) + return ret; + break; + } + + if (end < req_end) { + ret = op_unmap_cb(ops, priv, va, merge); + if (ret) + return ret; + continue; + } + + if (end > req_end) { + struct drm_gpuva_op_map n = { + .va.addr = req_end, + .va.range = range - req_range, + .gem.obj = obj, + .gem.offset = offset + req_range, + }; + struct drm_gpuva_op_unmap u = { + .va = va, + .keep = merge, + }; + + ret = op_remap_cb(ops, priv, NULL, &n, &u); + if (ret) + return ret; + break; + } + } else if (addr < req_addr) { + u64 ls_range = req_addr - addr; + struct drm_gpuva_op_map p = { + .va.addr = addr, + .va.range = ls_range, + .gem.obj = obj, + .gem.offset = offset, + }; + struct drm_gpuva_op_unmap u = { .va = va }; + + merge &= obj == req_obj && + offset + ls_range == req_offset; + u.keep = merge; + + if (end == req_end) { + ret = op_remap_cb(ops, priv, &p, NULL, &u); + if (ret) + return ret; + break; + } + + if (end < req_end) { + ret = op_remap_cb(ops, priv, &p, NULL, &u); + if (ret) + return ret; + continue; + } + + if (end > req_end) { + struct drm_gpuva_op_map n = { + .va.addr = req_end, + .va.range = end - req_end, + .gem.obj = obj, + .gem.offset = offset + ls_range + + req_range, + }; + + ret = op_remap_cb(ops, priv, &p, &n, &u); + if (ret) + return ret; + break; + } + } else if (addr > req_addr) { + merge &= obj == req_obj && + offset == req_offset + + (addr - req_addr); + + if (end == req_end) { + ret = op_unmap_cb(ops, priv, va, merge); + if (ret) + return ret; + break; + } + + if (end < req_end) { + ret = op_unmap_cb(ops, priv, va, merge); + if (ret) + return ret; + continue; + } + + if (end > req_end) { + struct drm_gpuva_op_map n = { + .va.addr = req_end, + .va.range = end - req_end, + .gem.obj = obj, + .gem.offset = offset + req_end - addr, + }; + struct drm_gpuva_op_unmap u = { + .va = va, + .keep = merge, + }; + + ret = op_remap_cb(ops, priv, NULL, &n, &u); + if (ret) + return ret; + break; + } + } + } + + return op_map_cb(ops, priv, + req_addr, req_range, + req_obj, req_offset); +} + +static int +__drm_gpuvm_sm_unmap(struct drm_gpuvm *gpuvm, + const struct drm_gpuvm_ops *ops, void *priv, + u64 req_addr, u64 req_range) +{ + struct drm_gpuva *va, *next; + u64 req_end = req_addr + req_range; + int ret; + + if (unlikely(!drm_gpuvm_range_valid(gpuvm, req_addr, req_range))) + return -EINVAL; + + drm_gpuvm_for_each_va_range_safe(va, next, gpuvm, req_addr, req_end) { + struct drm_gpuva_op_map prev = {}, next = {}; + bool prev_split = false, next_split = false; + struct drm_gem_object *obj = va->gem.obj; + u64 offset = va->gem.offset; + u64 addr = va->va.addr; + u64 range = va->va.range; + u64 end = addr + range; + + if (addr < req_addr) { + prev.va.addr = addr; + prev.va.range = req_addr - addr; + prev.gem.obj = obj; + prev.gem.offset = offset; + + prev_split = true; + } + + if (end > req_end) { + next.va.addr = req_end; + next.va.range = end - req_end; + next.gem.obj = obj; + next.gem.offset = offset + (req_end - addr); + + next_split = true; + } + + if (prev_split || next_split) { + struct drm_gpuva_op_unmap unmap = { .va = va }; + + ret = op_remap_cb(ops, priv, + prev_split ? &prev : NULL, + next_split ? &next : NULL, + &unmap); + if (ret) + return ret; + } else { + ret = op_unmap_cb(ops, priv, va, false); + if (ret) + return ret; + } + } + + return 0; +} + +/** + * drm_gpuvm_sm_map() - creates the &drm_gpuva_op split/merge steps + * @gpuvm: the &drm_gpuvm representing the GPU VA space + * @req_addr: the start address of the new mapping + * @req_range: the range of the new mapping + * @req_obj: the &drm_gem_object to map + * @req_offset: the offset within the &drm_gem_object + * @priv: pointer to a driver private data structure + * + * This function iterates the given range of the GPU VA space. It utilizes the + * &drm_gpuvm_ops to call back into the driver providing the split and merge + * steps. + * + * Drivers may use these callbacks to update the GPU VA space right away within + * the callback. In case the driver decides to copy and store the operations for + * later processing neither this function nor &drm_gpuvm_sm_unmap is allowed to + * be called before the &drm_gpuvm's view of the GPU VA space was + * updated with the previous set of operations. To update the + * &drm_gpuvm's view of the GPU VA space drm_gpuva_insert(), + * drm_gpuva_destroy_locked() and/or drm_gpuva_destroy_unlocked() should be + * used. + * + * A sequence of callbacks can contain map, unmap and remap operations, but + * the sequence of callbacks might also be empty if no operation is required, + * e.g. if the requested mapping already exists in the exact same way. + * + * There can be an arbitrary amount of unmap operations, a maximum of two remap + * operations and a single map operation. The latter one represents the original + * map operation requested by the caller. + * + * Returns: 0 on success or a negative error code + */ +int +drm_gpuvm_sm_map(struct drm_gpuvm *gpuvm, void *priv, + u64 req_addr, u64 req_range, + struct drm_gem_object *req_obj, u64 req_offset) +{ + const struct drm_gpuvm_ops *ops = gpuvm->ops; + + if (unlikely(!(ops && ops->sm_step_map && + ops->sm_step_remap && + ops->sm_step_unmap))) + return -EINVAL; + + return __drm_gpuvm_sm_map(gpuvm, ops, priv, + req_addr, req_range, + req_obj, req_offset); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_sm_map); + +/** + * drm_gpuvm_sm_unmap() - creates the &drm_gpuva_ops to split on unmap + * @gpuvm: the &drm_gpuvm representing the GPU VA space + * @priv: pointer to a driver private data structure + * @req_addr: the start address of the range to unmap + * @req_range: the range of the mappings to unmap + * + * This function iterates the given range of the GPU VA space. It utilizes the + * &drm_gpuvm_ops to call back into the driver providing the operations to + * unmap and, if required, split existent mappings. + * + * Drivers may use these callbacks to update the GPU VA space right away within + * the callback. In case the driver decides to copy and store the operations for + * later processing neither this function nor &drm_gpuvm_sm_map is allowed to be + * called before the &drm_gpuvm's view of the GPU VA space was updated + * with the previous set of operations. To update the &drm_gpuvm's view + * of the GPU VA space drm_gpuva_insert(), drm_gpuva_destroy_locked() and/or + * drm_gpuva_destroy_unlocked() should be used. + * + * A sequence of callbacks can contain unmap and remap operations, depending on + * whether there are actual overlapping mappings to split. + * + * There can be an arbitrary amount of unmap operations and a maximum of two + * remap operations. + * + * Returns: 0 on success or a negative error code + */ +int +drm_gpuvm_sm_unmap(struct drm_gpuvm *gpuvm, void *priv, + u64 req_addr, u64 req_range) +{ + const struct drm_gpuvm_ops *ops = gpuvm->ops; + + if (unlikely(!(ops && ops->sm_step_remap && + ops->sm_step_unmap))) + return -EINVAL; + + return __drm_gpuvm_sm_unmap(gpuvm, ops, priv, + req_addr, req_range); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_sm_unmap); + +static struct drm_gpuva_op * +gpuva_op_alloc(struct drm_gpuvm *gpuvm) +{ + const struct drm_gpuvm_ops *fn = gpuvm->ops; + struct drm_gpuva_op *op; + + if (fn && fn->op_alloc) + op = fn->op_alloc(); + else + op = kzalloc(sizeof(*op), GFP_KERNEL); + + if (unlikely(!op)) + return NULL; + + return op; +} + +static void +gpuva_op_free(struct drm_gpuvm *gpuvm, + struct drm_gpuva_op *op) +{ + const struct drm_gpuvm_ops *fn = gpuvm->ops; + + if (fn && fn->op_free) + fn->op_free(op); + else + kfree(op); +} + +static int +drm_gpuva_sm_step(struct drm_gpuva_op *__op, + void *priv) +{ + struct { + struct drm_gpuvm *vm; + struct drm_gpuva_ops *ops; + } *args = priv; + struct drm_gpuvm *gpuvm = args->vm; + struct drm_gpuva_ops *ops = args->ops; + struct drm_gpuva_op *op; + + op = gpuva_op_alloc(gpuvm); + if (unlikely(!op)) + goto err; + + memcpy(op, __op, sizeof(*op)); + + if (op->op == DRM_GPUVA_OP_REMAP) { + struct drm_gpuva_op_remap *__r = &__op->remap; + struct drm_gpuva_op_remap *r = &op->remap; + + r->unmap = kmemdup(__r->unmap, sizeof(*r->unmap), + GFP_KERNEL); + if (unlikely(!r->unmap)) + goto err_free_op; + + if (__r->prev) { + r->prev = kmemdup(__r->prev, sizeof(*r->prev), + GFP_KERNEL); + if (unlikely(!r->prev)) + goto err_free_unmap; + } + + if (__r->next) { + r->next = kmemdup(__r->next, sizeof(*r->next), + GFP_KERNEL); + if (unlikely(!r->next)) + goto err_free_prev; + } + } + + list_add_tail(&op->entry, &ops->list); + + return 0; + +err_free_unmap: + kfree(op->remap.unmap); +err_free_prev: + kfree(op->remap.prev); +err_free_op: + gpuva_op_free(gpuvm, op); +err: + return -ENOMEM; +} + +static const struct drm_gpuvm_ops gpuvm_list_ops = { + .sm_step_map = drm_gpuva_sm_step, + .sm_step_remap = drm_gpuva_sm_step, + .sm_step_unmap = drm_gpuva_sm_step, +}; + +/** + * drm_gpuvm_sm_map_ops_create() - creates the &drm_gpuva_ops to split and merge + * @gpuvm: the &drm_gpuvm representing the GPU VA space + * @req_addr: the start address of the new mapping + * @req_range: the range of the new mapping + * @req_obj: the &drm_gem_object to map + * @req_offset: the offset within the &drm_gem_object + * + * This function creates a list of operations to perform splitting and merging + * of existent mapping(s) with the newly requested one. + * + * The list can be iterated with &drm_gpuva_for_each_op and must be processed + * in the given order. It can contain map, unmap and remap operations, but it + * also can be empty if no operation is required, e.g. if the requested mapping + * already exists is the exact same way. + * + * There can be an arbitrary amount of unmap operations, a maximum of two remap + * operations and a single map operation. The latter one represents the original + * map operation requested by the caller. + * + * Note that before calling this function again with another mapping request it + * is necessary to update the &drm_gpuvm's view of the GPU VA space. The + * previously obtained operations must be either processed or abandoned. To + * update the &drm_gpuvm's view of the GPU VA space drm_gpuva_insert(), + * drm_gpuva_destroy_locked() and/or drm_gpuva_destroy_unlocked() should be + * used. + * + * After the caller finished processing the returned &drm_gpuva_ops, they must + * be freed with &drm_gpuva_ops_free. + * + * Returns: a pointer to the &drm_gpuva_ops on success, an ERR_PTR on failure + */ +struct drm_gpuva_ops * +drm_gpuvm_sm_map_ops_create(struct drm_gpuvm *gpuvm, + u64 req_addr, u64 req_range, + struct drm_gem_object *req_obj, u64 req_offset) +{ + struct drm_gpuva_ops *ops; + struct { + struct drm_gpuvm *vm; + struct drm_gpuva_ops *ops; + } args; + int ret; + + ops = kzalloc(sizeof(*ops), GFP_KERNEL); + if (unlikely(!ops)) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&ops->list); + + args.vm = gpuvm; + args.ops = ops; + + ret = __drm_gpuvm_sm_map(gpuvm, &gpuvm_list_ops, &args, + req_addr, req_range, + req_obj, req_offset); + if (ret) + goto err_free_ops; + + return ops; + +err_free_ops: + drm_gpuva_ops_free(gpuvm, ops); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_sm_map_ops_create); + +/** + * drm_gpuvm_sm_unmap_ops_create() - creates the &drm_gpuva_ops to split on + * unmap + * @gpuvm: the &drm_gpuvm representing the GPU VA space + * @req_addr: the start address of the range to unmap + * @req_range: the range of the mappings to unmap + * + * This function creates a list of operations to perform unmapping and, if + * required, splitting of the mappings overlapping the unmap range. + * + * The list can be iterated with &drm_gpuva_for_each_op and must be processed + * in the given order. It can contain unmap and remap operations, depending on + * whether there are actual overlapping mappings to split. + * + * There can be an arbitrary amount of unmap operations and a maximum of two + * remap operations. + * + * Note that before calling this function again with another range to unmap it + * is necessary to update the &drm_gpuvm's view of the GPU VA space. The + * previously obtained operations must be processed or abandoned. To update the + * &drm_gpuvm's view of the GPU VA space drm_gpuva_insert(), + * drm_gpuva_destroy_locked() and/or drm_gpuva_destroy_unlocked() should be + * used. + * + * After the caller finished processing the returned &drm_gpuva_ops, they must + * be freed with &drm_gpuva_ops_free. + * + * Returns: a pointer to the &drm_gpuva_ops on success, an ERR_PTR on failure + */ +struct drm_gpuva_ops * +drm_gpuvm_sm_unmap_ops_create(struct drm_gpuvm *gpuvm, + u64 req_addr, u64 req_range) +{ + struct drm_gpuva_ops *ops; + struct { + struct drm_gpuvm *vm; + struct drm_gpuva_ops *ops; + } args; + int ret; + + ops = kzalloc(sizeof(*ops), GFP_KERNEL); + if (unlikely(!ops)) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&ops->list); + + args.vm = gpuvm; + args.ops = ops; + + ret = __drm_gpuvm_sm_unmap(gpuvm, &gpuvm_list_ops, &args, + req_addr, req_range); + if (ret) + goto err_free_ops; + + return ops; + +err_free_ops: + drm_gpuva_ops_free(gpuvm, ops); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_sm_unmap_ops_create); + +/** + * drm_gpuvm_prefetch_ops_create() - creates the &drm_gpuva_ops to prefetch + * @gpuvm: the &drm_gpuvm representing the GPU VA space + * @addr: the start address of the range to prefetch + * @range: the range of the mappings to prefetch + * + * This function creates a list of operations to perform prefetching. + * + * The list can be iterated with &drm_gpuva_for_each_op and must be processed + * in the given order. It can contain prefetch operations. + * + * There can be an arbitrary amount of prefetch operations. + * + * After the caller finished processing the returned &drm_gpuva_ops, they must + * be freed with &drm_gpuva_ops_free. + * + * Returns: a pointer to the &drm_gpuva_ops on success, an ERR_PTR on failure + */ +struct drm_gpuva_ops * +drm_gpuvm_prefetch_ops_create(struct drm_gpuvm *gpuvm, + u64 addr, u64 range) +{ + struct drm_gpuva_ops *ops; + struct drm_gpuva_op *op; + struct drm_gpuva *va; + u64 end = addr + range; + int ret; + + ops = kzalloc(sizeof(*ops), GFP_KERNEL); + if (!ops) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&ops->list); + + drm_gpuvm_for_each_va_range(va, gpuvm, addr, end) { + op = gpuva_op_alloc(gpuvm); + if (!op) { + ret = -ENOMEM; + goto err_free_ops; + } + + op->op = DRM_GPUVA_OP_PREFETCH; + op->prefetch.va = va; + list_add_tail(&op->entry, &ops->list); + } + + return ops; + +err_free_ops: + drm_gpuva_ops_free(gpuvm, ops); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_prefetch_ops_create); + +/** + * drm_gpuvm_bo_unmap_ops_create() - creates the &drm_gpuva_ops to unmap a GEM + * @vm_bo: the &drm_gpuvm_bo abstraction + * + * This function creates a list of operations to perform unmapping for every + * GPUVA attached to a GEM. + * + * The list can be iterated with &drm_gpuva_for_each_op and consists out of an + * arbitrary amount of unmap operations. + * + * After the caller finished processing the returned &drm_gpuva_ops, they must + * be freed with &drm_gpuva_ops_free. + * + * It is the callers responsibility to protect the GEMs GPUVA list against + * concurrent access using the GEMs dma_resv lock. + * + * Returns: a pointer to the &drm_gpuva_ops on success, an ERR_PTR on failure + */ +struct drm_gpuva_ops * +drm_gpuvm_bo_unmap_ops_create(struct drm_gpuvm_bo *vm_bo) +{ + struct drm_gpuva_ops *ops; + struct drm_gpuva_op *op; + struct drm_gpuva *va; + int ret; + + drm_gem_gpuva_assert_lock_held(vm_bo->obj); + + ops = kzalloc(sizeof(*ops), GFP_KERNEL); + if (!ops) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&ops->list); + + drm_gpuvm_bo_for_each_va(va, vm_bo) { + op = gpuva_op_alloc(vm_bo->vm); + if (!op) { + ret = -ENOMEM; + goto err_free_ops; + } + + op->op = DRM_GPUVA_OP_UNMAP; + op->unmap.va = va; + list_add_tail(&op->entry, &ops->list); + } + + return ops; + +err_free_ops: + drm_gpuva_ops_free(vm_bo->vm, ops); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_unmap_ops_create); + +/** + * drm_gpuva_ops_free() - free the given &drm_gpuva_ops + * @gpuvm: the &drm_gpuvm the ops were created for + * @ops: the &drm_gpuva_ops to free + * + * Frees the given &drm_gpuva_ops structure including all the ops associated + * with it. + */ +void +drm_gpuva_ops_free(struct drm_gpuvm *gpuvm, + struct drm_gpuva_ops *ops) +{ + struct drm_gpuva_op *op, *next; + + drm_gpuva_for_each_op_safe(op, next, ops) { + list_del(&op->entry); + + if (op->op == DRM_GPUVA_OP_REMAP) { + kfree(op->remap.prev); + kfree(op->remap.next); + kfree(op->remap.unmap); + } + + gpuva_op_free(gpuvm, op); + } + + kfree(ops); +} +EXPORT_SYMBOL_GPL(drm_gpuva_ops_free); + +MODULE_DESCRIPTION("DRM GPUVM"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 6172f786012b4..4f6895096c704 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -245,8 +245,7 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_ req->value = 1; return 0; case DRM_CAP_PRIME: - req->value |= dev->driver->prime_fd_to_handle ? DRM_PRIME_CAP_IMPORT : 0; - req->value |= dev->driver->prime_handle_to_fd ? DRM_PRIME_CAP_EXPORT : 0; + req->value = DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT; return 0; case DRM_CAP_SYNCOBJ: req->value = drm_core_check_feature(dev, DRIVER_SYNCOBJ); @@ -680,9 +679,9 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb_ioctl, 0), DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, 0), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, 0), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, 0), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, 0), DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER), diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index 68a6d4b0ead75..45050fc989c6d 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -51,15 +51,10 @@ MODULE_IMPORT_NS(DMA_BUF); * between applications, they can't be guessed like the globally unique GEM * names. * - * Drivers that support the PRIME API implement the - * &drm_driver.prime_handle_to_fd and &drm_driver.prime_fd_to_handle operations. - * GEM based drivers must use drm_gem_prime_handle_to_fd() and - * drm_gem_prime_fd_to_handle() to implement these. For GEM based drivers the - * actual driver interfaces is provided through the &drm_gem_object_funcs.export - * and &drm_driver.gem_prime_import hooks. - * - * &dma_buf_ops implementations for GEM drivers are all individually exported - * for drivers which need to overwrite or reimplement some of them. + * Drivers that support the PRIME API implement the drm_gem_object_funcs.export + * and &drm_driver.gem_prime_import hooks. &dma_buf_ops implementations for + * drivers are all individually exported for drivers which need to overwrite + * or reimplement some of them. * * Reference Counting for GEM Drivers * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -372,11 +367,12 @@ int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data, { struct drm_prime_handle *args = data; - if (!dev->driver->prime_fd_to_handle) - return -ENOSYS; + if (dev->driver->prime_fd_to_handle) { + return dev->driver->prime_fd_to_handle(dev, file_priv, args->fd, + &args->handle); + } - return dev->driver->prime_fd_to_handle(dev, file_priv, - args->fd, &args->handle); + return drm_gem_prime_fd_to_handle(dev, file_priv, args->fd, &args->handle); } static struct dma_buf *export_and_register_object(struct drm_device *dev, @@ -518,15 +514,17 @@ int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data, { struct drm_prime_handle *args = data; - if (!dev->driver->prime_handle_to_fd) - return -ENOSYS; - /* check flags are valid */ if (args->flags & ~(DRM_CLOEXEC | DRM_RDWR)) return -EINVAL; - return dev->driver->prime_handle_to_fd(dev, file_priv, - args->handle, args->flags, &args->fd); + if (dev->driver->prime_handle_to_fd) { + return dev->driver->prime_handle_to_fd(dev, file_priv, + args->handle, args->flags, + &args->fd); + } + return drm_gem_prime_handle_to_fd(dev, file_priv, args->handle, + args->flags, &args->fd); } /** diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index f29952a55c05d..d0b79cf785c74 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -474,8 +474,6 @@ static const struct drm_driver etnaviv_drm_driver = { .driver_features = DRIVER_GEM | DRIVER_RENDER, .open = etnaviv_open, .postclose = etnaviv_postclose, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import_sg_table = etnaviv_gem_prime_import_sg_table, .gem_prime_mmap = drm_gem_prime_mmap, #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c index 1ac916b248917..ceaebf793909b 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c @@ -531,7 +531,7 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data, ret = drm_sched_job_init(&submit->sched_job, &ctx->sched_entity[args->pipe], - submit->ctx); + 1, submit->ctx); if (ret) goto err_submit_put; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index f667e7906d1f4..b08709715abd1 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1870,7 +1870,7 @@ static int etnaviv_gpu_rpm_suspend(struct device *dev) u32 idle, mask; /* If there are any jobs in the HW queue, we're not idle */ - if (atomic_read(&gpu->sched.hw_rq_count)) + if (atomic_read(&gpu->sched.credit_count)) return -EBUSY; /* Check whether the hardware (except FE and MC) is idle */ diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c b/drivers/gpu/drm/etnaviv/etnaviv_sched.c index 72e2553fbc984..752fc5a21cb38 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c @@ -71,12 +71,12 @@ static enum drm_gpu_sched_stat etnaviv_sched_timedout_job(struct drm_sched_job drm_sched_resubmit_jobs(&gpu->sched); - drm_sched_start(&gpu->sched, true); + drm_sched_start(&gpu->sched); return DRM_GPU_SCHED_STAT_NOMINAL; out_no_timeout: /* restart scheduler after GPU is usable again */ - drm_sched_start(&gpu->sched, true); + drm_sched_start(&gpu->sched); return DRM_GPU_SCHED_STAT_NOMINAL; } @@ -133,7 +133,8 @@ int etnaviv_sched_init(struct etnaviv_gpu *gpu) { int ret; - ret = drm_sched_init(&gpu->sched, &etnaviv_sched_ops, + ret = drm_sched_init(&gpu->sched, &etnaviv_sched_ops, NULL, + DRM_SCHED_PRIORITY_COUNT, etnaviv_hw_jobs_limit, etnaviv_job_hang_limit, msecs_to_jiffies(500), NULL, NULL, dev_name(gpu->dev), gpu->dev); diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index 4095b0d3ac2e3..64668e425f87b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -111,8 +111,6 @@ static const struct drm_driver exynos_drm_driver = { .lastclose = drm_fb_helper_lastclose, .postclose = exynos_drm_postclose, .dumb_create = exynos_drm_gem_dumb_create, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = exynos_drm_gem_prime_import, .gem_prime_import_sg_table = exynos_drm_gem_prime_import_sg_table, .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index be0ebed2a360f..449f5b9e6044b 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -1921,8 +1921,6 @@ static const struct drm_driver i915_drm_driver = { .lastclose = i915_driver_lastclose, .postclose = i915_driver_postclose, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = i915_gem_prime_import, .dumb_create = i915_gem_dumb_create, diff --git a/drivers/gpu/drm/lima/lima_device.c b/drivers/gpu/drm/lima/lima_device.c index 02cef0cea6572..0bf7105c8748b 100644 --- a/drivers/gpu/drm/lima/lima_device.c +++ b/drivers/gpu/drm/lima/lima_device.c @@ -514,7 +514,7 @@ int lima_device_suspend(struct device *dev) /* check any task running */ for (i = 0; i < lima_pipe_num; i++) { - if (atomic_read(&ldev->pipe[i].base.hw_rq_count)) + if (atomic_read(&ldev->pipe[i].base.credit_count)) return -EBUSY; } diff --git a/drivers/gpu/drm/lima/lima_drv.c b/drivers/gpu/drm/lima/lima_drv.c index 39cab4a55f572..51efdc107314f 100644 --- a/drivers/gpu/drm/lima/lima_drv.c +++ b/drivers/gpu/drm/lima/lima_drv.c @@ -276,9 +276,7 @@ static const struct drm_driver lima_drm_driver = { .patchlevel = 0, .gem_create_object = lima_gem_create_object, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import_sg_table = drm_gem_shmem_prime_import_sg_table, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .gem_prime_mmap = drm_gem_prime_mmap, }; diff --git a/drivers/gpu/drm/lima/lima_gem.c b/drivers/gpu/drm/lima/lima_gem.c index d72c5bf4e5ac1..900499ea31894 100644 --- a/drivers/gpu/drm/lima/lima_gem.c +++ b/drivers/gpu/drm/lima/lima_gem.c @@ -34,7 +34,7 @@ int lima_heap_alloc(struct lima_bo *bo, struct lima_vm *vm) new_size = min(new_size, bo->base.base.size); - mutex_lock(&bo->base.pages_lock); + dma_resv_lock(bo->base.base.resv, NULL); if (bo->base.pages) { pages = bo->base.pages; @@ -42,7 +42,7 @@ int lima_heap_alloc(struct lima_bo *bo, struct lima_vm *vm) pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT, sizeof(*pages), GFP_KERNEL | __GFP_ZERO); if (!pages) { - mutex_unlock(&bo->base.pages_lock); + dma_resv_unlock(bo->base.base.resv); return -ENOMEM; } @@ -56,13 +56,13 @@ int lima_heap_alloc(struct lima_bo *bo, struct lima_vm *vm) struct page *page = shmem_read_mapping_page(mapping, i); if (IS_ERR(page)) { - mutex_unlock(&bo->base.pages_lock); + dma_resv_unlock(bo->base.base.resv); return PTR_ERR(page); } pages[i] = page; } - mutex_unlock(&bo->base.pages_lock); + dma_resv_unlock(bo->base.base.resv); ret = sg_alloc_table_from_pages(&sgt, pages, i, 0, new_size, GFP_KERNEL); diff --git a/drivers/gpu/drm/lima/lima_sched.c b/drivers/gpu/drm/lima/lima_sched.c index e82931712d8a2..8247abee957e3 100644 --- a/drivers/gpu/drm/lima/lima_sched.c +++ b/drivers/gpu/drm/lima/lima_sched.c @@ -123,7 +123,7 @@ int lima_sched_task_init(struct lima_sched_task *task, for (i = 0; i < num_bos; i++) drm_gem_object_get(&bos[i]->base.base); - err = drm_sched_job_init(&task->base, &context->base, vm); + err = drm_sched_job_init(&task->base, &context->base, 1, vm); if (err) { kfree(task->bos); return err; @@ -371,7 +371,7 @@ static void lima_sched_build_error_task_list(struct lima_sched_task *task) } else { buffer_chunk->size = lima_bo_size(bo); - ret = drm_gem_shmem_vmap(&bo->base, &map); + ret = drm_gem_vmap_unlocked(&bo->base.base, &map); if (ret) { kvfree(et); goto out; @@ -379,7 +379,7 @@ static void lima_sched_build_error_task_list(struct lima_sched_task *task) memcpy(buffer_chunk + 1, map.vaddr, buffer_chunk->size); - drm_gem_shmem_vunmap(&bo->base, &map); + drm_gem_vunmap_unlocked(&bo->base.base, &map); } buffer_chunk = (void *)(buffer_chunk + 1) + buffer_chunk->size; @@ -430,7 +430,7 @@ static enum drm_gpu_sched_stat lima_sched_timedout_job(struct drm_sched_job *job lima_pm_idle(ldev); drm_sched_resubmit_jobs(&pipe->base); - drm_sched_start(&pipe->base, true); + drm_sched_start(&pipe->base); return DRM_GPU_SCHED_STAT_NOMINAL; } @@ -488,7 +488,9 @@ int lima_sched_pipe_init(struct lima_sched_pipe *pipe, const char *name) INIT_WORK(&pipe->recover_work, lima_sched_recover_work); - return drm_sched_init(&pipe->base, &lima_sched_ops, 1, + return drm_sched_init(&pipe->base, &lima_sched_ops, NULL, + DRM_SCHED_PRIORITY_COUNT, + 1, lima_job_hang_limit, msecs_to_jiffies(timeout), NULL, NULL, name, pipe->ldev->dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 25639fbfd374a..c7fa26f45780d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -472,8 +472,6 @@ static const struct drm_driver mtk_drm_driver = { .dumb_create = mtk_drm_gem_dumb_create, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = mtk_drm_gem_prime_import, .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index ed1e0c650bb1a..41e901cdf0762 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -667,7 +667,8 @@ static void suspend_scheduler(struct msm_gpu *gpu) */ for (i = 0; i < gpu->nr_rings; i++) { struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; - kthread_park(sched->thread); + + drm_sched_wqueue_stop(sched); } } @@ -677,7 +678,8 @@ static void resume_scheduler(struct msm_gpu *gpu) for (i = 0; i < gpu->nr_rings; i++) { struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; - kthread_unpark(sched->thread); + + drm_sched_wqueue_start(sched); } } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index f982a827be7ca..73539e6bea94a 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -1083,8 +1083,6 @@ static const struct drm_driver msm_driver = { .lastclose = drm_fb_helper_lastclose, .dumb_create = msm_gem_dumb_create, .dumb_map_offset = msm_gem_dumb_map_offset, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, .gem_prime_mmap = msm_gem_prime_mmap, #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index c12a6ac2d3840..3a8b9098b39ae 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -41,7 +41,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev, if (!submit) return ERR_PTR(-ENOMEM); - ret = drm_sched_job_init(&submit->base, queue->entity, queue); + ret = drm_sched_job_init(&submit->base, queue->entity, 1, queue); if (ret) { kfree(submit); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index b39cd332751dc..175d7fa7954aa 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -337,7 +337,7 @@ struct msm_gpu_perfcntr { * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some * cases, so we don't use it (no need for kernel generated jobs). */ -#define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_HIGH - DRM_SCHED_PRIORITY_MIN) +#define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_LOW - DRM_SCHED_PRIORITY_HIGH) /** * struct msm_file_private - per-drm_file context diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 57a8e9564540e..546bd6388b2eb 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -95,9 +95,10 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, /* currently managing hangcheck ourselves: */ sched_timeout = MAX_SCHEDULE_TIMEOUT; - ret = drm_sched_init(&ring->sched, &msm_sched_ops, - num_hw_submissions, 0, sched_timeout, - NULL, NULL, to_msm_bo(ring->bo)->name, gpu->dev->dev); + ret = drm_sched_init(&ring->sched, &msm_sched_ops, NULL, + DRM_SCHED_PRIORITY_COUNT, + num_hw_submissions, 0, sched_timeout, + NULL, NULL, to_msm_bo(ring->bo)->name, gpu->dev->dev); if (ret) { goto fail; } diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 28062d682f436..3b01e86e71a12 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -1260,8 +1260,6 @@ driver_stub = { .num_ioctls = ARRAY_SIZE(nouveau_ioctls), .fops = &nouveau_driver_fops, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 5b6d1668f405c..99c4c37bc26b6 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -693,8 +693,6 @@ static const struct drm_driver omap_drm_driver = { #ifdef CONFIG_DEBUG_FS .debugfs_init = omap_debugfs_init, #endif - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = omap_gem_prime_import, .dumb_create = omap_gem_dumb_create, .dumb_map_offset = omap_gem_dumb_map_offset, diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 3cd592dc91c76..54c54cf629e3f 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -202,6 +202,16 @@ config DRM_PANEL_INNOLUX_P079ZCA 24 bit RGB per pixel. It provides a MIPI DSI interface to the host and has a built-in LED backlight. +config DRM_PANEL_JADARD_JD9365DA_H3 + tristate "Jadard JD9365DA-H3 WXGA DSI panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Jadard JD9365DA-H3 + WXGA MIPI DSI panel. The panel support TFT dot matrix LCD with + 800RGBx1280 dots at maximum. + config DRM_PANEL_JDI_LT070ME05000 tristate "JDI LT070ME05000 WUXGA DSI panel" depends on OF @@ -424,6 +434,15 @@ config DRM_PANEL_PANASONIC_VVX10F034N00 WUXGA (1920x1200) Novatek NT1397-based DSI panel as found in some Xperia Z2 tablets +config DRM_PANEL_RADXA_DISPLAY_8HD + tristate "Radxa Display 8HD panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Radxa Display 8HD panel. + The panel support TFT dot matrix LCD with 800RGBx1280 dots at maximum. + config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN tristate "Raspberry Pi 7-inch touchscreen panel" depends on DRM_MIPI_DSI @@ -432,6 +451,14 @@ config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN Pi 7" Touchscreen. To compile this driver as a module, choose M here. +config DRM_PANEL_RASPITS_TC358762 + tristate "Raspits Pi 7-inch touchscreen panel" + depends on DRM_MIPI_DSI + help + Say Y here if you want to enable support for the Raspits + Pi 7" Touchscreen. To compile this driver as a module, + choose M here. + config DRM_PANEL_RAYDIUM_RM67191 tristate "Raydium RM67191 FHD 1080x1920 DSI video mode panel" depends on OF @@ -732,4 +759,15 @@ config DRM_PANEL_XINPENG_XPP055C272 Say Y here if you want to enable support for the Xinpeng XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI system interfaces. + +config DRM_PANEL_INNOLUX_AFJ101_BA2131 + tristate "Innolux AFJ101 BA2131 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Innolux BA2131 + TFT-LCD modules. The panel has a 800x1280 resolution and uses + 24 bit RGB per pixel. It provides a MIPI DSI interface to + the host and has a built-in LED backlight. endmenu diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 98e0a86a2004e..5daa24e795f10 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -16,8 +16,10 @@ obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o +obj-$(CONFIG_DRM_PANEL_INNOLUX_AFJ101_BA2131) += panel-innolux-afj101-ba2131.o obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o +obj-$(CONFIG_DRM_PANEL_JADARD_JD9365DA_H3) += panel-jadard-jd9365da-h3.o obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o @@ -40,7 +42,9 @@ obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o obj-$(CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS) += panel-osd-osd101t2587-53ts.o obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o +obj-$(CONFIG_DRM_PANEL_RADXA_DISPLAY_8HD) += panel-radxa-display-8hd.o obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o +obj-$(CONFIG_DRM_PANEL_RASPITS_TC358762) += panel-raspits-tc358762.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o diff --git a/drivers/gpu/drm/panel/panel-innolux-afj101-ba2131.c b/drivers/gpu/drm/panel/panel-innolux-afj101-ba2131.c new file mode 100644 index 0000000000000..4464741b1e2ef --- /dev/null +++ b/drivers/gpu/drm/panel/panel-innolux-afj101-ba2131.c @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2020 Kali Prasad + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include