From f324aa8f9c73060e8984624b86d75b3477dc06b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Kamil=20Trzci=C5=84ski?= <ayufan@ayufan.eu>
Date: Mon, 27 May 2019 10:25:11 +0200
Subject: [PATCH] ayufan: rock64: add board_init_sdmmc_pwr_en to configure
 iomux in SPL mode

---
 arch/arm/mach-rockchip/rk3328-board-spl.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c
index 88cda94b1e2..0c865c4ba10 100644
--- a/arch/arm/mach-rockchip/rk3328-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3328-board-spl.c
@@ -18,12 +18,34 @@
 #include <asm/arch/periph.h>
 #include <asm/arch/timer.h>
 
+#define GRF_BASE		0xFF100000
+
 DECLARE_GLOBAL_DATA_PTR;
 
 void board_debug_uart_init(void)
 {
 }
 
+void board_init_sdmmc_pwr_en(void)
+{
+	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+
+	printf("board_init_sdmmc_pwr_en\n");
+
+	rk_clrsetreg(&grf->com_iomux,
+		IOMUX_SEL_SDMMC_MASK,
+		IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
+
+	rk_clrsetreg(&grf->gpio0d_iomux,
+		GPIO0D6_SEL_MASK,
+		GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
+
+	rk_clrsetreg(&grf->gpio1a_iomux,
+		GPIO1A0_SEL_MASK,
+		GPIO1A0_CARD_DATA_CLK_CMD_DETN
+		<< GPIO1A0_SEL_SHIFT);
+}
+
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
@@ -36,6 +58,7 @@ void board_init_f(ulong dummy)
 	}
 
 	preloader_console_init();
+	board_init_sdmmc_pwr_en();
 
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 	if (ret) {