diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index af9d2001422..7805358701c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-minnie.dtb \ rk3328-evb.dtb \ rk3328-rock64.dtb \ + rk3328-roc-cc.dtb \ rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts new file mode 100644 index 00000000000..b9b8fbc5ec7 --- /dev/null +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -0,0 +1,246 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "rk3328.dtsi" +#include "rk3328-sdram-ddr3-666.dtsi" + +/ { + model = "Firefly ROC-RK3328-CC"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + + chosen { + stdout-path = &uart2; + }; + + vcc3v3_sdmmc: sdmmc-pwren { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_otg: vcc5v0-otg-drv { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc5v0_otg"; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host_xhci: vcc5v0-host-xhci-drv { + status = "disabled"; //usb host xhci and usb otg use the same gpio to enable power + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc5v0_host_xhci"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + }; +}; + +&saradc { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + status = "okay"; +}; + +&emmc { + u-boot,dm-pre-reloc; + bus-width = <8>; + cap-mmc-highspeed; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb20_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb_host0_xhci { + //vbus-supply = <&vcc5v0_host_xhci>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + maximum-speed = "high-speed"; +}; + +&i2c1 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + + pwrkey { + status = "okay"; + }; + + led1 { + label = "standby"; + }; + + led2 { + label = "power"; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_d0 */ + }; + }; +}; + diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index cefd6f5dba0..2cf829e7d08 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -22,6 +22,17 @@ config TARGET_ROCK64_RK3328 USB 3.0 and many others peripheral devices interface for makers to integrate with sensors and devices +config TARGET_ROC_RK3328_CC + bool "ROC-RK3328-CC board, " + select BOARD_LATE_INIT + help + ROC-RK3328-CC is a Raspberry Pi-2 sized 4K60P HDR Media Board Computer + powered by Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor + and support up to 4GB 2133MHz DDR4 memory. + It provides eMMC module socket, MicroSD Card slot, Pi-2 Bus, Pi-P5+ Bus, + USB 3.0 and many others peripheral devices interface for makers + to integrate with sensors and devices + endchoice config SYS_SOC @@ -32,5 +43,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3328/Kconfig" source "board/rockchip/rock64_rk3328/Kconfig" +source "board/rockchip/roc_rk3328_cc/Kconfig" endif diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 76dbdc87154..19f7c17d47e 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; size_t rockchip_sdram_size(phys_addr_t reg) { - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4, dbw, bg; size_t chipsize_mb = 0; size_t size_mb = 0; u32 ch; @@ -37,16 +37,20 @@ size_t rockchip_sdram_size(phys_addr_t reg) SYS_REG_BW_MASK)); row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; + dbw = sys_reg >> SYS_REG_DBW_SHIFT(ch) & SYS_REG_DBW_MASK; + /* only used by DDR4 */ + bg = (dbw == 1) ? 1 : 2; - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + chipsize_mb = (1 << (cs0_row + col + bg + bk + bw - 20)); if (rank > 1) chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); if (row_3_4) chipsize_mb = chipsize_mb * 3 / 4; size_mb += chipsize_mb; - debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", - rank, col, bk, cs0_row, bw, row_3_4); + debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d dbw %d\n", + rank, col, bk, cs0_row, bw, row_3_4, dbw); + } return (size_t)size_mb << 20; diff --git a/board/rockchip/roc_rk3328_cc/Kconfig b/board/rockchip/roc_rk3328_cc/Kconfig new file mode 100644 index 00000000000..074894a9116 --- /dev/null +++ b/board/rockchip/roc_rk3328_cc/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROC_RK3328_CC + +config SYS_BOARD + default "roc_rk3328_cc" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "roc_rk3328_cc" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/roc_rk3328_cc/Makefile b/board/rockchip/roc_rk3328_cc/Makefile new file mode 100644 index 00000000000..79290147ee7 --- /dev/null +++ b/board/rockchip/roc_rk3328_cc/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2018 FIREFLY +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += roc-rk3328-cc.o diff --git a/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c b/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c new file mode 100644 index 00000000000..51ccdb07d97 --- /dev/null +++ b/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2018 FIREFLY + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + diff --git a/configs/roc-rk3328-cc_defconfig b/configs/roc-rk3328-cc_defconfig new file mode 100644 index 00000000000..0fdcfcbb7ea --- /dev/null +++ b/configs/roc-rk3328-cc_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_ROC_RK3328_CC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc" +CONFIG_SMBIOS_PRODUCT_NAME="roc_rk3328_roc" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="board/rockchip/evb_rk3328/mk_fit_atf.sh" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF_SUPPORT=y +CONFIG_TPL_BOOTROM_SUPPORT=y +CONFIG_TPL_DRIVERS_MISC_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_ETHSW=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MTDPARTS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_LED=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Rockchip" +CONFIG_G_DNL_VENDOR_NUM=0x2207 +CONFIG_G_DNL_PRODUCT_NUM=0x330a +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_SMBIOS_MANUFACTURER="firefly" diff --git a/include/configs/roc_rk3328_cc.h b/include/configs/roc_rk3328_cc.h new file mode 100644 index 00000000000..fc9c84e2e02 --- /dev/null +++ b/include/configs/roc_rk3328_cc.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2018 FIREFLY + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ROC_RK3328_CC_H +#define __ROC_RK3328_CC_H + +#include + +#define CONFIG_SYS_MMC_ENV_DEV 1 + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif