From 762c4957489f5c934114908a359f9fc7a262b6c3 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Fri, 11 Aug 2023 19:13:59 +0100 Subject: [PATCH] riscv_debug: handle CH32V3x quirk The chip replies ok when probing the breakpoints but the reply is empty Co-authored-by: mean --- src/target/riscv_debug.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/target/riscv_debug.c b/src/target/riscv_debug.c index 3bfd3b52541..f002b4946ac 100644 --- a/src/target/riscv_debug.c +++ b/src/target/riscv_debug.c @@ -666,7 +666,8 @@ static void riscv_hart_discover_triggers(riscv_hart_s *const hart) riscv_csr_write(hart, RV_TRIG_SELECT | RV_CSR_FORCE_32_BIT, &trigger); /* Try reading the trigger info */ uint32_t info = 0; - if (!riscv_csr_read(hart, RV_TRIG_INFO | RV_CSR_FORCE_32_BIT, &info)) { + /* Some chips reply ok but return 0 (WCH)*/ + if (!riscv_csr_read(hart, RV_TRIG_INFO | RV_CSR_FORCE_32_BIT, &info) || !info) { /* * If that fails, it's probably because the tinfo register isn't implemented, so read * the tdata1 register instead and extract the type from the MSb and build the info bitset from that