From e9add75e8fe83d4935b085505db6847fdbda540b Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Thu, 15 Aug 2024 22:14:06 +0300 Subject: [PATCH 01/19] stm32h5: Replace DBGMCU base address for CPU access * BMD uses AP1 the AHB-AP and views the SoC address space like processor * 0xe0044000 is correct for AP0 the Debug APB but BMD doesn't use it --- src/target/stm32h5.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/target/stm32h5.c b/src/target/stm32h5.c index b3728c67c40..b49d8c811cc 100644 --- a/src/target/stm32h5.c +++ b/src/target/stm32h5.c @@ -98,7 +98,11 @@ #define STM32H5_FLASH_BANK_MASK 0x80000000U #define STM32H5_FLASH_SECTOR_COUNT_MASK 0x000000ffU -#define STM32H5_DBGMCU_BASE 0xe0044000 +/* + * Both on H56x and H503 DBGMCU is visible via AP0 on Debug APB at 0xe0044000, + * and via AP1 by the processor at 0x44024000 alias. + */ +#define STM32H5_DBGMCU_BASE 0x44024000 #define STM32H5_DBGMCU_IDCODE (STM32H5_DBGMCU_BASE + 0x00U) #define STM32H5_DBGMCU_CONFIG (STM32H5_DBGMCU_BASE + 0x04U) #define STM32H5_DBGMCU_APB1LFREEZE (STM32H5_DBGMCU_BASE + 0x08U) From eaa52e99c4393952f27f651f0cd77f7a284e4175 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Fri, 16 Aug 2024 20:39:40 +0300 Subject: [PATCH 02/19] stm32h5: Add SRAM alias for H503 at 0x20000000 --- src/target/stm32h5.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/target/stm32h5.c b/src/target/stm32h5.c index b49d8c811cc..9340853ba01 100644 --- a/src/target/stm32h5.c +++ b/src/target/stm32h5.c @@ -68,6 +68,8 @@ #define STM32H503_SRAM1_SIZE 0x00004000U #define STM32H503_SRAM2_BASE 0x0a004000U #define STM32H503_SRAM2_SIZE 0x00004000U +#define STM32H503_SRAM1_ALIAS 0x20000000U +#define STM32H503_SRAM2_ALIAS 0x20004000U #define STM32H5_FLASH_BASE 0x40022000 #define STM32H5_FLASH_ACCESS_CTRL (STM32H5_FLASH_BASE + 0x000U) @@ -240,6 +242,8 @@ bool stm32h5_probe(target_s *const target) */ target_add_ram32(target, STM32H503_SRAM1_BASE, STM32H503_SRAM1_SIZE); target_add_ram32(target, STM32H503_SRAM2_BASE, STM32H503_SRAM2_SIZE); + target_add_ram32(target, STM32H503_SRAM1_ALIAS, STM32H503_SRAM1_SIZE); + target_add_ram32(target, STM32H503_SRAM2_ALIAS, STM32H503_SRAM2_SIZE); /* Build the Flash map */ stm32h5_add_flash(target, STM32H503_FLASH_BANK1_BASE, STM32H503_FLASH_BANK_SIZE, From ea81f02f76bdfc94bb5a8f20c041ba24877fdd6b Mon Sep 17 00:00:00 2001 From: Dmitry Rezvanov <26044988+Misaka0x2730@users.noreply.github.com> Date: Sat, 17 Aug 2024 00:44:12 +0500 Subject: [PATCH 03/19] command: added "Platform commands:" message before platform-specific commands in cmd_help --- src/command.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/command.c b/src/command.c index 1c84e6540b3..52f94af8dd6 100644 --- a/src/command.c +++ b/src/command.c @@ -210,6 +210,7 @@ bool cmd_help(target_s *t, int argc, const char **argv) for (const command_s *cmd = cmd_list; cmd->cmd; cmd++) gdb_outf("\t%s -- %s\n", cmd->cmd, cmd->help); #ifdef PLATFORM_HAS_CUSTOM_COMMANDS + gdb_out("Platform commands:\n"); for (const command_s *cmd = platform_cmd_list; cmd->cmd; ++cmd) gdb_outf("\t%s -- %s\n", cmd->cmd, cmd->help); #endif From ac2605cfbb6c5800a2e306ec2600bdb79f89c35c Mon Sep 17 00:00:00 2001 From: dragonmux Date: Thu, 15 Aug 2024 11:23:31 +0100 Subject: [PATCH 04/19] stm32l4: Use the `priv` structure version of the `device` pointer, not the parameter in `stm32l4_configure_dbgmcu()` when configuring the DBGMCU --- src/target/stm32l4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/stm32l4.c b/src/target/stm32l4.c index da028c0b3bc..325bbc8adc7 100644 --- a/src/target/stm32l4.c +++ b/src/target/stm32l4.c @@ -575,7 +575,7 @@ static uint32_t stm32l4_main_sram_length(const target_s *const target) return (device->sram1 + device->sram2 + device->sram3) * 1024U; } -static bool stm32l4_configure_dbgmcu(target_s *const target, const stm32l4_device_info_s *device) +static bool stm32l4_configure_dbgmcu(target_s *const target, const stm32l4_device_info_s *const device) { /* If we're in the probe phase */ if (target->target_storage == NULL) { @@ -603,7 +603,7 @@ static bool stm32l4_configure_dbgmcu(target_s *const target, const stm32l4_devic * Now we have a stable debug environment, make sure the WDTs can't bonk the processor out from under us, * then Reconfigure the config register to prevent WFI/WFE from cutting debug access */ - if (device->family == STM32L4_FAMILY_L55x || device->family == STM32L4_FAMILY_U5xx) { + if (priv->device->family == STM32L4_FAMILY_L55x || priv->device->family == STM32L4_FAMILY_U5xx) { target_mem32_write32( target, STM32L5_DBGMCU_APB1FREEZE1, STM32L4_DBGMCU_APB1FREEZE1_IWDG | STM32L4_DBGMCU_APB1FREEZE1_WWDG); target_mem32_write32(target, STM32L5_DBGMCU_CONFIG, From db48ed56b66649214c2f8021b5405a8bea8fd01d Mon Sep 17 00:00:00 2001 From: Hristo Mitrev Date: Sun, 19 May 2024 22:24:19 +0300 Subject: [PATCH 05/19] Fix: -Wformat for tc_printf Signed-off-by: Hristo Mitrev --- src/target/ch579.c | 2 +- src/target/efm32.c | 18 +++++++++--------- src/target/lpc546xx.c | 2 +- src/target/nrf51.c | 18 +++++++++--------- src/target/renesas_ra.c | 2 +- src/target/sam3x.c | 2 +- src/target/samd.c | 2 +- src/target/samx5x.c | 2 +- src/target/semihosting.c | 2 +- src/target/stm32f1.c | 4 ++-- src/target/stm32g0.c | 2 +- src/target/stm32h7.c | 2 +- src/target/stm32l0.c | 19 ++++++++++--------- src/target/stm32l4.c | 2 +- src/target/target_internal.h | 10 +++++++++- 15 files changed, 49 insertions(+), 40 deletions(-) diff --git a/src/target/ch579.c b/src/target/ch579.c index 0ab94706d49..1528c940d27 100644 --- a/src/target/ch579.c +++ b/src/target/ch579.c @@ -136,7 +136,7 @@ bool ch579_probe(target_s *target) { uint8_t chip_id = target_mem32_read8(target, CH579_R8_CHIP_ID); if (chip_id != 0x79) { - DEBUG_ERROR("Not CH579! 0x%02" PRIx8 "\n", chip_id); + DEBUG_ERROR("Not CH579! 0x%02x\n", chip_id); return false; } diff --git a/src/target/efm32.c b/src/target/efm32.c index 52fb695c03b..fda2fc8e201 100644 --- a/src/target/efm32.c +++ b/src/target/efm32.c @@ -581,7 +581,7 @@ bool efm32_probe(target_s *t) /* Setup Target */ t->target_options |= TOPT_INHIBIT_NRST; t->driver = priv_storage->efm32_variant_string; - tc_printf(t, "flash size %u page size %u\n", flash_size, flash_page_size); + tc_printf(t, "flash size %" PRIu32 " page size %" PRIu32 "\n", flash_size, flash_page_size); target_add_ram32(t, SRAM_BASE, ram_size); efm32_add_flash(t, 0x00000000, flash_size, flash_page_size); @@ -744,11 +744,11 @@ static bool efm32_cmd_serial(target_s *t, int argc, const char **argv) break; default: - tc_printf(t, "Bad DI version %hhu! This driver doesn't know about this DI version\n", di_version); + tc_printf(t, "Bad DI version %u! This driver doesn't know about this DI version\n", di_version); return false; } - tc_printf(t, "Unique Number: 0x%016llx\n", unique); + tc_printf(t, "Unique Number: 0x%08" PRIx32 "%08" PRIx32 "\n", (uint32_t)(unique >> 32U), (uint32_t)unique); return true; } @@ -768,15 +768,15 @@ static bool efm32_cmd_efm_info(target_s *t, int argc, const char **argv) switch (di_version) { case 1: - tc_printf(t, "DI version 1 (silabs remix?) base 0x%08" PRIx32 "\n\n", EFM32_V1_DI); + tc_printf(t, "DI version 1 (silabs remix?) base 0x%08" PRIx16 "\n\n", EFM32_V1_DI); break; case 2: - tc_printf(t, "DI version 2 (energy micro remix?) base 0x%08" PRIx32 "\n\n", EFM32_V2_DI); + tc_printf(t, "DI version 2 (energy micro remix?) base 0x%08" PRIx16 "\n\n", EFM32_V2_DI); break; default: - tc_printf(t, "Bad DI version %hhu! This driver doesn't know about this DI version\n", di_version); + tc_printf(t, "Bad DI version %u! This driver doesn't know about this DI version\n", di_version); return false; } @@ -791,8 +791,8 @@ static bool efm32_cmd_efm_info(target_s *t, int argc, const char **argv) tc_printf(t, "%s %hu F%hu = %s %hukiB flash, %hukiB ram\n", device->name, part_number, flash_kib, device->description, flash_kib, ram_kib); - tc_printf(t, "Device says flash page size is %u bytes, we're using %u bytes\n", flash_page_size_reported, - flash_page_size); + tc_printf(t, "Device says flash page size is %" PRIu32 " bytes, we're using %" PRIu32 " bytes\n", + flash_page_size_reported, flash_page_size); if (flash_page_size_reported < flash_page_size) { tc_printf(t, "This is bad, flash writes may be corrupted\n"); } @@ -814,7 +814,7 @@ static bool efm32_cmd_efm_info(target_s *t, int argc, const char **argv) } } - tc_printf(t, "Package %s %hhu pins\n", pkgtype->name, miscchip.pincount); + tc_printf(t, "Package %s %u pins\n", pkgtype->name, miscchip.pincount); tc_printf(t, "Temperature grade %s\n", tempgrade->name); tc_printf(t, "\n"); } diff --git a/src/target/lpc546xx.c b/src/target/lpc546xx.c index 252fed6d745..341f2a1f352 100644 --- a/src/target/lpc546xx.c +++ b/src/target/lpc546xx.c @@ -208,7 +208,7 @@ static bool lpc546xx_cmd_read_partid(target_s *target, int argc, const char **ar iap_result_s result; if (lpc_iap_call(flash, &result, IAP_CMD_PARTID)) return false; - tc_printf(target, "PART ID: 0x%08x\n", result.values[0]); + tc_printf(target, "PART ID: 0x%08" PRIx32 "\n", result.values[0]); return true; } diff --git a/src/target/nrf51.c b/src/target/nrf51.c index c321b735013..2424168eebc 100644 --- a/src/target/nrf51.c +++ b/src/target/nrf51.c @@ -277,7 +277,7 @@ static bool nrf51_cmd_read_hwid(target_s *t, int argc, const char **argv) (void)argc; (void)argv; uint32_t hwid = target_mem32_read32(t, NRF51_FICR_CONFIGID) & 0xffffU; - tc_printf(t, "Hardware ID: 0x%04X\n", hwid); + tc_printf(t, "Hardware ID: 0x%04" PRIX32 "\n", hwid); return true; } @@ -287,7 +287,7 @@ static bool nrf51_cmd_read_fwid(target_s *t, int argc, const char **argv) (void)argc; (void)argv; uint32_t fwid = (target_mem32_read32(t, NRF51_FICR_CONFIGID) >> 16U) & 0xffffU; - tc_printf(t, "Firmware ID: 0x%04X\n", fwid); + tc_printf(t, "Firmware ID: 0x%04" PRIX32 "\n", fwid); return true; } @@ -299,7 +299,7 @@ static bool nrf51_cmd_read_deviceid(target_s *t, int argc, const char **argv) uint32_t deviceid_low = target_mem32_read32(t, NRF51_FICR_DEVICEID_LOW); uint32_t deviceid_high = target_mem32_read32(t, NRF51_FICR_DEVICEID_HIGH); - tc_printf(t, "Device ID: 0x%08X%08X\n", deviceid_high, deviceid_low); + tc_printf(t, "Device ID: 0x%08" PRIX32 "%08" PRIX32 "\n", deviceid_high, deviceid_low); return true; } @@ -328,7 +328,7 @@ static bool nrf51_cmd_read_deviceinfo(target_s *t, int argc, const char **argv) di.flash = target_mem32_read32(t, NRF51_FICR_DEVICE_INFO_FLASH); di.variant.f = target_mem32_read32(t, NRF51_FICR_DEVICE_INFO_VARIANT); - tc_printf(t, "Part:\t\tNRF%X\n", di.part); + tc_printf(t, "Part:\t\tNRF%" PRIX32 "\n", di.part); tc_printf(t, "Variant:\t%c%c%c%c\n", di.variant.c[3], di.variant.c[2], di.variant.c[1], di.variant.c[0]); tc_printf(t, "Package:\t"); switch (di.package) { @@ -345,12 +345,12 @@ static bool nrf51_cmd_read_deviceinfo(target_s *t, int argc, const char **argv) tc_printf(t, "QIxx\n"); break; default: - tc_printf(t, "Unknown (Code %X)\n", di.package); + tc_printf(t, "Unknown (Code %" PRIX32 ")\n", di.package); break; } - tc_printf(t, "Ram:\t\t%ukiB\n", di.ram); - tc_printf(t, "Flash:\t\t%ukiB\n", di.flash); + tc_printf(t, "Ram:\t\t%" PRIu32 "kiB\n", di.ram); + tc_printf(t, "Flash:\t\t%" PRIu32 "kiB\n", di.flash); return true; } @@ -363,9 +363,9 @@ static bool nrf51_cmd_read_deviceaddr(target_s *t, int argc, const char **argv) uint32_t addr_high = target_mem32_read32(t, NRF51_FICR_DEVICEADDR_HIGH) & 0xffffU; if (!(addr_type & 1U)) - tc_printf(t, "Publicly Listed Address: 0x%04X%08X\n", addr_high, addr_low); + tc_printf(t, "Publicly Listed Address: 0x%04" PRIX32 "%08" PRIX32 "\n", addr_high, addr_low); else - tc_printf(t, "Randomly Assigned Address: 0x%04X%08X\n", addr_high, addr_low); + tc_printf(t, "Randomly Assigned Address: 0x%04" PRIX32 "%08" PRIX32 "\n", addr_high, addr_low); return true; } diff --git a/src/target/renesas_ra.c b/src/target/renesas_ra.c index ed04ddcd092..c26ccbdf0d6 100644 --- a/src/target/renesas_ra.c +++ b/src/target/renesas_ra.c @@ -956,7 +956,7 @@ static bool renesas_uid(target_s *const target, const int argc, const char **con tc_printf(target, "Unique id: 0x"); for (size_t i = 0U; i < 16U; i++) - tc_printf(target, "%02" PRIx8, uid[i]); + tc_printf(target, "%02x", uid[i]); tc_printf(target, "\n"); return true; diff --git a/src/target/sam3x.c b/src/target/sam3x.c index 68cfa1169cf..adf62ed20a7 100644 --- a/src/target/sam3x.c +++ b/src/target/sam3x.c @@ -626,7 +626,7 @@ static bool sam_cmd_gpnvm(target_s *t, int argc, const char **argv) uint32_t gpnvm = 0; if (!sam_gpnvm_get(t, base, &gpnvm)) return false; - tc_printf(t, "GPNVM: 0x%08X\n", gpnvm); + tc_printf(t, "GPNVM: 0x%08" PRIX32 "\n", gpnvm); if (drv == DRIVER_SAMX7X && (mask & GPNVM_SAMX7X_TCM_BIT_MASK)) { sam_priv_s *storage = (sam_priv_s *)t->target_storage; diff --git a/src/target/samd.c b/src/target/samd.c index 698fd2d033a..60daa430ba1 100644 --- a/src/target/samd.c +++ b/src/target/samd.c @@ -846,7 +846,7 @@ static bool samd_cmd_serial(target_s *t, int argc, const char **argv) tc_printf(t, "Serial Number: 0x"); for (size_t i = 0; i < 4U; ++i) - tc_printf(t, "%08x", target_mem32_read32(t, SAMD_NVM_SERIAL(i))); + tc_printf(t, "%08" PRIx32 "", target_mem32_read32(t, SAMD_NVM_SERIAL(i))); tc_printf(t, "\n"); return true; } diff --git a/src/target/samx5x.c b/src/target/samx5x.c index 401e30b3272..736d52c27ab 100644 --- a/src/target/samx5x.c +++ b/src/target/samx5x.c @@ -730,7 +730,7 @@ static bool samx5x_cmd_serial(target_s *t, int argc, const char **argv) tc_printf(t, "Serial Number: 0x"); for (size_t i = 0; i < 4U; ++i) - tc_printf(t, "%08x", target_mem32_read32(t, SAMX5X_NVM_SERIAL(i))); + tc_printf(t, "%08" PRIx32 "", target_mem32_read32(t, SAMX5X_NVM_SERIAL(i))); tc_printf(t, "\n"); return true; } diff --git a/src/target/semihosting.c b/src/target/semihosting.c index 7f23bdc15c7..b85030f43a0 100644 --- a/src/target/semihosting.c +++ b/src/target/semihosting.c @@ -741,7 +741,7 @@ int32_t semihosting_exit(target_s *const target, const semihosting_exit_reason_e if (reason == EXIT_REASON_APPLICATION_EXIT) tc_printf(target, "exit(%" PRIu32 ")\n", status_code); else - tc_printf(target, "Exception trapped: %" PRIx32 " (%" PRIu32 ")\n", reason, status_code); + tc_printf(target, "Exception trapped: %x (%" PRIu32 ")\n", reason, status_code); target_halt_resume(target, true); return 0; } diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index 3534e72953e..8585b8950ce 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -1075,8 +1075,8 @@ static bool stm32f1_cmd_option(target_s *target, int argc, const char **argv) for (size_t i = 0U; i < 16U; i += 4U) { const uint32_t addr = FLASH_OBP_RDP + i; const uint32_t val = target_mem32_read32(target, addr); - tc_printf(target, "0x%08X: 0x%04X\n", addr, val & 0xffffU); - tc_printf(target, "0x%08X: 0x%04X\n", addr + 2U, val >> 16U); + tc_printf(target, "0x%08" PRIX32 ": 0x%04" PRIX32 "\n", addr, val & 0xffffU); + tc_printf(target, "0x%08" PRIX32 ": 0x%04" PRIX32 "\n", addr + 2U, val >> 16U); } return true; diff --git a/src/target/stm32g0.c b/src/target/stm32g0.c index 77b8d478f9a..6fd51ce8d0d 100644 --- a/src/target/stm32g0.c +++ b/src/target/stm32g0.c @@ -673,7 +673,7 @@ static void stm32g0_display_registers(target_s *target) { for (size_t i = 0; i < OPT_REG_COUNT; ++i) { const uint32_t val = target_mem32_read32(target, options_def[i].addr); - tc_printf(target, "0x%08X: 0x%08X\n", options_def[i].addr, val); + tc_printf(target, "0x%08" PRIX32 ": 0x%08" PRIX32 "\n", options_def[i].addr, val); } } diff --git a/src/target/stm32h7.c b/src/target/stm32h7.c index 2fd135f7871..2e3b52ed3f7 100644 --- a/src/target/stm32h7.c +++ b/src/target/stm32h7.c @@ -682,7 +682,7 @@ static bool stm32h7_crc(target_s *target, int argc, const char **argv) if (!stm32h7_crc_bank(target, STM32H7_FLASH_BANK2_BASE)) return false; uint32_t crc2 = target_mem32_read32(target, STM32H7_FPEC2_BASE + STM32H7_FLASH_CRCDATA); - tc_printf(target, "CRC: bank1 0x%08lx, bank2 0x%08lx\n", crc1, crc2); + tc_printf(target, "CRC: bank1 0x%08" PRIx32 ", bank2 0x%08" PRIx32 " \n", crc1, crc2); return true; } diff --git a/src/target/stm32l0.c b/src/target/stm32l0.c index 09092f249b7..7f8fd334a2e 100644 --- a/src/target/stm32l0.c +++ b/src/target/stm32l0.c @@ -757,7 +757,7 @@ static bool stm32lx_cmd_option(target_s *const target, const int argc, const cha uint32_t val = strtoul(argv[3], NULL, 0); if (!raw_write) val = (val & 0xffffU) | ((~val & 0xffffU) << 16U); - tc_printf(target, "%s %08x <- %08x\n", argv[1], addr, val); + tc_printf(target, "%s %08" PRIx32 " <- %08" PRIx32 "\n", argv[1], addr, val); if (addr >= STM32Lx_FLASH_OPT_BASE && addr < STM32Lx_FLASH_OPT_BASE + opt_size && (addr & 3U) == 0) { if (!stm32lx_option_write(target, addr, val)) @@ -770,22 +770,23 @@ static bool stm32lx_cmd_option(target_s *const target, const int argc, const cha for (size_t i = 0; i < opt_size; i += 4U) { const uint32_t addr = STM32Lx_FLASH_OPT_BASE + i; const uint32_t val = target_mem32_read32(target, addr); - tc_printf(target, "0x%08" PRIx32 ": 0x%04u 0x%04u %s\n", addr, val & 0xffffU, (val >> 16U) & 0xffffU, - (val & 0xffffU) == ((~val >> 16U) & 0xffffU) ? "OK" : "ERR"); + tc_printf(target, "0x%08" PRIx32 ": 0x%04" PRIu32 " 0x%04" PRIu32 " %s\n", addr, val & 0xffffU, + (val >> 16U) & 0xffffU, (val & 0xffffU) == ((~val >> 16U) & 0xffffU) ? "OK" : "ERR"); } const uint32_t options = target_mem32_read32(target, STM32Lx_FLASH_OPTR(flash_base)); const size_t read_protection = stm32lx_prot_level(options); if (stm32lx_is_stm32l1(target)) { tc_printf(target, - "OPTR: 0x%08" PRIx32 ", RDPRT %u, SPRMD %u, BOR %u, WDG_SW %u, nRST_STP %u, nRST_STBY %u, nBFB2 %u\n", - options, read_protection, (options & STM32L1_FLASH_OPTR_SPRMOD) ? 1 : 0, + "OPTR: 0x%08" PRIx32 ", RDPRT %" PRIu32 ", SPRMD %u, BOR %" PRIu32 " , WDG_SW %u" + ", nRST_STP %u, nRST_STBY %u, nBFB2 %u\n", + options, (uint32_t)read_protection, (options & STM32L1_FLASH_OPTR_SPRMOD) ? 1 : 0, (options >> STM32L1_FLASH_OPTR_BOR_LEV_SHIFT) & STM32L1_FLASH_OPTR_BOR_LEV_MASK, (options & STM32Lx_FLASH_OPTR_WDG_SW) ? 1 : 0, (options & STM32L1_FLASH_OPTR_nRST_STOP) ? 1 : 0, (options & STM32L1_FLASH_OPTR_nRST_STDBY) ? 1 : 0, (options & STM32L1_FLASH_OPTR_nBFB2) ? 1 : 0); } else { - tc_printf(target, "OPTR: 0x%08" PRIx32 ", RDPROT %u, WPRMOD %u, WDG_SW %u, BOOT1 %u\n", options, - read_protection, (options & STM32L0_FLASH_OPTR_WPRMOD) ? 1 : 0, + tc_printf(target, "OPTR: 0x%08" PRIx32 ", RDPROT %" PRIu32 ", WPRMOD %" PRIu16 ", WDG_SW %u, BOOT1 %u\n", + options, (uint32_t)read_protection, (options & STM32L0_FLASH_OPTR_WPRMOD) ? 1 : 0, (options & STM32Lx_FLASH_OPTR_WDG_SW) ? 1 : 0, (options & STM32L0_FLASH_OPTR_BOOT1) ? 1 : 0); } @@ -867,8 +868,8 @@ static bool stm32lx_cmd_eeprom(target_s *const target, const int argc, const cha tc_printf(target, " byte - Write a byte\n"); tc_printf(target, " halfword - Write a half-word\n"); tc_printf(target, " word - Write a word\n"); - tc_printf(target, "The value of must in the interval [0x%08x, 0x%x)\n", STM32Lx_FLASH_EEPROM_BASE, - STM32Lx_FLASH_EEPROM_BASE + stm32lx_nvm_eeprom_size(target)); + tc_printf(target, "The value of must in the interval [0x%08" PRIx32 ", 0x%" PRIx32 ")\n", + STM32Lx_FLASH_EEPROM_BASE, STM32Lx_FLASH_EEPROM_BASE + stm32lx_nvm_eeprom_size(target)); done: stm32lx_nvm_lock(target, flash_base); diff --git a/src/target/stm32l4.c b/src/target/stm32l4.c index 325bbc8adc7..b2f0095c323 100644 --- a/src/target/stm32l4.c +++ b/src/target/stm32l4.c @@ -1031,7 +1031,7 @@ static bool stm32l4_cmd_option(target_s *target, int argc, const char **argv) for (size_t i = 0; i < word_count; ++i) { const uint32_t addr = fpec_base + opt_reg_offsets[i]; const uint32_t val = target_mem32_read32(target, fpec_base + opt_reg_offsets[i]); - tc_printf(target, "0x%08X: 0x%08X\n", addr, val); + tc_printf(target, "0x%08" PRIX32 ": 0x%08" PRIX32 "\n", addr, val); } return true; } diff --git a/src/target/target_internal.h b/src/target/target_internal.h index 1d640011f77..313a4fdbfaf 100644 --- a/src/target/target_internal.h +++ b/src/target/target_internal.h @@ -208,7 +208,15 @@ bool target_mem64_write16(target_s *target, target_addr64_t addr, uint16_t value bool target_mem64_write8(target_s *target, target_addr64_t addr, uint8_t value); bool target_check_error(target_s *target); +#if defined(__MINGW32__) || defined(__MINGW64__) || defined(__CYGWIN__) +#define TC_FORMAT_ATTR __attribute__((format(__MINGW_PRINTF_FORMAT, 2, 3))) +#elif defined(__GNUC__) || defined(__clang__) +#define TC_FORMAT_ATTR __attribute__((format(printf, 2, 3))) +#else +#define TC_FORMAT_ATTR +#endif + /* Access to host controller interface */ -void tc_printf(target_s *target, const char *fmt, ...); +void tc_printf(target_s *target, const char *fmt, ...) TC_FORMAT_ATTR; #endif /* TARGET_TARGET_INTERNAL_H */ From cc33cb4de57934c42278db20747ee0f9eeda04bc Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sat, 17 Aug 2024 22:51:47 +0300 Subject: [PATCH 06/19] s32k3xx: Remove assert * Pulling __assert_func() and fiprintf() costs ~1.5 KiB of BMF flash * Target flash layer is guaranteed to call this with len=writesize anyways --- src/target/s32k3xx.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/target/s32k3xx.c b/src/target/s32k3xx.c index f79fac94ee6..06f02847806 100644 --- a/src/target/s32k3xx.c +++ b/src/target/s32k3xx.c @@ -23,8 +23,6 @@ * the XML memory map and Flash memory programming. */ -#include - #include "command.h" #include "general.h" #include "target.h" @@ -250,8 +248,6 @@ static bool s32k3xx_flash_erase(target_flash_s *const flash, target_addr_t addr, static bool s32k3xx_flash_write(target_flash_s *flash, target_addr_t dest, const void *src, size_t len) { - assert(len == flash->writesize); - const uint32_t *const s_data = src; s32k3xx_flash_prepare(flash); target_mem32_write32(flash->t, PFCPGM_PEADR_L, dest); From 2caf88dffe1c627136aaff06b6a85b3e133d9a3b Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 13:44:34 +0300 Subject: [PATCH 07/19] github: Enabled parallel make workers with output-sync per build target --- .github/workflows/build-pr.yml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/.github/workflows/build-pr.yml b/.github/workflows/build-pr.yml index 257be910190..c587d8f60b4 100644 --- a/.github/workflows/build-pr.yml +++ b/.github/workflows/build-pr.yml @@ -97,7 +97,7 @@ jobs: # Build the firmware for all platform variants and BMDA in BMP-only mode - name: Build all platform variants firmware and BMP only BMDA - run: make all_platforms HOSTED_BMP_ONLY=1 + run: make all_platforms HOSTED_BMP_ONLY=1 -j$(nproc) -Otarget - name: Clean run: make clean @@ -105,23 +105,23 @@ jobs: # Build all the firmware variants that have more than 128kiB of Flash, with RTT enabled - name: Build firmware with RTT run: | - make PROBE_HOST=96b_carbon ENABLE_RTT=1 + make PROBE_HOST=96b_carbon ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=blackpill-f401cc ENABLE_RTT=1 + make PROBE_HOST=blackpill-f401cc ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=blackpill-f401ce ENABLE_RTT=1 + make PROBE_HOST=blackpill-f401ce ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=blackpill-f411ce ENABLE_RTT=1 + make PROBE_HOST=blackpill-f411ce ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=f3 ENABLE_RTT=1 + make PROBE_HOST=f3 ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=f4discovery ENABLE_RTT=1 + make PROBE_HOST=f4discovery ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=hydrabus ENABLE_RTT=1 + make PROBE_HOST=hydrabus ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=launchpad-icdi ENABLE_RTT=1 + make PROBE_HOST=launchpad-icdi ENABLE_RTT=1 -j$(nproc) -Otarget make -C src clean - make PROBE_HOST=stlinkv3 ENABLE_RTT=1 + make PROBE_HOST=stlinkv3 ENABLE_RTT=1 -j$(nproc) -Otarget - name: Clean run: make clean @@ -132,7 +132,7 @@ jobs: # And build that full binary - name: Build full BMDA binary - run: make PROBE_HOST=hosted HOSTED_BMP_ONLY=0 + run: make PROBE_HOST=hosted HOSTED_BMP_ONLY=0 -j$(nproc) -Otarget build-windows-msvc: # Name the job more appropriately so we can tell which VS version is in use From b41f1c159472e752b5bc2d72e75d561bae7eaa6c Mon Sep 17 00:00:00 2001 From: ALTracer Date: Tue, 9 Apr 2024 10:51:05 +0300 Subject: [PATCH 08/19] stlink, swlink, blackpill-f4: clang-format SWO_DMA_* * Apparently clang-format now wants two spaces there --- src/platforms/common/blackpill-f4/blackpill-f4.h | 12 ++++++------ src/platforms/stlink/platform.h | 10 +++++----- src/platforms/swlink/platform.h | 10 +++++----- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/platforms/common/blackpill-f4/blackpill-f4.h b/src/platforms/common/blackpill-f4/blackpill-f4.h index 6fbb68b172c..6cdc7fe475b 100644 --- a/src/platforms/common/blackpill-f4/blackpill-f4.h +++ b/src/platforms/common/blackpill-f4/blackpill-f4.h @@ -299,12 +299,12 @@ extern bool debug_bmp; #define SWO_UART_PIN_AF GPIO_AF7 /* Bind to the same DMA Rx channel */ -#define SWO_DMA_BUS USBUSART1_DMA_BUS -#define SWO_DMA_CLK USBUSART1_DMA_CLK -#define SWO_DMA_CHAN USBUSART1_DMA_RX_CHAN -#define SWO_DMA_IRQ USBUSART1_DMA_RX_IRQ -#define SWO_DMA_ISR(x) USBUSART1_DMA_RX_ISRx(x) -#define SWO_DMA_TRG DMA_SxCR_CHSEL_4 +#define SWO_DMA_BUS USBUSART1_DMA_BUS +#define SWO_DMA_CLK USBUSART1_DMA_CLK +#define SWO_DMA_CHAN USBUSART1_DMA_RX_CHAN +#define SWO_DMA_IRQ USBUSART1_DMA_RX_IRQ +#define SWO_DMA_ISR(x) USBUSART1_DMA_RX_ISRx(x) +#define SWO_DMA_TRG DMA_SxCR_CHSEL_4 #define SET_RUN_STATE(state) \ { \ diff --git a/src/platforms/stlink/platform.h b/src/platforms/stlink/platform.h index 147d21d80f9..249dcd2d4bf 100644 --- a/src/platforms/stlink/platform.h +++ b/src/platforms/stlink/platform.h @@ -180,11 +180,11 @@ extern bool debug_bmp; #define SWO_UART_RX_PIN GPIO10 /* This DMA channel is set by the USART in use */ -#define SWO_DMA_BUS DMA1 -#define SWO_DMA_CLK RCC_DMA1 -#define SWO_DMA_CHAN DMA_CHANNEL5 -#define SWO_DMA_IRQ NVIC_DMA1_CHANNEL5_IRQ -#define SWO_DMA_ISR(x) dma1_channel5_isr(x) +#define SWO_DMA_BUS DMA1 +#define SWO_DMA_CLK RCC_DMA1 +#define SWO_DMA_CHAN DMA_CHANNEL5 +#define SWO_DMA_IRQ NVIC_DMA1_CHANNEL5_IRQ +#define SWO_DMA_ISR(x) dma1_channel5_isr(x) extern uint16_t led_idle_run; #define LED_IDLE_RUN led_idle_run diff --git a/src/platforms/swlink/platform.h b/src/platforms/swlink/platform.h index f7f5b6074d5..31c26c524bb 100644 --- a/src/platforms/swlink/platform.h +++ b/src/platforms/swlink/platform.h @@ -140,11 +140,11 @@ extern bool debug_bmp; #define SWO_UART_RX_PIN GPIO3 /* This DMA channel is set by the USART in use */ -#define SWO_DMA_BUS DMA1 -#define SWO_DMA_CLK RCC_DMA1 -#define SWO_DMA_CHAN DMA_CHANNEL6 -#define SWO_DMA_IRQ NVIC_DMA1_CHANNEL6_IRQ -#define SWO_DMA_ISR(x) dma1_channel6_isr(x) +#define SWO_DMA_BUS DMA1 +#define SWO_DMA_CLK RCC_DMA1 +#define SWO_DMA_CHAN DMA_CHANNEL6 +#define SWO_DMA_IRQ NVIC_DMA1_CHANNEL6_IRQ +#define SWO_DMA_ISR(x) dma1_channel6_isr(x) #define LED_PORT GPIOC #define LED_IDLE_RUN GPIO15 From 1251bc086b6911e034fc3124203b98ce89f6c232 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Mon, 27 Nov 2023 20:48:34 +0300 Subject: [PATCH 09/19] native, swlink: Allow TraceSWO Manchester on both platforms * Update the TRACE_TRIG_IN macro to current libopencm3 and move the `native` value from implementation to its platform.h; * Same for PWM input trigger macro * Pick one of implementations for swlink depending on makeflag --- src/platforms/common/stm32/traceswo.c | 6 +++--- src/platforms/native/platform.h | 6 ++++++ src/platforms/swlink/Makefile.inc | 11 +++++++++-- src/platforms/swlink/platform.h | 19 ++++++++++++++----- 4 files changed, 32 insertions(+), 10 deletions(-) diff --git a/src/platforms/common/stm32/traceswo.c b/src/platforms/common/stm32/traceswo.c index 79a70011d0d..8e8a32876da 100644 --- a/src/platforms/common/stm32/traceswo.c +++ b/src/platforms/common/stm32/traceswo.c @@ -57,15 +57,15 @@ void traceswo_init(uint32_t swo_chan_bitmask) */ /* Use TI1 as capture input for CH1 and CH2 */ - timer_ic_set_input(TRACE_TIM, TIM_IC1, TIM_IC_IN_TI1); - timer_ic_set_input(TRACE_TIM, TIM_IC2, TIM_IC_IN_TI1); + timer_ic_set_input(TRACE_TIM, TIM_IC1, TRACE_IC_IN); + timer_ic_set_input(TRACE_TIM, TIM_IC2, TRACE_IC_IN); /* Capture CH1 on rising edge, CH2 on falling edge */ timer_ic_set_polarity(TRACE_TIM, TIM_IC1, TIM_IC_RISING); timer_ic_set_polarity(TRACE_TIM, TIM_IC2, TIM_IC_FALLING); /* Trigger on Filtered Timer Input 1 (TI1FP1) */ - timer_slave_set_trigger(TRACE_TIM, TIM_SMCR_TS_TI1FP1); + timer_slave_set_trigger(TRACE_TIM, TRACE_TRIG_IN); /* Slave reset mode: reset counter on trigger */ timer_slave_set_mode(TRACE_TIM, TIM_SMCR_SMS_RM); diff --git a/src/platforms/native/platform.h b/src/platforms/native/platform.h index a79507f84b1..870171e37b7 100644 --- a/src/platforms/native/platform.h +++ b/src/platforms/native/platform.h @@ -27,6 +27,7 @@ #include "timing.h" #include "timing_stm32.h" +#define TRACESWO_PROTOCOL 1U /* 1 = Manchester, 2 = NRZ / async */ #define PLATFORM_HAS_TRACESWO #define PLATFORM_HAS_POWER_SWITCH @@ -288,10 +289,15 @@ extern int hwversion; #define USBUSART2_DMA_RX_IRQ NVIC_DMA1_CHANNEL6_IRQ #define USBUSART2_DMA_RX_ISR(x) dma1_channel6_isr(x) +#if TRACESWO_PROTOCOL == 1 +/* Use TIM3 Input 1 (from PA6/TDO) */ #define TRACE_TIM TIM3 #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) #define TRACE_IRQ NVIC_TIM3_IRQ #define TRACE_ISR(x) tim3_isr(x) +#define TRACE_IC_IN TIM_IC_IN_TI1 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 +#endif #define SET_RUN_STATE(state) running_status = (state) #define SET_IDLE_STATE(state) gpio_set_val(LED_PORT, LED_IDLE_RUN, state) diff --git a/src/platforms/swlink/Makefile.inc b/src/platforms/swlink/Makefile.inc index b19cae3f435..00fbf5336be 100644 --- a/src/platforms/swlink/Makefile.inc +++ b/src/platforms/swlink/Makefile.inc @@ -25,8 +25,15 @@ SRC += \ timing.c \ timing_stm32.c \ traceswodecode.c \ - traceswoasync.c \ - platform_common.c \ + platform_common.c + +ifeq ($(TRACESWO_PROTOCOL), 1) +SRC += traceswo.c +CFLAGS += -DTRACESWO_PROTOCOL=1 +else +SRC += traceswoasync.c +CFLAGS += -DTRACESWO_PROTOCOL=2 +endif all: blackmagic.bin blackmagic_dfu.bin blackmagic_dfu.hex diff --git a/src/platforms/swlink/platform.h b/src/platforms/swlink/platform.h index 31c26c524bb..62a5f408665 100644 --- a/src/platforms/swlink/platform.h +++ b/src/platforms/swlink/platform.h @@ -56,10 +56,6 @@ extern bool debug_bmp; #define LED_PORT_UART GPIOC #define LED_UART GPIO14 -#define PLATFORM_HAS_TRACESWO 1 -#define NUM_TRACE_PACKETS 128U /* This is an 8K buffer */ -#define TRACESWO_PROTOCOL 2U /* 1 = Manchester, 2 = NRZ / async */ - #define SWD_CR GPIO_CRH(SWDIO_PORT) #define SWD_CR_MULT (1U << ((13U - 8U) << 2U)) @@ -100,6 +96,7 @@ extern bool debug_bmp; #define IRQ_PRI_USBUSART_DMA (2U << 4U) #define IRQ_PRI_USB_VBUS (14U << 4U) #define IRQ_PRI_SWO_DMA (0U << 4U) +#define IRQ_PRI_TRACE (0U << 4U) #define USBUSART USART1 #define USBUSART_CR1 USART1_CR1 @@ -121,12 +118,22 @@ extern bool debug_bmp; #define USBUSART_DMA_RX_IRQ NVIC_DMA1_CHANNEL5_IRQ #define USBUSART_DMA_RX_ISR(x) dma1_channel5_isr(x) +#define PLATFORM_HAS_TRACESWO 1 +#define NUM_TRACE_PACKETS 128U /* This is an 8K buffer */ +//#define TRACESWO_PROTOCOL 2U /* 1 = Manchester, 2 = NRZ / async */ + +#if TRACESWO_PROTOCOL == 1 + +/* Use TIM2 Input 2 (from PB3/TDO with Remap) */ #define TRACE_TIM TIM2 #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM2) #define TRACE_IRQ NVIC_TIM2_IRQ #define TRACE_ISR(x) tim2_isr(x) #define TRACE_IC_IN TIM_IC_IN_TI2 -#define TRACE_TRIG_IN TIM_SMCR_TS_IT1FP2 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI2FP2 +/* was TIM_SMCR_TS_IT1FP2 from 2010 API */ + +#elif TRACESWO_PROTOCOL == 2 /* * On F103, only USART1 is on AHB2 and can reach 4.5MBaud at 72 MHz. @@ -146,6 +153,8 @@ extern bool debug_bmp; #define SWO_DMA_IRQ NVIC_DMA1_CHANNEL6_IRQ #define SWO_DMA_ISR(x) dma1_channel6_isr(x) +#endif /* TRACESWO_PROTOCOL */ + #define LED_PORT GPIOC #define LED_IDLE_RUN GPIO15 #define SET_RUN_STATE(state) From 9a70d007d1e2910217116b68eff948e42493bbe9 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Tue, 9 Apr 2024 10:43:12 +0300 Subject: [PATCH 10/19] stlink: Allow TraceSWO Manchester * Copy config of `native` (same pin & timer, PA6 TIM3_CH1) * Add makeflags and SWIM_AS_UART interlocks --- src/platforms/stlink/Makefile.inc | 6 ++++++ src/platforms/stlink/platform.h | 28 +++++++++++++++++++++------- 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/platforms/stlink/Makefile.inc b/src/platforms/stlink/Makefile.inc index 2b9131f317f..ff3ce06ba29 100644 --- a/src/platforms/stlink/Makefile.inc +++ b/src/platforms/stlink/Makefile.inc @@ -33,7 +33,13 @@ endif ifeq ($(SWIM_NRST_AS_UART), 1) CFLAGS += -DSWIM_NRST_AS_UART=1 else +ifeq ($(TRACESWO_PROTOCOL), 1) +SRC += traceswo.c +CFLAGS += -DTRACESWO_PROTOCOL=1 +else SRC += traceswoasync.c +CFLAGS += -DTRACESWO_PROTOCOL=2 +endif endif ifeq ($(BLUEPILL), 1) diff --git a/src/platforms/stlink/platform.h b/src/platforms/stlink/platform.h index 249dcd2d4bf..a2cd754916f 100644 --- a/src/platforms/stlink/platform.h +++ b/src/platforms/stlink/platform.h @@ -76,13 +76,6 @@ extern bool debug_bmp; #define LED_PORT_UART GPIOA #define LED_UART GPIO9 -#ifndef SWIM_NRST_AS_UART -#define PLATFORM_HAS_TRACESWO 1 -#endif - -#define NUM_TRACE_PACKETS 128U /* This is an 8K buffer */ -#define TRACESWO_PROTOCOL 2U /* 1 = Manchester, 2 = NRZ / async */ - #define SWD_CR GPIO_CRH(SWDIO_PORT) #define SWD_CR_MULT (1U << ((14U - 8U) << 2U)) @@ -134,6 +127,7 @@ extern bool debug_bmp; #define IRQ_PRI_USBUSART_DMA (2U << 4U) #define IRQ_PRI_USB_VBUS (14U << 4U) #define IRQ_PRI_SWO_DMA (0U << 4U) +#define IRQ_PRI_TRACE (0U << 4U) #ifdef SWIM_NRST_AS_UART #define USBUSART USART1 @@ -172,6 +166,24 @@ extern bool debug_bmp; #define USBUSART_DMA_BUS DMA1 #define USBUSART_DMA_CLK RCC_DMA1 +#ifndef SWIM_AS_UART +#define PLATFORM_HAS_TRACESWO 1 +#endif +#define NUM_TRACE_PACKETS 128U /* This is an 8K buffer */ +//#define TRACESWO_PROTOCOL 2U /* 1 = Manchester, 2 = NRZ / async */ + +#if TRACESWO_PROTOCOL == 1 + +/* Use TIM3 Input 1 (from PA6/TDO) */ +#define TRACE_TIM TIM3 +#define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) +#define TRACE_IRQ NVIC_TIM3_IRQ +#define TRACE_ISR(x) tim3_isr(x) +#define TRACE_IC_IN TIM_IC_IN_TI1 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 + +#elif TRACESWO_PROTOCOL == 2 + /* On F103, only USART1 is on AHB2 and can reach 4.5MBaud at 72 MHz. */ #define SWO_UART USART1 #define SWO_UART_DR USART1_DR @@ -186,6 +198,8 @@ extern bool debug_bmp; #define SWO_DMA_IRQ NVIC_DMA1_CHANNEL5_IRQ #define SWO_DMA_ISR(x) dma1_channel5_isr(x) +#endif /* TRACESWO_PROTOCOL */ + extern uint16_t led_idle_run; #define LED_IDLE_RUN led_idle_run #define SET_RUN_STATE(state) \ From b54eb023df7d08c61d7dc3bad73b2c4da7c4a4be Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Tue, 4 Jun 2024 21:34:41 +0300 Subject: [PATCH 11/19] common/stm32/traceswo: Map timer AF for STM32F4 (and F0, F3) --- src/platforms/common/stm32/traceswo.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/platforms/common/stm32/traceswo.c b/src/platforms/common/stm32/traceswo.c index 8e8a32876da..9b12840abc3 100644 --- a/src/platforms/common/stm32/traceswo.c +++ b/src/platforms/common/stm32/traceswo.c @@ -81,6 +81,12 @@ void traceswo_init(uint32_t swo_chan_bitmask) timer_enable_counter(TRACE_TIM); +#if defined(STM32F4) || defined(STM32F0) || defined(STM32F3) + /* AF2: TIM3/TIM4/TIM5 */ + gpio_mode_setup(TDO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TDO_PIN); + gpio_set_af(TDO_PORT, TRACE_TIM_PIN_AF, TDO_PIN); +#endif + traceswo_setmask(swo_chan_bitmask); decoding = (swo_chan_bitmask != 0); } From cf158ca642837d034f8355b63d2f372a4a22b765 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Tue, 9 Apr 2024 11:37:43 +0300 Subject: [PATCH 12/19] blackpill-f4: Map proper timer & channel for TraceSWO Manchester * TIM3 was used by native & stlink * Alternative pinouts put JTDO/TRACESWO on PB7 or PB6, which have AF for TIM4 CH1 or CH2, use them via PINOUT_SWITCH --- .../common/blackpill-f4/Makefile.inc | 9 ++++++- .../common/blackpill-f4/blackpill-f4.h | 26 +++++++++++++------ 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/src/platforms/common/blackpill-f4/Makefile.inc b/src/platforms/common/blackpill-f4/Makefile.inc index 044079a5374..79cbd5e768d 100644 --- a/src/platforms/common/blackpill-f4/Makefile.inc +++ b/src/platforms/common/blackpill-f4/Makefile.inc @@ -58,11 +58,18 @@ VPATH += \ SRC += \ blackpill-f4.c \ traceswodecode.c \ - traceswoasync.c \ serialno.c \ timing.c \ timing_stm32.c +ifeq ($(TRACESWO_PROTOCOL), 1) +SRC += traceswo.c +CFLAGS += -DTRACESWO_PROTOCOL=1 +else +SRC += traceswoasync.c +CFLAGS += -DTRACESWO_PROTOCOL=2 +endif + ifneq ($(BMD_BOOTLOADER), 1) all: blackmagic.bin else diff --git a/src/platforms/common/blackpill-f4/blackpill-f4.h b/src/platforms/common/blackpill-f4/blackpill-f4.h index 6cdc7fe475b..bee47065b94 100644 --- a/src/platforms/common/blackpill-f4/blackpill-f4.h +++ b/src/platforms/common/blackpill-f4/blackpill-f4.h @@ -32,10 +32,6 @@ #include "timing.h" #include "timing_stm32.h" -#define PLATFORM_HAS_TRACESWO -#define NUM_TRACE_PACKETS 256U /* 16K buffer */ -#define TRACESWO_PROTOCOL 2U /* 1 = RZ/Manchester, 2 = NRZ/async/uart */ - #if ENABLE_DEBUG == 1 #define PLATFORM_HAS_DEBUG extern bool debug_bmp; @@ -285,10 +281,22 @@ extern bool debug_bmp; #define IRQ_PRI_TRACE (0U << 4U) #define IRQ_PRI_SWO_DMA (0U << 4U) -#define TRACE_TIM TIM3 -#define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) -#define TRACE_IRQ NVIC_TIM3_IRQ -#define TRACE_ISR(x) tim3_isr(x) +#define PLATFORM_HAS_TRACESWO +#define NUM_TRACE_PACKETS 256U /* 16K buffer */ +//#define TRACESWO_PROTOCOL 2U /* 1 = RZ/Manchester, 2 = NRZ/async/uart */ + +#if TRACESWO_PROTOCOL == 1 + +/* Use TIM4 Input 2 (from PB7/TDO) or Input 1 (from PB6/TDO), AF2, trigger on Rising Edge */ +#define TRACE_TIM TIM4 +#define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM4) +#define TRACE_IRQ NVIC_TIM4_IRQ +#define TRACE_ISR(x) tim4_isr(x) +#define TRACE_IC_IN PINOUT_SWITCH(TIM_IC_IN_TI2, TIM_IC_IN_TI1) +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 +#define TRACE_TIM_PIN_AF GPIO_AF2 + +#elif TRACESWO_PROTOCOL == 2 /* On F411 use USART1_RX mapped on PB7 for async capture */ #define SWO_UART USBUSART1 @@ -306,6 +314,8 @@ extern bool debug_bmp; #define SWO_DMA_ISR(x) USBUSART1_DMA_RX_ISRx(x) #define SWO_DMA_TRG DMA_SxCR_CHSEL_4 +#endif /* TRACESWO_PROTOCOL */ + #define SET_RUN_STATE(state) \ { \ running_status = (state); \ From dbeb242d3199e5dff5935deb9b4985427228e077 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 15:20:28 +0300 Subject: [PATCH 13/19] 96b_carbon: Remove traceswo * This is an STM32F401RE platform with limited pin choice. * TDO is on PB12, which does not have AF for TIMx_CH1/2 or USARTx_RX. * Rather than lying to the user and performing UB, disable the driver completely. --- src/platforms/96b_carbon/Makefile.inc | 2 -- src/platforms/96b_carbon/meson.build | 2 +- src/platforms/96b_carbon/platform.h | 8 -------- 3 files changed, 1 insertion(+), 11 deletions(-) diff --git a/src/platforms/96b_carbon/Makefile.inc b/src/platforms/96b_carbon/Makefile.inc index b542ec8768e..97549572fb3 100644 --- a/src/platforms/96b_carbon/Makefile.inc +++ b/src/platforms/96b_carbon/Makefile.inc @@ -17,8 +17,6 @@ VPATH += platforms/common/stm32 SRC += \ platform.c \ - traceswodecode.c \ - traceswo.c \ serialno.c \ timing.c \ timing_stm32.c diff --git a/src/platforms/96b_carbon/meson.build b/src/platforms/96b_carbon/meson.build index a16520fb281..b882e66dffa 100644 --- a/src/platforms/96b_carbon/meson.build +++ b/src/platforms/96b_carbon/meson.build @@ -49,7 +49,7 @@ probe_host = declare_dependency( sources: probe_96b_carbon_sources, compile_args: probe_96b_carbon_args, link_args: probe_96b_carbon_link_args, - dependencies: [platform_common, platform_stm32f4, fixme_platform_stm32_traceswo], + dependencies: [platform_common, platform_stm32f4], ) probe_bootloader = declare_dependency( diff --git a/src/platforms/96b_carbon/platform.h b/src/platforms/96b_carbon/platform.h index 6349cda3936..f3024737f1b 100644 --- a/src/platforms/96b_carbon/platform.h +++ b/src/platforms/96b_carbon/platform.h @@ -28,7 +28,6 @@ #include "timing_stm32.h" #include "version.h" -#define PLATFORM_HAS_TRACESWO #define PLATFORM_IDENT "(Carbon)" /* @@ -86,14 +85,12 @@ #define USB_ISR otg_fs_isr /* * Interrupt priorities. Low numbers are high priority. - * TIM3 is used for traceswo capture and must be highest priority. * USBUSART can be lowest priority as it is using DMA to transfer * data to the buffer and thus is less critical than USB. */ #define IRQ_PRI_USB (1U << 4U) #define IRQ_PRI_USBUSART (2U << 4U) #define IRQ_PRI_USBUSART_DMA (2U << 4U) -#define IRQ_PRI_TRACE (0U << 4U) #define USBUSART USART2 #define USBUSART_CR1 USART2_CR1 @@ -123,11 +120,6 @@ gpio_set_af(USBUSART_RX_PORT, GPIO_AF7, USBUSART_RX_PIN); \ } while (0) -#define TRACE_TIM TIM3 -#define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) -#define TRACE_IRQ NVIC_TIM3_IRQ -#define TRACE_ISR(x) tim3_isr(x) - #define DEBUG(...) \ do { \ } while (false) From 0b8dc3db6fcffe131108ab5e4938ea676d0f8b70 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 15:29:22 +0300 Subject: [PATCH 14/19] ctxlink: Update TraceSWO TIM macros * TDO is PC7, it has TIM3_CH2 in AF2 (and USART6_RX in AF8) --- src/platforms/ctxlink/platform.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/platforms/ctxlink/platform.h b/src/platforms/ctxlink/platform.h index 97e45c7d0c9..13b9332bd5b 100644 --- a/src/platforms/ctxlink/platform.h +++ b/src/platforms/ctxlink/platform.h @@ -173,10 +173,14 @@ #define IRQ_PRI_USBUSART_DMA (2U << 4U) #define IRQ_PRI_TRACE (0U << 4U) +/* Use TIM3 Input 2 (from PC7/TDO) AF2, trigger on Rising Edge */ #define TRACE_TIM TIM3 #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) #define TRACE_IRQ NVIC_TIM3_IRQ #define TRACE_ISR(x) tim3_isr(x) +#define TRACE_IC_IN TIM_IC_IN_TI2 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 +#define TRACE_TIM_PIN_AF GPIO_AF2 #define SET_RUN_STATE(state) \ { \ From b230706a912422297a46747ebf79fc623def7d89 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 15:34:09 +0300 Subject: [PATCH 15/19] f072, f3: Update TraceSWO TIM macros --- src/platforms/f072/platform.h | 3 +++ src/platforms/f3/platform.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/platforms/f072/platform.h b/src/platforms/f072/platform.h index 259108d0fb2..70ca359e67e 100644 --- a/src/platforms/f072/platform.h +++ b/src/platforms/f072/platform.h @@ -132,6 +132,9 @@ #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) #define TRACE_IRQ NVIC_TIM3_IRQ #define TRACE_ISR tim3_isr +#define TRACE_IC_IN TIM_IC_IN_TI1 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 +#define TRACE_TIM_PIN_AF GPIO_AF1 #if ENABLE_DEBUG == 1 extern bool debug_bmp; diff --git a/src/platforms/f3/platform.h b/src/platforms/f3/platform.h index 3344f2b46f0..94983bd98da 100644 --- a/src/platforms/f3/platform.h +++ b/src/platforms/f3/platform.h @@ -125,6 +125,9 @@ #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) #define TRACE_IRQ NVIC_TIM3_IRQ #define TRACE_ISR tim3_isr +#define TRACE_IC_IN TIM_IC_IN_TI1 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 +#define TRACE_TIM_PIN_AF GPIO_AF2 #if ENABLE_DEBUG == 1 extern bool debug_bmp; From c694e4a15a5c8af1b31bb862af6622b3d2db6650 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 15:45:31 +0300 Subject: [PATCH 16/19] f4discovery: Update TraceSWO TIM macros --- src/platforms/f4discovery/platform.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/platforms/f4discovery/platform.h b/src/platforms/f4discovery/platform.h index 8aee0f5be84..0036e7c86da 100644 --- a/src/platforms/f4discovery/platform.h +++ b/src/platforms/f4discovery/platform.h @@ -130,6 +130,9 @@ #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) #define TRACE_IRQ NVIC_TIM3_IRQ #define TRACE_ISR(x) tim3_isr(x) +#define TRACE_IC_IN TIM_IC_IN_TI1 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 +#define TRACE_TIM_PIN_AF GPIO_AF2 #define SET_RUN_STATE(state) \ { \ From 9afe520d54fd3b1ec6dc505d743d61e8486a6f05 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 15:55:16 +0300 Subject: [PATCH 17/19] hydrabus: Update TraceSWO TIM macros * Cannot use PC2 TDO for TIM acceleration; chosen PC6 as TIM3_CH1. Needs an external wire. --- src/platforms/hydrabus/platform.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/platforms/hydrabus/platform.h b/src/platforms/hydrabus/platform.h index 13f53abad0a..3a3ed298241 100644 --- a/src/platforms/hydrabus/platform.h +++ b/src/platforms/hydrabus/platform.h @@ -124,10 +124,14 @@ /* For STM32F4 DMA trigger source must be specified */ #define USBUSART_DMA_TRG DMA_SxCR_CHSEL_4 +/* Use TIM3 Input 1 (from PC6), AF2, trigger on Rising Edge. FIXME: TDO is on PC2. */ #define TRACE_TIM TIM3 #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3) #define TRACE_IRQ NVIC_TIM3_IRQ #define TRACE_ISR(x) tim3_isr(x) +#define TRACE_IC_IN TIM_IC_IN_TI1 +#define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1 +#define TRACE_TIM_PIN_AF GPIO_AF2 #define SET_RUN_STATE(state) \ { \ From 992f8714ffff647ae87d2a63aa5be21d0fa4864b Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 16:21:45 +0300 Subject: [PATCH 18/19] meson: stlink, swlink, blackpill-f4: Default to Async TraceSWO --- src/platforms/common/blackpill-f4/meson.build | 1 + src/platforms/stlink/meson.build | 3 +++ src/platforms/swlink/meson.build | 1 + 3 files changed, 5 insertions(+) diff --git a/src/platforms/common/blackpill-f4/meson.build b/src/platforms/common/blackpill-f4/meson.build index 399ae8ea584..71206e54ba0 100644 --- a/src/platforms/common/blackpill-f4/meson.build +++ b/src/platforms/common/blackpill-f4/meson.build @@ -53,6 +53,7 @@ probe_blackpill_load_address = bmd_bootloader ? '0x08004000' : '0x08000000' probe_blackpill_args = [ f'-DDFU_SERIAL_LENGTH=@probe_blackpill_dfu_serial_length@', f'-DAPP_START=@probe_blackpill_load_address@', + '-DTRACESWO_PROTOCOL=2', ] blackpill_alternative_pinout = get_option('alternative_pinout') diff --git a/src/platforms/stlink/meson.build b/src/platforms/stlink/meson.build index a0c0a455c82..a5bb3422ccc 100644 --- a/src/platforms/stlink/meson.build +++ b/src/platforms/stlink/meson.build @@ -71,8 +71,11 @@ stlink_swim_nrst_as_uart = get_option('stlink_swim_nrst_as_uart') if probe == 'stlink' and stlink_swim_nrst_as_uart probe_stlink_args += ['-DSWIM_NRST_AS_UART=1'] + probe_stlink_dependencies += fixme_platform_stm32_traceswo + probe_stlink_args += ['-DTRACESWO_PROTOCOL=1'] else probe_stlink_dependencies += fixme_platform_stm32_traceswoasync + probe_stlink_args += ['-DTRACESWO_PROTOCOL=2'] endif probe_host = declare_dependency( diff --git a/src/platforms/swlink/meson.build b/src/platforms/swlink/meson.build index 9b862b98a96..d0471cc1703 100644 --- a/src/platforms/swlink/meson.build +++ b/src/platforms/swlink/meson.build @@ -42,6 +42,7 @@ probe_swlink_dfu_sources = files( probe_swlink_args = [ '-DDFU_SERIAL_LENGTH=9', + '-DTRACESWO_PROTOCOL=2', ] probe_swlink_common_link_args = [ From c43c1287895c2f447fbc061504f74e5c0bb707a1 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 18 Aug 2024 18:00:23 +0300 Subject: [PATCH 19/19] target_flash: Prevent NULL dereference when detached from targets --- src/target/target_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/target_flash.c b/src/target/target_flash.c index f20b7042d1b..2d744937634 100644 --- a/src/target/target_flash.c +++ b/src/target/target_flash.c @@ -300,7 +300,7 @@ bool target_flash_write(target_s *target, target_addr_t dest, const void *src, s bool target_flash_complete(target_s *target) { - if (!target->flash_mode) + if (!target || !target->flash_mode) return false; bool result = true; /* Catch false returns with &= */