diff --git a/src/target/cortexar.c b/src/target/cortexar.c
index d3937f013a3..868eeaf3087 100644
--- a/src/target/cortexar.c
+++ b/src/target/cortexar.c
@@ -312,6 +312,8 @@ static const uint16_t cortexar_spsr_encodings[5] = {
 /* Instruction Cache Invalidate ALL to Unification */
 #define CORTEXAR_ICIALLU 15U, ENCODE_CP_REG(7U, 5U, 0U, 0U)
 /* Data Cache Clean + Invalidate by Set/Way to Unification */
+#define CORTEXAR_DCCSW 15U, ENCODE_CP_REG(7U, 10U, 0U, 2U)
+/* Data Cache Clean + Invalidate by Set/Way to Unification */
 #define CORTEXAR_DCCISW 15U, ENCODE_CP_REG(7U, 14U, 0U, 2U)
 /* Address Translate Stage 1 Current state PL1 Read */
 #define CORTEXAR_ATS1CPR 15U, ENCODE_CP_REG(7U, 8U, 0U, 0U)
@@ -547,6 +549,7 @@ static void cortexar_regs_save(target_s *const target)
 
 static inline void cortexar_core_reg_write(target_s *const target, const uint8_t reg, const uint32_t value)
 {
+	cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
 	/* If the register is a GPR and not the program counter, use a "simple" MCR to read */
 	if (reg < 15U)
 		/* Build and issue a coprocessor to core transfer for the requested register and send the new data */
@@ -638,16 +641,33 @@ static void cortexar_coproc_write(target_s *const target, const uint8_t coproc,
 			ENCODE_CP_ACCESS(coproc & 0xfU, (op >> 8U) & 0x7U, 0U, (op >> 4U) & 0xfU, op & 0xfU, (op >> 12U) & 0x7U));
 }
 
+/*
+ * Check if the provided address falls within defined RAM ranges for the target
+ */
+static bool cortexar_check_is_addr_in_ram(target_s *const target, const target_addr_t addr)
+{
+	for (target_ram_s *r = target->ram; r; r = r->next) {
+		if (addr >= r->start && addr < r->start + r->length) {
+			return true;
+		}
+	}
+	return false;
+}
+
 /*
  * Perform a virtual to physical address translation.
  * NB: This requires the core to be halted! Trashes r0.
  */
 static target_addr_t cortexar_virt_to_phys(target_s *const target, const target_addr_t virt_addr)
 {
+	/* If address is a RAM location for the target, keep it as-is. */
+	if (cortexar_check_is_addr_in_ram(target, virt_addr)) {
+		return virt_addr;
+	}
+
 	/* Check if the target is PMSA and return early if it is */
 	if (!(target->target_options & TOPT_FLAVOUR_VIRT_MEM))
 		return virt_addr;
-
 	/*
 	 * Now we know the target is VMSA and so has the address translation machinery,
 	 * start by loading r0 with the VA to translate and request its translation
@@ -1455,6 +1475,7 @@ static void cortexar_halt_resume(target_s *const target, const bool step)
 	/* Invalidate all the instruction caches if we're on a VMSA model device */
 	if (target->target_options & TOPT_FLAVOUR_VIRT_MEM)
 		cortexar_coproc_write(target, CORTEXAR_ICIALLU, 0U);
+
 	/* Mark the fault status and address cache invalid */
 	priv->core_status &= ~CORTEXAR_STATUS_FAULT_CACHE_VALID;