How the reset pin connect to caravel soc?

[TonyHo722]

After trace code in https://github.com/efabless/caravel/tree/mpw-8c

my code trace

https://hackmd.io/@TonyHo/Bk163Nebn

Summary the result base on my code trace

When not defined TOP_ROUTING and define USE_POWER_PINS

resetb come from testbench when no defined TOP_ROUTING and connect to sky130_fd_io__top_xres4v2 resetb_pad.
the resetb_pad output resetb_core_h to caravel.v
[Tony] the resetb from testbench is only used in simulation for the behavior. When ACTUAL CHIP INTEGRATION, the resetb signal is no used.

When defined TOP_ROUTING

I suspect in silicon, the reset pin is connect to resetb_pad and resetb_pad output resetb_core_h to caravel.v (TOP_ROUTING is defined when ACTUAL CHIP INTEGRATION)

• I have no idea how to trace the code in resetb_pad during "ACTUAL CHIP INTEGRATION"
• how to get the schematic of resetb_pad? how it transfer reset pin input to resetb_core_h signal.

https://github.com/efabless/caravel/blob/mpw-8c/openlane/caravel/interactive.tcl#L20-L39

# ACTUAL CHIP INTEGRATION
prep -design $script_dir -tag caravel -overwrite 


file copy $script_dir/runs/caravel_lvs/tmp/merged_unpadded.lef $::env(TMP_DIR)/lvs.lef
file copy $script_dir/runs/caravel_lvs/tmp/lvs.def $::env(TMP_DIR)/lvs.def
file copy $script_dir/runs/caravel_lvs/tmp/lvs.v $::env(TMP_DIR)/lvs.v


set ::env(SYNTH_DEFINES) "TOP_ROUTING"
verilog_elaborate
#logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v

refernece documennt for TOP_ROUTING & USE_POWER_PINS

https://github.com/efabless/caravel/blob/e2f00e2770486737a083295514fa84b1423f0921/openlane/openlane.md