全端IC設計工程師養成計劃 (FullStack IC Designer Development)

The FullStack IC Designer Development will base on the Caravel SoC backbone. We target two ASIC tapeouts: Google Efabless SKY130 with open source EDA flow (Openlane & Efabless Caravel) and TSMC 0.18um with commercial EDA flow. We also plan to develop a validation system for the chips that come back as verification.

FullStack IC Designer Development

Caravel SoC

Caravel SoC is a platform for developing RISC-V CPU based hardware and software referred from Efabless Caravel “harness” SoC. You can develop and integrate custom design into this platform, then vefify their functionality with open source toolchain.

More detail can be found in Caravel's system specification.

Toolchain Prerequisites

• Ubuntu 20.04+
• RISC-V GCC Toolchains rv32i-4.0.0
• Icarus Verilog v10.3
• Icarus Verilog v12 + GTKWave Windows (option)
• GTKWave v3.3.103
• vtags-3.11
• GDBWave

Setup and Config

$ sudo apt update
$ sudo apt install iverilog gtkwave vim python gcc git -y
$ sudo wget -O /tmp/riscv32-unknown-elf.gcc-12.1.0.tar.gz https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv32i-4.0.0/riscv32-unknown-elf.gcc-12.1.0.tar.gz
$ sudo mkdir /opt/riscv
$ sudo tar -xzf /tmp/riscv32-unknown-elf.gcc-12.1.0.tar.gz -C /opt/riscv
$ sudo wget -O /tmp/vtags-3.11.tar.gz https://www.vim.org/scripts/download_script.php?src_id=28365
$ sudo tar -xzf /tmp/vtags-3.11.tar.gz -C /opt
$ python /opt/vtags-3.11/vim_glb_config.py
$ git clone https://github.com/bol-edu/caravel-soc ~/caravel-soc
$ cd ~/caravel-soc/
$ python /opt/vtags-3.11/vtags.py
$ cd ~/ && rm -rf ~/caravel-soc/
$ echo 'export PATH=$PATH:/opt/riscv/bin' >> ~/.bashrc
$ echo 'alias vtags="python /opt/vtags-3.11/vtags.py"' >> ~/.bashrc
$ echo 'source /opt/vtags-3.11/vtags_vim_api.vim' >> ~/.vimrc
$ source ~/.bashrc

validate your setup & config

Setup GDBWave - Post Simulation Debugging

$ sudo apt install make g++ zlib1g-dev gdb -y
$ git clone https://github.com/tomverbeure/gdbwave.git ~/gdbwave
$ pushd ~/gdbwave/src && make && popd

validate your setup gdbwave - post simulation debugging

Directory Structure

├── cvc-pdk                 # SKY130 OpenRAM SRAM Model
├── firmware                # Caravel System Firmware Libraries
├── rtl                     # Caravel RTL Designs
│   ├── header              # Headers
│   ├── soc                 # Boledu Revised SoC
│   ├── user                # User Project Designs
├── testbench               # Caravel Testbenches
│   ├── counter_la          # Counter with Logic Analyzer Interface
│   ├── counter_wb          # Counter with Wishbone Interface
│   └── gcd_la              # GCD with Logic Analyzer Interface
└── vip                     # Caravel Verification IP

Testbenches for Custom Designs

In each testbench subdirectory contains

1. Firmware driver (.c).
2. RTL testbench (.v).
3. Included RTL files (.list).
4. Run simulation script calls riscv32 command to compile c source to hex target and invokes iverilog && vvp to run RTL simulation.
5. GTKWave save file (.gtkw) saves selected signals from caravel-soc modules and corresponded testbench module.
6. Run debugging script produces gdb elf file, fst waveform file and starts gdbwave service (gdb remote target).
7. Make files and config file for gdb and gdbwave debugging.
8. Run clean script removes all simulation and debugging objects. The run debugging script use cases will be demonstrated in next section.

Git Clone Caravel SoC before Running Testbenches

$ git clone https://github.com/bol-edu/caravel-soc ~/caravel-soc

Counter with (LA) logic analyzer interface

• 32-bit LA input
• 32-bit LA output
• 16-bit mrpj_io as output

Files for simulation:

caravel-soc/testbench/counter_la/counter_la.c  
caravel-soc/testbench/counter_la/counter_la_tb.v  
caravel-soc/testbench/counter_la/include.rtl.list  
caravel-soc/testbench/counter_la/run_sim  
caravel-soc/testbench/counter_la/waveform.gtkw  

$ cd ~/caravel-soc/testbench/counter_la
$ ./run_sim
Reading counter_la.hex  
counter_la.hex loaded into memory  
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13  
VCD info: dumpfile counter_la.vcd opened for output.  
LA Test 1 started  
output:  
LA Test 2 passed  
$ gtkwave waveform.gtkw  

Counter with wishbone interface

• 32-bit wishbone input
• 32-bit wishbone output
• 16-bit mrpj_io as output

Files for simulation:

caravel-soc/testbench/counter_wb/counter_wb.c  
caravel-soc/testbench/counter_wb/counter_wb_tb.v  
caravel-soc/testbench/counter_wb/include.rtl.list  
caravel-soc/testbench/counter_wb/run_sim  
caravel-soc/testbench/counter_wb/waveform.gtkw  

$ cd ~/caravel-soc/testbench/counter_wb
$ ./run_sim
Reading counter_wb.hex  
counter_wb.hex loaded into memory  
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13  
VCD info: dumpfile counter_wb.vcd opened for output.  
Monitor: MPRJ-Logic WB Started  
Monitor: Mega-Project WB (RTL) Passed  
$ gtkwave waveform.gtkw  

GCD with (LA) logic analyzer interface

• 32-bit x 2 LA input
• 32-bit LA output
• 16-bit mrpj_io as output

Files for simulation:

caravel-soc/testbench/gcd_la/gcd_la.c  
caravel-soc/testbench/gcd_la/gcd_la_tb.v  
caravel-soc/testbench/gcd_la/include.rtl.list  
caravel-soc/testbench/gcd_la/run_sim  
caravel-soc/testbench/gcd_la/waveform.gtkw  

$ cd ~/caravel-soc/testbench/gcd_la
$ ./run_sim 
Reading gcd_la.hex  
gcd_la.hex loaded into memory  
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13  
VCD info: dumpfile gcd_la.vcd opened for output.  
LA Test seq_gcd(10312050, 29460792)=138 started  
LA Test seq_gcd(10312050, 29460792)=138 passed  
LA Test seq_gcd(1993627629, 1177417612)=7 started  
LA Test seq_gcd(1993627629, 1177417612)=7 passed  
LA Test seq_gcd(2097015289, 3812041926)=1 started  
LA Test seq_gcd(2097015289, 3812041926)=1 passed  
LA Test seq_gcd(1924134885, 3151131255)=135 started  
LA Test seq_gcd(1924134885, 3151131255)=135 passed  
LA Test seq_gcd(992211318, 512609597)=1 started  
LA Test seq_gcd(992211318, 512609597)=1 passed  
$ gtkwave waveform.gtkw

GDB + GDBWave Debugging for Custom Designs

Counter with (LA) logic analyzer interface

Files for debugging:

caravel-soc/testbench/counter_la/counter_la.c  
caravel-soc/testbench/counter_la/counter_la_tb.v  
caravel-soc/testbench/counter_la/gdb.make  
caravel-soc/testbench/counter_la/gdbwave.config  
caravel-soc/testbench/counter_la/gdbwave.make  
caravel-soc/testbench/counter_la/include.rtl.list  
caravel-soc/testbench/counter_la/run_debug  

execute run_debug to start gdbwave service and wait gdb connection

$ cd ~/caravel-soc/testbench/counter_la
$ ./run_debug

open another ssh terminal, change directory cd ~/caravel-soc/testbench/counter_la/gdb.debug and run make gdb, then execute gdb debug commands: (1) n (2) b main (3) c (4) b 122 (5) c (6) list (7) n (8) n (9) n (10) n (11) quit

counter_la.c (section)

gdbwave disconnection to gdb

Counter with wishbone interface

Files for debugging:

caravel-soc/testbench/counter_wb/counter_wb.c  
caravel-soc/testbench/counter_wb/counter_wb_tb.v  
caravel-soc/testbench/counter_wb/gdb.make  
caravel-soc/testbench/counter_wb/gdbwave.config  
caravel-soc/testbench/counter_wb/gdbwave.make  
caravel-soc/testbench/counter_wb/include.rtl.list  
caravel-soc/testbench/counter_wb/run_debug  

execute run_debug to start gdbwave service and wait gdb connection

$ cd ~/caravel-soc/testbench/counter_wb
$ ./run_debug

open another ssh terminal, change directory cd ~/caravel-soc/testbench/counter_wb/gdb.debug and run make gdb, then execute gdb debug commands: (1) n (2) b main (3) c (4) b 83 (5) c (6) list (7) n (8) n (9) n (10) n (11) quit

counter_wb.c (section)

gdbwave disconnection to gdb

GCD with (LA) logic analyzer interface

Files for debugging:

caravel-soc/testbench/gcd_la/gcd_la.c  
caravel-soc/testbench/gcd_la/gcd_la_tb.v  
caravel-soc/testbench/gcd_la/gdb.make  
caravel-soc/testbench/gcd_la/gdbwave.config  
caravel-soc/testbench/gcd_la/gdbwave.make  
caravel-soc/testbench/gcd_la/include.rtl.list  
caravel-soc/testbench/gcd_la/run_debug  

execute run_debug to start gdbwave service and wait gdb connection

$ cd ~/caravel-soc/testbench/gcd_la
$ ./run_debug

open another ssh terminal, change directory cd ~/caravel-soc/testbench/gcd_la/gdb.debug and run make gdb, then execute gdb debug commands: (1) n (2) b main (3) c (4) b 148 (5) c (6) list (7) p i (8) c (9) p i (10) c (11) p i (12) c
(13) p i (14) c (15) p i (16) n (17) n (18) n (19) n (20) quit

gcd_la.c (section)

gdbwave disconnection to gdb

Trace Verilog Code with Vim + vtags

We use vim + vtags to find signal trace source/drive target. First case, we demonstrate a signal mprj_io at gcd_la_tb module (gcd_la_tb.v) can be traced back to caravel module (cavavel.v) and chip_io module (chip_io.v).

$ cd ~/caravel-soc
$ vtags
$ vim vtags.db/

----------------Top Module List-------------
0 : counter_la_tb
1 : counter_wb_tb
2 : debug_regs
3 : gcd_la_tb
4 : sky130_sram_2kbyte_1rw1r_32x512_8
5 : wb_rw_test
Choise Top Module To Open (0-5):
3
"~/caravel-soc/testbench/gcd_la/gcd_la_tb.v" 275L, 12459C
Press ENTER or type command to continue
ENTER

＜Space＞＜Left＞ mprj_io at gcd_la_tb.v:29

vtags shows mprj_io connected to caravel module at gcd_la_tb.v:250

vim goto gcd_la_tb.v:250

＜Space＞＜Left＞ mprj_io at gcd_la_tb.v:250

found mprj_io at caravel.v:84

vtags can't fully parse dependencies of caravel.v, we use vim to find mprj_io connected to chip_io module at cavavel.v:345, then ＜Space＞＜Left＞ at mprj_io

mprj_io at chip_io.v:92

Another case, we demonstrate to find a signal clock drive target from gcd_la_tb module (gcd_la_tb.v) to caravel module (cavavel.v) and chip_io module (chip_io.v)

＜Space＞＜Right＞ at gcd_la_tb.v:21

vtags shows clock connected to caravel module at gcd_la_tb.v:248 (current line), then ＜Space＞＜Right＞ at clock

found clock at caravel.v:85, then ＜Space＞＜Right＞ at clock

found clock connected to chip_io module at caravel.v:346, then ＜Space＞＜Right＞ at clock

found clock at chip_io.v:62, then ＜Space＞＜Right＞ at clock

found clock connected to clock_core at chip_io.v:140, then ＜Space＞＜Right＞ at clock_core

found clock_core declaration at chip_io.v:72

Toolchain Reference Manuals

• Documentation for Icarus Verilog
• GTKWave 3.3 Wave Analyzer User's Guide
• vtags : verdi like, verilog code signal trace and show topo script
• Common GDB Commands
• GDBWave - A Post-Simulation Waveform-Based RISC-V GDB Debugging Server

Research Papers

• GHAZI: An Open-Source ASIC Implementation of RISC-V based SoC based SoC, 2022
• IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip, 2021