Driver asserting (or expecting in the case for Rx channel) Tlast twice ? Is this expected behavior and this is what it was intended ?

[samberhanu]

I have debug lines on the S2MM and MM2S interface. DMA is configured in DRE with 64-bit.
I am using the test application included in the example folder.

For a given N-bytes transfer, I am seeing 2*N bytes transfer. Every N-byte transfer, there is a TLAST for each transfer.
Ex: I tried transmitting 88 bytes (11 words as the stream interface is 64-bits). I saw at the 11th beat a TLAST and the same set of data that was transmitted initially being repeated on the MM2S tdata line but this time with another TLAST at the end.

In additon (and this actually is quite bothersome): at the very first initial transfer, that is very first usage of the driver after bootup, while doing MM2S transfer, 4 words leak out because s2mm_tready gets asserted (and the FIFO that i am using for loopback being fwft) even though there's no receive happening?

Can someone please advise what the exact behavior of this driver is when it comes to actual debug lines in the FPGA?
(i am experimenting on a zynq ultra+)

[samberhanu]

i've concluded the driver works, with only the caveat that if one expects normal AXIS transactions, that will not be the behavior you will see on your bdebug lines in the FPGA. The issue of the 4 beats is quite bothersome to me. I tried now with all types of bus width configurations but that also didn't resolve this issue.