From 919bbbee6ecf1fd507238c97c0ad425a35fa7b44 Mon Sep 17 00:00:00 2001 From: Jeff Charles Date: Wed, 29 Jan 2025 18:48:00 +0000 Subject: [PATCH 1/2] Winch: Add SIMD comparison instructions for x64 with AVX --- crates/wast-util/src/lib.rs | 12 +- tests/disas/winch/x64/f32x4_eq/const_avx.wat | 39 ++ tests/disas/winch/x64/f32x4_ge/const_avx.wat | 39 ++ tests/disas/winch/x64/f32x4_gt/const_avx.wat | 39 ++ tests/disas/winch/x64/f32x4_le/const_avx.wat | 39 ++ tests/disas/winch/x64/f32x4_lt/const_avx.wat | 39 ++ tests/disas/winch/x64/f32x4_ne/const_avx.wat | 39 ++ tests/disas/winch/x64/f64x2_eq/const_avx.wat | 46 ++ tests/disas/winch/x64/f64x2_ge/const_avx.wat | 46 ++ tests/disas/winch/x64/f64x2_gt/const_avx.wat | 46 ++ tests/disas/winch/x64/f64x2_le/const_avx.wat | 46 ++ tests/disas/winch/x64/f64x2_lt/const_avx.wat | 46 ++ tests/disas/winch/x64/f64x2_ne/const_avx.wat | 46 ++ tests/disas/winch/x64/i16x8_eq/const_avx.wat | 43 ++ .../disas/winch/x64/i16x8_ge_s/const_avx.wat | 42 ++ .../disas/winch/x64/i16x8_ge_u/const_avx.wat | 49 ++ .../disas/winch/x64/i16x8_gt_s/const_avx.wat | 43 ++ .../disas/winch/x64/i16x8_gt_u/const_avx.wat | 47 ++ .../disas/winch/x64/i16x8_le_s/const_avx.wat | 42 ++ .../disas/winch/x64/i16x8_le_u/const_avx.wat | 49 ++ .../disas/winch/x64/i16x8_lt_s/const_avx.wat | 43 ++ .../disas/winch/x64/i16x8_lt_u/const_avx.wat | 47 ++ tests/disas/winch/x64/i16x8_ne/const_avx.wat | 49 ++ tests/disas/winch/x64/i32x4_eq/const_avx.wat | 47 ++ .../disas/winch/x64/i32x4_ge_s/const_avx.wat | 53 +++ .../disas/winch/x64/i32x4_ge_u/const_avx.wat | 53 +++ .../disas/winch/x64/i32x4_gt_s/const_avx.wat | 47 ++ .../disas/winch/x64/i32x4_gt_u/const_avx.wat | 51 ++ .../disas/winch/x64/i32x4_le_s/const_avx.wat | 53 +++ .../disas/winch/x64/i32x4_le_u/const_avx.wat | 53 +++ .../disas/winch/x64/i32x4_lt_s/const_avx.wat | 47 ++ .../disas/winch/x64/i32x4_lt_u/const_avx.wat | 51 ++ tests/disas/winch/x64/i32x4_ne/const_avx.wat | 53 +++ tests/disas/winch/x64/i64x2_eq/const.wat | 46 ++ .../disas/winch/x64/i64x2_ge_s/const_avx.wat | 52 +++ .../disas/winch/x64/i64x2_gt_s/const_avx.wat | 46 ++ .../disas/winch/x64/i64x2_le_s/const_avx.wat | 52 +++ .../disas/winch/x64/i64x2_lt_s/const_avx.wat | 46 ++ tests/disas/winch/x64/i64x2_ne/const_avx.wat | 52 +++ tests/disas/winch/x64/i8x16_eq/const_avx.wat | 34 ++ .../disas/winch/x64/i8x16_ge_s/const_avx.wat | 42 ++ .../disas/winch/x64/i8x16_ge_u/const_avx.wat | 33 ++ .../disas/winch/x64/i8x16_gt_s/const_avx.wat | 34 ++ .../disas/winch/x64/i8x16_gt_u/const_avx.wat | 39 ++ .../disas/winch/x64/i8x16_le_s/const_avx.wat | 42 ++ .../disas/winch/x64/i8x16_le_u/const_avx.wat | 33 ++ .../disas/winch/x64/i8x16_lt_s/const_avx.wat | 34 ++ .../disas/winch/x64/i8x16_lt_u/const_avx.wat | 39 ++ tests/disas/winch/x64/i8x16_ne/const_avx.wat | 40 ++ tests/misc_testsuite/winch/_simd_splat.wast | 52 +-- winch/codegen/src/isa/aarch64/masm.rs | 62 ++- winch/codegen/src/isa/x64/asm.rs | 152 ++++++ winch/codegen/src/isa/x64/masm.rs | 218 ++++++++- winch/codegen/src/masm.rs | 122 +++++ winch/codegen/src/visitor.rs | 434 +++++++++++++++++- 55 files changed, 3151 insertions(+), 37 deletions(-) create mode 100644 tests/disas/winch/x64/f32x4_eq/const_avx.wat create mode 100644 tests/disas/winch/x64/f32x4_ge/const_avx.wat create mode 100644 tests/disas/winch/x64/f32x4_gt/const_avx.wat create mode 100644 tests/disas/winch/x64/f32x4_le/const_avx.wat create mode 100644 tests/disas/winch/x64/f32x4_lt/const_avx.wat create mode 100644 tests/disas/winch/x64/f32x4_ne/const_avx.wat create mode 100644 tests/disas/winch/x64/f64x2_eq/const_avx.wat create mode 100644 tests/disas/winch/x64/f64x2_ge/const_avx.wat create mode 100644 tests/disas/winch/x64/f64x2_gt/const_avx.wat create mode 100644 tests/disas/winch/x64/f64x2_le/const_avx.wat create mode 100644 tests/disas/winch/x64/f64x2_lt/const_avx.wat create mode 100644 tests/disas/winch/x64/f64x2_ne/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_eq/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_ge_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_ge_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_gt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_gt_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_le_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_le_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_lt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_lt_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i16x8_ne/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_eq/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_ge_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_ge_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_gt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_gt_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_le_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_le_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_lt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_lt_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i32x4_ne/const_avx.wat create mode 100644 tests/disas/winch/x64/i64x2_eq/const.wat create mode 100644 tests/disas/winch/x64/i64x2_ge_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i64x2_gt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i64x2_le_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i64x2_lt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i64x2_ne/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_eq/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_ge_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_ge_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_gt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_gt_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_le_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_le_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_lt_s/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_lt_u/const_avx.wat create mode 100644 tests/disas/winch/x64/i8x16_ne/const_avx.wat diff --git a/crates/wast-util/src/lib.rs b/crates/wast-util/src/lib.rs index d32298ff238a..73773ea455b4 100644 --- a/crates/wast-util/src/lib.rs +++ b/crates/wast-util/src/lib.rs @@ -433,24 +433,20 @@ impl WastTest { "spec_testsuite/simd_conversions.wast", "spec_testsuite/simd_f32x4.wast", "spec_testsuite/simd_f32x4_arith.wast", - "spec_testsuite/simd_f32x4_cmp.wast", "spec_testsuite/simd_f32x4_pmin_pmax.wast", "spec_testsuite/simd_f32x4_rounding.wast", "spec_testsuite/simd_f64x2.wast", "spec_testsuite/simd_f64x2_arith.wast", - "spec_testsuite/simd_f64x2_cmp.wast", "spec_testsuite/simd_f64x2_pmin_pmax.wast", "spec_testsuite/simd_f64x2_rounding.wast", "spec_testsuite/simd_i16x8_arith.wast", "spec_testsuite/simd_i16x8_arith2.wast", - "spec_testsuite/simd_i16x8_cmp.wast", "spec_testsuite/simd_i16x8_extadd_pairwise_i8x16.wast", "spec_testsuite/simd_i16x8_extmul_i8x16.wast", "spec_testsuite/simd_i16x8_q15mulr_sat_s.wast", "spec_testsuite/simd_i16x8_sat_arith.wast", "spec_testsuite/simd_i32x4_arith.wast", "spec_testsuite/simd_i32x4_arith2.wast", - "spec_testsuite/simd_i32x4_cmp.wast", "spec_testsuite/simd_i32x4_dot_i16x8.wast", "spec_testsuite/simd_i32x4_extadd_pairwise_i16x8.wast", "spec_testsuite/simd_i32x4_extmul_i16x8.wast", @@ -458,11 +454,9 @@ impl WastTest { "spec_testsuite/simd_i32x4_trunc_sat_f64x2.wast", "spec_testsuite/simd_i64x2_arith.wast", "spec_testsuite/simd_i64x2_arith2.wast", - "spec_testsuite/simd_i64x2_cmp.wast", "spec_testsuite/simd_i64x2_extmul_i32x4.wast", "spec_testsuite/simd_i8x16_arith.wast", "spec_testsuite/simd_i8x16_arith2.wast", - "spec_testsuite/simd_i8x16_cmp.wast", "spec_testsuite/simd_i8x16_sat_arith.wast", "spec_testsuite/simd_int_to_int_extend.wast", "spec_testsuite/simd_lane.wast", @@ -484,6 +478,12 @@ impl WastTest { "misc_testsuite/winch/_simd_lane.wast", "misc_testsuite/winch/_simd_splat.wast", "spec_testsuite/simd_align.wast", + "spec_testsuite/simd_f32x4_cmp.wast", + "spec_testsuite/simd_f64x2_cmp.wast", + "spec_testsuite/simd_i16x8_cmp.wast", + "spec_testsuite/simd_i32x4_cmp.wast", + "spec_testsuite/simd_i64x2_cmp.wast", + "spec_testsuite/simd_i8x16_cmp.wast", "spec_testsuite/simd_load_extend.wast", "spec_testsuite/simd_load_splat.wast", "spec_testsuite/simd_store16_lane.wast", diff --git a/tests/disas/winch/x64/f32x4_eq/const_avx.wat b/tests/disas/winch/x64/f32x4_eq/const_avx.wat new file mode 100644 index 000000000000..6571b42feafd --- /dev/null +++ b/tests/disas/winch/x64/f32x4_eq/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f32x4.eq (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpeqps %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, 0x3f(%rax) +;; 5b: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 69: addb %al, 0x3f(%rax) diff --git a/tests/disas/winch/x64/f32x4_ge/const_avx.wat b/tests/disas/winch/x64/f32x4_ge/const_avx.wat new file mode 100644 index 000000000000..619e943a9a48 --- /dev/null +++ b/tests/disas/winch/x64/f32x4_ge/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f32x4.ge (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpleps %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, 0x3f(%rax) +;; 5b: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 69: addb %al, 0x3f(%rax) diff --git a/tests/disas/winch/x64/f32x4_gt/const_avx.wat b/tests/disas/winch/x64/f32x4_gt/const_avx.wat new file mode 100644 index 000000000000..8587c73c760f --- /dev/null +++ b/tests/disas/winch/x64/f32x4_gt/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f32x4.gt (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpltps %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, 0x3f(%rax) +;; 5b: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 69: addb %al, 0x3f(%rax) diff --git a/tests/disas/winch/x64/f32x4_le/const_avx.wat b/tests/disas/winch/x64/f32x4_le/const_avx.wat new file mode 100644 index 000000000000..7f0a0099197c --- /dev/null +++ b/tests/disas/winch/x64/f32x4_le/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f32x4.le (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpleps %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, 0x3f(%rax) +;; 5b: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 69: addb %al, 0x3f(%rax) diff --git a/tests/disas/winch/x64/f32x4_lt/const_avx.wat b/tests/disas/winch/x64/f32x4_lt/const_avx.wat new file mode 100644 index 000000000000..83837742f09f --- /dev/null +++ b/tests/disas/winch/x64/f32x4_lt/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f32x4.lt (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpltps %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, 0x3f(%rax) +;; 5b: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 69: addb %al, 0x3f(%rax) diff --git a/tests/disas/winch/x64/f32x4_ne/const_avx.wat b/tests/disas/winch/x64/f32x4_ne/const_avx.wat new file mode 100644 index 000000000000..3f82371a2ba9 --- /dev/null +++ b/tests/disas/winch/x64/f32x4_ne/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f32x4.ne (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpneqps %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, 0x3f(%rax) +;; 5b: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 69: addb %al, 0x3f(%rax) diff --git a/tests/disas/winch/x64/f64x2_eq/const_avx.wat b/tests/disas/winch/x64/f64x2_eq/const_avx.wat new file mode 100644 index 000000000000..ca9af2b8367d --- /dev/null +++ b/tests/disas/winch/x64/f64x2_eq/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f64x2.eq (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpeqpd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/f64x2_ge/const_avx.wat b/tests/disas/winch/x64/f64x2_ge/const_avx.wat new file mode 100644 index 000000000000..540c3c24f4cd --- /dev/null +++ b/tests/disas/winch/x64/f64x2_ge/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f64x2.ge (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmplepd %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/f64x2_gt/const_avx.wat b/tests/disas/winch/x64/f64x2_gt/const_avx.wat new file mode 100644 index 000000000000..7d0f1c99848b --- /dev/null +++ b/tests/disas/winch/x64/f64x2_gt/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f64x2.gt (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpltpd %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/f64x2_le/const_avx.wat b/tests/disas/winch/x64/f64x2_le/const_avx.wat new file mode 100644 index 000000000000..e2b9c1bb9fc8 --- /dev/null +++ b/tests/disas/winch/x64/f64x2_le/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f64x2.le (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmplepd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/f64x2_lt/const_avx.wat b/tests/disas/winch/x64/f64x2_lt/const_avx.wat new file mode 100644 index 000000000000..b09a65230f14 --- /dev/null +++ b/tests/disas/winch/x64/f64x2_lt/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f64x2.lt (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpltpd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/f64x2_ne/const_avx.wat b/tests/disas/winch/x64/f64x2_ne/const_avx.wat new file mode 100644 index 000000000000..5d6ae20d28f4 --- /dev/null +++ b/tests/disas/winch/x64/f64x2_ne/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (f64x2.ne (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vcmpneqpd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_eq/const_avx.wat b/tests/disas/winch/x64/i16x8_eq/const_avx.wat new file mode 100644 index 000000000000..673a6052fae3 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_eq/const_avx.wat @@ -0,0 +1,43 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.eq (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rax) +;; 52: addl %eax, (%rax) +;; 54: addb (%rax), %al +;; 56: addl (%rax), %eax +;; 58: addb $0, %al +;; 5a: addl $0x7000600, %eax +;; 5f: addb %al, (%rdi) +;; 61: addb %al, (%rsi) +;; 63: addb %al, 0x3000400(%rip) +;; 69: addb %al, (%rdx) +;; 6b: addb %al, (%rcx) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_ge_s/const_avx.wat b/tests/disas/winch/x64/i16x8_ge_s/const_avx.wat new file mode 100644 index 000000000000..15ed377463e2 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_ge_s/const_avx.wat @@ -0,0 +1,42 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.ge_s (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4e +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpmaxsw %xmm0, %xmm1, %xmm0 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4e: ud2 +;; 50: addb %al, (%rax) +;; 52: addl %eax, (%rax) +;; 54: addb (%rax), %al +;; 56: addl (%rax), %eax +;; 58: addb $0, %al +;; 5a: addl $0x7000600, %eax +;; 5f: addb %al, (%rdi) +;; 61: addb %al, (%rsi) +;; 63: addb %al, 0x3000400(%rip) +;; 69: addb %al, (%rdx) +;; 6b: addb %al, (%rcx) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_ge_u/const_avx.wat b/tests/disas/winch/x64/i16x8_ge_u/const_avx.wat new file mode 100644 index 000000000000..0d24a8184169 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_ge_u/const_avx.wat @@ -0,0 +1,49 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.ge_u (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpmaxuw %xmm0, %xmm1, %xmm0 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rcx) +;; 63: addb %al, (%rdx) +;; 65: addb %al, (%rbx) +;; 67: addb %al, (%rax, %rax) +;; 6a: addl $0x7000600, %eax +;; 6f: addb %al, (%rdi) +;; 71: addb %al, (%rsi) +;; 73: addb %al, 0x3000400(%rip) +;; 79: addb %al, (%rdx) +;; 7b: addb %al, (%rcx) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_gt_s/const_avx.wat b/tests/disas/winch/x64/i16x8_gt_s/const_avx.wat new file mode 100644 index 000000000000..5d63a8582ad8 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_gt_s/const_avx.wat @@ -0,0 +1,43 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.gt_s (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtw %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rax) +;; 52: addl %eax, (%rax) +;; 54: addb (%rax), %al +;; 56: addl (%rax), %eax +;; 58: addb $0, %al +;; 5a: addl $0x7000600, %eax +;; 5f: addb %al, (%rdi) +;; 61: addb %al, (%rsi) +;; 63: addb %al, 0x3000400(%rip) +;; 69: addb %al, (%rdx) +;; 6b: addb %al, (%rcx) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_gt_u/const_avx.wat b/tests/disas/winch/x64/i16x8_gt_u/const_avx.wat new file mode 100644 index 000000000000..5bfbf14a25a0 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_gt_u/const_avx.wat @@ -0,0 +1,47 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.gt_u (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x57 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpmaxuw %xmm0, %xmm1, %xmm1 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; vpcmpeqw %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 57: ud2 +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rcx) +;; 63: addb %al, (%rdx) +;; 65: addb %al, (%rbx) +;; 67: addb %al, (%rax, %rax) +;; 6a: addl $0x7000600, %eax +;; 6f: addb %al, (%rdi) +;; 71: addb %al, (%rsi) +;; 73: addb %al, 0x3000400(%rip) +;; 79: addb %al, (%rdx) +;; 7b: addb %al, (%rcx) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_le_s/const_avx.wat b/tests/disas/winch/x64/i16x8_le_s/const_avx.wat new file mode 100644 index 000000000000..c49217a0a8e6 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_le_s/const_avx.wat @@ -0,0 +1,42 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.le_s (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4e +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpminsw %xmm0, %xmm1, %xmm0 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4e: ud2 +;; 50: addb %al, (%rax) +;; 52: addl %eax, (%rax) +;; 54: addb (%rax), %al +;; 56: addl (%rax), %eax +;; 58: addb $0, %al +;; 5a: addl $0x7000600, %eax +;; 5f: addb %al, (%rdi) +;; 61: addb %al, (%rsi) +;; 63: addb %al, 0x3000400(%rip) +;; 69: addb %al, (%rdx) +;; 6b: addb %al, (%rcx) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_le_u/const_avx.wat b/tests/disas/winch/x64/i16x8_le_u/const_avx.wat new file mode 100644 index 000000000000..98c740418381 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_le_u/const_avx.wat @@ -0,0 +1,49 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.le_u (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpminuw %xmm0, %xmm1, %xmm0 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rcx) +;; 63: addb %al, (%rdx) +;; 65: addb %al, (%rbx) +;; 67: addb %al, (%rax, %rax) +;; 6a: addl $0x7000600, %eax +;; 6f: addb %al, (%rdi) +;; 71: addb %al, (%rsi) +;; 73: addb %al, 0x3000400(%rip) +;; 79: addb %al, (%rdx) +;; 7b: addb %al, (%rcx) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_lt_s/const_avx.wat b/tests/disas/winch/x64/i16x8_lt_s/const_avx.wat new file mode 100644 index 000000000000..c09a8a0fc150 --- /dev/null +++ b/tests/disas/winch/x64/i16x8_lt_s/const_avx.wat @@ -0,0 +1,43 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.lt_s (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtw %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rax) +;; 52: addl %eax, (%rax) +;; 54: addb (%rax), %al +;; 56: addl (%rax), %eax +;; 58: addb $0, %al +;; 5a: addl $0x7000600, %eax +;; 5f: addb %al, (%rdi) +;; 61: addb %al, (%rsi) +;; 63: addb %al, 0x3000400(%rip) +;; 69: addb %al, (%rdx) +;; 6b: addb %al, (%rcx) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_lt_u/const_avx.wat b/tests/disas/winch/x64/i16x8_lt_u/const_avx.wat new file mode 100644 index 000000000000..532ad189833e --- /dev/null +++ b/tests/disas/winch/x64/i16x8_lt_u/const_avx.wat @@ -0,0 +1,47 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.lt_u (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x57 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpminuw %xmm0, %xmm1, %xmm1 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; vpcmpeqw %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 57: ud2 +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rcx) +;; 63: addb %al, (%rdx) +;; 65: addb %al, (%rbx) +;; 67: addb %al, (%rax, %rax) +;; 6a: addl $0x7000600, %eax +;; 6f: addb %al, (%rdi) +;; 71: addb %al, (%rsi) +;; 73: addb %al, 0x3000400(%rip) +;; 79: addb %al, (%rdx) +;; 7b: addb %al, (%rcx) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i16x8_ne/const_avx.wat b/tests/disas/winch/x64/i16x8_ne/const_avx.wat new file mode 100644 index 000000000000..ecc35071750f --- /dev/null +++ b/tests/disas/winch/x64/i16x8_ne/const_avx.wat @@ -0,0 +1,49 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i16x8.ne (v128.const i16x8 7 6 5 4 3 2 1 0) (v128.const i16x8 0 1 2 3 4 5 6 7)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x52 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpcmpeqw %xmm0, %xmm1, %xmm1 +;; vpcmpeqw %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 52: ud2 +;; 54: addb %al, (%rax) +;; 56: addb %al, (%rax) +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rax) +;; 62: addl %eax, (%rax) +;; 64: addb (%rax), %al +;; 66: addl (%rax), %eax +;; 68: addb $0, %al +;; 6a: addl $0x7000600, %eax +;; 6f: addb %al, (%rdi) +;; 71: addb %al, (%rsi) +;; 73: addb %al, 0x3000400(%rip) +;; 79: addb %al, (%rdx) +;; 7b: addb %al, (%rcx) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_eq/const_avx.wat b/tests/disas/winch/x64/i32x4_eq/const_avx.wat new file mode 100644 index 000000000000..4b79385758bc --- /dev/null +++ b/tests/disas/winch/x64/i32x4_eq/const_avx.wat @@ -0,0 +1,47 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.eq (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rax) +;; 52: addb %al, (%rax) +;; 54: addl %eax, (%rax) +;; 56: addb %al, (%rax) +;; 58: addb (%rax), %al +;; 5a: addb %al, (%rax) +;; 5c: addl (%rax), %eax +;; 5e: addb %al, (%rax) +;; 60: addl (%rax), %eax +;; 62: addb %al, (%rax) +;; 64: addb (%rax), %al +;; 66: addb %al, (%rax) +;; 68: addl %eax, (%rax) +;; 6a: addb %al, (%rax) +;; 6c: addb %al, (%rax) +;; 6e: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_ge_s/const_avx.wat b/tests/disas/winch/x64/i32x4_ge_s/const_avx.wat new file mode 100644 index 000000000000..181e69a4a52a --- /dev/null +++ b/tests/disas/winch/x64/i32x4_ge_s/const_avx.wat @@ -0,0 +1,53 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.ge_s (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpmaxsd %xmm0, %xmm1, %xmm0 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rcx) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rdx) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rbx) +;; 6d: addb %al, (%rax) +;; 6f: addb %al, (%rbx) +;; 71: addb %al, (%rax) +;; 73: addb %al, (%rdx) +;; 75: addb %al, (%rax) +;; 77: addb %al, (%rcx) +;; 79: addb %al, (%rax) +;; 7b: addb %al, (%rax) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_ge_u/const_avx.wat b/tests/disas/winch/x64/i32x4_ge_u/const_avx.wat new file mode 100644 index 000000000000..57bb34d0a969 --- /dev/null +++ b/tests/disas/winch/x64/i32x4_ge_u/const_avx.wat @@ -0,0 +1,53 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.ge_u (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpmaxud %xmm0, %xmm1, %xmm0 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rcx) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rdx) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rbx) +;; 6d: addb %al, (%rax) +;; 6f: addb %al, (%rbx) +;; 71: addb %al, (%rax) +;; 73: addb %al, (%rdx) +;; 75: addb %al, (%rax) +;; 77: addb %al, (%rcx) +;; 79: addb %al, (%rax) +;; 7b: addb %al, (%rax) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_gt_s/const_avx.wat b/tests/disas/winch/x64/i32x4_gt_s/const_avx.wat new file mode 100644 index 000000000000..395f09982296 --- /dev/null +++ b/tests/disas/winch/x64/i32x4_gt_s/const_avx.wat @@ -0,0 +1,47 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.gt_s (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rax) +;; 52: addb %al, (%rax) +;; 54: addl %eax, (%rax) +;; 56: addb %al, (%rax) +;; 58: addb (%rax), %al +;; 5a: addb %al, (%rax) +;; 5c: addl (%rax), %eax +;; 5e: addb %al, (%rax) +;; 60: addl (%rax), %eax +;; 62: addb %al, (%rax) +;; 64: addb (%rax), %al +;; 66: addb %al, (%rax) +;; 68: addl %eax, (%rax) +;; 6a: addb %al, (%rax) +;; 6c: addb %al, (%rax) +;; 6e: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_gt_u/const_avx.wat b/tests/disas/winch/x64/i32x4_gt_u/const_avx.wat new file mode 100644 index 000000000000..3cf7a65ed0d5 --- /dev/null +++ b/tests/disas/winch/x64/i32x4_gt_u/const_avx.wat @@ -0,0 +1,51 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.gt_u (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x57 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpmaxud %xmm0, %xmm1, %xmm1 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; vpcmpeqd %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 57: ud2 +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rcx) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rdx) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rbx) +;; 6d: addb %al, (%rax) +;; 6f: addb %al, (%rbx) +;; 71: addb %al, (%rax) +;; 73: addb %al, (%rdx) +;; 75: addb %al, (%rax) +;; 77: addb %al, (%rcx) +;; 79: addb %al, (%rax) +;; 7b: addb %al, (%rax) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_le_s/const_avx.wat b/tests/disas/winch/x64/i32x4_le_s/const_avx.wat new file mode 100644 index 000000000000..30d1c2a6ce79 --- /dev/null +++ b/tests/disas/winch/x64/i32x4_le_s/const_avx.wat @@ -0,0 +1,53 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.le_s (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpminsd %xmm0, %xmm1, %xmm0 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rcx) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rdx) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rbx) +;; 6d: addb %al, (%rax) +;; 6f: addb %al, (%rbx) +;; 71: addb %al, (%rax) +;; 73: addb %al, (%rdx) +;; 75: addb %al, (%rax) +;; 77: addb %al, (%rcx) +;; 79: addb %al, (%rax) +;; 7b: addb %al, (%rax) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_le_u/const_avx.wat b/tests/disas/winch/x64/i32x4_le_u/const_avx.wat new file mode 100644 index 000000000000..5a352c3ab62c --- /dev/null +++ b/tests/disas/winch/x64/i32x4_le_u/const_avx.wat @@ -0,0 +1,53 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.le_u (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpminud %xmm0, %xmm1, %xmm0 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rcx) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rdx) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rbx) +;; 6d: addb %al, (%rax) +;; 6f: addb %al, (%rbx) +;; 71: addb %al, (%rax) +;; 73: addb %al, (%rdx) +;; 75: addb %al, (%rax) +;; 77: addb %al, (%rcx) +;; 79: addb %al, (%rax) +;; 7b: addb %al, (%rax) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_lt_s/const_avx.wat b/tests/disas/winch/x64/i32x4_lt_s/const_avx.wat new file mode 100644 index 000000000000..c414c7b4ecbe --- /dev/null +++ b/tests/disas/winch/x64/i32x4_lt_s/const_avx.wat @@ -0,0 +1,47 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.lt_s (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtd %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rax) +;; 52: addb %al, (%rax) +;; 54: addl %eax, (%rax) +;; 56: addb %al, (%rax) +;; 58: addb (%rax), %al +;; 5a: addb %al, (%rax) +;; 5c: addl (%rax), %eax +;; 5e: addb %al, (%rax) +;; 60: addl (%rax), %eax +;; 62: addb %al, (%rax) +;; 64: addb (%rax), %al +;; 66: addb %al, (%rax) +;; 68: addl %eax, (%rax) +;; 6a: addb %al, (%rax) +;; 6c: addb %al, (%rax) +;; 6e: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_lt_u/const_avx.wat b/tests/disas/winch/x64/i32x4_lt_u/const_avx.wat new file mode 100644 index 000000000000..fe17601c29ac --- /dev/null +++ b/tests/disas/winch/x64/i32x4_lt_u/const_avx.wat @@ -0,0 +1,51 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.lt_u (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x57 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpminud %xmm0, %xmm1, %xmm1 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; vpcmpeqd %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 57: ud2 +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rcx) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rdx) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rbx) +;; 6d: addb %al, (%rax) +;; 6f: addb %al, (%rbx) +;; 71: addb %al, (%rax) +;; 73: addb %al, (%rdx) +;; 75: addb %al, (%rax) +;; 77: addb %al, (%rcx) +;; 79: addb %al, (%rax) +;; 7b: addb %al, (%rax) +;; 7d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i32x4_ne/const_avx.wat b/tests/disas/winch/x64/i32x4_ne/const_avx.wat new file mode 100644 index 000000000000..712aaf13243d --- /dev/null +++ b/tests/disas/winch/x64/i32x4_ne/const_avx.wat @@ -0,0 +1,53 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i32x4.ne (v128.const i32x4 3 2 1 0) (v128.const i32x4 0 1 2 3)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x52 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpcmpeqd %xmm0, %xmm1, %xmm1 +;; vpcmpeqd %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 52: ud2 +;; 54: addb %al, (%rax) +;; 56: addb %al, (%rax) +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 64: addl %eax, (%rax) +;; 66: addb %al, (%rax) +;; 68: addb (%rax), %al +;; 6a: addb %al, (%rax) +;; 6c: addl (%rax), %eax +;; 6e: addb %al, (%rax) +;; 70: addl (%rax), %eax +;; 72: addb %al, (%rax) +;; 74: addb (%rax), %al +;; 76: addb %al, (%rax) +;; 78: addl %eax, (%rax) +;; 7a: addb %al, (%rax) +;; 7c: addb %al, (%rax) +;; 7e: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i64x2_eq/const.wat b/tests/disas/winch/x64/i64x2_eq/const.wat new file mode 100644 index 000000000000..4c9fceb9900d --- /dev/null +++ b/tests/disas/winch/x64/i64x2_eq/const.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i64x2.eq (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpeqq %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i64x2_ge_s/const_avx.wat b/tests/disas/winch/x64/i64x2_ge_s/const_avx.wat new file mode 100644 index 000000000000..312a0a4c788f --- /dev/null +++ b/tests/disas/winch/x64/i64x2_ge_s/const_avx.wat @@ -0,0 +1,52 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i64x2.ge_s (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x54 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpcmpgtq %xmm1, %xmm0, %xmm0 +;; vpcmpeqq %xmm1, %xmm1, %xmm1 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 54: ud2 +;; 56: addb %al, (%rax) +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 64: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 68: addl %eax, (%rax) +;; 6a: addb %al, (%rax) +;; 6c: addb %al, (%rax) +;; 6e: addb %al, (%rax) +;; 70: addl %eax, (%rax) +;; 72: addb %al, (%rax) +;; 74: addb %al, (%rax) +;; 76: addb %al, (%rax) +;; 78: addb %al, (%rax) +;; 7a: addb %al, (%rax) +;; 7c: addb %al, (%rax) +;; 7e: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i64x2_gt_s/const_avx.wat b/tests/disas/winch/x64/i64x2_gt_s/const_avx.wat new file mode 100644 index 000000000000..b7316db48ddc --- /dev/null +++ b/tests/disas/winch/x64/i64x2_gt_s/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i64x2.gt_s (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtq %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i64x2_le_s/const_avx.wat b/tests/disas/winch/x64/i64x2_le_s/const_avx.wat new file mode 100644 index 000000000000..aecc1dddda70 --- /dev/null +++ b/tests/disas/winch/x64/i64x2_le_s/const_avx.wat @@ -0,0 +1,52 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i64x2.le_s (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x54 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpcmpgtq %xmm0, %xmm1, %xmm1 +;; vpcmpeqq %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 54: ud2 +;; 56: addb %al, (%rax) +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 64: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 68: addl %eax, (%rax) +;; 6a: addb %al, (%rax) +;; 6c: addb %al, (%rax) +;; 6e: addb %al, (%rax) +;; 70: addl %eax, (%rax) +;; 72: addb %al, (%rax) +;; 74: addb %al, (%rax) +;; 76: addb %al, (%rax) +;; 78: addb %al, (%rax) +;; 7a: addb %al, (%rax) +;; 7c: addb %al, (%rax) +;; 7e: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i64x2_lt_s/const_avx.wat b/tests/disas/winch/x64/i64x2_lt_s/const_avx.wat new file mode 100644 index 000000000000..70c06e2e39be --- /dev/null +++ b/tests/disas/winch/x64/i64x2_lt_s/const_avx.wat @@ -0,0 +1,46 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i64x2.lt_s (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4b +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtq %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4b: ud2 +;; 4d: addb %al, (%rax) +;; 4f: addb %al, (%rax) +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rcx) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rcx) +;; 61: addb %al, (%rax) +;; 63: addb %al, (%rax) +;; 65: addb %al, (%rax) +;; 67: addb %al, (%rax) +;; 69: addb %al, (%rax) +;; 6b: addb %al, (%rax) +;; 6d: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i64x2_ne/const_avx.wat b/tests/disas/winch/x64/i64x2_ne/const_avx.wat new file mode 100644 index 000000000000..a4041fa52ba7 --- /dev/null +++ b/tests/disas/winch/x64/i64x2_ne/const_avx.wat @@ -0,0 +1,52 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i64x2.ne (v128.const i64x2 1 0) (v128.const i64x2 0 1)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x54 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpcmpeqq %xmm0, %xmm1, %xmm1 +;; vpcmpeqq %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 54: ud2 +;; 56: addb %al, (%rax) +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rax) +;; 62: addb %al, (%rax) +;; 64: addb %al, (%rax) +;; 66: addb %al, (%rax) +;; 68: addl %eax, (%rax) +;; 6a: addb %al, (%rax) +;; 6c: addb %al, (%rax) +;; 6e: addb %al, (%rax) +;; 70: addl %eax, (%rax) +;; 72: addb %al, (%rax) +;; 74: addb %al, (%rax) +;; 76: addb %al, (%rax) +;; 78: addb %al, (%rax) +;; 7a: addb %al, (%rax) +;; 7c: addb %al, (%rax) +;; 7e: addb %al, (%rax) diff --git a/tests/disas/winch/x64/i8x16_eq/const_avx.wat b/tests/disas/winch/x64/i8x16_eq/const_avx.wat new file mode 100644 index 000000000000..e03e4d21d7a7 --- /dev/null +++ b/tests/disas/winch/x64/i8x16_eq/const_avx.wat @@ -0,0 +1,34 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.eq (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rcx) +;; 52: addb (%rbx), %al +;; 54: addb $5, %al diff --git a/tests/disas/winch/x64/i8x16_ge_s/const_avx.wat b/tests/disas/winch/x64/i8x16_ge_s/const_avx.wat new file mode 100644 index 000000000000..53452432218f --- /dev/null +++ b/tests/disas/winch/x64/i8x16_ge_s/const_avx.wat @@ -0,0 +1,42 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.ge_s (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpmaxsb %xmm0, %xmm1, %xmm0 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addl %eax, (%rdx) +;; 63: addl 0x9080706(, %rax), %eax +;; 6a: orb (%rbx), %cl +;; 6c: orb $0xd, %al diff --git a/tests/disas/winch/x64/i8x16_ge_u/const_avx.wat b/tests/disas/winch/x64/i8x16_ge_u/const_avx.wat new file mode 100644 index 000000000000..0e93f0bf16c5 --- /dev/null +++ b/tests/disas/winch/x64/i8x16_ge_u/const_avx.wat @@ -0,0 +1,33 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.ge_u (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4e +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpmaxub %xmm0, %xmm1, %xmm0 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4e: ud2 +;; 50: addb %al, (%rcx) +;; 52: addb (%rbx), %al +;; 54: addb $5, %al diff --git a/tests/disas/winch/x64/i8x16_gt_s/const_avx.wat b/tests/disas/winch/x64/i8x16_gt_s/const_avx.wat new file mode 100644 index 000000000000..56eb70bc5444 --- /dev/null +++ b/tests/disas/winch/x64/i8x16_gt_s/const_avx.wat @@ -0,0 +1,34 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.gt_s (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtb %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rcx) +;; 52: addb (%rbx), %al +;; 54: addb $5, %al diff --git a/tests/disas/winch/x64/i8x16_gt_u/const_avx.wat b/tests/disas/winch/x64/i8x16_gt_u/const_avx.wat new file mode 100644 index 000000000000..f5ea29ef2060 --- /dev/null +++ b/tests/disas/winch/x64/i8x16_gt_u/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.gt_u (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x56 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpmaxub %xmm0, %xmm1, %xmm1 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; vpcmpeqb %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 56: ud2 +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rcx) +;; 62: addb (%rbx), %al +;; 64: addb $5, %al diff --git a/tests/disas/winch/x64/i8x16_le_s/const_avx.wat b/tests/disas/winch/x64/i8x16_le_s/const_avx.wat new file mode 100644 index 000000000000..befc755d7150 --- /dev/null +++ b/tests/disas/winch/x64/i8x16_le_s/const_avx.wat @@ -0,0 +1,42 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.le_s (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4f +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpminsb %xmm0, %xmm1, %xmm0 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4f: ud2 +;; 51: addb %al, (%rax) +;; 53: addb %al, (%rax) +;; 55: addb %al, (%rax) +;; 57: addb %al, (%rax) +;; 59: addb %al, (%rax) +;; 5b: addb %al, (%rax) +;; 5d: addb %al, (%rax) +;; 5f: addb %al, (%rax) +;; 61: addl %eax, (%rdx) +;; 63: addl 0x9080706(, %rax), %eax +;; 6a: orb (%rbx), %cl +;; 6c: orb $0xd, %al diff --git a/tests/disas/winch/x64/i8x16_le_u/const_avx.wat b/tests/disas/winch/x64/i8x16_le_u/const_avx.wat new file mode 100644 index 000000000000..070c0f15d038 --- /dev/null +++ b/tests/disas/winch/x64/i8x16_le_u/const_avx.wat @@ -0,0 +1,33 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.le_u (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4e +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpminub %xmm0, %xmm1, %xmm0 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4e: ud2 +;; 50: addb %al, (%rcx) +;; 52: addb (%rbx), %al +;; 54: addb $5, %al diff --git a/tests/disas/winch/x64/i8x16_lt_s/const_avx.wat b/tests/disas/winch/x64/i8x16_lt_s/const_avx.wat new file mode 100644 index 000000000000..99e987d7473c --- /dev/null +++ b/tests/disas/winch/x64/i8x16_lt_s/const_avx.wat @@ -0,0 +1,34 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.lt_s (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x4a +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x1c(%rip), %xmm0 +;; movdqu 0x24(%rip), %xmm1 +;; vpcmpgtb %xmm1, %xmm0, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 4a: ud2 +;; 4c: addb %al, (%rax) +;; 4e: addb %al, (%rax) +;; 50: addb %al, (%rcx) +;; 52: addb (%rbx), %al +;; 54: addb $5, %al diff --git a/tests/disas/winch/x64/i8x16_lt_u/const_avx.wat b/tests/disas/winch/x64/i8x16_lt_u/const_avx.wat new file mode 100644 index 000000000000..0303ece10609 --- /dev/null +++ b/tests/disas/winch/x64/i8x16_lt_u/const_avx.wat @@ -0,0 +1,39 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.lt_u (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x56 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpminub %xmm0, %xmm1, %xmm1 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; vpcmpeqb %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 56: ud2 +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rcx) +;; 62: addb (%rbx), %al +;; 64: addb $5, %al diff --git a/tests/disas/winch/x64/i8x16_ne/const_avx.wat b/tests/disas/winch/x64/i8x16_ne/const_avx.wat new file mode 100644 index 000000000000..98f551cc127b --- /dev/null +++ b/tests/disas/winch/x64/i8x16_ne/const_avx.wat @@ -0,0 +1,40 @@ +;;! target = "x86_64" +;;! test = "winch" +;;! flags = [ "-Ccranelift-has-avx" ] + +(module + (func (result v128) + (i8x16.ne (v128.const i8x16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + ) +) +;; wasm[0]::function[0]: +;; pushq %rbp +;; movq %rsp, %rbp +;; movq 8(%rdi), %r11 +;; movq 0x10(%r11), %r11 +;; addq $0x10, %r11 +;; cmpq %rsp, %r11 +;; ja 0x52 +;; 1c: movq %rdi, %r14 +;; subq $0x10, %rsp +;; movq %rdi, 8(%rsp) +;; movq %rsi, (%rsp) +;; movdqu 0x2c(%rip), %xmm0 +;; movdqu 0x34(%rip), %xmm1 +;; vpcmpeqb %xmm0, %xmm1, %xmm1 +;; vpcmpeqb %xmm0, %xmm0, %xmm0 +;; vpxor %xmm0, %xmm1, %xmm1 +;; movdqa %xmm1, %xmm0 +;; addq $0x10, %rsp +;; popq %rbp +;; retq +;; 52: ud2 +;; 54: addb %al, (%rax) +;; 56: addb %al, (%rax) +;; 58: addb %al, (%rax) +;; 5a: addb %al, (%rax) +;; 5c: addb %al, (%rax) +;; 5e: addb %al, (%rax) +;; 60: addb %al, (%rcx) +;; 62: addb (%rbx), %al +;; 64: addb $5, %al diff --git a/tests/misc_testsuite/winch/_simd_splat.wast b/tests/misc_testsuite/winch/_simd_splat.wast index e03248a0507a..be674998dd0d 100644 --- a/tests/misc_testsuite/winch/_simd_splat.wast +++ b/tests/misc_testsuite/winch/_simd_splat.wast @@ -171,7 +171,7 @@ (assert_return (invoke "as-v128_store-operand-4" (i64.const 1)) (v128.const i64x2 1 1)) (assert_return (invoke "as-v128_store-operand-5" (f64.const -0x1p+0)) (v128.const f64x2 -0x1p+0 -0x1p+0)) -;; (module +(module ;; ;; Accessing lane ;; (func (export "as-i8x16_extract_lane_s-operand-first") (param i32) (result i32) ;; (i8x16.extract_lane_s 0 (i8x16.splat (local.get 0)))) @@ -257,21 +257,21 @@ ;; (i32x4.all_true (i32x4.splat (local.get 0)))) ;; (func (export "as-i32x4_all_true-operand2") (param i64) (result i32) ;; (i32x4.all_true (i64x2.splat (local.get 0)))) -;; -;; ;; Comparisons -;; (func (export "as-i8x16_eq-operands") (param i32 i32) (result v128) -;; (i8x16.eq (i8x16.splat (local.get 0)) (i8x16.splat (local.get 1)))) -;; (func (export "as-i16x8_eq-operands") (param i32 i32) (result v128) -;; (i16x8.eq (i16x8.splat (local.get 0)) (i16x8.splat (local.get 1)))) -;; (func (export "as-i32x4_eq-operands1") (param i32 i32) (result v128) -;; (i32x4.eq (i32x4.splat (local.get 0)) (i32x4.splat (local.get 1)))) -;; (func (export "as-i32x4_eq-operands2") (param i64 i64) (result v128) -;; (i32x4.eq (i64x2.splat (local.get 0)) (i64x2.splat (local.get 1)))) -;; (func (export "as-f32x4_eq-operands") (param f32 f32) (result v128) -;; (f32x4.eq (f32x4.splat (local.get 0)) (f32x4.splat (local.get 1)))) -;; (func (export "as-f64x2_eq-operands") (param f64 f64) (result v128) -;; (f64x2.eq (f64x2.splat (local.get 0)) (f64x2.splat (local.get 1)))) -;; + + ;; Comparisons + (func (export "as-i8x16_eq-operands") (param i32 i32) (result v128) + (i8x16.eq (i8x16.splat (local.get 0)) (i8x16.splat (local.get 1)))) + (func (export "as-i16x8_eq-operands") (param i32 i32) (result v128) + (i16x8.eq (i16x8.splat (local.get 0)) (i16x8.splat (local.get 1)))) + (func (export "as-i32x4_eq-operands1") (param i32 i32) (result v128) + (i32x4.eq (i32x4.splat (local.get 0)) (i32x4.splat (local.get 1)))) + (func (export "as-i32x4_eq-operands2") (param i64 i64) (result v128) + (i32x4.eq (i64x2.splat (local.get 0)) (i64x2.splat (local.get 1)))) + (func (export "as-f32x4_eq-operands") (param f32 f32) (result v128) + (f32x4.eq (f32x4.splat (local.get 0)) (f32x4.splat (local.get 1)))) + (func (export "as-f64x2_eq-operands") (param f64 f64) (result v128) + (f64x2.eq (f64x2.splat (local.get 0)) (f64x2.splat (local.get 1)))) + ;; ;; Floating-point sign bit operations ;; (func (export "as-f32x4_abs-operand") (param f32) (result v128) ;; (f32x4.abs (f32x4.splat (local.get 0)))) @@ -289,8 +289,8 @@ ;; (f32x4.convert_i32x4_s (i32x4.splat (local.get 0)))) ;; (func (export "as-i32x4_trunc_s_f32x4_sat-operand") (param f32) (result v128) ;; (i32x4.trunc_sat_f32x4_s (f32x4.splat (local.get 0)))) -;; ) -;; +) + ;; (assert_return (invoke "as-i8x16_extract_lane_s-operand-first" (i32.const 42)) (i32.const 42)) ;; (assert_return (invoke "as-i8x16_extract_lane_s-operand-last" (i32.const -42)) (i32.const -42)) ;; (assert_return (invoke "as-i16x8_extract_lane_s-operand-first" (i32.const 0xffff7fff)) (i32.const 32767)) @@ -328,14 +328,14 @@ ;; (assert_return (invoke "as-i16x8_all_true-operand" (i32.const 0xffff)) (i32.const 1)) ;; (assert_return (invoke "as-i32x4_all_true-operand1" (i32.const 0xf0f0f0f0)) (i32.const 1)) ;; (assert_return (invoke "as-i32x4_all_true-operand2" (i64.const -1)) (i32.const 1)) -;; -;; (assert_return (invoke "as-i8x16_eq-operands" (i32.const 1) (i32.const 2)) (v128.const i8x16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)) -;; (assert_return (invoke "as-i16x8_eq-operands" (i32.const -1) (i32.const 65535)) (v128.const i16x8 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff)) -;; (assert_return (invoke "as-i32x4_eq-operands1" (i32.const -1) (i32.const 0xffffffff)) (v128.const i32x4 0xffffffff 0xffffffff 0xffffffff 0xffffffff)) -;; (assert_return (invoke "as-f32x4_eq-operands" (f32.const +0.0) (f32.const -0.0)) (v128.const i32x4 0xffffffff 0xffffffff 0xffffffff 0xffffffff)) -;; (assert_return (invoke "as-i32x4_eq-operands2" (i64.const 1) (i64.const 2)) (v128.const i64x2 0xffffffff00000000 0xffffffff00000000)) -;; (assert_return (invoke "as-f64x2_eq-operands" (f64.const +0.0) (f64.const -0.0)) (v128.const i64x2 -1 -1)) -;; + +(assert_return (invoke "as-i8x16_eq-operands" (i32.const 1) (i32.const 2)) (v128.const i8x16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)) +(assert_return (invoke "as-i16x8_eq-operands" (i32.const -1) (i32.const 65535)) (v128.const i16x8 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff)) +(assert_return (invoke "as-i32x4_eq-operands1" (i32.const -1) (i32.const 0xffffffff)) (v128.const i32x4 0xffffffff 0xffffffff 0xffffffff 0xffffffff)) +(assert_return (invoke "as-f32x4_eq-operands" (f32.const +0.0) (f32.const -0.0)) (v128.const i32x4 0xffffffff 0xffffffff 0xffffffff 0xffffffff)) +(assert_return (invoke "as-i32x4_eq-operands2" (i64.const 1) (i64.const 2)) (v128.const i64x2 0xffffffff00000000 0xffffffff00000000)) +(assert_return (invoke "as-f64x2_eq-operands" (f64.const +0.0) (f64.const -0.0)) (v128.const i64x2 -1 -1)) + ;; (assert_return (invoke "as-f32x4_abs-operand" (f32.const -1.125)) (v128.const f32x4 1.125 1.125 1.125 1.125)) ;; (assert_return (invoke "as-f32x4_min-operands" (f32.const 0.25) (f32.const 1e-38)) (v128.const f32x4 1e-38 1e-38 1e-38 1e-38)) ;; (assert_return (invoke "as-f32x4_div-operands" (f32.const 1.0) (f32.const 8.0)) (v128.const f32x4 0.125 0.125 0.125 0.125)) diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs index 9c8d5bc0bfba..852d6cec634e 100644 --- a/winch/codegen/src/isa/aarch64/masm.rs +++ b/winch/codegen/src/isa/aarch64/masm.rs @@ -15,7 +15,7 @@ use crate::{ CalleeKind, DivKind, Extend, ExtendKind, ExtractLaneKind, FloatCmpKind, Imm as I, IntCmpKind, LoadKind, MacroAssembler as Masm, MulWideKind, OperandSize, RegImm, RemKind, ReplaceLaneKind, RmwOp, RoundingMode, SPOffset, ShiftKind, SplatKind, StackSlot, StoreKind, - TrapCode, TruncKind, Zero, + TrapCode, TruncKind, VectorCompareKind, VectorEqualityKind, Zero, }, stack::TypedReg, }; @@ -945,6 +945,66 @@ impl Masm for MacroAssembler { Err(anyhow!(CodeGenError::unimplemented_masm_instruction())) } + fn v128_eq( + &mut self, + _dst: WritableReg, + _lhs: Reg, + _rhs: Reg, + _kind: VectorEqualityKind, + ) -> Result<()> { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + + fn v128_ne( + &mut self, + _dst: WritableReg, + _lhs: Reg, + _rhs: Reg, + _kind: VectorEqualityKind, + ) -> Result<()> { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + + fn v128_lt( + &mut self, + _dst: WritableReg, + _lhs: Reg, + _rhs: Reg, + _kind: VectorCompareKind, + ) -> Result<()> { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + + fn v128_le( + &mut self, + _dst: WritableReg, + _lhs: Reg, + _rhs: Reg, + _kind: VectorCompareKind, + ) -> Result<()> { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + + fn v128_gt( + &mut self, + _dst: WritableReg, + _lhs: Reg, + _rhs: Reg, + _kind: VectorCompareKind, + ) -> Result<()> { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + + fn v128_ge( + &mut self, + _dst: WritableReg, + _lhs: Reg, + _rhs: Reg, + _kind: VectorCompareKind, + ) -> Result<()> { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + fn v128_not(&mut self, _dst: WritableReg) -> Result<()> { Err(anyhow!(CodeGenError::unimplemented_masm_instruction())) } diff --git a/winch/codegen/src/isa/x64/asm.rs b/winch/codegen/src/isa/x64/asm.rs index da427c5ddae0..8e51c100e246 100644 --- a/winch/codegen/src/isa/x64/asm.rs +++ b/winch/codegen/src/isa/x64/asm.rs @@ -178,6 +178,18 @@ impl From for ExtMode { } } +/// Kinds of comparisons supported by `vcmp`. +pub(super) enum VcmpKind { + /// Equal comparison. + Eq, + /// Not equal comparison. + Ne, + /// Less than comparison. + Lt, + /// Less than or equal comparison. + Le, +} + /// Low level assembler implementation for x64. pub(crate) struct Assembler { /// The machine instruction buffer. @@ -1923,6 +1935,146 @@ impl Assembler { Ok(()) } + + /// Compare vector registers `lhs` and `rhs` for equality between packed + /// integers and write the resulting vector into `dst`. + pub fn xmm_vpcmpeq_rrr(&mut self, dst: WritableReg, lhs: Reg, rhs: Reg, size: OperandSize) { + let op = match size { + OperandSize::S8 => AvxOpcode::Vpcmpeqb, + OperandSize::S16 => AvxOpcode::Vpcmpeqw, + OperandSize::S32 => AvxOpcode::Vpcmpeqd, + OperandSize::S64 => AvxOpcode::Vpcmpeqq, + _ => unimplemented!(), + }; + + self.emit(Inst::XmmRmiRVex { + op, + src1: lhs.into(), + src2: XmmMemImm::unwrap_new(rhs.into()), + dst: dst.to_reg().into(), + }) + } + + /// Performs a greater than comparison with vectors of signed integers in + /// `lhs` and `rhs` and puts the results in `dst`. + pub fn xmm_vpcmpgt_rrr(&mut self, dst: WritableReg, lhs: Reg, rhs: Reg, size: OperandSize) { + let op = match size { + OperandSize::S8 => AvxOpcode::Vpcmpgtb, + OperandSize::S16 => AvxOpcode::Vpcmpgtw, + OperandSize::S32 => AvxOpcode::Vpcmpgtd, + OperandSize::S64 => AvxOpcode::Vpcmpgtq, + _ => unimplemented!(), + }; + + self.emit(Inst::XmmRmiRVex { + op, + src1: lhs.into(), + src2: XmmMemImm::unwrap_new(rhs.into()), + dst: dst.to_reg().into(), + }) + } + + /// Performs a max operation with vectors of signed integers in `lhs` and + /// `rhs` and puts the results in `dst`. + pub fn xmm_vpmaxs_rrr(&mut self, dst: WritableReg, lhs: Reg, rhs: Reg, size: OperandSize) { + let op = match size { + OperandSize::S8 => AvxOpcode::Vpmaxsb, + OperandSize::S16 => AvxOpcode::Vpmaxsw, + OperandSize::S32 => AvxOpcode::Vpmaxsd, + _ => unimplemented!(), + }; + + self.emit(Inst::XmmRmiRVex { + op, + src1: lhs.into(), + src2: XmmMemImm::unwrap_new(rhs.into()), + dst: dst.to_reg().into(), + }) + } + + /// Performs a max operation with vectors of unsigned integers in `lhs` and + /// `rhs` and puts the results in `dst`. + pub fn xmm_vpmaxu_rrr(&mut self, dst: WritableReg, lhs: Reg, rhs: Reg, size: OperandSize) { + let op = match size { + OperandSize::S8 => AvxOpcode::Vpmaxub, + OperandSize::S16 => AvxOpcode::Vpmaxuw, + OperandSize::S32 => AvxOpcode::Vpmaxud, + _ => unimplemented!(), + }; + + self.emit(Inst::XmmRmiRVex { + op, + src1: lhs.into(), + src2: XmmMemImm::unwrap_new(rhs.into()), + dst: dst.to_reg().into(), + }) + } + + /// Performs a min operation with vectors of signed integers in `lhs` and + /// `rhs` and puts the results in `dst`. + pub fn xmm_vpmins_rrr(&mut self, dst: WritableReg, lhs: Reg, rhs: Reg, size: OperandSize) { + let op = match size { + OperandSize::S8 => AvxOpcode::Vpminsb, + OperandSize::S16 => AvxOpcode::Vpminsw, + OperandSize::S32 => AvxOpcode::Vpminsd, + _ => unimplemented!(), + }; + + self.emit(Inst::XmmRmiRVex { + op, + src1: lhs.into(), + src2: XmmMemImm::unwrap_new(rhs.into()), + dst: dst.to_reg().into(), + }) + } + + /// Performs a min operation with vectors of unsigned integers in `lhs` and + /// `rhs` and puts the results in `dst`. + pub fn xmm_vpminu_rrr(&mut self, dst: WritableReg, lhs: Reg, rhs: Reg, size: OperandSize) { + let op = match size { + OperandSize::S8 => AvxOpcode::Vpminub, + OperandSize::S16 => AvxOpcode::Vpminuw, + OperandSize::S32 => AvxOpcode::Vpminud, + _ => unimplemented!(), + }; + + self.emit(Inst::XmmRmiRVex { + op, + src1: lhs.into(), + src2: XmmMemImm::unwrap_new(rhs.into()), + dst: dst.to_reg().into(), + }) + } + + /// Performs a comparison operation between vectors of floats in `lhs` and + /// `rhs` and puts the results in `dst`. + pub fn xmm_vcmpp_rrr( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + size: OperandSize, + kind: VcmpKind, + ) { + let op = match size { + OperandSize::S32 => AvxOpcode::Vcmpps, + OperandSize::S64 => AvxOpcode::Vcmppd, + _ => unimplemented!(), + }; + + self.emit(Inst::XmmRmRImmVex { + op, + src1: lhs.into(), + src2: XmmMem::unwrap_new(rhs.into()), + dst: dst.to_reg().into(), + imm: match kind { + VcmpKind::Eq => 0, + VcmpKind::Lt => 1, + VcmpKind::Le => 2, + VcmpKind::Ne => 4, + }, + }); + } } /// Captures the region in a MachBuffer where an add-with-immediate instruction would be emitted, diff --git a/winch/codegen/src/isa/x64/masm.rs b/winch/codegen/src/isa/x64/masm.rs index 7f6822b214e0..78f1811899db 100644 --- a/winch/codegen/src/isa/x64/masm.rs +++ b/winch/codegen/src/isa/x64/masm.rs @@ -1,7 +1,7 @@ use super::{ abi::X64ABI, address::Address, - asm::{Assembler, PatchableAddToReg}, + asm::{Assembler, PatchableAddToReg, VcmpKind}, regs::{self, rbp, rsp}, }; use anyhow::{anyhow, bail, Result}; @@ -9,8 +9,8 @@ use anyhow::{anyhow, bail, Result}; use crate::masm::{ DivKind, Extend, ExtendKind, ExtractLaneKind, FloatCmpKind, Imm as I, IntCmpKind, LaneSelector, LoadKind, MacroAssembler as Masm, MulWideKind, OperandSize, RegImm, RemKind, ReplaceLaneKind, - RmwOp, RoundingMode, ShiftKind, SplatKind, StoreKind, TrapCode, TruncKind, Zero, TRUSTED_FLAGS, - UNTRUSTED_FLAGS, + RmwOp, RoundingMode, ShiftKind, SplatKind, StoreKind, TrapCode, TruncKind, VectorCompareKind, + VectorEqualityKind, Zero, TRUSTED_FLAGS, UNTRUSTED_FLAGS, }; use crate::{ abi::{self, align_to, calculate_frame_adjustment, LocalSlot}, @@ -1612,6 +1612,218 @@ impl Masm for MacroAssembler { Ok(()) } + fn v128_eq( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorEqualityKind, + ) -> Result<()> { + self.ensure_has_avx()?; + + match kind { + VectorEqualityKind::I8x16 + | VectorEqualityKind::I16x8 + | VectorEqualityKind::I32x4 + | VectorEqualityKind::I64x2 => { + self.asm.xmm_vpcmpeq_rrr(dst, lhs, rhs, kind.lane_size()) + } + VectorEqualityKind::F32x4 | VectorEqualityKind::F64x2 => { + self.asm + .xmm_vcmpp_rrr(dst, lhs, rhs, kind.lane_size(), VcmpKind::Eq) + } + } + Ok(()) + } + + fn v128_ne( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorEqualityKind, + ) -> Result<()> { + self.ensure_has_avx()?; + + match kind { + VectorEqualityKind::I8x16 + | VectorEqualityKind::I16x8 + | VectorEqualityKind::I32x4 + | VectorEqualityKind::I64x2 => { + // Check for equality and invert the results. + self.asm + .xmm_vpcmpeq_rrr(writable!(lhs), lhs, rhs, kind.lane_size()); + self.asm + .xmm_vpcmpeq_rrr(writable!(rhs), rhs, rhs, kind.lane_size()); + self.asm.xmm_rmi_rvex(AvxOpcode::Vpxor, lhs, rhs, dst); + } + VectorEqualityKind::F32x4 | VectorEqualityKind::F64x2 => { + self.asm + .xmm_vcmpp_rrr(dst, lhs, rhs, kind.lane_size(), VcmpKind::Ne) + } + } + Ok(()) + } + + fn v128_lt( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()> { + self.ensure_has_avx()?; + + match kind { + VectorCompareKind::I8x16S + | VectorCompareKind::I16x8S + | VectorCompareKind::I32x4S + | VectorCompareKind::I64x2S => { + // Perform a greater than check with reversed parameters. + self.asm.xmm_vpcmpgt_rrr(dst, rhs, lhs, kind.lane_size()) + } + VectorCompareKind::I8x16U | VectorCompareKind::I16x8U | VectorCompareKind::I32x4U => { + // Set `lhs` to min values, check for equality, then invert the + // result. + // If `lhs` is smaller, then equality check will fail and result + // will be inverted to true. Otherwise the equality check will + // pass and be inverted to false. + self.asm + .xmm_vpminu_rrr(writable!(lhs), lhs, rhs, kind.lane_size()); + self.asm + .xmm_vpcmpeq_rrr(writable!(lhs), lhs, rhs, kind.lane_size()); + self.asm + .xmm_vpcmpeq_rrr(writable!(rhs), rhs, rhs, kind.lane_size()); + self.asm.xmm_rmi_rvex(AvxOpcode::Vpxor, lhs, rhs, dst); + } + VectorCompareKind::F32x4 | VectorCompareKind::F64x2 => { + self.asm + .xmm_vcmpp_rrr(dst, lhs, rhs, kind.lane_size(), VcmpKind::Lt) + } + } + Ok(()) + } + + fn v128_le( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()> { + self.ensure_has_avx()?; + + match kind { + VectorCompareKind::I8x16S | VectorCompareKind::I16x8S | VectorCompareKind::I32x4S => { + // Set the `rhs` vector to the signed minimum values and then + // compare them with `lhs` for equality. + self.asm + .xmm_vpmins_rrr(writable!(rhs), lhs, rhs, kind.lane_size()); + self.asm.xmm_vpcmpeq_rrr(dst, lhs, rhs, kind.lane_size()); + } + VectorCompareKind::I64x2S => { + // Do a greater than check and invert the results. + self.asm + .xmm_vpcmpgt_rrr(writable!(lhs), lhs, rhs, kind.lane_size()); + self.asm + .xmm_vpcmpeq_rrr(writable!(rhs), rhs, rhs, kind.lane_size()); + self.asm.xmm_rmi_rvex(AvxOpcode::Vpxor, lhs, rhs, dst); + } + VectorCompareKind::I8x16U | VectorCompareKind::I16x8U | VectorCompareKind::I32x4U => { + // Set the `rhs` vector to the signed minimum values and then + // compare them with `lhs` for equality. + self.asm + .xmm_vpminu_rrr(writable!(rhs), lhs, rhs, kind.lane_size()); + self.asm.xmm_vpcmpeq_rrr(dst, lhs, rhs, kind.lane_size()); + } + VectorCompareKind::F32x4 | VectorCompareKind::F64x2 => { + self.asm + .xmm_vcmpp_rrr(dst, lhs, rhs, kind.lane_size(), VcmpKind::Le) + } + } + Ok(()) + } + + fn v128_gt( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()> { + self.ensure_has_avx()?; + + match kind { + VectorCompareKind::I8x16S + | VectorCompareKind::I16x8S + | VectorCompareKind::I32x4S + | VectorCompareKind::I64x2S => { + self.asm.xmm_vpcmpgt_rrr(dst, lhs, rhs, kind.lane_size()) + } + VectorCompareKind::I8x16U | VectorCompareKind::I16x8U | VectorCompareKind::I32x4U => { + // Set `lhs` to max values, check for equality, then invert the + // result. + // If `lhs` is larger, then equality check will fail and result + // will be inverted to true. Otherwise the equality check will + // pass and be inverted to false. + self.asm + .xmm_vpmaxu_rrr(writable!(lhs), lhs, rhs, kind.lane_size()); + self.asm + .xmm_vpcmpeq_rrr(writable!(lhs), lhs, rhs, kind.lane_size()); + self.asm + .xmm_vpcmpeq_rrr(writable!(rhs), rhs, rhs, kind.lane_size()); + self.asm.xmm_rmi_rvex(AvxOpcode::Vpxor, lhs, rhs, dst); + } + VectorCompareKind::F32x4 | VectorCompareKind::F64x2 => { + // Do a less than comparison with the operands swapped. + self.asm + .xmm_vcmpp_rrr(dst, rhs, lhs, kind.lane_size(), VcmpKind::Lt) + } + } + Ok(()) + } + + fn v128_ge( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()> { + self.ensure_has_avx()?; + + match kind { + VectorCompareKind::I8x16S | VectorCompareKind::I16x8S | VectorCompareKind::I32x4S => { + // Set each lane to maximum value and then compare for equality. + self.asm + .xmm_vpmaxs_rrr(writable!(rhs), lhs, rhs, kind.lane_size()); + self.asm.xmm_vpcmpeq_rrr(dst, lhs, rhs, kind.lane_size()); + } + VectorCompareKind::I64x2S => { + // Perform a greater than comparison with operands swapped, + // then invert the results. + self.asm + .xmm_vpcmpgt_rrr(writable!(rhs), rhs, lhs, kind.lane_size()); + self.asm.xmm_vpcmpeq_rrr(dst, lhs, lhs, kind.lane_size()); + self.asm + .xmm_rmi_rvex(AvxOpcode::Vpxor, dst.to_reg(), rhs, dst); + } + VectorCompareKind::I8x16U | VectorCompareKind::I16x8U | VectorCompareKind::I32x4U => { + // Set lanes to maximum values and compare them for equality. + self.asm + .xmm_vpmaxu_rrr(writable!(rhs), lhs, rhs, kind.lane_size()); + self.asm.xmm_vpcmpeq_rrr(dst, lhs, rhs, kind.lane_size()); + } + VectorCompareKind::F32x4 | VectorCompareKind::F64x2 => { + // Perform a less than or equal comparison on swapped operands. + self.asm + .xmm_vcmpp_rrr(dst, rhs, lhs, kind.lane_size(), VcmpKind::Le) + } + } + + Ok(()) + } + fn fence(&mut self) -> Result<()> { self.asm.fence(FenceKind::MFence); Ok(()) diff --git a/winch/codegen/src/masm.rs b/winch/codegen/src/masm.rs index 69e2adba5b11..3e029f3462dc 100644 --- a/winch/codegen/src/masm.rs +++ b/winch/codegen/src/masm.rs @@ -496,6 +496,68 @@ pub struct LaneSelector { pub size: OperandSize, } +/// Kinds of vector equalities and non-equalities supported by WebAssembly. +pub(crate) enum VectorEqualityKind { + /// 16 lanes of 8 bit integers. + I8x16, + /// 8 lanes of 16 bit integers. + I16x8, + /// 4 lanes of 32 bit integers. + I32x4, + /// 2 lanes of 64 bit integers. + I64x2, + /// 4 lanes of 32 bit floats. + F32x4, + /// 2 lanes of 64 bit floats. + F64x2, +} + +impl VectorEqualityKind { + /// Get the lane size to use. + pub(crate) fn lane_size(&self) -> OperandSize { + match self { + Self::I8x16 => OperandSize::S8, + Self::I16x8 => OperandSize::S16, + Self::I32x4 | Self::F32x4 => OperandSize::S32, + Self::I64x2 | Self::F64x2 => OperandSize::S64, + } + } +} + +/// Kinds of vector comparisons supported by WebAssembly. +pub(crate) enum VectorCompareKind { + /// 16 lanes of signed 8 bit integers. + I8x16S, + /// 16 lanes of unsigned 8 bit integers. + I8x16U, + /// 8 lanes of signed 16 bit integers. + I16x8S, + /// 8 lanes of unsigned 16 bit integers. + I16x8U, + /// 4 lanes of signed 32 bit integers. + I32x4S, + /// 4 lanes of unsigned 32 bit integers. + I32x4U, + /// 2 lanes of signed 64 bit integers. + I64x2S, + /// 4 lanes of 32 bit floats. + F32x4, + /// 2 lanes of 64 bit floats. + F64x2, +} + +impl VectorCompareKind { + /// Get the lane size to use. + pub(crate) fn lane_size(&self) -> OperandSize { + match self { + Self::I8x16S | Self::I8x16U => OperandSize::S8, + Self::I16x8S | Self::I16x8U => OperandSize::S16, + Self::I32x4S | Self::I32x4U | Self::F32x4 => OperandSize::S32, + Self::I64x2S | Self::F64x2 => OperandSize::S64, + } + } +} + /// Operand size, in bits. #[derive(Copy, Debug, Clone, Eq, PartialEq)] pub(crate) enum OperandSize { @@ -1488,6 +1550,66 @@ pub(crate) trait MacroAssembler { extend: Option>, ) -> Result<()>; + /// Compares vector registers `lhs` and `rhs` for equality and puts the + /// vector of results in `dst`. + fn v128_eq( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorEqualityKind, + ) -> Result<()>; + + /// Compares vector registers `lhs` and `rhs` for inequality and puts the + /// vector of results in `dst`. + fn v128_ne( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorEqualityKind, + ) -> Result<()>; + + /// Performs a less than comparison with vector registers `lhs` and `rhs` + /// and puts the vector of results in `dst`. + fn v128_lt( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()>; + + /// Performs a less than or equal comparison with vector registers `lhs` + /// and `rhs` and puts the vector of results in `dst`. + fn v128_le( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()>; + + /// Performs a greater than comparison with vector registers `lhs` and + /// `rhs` and puts the vector of results in `dst`. + fn v128_gt( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()>; + + /// Performs a greater than or equal comparison with vector registers `lhs` + /// and `rhs` and puts the vector of results in `dst`. + fn v128_ge( + &mut self, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, + ) -> Result<()>; + /// Emit a memory fence. fn fence(&mut self) -> Result<()>; diff --git a/winch/codegen/src/visitor.rs b/winch/codegen/src/visitor.rs index af2e4203d11d..08ea55cd76cb 100644 --- a/winch/codegen/src/visitor.rs +++ b/winch/codegen/src/visitor.rs @@ -13,7 +13,7 @@ use crate::masm::{ DivKind, Extend, ExtractLaneKind, FloatCmpKind, IntCmpKind, LoadKind, MacroAssembler, MemMoveDirection, MulWideKind, OperandSize, RegImm, RemKind, ReplaceLaneKind, RmwOp, RoundingMode, SPOffset, ShiftKind, Signed, SplatKind, SplatLoadKind, StoreKind, TruncKind, - VectorExtendKind, Zero, + VectorCompareKind, VectorEqualityKind, VectorExtendKind, Zero, }; use crate::reg::{writable, Reg}; @@ -351,6 +351,54 @@ macro_rules! def_unsupported { (emit I64AtomicRmw16CmpxchgU $($rest:tt)*) => {}; (emit I64AtomicRmw32CmpxchgU $($rest:tt)*) => {}; (emit I64AtomicRmwCmpxchg $($rest:tt)*) => {}; + (emit I8x16Eq $($rest:tt)*) => {}; + (emit I16x8Eq $($rest:tt)*) => {}; + (emit I32x4Eq $($rest:tt)*) => {}; + (emit I64x2Eq $($rest:tt)*) => {}; + (emit F32x4Eq $($rest:tt)*) => {}; + (emit F64x2Eq $($rest:tt)*) => {}; + (emit I8x16Ne $($rest:tt)*) => {}; + (emit I16x8Ne $($rest:tt)*) => {}; + (emit I32x4Ne $($rest:tt)*) => {}; + (emit I64x2Ne $($rest:tt)*) => {}; + (emit F32x4Ne $($rest:tt)*) => {}; + (emit F64x2Ne $($rest:tt)*) => {}; + (emit I8x16LtS $($rest:tt)*) => {}; + (emit I8x16LtU $($rest:tt)*) => {}; + (emit I16x8LtS $($rest:tt)*) => {}; + (emit I16x8LtU $($rest:tt)*) => {}; + (emit I32x4LtS $($rest:tt)*) => {}; + (emit I32x4LtU $($rest:tt)*) => {}; + (emit I64x2LtS $($rest:tt)*) => {}; + (emit F32x4Lt $($rest:tt)*) => {}; + (emit F64x2Lt $($rest:tt)*) => {}; + (emit I8x16LeS $($rest:tt)*) => {}; + (emit I8x16LeU $($rest:tt)*) => {}; + (emit I16x8LeS $($rest:tt)*) => {}; + (emit I16x8LeU $($rest:tt)*) => {}; + (emit I32x4LeS $($rest:tt)*) => {}; + (emit I32x4LeU $($rest:tt)*) => {}; + (emit I64x2LeS $($rest:tt)*) => {}; + (emit F32x4Le $($rest:tt)*) => {}; + (emit F64x2Le $($rest:tt)*) => {}; + (emit I8x16GtS $($rest:tt)*) => {}; + (emit I8x16GtU $($rest:tt)*) => {}; + (emit I16x8GtS $($rest:tt)*) => {}; + (emit I16x8GtU $($rest:tt)*) => {}; + (emit I32x4GtS $($rest:tt)*) => {}; + (emit I32x4GtU $($rest:tt)*) => {}; + (emit I64x2GtS $($rest:tt)*) => {}; + (emit F32x4Gt $($rest:tt)*) => {}; + (emit F64x2Gt $($rest:tt)*) => {}; + (emit I8x16GeS $($rest:tt)*) => {}; + (emit I8x16GeU $($rest:tt)*) => {}; + (emit I16x8GeS $($rest:tt)*) => {}; + (emit I16x8GeU $($rest:tt)*) => {}; + (emit I32x4GeS $($rest:tt)*) => {}; + (emit I32x4GeU $($rest:tt)*) => {}; + (emit I64x2GeS $($rest:tt)*) => {}; + (emit F32x4Ge $($rest:tt)*) => {}; + (emit F64x2Ge $($rest:tt)*) => {}; (emit MemoryAtomicWait32 $($rest:tt)*) => {}; (emit MemoryAtomicWait64 $($rest:tt)*) => {}; (emit MemoryAtomicNotify $($rest:tt)*) => {}; @@ -2922,6 +2970,390 @@ where }) } + fn visit_i8x16_eq(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_eq(writable!(dst), dst, src, VectorEqualityKind::I8x16)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_eq(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_eq(writable!(dst), dst, src, VectorEqualityKind::I16x8)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_eq(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_eq(writable!(dst), dst, src, VectorEqualityKind::I32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i64x2_eq(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_eq(writable!(dst), dst, src, VectorEqualityKind::I64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f32x4_eq(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_eq(writable!(dst), dst, src, VectorEqualityKind::F32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f64x2_eq(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_eq(writable!(dst), dst, src, VectorEqualityKind::F64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_ne(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_ne(writable!(dst), dst, src, VectorEqualityKind::I8x16)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_ne(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_ne(writable!(dst), dst, src, VectorEqualityKind::I16x8)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_ne(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_ne(writable!(dst), dst, src, VectorEqualityKind::I32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i64x2_ne(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_ne(writable!(dst), dst, src, VectorEqualityKind::I64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f32x4_ne(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_ne(writable!(dst), dst, src, VectorEqualityKind::F32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f64x2_ne(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_ne(writable!(dst), dst, src, VectorEqualityKind::F64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_lt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::I8x16S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_lt_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::I8x16U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_lt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::I16x8S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_lt_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::I16x8U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_lt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::I32x4S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_lt_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::I32x4U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i64x2_lt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::I64x2S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f32x4_lt(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::F32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f64x2_lt(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_lt(writable!(dst), dst, src, VectorCompareKind::F64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_le_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::I8x16S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_le_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::I8x16U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_le_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::I16x8S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_le_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::I16x8U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_le_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::I32x4S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_le_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::I32x4U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i64x2_le_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::I64x2S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f32x4_le(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::F32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f64x2_le(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_le(writable!(dst), dst, src, VectorCompareKind::F64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_gt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::I8x16S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_gt_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::I8x16U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_gt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::I16x8S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_gt_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::I16x8U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_gt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::I32x4S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_gt_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::I32x4U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i64x2_gt_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::I64x2S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f32x4_gt(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::F32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f64x2_gt(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_gt(writable!(dst), dst, src, VectorCompareKind::F64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_ge_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::I8x16S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i8x16_ge_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S8, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::I8x16U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_ge_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::I16x8S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i16x8_ge_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S16, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::I16x8U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_ge_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::I32x4S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i32x4_ge_u(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::I32x4U)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_i64x2_ge_s(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S64, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::I64x2S)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f32x4_ge(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::F32x4)?; + Ok(TypedReg::v128(dst)) + }) + } + + fn visit_f64x2_ge(&mut self) -> Self::Output { + self.context + .binop(self.masm, OperandSize::S32, |masm, dst, src, _size| { + masm.v128_ge(writable!(dst), dst, src, VectorCompareKind::F64x2)?; + Ok(TypedReg::v128(dst)) + }) + } + fn visit_i8x16_replace_lane(&mut self, lane: u8) -> Self::Output { self.context .replace_lane_op(self.masm, ReplaceLaneKind::I8x16, |masm, src, dst, kind| { From 83e514bd3fefff5d5057aad31a67f5f25bd742cd Mon Sep 17 00:00:00 2001 From: Jeff Charles Date: Wed, 29 Jan 2025 19:11:19 +0000 Subject: [PATCH 2/2] Move passing test out of unsupported list --- crates/wast-util/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crates/wast-util/src/lib.rs b/crates/wast-util/src/lib.rs index 73773ea455b4..b2eb08953ad3 100644 --- a/crates/wast-util/src/lib.rs +++ b/crates/wast-util/src/lib.rs @@ -425,7 +425,6 @@ impl WastTest { "misc_testsuite/simd/almost-extmul.wast", "misc_testsuite/simd/canonicalize-nan.wast", "misc_testsuite/simd/cvt-from-uint.wast", - "misc_testsuite/simd/issue6725-no-egraph-panic.wast", "misc_testsuite/simd/issue_3327_bnot_lowering.wast", "spec_testsuite/simd_bit_shift.wast", "spec_testsuite/simd_boolean.wast", @@ -473,6 +472,7 @@ impl WastTest { #[cfg(target_arch = "x86_64")] if !(std::is_x86_feature_detected!("avx") && std::is_x86_feature_detected!("avx2")) { let unsupported = [ + "misc_testsuite/simd/issue6725-no-egraph-panic.wast", "misc_testsuite/simd/replace-lane-preserve.wast", "misc_testsuite/simd/spillslot-size-fuzzbug.wast", "misc_testsuite/winch/_simd_lane.wast",