riscv.gprj

<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
    <FileList>
        <File path="src/Configuration.v" type="file.verilog" enable="1"/>
        <File path="src/RAM.v" type="file.verilog" enable="1"/>
        <File path="src/RAMIO.v" type="file.verilog" enable="1"/>
        <File path="src/Registers.v" type="file.verilog" enable="1"/>
        <File path="src/SoC.v" type="file.verilog" enable="1"/>
        <File path="src/Top.v" type="file.verilog" enable="1"/>
        <File path="src/UartRx.v" type="file.verilog" enable="1"/>
        <File path="src/UartTx.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
        <File path="riscv.cst" type="file.cst" enable="1"/>
    </FileList>
</Project>