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vivado.log
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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Mon Sep 28 09:59:48 2020
# Process ID: 2904
# Current directory: C:/Users/cs/Desktop/FPGA/project/project_testbench
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11996 C:\Users\cs\Desktop\FPGA\project\project_testbench\project_testbench.xpr
# Log file: C:/Users/cs/Desktop/FPGA/project/project_testbench/vivado.log
# Journal file: C:/Users/cs/Desktop/FPGA/project/project_testbench\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/softwares/FPGA_VIVADO/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 842.246 ; gain = 86.730
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'top' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj top_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.srcs/sources_1/imports/new/debounce.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module debounce
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.srcs/sources_1/imports/new/pwpart.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module pwpart
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.srcs/sources_1/imports/new/show.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module show
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.srcs/sources_1/imports/new/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: D:/softwares/FPGA_VIVADO/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto e6a84b0028074a1b96fb621e05511624 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.debounce
Compiling module xil_defaultlib.pwpart
Compiling module xil_defaultlib.show
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.glbl
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
Built simulation snapshot top_behav
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 902.344 ; gain = 0.000
INFO: [Common 17-344] 'run_program' was cancelled
INFO: [Vivado 12-5357] 'elaborate' step aborted
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 902.344 ; gain = 0.000
INFO: [Common 17-344] 'launch_simulation' was cancelled
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'top' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj top_vlog.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: D:/softwares/FPGA_VIVADO/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto e6a84b0028074a1b96fb621e05511624 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source top.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
run all
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit