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vivado_pid2904.str
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/*
Xilinx Vivado v2017.4 (64-bit) [Major: 2017, Minor: 4]
SW Build: 2086221 on Fri Dec 15 20:55:39 MST 2017
IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017
Process ID: 2904
License: Customer
Current time: Mon Sep 28 10:00:05 CST 2020
Time zone: China Standard Time (Asia/Shanghai)
OS: Windows 10
OS Version: 10.0
OS Architecture: amd64
Available processors (cores): 20
Screen size: 1536x864
Screen resolution (DPI): 96
Available screens: 1
Available disk space: 75 GB
Default font: family=Dialog,name=Dialog,style=plain,size=12
Java version: 1.8.0_112 64-bit
Java home: D:/softwares/FPGA_VIVADO/Vivado/2017.4/tps/win64/jre
JVM executable location: D:/softwares/FPGA_VIVADO/Vivado/2017.4/tps/win64/jre/bin/java.exe
User name: cs
User home directory: C:/Users/cs
User working directory: C:/Users/cs/Desktop/FPGA/project/project_testbench
User country: CN
User language: zh
User locale: zh_CN
RDI_BASEROOT: D:/softwares/FPGA_VIVADO/Vivado
HDI_APPROOT: D:/softwares/FPGA_VIVADO/Vivado/2017.4
RDI_DATADIR: D:/softwares/FPGA_VIVADO/Vivado/2017.4/data
RDI_BINDIR: D:/softwares/FPGA_VIVADO/Vivado/2017.4/bin
Vivado preferences file location: C:/Users/cs/AppData/Roaming/Xilinx/Vivado/2017.4/vivado.xml
Vivado preferences directory: C:/Users/cs/AppData/Roaming/Xilinx/Vivado/2017.4/
Vivado layouts directory: C:/Users/cs/AppData/Roaming/Xilinx/Vivado/2017.4/layouts
PlanAhead jar file location: D:/softwares/FPGA_VIVADO/Vivado/2017.4/lib/classes/planAhead.jar
Vivado log file location: C:/Users/cs/Desktop/FPGA/project/project_testbench/vivado.log
Vivado journal file location: C:/Users/cs/Desktop/FPGA/project/project_testbench/vivado.jou
Engine tmp dir: C:/Users/cs/Desktop/FPGA/project/project_testbench/.Xil/Vivado-2904-DESKTOP-MUFSVU9
GUI allocated memory: 180 MB
GUI max memory: 3,052 MB
Engine allocated memory: 571 MB
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
*/
// TclEventType: START_GUI
// Tcl Message: start_gui
// TclEventType: PROJECT_OPEN_DIALOG
// [GUI Memory]: 61 MB (+61916kb) [00:00:07]
// [Engine Memory]: 524 MB (+398285kb) [00:00:07]
// Opening Vivado Project: C:\Users\cs\Desktop\FPGA\project\project_testbench\project_testbench.xpr. Version: Vivado v2017.4
// bs (cj): Open Project : addNotify
// TclEventType: DEBUG_PROBE_SET_CHANGE
// Tcl Message: open_project C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.xpr
// TclEventType: MSGMGR_MOVEMSG
// TclEventType: FILE_SET_NEW
// [GUI Memory]: 65 MB (+527kb) [00:00:09]
// [Engine Memory]: 571 MB (+21019kb) [00:00:09]
// TclEventType: RUN_COMPLETED
// TclEventType: RUN_FAILED
// TclEventType: RUN_CURRENT
// TclEventType: PROJECT_NEW
// Tcl Message: open_project C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.xpr
// Tcl Message: Scanning sources... Finished scanning sources
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified
// TclEventType: PROJECT_NEW
// [GUI Memory]: 78 MB (+9849kb) [00:00:10]
// [Engine Memory]: 607 MB (+8532kb) [00:00:10]
// [GUI Memory]: 83 MB (+994kb) [00:00:11]
// [Engine Memory]: 657 MB (+20449kb) [00:00:11]
// [GUI Memory]: 87 MB (+427kb) [00:00:12]
// [GUI Memory]: 97 MB (+6024kb) [00:00:12]
// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/softwares/FPGA_VIVADO/Vivado/2017.4/data/ip'.
// HMemoryUtils.trashcanNow. Engine heap size: 673 MB. GUI used memory: 40 MB. Current time: 9/28/20 10:00:08 AM CST
// Project name: project_testbench; location: C:/Users/cs/Desktop/FPGA/project/project_testbench; part: xc7a100tcsg324-1
// [Engine Memory]: 733 MB (+44527kb) [00:00:13]
// Tcl Message: open_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 842.246 ; gain = 86.730
dismissDialog("Open Project"); // bs (cj)
// TclEventType: DG_ANALYSIS_MSG_RESET
// TclEventType: DG_GRAPH_GENERATED
// Tcl Message: update_compile_order -fileset sources_1
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cj)
selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ac (ai, cj)
// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
// e (cj): Run Simulation : addNotify
// TclEventType: LAUNCH_SIM
// TclEventType: FILE_SET_OPTIONS_CHANGE
// Tcl Message: launch_simulation
// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
// TclEventType: LAUNCH_SIM_LOG
// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
selectButton(RDIResource.ProgressDialog_CANCEL, "Cancel"); // a (e)
// Tcl Message: INFO: [Common 17-41] Interrupt caught. Command should exit soon.
// Tcl Message: Built simulation snapshot top_behav
// Tcl Message: run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 902.344 ; gain = 0.000
// Tcl Message: INFO: [Common 17-344] 'run_program' was cancelled INFO: [Vivado 12-5357] 'elaborate' step aborted
// Tcl Message: launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 902.344 ; gain = 0.000
// Tcl Message: INFO: [Common 17-344] 'launch_simulation' was cancelled
// CommandFailedException: ERROR: [Common 17-69] Command failed:
// 'd' command handler elapsed time: 7 seconds
dismissDialog("Run Simulation"); // e (cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, top (top.v)]", 1); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, top (top.v), debounce1 : debounce (debounce.v)]", 2, false); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, top (top.v), debounce1 : debounce (debounce.v)]", 2, false, false, false, false, false, true); // B (D, cj) - Double Click
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, top (top.v)]", 1, true); // B (D, cj) - Node
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, top (top.v)]", 1, true, false, false, false, false, true); // B (D, cj) - Double Click - Node
selectCodeEditor("top.v", 195, 93); // cd (w, cj)
selectCodeEditor("top.v", 103, 99); // cd (w, cj)
selectCodeEditor("top.v", 68, 91); // cd (w, cj)
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cj)
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, IP Integrator]", 1); // u (O, cj)
selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ac (ai, cj)
// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
// am (cj): Save Project: addNotify
selectButton(PAResourceQtoS.SaveProjectUtils_DONT_SAVE, "Don't Save"); // a (am)
// e (cj): Run Simulation : addNotify
dismissDialog("Save Project"); // am (cj)
// TclEventType: LAUNCH_SIM
// TclEventType: FILE_SET_OPTIONS_CHANGE
// Tcl Message: launch_simulation
// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
// TclEventType: LAUNCH_SIM_LOG
// Tcl Message: "xvlog --incr --relax -prj top_vlog.prj"
// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim'
// TclEventType: LAUNCH_SIM
// TclEventType: LOAD_FEATURE
// Tcl Message: Vivado Simulator 2017.4 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: D:/softwares/FPGA_VIVADO/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto e6a84b0028074a1b96fb621e05511624 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
// Tcl Message: with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}"
// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
// Tcl Message: Vivado Simulator 2017.4
// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
// TclEventType: WAVEFORM_UPDATE_TITLE
// TclEventType: WAVEFORM_OPEN_WCFG
// Tcl Message: Time resolution is 1 ps
// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
// TclEventType: WAVEFORM_OPEN_WCFG
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: WAVEFORM_UPDATE_COMMANDS
// Waveform: addNotify
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: WAVEFORM_MODEL_EVENT
// HMemoryUtils.trashcanNow. Engine heap size: 733 MB. GUI used memory: 49 MB. Current time: 9/28/20 10:00:47 AM CST
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: WAVEFORM_UPDATE_COMMANDS
// TclEventType: WAVEFORM_UPDATE_TITLE
// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: WAVEFORM_UPDATE_COMMANDS
// TclEventType: SIMULATION_UPDATE_LATEST_TIME
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: SIMULATION_UPDATE_LATEST_TIME
// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
// Tcl Message: source top.tcl
// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns
// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
// 'd' command handler elapsed time: 6 seconds
dismissDialog("Run Simulation"); // e (cj)
selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, "simulation_live_run_all"); // B (f, cj)
// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL
// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
// Tcl Message: run all
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: WAVEFORM_UPDATE_COMMANDS
// TclEventType: SIMULATION_UPDATE_LATEST_TIME
selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK, "simulation_live_break"); // B (f, cj)
// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: WAVEFORM_UPDATE_COMMANDS
// TclEventType: SIMULATION_UPDATE_LATEST_TIME
// TclEventType: WAVEFORM_MODEL_EVENT
// HMemoryUtils.trashcanNow. Engine heap size: 733 MB. GUI used memory: 48 MB. Current time: 9/28/20 10:00:53 AM CST
// TclEventType: WAVEFORM_MODEL_EVENT
// TclEventType: WAVEFORM_UPDATE_WAVEFORM
// TclEventType: SIMULATION_UPDATE_LATEST_TIME
// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
// TclEventType: SIMULATION_STOPPED
// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
// Elapsed time: 11 seconds
closeMainWindow("project_testbench - [C:/Users/cs/Desktop/FPGA/project/project_testbench/project_testbench.xpr] - Vivado 2017.4"); // cj
// am (cj): Save Project: addNotify
selectButton(PAResourceQtoS.SaveProjectUtils_DONT_SAVE, "Don't Save"); // a (am)
// c (cj): Save Simulation Sources: addNotify